1. Technical Field
Embodiments of the present invention relate to a semiconductor apparatus, and more particularly, to a main decoding circuit of the semiconductor memory apparatus.
2. Related Art
As the demand for a high-speed semiconductor memory apparatus has increased, semiconductor memory apparatus designs having a stack bank structure have been recently used so as to improve data access times. In the semiconductor memory apparatus having the stack bank structure, a memory cell region is partitioned into a plurality of memory blocks, and a plurality of stacked memory banks respectively comprise the memory block.
FIG. 1 is a block diagram schematically showing a configuration of a conventional semiconductor memory apparatus having the stack bank structure. As shown in FIG. 1, the semiconductor memory apparatus includes first and second memory banks Bank0 and Bank1, a predecoder 10, and first and second main decoding units 21 and 22. The first and second memory banks Bank0 and Bank1 constitute the stack bank structure. That is, the first memory bank Bank0 corresponds to an up bank and the second memory bank Bank1 corresponds to a down bank. At the respective first and second memory banks Bank0 and Bank1, a bit line (not shown) for accessing data stored in a memory cell is disposed, and a local input/output line (not shown) electrically connected to the respective bit line is disposed. The electrical connection between the bit line and the local input/output line is made by enabling column selection lines CSL_up<0:n> and CSL_dn<0:n>. The column selection lines CSL_up<0:n> and CSL_dn<0:n> are respectively disposed at the first and second memory banks Bank0 and Bank1, and the predecoder 10 and the first and second main decoding units 21 and 22 respectively generate a column selection signal configured to enable the column selection lines CSL_up<0:n> and CSL_dn<0:n>.
The predecoder 10 and the first and second main decoding units 21 and 22 constitute a column decoder of the semiconductor memory apparatus. The predecoder 10 receives column address signals ‘bay<2:3>’, ‘bay<4:5>’ and ‘bay<6:7,9>’ and strobe signals ‘strobe<0:1>’ to generate column decoding signals ‘lay23_up<0:3>’, ‘lay23_dn<0:3>’, ‘lay45’ and ‘lay679’. In order to generate the column selection signal configured to enable the column selection lines CSL_up<0:n> of the first memory bank Bank0 and the column selection lines CSL_dn<0:n> of the second memory bank Bank1, the predecoder 10 separately generates the column decoding signals ‘lay23_up<0:3>’ to be provided to the first main decoding unit 21 and the column decoding signals ‘lay23_dn<0:3>’ to be provided to the second main decoding unit 22, in response to the column address signals ‘bay<2:3>’ and the strobe signals ‘strobe<0:1>’.
The first main decoding unit 21 is enabled in response to the column decoding signals ‘lay23_up<0:3>’, ‘lay45’ and ‘lay679’ generated from the predecoder 10, and generates the column selection signal configured to enable the column selection lines CSL_up<0:n> of the first memory bank Bank0. On the other hand, the second main decoding unit 22 is enabled in response to the column decoding signals ‘lay23_dn<0:3>’, ‘lay45’ and ‘lay679’ generated from the predecoder 10, and generates the column selection signal configured to enable the column selection lines CSL_dn<0:n> of the second memory bank Bank1. As shown in FIG. 1, the respective first and second main decoding units 21 and 22 can comprise a plurality of main decoders Main_DEC having a substantially the same configurations. Herein, for example, four column selection lines can be assigned to each of the plurality of main decoders Main_DEC.
The column decoding signals ‘lay45’ and ‘lay679’ generated from the predecoder 10 determine which one of the plurality of main decoders Main_DEC constituting the first main decoding unit 21 is to be enabled and in which one of the plurality of main decoders Main_DEC corresponding to the second main decoding unit 22 is to be enabled. In addition, the column decoding signals ‘lay23_up<0:3>’ and ‘lay23_dn<0:3>’ determine which one of the four column selection lines assigned to the main decoder, being enabled in response to the column decoding signals ‘lay45’ and ‘lay679’, is to be enabled. Therefore, the first main decoding unit 21 can enable any one of the column selection lines CSL_up<0:n> of the first memory bank Bank0 in response to the column decoding signals ‘lay23_up<0:3>’, ‘lay45’ and ‘lay679’, and on the other hand, the second main decoding unit 22 can enable any one of the column selection lines CSL_dn<0:n> of the second memory bank Bank1 in response to the column decoding signals ‘lay23_dn<0:3>’, ‘lay45’ and ‘lay679’.
As such, according to the prior art, each of the plurality of memory banks constituting the stack bank structure necessarily requires a separate main decoding circuit. That is, since the column selection lines of the plurality of memory banks constituting the stack bank structure are different from each other and it is necessary to reduce a load on the main decoding circuit facing the column selection line, then the separate main decoding circuit is required for each of the plurality of stacked memory banks.