1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Silicon) semiconductor device and particularly to a semiconductor device having an element isolation structure with improved isolation properties.
2. Description of the Background Art
One of techniques of performing dielectric isolation between semiconductor elements is trench isolation, in which a trench formed in a surface of a semiconductor substrate is filled with a polysilicon film or silicon oxide film. This structure covers only a very small area with a very low parasitic capacitance, which is thus suitable for high-level integration and speedup of semiconductor devices as compared to other dielectric isolation techniques.
FIGS. 15 and 16 are cross-sectional views each showing a step of a method of manufacturing a conventional semiconductor device. These drawings illustrate a semiconductor substrate 101, a trench 102, silicon oxide films 1021, 1031 and a silicon nitride film 1022. Referring to these drawings, the silicon oxide film 1021 and the silicon nitride film 1022 are first deposited in this order on a surface of the semiconductor substrate 101. The silicon nitride film 1022 and the silicon oxide film 1021 are patterned so as to have an opening on a region where the trench 102 is to be formed by anisotropic etching using a photoresist mask (not shown). The surface of the semiconductor substrate 101 is etched using the silicon nitride film 1022 and the silicon oxide film 1021 as a mask to form the trench 102.
Next, an insulation film such as the silicon oxide film 1031 is formed on the entire surface using a CVD (Chemical Vapor Deposition) technique. The silicon oxide film 1031 on a surface of the silicon nitride film 1022 is then removed by a CMP (Chemical Mechanical Polishing) technique using the silicon nitride film 1022 as a stopper, so that the silicon oxide film 1031 is left only in the insides of the trench 102 and the opening of the silicon nitride film 1022. FIG. 15 shows semiconductor elements at a stage upon completion of this step.
FIG. 16 illustrates a silicon oxide film 103, a p-well 1041, an n-well 1042, a p-channel cut layer 1051, an n-channel cut layer 1052, a gate insulation film 106, a gate electrode 107, an n-type source/drain regions 1081 and a p-type source/drain regions 1082.
Referring to FIG. 16, after the step shown in FIG. 15, the silicon oxide film 103 is formed by removing the silicon nitride film 1022 and the silicon oxide film 1021 and removing the surface of the silicon oxide film 1031. After forming the silicon oxide film 103, a photoresist mask (not shown) having an opening on an nMOS region and a pMOS region is formed, thereby forming the p-well 1041 and the p-channel cut layer 1051, and the n-well 1042 and the n-channel cut layer 1052, respectively.
Next, after removing the photoresist masks, a silicon oxide film and a polysilicon layer are formed on the entire surface and patterned to form the gate insulation film 106 and the gate electrode 107.
Thereafter, another photoresist mask (not shown) having an opening on the nMOS region and the pMOS region is formed, thereby forming the n-type source/drain regions 1081 while n-type impurities are introduced into the gate electrode 107 in the nMOS region, and forming the p-type source/drain regions 1082 while p-type impurities are introduced into the gate electrode 107 in the pMOS region. The photoresist masks are then removed. FIG. 16 shows the semiconductor elements at a stage upon completion of this step.
A trench width decreases with size reduction of elements. This arises a problem that, in anisotropic etching for forming trenches, the etch rate depends on patterns, which results in variation in the depth of the trenches as formed and variation in the surface height of silicon oxide films buried in the trenches. Further, non-uniformity in the surface also disadvantageously causes trench depth variation. Furthermore, when filling the trenches with the silicon oxide films and performing planarization, variation disadvantageously occurs in the surface height of the buried silicon oxide films due to the differences of the trenches in width and the like. This variation disadvantageously creates a region under an isolating insulation film in which no channel cut layer is formed, so that punch-through between elements cannot be prevented in this region.
An object of the present invention is to provide a semiconductor device having good isolation properties with reduced punch-through between elements in a semiconductor integrated circuit reduced in size.
The semiconductor device according to the present invention includes a first semiconductor region of a first conductivity type, an isolating insulation film, a first channel cut layer of the first conductivity type, a second channel cut layer of the first conductivity type and a plurality of MOS transistors of a second conductivity type. The first semiconductor region of the first conductivity type is provided in a main surface of a semiconductor substrate. The isolating insulation film is provided in the main surface of the semiconductor substrate and separates the first semiconductor region into a plurality of active regions. The isolating insulation film has a bottom surface including first and second bottoms provided at first and second depths different from each other. The first channel cut layer of the first conductivity type is provided in the vicinity of the first bottom at the first depth in the first semiconductor region. The second channel cut layer of the first conductivity type is provided in the vicinity of the second bottom at the second depth in the semiconductor region. The plurality of MOS transistors of a second conductivity type are formed at a main surface of each of the plurality of active regions.
The channel cut layers are formed at different depths even if variation occurs in the depth of the bottom surfaces of the isolating insulation film and in the surface height of the isolating insulation film, and are therefore present in the semiconductor substrate under the isolating insulation film. This allows punch-through between elements to be reduced sufficiently. Consequently, the semiconductor device has good isolation properties.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.