1. Field of the Invention
The present invention relates to an apparatus for manufacturing a semiconductor device, and more particularly, to an apparatus for manufacturing a semiconductor device with improved uniformity of plasma density.
2. Description of the Related Art
Apparatuses for manufacturing semiconductor devices can be classified as an apparatus for forming a thin film on a semiconductor substrate, an apparatus for performing a photolithography process to form a mask pattern on the thin film to form fine patterns, an apparatus for etching the thin film using the mask pattern as an etching mask to form fine patterns, and an apparatus for implanting impurity ions into the semiconductor substrate. As the line width of patterns is reduced due to increased integration density of semiconductor devices, the quality and capabilities of etching apparatuses and deposition apparatuses used for forming fine patterns become more important. Etching apparatuses are typically classified as either dry etching apparatuses, such as plasma etching apparatuses, and wet etching apparatuses. As the integration density of semiconductor devices increases, dry etching apparatuses, which enable anisotropic etching to be performed, are typically used, and apparatuses adopting a chemical vapor deposition method using plasma, e.g., plasma-enhanced chemical vapor deposition (PE-CVD), are used as deposition apparatuses.
FIGS. 1A and 1B show two-dimensional views of apparatuses for manufacturing a semiconductor device according to the prior art. FIG. 1A shows an induced coupled plasma etching apparatus 10 having a dielectric plane structure, and FIG. 1B shows an induced coupled plasma etching apparatus 40 having a dielectric dome structure. For illustrative convenience, it is considered that chambers 12 and 42 are cylindrical, lower electrodes 26 and 56 are circular plates, an insulating plate 20 shown in FIG. 1A is circular, and an insulating plate 50 shown in FIG. 1B is dome-shaped. A plurality of induction coils 14 shown in FIG. 1A for generating a plasma source span a distance that is substantially equal to the diameter L1 of the insulating plate 20. Similarly, a plurality of induction coils 44 shown in FIG. 1B span a distance that is substantially equal to the length of curved surface of the insulating plate 50. The insulating plate 20 and the lower electrode 26 shown in FIG. 1A have almost the same diameters L1 and L2, and the projected diameter L4 of the curved surface of the insulting plate 50 shown in FIG. 1B is designed to be substantially equal to the diameter L5 of the lower electrode 56. The diameters of wafers 30 and 60 supported by static chucks 28 and 58 that are mounted on the lower electrodes 26 and 56 are designed to be smaller than the diameters of the lower electrodes 26 and 56. Confinement layers 22 and 52, which confine plasma regions 24, 54a, and 54b, are designed to contact the edges of the insulating plates 20 and 50 and extend in a direction that is perpendicular to the lower electrodes 26 and 56.
Referring to FIGS. 1A and 1B, insulating layers or conductive layers are deposited on the wafers 30 and 60 and then etched to obtain desired patterns.
A low-frequency power supplied from first power supplies 16 and 46 is applied to a plurality of induction coils 14 and 44 to generate a magnetic flux. Inductance of coils 14 and 44 creates an electric field and a magnetic field in a plasma region 24, 54a, and 54b via the insulating plates 20 and 50 included in the chambers 12 and 42. Here, a high-frequency external power is supplied to the lower electrodes 26 and 56 via second power supplies 18 and 48. Electrons move due to the magnetic field and the electric field in the plasma regions 24, 54a, and 54b and are accelerated to bombard a reactive gas to generate reactive ions of plasma. The reactive ions are diffused/absorbed into objects to be etched on the wafers 30 and 60.
Since plasma (or reactive ions) is incident to the center of the wafers 30 and 60 and diffused into the sides of the wafers 30 and 60, plasma density at the center of the wafers 30 and 60 is higher than plasma density at the edge of the wafers 30 and 60. Thus, since a large amount of plasma is incident to the center of wafers 30 and 60, patterns positioned at the center of the wafers 30 and 60 are over-etched. Since a small amount of reactive ions is diffused/absorbed at the edge of the wafers 30 and 60, patterns positioned at the edge of the wafers 30 and 60 are under-etched. Since the under-etched or over-etched patterns can greatly affect a subsequent process and/or the characteristics of the semiconductor device, it is important to maintain uniformity of etching throughout a wafer.
The above-described non-uniformity of plasma density occurs in deposition apparatuses as well as etching apparatuses. The thickness of a pattern formed at the edge of a wafer is thinner than the thickness of a pattern formed at the center of the wafer, and thus uniformity of the patterns is not ensured.
In order to meet semiconductor users' demand for high added value as well as low price, the price of semiconductor devices is typically lowered by manufacturing a large number of chips in a single process, i.e., using large diameter of wafers. Wafers having a diameter of 200 mm are typically used for producing most advanced semiconductor devices, such as memories and logics. However, it is expected that semiconductor devices will soon be mass-produced using wafers having diameters of 300 mm.
The differences in plasma density at different locations on a wafer becomes more pronounced for such larger-diameter wafers. A variety of techniques for correcting non-uniformity of plasma density have been proposed for wafers having a diameter of 200 mm, but these fail to adequately ensure etching uniformity and deposition uniformity when processing wafers having a diameter of 300 mm. Further, since plasma density is low at the edge of wafers, etch rate or deposition rate necessary for forming patterns at the edge of the wafers according to a design is not typically attained.
Accordingly, the semiconductor industry requires a technique by which a high plasma density region is formed on a wafer having a large diameter (i.e. over 200 mm and 300 mm) in order to obtain uniform etching and/or deposition throughout the wafer.