1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) cell and a method of manufacturing the same.
2. Description of the Related Art
As the elements incorporated into a semiconductor device are integrated to a higher degree, the width of wires such as gate lines and bit lines and the distance therebetween have gradually decreased. Thus, in order to increase the alignment margin in a photolithography process for forming contact holes which penetrate a given region between the wires, self-aligned contact (SAC) techniques have been developed and used. Particularly, in the case of a highly integrated DRAM cell, a method of forming bit lines and storage node pads on common drain and source regions of cell transition by using an SAC technique, and then forming storage node contact plugs and storage nodes on the storage node pads, is widely used.
FIG. 1 is a top plan view showing a portion of a cell array area of a conventional DRAM device. As illustrated, an active region is arranged in two dimensions on a semiconductor substrate. The active region has a plurality of line or bar shaped sub-regions 3a which are defined by an isolation layer. On the active region, a plurality of word lines 7 are disposed parallel to each other to cross the line shaped sub-regions 3a of the active region. Each line shaped sub-region 3a is crossed by two word lines 7, and thereby divided into three portions. One of the three portions that is between the two word lines 7 forms a common drain region, and the other two of the three portions that are on both sides of the common drain region form source regions. The common drain source regions are selectively exposed by means of a pad separation pattern 17 disposed on a side of each line shaped sub-region 3a. On each source region, a storage node pad 21s is disposed, whereas on each common drain region, a bit line pad 21d is disposed. The bit line pad 21d is extended to the upper portion of the isolation layer adjacent to the common drain region. Over the word lines 7, a plurality of bit lines 27 are disposed to cross the word lines 7. Each bit line 27 is electrically connected with the bit line pads 21d crossed therewith through bit line contacts 25.
FIGS. 2A, 3A, 4A, 5A and 6A are cross-sectional views taken along line 2A—2A of FIG. 1, showing the process steps of a conventional method of manufacturing a DRAM cell. FIGS. 2B, 3B, 4B, 5B and 6B are cross-sectional views taken along line 2B—2B of FIG. 1, also showing the process steps of the conventional method of manufacturing the DRAM cell and as corresponding to steps in FIGS. 2A, 3A, 4A, 5A and 6A.
Referring to FIG. 2A and FIG. 2B, first, an isolation layer 3 is formed on a semiconductor substrate to define an active region having a plurality of line shaped sub-regions (3a of FIG. 1). On the substrate 1 having the active region, a gate oxide layer 5 is formed. Then, a word line pattern 10 having a plurality of line shaped portions disposed parallel to each other is formed on the whole surface of the substrate to cross the active region. The word line pattern 10 is composed of a conductive layer pattern 7 forming word lines and a word line capping layer pattern 9 deposited in order.
To form impurity regions 11d, 11s, ion implantation is carried out on the active region by using the word line pattern 10 and the isolation layer 3 as an ion implantation mask. The impurity regions 11d formed between two line shaped portions of the word line pattern 10 in each line shaped sub-region 3a of the active region form common drain regions of DRAM cell transistors, and the impurity regions 11s formed on both sides of each common drain region forms source regions of the DRAM cell transistors. Then, on side walls of each line shaped portion of the word line pattern 10, word line spacers 13 are formed. And then, a pad insulating layer 15 is formed on the whole surface of the substrate on which the word line spacers are formed.
Referring to FIG. 3A and FIG. 3B, a pad separation pattern 17 is formed on the pad insulating layer 15. The pad separation pattern 17 is formed by a photolithography process, using a photo-resist pattern as a mask. Then, the pad insulating layer 15 is etched by using the pad separation pattern 17 as a mask, to form bit line pad contact holes 19d exposing the common drain regions 11d and storage node pad contact holes 19s exposing the source regions 11s. At this time, the bit line pad contact holes 19d also expose portions of the isolation layer 3 adjacent the common drain regions 11d. 
Referring to FIG. 4A and FIG. 4B, the pad separation pattern 17 is removed. Then, a doped polysilicon layer is formed on the whole surface of the substrate on which the pad separation pattern 17 is removed. Then, until the word line capping pattern 9 is exposed, the doped polysilicon layer is planarized to form bit line pads 12d and storage node pads 21s in the bit line pad contact holes 19d and the storage node pad contact holes 19s, respectively. Thereafter, a bit line insulating layer 23 is formed over the whole surface of the substrate on which the bit line pads 21d and storage node pads 21s are formed. Thereafter, the bit line insulating layer 23 is patterned to form bit line contact holes (25 of FIG. 1) exposing the bit line pads 21d. 
Over the whole surface of the substrate, a conductive layer filling the bit line contact holes 25 and a bit line capping layer are continuously formed. Then, the bit line capping layer and the conductive layer are continuously patterned to form a bit line pattern 30 crossing the word line pattern 10. The bit line pattern 30 having a plurality of line shaped portions is composed of a conductive layer pattern 27 forming bit lines and a bit line capping layer pattern 29. The bit lines of the conductive layer pattern 27 are electrically connected with the bit line pads 21d through the bit line contacts. And then, on side walls of each line shaped portion of the bit line pattern 30, bit line spacers 31 are formed. Thereafter, an interlayer insulating layer 33 is formed over the whole surface of the substrate over which the bit line spacers 31 are formed.
Referring to FIGS. 5A and 5B, the interlayer insulating layer 33 and the bit line insulating layer 23 are continuously patterned to form storage node plug contact holes exposing the storage node pads 21s. At this time, the bit line capping layer pattern 29 and the bit line spacers 31 function as an etch stop layer. Accordingly, a width of each storage node plug contact hole in a direction parallel to the line shaped portion of the word line pattern 10 is determined by distance between the line shaped portions of the bit line pattern 30. However, a width W of the storage node plug contact hole in a direction vertical to the line shaped portion of the word line pattern 10 is restricted by the bit line pad 21d, as shown in FIG. 5A. Namely, the bit line pads 21d adjacent to the storage node plug pads 21s have not been exposed by means of the storage node contact plug holes. Therefore, side walls of the storage node plug contact holes are spaced apart as much as a given distance D from the bit line pads 21d. As a result, maximizing cross-sectional area of each storage node plug contact hole is restricted.
Then, to fill the storage node plug contact holes, a conductive layer is formed over the whole surface of the substrate. And then, until the bit line capping layer pattern 29 is exposed, the conductive layer is planarized to form storage node plugs 35s in the storage node plug contact holes.
Referring to FIG. 6A and FIG. 6B, an etch stop layer 37 and a lower sacrificial insulating layer 39 are continuously formed over the whole surface of the substrate including the storage node plugs 35s. The etch stop layer 37 is formed of a layer of materials having an etch selectivity with respect to the lower sacrificial insulating layer 39 and the interlayer insulating layer 33. Then, the lower sacrificial insulating layer 39 and the etch stop layer 37 are continuously patterned to form storage node holes exposing the storage node plugs 35s. And then, a conformal conductive layer, i.e., a conformal doped polysilicon layer is formed over the whole surface of the substrate over which the storage node holes are formed. Thereafter, an upper sacrificial insulating layer is formed on the conformal conductive layer to fill the storage node holes. Until the upper surface of the lower sacrificial insulating layer 39 is exposed, the upper sacrificial insulating layer and the conformal conductive layer are continuously planarized. As a result, cylindrical shaped storage nodes 41 are formed in the storage node holes and an upper sacrificial insulating layer pattern 43 is formed.
According to the conventional method of manufacturing a DRAM cell as described above, the fabrication process is complicated. Also, the storage node pad 21s and the storage node plugs 35s are interposed between the storage nodes 41 and the source regions 11s, so that contact resistance therebetween is increased. Accordingly, a new method of decreasing the contact resistance and simplifying the fabrication process is required.