

Specialized Evolution of the General Purpose CPU - adamnemecek
http://blog.acolyer.org/2015/02/06/specialized-evolution-of-the-general-purpose-cpu/

======
vardump
X86 instructions are getting a bit more specialized over time. Like Intel's
new SSD (solid state disk, non-volatile storage) instructions.

Seriously.

[http://danluu.com/clwb-pcommit/](http://danluu.com/clwb-pcommit/)

Description for PCOMMIT from Intel's documentation:

    
    
      The PCOMMIT instruction causes certain store-to-memory
      operations to persistent memory ranges to become
      persistent (power failure protected).1 Specifically,
      PCOMMIT applies to those stores that have been accepted
      to memory.
    

...

Intel's description about CLWB:

    
    
      Writes back to memory the cache line (if dirty) that
      contains the linear address specified with the memory
      operand from any level of the cache hierarchy in the
      cache coherence domain. The line may be retained in the
      cache hierarchy in non-modified state. Retaining the
      line in the cache hierarchy is a performance optimization
      (treated as a hint by hardware) to reduce the possibility
      of cache miss on a subsequent access. Hardware may
      choose to retain the line at any of the levels in the
      cache hierarchy, and in some cases, may invalidate the
      line from the cache hierarchy. The source operand is a
      byte memory location.
    

[https://software.intel.com/sites/default/files/managed/0d/53...](https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf)

~~~
walterbell
Do you know which CPUs have or will have these instructions?

------
nn3
Direct link to the paper CIDR paper with all the data

[http://www.cidrdb.org/cidr2015/CIDR15_KeyNote.pdf](http://www.cidrdb.org/cidr2015/CIDR15_KeyNote.pdf)

The original link is really only blog spam about it and should be replaced

Yes it's a fascinating paper. Contradicts the conventional "CPUs have stopped
getting faster" story you often read

