The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology. For example, the reduction of design features makes it difficult for the memory device to meet its expected data retention requirement.
In addition, various processes that are used to complete the formation of a working memory device, such as an electrically erasable programmable read only memory (EEPROM) device, often create problems associated with the operation of the memory device. For example, it is often difficult to deposit an interlayer dielectric that fills all the space between adjacent memory cells. This often leads to gaps or voids in the interlayer dielectric. Such gaps or voids in the interlayer dielectric may lead to charge leakage problems associated with memory cells in the memory device. These voids may also make it difficult to program and/or erase the memory device in an efficient manner and, ultimately, may lead to device failure.