1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a data line sense amplifier circuit of a semiconductor memory device.
2. Description of the Related Art
As semiconductor devices become more integrated, methods are developed to increase the number of semiconductor devices included in one wafer.
The increased number of semiconductor devices included in one wafer means that the linewidth of signal transfer lines used inside of a semiconductor device becomes fine. The fine linewidth may cause an increased parasitic resistance of a signal transfer line and an increased size of a capacitor inside of a semiconductor device.
For example, a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device may have decreased performance when sense-amplifying the data of a pair of bit lines due to the fine linewidth of a signal transfer line as a bit line sense amplifier senses the data of the pair of bit lines in a cell array region when a voltage level needs to be amplified.
Designing the semiconductor device with a minimum number of signal transfer lines increases the overall operation performance of the semiconductor device, regardless of whether the lines are signal transfer lines for transferring a signal, e.g., data or a command, or voltage transfer lines for transferring a voltage, such as a power source voltage or an internal voltage.