The present invention relates to an address multiplexing apparatus for multiplexing address data for accessing a memory and, more particularly, to an address multiplexing apparatus which can be commonly used for a plurality of types of memories.
A dynamic random access memory (to hereinafter be referred to as a DRAM) is a typical known memory to which multiplexed address data is supplied. A conventional address multiplexing apparatus will now be described, with reference to access control of a DRAM.
A signal in which 2n-bit address data for designating a cell to be accessed is multiplexed such that n bits serve as row address data and the remaining n bits serve as column address data is input to a DRAM. For example, in the case of a 256K bit DRAM requiring the input of 18-bit address data in order for a cell to be selected and accessed, 9 bits of the address data are input as row address data, and the other 9 bits are input as column address data. Conventionally, the 2n-bit address data is multiplexed so that the upper n bits serve as row address data and the lower n bits serve as column address data. For this purpose, the conventional address multiplexing apparatus receives nonmultiplexed address data from, for example, a processor, and a signal, supplied from a DRAM access timing generator, for designating whether a row address (RAS) or a column address (CAS) is to be selected. The apparatus multiplexes the received address data in accordance with the signal designating the row or column address, so that the upper n bits serve as the row address data and the lower n bits serve as the column address data, and outputs the multiplexed address data.
In this case, when the DRAM is continuously accessed and if addresses to be accessed have the same upper n bits, the row address need not then be input, the column address only being input. This is known as "page mode access". Using this method, the time necessary for accessing the memory can be shortened.
However, in the case of such a multiplexing method being used, it is then difficult to realize an address multiplexing apparatus which can be commonly used for a plurality of types of memories having different capacities. For example, assume that an address multiplexing apparatus is designed, which can be commonly used for a 256K bit DRAM requiring 18-bit address data, and a 1M bit DRAM requiring 20-bit address data. Then, multiplexed output address data will require 9 bits, in the case of the 256K bit DRAM, and 10 bits, in the case of 1M bit DRAM. For this reason, output lines corresponding to 10 bits must be provided, and multiplexing as shown in FIG. 5 must be performed. A multiplexing apparatus which realizes this multiplexing method receives signals respectively designating 1M row address data (RAS-1M), 256K row address data (RAS-256K), and column address data (CAS), and outputs address data multiplexed in accordance with the received signals. Since the output address has been multiplexed, a 3-to-1 selector must be used to select one bit of the input address data in accordance with each of the nine lower bits of the multiplexed output address. More specifically, when the output address has been multiplexed in the format of FIG. 5, the 3-to-1 selector selects, for example, bit A.sub.0 when the column address of 1M mode or 256K mode, bit A.sub.9 when the row address of 256K mode, and A.sub.10 when the row address of 1M mode in accordance with the least significant bit M.sub.0 of the multiplexed output address.
With the aim of realizing the multiplexing shown in FIG. 5, a circuit has been proposed which comprises ten 3-to-1 selectors 63 arranged between input address line 61 and output address line 62, as is shown in FIG. 6. As is shown in FIG. 7, each selector 63 comprises three AND gates 71, 72, and 73, one OR gate 74, and two inverters 75 and 76, and has a very complicated arrangement.
If this multiplexing apparatus is also to be used for a 64K bit DRAM requiring 16-bit address data, as well as for the 1M bit and 256K bit DRAMs, then the multiplexing shown in FIG. 8 must be performed and a 4-to-1 selector must be used to select one bit of the input address data in accordance with each of the eight lower bits of the multiplexed output address. In this case, the arrangement of each selector is more complex than that shown in FIG. 7. Thus, when a single address multiplexing apparatus is commonly used for a plurality of types of memories, the address multiplexing apparatus becomes increasingly complicated and larger in scale.
As may be understood from the two multiplexing apparatuses described above, any apparatus, that is designed to simply multiplex 2n-bit address data so that the apparatus can be used in addressing memories of different capacities, is inevitably very complex. If two adjacent bits are multiplexed, a 2-to-1 selector may be used, but page mode access cannot be performed.