1. Field of Invention
The present invention relates to an apparatus and method for testing the WAIT signal line of a communication interface socket, which is applicable for the computer to detect whether the signal lines of its sockets can work properly.
2. Related Art
Nowadays, the communication interface socket has become a necessary one among the extended connection sockets of a computer. For example, the PCMCIA socket of a notebook computer has 68 pins and is used to accommodate a credit card size but a little thicker extended functional card, such as the network card, FAX/MODEM card, and MPEG card, etc. to enhance the ability of the notebook computer.
At present, the extended functional cards can be divided into three different specifications, Type I, Type II, and Type III, respectively. Each of the extended functional cards belong to the three specifications has a corresponding connection port to the 68 pins connector of a PCMCIA socket to transmit data between the extended functional card and the notebook computer. Therefore, in order to check whether an extended functional card can be used in a notebook computer, each of the pins of the PCMCIA socket should be tested at first.
The WAIT signal line is a special one among the lines of the PCMCIA socket, which is used to extend the Bus Access Cycle when the communication speed specified by the computer or the extended functional card is not fast enough. The function of the WAIT signal line is transparent to the software, in other words, the driver software for controlling the PCMCIA interface can work properly without knowing the actual status of this signal line, whereas it is very important in the hardware design.
If the Bus Access Cycle is faster than the specified speed, then the hardware controller will not be possible to receive or transmit data in the specified speed and consequently result a lot of error data. Therefore, the extended functional card can not be used.
Up to now, a special apparatus called SYCARD has been used for testing the computer interface sockets. It utilizes a testing software installed in the computer and a special testing interface card inserted into the communication interface socket to test the data read and write operations of the testing card.
The approach used by the SYCARD for testing the WAIT signal line can be described as below. The PCMCIA socket controller is controlled to produce 700 ns of delay and the Bus Access Cycle is also measured. If the duration time of the Bus Access Cycle exceeds 700 ns, then the status of the WAIT signal line can be regarded as correct. But in order to measure the time in the order of ns, i.e. 10{circumflex over ( )}xe2x88x929, the resolution of the measurement instruments should be quite high and the cost is also high. Therefore, the SYCARD utilizes the specialized ASICs to perform the testing and the cost is very expansive.
The primary object of the present invention is to provide an apparatus and method for testing the WAIT signal line of a communication interface socket, which can utilize some simple tools to detect whether the WAIT signal line of the PCMCIA socket can work properly without using any complex approach commonly used today.
One another object of the present invention is to provide an apparatus and method for testing the WAIT signal line of a communication interface socket to save the cost for testing the WAIT signal line of the PCMCIA socket.
One more object of the present invention is also to provide an apparatus and method for testing the WAIT signal line of a communication interface socket, by which the testing approach is greatly simplified without lowing the measurement resolution as compared with the current approaches so as to improve the test efficiency.
According to the technologies disclosed in the present invention, the apparatus for testing the WAIT signal line of a communication interface socket comprises:
a socket connection interface, which is used to connect to the communication interface socket for the testing of the signal lines;
a group of status signal lines, which comprises the IOWR and IN signal lines for identifying the status of the WAIT signal line;
an electrical switch, which is used to connect the IOWR signal line with the IN signal line so that the status of the IOWR signal line can be represented by that of the IN signal line; and
a group of switch control lines, which comprises several signal lines for enabling/disabling the electrical switch.
According to the technologies disclosed in the present invention, the method for testing the WAIT signal line of a communication interface socket comprises:
enabling the electrical switch;
executing an I/O write operation to change the status of the IOWR signal line into a LOW state;
connecting the IN signal line with the IOWR signal line so that the status of the IOWR signal line can be represented by the status of the IN signal line;
detecting the statuses of the IN signal line and the IOWR signal line;
detecting whether the IN signal line always keeps in a LOW state for 12 us of delay; and
showing the status of the WAIT signal line according to the detection results.
Wherein, the statuses of the IN signal line and the IOWR signal line are the same when the electrical switch is enabled. If the IN signal line always keeps in a LOW state for 12 us of delay, the WAIT signal line can be regarded as normal, whereas if a HIGH state happened upon the IN signal line during 12 us of delay, the WAIT signal line should be regarded as abnormal.