A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design.
Chip designers often use electronic design automation (EDA) software tools to assist in the design process. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (e.g., given specific coordinate locations in the circuit layout) and “routed” (e.g., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. In the area of custom designs, where complexity is less than digital design, the ‘logic synthesis’ approach is not taken, and the user can instead directly conduct placement and routing based on the logic connection blueprint (schematic). In addition, with respect to custom designs, users may hand-craft their own proprietary library of components, rather than using standard-cell library, just for better optimization.
An important part of the design process is for the circuit designer and/or verification engineers to test and optimize the design using a set of EDA testing and analysis tools. Various types of verification and analysis tests may be performed upon the circuit design. For example, at the logical level, simulation and formal verification may be used to test the IC design. At the physical implementation level, testing and optimization steps include extraction, verification, and compaction.
With respect to verification tasks for modern designs, it is becoming more and more important to perform electromigration (EM) analysis upon a circuit design to ensure the long-term reliability of that design. Electromigration refers to the movement of materials in a semiconductor, where usage of a circuit may cause mass transport of metal due to the momentum transfer between conducting electrons and diffusing metal atoms. If the current density is high enough, momentum transfer may occur from moving electrons to the metal ions that make up the interconnect material, where ions drift in the direction of the electron flow to cause displacement of metal atoms in a semiconductor. With modern integrated circuits having greater density and higher current requirements, combined with smaller feature sizes and wire widths in every new generation of process technologies, this means that EM effects may very well cause the occurrence of open and short circuits in the IC chip.
Conventionally, EM analysis is handled very late in the design cycle during a post-routing optimization stage. The reason for the late-stage nature of the EM analysis is because known EDA tools are typically unable to perform a reliable analysis of electromigration effects until a fairly complete routing design has been generated for the electronic product. This is because the EM tool is very reliant upon the specific location and widths of wires in the design, which are not typically realized until late in the design cycle after the physical design stage of the design process.
The problem with the conventional approach to perform EM analysis only at the late design stages is that it can be very inefficient to wait until late in the design cycle to identify EM-related problems in the design. One reason is because late stage changes to any part of the design may cause significant perturbations that ripple across and affect other parts of the design, and thus constrain the set of efficient fixes that may be available and/or cause negative unintended consequences. In addition, a significant amount investment of time and resources may have already been incurred by the late design stages, and therefore it is often highly inefficient to redesign some or all of the circuit, by the later stages. Instead, it is much more desirable and efficient to be able to identify and fix EM problems at earlier stages of the design process.
Therefore, there is a need for an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process.