As technology progresses and higher switching speeds are sought, the physical size of semiconductor devices continues to decrease. For some time metal gates were the norm for metal-oxide-semiconductor (MOS) devices. Early MOS devices often had metal gate electrodes made from aluminum or alloys of aluminum. Aluminum was preferred for its ease of deposition and etching, its favorable adhesion to SiO2 and Si surfaces, and its lack of corrosion issues. However, aluminum had some downsides, such as electro-migration and spiking into shallow junctions. The downsides were often overcome by alloying aluminum with copper or silicon. However, as multiple levels of metal interconnects at the back-end-of-the-line, aluminum and aluminum alloys were not able to withstand the high thermal budgets needed for deposition and annealing of intermetal dielectrics due to aluminum's low melting and alloying temperatures.
In the early 1970's, doped polysilicon gate electrodes began to be used. This also led to complementary-MOS (CMOS) technology that provided the ability to tailor the work function of the gate electrode for negative-channel MOS (NMOS) and positive-channel MOS (PMOS) devices. The work function of the gate electrode did not require a lot of attention in the design because the threshold voltage for the device depended more upon other factors, such as substrate doping, gate oxide charge, and gate oxide thickness. And because operating voltages were high relative to today's standards for high-speed logic devices, the gate electrode was not as critical in the control of the threshold voltage setting.
Scaling down the physical size of semiconductor devices continued due to technical and economic factors. For example, the output or drive current of a device available to switch its load devices increases linearly as its physical channel length decreases. Also, the current required by load devices to achieve switching decreases as their gate area and physical channel length decreases. Because the drive current requirement to switch the load devices depends, at least in part, on the total load capacitance and area, there is also a strong motivation to reduce the size of the complete device, not only its physical channel length. And economically, it is desirable to increase the number of devices yielded from each wafer, which further drives the device dimensions smaller. But as device dimensions decrease, new technical issues arise.
Doped polysilicon gate electrodes are now being found to be inadequate compared to metal silicided gates. Transistor physical gate length (or channel length) is reaching a point where doping levels in polysilicon can no longer be increased sufficiently to support the electrical potential profiles desired. In CMOS devices where the polysilicon gate electrode is doped with an opposite conductivity type than the channel in the substrate, there is a tendency for the gate electrode to deplete and invert when the device is biased into substrate inversion for operation. Any depletion of the polysilicon surface at the gate dielectric acts as an additional dielectric region, which increases the equivalent oxide thickness (EOT) of the gate dielectric. A push to increase boron concentrations in the polysilicon gate dielectric to minimize depletion, together with the trend of thinning the gate dielectric, has lead to increased boron diffusion through the gate dielectric and into the channel of the PMOS device. This alters the threshold voltage in an uncontrollable and undesirable way.
As a result of the recent issues with traditional doped polysilicon gate electrodes discussed above (at least in part), there has been a return to the use of metal gate electrodes in the form of metal silicided gate electrodes, especially in dual-work function gate electrodes. Fully silicided (FUSI) gate electrodes are often preferred based on process/tool compatibility and because it offers advantages over metal gate electrodes. However, there are already many well established processes in place for making semiconductor devices with doped polysilicon gate electrodes. Thus, it is often preferred to use processes that integrate the formation a FUSI gate electrode with minimal changes to current or past process flows used to make devices with a doped polysilicon gate electrode.
During the formation of a FUSI gate electrode, often the source/drain regions are also silicided, and preferably during the same process of forming the FUSI gate electrode (i.e., one silicidation process for both the gate electrode and the source/drain regions). However, this often leads to deep silicidation in the source/drain regions below the surface of the substrate. This is typically undesirable because it creates a current crowding effect at the channel region. Hence, a need exists for a way to form silicided gate electrodes while forming silicided source/drain regions, but without creating a structure susceptible to current crowding effects. It would be further desirable to be able to silicide the gate electrode while siliciding the source/drain regions in a single silicidation step.