1. Field of the Invention
The present invention relates to digital electronics, and more specifically, to a digital counter circuit.
2. Description of the Prior Art
All kinds of microprocessor systems have become an important foundation for modern information devices. A basic application specific integrated circuit (ASIC) can be viewed as a basic microprocessor system. Electronic devices with complete architecture, such as cellular phones, personal digital assistants, or personal computers, assemble lots of microprocessor systems to implement various digital processing functions. In microprocessor systems, the method of pulse triggering sequential control is often used to negotiate the systems in different structure blocks at different times for specific functions, thus the overall function for this microprocessor can be achieved. For instance, if one microprocessor system is required to implement a particular task, A circuit must process the information and then pass it on to B circuit, and then B circuit will carry on and continue to process data. Now microprocessor systems can use sequential control, first to trigger circuit A for data processing, and sequentially trigger circuit A to transfer finished data to circuit B, and then trigger circuit B to receive data, and begin data processing.
With sequential control triggering, the order of all structure blocks of microprocessor systems can be organized to implement the functionality of microprocessor systems.
When a microprocessor system is required to use sequential control, a state machine will base a trigger on a pulse to create the varying states according to predetermined order, and these states will trigger other structure blocks in the microprocessor system to perform various functions. Please refer to FIG. 1. FIG. 1 is a functional block diagram of a prior art state machine 10. State machine 10 has a plurality of state units 12 (FIG. 1 shows three units as representatives), and all state units 12 set a sequential logic circuit 14 and a combinational logic circuit 16. In general, every state unit 12 can produce a one bit state bit 18 as a corresponding output state. By combining state bits 18 generated by all state units 12 in the state machine 10, a multi-bit state 20 of digital data is then formed. In order to coordinate a unified operation for all state units 12, the state machine 10 uses a pulse CLK0 as the triggering clock to trigger the operation of all state units. Pulse CLK0 has a plurality of cyclic pulses, every pulse triggering the state machine 10 to update its state 20.
In all state units 12, the sequential logic circuit 14 is usually a flip-flop having an input port D0 to receive an input signal, an output port Q0 to transmit an output state bit, a setting port S0, and a pulse end T0. The sequential logic circuit 14 can receive the pulse CLK0 trigger from pulse end T0 in every cycle of pulse CLK0. The input signal comes in from input port D0, and the state bit 18 after update will then be sent out from output port Q0. The operational feature of the sequential logic circuit 14 is that in certain cycles of pulse CLK0, the updated state bit 18 will be outputted. This state bit is not only related to the input data received by the input port D0, but is also related to the state bit 18 (namely the state bit 18 before update) of a previous cycle from output port Q0. In other words, the sequential logic circuit 14 can “memorize” a previous output state bit.In addition, setting port S0 of the sequential logic circuit 14 is used to receive an initial state 22. The sequential logic circuit 14 then uses this initial state to set a state bit from the output port Q0 to a specific initial value. When the sequential logic circuit 14 receives triggers from following the cyclic pulse CLK0, the state bit 18 that is sent out from the output port Q0 starts to update sequentially from this specific initial value. The combinational logic circuit 16 of all state units 12 are usually formed by all sorts of logic gates, which use state 20 to produce input data corresponds to sequential logic circuit 14.
The operational principle of the state machine 10 is described below. When the state machine 10 starts to operate, it will first transfer initial states to every state unit 12, set output state 20 of every state unit 12 to a specific initial value. Then, triggered by every cycle of pulse CLK0, each state unit 12 will update its own state bit 18, and thus so will the state 20. In certain cycles of pulse CLK0, the corresponding state 20 will go through the combinational logic 16 of each state unit 12 and generate the input for every sequential logic circuit 14. And in the next cycle, all state units 12 can use the input data from combinational logic circuit (i.e. state 20 of the previous cycle), plus the “memory” function of all sequential logic circuits to update state 20. Circuit designers only have to design combinational logic circuits in state unit 12, and the state machine 10 will be triggered by pulse CLK0, and update the contents of state 20 according to the specific sequence.
Among all microprocessor systems, a counter is a special kind of microprocessor system. Please refer to FIG. 2. FIG. 2 is a functional block diagram of a prior art counting down binary counter 30. In the example of FIG. 2, the counter 30 has a plurality of state units (four shown in FIG. 2 as representatives) 31 and one accessory circuit 35. These four state units 31 are used to generate bits B1 to B4 to become the state 36 of counter 30 (i.e. the counting value of counter 30). In other words, bits B1 to B4 are the state bits of every state unit 31 of counter 30. After receiving an initial value enable signal EN1, accessory circuit 35 uses an initial state 34 to set the corresponding initial values of state bits in every state unit 31. After receiving a counter enable signal EN2, a triggering clock pulse CLK is transferred to every state unit 31. In all state units 31, a flip-flop 32 can be used as a sequential logic circuit. The state units 31 use AND gates 37 to assemble the various combinational logic circuits. The flip-flops 32 can be T type flip-flops with an input end T as an input port, and two output ends Q and Q″ for transferring two inverse bits are the output port. A setting end S is the setting port, which is used to receive an initial state setting from accessory circuit 35 to set the corresponding initial value of state bit in every initial state of sequential logic circuit. The pulse end CK is used to receive the triggering pulse CLK.
When a microprocessor system uses prior art counter 30 to perform counting, it first loads enable signal EN1 with initial values to trigger accessory circuit 35, and uses initial values 34 to set initial values of every corresponding state bit in every state unit 31. When counting begins, the counting enable signal EN2 triggers accessory circuit 35 to transfer pulse CLK to every state unit 31, and counter 30 uses the triggering of pulse CLK to start counting.
Please refer to FIG. 3 and FIG. 2. In the counter 30, based on the design of various combinational logic circuits of the state units 31, the sequential changes follow the triggering of pulse CLK for state 36 as is shown in FIG. 3. The vertical axis of FIG. 3 is time, and waveform 38 represents changes of pulse CLK through time (a horizontal axis of waveform 38 is a magnitude of the waveform). As shown in FIG. 3, pulse CLK has a plurality of cyclic pulses, and the duration of every cycle is T. Follow the triggering of pulse CLK in cycle T1, T2 and T3, the combination of state 36 from bit B1 to B4 changes sequentially from “1111”, “1110”, “1101” and so on, as shown in FIG. 3. In other words, if we consider state 36 as the counting value of counter 30, state 36 in FIG. 3 counts down from “1111” to “0000”.
Counters are used extensively in microprocessors and computer systems. For instance, please refer to the counter 30 in FIG. 2 and FIG. 3. If a first structure block in a microprocessor has to issue a special command to a second structure block at a certain interval (say 16 pulse cycles), the first structure block can set timer 30 to start counting down from a certain initial value (such as “1111” in FIG. 3). After a certain count (for instance “0000” in FIG. 3), the first structure block will know how many pulse cycles of time has passed and issue this special command. On the other hand, if the first structure block in the microprocessor is required to transfer certain data (say 16 items) to another second structure block, after the counter 30 counts down from “1111” to “0000”, the first structure block will know that the 16 data entries have been transferred.
In order to have more functional flexibility in microprocessors, every structure block can set different initial values for the counter. To further elaborate on the previous example, if the first structure block originally issues a special command every 16 pulse cycles, but because of operational needs it has to be modified to issue a special command every eight pulse cycles, the first structure block can set the initial state of counter 30 to “0111” and start counting down from “0111”. Similarly, when the counter 30 reaches “0000”, first structure block will know that eight cycles have passed, as shown in FIG. 4. FIG. 4 is a state change table of state 36 of counter 30 starting from “0111” and counting down to “0000”. The vertical axis in FIG. 4 is time. If after transferring 16 data entries, the first structure block has four more data entries to transfer, the first structure block can set the initial state of counter to “0011” and transfer according to a count down of “0011”, “0010”, “0001” and “0000”. When it reaches “0000”, the first structure block will know that four data entries have been transferred. Common state machines can perform similar functions.
When operating counters with the above method, some state units stay in the same state without any changes. For instance, referring to the example in FIG. 4, when the counter 30 is used to count eight (eight cycle pulses), state output for the state unit that generates bit B4 is never changed, that is, bit B4 is always “0”. Similarly, if counter 30 is used only to count four, only the state units corresponding to bits B2 and B1 will operate and be updated; the state units corresponding to bits B3 and B4 will not be updated. Furthermore, if more flexibility of a counter is needed, more counting units can be added to the counter so that the states of the counter (the counting value) will have more state bits. For instance, for one eight bit counter, there are 256 pulse cycles required to go through in the process of counting down from “11111111” to “00000000”. By controlling the initial states, it can count any number between 1 and 256. Similarly, when counting numbers less than 256, there will be state units in the eight bit counter not changing states. The less the number, the more state units without changing states. If an eight bit counter is used to count the number “8”, there will be five state units without changing states. When counting the number “4”, six state units will not change their states. This situation happens when using state machines flexibly, that is, when state output of some state units remains the same.
However, as shown in FIG. 1 and FIG. 2, because every state unit in the state machine or counter has to coordinate operation in synchronization, prior art state units are unified by a single pulse trigger; even though some state units do not change states, the pulse still drives these state units. In general, modern technology implements state units and sequential logic by complementary metal oxide semiconductor (CMOS). Please refer to FIG. 5. FIG. 5 is a typical logic gate 40 implementation of a CMOS circuit. A logic gate 40 uses a bias source Vd and grounding G as a DC bias. N-type CMOS gates M1, M2 are electrically connected to nodes N1, N2 respectively, and P-type CMOS gates M3, M4 are electrically connected to nodes N1, N2 respectively, and receive input from bit A and bit B respectively. Output bit C is taken from node N3 to complete an implementation of a NAND gate. When input bit A is an alternating pulse of “0”, “1”, and bit B is fixed at “0”, the output bit C will not change along with bit A but will be “1”. Under this circumstance, although the output bit C of the logic gate 40 never changes, and bit A is still being driven between “1” and “0” (between a high and a low voltage level), power consumption still exists. As CMOS gates can be viewed as capacitors, when bit A goes from “0” to “1”, power is required to charge gates of transistors M1 and M3. When bit A goes from “1” to “0”, power is also required to discharge gates of transistors M1 and M3. In other words, even though the state of a state unit is not changing according to the pulse trigger, the state unit, being formed by logic gates, still consumes driving power.
Consider the flexible or variable usage of the prior art counter or state machine as discussed above. Only a subset of state units is used, other redundant state units do not change the output state. But when pulses drive the state units of the counter or state machine, the state units that do not change state still consume driving energy of the pulses. For instance, when counter 30 in FIG. 2 is used to count the number “8” according to the method of FIG. 4, even though bit B4 never changes, the corresponding state unit still consumes driving power. So, not only is the power consumption of the microprocessor system wasted, it also becomes more difficult to promote circuit integration in microprocessor system chips.