Multi-layered structures with dual layers of polysilicon over oxide layers of differing thickness have many uses in integrated circuits. Such structures are particularly useful for construction of MOS integrated circuits including Dynamic Random Access Memory (DRAM) cells and Static Random Access Memory (SRAM) cells, for example. The methods of manufacturing multi-layered dual-polysilicon structures currently require multiple and sometimes complicated processing steps including implantation barrier deposition and removal, polysilicon deposition, patterning, and etching.
These multiple, and sometimes repetitive, processing steps increase the fabrication time and expense of manufacturing integrated circuits and semiconductor devices. Moreover, fabrication tolerances are controlled in part by the type and number of processing steps. Thus, fewer and simpler processing steps will yield tighter manufacturing tolerances and denser integrated circuits and semiconductor devices.
Thus there exists a need in the art for a method of forming a multi-layered dual-polysilicon structure that overcomes the above-described shortcomings.