The present invention relates to a pixel calculating device that has a filtering circuit for resizing images.
In recent years, remarkable technical developments have been made in relation to digital imaging equipment, and now available on the market are media processors capable, for example, of compressing, decompressing, and resizing moving images. In image resizing, finite impulse response (FIR) filters are commonly used.
FIG. 1 is a block diagram showing an exemplary prior art FIR filtering circuit. The FIR filter shown in FIG. 1 has seven taps and symmetrical coefficients. In this circuit, data inputted in time series from data input terminal 1001 is sent sequentially to delayers 1002, 1003, 1004, 1005, 1006, and 1007.
When the filter coefficients are symmetrical, tap pairings having the same coefficient value are pre-summed and then multiplied by the shared coefficient, rather than multiplying each tap individually by the coefficient. The filter coefficients are said to be in symmetry when the coefficients corresponding the input and output (i.e. xe2x80x9ctapsxe2x80x9d) from data input terminal 1001 and the delayers 1002 to 1007, respectively, are symmetrical around the center tap (i.e. the output of delayer 1004).
In the prior art FIR filter, for example, the input of data input unit 1001 and the output of delayer 1007 are summed in adder 1008 and the result is multiplied by coefficient h0 in multiplier 1008. Likewise, the output from delayers 1002 and 1006 are summed in adder 1009 and the result is multiplied by coefficient h1 in multiplier 1009. The output from multipliers 1011 to 1014 is then summed in adder 1015 and the result of the filtering is outputted in time-series from data output terminal 1016.
The value of coefficients h0 to h3 is determined by the rate of image downscaling. If the downscaling rate is xc2xd the output from adders 1008xcx9c1010 is decimated by xc2xd to obtain the downscaled image.
Symmetrical filter coefficients are preferred because of the favorable image quality resulting from the linear phase (i.e. the phase being linear with respect to frequency).
However, with the above prior art method, the configuration of the circuit dictates that the pixel data comprising the image are inputted sequentially from left to right, thus allowing only one pixel to be inputted per clock cycle. Improvements in circuitry processing speeds can be accomplished by increases in operating frequency, although increasing the operating frequency adversely leads to increases in cost and power consumption.
Furthermore, the prior art method lacks flexibility because it requires a different circuit depending on the number of taps. Substantial costs are also involved in providing a different circuit for variations in the number of taps.
Thus a first objective of the present invention is to provide a pixel calculating device capable of conducting high-speed filtering without necessarily increasing the operating frequency, and which allows for variations in the number of taps.
A second objective of the present invention is to provide a pixel calculating device capable of conducting not only filtering but also motion compensation (MC) processing, and which allows for the circuitry to be reduced in size.
A third objective of the present invention is to provide a pixel calculating device capable of conducting not only filtering but also motion estimation (ME) processing, and which allows for the circuitry to be reduced in size.
A fourth objective of the present invention is to provide a pixel calculating device capable of conducting not only filtering but also on-screen display (OSD) processing, and which allows for the circuitry to be reduced in size.
The pixel calculating device provided to achieve the first objective conducts filtering and includes N number of pixel processing units, a supply unit for supplying N pieces of pixel data and filter coefficients, and a control unit for controlling the N pixel processing units in parallel. Each of the pixel processing units performs operations using the pixel data and filter coefficient supplied from the supply unit, and then acquires pixel data from an adjacent pixel processing unit, performs further operations using the acquired pixel data, and accumulates operation results. The control unit controls each of the pixel processing units to repeat the operations of acquiring the pixel data from the adjacent pixel processing unit, performing operations using the acquired pixel data, and accumulating the operation results. Furthermore, the N pixel processing units form a first shifter that shifts N pieces of pixel data to the right, and a second shifter that shifts N pieces of pixel data to the left. Also, each of the pixel processing units performs the operations using two pieces of pixel data shifted from two adjacent pixel processing units.
According to this structure, high-speed filtering can be conducted without necessarily increasing the operating frequency, and the number of taps is variable.
The pixel calculating device provided to achieve the second objective includes a supply unit that supplies pixel data of a differential image and pixel data of a reference frame.
According to this structure, the device is capable of conducting not only filtering but also motion compensation (MC) processing, and does not required the filtering device and the MC circuit to be provided separately. This structure therefore allows for the circuitry to be reduced in size.