For cost reasons, the choice of semiconductor technology for mixed-signal Integrated Circuits (IC) is often made in favour of Low Voltage (LV), Dual Gate Oxide (DGO) process technologies derived from dense, mainstream digital semiconductor technologies
Like all electrical and electronic components, DGO MOS (Metal Oxide Semiconductor) transistors are limited in the amounts of voltage they can handle without sustaining damage. In particular DGO MOS transistors are rated for the maximum allowable voltage across their gate oxide layer, and across their channel region. This yields in technology voltage max ratings, commonly referred to as VGSmax and VDSmax, respectively, in the IC datasheet.
For example, the 0.18 um Mixed-Signal semiconductor technology as used by Taiwan Semiconductor Manufacturing Company Limited of Hinsui Taiwan, hereinafter TSMC, offers 1.8V rated MOS transistors for core logic and LV analog functions, and 3.6V rated MOS transistors for I/Os and Medium Voltage (MV) analog functions.
Some ICs, however, may embed functions which require a High Voltage (HV) which may exceed the technology max ratings. For instance, an IC having a Non Volatile Memory (NVM) requires an external HV supply for the NVM programming. Typically, the HV supply is only present on a HV pad of the circuit during NVM programming. The rest of the time, the pad is not driven externally (i.e., it is unconnected). When applied, the HV supply must be selectively routed from the HV pad to the VPP terminal of the NVM block in the circuit. This is to be achieved by an appropriate voltage switching circuitry using devices of LV or MV technology.
Some solutions may imply using MV devices out of their Safe Operating Areas (SOA). Yet, overvoltage conditions result in damage to transistors, causing permanent leakage. The leakage can be reduced to acceptable values by decreasing the voltage and time applied for NVM programming. Due to this issue, the programming voltage and duration have to be adjusted to get the best possible trade-off between transistor reliability and NVM data retention efficiency. In some applications, however, the leakage has to be very low and the delicate and risky adjustments have to be avoided.
Known solutions use modified devices that are not in the regular Process Development Kit (PDK) for the respective semiconductor technology. U.S. Pat. No. 7,236,002 discloses an electronic system for combined usage at differing voltage ranges as defined by a low-voltage range for operating standard CMOS devices and a high voltage range exceeding said standard CMOS low-voltage operating range significantly by multiples and thus necessarily utilizing input ports with an intrinsic high-voltage protection feature. The proposed structure is based on a digital CMOS input with N-channel extended drain transistor for high voltage protection. However, such a transistor extended-drain realization for CMOS transistor is not supported in all low cost technology PDK's.
U.S. Pat. No. 6,181,193 proposes a high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thickoxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver. The voltage applied to the pad is clamped with Electrostatic Discharge ESD protection diodes. Nevertheless, the maximum voltage which must be sustained by the input/output buffers interface circuit for high input voltage or low internal voltage require a large DGO maximum rating.