Magnetic memory devices consist of a stack of layers in which two ferromagnetic layers, typically referred to as a reference layer and a free layer, are separated by a thin non-magnetic dielectric layer referred to as a barrier layer. It is challenging to achieve high Tunneling Magneto Resistance (TMR) values due to imperfections in interface quality and defects in crystal growth of materials. The ferro-magnet and non-magnet barrier layer lattice mismatch and interfacial defects caused by undesirable strain results in degradation of device performance. It is desired to customize the MTJ device structure to reduce the crystal defects and improve the interface lattice epitaxy and hence improve the device performance.
Several patents teach adding stress compensating films to the MTJ structure to exert compensating stress on the structure, including U.S. Pat. No. 9,406,874 (Kula et al) and U.S. Pat. No. 9,000,545 (Kajiyama).