You are an expert in writing code in many different languages. Your goal is to perform code completion for the following code, keeping in mind the rest of the code and the file meta data.
    Metadata details:
    filename: alu.rs
    path of file: ./repos/faucon/faucon-emu/src/cpu/instructions
    
    the code of the file until where you have to start completion: //! Arithmetic Falcon instructions.

use enum_primitive::FromPrimitive;
use faucon_asm::{Instruction, InstructionKind, Operand, OperandSize};

use super::{utils, Cpu, CpuFlag};

fn sign(x: u32, size: OperandSize) -> bool {
    (x >> (size.value() as u32 - 1) & 1) != 0
}

fn carry(a: bool, b: bool, c: bool) -> bool {
    // If a and b are both set, there is always carry out.
    if a && b {
        return true;
    }

    // One of a and b is set. In this case, there is carry out if
    // the result has bit 0 set.
    if a || b && !c {
        return true;
    }

    // Neither a nor b is set, there is no possibility of carry out.
    false
}

fn overflow(a: bool, b: bool, c: bool) -> bool {
    a == b && a != c
}

/// Compares two operands and stores ALU flags based on the result.
pub fn cmp(cpu: &mut Cpu, insn: &Instruction) -> usize {
    let operands = insn.operands();

    // Extract the instruction operands (register and register or immediate).
    let source1 = utils::get_value(cpu, insn.operand_size(), operand
    
pub fn shift(cpu: &mut Cpu, insn: &Instruction) -> usize {
    let operands = insn.operands();

    // Extract the instruction operands (register, register and register or immediate).
    let destination = operands[0];
    let source1 = utils::get_value(cpu, insn.operand_size(), operands[1]);
    let mut source2 = utils::get_value(cpu, insn.operand_size(), operands[2]);

    // Truncate source2 accordingly, depending on the operand size.
    match insn.operand_size() {
        OperandSize::EightBit => source2 &= 0x7,
        OperandSize::SixteenBit => source2 &= 0xF,
        OperandSize::ThirtyTwoBit => source2 &= 0x1F,
        _ => unreachable!(),
    };

    // Carry out the operation and store the result.
    let res = match insn.kind() {
        InstructionKind::SHL | InstructionKind::SHLC => {
            let mut result = source1.wrapping_shl(source2);

            if insn.kind() == InstructionKind::SHLC && source2 != 0 {
                result |= (cpu.registers.get_flag(CpuFlag::CARRY) as u32) << (source2 - 1);
            }

            if source2 == 0 {
                cpu.registers.set_flag(CpuFlag::CARRY, false);
            } else {
                cpu.registers.set_flag(
                    CpuFlag::CARRY,
                    (source1 >> (insn.operand_size().value() as u32 - source2) & 1) != 0,
                );
            }

            result
        }
        InstructionKind::SHR | InstructionKind::SAR | InstructionKind::SHRC => {
            let mut result = source1.wrapping_shr(source2);

            if insn.kind() == InstructionKind::SHRC && source2 != 0 {
                result |= (cpu.registers.get_flag(CpuFlag::CARRY) as u32)
                    << (insn.operand_size().value() as u32 - source2);
            } else if insn.kind() == InstructionKind::SAR && sign(source1, insn.operand_size()) {
                result |= !0 << (insn.operand_size().value() as u32 - source2);
            }

            if source2 == 0 {
                cpu.registers.set_flag(CpuFlag::CARRY, false);
            } else {
                cpu.registers
                    .set_flag(CpuFlag::CARRY, ((source2 - 1) & 1) != 0);
            }

            result
        }
        _ => unreachable!(),
    };

    // Store the result value accordingly.
    utils::write_value_to_reg(cpu, insn.operand_size(), destination, res);

    // Set the remaining ALU flags.
    cpu.registers.set_flag(CpuFlag::OVERFLOW, false);
    cpu.registers.set_flag(
        CpuFlag::NEGATIVE,
        sign(cpu.registers[destination], insn.operand_size()),
    );
    cpu.registers
        .set_flag(CpuFlag::ZERO, cpu.registers[destination] == 0);

    // Signal regular PC increment to the CPU.
    cpu.increment_pc = true;

    1
}