You are an expert in writing code in many different languages. Your goal is to perform code completion for the following code, keeping in mind the rest of the code and the file meta data.
    Metadata details:
    filename: consts.go
    path of file: ./repos/sliver/vendor/github.com/tetratelabs/wazero/internal/asm/arm64
    
    the code of the file until where you have to start completion: package arm64

import (
	"fmt"

	"github.com/tetratelabs/wazero/internal/asm"
)

// Arm64-specific register states.
//
// Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm
// See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes
const (
	// CondEQ is the eq (equal) condition code
	CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota
	// CondNE is the ne (not equal) condition code
	CondNE
	// CondHS is the hs (unsigned higher or same) condition code
	CondHS
	// CondLO is the lo (unsigned lower) condition code
	CondLO
	// CondMI is the mi (negative) condition code
	CondMI
	// CondPL is the pl (positive or zero) condition code
	CondPL
	// CondVS is the vs (signed overflow) condition code
	CondVS
	// CondVC is the vc (no signed overflow) condition code
	CondVC
	// CondHI is the hi (unsigned higher) condition code
	CondHI
	// CondLS is the ls (unsigned lower or same) condition code
	CondLS
	// CondGE is the ge (signed greater than or equal) condition code
	CondGE
	// CondLT is the lt (signed less than) condition code
	CondLT
	// CondGT is the gt (signed greater than) condition code
	CondGT
	// CondLE is the le (signed less than or equal) condition code
	CondLE
	// CondAL is the al (always executed) condition code
	CondAL
	// CondNV has the same meaning as CondAL
	CondNV
)

// Arm64-specific registers.
//
// Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm
// See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state
const (
	// Integer registers.

	// RegR0 is the R0 register
	RegR0 asm.Register = asm.NilRegister + 1 + iota
	// R
    
func RegisterName(r asm.Register) string {
	switch r {
	case asm.NilRegister:
		return "nil"
	case RegR0:
		return "R0"
	case RegR1:
		return "R1"
	case RegR2:
		return "R2"
	case RegR3:
		return "R3"
	case RegR4:
		return "R4"
	case RegR5:
		return "R5"
	case RegR6:
		return "R6"
	case RegR7:
		return "R7"
	case RegR8:
		return "R8"
	case RegR9:
		return "R9"
	case RegR10:
		return "R10"
	case RegR11:
		return "R11"
	case RegR12:
		return "R12"
	case RegR13:
		return "R13"
	case RegR14:
		return "R14"
	case RegR15:
		return "R15"
	case RegR16:
		return "R16"
	case RegR17:
		return "R17"
	case RegR18:
		return "R18"
	case RegR19:
		return "R19"
	case RegR20:
		return "R20"
	case RegR21:
		return "R21"
	case RegR22:
		return "R22"
	case RegR23:
		return "R23"
	case RegR24:
		return "R24"
	case RegR25:
		return "R25"
	case RegR26:
		return "R26"
	case RegR27:
		return "R27"
	case RegR28:
		return "R28"
	case RegR29:
		return "R29"
	case RegR30:
		return "R30"
	case RegRZR:
		return "RZR"
	case RegSP:
		return "SP"
	case RegV0:
		return "V0"
	case RegV1:
		return "V1"
	case RegV2:
		return "V2"
	case RegV3:
		return "V3"
	case RegV4:
		return "V4"
	case RegV5:
		return "V5"
	case RegV6:
		return "V6"
	case RegV7:
		return "V7"
	case RegV8:
		return "V8"
	case RegV9:
		return "V9"
	case RegV10:
		return "V10"
	case RegV11:
		return "V11"
	case RegV12:
		return "V12"
	case RegV13:
		return "V13"
	case RegV14:
		return "V14"
	case RegV15:
		return "V15"
	case RegV16:
		return "V16"
	case RegV17:
		return "V17"
	case RegV18:
		return "V18"
	case RegV19:
		return "V19"
	case RegV20:
		return "V20"
	case RegV21:
		return "V21"
	case RegV22:
		return "V22"
	case RegV23:
		return "V23"
	case RegV24:
		return "V24"
	case RegV25:
		return "V25"
	case RegV26:
		return "V26"
	case RegV27:
		return "V27"
	case RegV28:
		return "V28"
	case RegV29:
		return "V29"
	case RegV30:
		return "V30"
	case RegV31:
		return "V31"
	case RegFPSR:
		return "FPSR"
	case RegCondEQ:
		return "COND_EQ"
	case RegCondNE:
		return "COND_NE"
	case RegCondHS:
		return "COND_HS"
	case RegCondLO:
		return "COND_LO"
	case RegCondMI:
		return "COND_MI"
	case RegCondPL:
		return "COND_PL"
	case RegCondVS:
		return "COND_VS"
	case RegCondVC:
		return "COND_VC"
	case RegCondHI:
		return "COND_HI"
	case RegCondLS:
		return "COND_LS"
	case RegCondGE:
		return "COND_GE"
	case RegCondLT:
		return "COND_LT"
	case RegCondGT:
		return "COND_GT"
	case RegCondLE:
		return "COND_LE"
	case RegCondAL:
		return "COND_AL"
	case RegCondNV:
		return "COND_NV"
	}
	return "UNKNOWN"
}