You are an expert in writing code in many different languages. Your goal is to perform code completion for the following code, keeping in mind the rest of the code and the file meta data.
    Metadata details:
    filename: ddr.rs
    path of file: ./repos/oreboot/src/soc/src/sifive/fu540
    
    the code of the file until where you have to start completion: use super::reg;
use super::ux00;
use consts::DeviceCtl;
use core::convert::TryInto;
use core::ops
    
fn sdram_init() {
    ux00::ux00ddr_writeregmap();
    ux00::ux00ddr_disableaxireadinterleave();

    ux00::ux00ddr_disableoptimalrmodw();

    ux00::ux00ddr_enablewriteleveling();
    ux00::ux00ddr_enablereadleveling();
    ux00::ux00ddr_enablereadlevelinggate();
    if ux00::ux00ddr_getdramclass() == ux00::DRAM_CLASS_DDR4 {
        ux00::ux00ddr_enablevreftraining();
    }

    //mask off interrupts for leveling completion
    ux00::ux00ddr_mask_leveling_completed_interrupt();

    ux00::ux00ddr_mask_mc_init_complete_interrupt();
    ux00::ux00ddr_mask_outofrange_interrupts();
    let ddr_size: u64 = mem_size();
    ux00::ux00ddr_setuprangeprotection(ddr_size);
    ux00::ux00ddr_mask_port_command_error_interrupt();

    let ddr_end: u64 = reg::DRAM as u64 + ddr_size;
    let ddr_bus_blocker: u64 = reg::DDR_BUS_BLOCKER as u64;
    ux00::ux00ddr_start(ddr_bus_blocker, ddr_end);

    ux00::ux00ddr_phy_fixup();
}