You are an expert in writing code in many different languages. Your goal is to perform code completion for the following code, keeping in mind the rest of the code and the file meta data.
    Metadata details:
    filename: r820t.rs
    path of file: ./repos/rtl-sdr-rs/src/tuners
    
    the code of the file until where you have to start completion: use super::{Tuner, TunerGain, TunerInfo};
use crate::device::Device;
use crate::error::Result;
use crate::error::RtlsdrError::RtlsdrErr;
use log::info;

const R820T_I2C_ADDR: u16 = 0x34;
// const R828D_I2C_ADDR: u8 = 0x74; for now only support the T
const VER_NUM: u8 = 49;
pub const R82XX_IF_FREQ: u32 = 3570000;
const NUM_REGS: usize = 32;
const RW_REG_START: usize = 5; // registers 0-4 are read-only
const NUM_CACHE_REGS: usize = NUM_REGS - RW_REG_START; // only cache RW regs
const MAX_I2C_MSG_LEN: usize = 8;

// Init registers (32 total, first 5 are read-only)
const REG_INIT: [u8; NUM_CACHE_REGS] = [
    0x83, 0x32, 0x75, /* 05 to 07 */
    0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
    0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
    0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
    0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
    0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
    0x54, 0xae, 0x4a, 0xc0, /* 1c to 1f */
];

/* measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
* input power, for raw results see:
* http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
*/
const _VGA_BASE_GAIN: i32 = -47;
const GAINS: [i32; 29] = [
    0, 9, 14, 27, 37
    
    fn set_mux(&mut self, handle: &Device, freq: u32) -> Result<()> {
        // Get the proper frequency range
        let freq_mhz = freq / 1_000_000;
        // Find the range that freq is within
        let range = {
            let mut r: &FreqRange = &FREQ_RANGES[0];
            for range in FREQ_RANGES.iter() {
                if freq_mhz < range.freq {
                    // past freq, break
                    break;
                }
                // range still below freq, save it and continue iterating
                r = range;
            }
            r
        };

        // Open Drain
        self.write_reg_mask(handle, 0x17, range.open_d, 0x08)?;

        // RF_MUX, Polymux
        self.write_reg_mask(handle, 0x1a, range.rf_mux_ploy, 0xc3)?;

        // TF Band
        self.write_regs(handle, 0x1b, &[range.tf_c])?;

        // XTAL CAP & Drive
        let val = match self.xtal_cap_sel {
            XtalCapValue::XtalLowCap30p | XtalCapValue::XtalLowCap20p => range.xtal_cap20p | 0x08,
            XtalCapValue::XtalLowCap10p => range.xtal_cap10p | 0x08,
            XtalCapValue::XtalHighCap0p => range.xtal_cap0p | 0x00,
            XtalCapValue::XtalLowCap0p => range.xtal_cap0p | 0x08,
        };
        self.write_reg_mask(handle, 0x10, val, 0x0b)?;
        self.write_reg_mask(handle, 0x08, 0x00, 0x3f)?;
        self.write_reg_mask(handle, 0x09, 0x00, 0x3f)?;
        Ok(())
    }