(self, offset, size, expr=None)
return RichR(r_value, variable=var, typevar=typevar)
:param offset:
        :param size:
        :return:
def _read_from_register(self, offset, size, expr=None):
        """

        :param offset:
        :param size:
        :return:
        """

        codeloc = self._codeloc()

        try:
            values: Optional[MultiValues] = self.state.register_region.load(offset, size=size)
        except SimMemoryMissingError:
            values = None

        if self.arch.is_artificial_register(offset, size):
            # don't even load values for artificial registers
            r_value = self.state.top(size * self.arch.byte_width)
            return RichR(r_value, variable=None, typevar=None)
        if offset in (self.arch.sp_offset, self.arch.ip_offset):
            # load values. don't worry about variables
            if values is None:
                r_value = self.state.top(size * self.arch.byte_width)
            else:
                r_value = next(iter(next(iter(values.values.values()))))
            return RichR(r_value, variable=None, typevar=None)

        if not values:
            # the value does not exist. create a new variable
            variable = SimRegisterVariable(offset, size,
                                           ident=self.variable_manager[self.func_addr].next_variable_ident(
                                               'register'),
                                           region=self.func_addr,
                                           )
            value = self.state.top(size * self.state.arch.byte_width)
            value = self.state.annotate_with_variables(value, [(0, variable)])
            self.state.register_region.store(offset, value)
            self.variable_manager[self.func_addr].add_variable('register', offset, variable)

            value_list = [{ value }]
        else:
            value_list = list(values.values.values())

        variable_set = set()
        for value_set in value_list:
            for value in value_set:
                for _, var in self.state.extract_variables(value):
                    self.variable_manager[self.func_addr].read_from(var, None, codeloc, atom=expr)
                    variable_set.add(var)

        if self.arch.is_artificial_register(offset, size) or offset == self.arch.sp_offset:
            typevar = None
            var = None
        else:
            # we accept the precision loss here by only returning the first variable
            # FIXME: Multiple variables
            typevar = None
            var = None
            if variable_set:
                var = next(iter(variable_set))

                # add delayed type constraints
                if var in self.state.delayed_type_constraints:
                    for constraint in self.state.delayed_type_constraints[var]:
                        self.state.add_type_constraint(constraint)
                    self.state.delayed_type_constraints.pop(var)

                if var not in self.state.typevars:
                    typevar = typevars.TypeVariable()
                    self.state.typevars.add_type_variable(var, codeloc, typevar)
                else:
                    # FIXME: This is an extremely stupid hack. Fix it later.
                    # typevar = next(reversed(list(self.state.typevars[var].values())))
                    typevar = self.state.typevars[var]

        if len(value_list) == 1:
            r_value = next(iter(value_list[0]))
        else:
            r_value = self.state.top(size * self.arch.byte_width)  # fall back to top
        return RichR(r_value, variable=var, typevar=typevar)
def _read_from_register ( self , offset , size , expr = None ) : codeloc = self . _codeloc ( ) try : values : Optional [ MultiValues ] = self . state . register_region . load ( offset , size = size ) except SimMemoryMissingError : values = None if self . arch . is_artificial_register ( offset , size ) : # don't even load values for artificial registers r_value = self . state . top ( size * self . arch . byte_width ) return RichR ( r_value , variable = None , typevar = None ) if offset in ( self . arch . sp_offset , self . arch . ip_offset ) : # load values. don't worry about variables if values is None : r_value = self . state . top ( size * self . arch . byte_width ) else : r_value = next ( iter ( next ( iter ( values . values . values ( ) ) ) ) ) return RichR ( r_value , variable = None , typevar = None ) if not values : # the value does not exist. create a new variable variable = SimRegisterVariable ( offset , size , ident = self . variable_manager [ self . func_addr ] . next_variable_ident ( 'register' ) , region = self . func_addr , ) value = self . state . top ( size * self . state . arch . byte_width ) value = self . state . annotate_with_variables ( value , [ ( 0 , variable ) ] ) self . state . register_region . store ( offset , value ) self . variable_manager [ self . func_addr ] . add_variable ( 'register' , offset , variable ) value_list = [ { value } ] else : value_list = list ( values . values . values ( ) ) variable_set = set ( ) for value_set in value_list : for value in value_set : for _ , var in self . state . extract_variables ( value ) : self . variable_manager [ self . func_addr ] . read_from ( var , None , codeloc , atom = expr ) variable_set . add ( var ) if self . arch . is_artificial_register ( offset , size ) or offset == self . arch . sp_offset : typevar = None var = None else : # we accept the precision loss here by only returning the first variable # FIXME: Multiple variables typevar = None var = None if variable_set : var = next ( iter ( variable_set ) ) # add delayed type constraints if var in self . state . delayed_type_constraints : for constraint in self . state . delayed_type_constraints [ var ] : self . state . add_type_constraint ( constraint ) self . state . delayed_type_constraints . pop ( var ) if var not in self . state . typevars : typevar = typevars . TypeVariable ( ) self . state . typevars . add_type_variable ( var , codeloc , typevar ) else : # FIXME: This is an extremely stupid hack. Fix it later. # typevar = next(reversed(list(self.state.typevars[var].values()))) typevar = self . state . typevars [ var ] if len ( value_list ) == 1 : r_value = next ( iter ( value_list [ 0 ] ) ) else : r_value = self . state . top ( size * self . arch . byte_width ) # fall back to top return RichR ( r_value , variable = var , typevar = typevar )