(self, variable: SimRegisterVariable)
Filters all registers that are surly not members of function arguments.
        This can be seen as a workaround, since VariableRecoveryFast sometimes gives input variables of cc_ndep (which
        is a VEX-specific register) :-(

        :param variable: The variable to test.
        :return:         True if it is an acceptable function argument, False otherwise.
        :rtype:          bool
Filters all registers that are surly not members of function arguments.
        This can be seen as a workaround, since VariableRecoveryFast sometimes gives input variables of cc_ndep (which
        is a VEX-specific register) :-(
Filters all registers that are surly not members of function arguments . This can be seen as a workaround since VariableRecoveryFast sometimes gives input variables of cc_ndep ( which is a VEX - specific register ) : - (
def _is_sane_register_variable(self, variable: SimRegisterVariable) -> bool:
        """
        Filters all registers that are surly not members of function arguments.
        This can be seen as a workaround, since VariableRecoveryFast sometimes gives input variables of cc_ndep (which
        is a VEX-specific register) :-(

        :param variable: The variable to test.
        :return:         True if it is an acceptable function argument, False otherwise.
        :rtype:          bool
        """

        arch = self.project.arch

        if arch.name == 'AARCH64':
            return 16 <= variable.reg < 80  # x0-x7

        elif arch.name == 'AMD64':
            return (24 <= variable.reg < 40 or  # rcx, rdx
                    64 <= variable.reg < 104  # rsi, rdi, r8, r9, r10
                    )
                    # 224 <= variable.reg < 480)  # xmm0-xmm7

        elif is_arm_arch(arch):
            return 8 <= variable.reg < 24  # r0-r3

        elif arch.name == 'MIPS32':
            return 24 <= variable.reg < 40  # a0-a3

        elif arch.name == 'MIPS64':
            return 48 <= variable.reg < 80 or 112 <= variable.reg < 208 # a0-a3 or t4-t7

        elif arch.name == 'PPC32':
            return 28 <= variable.reg < 60  # r3-r10

        elif arch.name == 'X86':
            return (8 <= variable.reg < 24 or  # eax, ebx, ecx, edx
                    160 <= variable.reg < 288)  # xmm0-xmm7

        else:
            l.critical('Unsupported architecture %s.', arch.name)
            return True
def _is_sane_register_variable ( self , variable : SimRegisterVariable ) -> bool : arch = self . project . arch if arch . name == 'AARCH64' : return 16 <= variable . reg < 80 # x0-x7 elif arch . name == 'AMD64' : return ( 24 <= variable . reg < 40 or # rcx, rdx 64 <= variable . reg < 104 # rsi, rdi, r8, r9, r10 ) # 224 <= variable.reg < 480)  # xmm0-xmm7 elif is_arm_arch ( arch ) : return 8 <= variable . reg < 24 # r0-r3 elif arch . name == 'MIPS32' : return 24 <= variable . reg < 40 # a0-a3 elif arch . name == 'MIPS64' : return 48 <= variable . reg < 80 or 112 <= variable . reg < 208 # a0-a3 or t4-t7 elif arch . name == 'PPC32' : return 28 <= variable . reg < 60 # r3-r10 elif arch . name == 'X86' : return ( 8 <= variable . reg < 24 or # eax, ebx, ecx, edx 160 <= variable . reg < 288 ) # xmm0-xmm7 else : l . critical ( 'Unsupported architecture %s.' , arch . name ) return True