(self, regs_dump)
Initialize register values within the state

        :param regs_dump: The output of ``info registers`` in gdb.
Initialize register values within the state
Initialize register values within the state
def set_regs(self, regs_dump):
        """
        Initialize register values within the state

        :param regs_dump: The output of ``info registers`` in gdb.
        """

        if self.real_stack_top == 0 and self.adjust_stack is True:
            raise SimStateError("You need to set the stack first, or set"
                    "adjust_stack to False. Beware that in this case, sp and bp won't be updated")

        data = self._read_data(regs_dump)
        rdata = re.split(b"\n", data)
        for r in rdata:
            if r == b"":
                continue
            reg = re.split(b" +", r)[0].decode()
            val = int(re.split(b" +", r)[1],16)
            try:
                self.state.registers.store(reg, claripy.BVV(val, self.state.arch.bits))
            # Some registers such as cs, ds, eflags etc. aren't supported in angr
            except KeyError as e:
                l.warning("Reg %s was not set", e)

        self._adjust_regs()
def set_regs ( self , regs_dump ) : if self . real_stack_top == 0 and self . adjust_stack is True : raise SimStateError ( "You need to set the stack first, or set" "adjust_stack to False. Beware that in this case, sp and bp won't be updated" ) data = self . _read_data ( regs_dump ) rdata = re . split ( b"\n" , data ) for r in rdata : if r == b"" : continue reg = re . split ( b" +" , r ) [ 0 ] . decode ( ) val = int ( re . split ( b" +" , r ) [ 1 ] , 16 ) try : self . state . registers . store ( reg , claripy . BVV ( val , self . state . arch . bits ) ) # Some registers such as cs, ds, eflags etc. aren't supported in angr except KeyError as e : l . warning ( "Reg %s was not set" , e ) self . _adjust_regs ( )