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| description
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| header
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| module_code
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mux2to1v | 1 | Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b. | module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
| module top_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [99:0] a,
input [99:0] b,
input sel,
output [99:0] out
);
assign out = sel ? b : a;
endmodule
module stimulus_gen (
input clk,
output logic [99:0] a,b,
output logic sel,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 'hdeadbeef;
b <= 'h5eaf00d;
sel <= 0;
@(negedge clk);
wavedrom_start("Beef or seafood?");
repeat(6) @(posedge clk) sel <= ~sel;
@(negedge clk);
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= {$random, $random, $random, $random, $random, $random, $random};
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [99:0] a;
logic [99:0] b;
logic sel;
logic [99:0] out_ref;
logic [99:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.sel );
reference_module good1 (
.a,
.b,
.sel,
.out(out_ref) );
top_module top_module1 (
.a,
.b,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
m2014_q6b | 2 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Assume that you want to Implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement just the next-state logic for y[2] in Verilog. The output Y2 is y[2]. | module top_module(
input [3:1] y,
input w,
output reg Y2);
| module top_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;
4'h8: Y2 = 1'b0;
4'h9: Y2 = 1'b1;
4'ha: Y2 = 1'b1;
4'hb: Y2 = 1'b1;
default: Y2 = 1'bx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [3:1] y,
input w,
output reg Y2);
always_comb begin
case ({y, w})
4'h0: Y2 = 1'b0;
4'h1: Y2 = 1'b0;
4'h2: Y2 = 1'b1;
4'h3: Y2 = 1'b1;
4'h4: Y2 = 1'b0;
4'h5: Y2 = 1'b1;
4'h6: Y2 = 1'b0;
4'h7: Y2 = 1'b0;
4'h8: Y2 = 1'b0;
4'h9: Y2 = 1'b1;
4'ha: Y2 = 1'b1;
4'hb: Y2 = 1'b1;
default: Y2 = 1'bx;
endcase
end
endmodule
module stimulus_gen (
input clk,
output reg [3:1] y,
output reg w
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{y,w} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y2;
int errortime_Y2;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:1] y;
logic w;
logic Y2_ref;
logic Y2_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
reference_module good1 (
.y,
.w,
.Y2(Y2_ref) );
top_module top_module1 (
.y,
.w,
.Y2(Y2_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y2", stats1.errors_Y2, stats1.errortime_Y2);
else $display("Hint: Output '%s' has no mismatches.", "Y2");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y2_ref } === ( { Y2_ref } ^ { Y2_dut } ^ { Y2_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))
begin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;
stats1.errors_Y2 = stats1.errors_Y2+1'b1; end
end
endmodule
|
ringer | 3 | Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer. | module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
| module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
module stimulus_gen (
input clk,
output reg ring, vibrate_mode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{vibrate_mode,ring} <= 1'b0;
wavedrom_start();
repeat(10) @(posedge clk)
{vibrate_mode,ring} <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_ringer;
int errortime_ringer;
int errors_motor;
int errortime_motor;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic ring;
logic vibrate_mode;
logic ringer_ref;
logic ringer_dut;
logic motor_ref;
logic motor_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,ring,vibrate_mode,ringer_ref,ringer_dut,motor_ref,motor_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.ring,
.vibrate_mode );
reference_module good1 (
.ring,
.vibrate_mode,
.ringer(ringer_ref),
.motor(motor_ref) );
top_module top_module1 (
.ring,
.vibrate_mode,
.ringer(ringer_dut),
.motor(motor_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_ringer) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "ringer", stats1.errors_ringer, stats1.errortime_ringer);
else $display("Hint: Output '%s' has no mismatches.", "ringer");
if (stats1.errors_motor) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "motor", stats1.errors_motor, stats1.errortime_motor);
else $display("Hint: Output '%s' has no mismatches.", "motor");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { ringer_ref, motor_ref } === ( { ringer_ref, motor_ref } ^ { ringer_dut, motor_dut } ^ { ringer_ref, motor_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (ringer_ref !== ( ringer_ref ^ ringer_dut ^ ringer_ref ))
begin if (stats1.errors_ringer == 0) stats1.errortime_ringer = $time;
stats1.errors_ringer = stats1.errors_ringer+1'b1; end
if (motor_ref !== ( motor_ref ^ motor_dut ^ motor_ref ))
begin if (stats1.errors_motor == 0) stats1.errortime_motor = $time;
stats1.errors_motor = stats1.errors_motor+1'b1; end
end
endmodule
|
alwaysblock1 | 4 | Build an AND gate using both an assign statement and a combinational always block. | module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
| module top_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out_assign,
output reg out_alwaysblock
);
assign out_assign = a & b;
always @(*) out_alwaysblock = a & b;
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("AND gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_alwaysblock;
int errortime_out_alwaysblock;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_assign_ref;
logic out_assign_dut;
logic out_alwaysblock_ref;
logic out_alwaysblock_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_assign_ref,out_assign_dut,out_alwaysblock_ref,out_alwaysblock_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
reference_module good1 (
.a,
.b,
.out_assign(out_assign_ref),
.out_alwaysblock(out_alwaysblock_ref) );
top_module top_module1 (
.a,
.b,
.out_assign(out_assign_dut),
.out_alwaysblock(out_alwaysblock_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_alwaysblock) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_alwaysblock", stats1.errors_out_alwaysblock, stats1.errortime_out_alwaysblock);
else $display("Hint: Output '%s' has no mismatches.", "out_alwaysblock");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_alwaysblock_ref } === ( { out_assign_ref, out_alwaysblock_ref } ^ { out_assign_dut, out_alwaysblock_dut } ^ { out_assign_ref, out_alwaysblock_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_alwaysblock_ref !== ( out_alwaysblock_ref ^ out_alwaysblock_dut ^ out_alwaysblock_ref ))
begin if (stats1.errors_out_alwaysblock == 0) stats1.errortime_out_alwaysblock = $time;
stats1.errors_out_alwaysblock = stats1.errors_out_alwaysblock+1'b1; end
end
endmodule
|
zero | 5 | Build a circuit that always outputs a LOW. | module top_module(
output zero);
| module top_module(
output zero);
assign zero = 1'b0;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
output zero);
assign zero = 1'b0;
endmodule
module stimulus_gen (
input clk,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Output should 0");
repeat(20) @(posedge clk, negedge clk);
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_zero;
int errortime_zero;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic zero_ref;
logic zero_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,zero_ref,zero_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* );
reference_module good1 (
.zero(zero_ref) );
top_module top_module1 (
.zero(zero_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_zero) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "zero", stats1.errors_zero, stats1.errortime_zero);
else $display("Hint: Output '%s' has no mismatches.", "zero");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { zero_ref } === ( { zero_ref } ^ { zero_dut } ^ { zero_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (zero_ref !== ( zero_ref ^ zero_dut ^ zero_ref ))
begin if (stats1.errors_zero == 0) stats1.errortime_zero = $time;
stats1.errors_zero = stats1.errors_zero+1'b1; end
end
endmodule
|
circuit7 | 6 | This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time clk a q
// 0ns 0 x x
// 5ns 1 0 x
// 10ns 0 0 x
// 15ns 1 0 1
// 20ns 0 0 1
// 25ns 1 0 1
// 30ns 0 0 1
// 35ns 1 1 1
// 40ns 0 1 1
// 45ns 1 1 0
// 50ns 0 1 0
// 55ns 1 1 0
// 60ns 0 1 0
// 65ns 1 1 0
// 70ns 0 1 0
// 75ns 1 1 0
// 80ns 0 1 0
// 85ns 1 1 0
// 90ns 0 1 0 | module top_module (
input clk,
input a,
output reg q
);
| module top_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input a,
output reg q
);
always @(posedge clk)
q <= ~a;
endmodule
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(posedge clk) {a} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a} <= 0;
repeat(10) @(posedge clk) a <= $urandom;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
a <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a );
reference_module good1 (
.clk,
.a,
.q(q_ref) );
top_module top_module1 (
.clk,
.a,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
ece241_2014_q5a | 7 | You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires a positive edge triggered asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted. | module top_module (
input clk,
input areset,
input x,
output z
);
| module top_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <= x ? B : C;
C: state <= x ? B : C;
endcase
end
end
assign z = (state == C);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input areset,
input x,
output z
);
parameter A=0,B=1,C=2;
reg [1:0] state;
always @(posedge clk, posedge areset) begin
if (areset)
state <= A;
else begin
case (state)
A: state <= x ? C : A;
B: state <= x ? B : C;
C: state <= x ? B : C;
endcase
end
end
assign z = (state == C);
endmodule
module stimulus_gen (
input clk,
output logic x,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
x <= 0;
reset <= 1;
@(posedge clk) reset <= 0; x <= 1;
@(posedge clk) x <= 0;
reset_test(1);
@(negedge clk) wavedrom_start();
@(posedge clk) {reset,x} <= 2'h2;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h1;
@(posedge clk) {reset,x} <= 2'h0;
@(posedge clk) {reset,x} <= 2'h0;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk)
{reset,x} <= {($random&31) == 0, ($random&1)==0 };
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.x );
reference_module good1 (
.clk,
.areset,
.x,
.z(z_ref) );
top_module top_module1 (
.clk,
.areset,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
endmodule
|
fsm3 | 8 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A.
// state | next state in=0, next state in=1 | output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1 | module top_module (
input clk,
input in,
input areset,
output out
);
| module top_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
module stimulus_gen (
input clk,
output logic in,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk) reset <= 0; in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk);
@(negedge clk) reset <= 1;
@(posedge clk) reset <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic areset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.areset );
reference_module good1 (
.clk,
.in,
.areset,
.out(out_ref) );
top_module top_module1 (
.clk,
.in,
.areset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
vector2 | 9 | Build a circuit that reverses the byte order of a 32-bit vector. | module top_module (
input [31:0] in,
output [31:0] out
);
| module top_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [31:0] in,
output [31:0] out
);
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
endmodule
module stimulus_gen (
input clk,
output logic [31:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk, negedge clk)
in <= $random;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
in <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [31:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
reference_module good1 (
.in,
.out(out_ref) );
top_module top_module1 (
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
m2014_q4c | 10 | Implement a simple D flip flop with active high synchronous reset (reset output to 0). | module top_module (
input clk,
input d,
input r,
output logic q
);
| module top_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input d,
input r,
output logic q
);
always@(posedge clk) begin
if (r)
q <= 0;
else
q <= d;
end
endmodule
module stimulus_gen (
input clk,
output logic d, r
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{d,r} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic r;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,r,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.r );
reference_module good1 (
.clk,
.d,
.r,
.q(q_ref) );
top_module top_module1 (
.clk,
.d,
.r,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
mt2015_q4a | 11 | Implement the boolean function z = (x^y) & x. | module top_module(
input x,
input y,
output z);
| module top_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(101) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic y;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
reference_module good1 (
.x,
.y,
.z(z_ref) );
top_module top_module1 (
.x,
.y,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
endmodule
|
shift18 | 12 | Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by "amount." Assume the right shit is an arithmetic right shift.
// Signals are defined as below:
// (1) load: Loads shift register with data[63:0] instead of shifting. Active high.
// (2) ena: Chooses whether to shift. Active high.
// (3) amount: Chooses which direction and how much to shift.
// (a) 2'b00: shift left by 1 bit.
// (b) 2'b01: shift left by 8 bits.
// (c) 2'b10: shift right by 1 bit.
// (d) 2'b11: shift right by 8 bits.
// (4) q: The contents of the shifter. | module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
| module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <= {{8{q[63]}}, q[63:8]};
default: q <= 64'hx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <= {{8{q[63]}}, q[63:8]};
default: q <= 64'hx;
endcase
end
endmodule
module stimulus_gen (
input clk,
output reg load,
output reg ena,
output reg[1:0] amount,
output reg[63:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
load <= 1;
ena <= 0;
data <= 'x;
amount <= 0;
@(posedge clk) data <= 64'h000100;
wavedrom_start("Shifting");
@(posedge clk) load <= 0; ena <= 1;
amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 1;
@(posedge clk) amount <= 1;
@(posedge clk) amount <= 0;
@(posedge clk) amount <= 0;
@(posedge clk) amount <= 3;
@(posedge clk) amount <= 3;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(negedge clk);
wavedrom_stop();
@(posedge clk); load <= 1; data <= 64'hx;
@(posedge clk); load <= 1; data <= 64'h80000000_00000000;
wavedrom_start("Arithmetic right shift");
@(posedge clk) load <= 0; ena <= 1;
amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(negedge clk);
wavedrom_stop();
@(posedge clk);
@(posedge clk);
repeat(4000) @(posedge clk, negedge clk) begin
load <= !($random & 31);
ena <= |($random & 15);
amount <= $random;
data <= {$random,$random};
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic ena;
logic [1:0] amount;
logic [63:0] data;
logic [63:0] q_ref;
logic [63:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,amount,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.ena,
.amount,
.data );
reference_module good1 (
.clk,
.load,
.ena,
.amount,
.data,
.q(q_ref) );
top_module top_module1 (
.clk,
.load,
.ena,
.amount,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
ece241_2013_q8 | 13 | Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have a negative edge triggered asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences. | module top_module (
input clk,
input aresetn,
input x,
output reg z
);
| module top_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S10: next = x ? S1 : S;
default: next = 'x;
endcase
end
always_comb begin
case (state)
S: z = 0;
S1: z = 0;
S10: z = x;
default: z = 'x;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S10: next = x ? S1 : S;
default: next = 'x;
endcase
end
always_comb begin
case (state)
S: z = 0;
S1: z = 0;
S10: z = x;
default: z = 'x;
endcase
end
endmodule
module stimulus_gen (
input clk,
output logic aresetn,
output logic x,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign aresetn = ~reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
x <= 0;
repeat(3) @(posedge clk);
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
end
initial begin
reset <= 1;
@(posedge clk) reset <= 0;
reset_test(1);
@(negedge clk) wavedrom_start();
@(posedge clk) x <= 0;
@(posedge clk) x <= 0;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
x <= $random;
reset <= ($random&31) == 0;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic aresetn;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,aresetn,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.aresetn,
.x );
reference_module good1 (
.clk,
.aresetn,
.x,
.z(z_ref) );
top_module top_module1 (
.clk,
.aresetn,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
endmodule
|
m2014_q6 | 14 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Implement this state machine in Verilog. | module top_module (
input clk,
input reset,
input w,
output z
);
| module top_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A: next = w ? A : B;
B: next = w ? D : C;
C: next = w ? D : E;
D: next = w ? A : F;
E: next = w ? D : E;
F: next = w ? D : C;
default: next = 'x;
endcase
end
assign z = (state == E || state == F);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A: next = w ? A : B;
B: next = w ? D : C;
C: next = w ? D : E;
D: next = w ? A : F;
E: next = w ? D : E;
F: next = w ? D : C;
default: next = 'x;
endcase
end
assign z = (state == E || state == F);
endmodule
module stimulus_gen (
input clk,
output logic reset,
output logic w
);
initial begin
repeat(200) @(posedge clk, negedge clk) begin
w <= $random;
reset <= ($random & 15) == 0;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic w;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.w );
reference_module good1 (
.clk,
.reset,
.w,
.z(z_ref) );
top_module top_module1 (
.clk,
.reset,
.w,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
endmodule
|
fsm_ps2data | 15 | We want a finite state machine that will search for message boundaries when given an input byte stream. The algorithm we'll use is to discard bytes until we see one with in[3]=1. We then assume that this is byte 1 of a message, and signal the receipt of a message once all 3 bytes have been received (done). The FSM should signal done in the cycle immediately after the third byte of each message was successfully received.
// Implement the datapath module that will output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.). The reset signal is active high synchronous. out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).
// Waveform example:
// time clk reset in[7:0] done out_bytes
// 0ns 0 1 0 x x
// 5ns 1 1 0 0 x
// 10ns 0 1 0 0 x
// 15ns 1 0 2c 0 x
// 20ns 0 0 2c 0 x
// 25ns 1 0 81 0 x
// 30ns 0 0 81 0 x
// 35ns 1 0 9 0 x
// 40ns 0 0 9 0 x
// 45ns 1 0 6b 1 2c8109
// 50ns 0 0 6b 1 2c8109
// 55ns 1 0 d 0 x
// 60ns 0 0 d 0 x
// 65ns 1 0 8d 0 x
// 70ns 0 0 8d 0 x
// 75ns 1 0 6d 1 6b0d8d
// 80ns 0 0 6d 1 6b0d8d
// 85ns 1 0 12 0 x
// 90ns 0 0 12 0 x
// 95ns 1 0 1 0 x
// 100ns 0 0 1 0 x
// 105ns 1 0 d 1 6d1201
// 110ns 0 0 d 1 6d1201
// 115ns 1 0 76 0 x
// 120ns 0 0 76 0 x
// 125ns 1 0 3d 0 x
// 130ns 0 0 3d 0 x
// 135ns 1 0 ed 1 d763d
// 140ns 0 0 ed 1 d763d
// 145ns 1 0 8c 0 x
// 150ns 0 0 8c 0 x
// 155ns 1 0 f9 0 x
// 160ns 0 0 f9 0 x
// 165ns 1 0 ce 1 ed8cf9
// 170ns 0 0 ce 1 ed8cf9
// 175ns 1 0 c5 0 x
// 180ns 0 0 c5 0 x
// 185ns 1 0 aa 0 x
// 190ns 0 0 aa 0 x | module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
| module top_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = in3 ? BYTE2 : BYTE1;
endcase
end
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
assign done = (state==DONE);
reg [23:0] out_bytes_r;
always @(posedge clk)
out_bytes_r <= {out_bytes_r[15:0], in};
// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.
assign out_bytes = done ? out_bytes_r : 'x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = in3 ? BYTE2 : BYTE1;
endcase
end
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
assign done = (state==DONE);
reg [23:0] out_bytes_r;
always @(posedge clk)
out_bytes_r <= {out_bytes_r[15:0], in};
// Implementations may vary: Allow user to do anything while the output doesn't have to be valid.
assign out_bytes = done ? out_bytes_r : 'x;
endmodule
module stimulus_gen (
input clk,
output logic [7:0] in,
output logic reset
);
initial begin
repeat(200) @(negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
reset <= 1'b0;
in <= '0;
repeat(10) @(posedge clk);
repeat(200) begin
in <= $random;
in[3] <= 1'b1;
@(posedge clk);
in <= $random;
@(posedge clk);
in <= $random;
@(posedge clk);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_bytes;
int errortime_out_bytes;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic reset;
logic [23:0] out_bytes_ref;
logic [23:0] out_bytes_dut;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_bytes_ref,out_bytes_dut,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
reference_module good1 (
.clk,
.in,
.reset,
.out_bytes(out_bytes_ref),
.done(done_ref) );
top_module top_module1 (
.clk,
.in,
.reset,
.out_bytes(out_bytes_dut),
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_bytes) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_bytes", stats1.errors_out_bytes, stats1.errortime_out_bytes);
else $display("Hint: Output '%s' has no mismatches.", "out_bytes");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_bytes_ref, done_ref } === ( { out_bytes_ref, done_ref } ^ { out_bytes_dut, done_dut } ^ { out_bytes_ref, done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_bytes_ref !== ( out_bytes_ref ^ out_bytes_dut ^ out_bytes_ref ))
begin if (stats1.errors_out_bytes == 0) stats1.errortime_out_bytes = $time;
stats1.errors_out_bytes = stats1.errors_out_bytes+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
endmodule
|
2012_q2b | 16 |
// Consider the state machine shown below:
// A (0) --1--> B
// A (0) --0--> A
// B (0) --1--> C
// B (0) --0--> D
// C (0) --1--> E
// C (0) --0--> D
// D (0) --1--> F
// D (0) --0--> A
// E (1) --1--> E
// E (1) --0--> D
// F (1) --1--> C
// F (1) --0--> D
// Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)
// Write a Verilog for the signal Y1, which is the input of state flip-flop y[1], for the signal Y3, which is the input of state flip-flop y[3]. Derive the Verilog by inspection assuming a one-hot encoding.
| module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
| module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0]&w;
assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w;
endmodule
module stimulus_gen (
input clk,
output logic[5:0] y,
output logic w,
input tb_match
);
int errored1 = 0;
int onehot_error = 0;
int temp;
initial begin
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
y <= 1<< ($unsigned($random) % 6);
w <= $random;
if (!tb_match) onehot_error++;
end
// Random.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
do
temp = $random;
while ( !{temp[5:4],temp[2:1]} == !{temp[3],temp[0]} );
// Make y[3,0] and y[5,4,2,1] mutually exclusive, so we can accept Y3=(~y[3] & ~y[0]) &~w as a valid answer too.
y <= temp;
w <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.");
if (!onehot_error && errored1)
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y1;
int errortime_Y1;
int errors_Y3;
int errortime_Y3;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [5:0] y;
logic w;
logic Y1_ref;
logic Y1_dut;
logic Y3_ref;
logic Y3_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut,Y3_ref,Y3_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
reference_module good1 (
.y,
.w,
.Y1(Y1_ref),
.Y3(Y3_ref) );
top_module top_module1 (
.y,
.w,
.Y1(Y1_dut),
.Y3(Y3_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y1", stats1.errors_Y1, stats1.errortime_Y1);
else $display("Hint: Output '%s' has no mismatches.", "Y1");
if (stats1.errors_Y3) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y3", stats1.errors_Y3, stats1.errortime_Y3);
else $display("Hint: Output '%s' has no mismatches.", "Y3");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y1_ref, Y3_ref } === ( { Y1_ref, Y3_ref } ^ { Y1_dut, Y3_dut } ^ { Y1_ref, Y3_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))
begin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;
stats1.errors_Y1 = stats1.errors_Y1+1'b1; end
if (Y3_ref !== ( Y3_ref ^ Y3_dut ^ Y3_ref ))
begin if (stats1.errors_Y3 == 0) stats1.errortime_Y3 = $time;
stats1.errors_Y3 = stats1.errors_Y3+1'b1; end
end
endmodule
|
vector0 | 17 | Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc. | module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
| module top_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input [2:0] vec,
output [2:0] outv,
output o2,
output o1,
output o0
);
assign outv = vec;
assign {o2, o1, o0} = vec;
endmodule
module stimulus_gen (
input clk,
output reg [2:0] vec,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
vec <= 3'b0;
@(negedge clk);
wavedrom_start();
repeat(10) @(posedge clk)
vec <= count++;
wavedrom_stop();
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_outv;
int errortime_outv;
int errors_o2;
int errortime_o2;
int errors_o1;
int errortime_o1;
int errors_o0;
int errortime_o0;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] vec;
logic [2:0] outv_ref;
logic [2:0] outv_dut;
logic o2_ref;
logic o2_dut;
logic o1_ref;
logic o1_dut;
logic o0_ref;
logic o0_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,vec,outv_ref,outv_dut,o2_ref,o2_dut,o1_ref,o1_dut,o0_ref,o0_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.vec );
reference_module good1 (
.vec,
.outv(outv_ref),
.o2(o2_ref),
.o1(o1_ref),
.o0(o0_ref) );
top_module top_module1 (
.vec,
.outv(outv_dut),
.o2(o2_dut),
.o1(o1_dut),
.o0(o0_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_outv) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "outv", stats1.errors_outv, stats1.errortime_outv);
else $display("Hint: Output '%s' has no mismatches.", "outv");
if (stats1.errors_o2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o2", stats1.errors_o2, stats1.errortime_o2);
else $display("Hint: Output '%s' has no mismatches.", "o2");
if (stats1.errors_o1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o1", stats1.errors_o1, stats1.errortime_o1);
else $display("Hint: Output '%s' has no mismatches.", "o1");
if (stats1.errors_o0) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "o0", stats1.errors_o0, stats1.errortime_o0);
else $display("Hint: Output '%s' has no mismatches.", "o0");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { outv_ref, o2_ref, o1_ref, o0_ref } === ( { outv_ref, o2_ref, o1_ref, o0_ref } ^ { outv_dut, o2_dut, o1_dut, o0_dut } ^ { outv_ref, o2_ref, o1_ref, o0_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (outv_ref !== ( outv_ref ^ outv_dut ^ outv_ref ))
begin if (stats1.errors_outv == 0) stats1.errortime_outv = $time;
stats1.errors_outv = stats1.errors_outv+1'b1; end
if (o2_ref !== ( o2_ref ^ o2_dut ^ o2_ref ))
begin if (stats1.errors_o2 == 0) stats1.errortime_o2 = $time;
stats1.errors_o2 = stats1.errors_o2+1'b1; end
if (o1_ref !== ( o1_ref ^ o1_dut ^ o1_ref ))
begin if (stats1.errors_o1 == 0) stats1.errortime_o1 = $time;
stats1.errors_o1 = stats1.errors_o1+1'b1; end
if (o0_ref !== ( o0_ref ^ o0_dut ^ o0_ref ))
begin if (stats1.errors_o0 == 0) stats1.errortime_o0 = $time;
stats1.errors_o0 = stats1.errors_o0+1'b1; end
end
endmodule
|
kmap4 | 18 | Implement the circuit described by the Karnaugh map below.
// ab
// cd 00 01 11 10
// 00 | 0 | 1 | 0 | 1 |
// 01 | 1 | 0 | 1 | 0 |
// 11 | 0 | 1 | 0 | 1 |
// 10 | 1 | 0 | 1 | 0 | | module top_module (
input a,
input b,
input c,
input d,
output reg out
);
| module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out = 1;
4'h5: out = 0;
4'h7: out = 1;
4'h6: out = 0;
4'hc: out = 0;
4'hd: out = 1;
4'hf: out = 0;
4'he: out = 1;
4'h8: out = 1;
4'h9: out = 0;
4'hb: out = 1;
4'ha: out = 0;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out = 1;
4'h5: out = 0;
4'h7: out = 1;
4'h6: out = 0;
4'hc: out = 0;
4'hd: out = 1;
4'hf: out = 0;
4'he: out = 1;
4'h8: out = 1;
4'h9: out = 0;
4'hb: out = 1;
4'ha: out = 0;
endcase
end
endmodule
module stimulus_gen (
input clk,
output reg a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c,d} <= 4'b0;
wavedrom_start();
repeat(16) @(posedge clk)
{a,b,c,d} <= count++;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{d,c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
reference_module good1 (
.a,
.b,
.c,
.d,
.out(out_ref) );
top_module top_module1 (
.a,
.b,
.c,
.d,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
vector1 | 19 | Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. | module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
| module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign {out_hi, out_lo} = in;
endmodule
module stimulus_gen (
input clk,
output logic [15:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
in <= $random;
initial begin
wavedrom_start("Random inputs");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(100) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_hi;
int errortime_out_hi;
int errors_out_lo;
int errortime_out_lo;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] in;
logic [7:0] out_hi_ref;
logic [7:0] out_hi_dut;
logic [7:0] out_lo_ref;
logic [7:0] out_lo_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,out_hi_ref,out_hi_dut,out_lo_ref,out_lo_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
reference_module good1 (
.in,
.out_hi(out_hi_ref),
.out_lo(out_lo_ref) );
top_module top_module1 (
.in,
.out_hi(out_hi_dut),
.out_lo(out_lo_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_hi) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_hi", stats1.errors_out_hi, stats1.errortime_out_hi);
else $display("Hint: Output '%s' has no mismatches.", "out_hi");
if (stats1.errors_out_lo) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_lo", stats1.errors_out_lo, stats1.errortime_out_lo);
else $display("Hint: Output '%s' has no mismatches.", "out_lo");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_hi_ref, out_lo_ref } === ( { out_hi_ref, out_lo_ref } ^ { out_hi_dut, out_lo_dut } ^ { out_hi_ref, out_lo_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_hi_ref !== ( out_hi_ref ^ out_hi_dut ^ out_hi_ref ))
begin if (stats1.errors_out_hi == 0) stats1.errortime_out_hi = $time;
stats1.errors_out_hi = stats1.errors_out_hi+1'b1; end
if (out_lo_ref !== ( out_lo_ref ^ out_lo_dut ^ out_lo_ref ))
begin if (stats1.errors_out_lo == 0) stats1.errortime_out_lo = $time;
stats1.errors_out_lo = stats1.errors_out_lo+1'b1; end
end
endmodule
|
norgate | 20 | Create a module that implements a NOR gate. | module top_module(
input a,
input b,
output out
);
| module top_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("NOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $random;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
reference_module good1 (
.a,
.b,
.out(out_ref) );
top_module top_module1 (
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
alwaysblock2 | 21 | Build an XOR gate three ways, using an assign statement (output out_assign), a combinational always block (output out_always_comb), and a clocked always block (output out_always_ff). Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed. | module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
| module top_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input a,
input b,
output out_assign,
output reg out_always_comb,
output reg out_always_ff
);
assign out_assign = a ^ b;
always @(*) out_always_comb = a ^ b;
always @(posedge clk) out_always_ff <= a ^ b;
endmodule
module stimulus_gen (
input clk,
output reg a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b} <= 1'b0;
wavedrom_start("XOR gate");
repeat(10) @(posedge clk)
{a,b} <= count++;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_assign;
int errortime_out_assign;
int errors_out_always_comb;
int errortime_out_always_comb;
int errors_out_always_ff;
int errortime_out_always_ff;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic out_assign_ref;
logic out_assign_dut;
logic out_always_comb_ref;
logic out_always_comb_dut;
logic out_always_ff_ref;
logic out_always_ff_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,out_assign_ref,out_assign_dut,out_always_comb_ref,out_always_comb_dut,out_always_ff_ref,out_always_ff_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
reference_module good1 (
.clk,
.a,
.b,
.out_assign(out_assign_ref),
.out_always_comb(out_always_comb_ref),
.out_always_ff(out_always_ff_ref) );
top_module top_module1 (
.clk,
.a,
.b,
.out_assign(out_assign_dut),
.out_always_comb(out_always_comb_dut),
.out_always_ff(out_always_ff_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_assign) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_assign", stats1.errors_out_assign, stats1.errortime_out_assign);
else $display("Hint: Output '%s' has no mismatches.", "out_assign");
if (stats1.errors_out_always_comb) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always_comb", stats1.errors_out_always_comb, stats1.errortime_out_always_comb);
else $display("Hint: Output '%s' has no mismatches.", "out_always_comb");
if (stats1.errors_out_always_ff) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_always_ff", stats1.errors_out_always_ff, stats1.errortime_out_always_ff);
else $display("Hint: Output '%s' has no mismatches.", "out_always_ff");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } === ( { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ^ { out_assign_dut, out_always_comb_dut, out_always_ff_dut } ^ { out_assign_ref, out_always_comb_ref, out_always_ff_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_assign_ref !== ( out_assign_ref ^ out_assign_dut ^ out_assign_ref ))
begin if (stats1.errors_out_assign == 0) stats1.errortime_out_assign = $time;
stats1.errors_out_assign = stats1.errors_out_assign+1'b1; end
if (out_always_comb_ref !== ( out_always_comb_ref ^ out_always_comb_dut ^ out_always_comb_ref ))
begin if (stats1.errors_out_always_comb == 0) stats1.errortime_out_always_comb = $time;
stats1.errors_out_always_comb = stats1.errors_out_always_comb+1'b1; end
if (out_always_ff_ref !== ( out_always_ff_ref ^ out_always_ff_dut ^ out_always_ff_ref ))
begin if (stats1.errors_out_always_ff == 0) stats1.errortime_out_always_ff = $time;
stats1.errors_out_always_ff = stats1.errors_out_always_ff+1'b1; end
end
endmodule
|
m2014_q6c | 22 | Consider the state machine shown below:
// A (0) --0--> B
// A (0) --1--> A
// B (0) --0--> C
// B (0) --1--> D
// C (0) --0--> E
// C (0) --1--> D
// D (0) --0--> F
// D (0) --1--> A
// E (1) --0--> E
// E (1) --1--> D
// F (1) --0--> C
// F (1) --1--> D
// Resets into state A. For this part, assume that a one-hot code is used with the state assignment y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.
// Write Verilog for the next-state signals Y2 and Y4 corresponding to signal y[2] and y[4]. Derive the logic equations by inspection assuming a one-hot encoding. | module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
| module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1]&~w;
assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w;
endmodule
module stimulus_gen (
input clk,
output logic[6:1] y,
output logic w,
input tb_match
);
int errored1 = 0;
int onehot_error = 0;
int temp;
initial begin
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
y <= 1<< ($unsigned($random) % 6);
w <= $random;
if (!tb_match) onehot_error++;
end
// Random.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
do
temp = $random;
while ( !{temp[6:5],temp[3:2]} == !{temp[4],temp[1]} );
// Make y[4,1] and y[6,5,3,2] mutually exclusive, so we can accept Y4=(~y[1] & ~y[4]) &w as a valid answer too.
y[6:1] <= temp[6:1];
w <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with semi-random inputs.");
if (!onehot_error && errored1)
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y2;
int errortime_Y2;
int errors_Y4;
int errortime_Y4;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [6:1] y;
logic w;
logic Y2_ref;
logic Y2_dut;
logic Y4_ref;
logic Y4_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y2_ref,Y2_dut,Y4_ref,Y4_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
reference_module good1 (
.y,
.w,
.Y2(Y2_ref),
.Y4(Y4_ref) );
top_module top_module1 (
.y,
.w,
.Y2(Y2_dut),
.Y4(Y4_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y2", stats1.errors_Y2, stats1.errortime_Y2);
else $display("Hint: Output '%s' has no mismatches.", "Y2");
if (stats1.errors_Y4) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y4", stats1.errors_Y4, stats1.errortime_Y4);
else $display("Hint: Output '%s' has no mismatches.", "Y4");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y2_ref, Y4_ref } === ( { Y2_ref, Y4_ref } ^ { Y2_dut, Y4_dut } ^ { Y2_ref, Y4_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y2_ref !== ( Y2_ref ^ Y2_dut ^ Y2_ref ))
begin if (stats1.errors_Y2 == 0) stats1.errortime_Y2 = $time;
stats1.errors_Y2 = stats1.errors_Y2+1'b1; end
if (Y4_ref !== ( Y4_ref ^ Y4_dut ^ Y4_ref ))
begin if (stats1.errors_Y4 == 0) stats1.errortime_Y4 = $time;
stats1.errors_Y4 = stats1.errors_Y4+1'b1; end
end
endmodule
|
mux256to1 | 23 | Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc. | module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
| module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
module stimulus_gen (
input clk,
output logic [255:0] in,
output logic [7:0] sel
);
always @(posedge clk, negedge clk) begin
for (int i=0;i<8; i++)
in[i*32+:32] <= $random;
sel <= $random;
end
initial begin
repeat(1000) @(negedge clk);
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [255:0] in;
logic [7:0] sel;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,sel,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.sel );
reference_module good1 (
.in,
.sel,
.out(out_ref) );
top_module top_module1 (
.in,
.sel,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
2014_q4a | 24 | Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers. | module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
| module top_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input w,
input R,
input E,
input L,
output reg Q
);
always @(posedge clk)
if (L)
Q <= R;
else if (E)
Q <= w;
endmodule
module stimulus_gen (
input clk,
output logic w, R, E, L
);
initial begin
repeat(200) @(posedge clk, negedge clk) begin
{w,R,E,L} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Q;
int errortime_Q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic w;
logic R;
logic E;
logic L;
logic Q_ref;
logic Q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,w,R,E,L,Q_ref,Q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.w,
.R,
.E,
.L );
reference_module good1 (
.clk,
.w,
.R,
.E,
.L,
.Q(Q_ref) );
top_module top_module1 (
.clk,
.w,
.R,
.E,
.L,
.Q(Q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Q", stats1.errors_Q, stats1.errortime_Q);
else $display("Hint: Output '%s' has no mismatches.", "Q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))
begin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;
stats1.errors_Q = stats1.errors_Q+1'b1; end
end
endmodule
|
ece241_2014_q4 | 25 | Given the finite state machine circuit described below, assume that the D flip-flops are initially reset to zero before the machine begins.
// Build this circuit in Verilog.
// Input x goes to three different two-input gates: a XOR, an AND, and a OR gate. Each of the three gates is connected to the input of a D flip-flop and then the flip-flop outputs all go to a three-input XNOR, whose output is Z. The second input of the XOR is its corresponding flip-flop's output, the second input of the AND is its corresponding flip-flop's complemented output, and finally the second input of the OR is its corresponding flip-flop's complementary output. | module top_module (
input clk,
input x,
output z
);
| module top_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input x,
output z
);
reg [2:0] s = 0;
always @(posedge clk) begin
s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x };
end
assign z = ~|s;
endmodule
module stimulus_gen (
input clk,
output logic x,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
x <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h0;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(posedge clk) x <= 2'h1;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
x <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x );
reference_module good1 (
.clk,
.x,
.z(z_ref) );
top_module top_module1 (
.clk,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
endmodule
|
circuit4 | 26 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d q
// 0ns 0 0 0 0 0
// 5ns 0 0 0 0 0
// 10ns 0 0 0 0 0
// 15ns 0 0 0 0 0
// 20ns 0 0 0 1 0
// 25ns 0 0 1 0 1
// 30ns 0 0 1 1 1
// 35ns 0 1 0 0 1
// 40ns 0 1 0 1 1
// 45ns 0 1 1 0 1
// 50ns 0 1 1 1 1
// 55ns 1 0 0 0 0
// 60ns 1 0 0 1 0
// 65ns 1 0 1 0 1
// 70ns 1 0 1 1 1
// 75ns 1 1 0 0 1
// 80ns 1 1 0 1 1
// 85ns 1 1 1 0 1
// 90ns 1 1 1 1 1 | module top_module (
input a,
input b,
input c,
input d,
output q
);
| module top_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d} <= 0;
repeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
reference_module good1 (
.a,
.b,
.c,
.d,
.q(q_ref) );
top_module top_module1 (
.a,
.b,
.c,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
rule110 | 27 | Rule 110 is a one-dimensional cellular automaton with interesting properties (such as being Turing-complete). There is a one-dimensional array of cells (on or off). At each time step, the state of each cell changes. In Rule 110, the next state of each cell depends only on itself and its two neighbours, according to the following table:
// Left | Center | Right | Center's next state
// 1 | 1 | 1 | 0
// 1 | 1 | 0 | 1
// 1 | 0 | 1 | 1
// 1 | 0 | 0 | 0
// 0 | 1 | 1 | 1
// 0 | 1 | 0 | 1
// 0 | 0 | 1 | 1
// 0 | 0 | 0 | 0
// In this circuit, create a 512-cell system (q[511:0]), and advance by one time step each clock cycle. The synchronous active high load input indicates the state of the system should be loaded with data[511:0]. Assume the boundaries (q[-1] and q[512]) are both zero (off). | module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
| module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |
(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )
;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |
(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )
;
end
end
endmodule
module stimulus_gen (
input clk,
output reg load,
output reg[511:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
data <= 0;
data[0] <= 1'b1;
load <= 1;
@(posedge clk); wavedrom_start("Load q[511:0] = 1: See Hint.");
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(10) @(posedge clk);
wavedrom_stop();
data <= 0;
data[256] <= 1'b1;
load <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 512'h4df;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= $random;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 0;
load <= 1;
repeat (20) @(posedge clk);
@(posedge clk) data <= 2;
@(posedge clk) data <= 4;
@(posedge clk) begin
data <= 9;
load <= 0;
end
@(posedge clk) data <= 12;
repeat(100) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [511:0] data;
logic [511:0] q_ref;
logic [511:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.data );
reference_module good1 (
.clk,
.load,
.data,
.q(q_ref) );
top_module top_module1 (
.clk,
.load,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
fsm3s | 28 | The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A.
// State | Next state in=0, Next state in=1 | Output
// A | A, B | 0
// B | C, B | 0
// C | A, D | 0
// D | C, B | 1 | module top_module (
input clk,
input in,
input reset,
output out
);
| module top_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
module stimulus_gen (
input clk,
output logic in,
output logic reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk) reset <= 0; in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk);
@(negedge clk) reset <= 1;
@(posedge clk) reset <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic reset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
reference_module good1 (
.clk,
.in,
.reset,
.out(out_ref) );
top_module top_module1 (
.clk,
.in,
.reset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
circuit5 | 29 | This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
// time a b c d e q
// 0ns x x x x x x
// 5ns x x x x x x
// 10ns x x x x x x
// 15ns a b 0 d e b
// 20ns a b 1 d e e
// 25ns a b 2 d e a
// 30ns a b 3 d e d
// 35ns a b 4 d e f
// 40ns a b 5 d e f
// 45ns a b 6 d e f
// 50ns a b 7 d e f
// 55ns a b 8 d e f
// 60ns a b 9 d e f
// 65ns a b a d e f
// 70ns a b b d e f
// 75ns a b c d e f
// 80ns a b d d e f
// 85ns a b e d e f
// 90ns a b f d e f | module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
| module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
module stimulus_gen (
input clk,
output logic [3:0] a,b,c,d,e,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d,e} <= {20'hab0de};
repeat(18) @(posedge clk, negedge clk) c <= c + 1;
wavedrom_stop();
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d,e} <= {20'h12034};
repeat(8) @(posedge clk, negedge clk) c <= c + 1;
@(posedge clk) {a,b,c,d,e} <= {20'h56078};
repeat(8) @(posedge clk, negedge clk) c <= c + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] a;
logic [3:0] b;
logic [3:0] c;
logic [3:0] d;
logic [3:0] e;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e );
reference_module good1 (
.a,
.b,
.c,
.d,
.e,
.q(q_ref) );
top_module top_module1 (
.a,
.b,
.c,
.d,
.e,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
bugs_mux2 | 30 | Find the bug and fix this 8-bit wide 2-to-1 mux.
// module top_module (
// input sel,
// input [7:0] a,
// input [7:0] b,
// output out );
// assign out = (~sel & a) | (sel & b);
// endmodule | module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
| module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = sel ? a : b;
endmodule
module stimulus_gen (
input clk,
output logic sel,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b, sel} <= '0;
@(negedge clk) wavedrom_start("");
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b0};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a,b,sel} <= {8'haa, 8'hbb, 1'b1};
@(posedge clk, negedge clk) {a, b} <= {8'hff, 8'h00}; sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b1;
@(posedge clk, negedge clk) sel <= 1'b0;
@(posedge clk, negedge clk) sel <= 1'b1;
@(posedge clk, negedge clk) sel <= 1'b1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,sel} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic sel;
logic [7:0] a;
logic [7:0] b;
logic [7:0] out_ref;
logic [7:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,sel,a,b,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.sel,
.a,
.b );
reference_module good1 (
.sel,
.a,
.b,
.out(out_ref) );
top_module top_module1 (
.sel,
.a,
.b,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
mt2015_muxdff | 31 | Consider this Verilog module "full_module":
// module full_module (
// input [2:0] r,
// input L,
// input clk,
// output reg [2:0] q
);
// always @(posedge clk) begin
// if (L) begin
// q <= r;
// end else begin
// q <= {q[1] ^ q[2], q[0], q[2]};
// end
// end
// endmodule
// You want to create a hierarchical Verilog design where a flipflop and 2-1 multiplexer are in a submodule, and that submodule is instantiated three times in this code. Create the submodule called "top_module".
| module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
| module top_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.
*/
module reference_module(
input clk,
input L,
input q_in,
input r_in,
output reg Q);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
module stimulus_gen (
input clk,
output logic L,
output logic r_in,
output logic q_in
);
always @(posedge clk, negedge clk)
{L, r_in, q_in} <= $random % 8;
initial begin
repeat(100) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Q;
int errortime_Q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic L;
logic q_in;
logic r_in;
logic Q_ref;
logic Q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,L,q_in,r_in,Q_ref,Q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.L,
.q_in,
.r_in );
reference_module good1 (
.clk,
.L,
.q_in,
.r_in,
.Q(Q_ref) );
top_module top_module1 (
.clk,
.L,
.q_in,
.r_in,
.Q(Q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Q", stats1.errors_Q, stats1.errortime_Q);
else $display("Hint: Output '%s' has no mismatches.", "Q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))
begin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;
stats1.errors_Q = stats1.errors_Q+1'b1; end
end
endmodule
|
edgecapture | 32 | For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (active high synchronous reset). | module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
| module top_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input reset,
input [31:0] in,
output reg [31:0] out);
reg [31:0] d_last;
always @(posedge clk) begin
d_last <= in;
if (reset)
out <= '0;
else
out <= out | (~in & d_last);
end
endmodule
module stimulus_gen (
input clk,
input tb_match,
output reg [31:0] in,
output reg reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
in <= 0;
reset <= 1;
@(posedge clk);
reset <= 1;
in = 0;
@(negedge clk) wavedrom_start("Example");
repeat(1) @(posedge clk);
reset = 0;
@(posedge clk) in = 32'h2;
repeat(4) @(posedge clk);
in = 32'he;
repeat(2) @(posedge clk);
in = 0;
@(posedge clk) in = 32'h2;
repeat(2) @(posedge clk);
reset = 1;
@(posedge clk);
reset = 0; in = 0;
repeat(3) @(posedge clk);
@(negedge clk) wavedrom_stop();
@(negedge clk) wavedrom_start("");
repeat(2) @(posedge clk);
in <= 1;
repeat(2) @(posedge clk);
in <= 0;
repeat(2) @(negedge clk);
in <= 6;
repeat(1) @(negedge clk);
in <= 0;
repeat(2) @(posedge clk);
in <= 32'h10;
repeat(2) @(posedge clk);
reset <= 1;
repeat(1) @(posedge clk);
in <= 32'h0;
repeat(1) @(posedge clk);
reset <= 0;
repeat(1) @(posedge clk);
reset <= 1;
in <= 32'h20;
repeat(1) @(posedge clk);
reset <= 0;
in <= 32'h00;
repeat(2) @(posedge clk);
@(negedge clk) wavedrom_stop();
repeat(200)
@(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 15);
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [31:0] in;
logic [31:0] out_ref;
logic [31:0] out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.in );
reference_module good1 (
.clk,
.reset,
.in,
.out(out_ref) );
top_module top_module1 (
.clk,
.reset,
.in,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
endmodule
|
dff8 | 33 | Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk. | module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
| module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input [7:0] d,
output reg [7:0] q);
initial
q = 8'h0;
always @(posedge clk)
q <= d;
endmodule
module stimulus_gen (
input clk,
output reg [7:0] d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
always @(posedge clk, negedge clk)
d <= $random % 256;
initial begin
@(posedge clk);
wavedrom_start("Positive-edge triggered DFF");
repeat(10) @(posedge clk);
wavedrom_stop();
#100;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] d;
logic [7:0] q_ref;
logic [7:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d );
reference_module good1 (
.clk,
.d,
.q(q_ref) );
top_module top_module1 (
.clk,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
endmodule
|
ece241_2014_q1c | 34 | Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. | module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
| module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
wire [8:0] sum = a+b;
assign s = sum[7:0];
assign overflow = !(a[7]^b[7]) && (a[7] != s[7]);
endmodule
module stimulus_gen (
input clk,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b} <= 0;
@(negedge clk) wavedrom_start();
@(posedge clk) {a, b} <= 16'h0;
@(posedge clk) {a, b} <= 16'h0070;
@(posedge clk) {a, b} <= 16'h7070;
@(posedge clk) {a, b} <= 16'h7090;
@(posedge clk) {a, b} <= 16'h9070;
@(posedge clk) {a, b} <= 16'h9090;
@(posedge clk) {a, b} <= 16'h90ff;
@(negedge clk) wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b} <= $random;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_s;
int errortime_s;
int errors_overflow;
int errortime_overflow;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] a;
logic [7:0] b;
logic [7:0] s_ref;
logic [7:0] s_dut;
logic overflow_ref;
logic overflow_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,s_ref,s_dut,overflow_ref,overflow_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
reference_module good1 (
.a,
.b,
.s(s_ref),
.overflow(overflow_ref) );
top_module top_module1 (
.a,
.b,
.s(s_dut),
.overflow(overflow_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_s) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "s", stats1.errors_s, stats1.errortime_s);
else $display("Hint: Output '%s' has no mismatches.", "s");
if (stats1.errors_overflow) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "overflow", stats1.errors_overflow, stats1.errortime_overflow);
else $display("Hint: Output '%s' has no mismatches.", "overflow");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { s_ref, overflow_ref } === ( { s_ref, overflow_ref } ^ { s_dut, overflow_dut } ^ { s_ref, overflow_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (s_ref !== ( s_ref ^ s_dut ^ s_ref ))
begin if (stats1.errors_s == 0) stats1.errortime_s = $time;
stats1.errors_s = stats1.errors_s+1'b1; end
if (overflow_ref !== ( overflow_ref ^ overflow_dut ^ overflow_ref ))
begin if (stats1.errors_overflow == 0) stats1.errortime_overflow = $time;
stats1.errors_overflow = stats1.errors_overflow+1'b1; end
end
endmodule
|
review2015_fsmonehot | 35 | Given the following Moore state machine with 3 input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done). Unless otherwise stated in the diagram below, assume outputs are 0 and inputs are don't cares.
// S () --d=0--> S
// S () --d=1--> S1
// S1 () --d=0--> S
// S1 () --d=1--> S11
// S11 () --d=0--> S110
// S11 () --d=1--> S11
// S110 () --d=0--> S
// S110 () --d=1--> B0
// B0 (shift_ena=1) -- (always go to next cycle) --> B1
// B1 (shift_ena=1) -- (always go to next cycle) --> B2
// B2 (shift_ena=1) -- (always go to next cycle) --> B3
// B3 (shift_ena=1) -- (always go to next cycle) --> Count
// Count (counting=1) --!(done_counting)--> Count
// Count (counting=1) --(done_counting)--> Wait
// Wait (done=1) --ack=0--> Wait
// Wait (done=1) --ack=1--> S
// At reset, the state machine starts in state "S". Derive next-state logic equations and output logic equations by inspection assuming the following one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait) = (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
// Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine.
// Write code that generates the following equations:
// - B3_next -- next-state logic for state B3
// - S_next
// - S1_next
// - Count_next
// - Wait_next
// - done -- output logic
// - counting
// - shift_ena
| module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
| module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;
assign S1_next = state[S]&d;
assign Count_next = state[B3] | state[Count]&~done_counting;
assign Wait_next = state[Count]&done_counting | state[Wait]&~ack;
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = |state[B3:B0];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;
assign S1_next = state[S]&d;
assign Count_next = state[B3] | state[Count]&~done_counting;
assign Wait_next = state[Count]&done_counting | state[Wait]&~ack;
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = |state[B3:B0];
endmodule
module stimulus_gen (
input clk,
output reg d, done_counting, ack,
output reg [9:0] state,
input tb_match
);
bit failed = 0;
bit fail_onehot = 0;
always @(posedge clk, negedge clk)
if (!tb_match)
failed <= 1;
initial begin
{d, done_counting, ack} <= 3'h0;
state <= 10'h0;
repeat(300) @(posedge clk, negedge clk) begin
{d, done_counting, ack} = $random;
state <= 1<< ($unsigned($random) % 10);
end
@(posedge clk) fail_onehot <= failed;
repeat(3000) @(posedge clk, negedge clk) begin
{d, done_counting, ack} = $random;
state <= $random;
end
@(posedge clk);
if (!fail_onehot && failed) begin
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
$display ("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_B3_next;
int errortime_B3_next;
int errors_S_next;
int errortime_S_next;
int errors_S1_next;
int errortime_S1_next;
int errors_Count_next;
int errortime_Count_next;
int errors_Wait_next;
int errortime_Wait_next;
int errors_done;
int errortime_done;
int errors_counting;
int errortime_counting;
int errors_shift_ena;
int errortime_shift_ena;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic done_counting;
logic ack;
logic [9:0] state;
logic B3_next_ref;
logic B3_next_dut;
logic S_next_ref;
logic S_next_dut;
logic S1_next_ref;
logic S1_next_dut;
logic Count_next_ref;
logic Count_next_dut;
logic Wait_next_ref;
logic Wait_next_dut;
logic done_ref;
logic done_dut;
logic counting_ref;
logic counting_dut;
logic shift_ena_ref;
logic shift_ena_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,d,done_counting,ack,state,B3_next_ref,B3_next_dut,S_next_ref,S_next_dut,S1_next_ref,S1_next_dut,Count_next_ref,Count_next_dut,Wait_next_ref,Wait_next_dut,done_ref,done_dut,counting_ref,counting_dut,shift_ena_ref,shift_ena_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.done_counting,
.ack,
.state );
reference_module good1 (
.d,
.done_counting,
.ack,
.state,
.B3_next(B3_next_ref),
.S_next(S_next_ref),
.S1_next(S1_next_ref),
.Count_next(Count_next_ref),
.Wait_next(Wait_next_ref),
.done(done_ref),
.counting(counting_ref),
.shift_ena(shift_ena_ref) );
top_module top_module1 (
.d,
.done_counting,
.ack,
.state,
.B3_next(B3_next_dut),
.S_next(S_next_dut),
.S1_next(S1_next_dut),
.Count_next(Count_next_dut),
.Wait_next(Wait_next_dut),
.done(done_dut),
.counting(counting_dut),
.shift_ena(shift_ena_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_B3_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "B3_next", stats1.errors_B3_next, stats1.errortime_B3_next);
else $display("Hint: Output '%s' has no mismatches.", "B3_next");
if (stats1.errors_S_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "S_next", stats1.errors_S_next, stats1.errortime_S_next);
else $display("Hint: Output '%s' has no mismatches.", "S_next");
if (stats1.errors_S1_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "S1_next", stats1.errors_S1_next, stats1.errortime_S1_next);
else $display("Hint: Output '%s' has no mismatches.", "S1_next");
if (stats1.errors_Count_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Count_next", stats1.errors_Count_next, stats1.errortime_Count_next);
else $display("Hint: Output '%s' has no mismatches.", "Count_next");
if (stats1.errors_Wait_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Wait_next", stats1.errors_Wait_next, stats1.errortime_Wait_next);
else $display("Hint: Output '%s' has no mismatches.", "Wait_next");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
if (stats1.errors_counting) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "counting", stats1.errors_counting, stats1.errortime_counting);
else $display("Hint: Output '%s' has no mismatches.", "counting");
if (stats1.errors_shift_ena) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "shift_ena", stats1.errors_shift_ena, stats1.errortime_shift_ena);
else $display("Hint: Output '%s' has no mismatches.", "shift_ena");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } === ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ^ { B3_next_dut, S_next_dut, S1_next_dut, Count_next_dut, Wait_next_dut, done_dut, counting_dut, shift_ena_dut } ^ { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (B3_next_ref !== ( B3_next_ref ^ B3_next_dut ^ B3_next_ref ))
begin if (stats1.errors_B3_next == 0) stats1.errortime_B3_next = $time;
stats1.errors_B3_next = stats1.errors_B3_next+1'b1; end
if (S_next_ref !== ( S_next_ref ^ S_next_dut ^ S_next_ref ))
begin if (stats1.errors_S_next == 0) stats1.errortime_S_next = $time;
stats1.errors_S_next = stats1.errors_S_next+1'b1; end
if (S1_next_ref !== ( S1_next_ref ^ S1_next_dut ^ S1_next_ref ))
begin if (stats1.errors_S1_next == 0) stats1.errortime_S1_next = $time;
stats1.errors_S1_next = stats1.errors_S1_next+1'b1; end
if (Count_next_ref !== ( Count_next_ref ^ Count_next_dut ^ Count_next_ref ))
begin if (stats1.errors_Count_next == 0) stats1.errortime_Count_next = $time;
stats1.errors_Count_next = stats1.errors_Count_next+1'b1; end
if (Wait_next_ref !== ( Wait_next_ref ^ Wait_next_dut ^ Wait_next_ref ))
begin if (stats1.errors_Wait_next == 0) stats1.errortime_Wait_next = $time;
stats1.errors_Wait_next = stats1.errors_Wait_next+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
if (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))
begin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;
stats1.errors_counting = stats1.errors_counting+1'b1; end
if (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))
begin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;
stats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end
end
endmodule
|
counter_2bc | 36 | Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asynchronous reset that resets the counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit counter value. | module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
| module top_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
if(state < 3 && train_taken)
state <= state + 1;
else if(state > 0 && !train_taken)
state <= state - 1;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module(
input clk,
input areset,
input train_valid,
input train_taken,
output logic [1:0] state
);
always @(posedge clk, posedge areset) begin
if (areset)
state <= 1;
else if (train_valid) begin
if(state < 3 && train_taken)
state <= state + 1;
else if(state > 0 && !train_taken)
state <= state - 1;
end
end
endmodule
module stimulus_gen(
input clk,
output logic areset,
output logic train_valid,
output train_taken,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
output int wavedrom_hide_after_time
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
assign areset = reset;
logic train_taken_r;
assign train_taken = train_valid ? train_taken_r : 1'bx;
initial begin
@(posedge clk);
@(posedge clk) reset <= 1;
@(posedge clk) reset <= 0;
train_taken_r <= 1;
train_valid <= 1;
wavedrom_start("Asynchronous reset");
reset_test(1); // Test for asynchronous reset
wavedrom_stop();
@(posedge clk) reset <= 1;
train_taken_r <= 1;
train_valid <= 0;
@(posedge clk) reset <= 0;
wavedrom_start("Count up, then down");
train_taken_r <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
train_taken_r <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
wavedrom_stop();
repeat(1000) @(posedge clk,negedge clk)
{train_valid, train_taken_r} <= {$urandom} ;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_state;
int errortime_state;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic train_valid;
logic train_taken;
logic [1:0] state_ref;
logic [1:0] state_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,train_valid,train_taken,state_ref,state_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.train_valid,
.train_taken );
reference_module good1 (
.clk,
.areset,
.train_valid,
.train_taken,
.state(state_ref) );
top_module top_module1 (
.clk,
.areset,
.train_valid,
.train_taken,
.state(state_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "state", stats1.errors_state, stats1.errortime_state);
else $display("Hint: Output '%s' has no mismatches.", "state");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { state_ref } === ( { state_ref } ^ { state_dut } ^ { state_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (state_ref !== ( state_ref ^ state_dut ^ state_ref ))
begin if (stats1.errors_state == 0) stats1.errortime_state = $time;
stats1.errors_state = stats1.errors_state+1'b1; end
end
endmodule
|
always_casez | 37 | Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high. | module top_module (
input [7:0] in,
output reg [2:0] pos
);
| module top_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4;
8'bzz1zzzzz: pos = 3'h5;
8'bz1zzzzzz: pos = 3'h6;
8'b1zzzzzzz: pos = 3'h7;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [7:0] in,
output reg [2:0] pos
);
always @(*) begin
casez (in)
default : pos = 2'h0;
8'bzzzzzzz1: pos = 3'h0;
8'bzzzzzz1z: pos = 3'h1;
8'bzzzzz1zz: pos = 3'h2;
8'bzzzz1zzz: pos = 3'h3;
8'bzzz1zzzz: pos = 3'h4;
8'bzz1zzzzz: pos = 3'h5;
8'bz1zzzzzz: pos = 3'h6;
8'b1zzzzzzz: pos = 3'h7;
endcase
end
endmodule
module stimulus_gen (
input clk,
output logic [7:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Priority encoder");
@(posedge clk) in <= 8'h1;
repeat(8) @(posedge clk) in <= in << 1;
in <= 8'h10;
repeat(8) @(posedge clk) in <= in + 1;
@(negedge clk) wavedrom_stop();
repeat(50) @(posedge clk, negedge clk) begin
in <= $urandom;
end
repeat(260) @(posedge clk, negedge clk) begin
in <= in + 1;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_pos;
int errortime_pos;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic [2:0] pos_ref;
logic [2:0] pos_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
reference_module good1 (
.in,
.pos(pos_ref) );
top_module top_module1 (
.in,
.pos(pos_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_pos) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "pos", stats1.errors_pos, stats1.errortime_pos);
else $display("Hint: Output '%s' has no mismatches.", "pos");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))
begin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;
stats1.errors_pos = stats1.errors_pos+1'b1; end
end
endmodule
|
always_nolatches | 38 | Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.
// Scancode[15:0] | Arrow key
// 16'he06b | left arrow
// 16'he072 | down arrow
// 16'he074 | right arrow
// 16'he075 | up arrow
// Anything else | none
// Your circuit has one 16-bit input, and four outputs. Build this circuit that recognizes these four scancodes and asserts the correct output.
| module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
| module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module reference_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
module stimulus_gen (
input clk,
output logic [15:0] scancode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Recognize arrow keys");
@(posedge clk) scancode <= 16'h0;
@(posedge clk) scancode <= 16'h1;
@(posedge clk) scancode <= 16'he075;
@(posedge clk) scancode <= 16'he06b;
@(posedge clk) scancode <= 16'he06c;
@(posedge clk) scancode <= 16'he072;
@(posedge clk) scancode <= 16'he074;
@(posedge clk) scancode <= 16'he076;
@(posedge clk) scancode <= 16'hffff;
@(negedge clk) wavedrom_stop();
repeat(30000) @(posedge clk, negedge clk) begin
scancode <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_left;
int errortime_left;
int errors_down;
int errortime_down;
int errors_right;
int errortime_right;
int errors_up;
int errortime_up;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] scancode;
logic left_ref;
logic left_dut;
logic down_ref;
logic down_dut;
logic right_ref;
logic right_dut;
logic up_ref;
logic up_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,scancode,left_ref,left_dut,down_ref,down_dut,right_ref,right_dut,up_ref,up_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.scancode );
reference_module good1 (
.scancode,
.left(left_ref),
.down(down_ref),
.right(right_ref),
.up(up_ref) );
top_module top_module1 (
.scancode,
.left(left_dut),
.down(down_dut),
.right(right_dut),
.up(up_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "left", stats1.errors_left, stats1.errortime_left);
else $display("Hint: Output '%s' has no mismatches.", "left");
if (stats1.errors_down) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "down", stats1.errors_down, stats1.errortime_down);
else $display("Hint: Output '%s' has no mismatches.", "down");
if (stats1.errors_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "right", stats1.errors_right, stats1.errortime_right);
else $display("Hint: Output '%s' has no mismatches.", "right");
if (stats1.errors_up) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "up", stats1.errors_up, stats1.errortime_up);
else $display("Hint: Output '%s' has no mismatches.", "up");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { left_ref, down_ref, right_ref, up_ref } === ( { left_ref, down_ref, right_ref, up_ref } ^ { left_dut, down_dut, right_dut, up_dut } ^ { left_ref, down_ref, right_ref, up_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (left_ref !== ( left_ref ^ left_dut ^ left_ref ))
begin if (stats1.errors_left == 0) stats1.errortime_left = $time;
stats1.errors_left = stats1.errors_left+1'b1; end
if (down_ref !== ( down_ref ^ down_dut ^ down_ref ))
begin if (stats1.errors_down == 0) stats1.errortime_down = $time;
stats1.errors_down = stats1.errors_down+1'b1; end
if (right_ref !== ( right_ref ^ right_dut ^ right_ref ))
begin if (stats1.errors_right == 0) stats1.errortime_right = $time;
stats1.errors_right = stats1.errors_right+1'b1; end
if (up_ref !== ( up_ref ^ up_dut ^ up_ref ))
begin if (stats1.errors_up == 0) stats1.errortime_up = $time;
stats1.errors_up = stats1.errors_up+1'b1; end
end
endmodule
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