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// IP VLNV: xilinx.com:hls:doGain:1.0
// IP Revision: 1712040438

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
top_doGain_0_0 your_instance_name (
  .s_axi_CRTL_BUS_AWADDR(s_axi_CRTL_BUS_AWADDR),    // input wire [4 : 0] s_axi_CRTL_BUS_AWADDR
  .s_axi_CRTL_BUS_AWVALID(s_axi_CRTL_BUS_AWVALID),  // input wire s_axi_CRTL_BUS_AWVALID
  .s_axi_CRTL_BUS_AWREADY(s_axi_CRTL_BUS_AWREADY),  // output wire s_axi_CRTL_BUS_AWREADY
  .s_axi_CRTL_BUS_WDATA(s_axi_CRTL_BUS_WDATA),      // input wire [31 : 0] s_axi_CRTL_BUS_WDATA
  .s_axi_CRTL_BUS_WSTRB(s_axi_CRTL_BUS_WSTRB),      // input wire [3 : 0] s_axi_CRTL_BUS_WSTRB
  .s_axi_CRTL_BUS_WVALID(s_axi_CRTL_BUS_WVALID),    // input wire s_axi_CRTL_BUS_WVALID
  .s_axi_CRTL_BUS_WREADY(s_axi_CRTL_BUS_WREADY),    // output wire s_axi_CRTL_BUS_WREADY
  .s_axi_CRTL_BUS_BRESP(s_axi_CRTL_BUS_BRESP),      // output wire [1 : 0] s_axi_CRTL_BUS_BRESP
  .s_axi_CRTL_BUS_BVALID(s_axi_CRTL_BUS_BVALID),    // output wire s_axi_CRTL_BUS_BVALID
  .s_axi_CRTL_BUS_BREADY(s_axi_CRTL_BUS_BREADY),    // input wire s_axi_CRTL_BUS_BREADY
  .s_axi_CRTL_BUS_ARADDR(s_axi_CRTL_BUS_ARADDR),    // input wire [4 : 0] s_axi_CRTL_BUS_ARADDR
  .s_axi_CRTL_BUS_ARVALID(s_axi_CRTL_BUS_ARVALID),  // input wire s_axi_CRTL_BUS_ARVALID
  .s_axi_CRTL_BUS_ARREADY(s_axi_CRTL_BUS_ARREADY),  // output wire s_axi_CRTL_BUS_ARREADY
  .s_axi_CRTL_BUS_RDATA(s_axi_CRTL_BUS_RDATA),      // output wire [31 : 0] s_axi_CRTL_BUS_RDATA
  .s_axi_CRTL_BUS_RRESP(s_axi_CRTL_BUS_RRESP),      // output wire [1 : 0] s_axi_CRTL_BUS_RRESP
  .s_axi_CRTL_BUS_RVALID(s_axi_CRTL_BUS_RVALID),    // output wire s_axi_CRTL_BUS_RVALID
  .s_axi_CRTL_BUS_RREADY(s_axi_CRTL_BUS_RREADY),    // input wire s_axi_CRTL_BUS_RREADY
  .ap_clk(ap_clk),                                  // input wire ap_clk
  .ap_rst_n(ap_rst_n),                              // input wire ap_rst_n
  .interrupt(interrupt),                            // output wire interrupt
  .inStream_TVALID(inStream_TVALID),                // input wire inStream_TVALID
  .inStream_TREADY(inStream_TREADY),                // output wire inStream_TREADY
  .inStream_TDATA(inStream_TDATA),                  // input wire [31 : 0] inStream_TDATA
  .inStream_TDEST(inStream_TDEST),                  // input wire [5 : 0] inStream_TDEST
  .inStream_TKEEP(inStream_TKEEP),                  // input wire [3 : 0] inStream_TKEEP
  .inStream_TSTRB(inStream_TSTRB),                  // input wire [3 : 0] inStream_TSTRB
  .inStream_TUSER(inStream_TUSER),                  // input wire [1 : 0] inStream_TUSER
  .inStream_TLAST(inStream_TLAST),                  // input wire [0 : 0] inStream_TLAST
  .inStream_TID(inStream_TID),                      // input wire [4 : 0] inStream_TID
  .outStream_TVALID(outStream_TVALID),              // output wire outStream_TVALID
  .outStream_TREADY(outStream_TREADY),              // input wire outStream_TREADY
  .outStream_TDATA(outStream_TDATA),                // output wire [31 : 0] outStream_TDATA
  .outStream_TDEST(outStream_TDEST),                // output wire [5 : 0] outStream_TDEST
  .outStream_TKEEP(outStream_TKEEP),                // output wire [3 : 0] outStream_TKEEP
  .outStream_TSTRB(outStream_TSTRB),                // output wire [3 : 0] outStream_TSTRB
  .outStream_TUSER(outStream_TUSER),                // output wire [1 : 0] outStream_TUSER
  .outStream_TLAST(outStream_TLAST),                // output wire [0 : 0] outStream_TLAST
  .outStream_TID(outStream_TID)                    // output wire [4 : 0] outStream_TID
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file top_doGain_0_0.v when simulating
// the core, top_doGain_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

