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// IP VLNV: xilinx.com:ip:axis_interconnect:1.1
// IP Revision: 17

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axis_interconnect_in your_instance_name (
  .ACLK(ACLK),                                  // input wire ACLK
  .ARESETN(ARESETN),                            // input wire ARESETN
  .S00_AXIS_ACLK(S00_AXIS_ACLK),                // input wire S00_AXIS_ACLK
  .S01_AXIS_ACLK(S01_AXIS_ACLK),                // input wire S01_AXIS_ACLK
  .S02_AXIS_ACLK(S02_AXIS_ACLK),                // input wire S02_AXIS_ACLK
  .S03_AXIS_ACLK(S03_AXIS_ACLK),                // input wire S03_AXIS_ACLK
  .S04_AXIS_ACLK(S04_AXIS_ACLK),                // input wire S04_AXIS_ACLK
  .S00_AXIS_ARESETN(S00_AXIS_ARESETN),          // input wire S00_AXIS_ARESETN
  .S01_AXIS_ARESETN(S01_AXIS_ARESETN),          // input wire S01_AXIS_ARESETN
  .S02_AXIS_ARESETN(S02_AXIS_ARESETN),          // input wire S02_AXIS_ARESETN
  .S03_AXIS_ARESETN(S03_AXIS_ARESETN),          // input wire S03_AXIS_ARESETN
  .S04_AXIS_ARESETN(S04_AXIS_ARESETN),          // input wire S04_AXIS_ARESETN
  .S00_AXIS_TVALID(S00_AXIS_TVALID),            // input wire S00_AXIS_TVALID
  .S01_AXIS_TVALID(S01_AXIS_TVALID),            // input wire S01_AXIS_TVALID
  .S02_AXIS_TVALID(S02_AXIS_TVALID),            // input wire S02_AXIS_TVALID
  .S03_AXIS_TVALID(S03_AXIS_TVALID),            // input wire S03_AXIS_TVALID
  .S04_AXIS_TVALID(S04_AXIS_TVALID),            // input wire S04_AXIS_TVALID
  .S00_AXIS_TREADY(S00_AXIS_TREADY),            // output wire S00_AXIS_TREADY
  .S01_AXIS_TREADY(S01_AXIS_TREADY),            // output wire S01_AXIS_TREADY
  .S02_AXIS_TREADY(S02_AXIS_TREADY),            // output wire S02_AXIS_TREADY
  .S03_AXIS_TREADY(S03_AXIS_TREADY),            // output wire S03_AXIS_TREADY
  .S04_AXIS_TREADY(S04_AXIS_TREADY),            // output wire S04_AXIS_TREADY
  .S00_AXIS_TDATA(S00_AXIS_TDATA),              // input wire [63 : 0] S00_AXIS_TDATA
  .S01_AXIS_TDATA(S01_AXIS_TDATA),              // input wire [63 : 0] S01_AXIS_TDATA
  .S02_AXIS_TDATA(S02_AXIS_TDATA),              // input wire [63 : 0] S02_AXIS_TDATA
  .S03_AXIS_TDATA(S03_AXIS_TDATA),              // input wire [63 : 0] S03_AXIS_TDATA
  .S04_AXIS_TDATA(S04_AXIS_TDATA),              // input wire [63 : 0] S04_AXIS_TDATA
  .S00_AXIS_TKEEP(S00_AXIS_TKEEP),              // input wire [7 : 0] S00_AXIS_TKEEP
  .S01_AXIS_TKEEP(S01_AXIS_TKEEP),              // input wire [7 : 0] S01_AXIS_TKEEP
  .S02_AXIS_TKEEP(S02_AXIS_TKEEP),              // input wire [7 : 0] S02_AXIS_TKEEP
  .S03_AXIS_TKEEP(S03_AXIS_TKEEP),              // input wire [7 : 0] S03_AXIS_TKEEP
  .S04_AXIS_TKEEP(S04_AXIS_TKEEP),              // input wire [7 : 0] S04_AXIS_TKEEP
  .S00_AXIS_TLAST(S00_AXIS_TLAST),              // input wire S00_AXIS_TLAST
  .S01_AXIS_TLAST(S01_AXIS_TLAST),              // input wire S01_AXIS_TLAST
  .S02_AXIS_TLAST(S02_AXIS_TLAST),              // input wire S02_AXIS_TLAST
  .S03_AXIS_TLAST(S03_AXIS_TLAST),              // input wire S03_AXIS_TLAST
  .S04_AXIS_TLAST(S04_AXIS_TLAST),              // input wire S04_AXIS_TLAST
  .S00_AXIS_TID(S00_AXIS_TID),                  // input wire [2 : 0] S00_AXIS_TID
  .S01_AXIS_TID(S01_AXIS_TID),                  // input wire [2 : 0] S01_AXIS_TID
  .S02_AXIS_TID(S02_AXIS_TID),                  // input wire [2 : 0] S02_AXIS_TID
  .S03_AXIS_TID(S03_AXIS_TID),                  // input wire [2 : 0] S03_AXIS_TID
  .S04_AXIS_TID(S04_AXIS_TID),                  // input wire [2 : 0] S04_AXIS_TID
  .S00_AXIS_TUSER(S00_AXIS_TUSER),              // input wire [7 : 0] S00_AXIS_TUSER
  .S01_AXIS_TUSER(S01_AXIS_TUSER),              // input wire [7 : 0] S01_AXIS_TUSER
  .S02_AXIS_TUSER(S02_AXIS_TUSER),              // input wire [7 : 0] S02_AXIS_TUSER
  .S03_AXIS_TUSER(S03_AXIS_TUSER),              // input wire [7 : 0] S03_AXIS_TUSER
  .S04_AXIS_TUSER(S04_AXIS_TUSER),              // input wire [7 : 0] S04_AXIS_TUSER
  .M00_AXIS_ACLK(M00_AXIS_ACLK),                // input wire M00_AXIS_ACLK
  .M00_AXIS_ARESETN(M00_AXIS_ARESETN),          // input wire M00_AXIS_ARESETN
  .M00_AXIS_TVALID(M00_AXIS_TVALID),            // output wire M00_AXIS_TVALID
  .M00_AXIS_TREADY(M00_AXIS_TREADY),            // input wire M00_AXIS_TREADY
  .M00_AXIS_TDATA(M00_AXIS_TDATA),              // output wire [1023 : 0] M00_AXIS_TDATA
  .M00_AXIS_TKEEP(M00_AXIS_TKEEP),              // output wire [127 : 0] M00_AXIS_TKEEP
  .M00_AXIS_TLAST(M00_AXIS_TLAST),              // output wire M00_AXIS_TLAST
  .M00_AXIS_TID(M00_AXIS_TID),                  // output wire [2 : 0] M00_AXIS_TID
  .M00_AXIS_TUSER(M00_AXIS_TUSER),              // output wire [127 : 0] M00_AXIS_TUSER
  .S00_ARB_REQ_SUPPRESS(S00_ARB_REQ_SUPPRESS),  // input wire S00_ARB_REQ_SUPPRESS
  .S01_ARB_REQ_SUPPRESS(S01_ARB_REQ_SUPPRESS),  // input wire S01_ARB_REQ_SUPPRESS
  .S02_ARB_REQ_SUPPRESS(S02_ARB_REQ_SUPPRESS),  // input wire S02_ARB_REQ_SUPPRESS
  .S03_ARB_REQ_SUPPRESS(S03_ARB_REQ_SUPPRESS),  // input wire S03_ARB_REQ_SUPPRESS
  .S04_ARB_REQ_SUPPRESS(S04_ARB_REQ_SUPPRESS),  // input wire S04_ARB_REQ_SUPPRESS
  .S00_FIFO_DATA_COUNT(S00_FIFO_DATA_COUNT),    // output wire [31 : 0] S00_FIFO_DATA_COUNT
  .S01_FIFO_DATA_COUNT(S01_FIFO_DATA_COUNT),    // output wire [31 : 0] S01_FIFO_DATA_COUNT
  .S02_FIFO_DATA_COUNT(S02_FIFO_DATA_COUNT),    // output wire [31 : 0] S02_FIFO_DATA_COUNT
  .S03_FIFO_DATA_COUNT(S03_FIFO_DATA_COUNT),    // output wire [31 : 0] S03_FIFO_DATA_COUNT
  .S04_FIFO_DATA_COUNT(S04_FIFO_DATA_COUNT)    // output wire [31 : 0] S04_FIFO_DATA_COUNT
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file axis_interconnect_in.v when simulating
// the core, axis_interconnect_in. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

