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// IP VLNV: xilinx.com:ip:axi_vdma:6.2
// IP Revision: 4

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
system_axi_hdmi_dma_0 your_instance_name (
  .s_axi_lite_aclk(s_axi_lite_aclk),        // input wire s_axi_lite_aclk
  .m_axi_mm2s_aclk(m_axi_mm2s_aclk),        // input wire m_axi_mm2s_aclk
  .m_axis_mm2s_aclk(m_axis_mm2s_aclk),      // input wire m_axis_mm2s_aclk
  .axi_resetn(axi_resetn),                  // input wire axi_resetn
  .s_axi_lite_awvalid(s_axi_lite_awvalid),  // input wire s_axi_lite_awvalid
  .s_axi_lite_awready(s_axi_lite_awready),  // output wire s_axi_lite_awready
  .s_axi_lite_awaddr(s_axi_lite_awaddr),    // input wire [8 : 0] s_axi_lite_awaddr
  .s_axi_lite_wvalid(s_axi_lite_wvalid),    // input wire s_axi_lite_wvalid
  .s_axi_lite_wready(s_axi_lite_wready),    // output wire s_axi_lite_wready
  .s_axi_lite_wdata(s_axi_lite_wdata),      // input wire [31 : 0] s_axi_lite_wdata
  .s_axi_lite_bresp(s_axi_lite_bresp),      // output wire [1 : 0] s_axi_lite_bresp
  .s_axi_lite_bvalid(s_axi_lite_bvalid),    // output wire s_axi_lite_bvalid
  .s_axi_lite_bready(s_axi_lite_bready),    // input wire s_axi_lite_bready
  .s_axi_lite_arvalid(s_axi_lite_arvalid),  // input wire s_axi_lite_arvalid
  .s_axi_lite_arready(s_axi_lite_arready),  // output wire s_axi_lite_arready
  .s_axi_lite_araddr(s_axi_lite_araddr),    // input wire [8 : 0] s_axi_lite_araddr
  .s_axi_lite_rvalid(s_axi_lite_rvalid),    // output wire s_axi_lite_rvalid
  .s_axi_lite_rready(s_axi_lite_rready),    // input wire s_axi_lite_rready
  .s_axi_lite_rdata(s_axi_lite_rdata),      // output wire [31 : 0] s_axi_lite_rdata
  .s_axi_lite_rresp(s_axi_lite_rresp),      // output wire [1 : 0] s_axi_lite_rresp
  .mm2s_fsync(mm2s_fsync),                  // input wire mm2s_fsync
  .mm2s_frame_ptr_in(mm2s_frame_ptr_in),    // input wire [5 : 0] mm2s_frame_ptr_in
  .mm2s_frame_ptr_out(mm2s_frame_ptr_out),  // output wire [5 : 0] mm2s_frame_ptr_out
  .m_axi_mm2s_araddr(m_axi_mm2s_araddr),    // output wire [31 : 0] m_axi_mm2s_araddr
  .m_axi_mm2s_arlen(m_axi_mm2s_arlen),      // output wire [7 : 0] m_axi_mm2s_arlen
  .m_axi_mm2s_arsize(m_axi_mm2s_arsize),    // output wire [2 : 0] m_axi_mm2s_arsize
  .m_axi_mm2s_arburst(m_axi_mm2s_arburst),  // output wire [1 : 0] m_axi_mm2s_arburst
  .m_axi_mm2s_arprot(m_axi_mm2s_arprot),    // output wire [2 : 0] m_axi_mm2s_arprot
  .m_axi_mm2s_arcache(m_axi_mm2s_arcache),  // output wire [3 : 0] m_axi_mm2s_arcache
  .m_axi_mm2s_arvalid(m_axi_mm2s_arvalid),  // output wire m_axi_mm2s_arvalid
  .m_axi_mm2s_arready(m_axi_mm2s_arready),  // input wire m_axi_mm2s_arready
  .m_axi_mm2s_rdata(m_axi_mm2s_rdata),      // input wire [63 : 0] m_axi_mm2s_rdata
  .m_axi_mm2s_rresp(m_axi_mm2s_rresp),      // input wire [1 : 0] m_axi_mm2s_rresp
  .m_axi_mm2s_rlast(m_axi_mm2s_rlast),      // input wire m_axi_mm2s_rlast
  .m_axi_mm2s_rvalid(m_axi_mm2s_rvalid),    // input wire m_axi_mm2s_rvalid
  .m_axi_mm2s_rready(m_axi_mm2s_rready),    // output wire m_axi_mm2s_rready
  .m_axis_mm2s_tdata(m_axis_mm2s_tdata),    // output wire [63 : 0] m_axis_mm2s_tdata
  .m_axis_mm2s_tkeep(m_axis_mm2s_tkeep),    // output wire [7 : 0] m_axis_mm2s_tkeep
  .m_axis_mm2s_tuser(m_axis_mm2s_tuser),    // output wire [0 : 0] m_axis_mm2s_tuser
  .m_axis_mm2s_tvalid(m_axis_mm2s_tvalid),  // output wire m_axis_mm2s_tvalid
  .m_axis_mm2s_tready(m_axis_mm2s_tready),  // input wire m_axis_mm2s_tready
  .m_axis_mm2s_tlast(m_axis_mm2s_tlast),    // output wire m_axis_mm2s_tlast
  .mm2s_introut(mm2s_introut)              // output wire mm2s_introut
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file system_axi_hdmi_dma_0.v when simulating
// the core, system_axi_hdmi_dma_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

