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// IP VLNV: xilinx.com:ip:xadc_wiz:3.3
// IP Revision: 3

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
xadc_wiz_0 your_instance_name (
  .m_axis_tvalid(m_axis_tvalid),              // output wire m_axis_tvalid
  .m_axis_tready(m_axis_tready),              // input wire m_axis_tready
  .m_axis_tdata(m_axis_tdata),                // output wire [15 : 0] m_axis_tdata
  .m_axis_tid(m_axis_tid),                    // output wire [4 : 0] m_axis_tid
  .s_axis_aclk(s_axis_aclk),                  // input wire s_axis_aclk
  .s_axi_aclk(s_axi_aclk),                    // input wire s_axi_aclk
  .s_axi_aresetn(s_axi_aresetn),              // input wire s_axi_aresetn
  .s_axi_awaddr(s_axi_awaddr),                // input wire [10 : 0] s_axi_awaddr
  .s_axi_awvalid(s_axi_awvalid),              // input wire s_axi_awvalid
  .s_axi_awready(s_axi_awready),              // output wire s_axi_awready
  .s_axi_wdata(s_axi_wdata),                  // input wire [31 : 0] s_axi_wdata
  .s_axi_wstrb(s_axi_wstrb),                  // input wire [3 : 0] s_axi_wstrb
  .s_axi_wvalid(s_axi_wvalid),                // input wire s_axi_wvalid
  .s_axi_wready(s_axi_wready),                // output wire s_axi_wready
  .s_axi_bresp(s_axi_bresp),                  // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid(s_axi_bvalid),                // output wire s_axi_bvalid
  .s_axi_bready(s_axi_bready),                // input wire s_axi_bready
  .s_axi_araddr(s_axi_araddr),                // input wire [10 : 0] s_axi_araddr
  .s_axi_arvalid(s_axi_arvalid),              // input wire s_axi_arvalid
  .s_axi_arready(s_axi_arready),              // output wire s_axi_arready
  .s_axi_rdata(s_axi_rdata),                  // output wire [31 : 0] s_axi_rdata
  .s_axi_rresp(s_axi_rresp),                  // output wire [1 : 0] s_axi_rresp
  .s_axi_rvalid(s_axi_rvalid),                // output wire s_axi_rvalid
  .s_axi_rready(s_axi_rready),                // input wire s_axi_rready
  .ip2intc_irpt(ip2intc_irpt),                // output wire ip2intc_irpt
  .vp_in(vp_in),                              // input wire vp_in
  .vn_in(vn_in),                              // input wire vn_in
  .vauxp3(vauxp3),                            // input wire vauxp3
  .vauxn3(vauxn3),                            // input wire vauxn3
  .user_temp_alarm_out(user_temp_alarm_out),  // output wire user_temp_alarm_out
  .vccint_alarm_out(vccint_alarm_out),        // output wire vccint_alarm_out
  .vccaux_alarm_out(vccaux_alarm_out),        // output wire vccaux_alarm_out
  .ot_out(ot_out),                            // output wire ot_out
  .channel_out(channel_out),                  // output wire [4 : 0] channel_out
  .eoc_out(eoc_out),                          // output wire eoc_out
  .alarm_out(alarm_out),                      // output wire alarm_out
  .eos_out(eos_out),                          // output wire eos_out
  .busy_out(busy_out),                        // output wire busy_out
  .temp_out(temp_out)                        // output wire [11 : 0] temp_out
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file xadc_wiz_0.v when simulating
// the core, xadc_wiz_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

