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// IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
// IP Revision: 2

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
daala_zynq_axi_bram_ctrl_0_0 your_instance_name (
  .s_axi_aclk(s_axi_aclk),        // input s_axi_aclk
  .s_axi_aresetn(s_axi_aresetn),  // input s_axi_aresetn
  .s_axi_awid(s_axi_awid),        // input [0 : 0] s_axi_awid
  .s_axi_awaddr(s_axi_awaddr),    // input [12 : 0] s_axi_awaddr
  .s_axi_awlen(s_axi_awlen),      // input [7 : 0] s_axi_awlen
  .s_axi_awsize(s_axi_awsize),    // input [2 : 0] s_axi_awsize
  .s_axi_awburst(s_axi_awburst),  // input [1 : 0] s_axi_awburst
  .s_axi_awlock(s_axi_awlock),    // input s_axi_awlock
  .s_axi_awcache(s_axi_awcache),  // input [3 : 0] s_axi_awcache
  .s_axi_awprot(s_axi_awprot),    // input [2 : 0] s_axi_awprot
  .s_axi_awvalid(s_axi_awvalid),  // input s_axi_awvalid
  .s_axi_awready(s_axi_awready),  // output s_axi_awready
  .s_axi_wdata(s_axi_wdata),      // input [63 : 0] s_axi_wdata
  .s_axi_wstrb(s_axi_wstrb),      // input [7 : 0] s_axi_wstrb
  .s_axi_wlast(s_axi_wlast),      // input s_axi_wlast
  .s_axi_wvalid(s_axi_wvalid),    // input s_axi_wvalid
  .s_axi_wready(s_axi_wready),    // output s_axi_wready
  .s_axi_bid(s_axi_bid),          // output [0 : 0] s_axi_bid
  .s_axi_bresp(s_axi_bresp),      // output [1 : 0] s_axi_bresp
  .s_axi_bvalid(s_axi_bvalid),    // output s_axi_bvalid
  .s_axi_bready(s_axi_bready),    // input s_axi_bready
  .s_axi_arid(s_axi_arid),        // input [0 : 0] s_axi_arid
  .s_axi_araddr(s_axi_araddr),    // input [12 : 0] s_axi_araddr
  .s_axi_arlen(s_axi_arlen),      // input [7 : 0] s_axi_arlen
  .s_axi_arsize(s_axi_arsize),    // input [2 : 0] s_axi_arsize
  .s_axi_arburst(s_axi_arburst),  // input [1 : 0] s_axi_arburst
  .s_axi_arlock(s_axi_arlock),    // input s_axi_arlock
  .s_axi_arcache(s_axi_arcache),  // input [3 : 0] s_axi_arcache
  .s_axi_arprot(s_axi_arprot),    // input [2 : 0] s_axi_arprot
  .s_axi_arvalid(s_axi_arvalid),  // input s_axi_arvalid
  .s_axi_arready(s_axi_arready),  // output s_axi_arready
  .s_axi_rid(s_axi_rid),          // output [0 : 0] s_axi_rid
  .s_axi_rdata(s_axi_rdata),      // output [63 : 0] s_axi_rdata
  .s_axi_rresp(s_axi_rresp),      // output [1 : 0] s_axi_rresp
  .s_axi_rlast(s_axi_rlast),      // output s_axi_rlast
  .s_axi_rvalid(s_axi_rvalid),    // output s_axi_rvalid
  .s_axi_rready(s_axi_rready),    // input s_axi_rready
  .bram_rst_a(bram_rst_a),        // output bram_rst_a
  .bram_clk_a(bram_clk_a),        // output bram_clk_a
  .bram_en_a(bram_en_a),          // output bram_en_a
  .bram_we_a(bram_we_a),          // output [7 : 0] bram_we_a
  .bram_addr_a(bram_addr_a),      // output [12 : 0] bram_addr_a
  .bram_wrdata_a(bram_wrdata_a),  // output [63 : 0] bram_wrdata_a
  .bram_rddata_a(bram_rddata_a),  // input [63 : 0] bram_rddata_a
  .bram_rst_b(bram_rst_b),        // output bram_rst_b
  .bram_clk_b(bram_clk_b),        // output bram_clk_b
  .bram_en_b(bram_en_b),          // output bram_en_b
  .bram_we_b(bram_we_b),          // output [7 : 0] bram_we_b
  .bram_addr_b(bram_addr_b),      // output [12 : 0] bram_addr_b
  .bram_wrdata_b(bram_wrdata_b),  // output [63 : 0] bram_wrdata_b
  .bram_rddata_b(bram_rddata_b)  // input [63 : 0] bram_rddata_b
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file daala_zynq_axi_bram_ctrl_0_0.v when simulating
// the core, daala_zynq_axi_bram_ctrl_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

