///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2018 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor     : Xilinx
// \   \   \/     Version    : 1.0
//  \   \         Application: Xilinx CORE Generator
//  /   /         Filename   : CNT_ICON.veo
// /___/   /\     Timestamp  : Tue Apr 10 14:31:43 中国标准时间 2018
// \   \  /  \
//  \___\/\___\
//
// Design Name: ISE Instantiation template
///////////////////////////////////////////////////////////////////////////////

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

// Instantiate the module
// ---------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
CNT_ICON instance_name (
    .CONTROL0(CONTROL0),
    .CONTROL1(CONTROL1)
);

// INST_TAG_END ------ End INSTANTIATION Template ---------

