-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.2
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ColorMat2AXIvideo is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    color_mat_rows_dout : IN STD_LOGIC_VECTOR (15 downto 0);
    color_mat_rows_empty_n : IN STD_LOGIC;
    color_mat_rows_read : OUT STD_LOGIC;
    color_mat_cols_dout : IN STD_LOGIC_VECTOR (15 downto 0);
    color_mat_cols_empty_n : IN STD_LOGIC;
    color_mat_cols_read : OUT STD_LOGIC;
    color_mat_data_V_V_dout : IN STD_LOGIC_VECTOR (95 downto 0);
    color_mat_data_V_V_empty_n : IN STD_LOGIC;
    color_mat_data_V_V_read : OUT STD_LOGIC;
    m_axis_video_TDATA : OUT STD_LOGIC_VECTOR (95 downto 0);
    m_axis_video_TVALID : OUT STD_LOGIC;
    m_axis_video_TREADY : IN STD_LOGIC;
    m_axis_video_TKEEP : OUT STD_LOGIC_VECTOR (11 downto 0);
    m_axis_video_TSTRB : OUT STD_LOGIC_VECTOR (11 downto 0);
    m_axis_video_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axis_video_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;


architecture behav of ColorMat2AXIvideo is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
    constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv14_0 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000";
    constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
    constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_lv15_7FFF : STD_LOGIC_VECTOR (14 downto 0) := "111111111111111";
    constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
    constant ap_const_lv14_1 : STD_LOGIC_VECTOR (13 downto 0) := "00000000000001";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
    constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
    constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
    constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
    constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
    constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
    constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
    constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
    constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
    constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
    constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
    constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
    constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
    constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
    constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
    constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
    constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
    constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal color_mat_rows_blk_n : STD_LOGIC;
    signal color_mat_cols_blk_n : STD_LOGIC;
    signal color_mat_data_V_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0 : BOOLEAN;
    signal icmp_ln141_reg_444 : STD_LOGIC_VECTOR (0 downto 0);
    signal m_axis_video_TDATA_blk_n : STD_LOGIC;
    signal j_0_i_reg_194 : STD_LOGIC_VECTOR (13 downto 0);
    signal color_mat_rows_read_reg_420 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal tmp_fu_205_p4 : STD_LOGIC_VECTOR (13 downto 0);
    signal tmp_reg_425 : STD_LOGIC_VECTOR (13 downto 0);
    signal add_ln153_fu_219_p2 : STD_LOGIC_VECTOR (14 downto 0);
    signal add_ln153_reg_430 : STD_LOGIC_VECTOR (14 downto 0);
    signal icmp_ln136_fu_230_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal i_fu_235_p2 : STD_LOGIC_VECTOR (15 downto 0);
    signal i_reg_439 : STD_LOGIC_VECTOR (15 downto 0);
    signal icmp_ln141_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
    signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_state4_io : BOOLEAN;
    signal ap_block_pp0_stage0_11001 : BOOLEAN;
    signal j_fu_250_p2 : STD_LOGIC_VECTOR (13 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal tmp_last_V_fu_256_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_last_V_reg_453 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_pp0_stage0_subdone : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
    signal i_0_i_reg_183 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_CS_fsm_state5 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
    signal tmp_user_V_fu_132 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_pp0_stage0_01001 : BOOLEAN;
    signal zext_ln124_fu_215_p1 : STD_LOGIC_VECTOR (14 downto 0);
    signal zext_ln141_fu_241_p1 : STD_LOGIC_VECTOR (14 downto 0);
    signal p_Result_3_2_i_fu_369_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_3_1_i_fu_359_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_3_i_fu_349_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_2_2_i_fu_339_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_2_1_i_fu_329_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_2_i_fu_319_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_1_2_i_fu_309_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_1_1_i_fu_299_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_1_i_fu_289_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_0_2_i_fu_279_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal trunc_ln647_fu_275_p1 : STD_LOGIC_VECTOR (7 downto 0);
    signal p_Result_0_i_fu_265_p4 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;


begin




    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_continue = ap_const_logic_1)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((icmp_ln136_fu_230_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif (((icmp_ln136_fu_230_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then 
                    ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
                elsif ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                elsif (((icmp_ln136_fu_230_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
                    ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    i_0_i_reg_183_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state5)) then 
                i_0_i_reg_183 <= i_reg_439;
            elsif ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
                i_0_i_reg_183 <= ap_const_lv16_0;
            end if; 
        end if;
    end process;

    j_0_i_reg_194_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln141_fu_245_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
                j_0_i_reg_194 <= j_fu_250_p2;
            elsif (((icmp_ln136_fu_230_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
                j_0_i_reg_194 <= ap_const_lv14_0;
            end if; 
        end if;
    end process;

    tmp_user_V_fu_132_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln141_reg_444 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
                tmp_user_V_fu_132 <= ap_const_lv1_0;
            elsif ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
                tmp_user_V_fu_132 <= ap_const_lv1_1;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                add_ln153_reg_430 <= add_ln153_fu_219_p2;
                color_mat_rows_read_reg_420 <= color_mat_rows_dout;
                tmp_reg_425 <= color_mat_cols_dout(15 downto 2);
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
                i_reg_439 <= i_fu_235_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
                icmp_ln141_reg_444 <= icmp_ln141_fu_245_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((icmp_ln141_fu_245_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
                tmp_last_V_reg_453 <= tmp_last_V_fu_256_p2;
            end if;
        end if;
    end process;

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, color_mat_rows_empty_n, color_mat_cols_empty_n, icmp_ln136_fu_230_p2, ap_CS_fsm_state2, icmp_ln141_fu_245_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                if (((icmp_ln136_fu_230_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_pp0_stage0 => 
                if (not(((icmp_ln141_fu_245_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif (((icmp_ln141_fu_245_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone))) then
                    ap_NS_fsm <= ap_ST_fsm_state5;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state5 => 
                ap_NS_fsm <= ap_ST_fsm_state2;
            when others =>  
                ap_NS_fsm <= "XXXX";
        end case;
    end process;
    add_ln153_fu_219_p2 <= std_logic_vector(unsigned(zext_ln124_fu_215_p1) + unsigned(ap_const_lv15_7FFF));
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);
    ap_CS_fsm_state5 <= ap_CS_fsm(3);
        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_01001_assign_proc : process(color_mat_data_V_V_empty_n, ap_enable_reg_pp0_iter1, icmp_ln141_reg_444)
    begin
                ap_block_pp0_stage0_01001 <= ((icmp_ln141_reg_444 = ap_const_lv1_0) and (color_mat_data_V_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
    end process;


    ap_block_pp0_stage0_11001_assign_proc : process(color_mat_data_V_V_empty_n, ap_enable_reg_pp0_iter1, icmp_ln141_reg_444, ap_block_state4_io)
    begin
                ap_block_pp0_stage0_11001 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((icmp_ln141_reg_444 = ap_const_lv1_0) and (color_mat_data_V_V_empty_n = ap_const_logic_0))));
    end process;


    ap_block_pp0_stage0_subdone_assign_proc : process(color_mat_data_V_V_empty_n, ap_enable_reg_pp0_iter1, icmp_ln141_reg_444, ap_block_state4_io)
    begin
                ap_block_pp0_stage0_subdone <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((icmp_ln141_reg_444 = ap_const_lv1_0) and (color_mat_data_V_V_empty_n = ap_const_logic_0))));
    end process;


    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, color_mat_rows_empty_n, color_mat_cols_empty_n)
    begin
                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
    end process;

        ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state4_io_assign_proc : process(m_axis_video_TREADY, icmp_ln141_reg_444)
    begin
                ap_block_state4_io <= ((icmp_ln141_reg_444 = ap_const_lv1_0) and (m_axis_video_TREADY = ap_const_logic_0));
    end process;


    ap_block_state4_pp0_stage0_iter1_assign_proc : process(color_mat_data_V_V_empty_n, icmp_ln141_reg_444)
    begin
                ap_block_state4_pp0_stage0_iter1 <= ((icmp_ln141_reg_444 = ap_const_lv1_0) and (color_mat_data_V_V_empty_n = ap_const_logic_0));
    end process;


    ap_condition_pp0_exit_iter0_state3_assign_proc : process(icmp_ln141_fu_245_p2)
    begin
        if ((icmp_ln141_fu_245_p2 = ap_const_lv1_1)) then 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_done_reg, icmp_ln136_fu_230_p2, ap_CS_fsm_state2)
    begin
        if (((icmp_ln136_fu_230_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(icmp_ln136_fu_230_p2, ap_CS_fsm_state2)
    begin
        if (((icmp_ln136_fu_230_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    color_mat_cols_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, color_mat_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            color_mat_cols_blk_n <= color_mat_cols_empty_n;
        else 
            color_mat_cols_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    color_mat_cols_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, color_mat_rows_empty_n, color_mat_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            color_mat_cols_read <= ap_const_logic_1;
        else 
            color_mat_cols_read <= ap_const_logic_0;
        end if; 
    end process;


    color_mat_data_V_V_blk_n_assign_proc : process(color_mat_data_V_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln141_reg_444)
    begin
        if (((icmp_ln141_reg_444 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            color_mat_data_V_V_blk_n <= color_mat_data_V_V_empty_n;
        else 
            color_mat_data_V_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    color_mat_data_V_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln141_reg_444, ap_block_pp0_stage0_11001)
    begin
        if (((icmp_ln141_reg_444 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
            color_mat_data_V_V_read <= ap_const_logic_1;
        else 
            color_mat_data_V_V_read <= ap_const_logic_0;
        end if; 
    end process;


    color_mat_rows_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, color_mat_rows_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            color_mat_rows_blk_n <= color_mat_rows_empty_n;
        else 
            color_mat_rows_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    color_mat_rows_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, color_mat_rows_empty_n, color_mat_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (color_mat_cols_empty_n = ap_const_logic_0) or (color_mat_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            color_mat_rows_read <= ap_const_logic_1;
        else 
            color_mat_rows_read <= ap_const_logic_0;
        end if; 
    end process;

    i_fu_235_p2 <= std_logic_vector(unsigned(i_0_i_reg_183) + unsigned(ap_const_lv16_1));
    icmp_ln136_fu_230_p2 <= "1" when (i_0_i_reg_183 = color_mat_rows_read_reg_420) else "0";
    icmp_ln141_fu_245_p2 <= "1" when (j_0_i_reg_194 = tmp_reg_425) else "0";
    j_fu_250_p2 <= std_logic_vector(unsigned(j_0_i_reg_194) + unsigned(ap_const_lv14_1));
    m_axis_video_TDATA <= (((((((((((p_Result_3_2_i_fu_369_p4 & p_Result_3_1_i_fu_359_p4) & p_Result_3_i_fu_349_p4) & p_Result_2_2_i_fu_339_p4) & p_Result_2_1_i_fu_329_p4) & p_Result_2_i_fu_319_p4) & p_Result_1_2_i_fu_309_p4) & p_Result_1_1_i_fu_299_p4) & p_Result_1_i_fu_289_p4) & p_Result_0_2_i_fu_279_p4) & trunc_ln647_fu_275_p1) & p_Result_0_i_fu_265_p4);

    m_axis_video_TDATA_blk_n_assign_proc : process(m_axis_video_TREADY, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln141_reg_444)
    begin
        if (((icmp_ln141_reg_444 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then 
            m_axis_video_TDATA_blk_n <= m_axis_video_TREADY;
        else 
            m_axis_video_TDATA_blk_n <= ap_const_logic_1;
        end if; 
    end process;

    m_axis_video_TDEST <= ap_const_lv1_0;
    m_axis_video_TID <= ap_const_lv1_0;
    m_axis_video_TKEEP <= ap_const_lv12_FFF;
    m_axis_video_TLAST <= tmp_last_V_reg_453;
    m_axis_video_TSTRB <= ap_const_lv12_0;
    m_axis_video_TUSER <= tmp_user_V_fu_132;

    m_axis_video_TVALID_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln141_reg_444, ap_block_pp0_stage0_11001)
    begin
        if (((icmp_ln141_reg_444 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
            m_axis_video_TVALID <= ap_const_logic_1;
        else 
            m_axis_video_TVALID <= ap_const_logic_0;
        end if; 
    end process;

    p_Result_0_2_i_fu_279_p4 <= color_mat_data_V_V_dout(23 downto 16);
    p_Result_0_i_fu_265_p4 <= color_mat_data_V_V_dout(15 downto 8);
    p_Result_1_1_i_fu_299_p4 <= color_mat_data_V_V_dout(31 downto 24);
    p_Result_1_2_i_fu_309_p4 <= color_mat_data_V_V_dout(47 downto 40);
    p_Result_1_i_fu_289_p4 <= color_mat_data_V_V_dout(39 downto 32);
    p_Result_2_1_i_fu_329_p4 <= color_mat_data_V_V_dout(55 downto 48);
    p_Result_2_2_i_fu_339_p4 <= color_mat_data_V_V_dout(71 downto 64);
    p_Result_2_i_fu_319_p4 <= color_mat_data_V_V_dout(63 downto 56);
    p_Result_3_1_i_fu_359_p4 <= color_mat_data_V_V_dout(79 downto 72);
    p_Result_3_2_i_fu_369_p4 <= color_mat_data_V_V_dout(95 downto 88);
    p_Result_3_i_fu_349_p4 <= color_mat_data_V_V_dout(87 downto 80);
    tmp_fu_205_p4 <= color_mat_cols_dout(15 downto 2);
    tmp_last_V_fu_256_p2 <= "1" when (zext_ln141_fu_241_p1 = add_ln153_reg_430) else "0";
    trunc_ln647_fu_275_p1 <= color_mat_data_V_V_dout(8 - 1 downto 0);
    zext_ln124_fu_215_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_205_p4),15));
    zext_ln141_fu_241_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_0_i_reg_194),15));
end behav;
