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// IP VLNV: xilinx.com:ip:axi_quad_spi:3.1
// IP Revision: 1

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
zynq_1_axi_quad_spi_0_0 your_instance_name (
  .ext_spi_clk(ext_spi_clk),        // input wire ext_spi_clk
  .s_axi4_aclk(s_axi4_aclk),        // input wire s_axi4_aclk
  .s_axi4_aresetn(s_axi4_aresetn),  // input wire s_axi4_aresetn
  .s_axi4_awid(s_axi4_awid),        // input wire [11 : 0] s_axi4_awid
  .s_axi4_awaddr(s_axi4_awaddr),    // input wire [23 : 0] s_axi4_awaddr
  .s_axi4_awlen(s_axi4_awlen),      // input wire [7 : 0] s_axi4_awlen
  .s_axi4_awsize(s_axi4_awsize),    // input wire [2 : 0] s_axi4_awsize
  .s_axi4_awburst(s_axi4_awburst),  // input wire [1 : 0] s_axi4_awburst
  .s_axi4_awlock(s_axi4_awlock),    // input wire s_axi4_awlock
  .s_axi4_awcache(s_axi4_awcache),  // input wire [3 : 0] s_axi4_awcache
  .s_axi4_awprot(s_axi4_awprot),    // input wire [2 : 0] s_axi4_awprot
  .s_axi4_awvalid(s_axi4_awvalid),  // input wire s_axi4_awvalid
  .s_axi4_awready(s_axi4_awready),  // output wire s_axi4_awready
  .s_axi4_wdata(s_axi4_wdata),      // input wire [31 : 0] s_axi4_wdata
  .s_axi4_wstrb(s_axi4_wstrb),      // input wire [3 : 0] s_axi4_wstrb
  .s_axi4_wlast(s_axi4_wlast),      // input wire s_axi4_wlast
  .s_axi4_wvalid(s_axi4_wvalid),    // input wire s_axi4_wvalid
  .s_axi4_wready(s_axi4_wready),    // output wire s_axi4_wready
  .s_axi4_bid(s_axi4_bid),          // output wire [11 : 0] s_axi4_bid
  .s_axi4_bresp(s_axi4_bresp),      // output wire [1 : 0] s_axi4_bresp
  .s_axi4_bvalid(s_axi4_bvalid),    // output wire s_axi4_bvalid
  .s_axi4_bready(s_axi4_bready),    // input wire s_axi4_bready
  .s_axi4_arid(s_axi4_arid),        // input wire [11 : 0] s_axi4_arid
  .s_axi4_araddr(s_axi4_araddr),    // input wire [23 : 0] s_axi4_araddr
  .s_axi4_arlen(s_axi4_arlen),      // input wire [7 : 0] s_axi4_arlen
  .s_axi4_arsize(s_axi4_arsize),    // input wire [2 : 0] s_axi4_arsize
  .s_axi4_arburst(s_axi4_arburst),  // input wire [1 : 0] s_axi4_arburst
  .s_axi4_arlock(s_axi4_arlock),    // input wire s_axi4_arlock
  .s_axi4_arcache(s_axi4_arcache),  // input wire [3 : 0] s_axi4_arcache
  .s_axi4_arprot(s_axi4_arprot),    // input wire [2 : 0] s_axi4_arprot
  .s_axi4_arvalid(s_axi4_arvalid),  // input wire s_axi4_arvalid
  .s_axi4_arready(s_axi4_arready),  // output wire s_axi4_arready
  .s_axi4_rid(s_axi4_rid),          // output wire [11 : 0] s_axi4_rid
  .s_axi4_rdata(s_axi4_rdata),      // output wire [31 : 0] s_axi4_rdata
  .s_axi4_rresp(s_axi4_rresp),      // output wire [1 : 0] s_axi4_rresp
  .s_axi4_rlast(s_axi4_rlast),      // output wire s_axi4_rlast
  .s_axi4_rvalid(s_axi4_rvalid),    // output wire s_axi4_rvalid
  .s_axi4_rready(s_axi4_rready),    // input wire s_axi4_rready
  .io0_i(io0_i),                    // input wire io0_i
  .io0_o(io0_o),                    // output wire io0_o
  .io0_t(io0_t),                    // output wire io0_t
  .io1_i(io1_i),                    // input wire io1_i
  .io1_o(io1_o),                    // output wire io1_o
  .io1_t(io1_t),                    // output wire io1_t
  .sck_i(sck_i),                    // input wire sck_i
  .sck_o(sck_o),                    // output wire sck_o
  .sck_t(sck_t),                    // output wire sck_t
  .ss_i(ss_i),                      // input wire [0 : 0] ss_i
  .ss_o(ss_o),                      // output wire [0 : 0] ss_o
  .ss_t(ss_t),                      // output wire ss_t
  .ip2intc_irpt(ip2intc_irpt)      // output wire ip2intc_irpt
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file zynq_1_axi_quad_spi_0_0.v when simulating
// the core, zynq_1_axi_quad_spi_0_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

