-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.2
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity update_row_idx is
port (
    ap_ready : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read : IN STD_LOGIC_VECTOR (7 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read : IN STD_LOGIC_VECTOR (7 downto 0);
    ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
    ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
    ap_return_2 : OUT STD_LOGIC_VECTOR (7 downto 0);
    ap_return_3 : OUT STD_LOGIC_VECTOR (7 downto 0);
    ap_return_4 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end;


architecture behav of update_row_idx is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_logic_0 : STD_LOGIC := '0';



begin



    ap_ready <= ap_const_logic_1;
    ap_return_0 <= GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read;
    ap_return_1 <= GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read;
    ap_return_2 <= GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read;
    ap_return_3 <= GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read;
    ap_return_4 <= GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read;
end behav;
