-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.op (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
-- Date        : Tue May 22 11:59:41 2018
-- Host        : ip-10-206-20-46 running 64-bit CentOS release 6.5 (Final)
-- Command     : write_vhdl -force -mode synth_stub
--               /proj/soc_work/cccabra/F1/Chimera/design/rtl/v4_venom_cl_github/v4_venom_cl_github.srcs/sources_1/bd/cl_axi_interconnect/cl_axi_interconnect_stub.vhdl
-- Design      : cl_axi_interconnect
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xcvu9p-flgb2104-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cl_axi_interconnect is
  Port ( 
    ACLK : in STD_LOGIC;
    ARESETN : in STD_LOGIC;
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arready : in STD_LOGIC;
    M00_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC;
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awready : in STD_LOGIC;
    M00_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC;
    M00_AXI_bid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M00_AXI_bready : out STD_LOGIC;
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC;
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    M00_AXI_rid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M00_AXI_rlast : in STD_LOGIC;
    M00_AXI_rready : out STD_LOGIC;
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rvalid : in STD_LOGIC;
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    M00_AXI_wlast : out STD_LOGIC;
    M00_AXI_wready : in STD_LOGIC;
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M00_AXI_wvalid : out STD_LOGIC;
    M01_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M01_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M01_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M01_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arready : in STD_LOGIC;
    M01_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_arvalid : out STD_LOGIC;
    M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M01_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M01_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M01_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awready : in STD_LOGIC;
    M01_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_awvalid : out STD_LOGIC;
    M01_AXI_bid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M01_AXI_bready : out STD_LOGIC;
    M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_bvalid : in STD_LOGIC;
    M01_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    M01_AXI_rid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M01_AXI_rlast : in STD_LOGIC;
    M01_AXI_rready : out STD_LOGIC;
    M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_rvalid : in STD_LOGIC;
    M01_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    M01_AXI_wlast : out STD_LOGIC;
    M01_AXI_wready : in STD_LOGIC;
    M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M01_AXI_wvalid : out STD_LOGIC;
    M02_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M02_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_arid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M02_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M02_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M02_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_arready : in STD_LOGIC;
    M02_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_arvalid : out STD_LOGIC;
    M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M02_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_awid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M02_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M02_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M02_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_awready : in STD_LOGIC;
    M02_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M02_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M02_AXI_awvalid : out STD_LOGIC;
    M02_AXI_bid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M02_AXI_bready : out STD_LOGIC;
    M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_bvalid : in STD_LOGIC;
    M02_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    M02_AXI_rid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M02_AXI_rlast : in STD_LOGIC;
    M02_AXI_rready : out STD_LOGIC;
    M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M02_AXI_rvalid : in STD_LOGIC;
    M02_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    M02_AXI_wlast : out STD_LOGIC;
    M02_AXI_wready : in STD_LOGIC;
    M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M02_AXI_wvalid : out STD_LOGIC;
    M03_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M03_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_arid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M03_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M03_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M03_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_arready : in STD_LOGIC;
    M03_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_arvalid : out STD_LOGIC;
    M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M03_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_awid : out STD_LOGIC_VECTOR ( 6 downto 0 );
    M03_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M03_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M03_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_awready : in STD_LOGIC;
    M03_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M03_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M03_AXI_awvalid : out STD_LOGIC;
    M03_AXI_bid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M03_AXI_bready : out STD_LOGIC;
    M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_bvalid : in STD_LOGIC;
    M03_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    M03_AXI_rid : in STD_LOGIC_VECTOR ( 6 downto 0 );
    M03_AXI_rlast : in STD_LOGIC;
    M03_AXI_rready : out STD_LOGIC;
    M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M03_AXI_rvalid : in STD_LOGIC;
    M03_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    M03_AXI_wlast : out STD_LOGIC;
    M03_AXI_wready : in STD_LOGIC;
    M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M03_AXI_wvalid : out STD_LOGIC;
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arready : out STD_LOGIC;
    S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC;
    S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awready : out STD_LOGIC;
    S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_awvalid : in STD_LOGIC;
    S00_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_AXI_bready : in STD_LOGIC;
    S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_bvalid : out STD_LOGIC;
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    S00_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S00_AXI_rlast : out STD_LOGIC;
    S00_AXI_rready : in STD_LOGIC;
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rvalid : out STD_LOGIC;
    S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    S00_AXI_wlast : in STD_LOGIC;
    S00_AXI_wready : out STD_LOGIC;
    S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S00_AXI_wvalid : in STD_LOGIC;
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arready : out STD_LOGIC;
    S01_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC;
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awready : out STD_LOGIC;
    S01_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC;
    S01_AXI_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S01_AXI_bready : in STD_LOGIC;
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC;
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    S01_AXI_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
    S01_AXI_rlast : out STD_LOGIC;
    S01_AXI_rready : in STD_LOGIC;
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rvalid : out STD_LOGIC;
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    S01_AXI_wlast : in STD_LOGIC;
    S01_AXI_wready : out STD_LOGIC;
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S01_AXI_wvalid : in STD_LOGIC
  );

end cl_axi_interconnect;

architecture stub of cl_axi_interconnect is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ACLK,ARESETN,M00_AXI_araddr[63:0],M00_AXI_arburst[1:0],M00_AXI_arcache[3:0],M00_AXI_arid[6:0],M00_AXI_arlen[7:0],M00_AXI_arlock[0:0],M00_AXI_arprot[2:0],M00_AXI_arqos[3:0],M00_AXI_arready,M00_AXI_arregion[3:0],M00_AXI_arsize[2:0],M00_AXI_arvalid,M00_AXI_awaddr[63:0],M00_AXI_awburst[1:0],M00_AXI_awcache[3:0],M00_AXI_awid[6:0],M00_AXI_awlen[7:0],M00_AXI_awlock[0:0],M00_AXI_awprot[2:0],M00_AXI_awqos[3:0],M00_AXI_awready,M00_AXI_awregion[3:0],M00_AXI_awsize[2:0],M00_AXI_awvalid,M00_AXI_bid[6:0],M00_AXI_bready,M00_AXI_bresp[1:0],M00_AXI_bvalid,M00_AXI_rdata[511:0],M00_AXI_rid[6:0],M00_AXI_rlast,M00_AXI_rready,M00_AXI_rresp[1:0],M00_AXI_rvalid,M00_AXI_wdata[511:0],M00_AXI_wlast,M00_AXI_wready,M00_AXI_wstrb[63:0],M00_AXI_wvalid,M01_AXI_araddr[63:0],M01_AXI_arburst[1:0],M01_AXI_arcache[3:0],M01_AXI_arid[6:0],M01_AXI_arlen[7:0],M01_AXI_arlock[0:0],M01_AXI_arprot[2:0],M01_AXI_arqos[3:0],M01_AXI_arready,M01_AXI_arregion[3:0],M01_AXI_arsize[2:0],M01_AXI_arvalid,M01_AXI_awaddr[63:0],M01_AXI_awburst[1:0],M01_AXI_awcache[3:0],M01_AXI_awid[6:0],M01_AXI_awlen[7:0],M01_AXI_awlock[0:0],M01_AXI_awprot[2:0],M01_AXI_awqos[3:0],M01_AXI_awready,M01_AXI_awregion[3:0],M01_AXI_awsize[2:0],M01_AXI_awvalid,M01_AXI_bid[6:0],M01_AXI_bready,M01_AXI_bresp[1:0],M01_AXI_bvalid,M01_AXI_rdata[511:0],M01_AXI_rid[6:0],M01_AXI_rlast,M01_AXI_rready,M01_AXI_rresp[1:0],M01_AXI_rvalid,M01_AXI_wdata[511:0],M01_AXI_wlast,M01_AXI_wready,M01_AXI_wstrb[63:0],M01_AXI_wvalid,M02_AXI_araddr[63:0],M02_AXI_arburst[1:0],M02_AXI_arcache[3:0],M02_AXI_arid[6:0],M02_AXI_arlen[7:0],M02_AXI_arlock[0:0],M02_AXI_arprot[2:0],M02_AXI_arqos[3:0],M02_AXI_arready,M02_AXI_arregion[3:0],M02_AXI_arsize[2:0],M02_AXI_arvalid,M02_AXI_awaddr[63:0],M02_AXI_awburst[1:0],M02_AXI_awcache[3:0],M02_AXI_awid[6:0],M02_AXI_awlen[7:0],M02_AXI_awlock[0:0],M02_AXI_awprot[2:0],M02_AXI_awqos[3:0],M02_AXI_awready,M02_AXI_awregion[3:0],M02_AXI_awsize[2:0],M02_AXI_awvalid,M02_AXI_bid[6:0],M02_AXI_bready,M02_AXI_bresp[1:0],M02_AXI_bvalid,M02_AXI_rdata[511:0],M02_AXI_rid[6:0],M02_AXI_rlast,M02_AXI_rready,M02_AXI_rresp[1:0],M02_AXI_rvalid,M02_AXI_wdata[511:0],M02_AXI_wlast,M02_AXI_wready,M02_AXI_wstrb[63:0],M02_AXI_wvalid,M03_AXI_araddr[63:0],M03_AXI_arburst[1:0],M03_AXI_arcache[3:0],M03_AXI_arid[6:0],M03_AXI_arlen[7:0],M03_AXI_arlock[0:0],M03_AXI_arprot[2:0],M03_AXI_arqos[3:0],M03_AXI_arready,M03_AXI_arregion[3:0],M03_AXI_arsize[2:0],M03_AXI_arvalid,M03_AXI_awaddr[63:0],M03_AXI_awburst[1:0],M03_AXI_awcache[3:0],M03_AXI_awid[6:0],M03_AXI_awlen[7:0],M03_AXI_awlock[0:0],M03_AXI_awprot[2:0],M03_AXI_awqos[3:0],M03_AXI_awready,M03_AXI_awregion[3:0],M03_AXI_awsize[2:0],M03_AXI_awvalid,M03_AXI_bid[6:0],M03_AXI_bready,M03_AXI_bresp[1:0],M03_AXI_bvalid,M03_AXI_rdata[511:0],M03_AXI_rid[6:0],M03_AXI_rlast,M03_AXI_rready,M03_AXI_rresp[1:0],M03_AXI_rvalid,M03_AXI_wdata[511:0],M03_AXI_wlast,M03_AXI_wready,M03_AXI_wstrb[63:0],M03_AXI_wvalid,S00_AXI_araddr[63:0],S00_AXI_arburst[1:0],S00_AXI_arcache[3:0],S00_AXI_arid[5:0],S00_AXI_arlen[7:0],S00_AXI_arlock[0:0],S00_AXI_arprot[2:0],S00_AXI_arqos[3:0],S00_AXI_arready,S00_AXI_arregion[3:0],S00_AXI_arsize[2:0],S00_AXI_arvalid,S00_AXI_awaddr[63:0],S00_AXI_awburst[1:0],S00_AXI_awcache[3:0],S00_AXI_awid[5:0],S00_AXI_awlen[7:0],S00_AXI_awlock[0:0],S00_AXI_awprot[2:0],S00_AXI_awqos[3:0],S00_AXI_awready,S00_AXI_awregion[3:0],S00_AXI_awsize[2:0],S00_AXI_awvalid,S00_AXI_bid[5:0],S00_AXI_bready,S00_AXI_bresp[1:0],S00_AXI_bvalid,S00_AXI_rdata[511:0],S00_AXI_rid[5:0],S00_AXI_rlast,S00_AXI_rready,S00_AXI_rresp[1:0],S00_AXI_rvalid,S00_AXI_wdata[511:0],S00_AXI_wlast,S00_AXI_wready,S00_AXI_wstrb[63:0],S00_AXI_wvalid,S01_AXI_araddr[63:0],S01_AXI_arburst[1:0],S01_AXI_arcache[3:0],S01_AXI_arid[5:0],S01_AXI_arlen[7:0],S01_AXI_arlock[0:0],S01_AXI_arprot[2:0],S01_AXI_arqos[3:0],S01_AXI_arready,S01_AXI_arregion[3:0],S01_AXI_arsize[2:0],S01_AXI_arvalid,S01_AXI_awaddr[63:0],S01_AXI_awburst[1:0],S01_AXI_awcache[3:0],S01_AXI_awid[5:0],S01_AXI_awlen[7:0],S01_AXI_awlock[0:0],S01_AXI_awprot[2:0],S01_AXI_awqos[3:0],S01_AXI_awready,S01_AXI_awregion[3:0],S01_AXI_awsize[2:0],S01_AXI_awvalid,S01_AXI_bid[5:0],S01_AXI_bready,S01_AXI_bresp[1:0],S01_AXI_bvalid,S01_AXI_rdata[511:0],S01_AXI_rid[5:0],S01_AXI_rlast,S01_AXI_rready,S01_AXI_rresp[1:0],S01_AXI_rvalid,S01_AXI_wdata[511:0],S01_AXI_wlast,S01_AXI_wready,S01_AXI_wstrb[63:0],S01_AXI_wvalid";
begin
end;
