-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.2
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity process_image is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1 : OUT STD_LOGIC;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
    p_src_rows_read : IN STD_LOGIC_VECTOR (15 downto 0);
    p_src_cols_read : IN STD_LOGIC_VECTOR (15 downto 0);
    p_src_data_V_V_dout : IN STD_LOGIC_VECTOR (39 downto 0);
    p_src_data_V_V_empty_n : IN STD_LOGIC;
    p_src_data_V_V_read : OUT STD_LOGIC;
    p_dst_data_V_V_din : OUT STD_LOGIC_VECTOR (39 downto 0);
    p_dst_data_V_V_full_n : IN STD_LOGIC;
    p_dst_data_V_V_write : OUT STD_LOGIC );
end;


architecture behav of process_image is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
    constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
    constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (10 downto 0) := "00000001000";
    constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (10 downto 0) := "00000010000";
    constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (10 downto 0) := "00000100000";
    constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (10 downto 0) := "00001000000";
    constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (10 downto 0) := "00010000000";
    constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (10 downto 0) := "00100000000";
    constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (10 downto 0) := "01000000000";
    constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (10 downto 0) := "10000000000";
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_boolean_0 : BOOLEAN := false;
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
    constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
    constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
    constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000";
    constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
    constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
    constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
    constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
    constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
    constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
    constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
    constant ap_const_lv16_2 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000010";
    constant ap_const_lv40_0 : STD_LOGIC_VECTOR (39 downto 0) := "0000000000000000000000000000000000000000";
    constant ap_const_lv17_3 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000011";
    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
    constant ap_const_lv15_1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
    constant ap_const_lv17_2 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000010";
    constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";

    signal ap_CS_fsm : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal p_src_data_V_V_blk_n : STD_LOGIC;
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_block_pp0_stage0 : BOOLEAN;
    signal icmp_ln303_reg_546 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
    signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
    signal ap_block_pp1_stage0 : BOOLEAN;
    signal icmp_ln303_1_reg_555 : STD_LOGIC_VECTOR (0 downto 0);
    signal c_0_0_reg_188 : STD_LOGIC_VECTOR (14 downto 0);
    signal c_0_1_reg_200 : STD_LOGIC_VECTOR (14 downto 0);
    signal tmp_32_fu_388_p4 : STD_LOGIC_VECTOR (14 downto 0);
    signal tmp_32_reg_532 : STD_LOGIC_VECTOR (14 downto 0);
    signal zext_ln301_fu_406_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal zext_ln301_reg_541 : STD_LOGIC_VECTOR (31 downto 0);
    signal icmp_ln303_fu_410_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
    signal ap_block_state3_pp0_stage0_iter1 : BOOLEAN;
    signal ap_block_pp0_stage0_11001 : BOOLEAN;
    signal add_ln303_fu_415_p2 : STD_LOGIC_VECTOR (14 downto 0);
    signal add_ln303_reg_550 : STD_LOGIC_VECTOR (14 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal icmp_ln303_1_fu_426_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
    signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
    signal ap_block_pp1_stage0_11001 : BOOLEAN;
    signal add_ln303_1_fu_431_p2 : STD_LOGIC_VECTOR (14 downto 0);
    signal add_ln303_1_reg_559 : STD_LOGIC_VECTOR (14 downto 0);
    signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
    signal add_ln314_fu_447_p2 : STD_LOGIC_VECTOR (14 downto 0);
    signal ap_CS_fsm_state8 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
    signal add_ln314_1_fu_463_p2 : STD_LOGIC_VECTOR (14 downto 0);
    signal ap_CS_fsm_state10 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
    signal add_ln325_fu_477_p2 : STD_LOGIC_VECTOR (16 downto 0);
    signal add_ln325_reg_580 : STD_LOGIC_VECTOR (16 downto 0);
    signal ap_CS_fsm_state11 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
    signal GenericBPC_row_idx_v_5_reg_588 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_CS_fsm_state12 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
    signal icmp_ln325_fu_487_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal GenericBPC_row_idx_v_6_reg_593 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_7_reg_598 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_8_reg_603 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_9_reg_608 : STD_LOGIC_VECTOR (7 downto 0);
    signal r_fu_512_p2 : STD_LOGIC_VECTOR (15 downto 0);
    signal r_reg_613 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_CS_fsm_state13 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
    signal grp_process_row_fu_328_ap_ready : STD_LOGIC;
    signal grp_process_row_fu_328_ap_done : STD_LOGIC;
    signal ap_block_pp0_stage0_subdone : BOOLEAN;
    signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
    signal ap_CS_fsm_state4 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
    signal ap_block_pp1_stage0_subdone : BOOLEAN;
    signal ap_condition_pp1_exit_iter0_state5 : STD_LOGIC;
    signal grp_process_row_fu_328_ap_start : STD_LOGIC;
    signal grp_process_row_fu_328_ap_idle : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1 : STD_LOGIC_VECTOR (9 downto 0);
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1 : STD_LOGIC;
    signal grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1 : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_p_src_data_V_V_read : STD_LOGIC;
    signal grp_process_row_fu_328_p_dst_data_V_V_din : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_process_row_fu_328_p_dst_data_V_V_write : STD_LOGIC;
    signal grp_process_row_fu_328_ap_return_0 : STD_LOGIC_VECTOR (31 downto 0);
    signal grp_process_row_fu_328_ap_return_1 : STD_LOGIC_VECTOR (31 downto 0);
    signal call_ret5_update_row_idx_fu_364_ap_ready : STD_LOGIC;
    signal call_ret5_update_row_idx_fu_364_ap_return_0 : STD_LOGIC_VECTOR (7 downto 0);
    signal call_ret5_update_row_idx_fu_364_ap_return_1 : STD_LOGIC_VECTOR (7 downto 0);
    signal call_ret5_update_row_idx_fu_364_ap_return_2 : STD_LOGIC_VECTOR (7 downto 0);
    signal call_ret5_update_row_idx_fu_364_ap_return_3 : STD_LOGIC_VECTOR (7 downto 0);
    signal call_ret5_update_row_idx_fu_364_ap_return_4 : STD_LOGIC_VECTOR (7 downto 0);
    signal ap_phi_mux_c_0_0_phi_fu_192_p4 : STD_LOGIC_VECTOR (14 downto 0);
    signal ap_phi_mux_c_0_1_phi_fu_204_p4 : STD_LOGIC_VECTOR (14 downto 0);
    signal c2_0_0_reg_212 : STD_LOGIC_VECTOR (14 downto 0);
    signal icmp_ln314_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state7 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
    signal c2_0_1_reg_223 : STD_LOGIC_VECTOR (14 downto 0);
    signal icmp_ln314_1_fu_458_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal ap_CS_fsm_state9 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
    signal GenericBPC_row_idx_v_reg_234 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_1_reg_246 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_2_reg_258 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_3_reg_270 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_row_idx_v_4_reg_282 : STD_LOGIC_VECTOR (7 downto 0);
    signal GenericBPC_rd_ptr_reg_294 : STD_LOGIC_VECTOR (31 downto 0);
    signal GenericBPC_wr_ptr_0_reg_304 : STD_LOGIC_VECTOR (31 downto 0);
    signal r3_0_reg_316 : STD_LOGIC_VECTOR (15 downto 0);
    signal grp_process_row_fu_328_ap_start_reg : STD_LOGIC := '0';
    signal zext_ln306_fu_421_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln306_1_fu_437_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln317_fu_453_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln317_1_fu_469_p1 : STD_LOGIC_VECTOR (63 downto 0);
    signal zext_ln113_fu_378_p1 : STD_LOGIC_VECTOR (16 downto 0);
    signal add_ln113_fu_382_p2 : STD_LOGIC_VECTOR (16 downto 0);
    signal and_ln_fu_398_p3 : STD_LOGIC_VECTOR (15 downto 0);
    signal zext_ln325_fu_474_p1 : STD_LOGIC_VECTOR (16 downto 0);
    signal zext_ln325_1_fu_483_p1 : STD_LOGIC_VECTOR (16 downto 0);
    signal ap_NS_fsm : STD_LOGIC_VECTOR (10 downto 0);
    signal ap_idle_pp0 : STD_LOGIC;
    signal ap_enable_pp0 : STD_LOGIC;
    signal ap_idle_pp1 : STD_LOGIC;
    signal ap_enable_pp1 : STD_LOGIC;

    component process_row IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_q0 : IN STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1 : OUT STD_LOGIC_VECTOR (9 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1 : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1 : OUT STD_LOGIC_VECTOR (39 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_num_clks_per_row_read : IN STD_LOGIC_VECTOR (14 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_rd_ptr_read : IN STD_LOGIC_VECTOR (31 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_wr_ptr_read : IN STD_LOGIC_VECTOR (31 downto 0);
        r : IN STD_LOGIC_VECTOR (15 downto 0);
        p_src_rows_read : IN STD_LOGIC_VECTOR (15 downto 0);
        p_src_data_V_V_dout : IN STD_LOGIC_VECTOR (39 downto 0);
        p_src_data_V_V_empty_n : IN STD_LOGIC;
        p_src_data_V_V_read : OUT STD_LOGIC;
        p_dst_data_V_V_din : OUT STD_LOGIC_VECTOR (39 downto 0);
        p_dst_data_V_V_full_n : IN STD_LOGIC;
        p_dst_data_V_V_write : OUT STD_LOGIC;
        ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
        ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
    end component;


    component update_row_idx IS
    port (
        ap_ready : OUT STD_LOGIC;
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read : IN STD_LOGIC_VECTOR (7 downto 0);
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read : IN STD_LOGIC_VECTOR (7 downto 0);
        ap_return_0 : OUT STD_LOGIC_VECTOR (7 downto 0);
        ap_return_1 : OUT STD_LOGIC_VECTOR (7 downto 0);
        ap_return_2 : OUT STD_LOGIC_VECTOR (7 downto 0);
        ap_return_3 : OUT STD_LOGIC_VECTOR (7 downto 0);
        ap_return_4 : OUT STD_LOGIC_VECTOR (7 downto 0) );
    end component;



begin
    grp_process_row_fu_328 : component process_row
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_process_row_fu_328_ap_start,
        ap_done => grp_process_row_fu_328_ap_done,
        ap_idle => grp_process_row_fu_328_ap_idle,
        ap_ready => grp_process_row_fu_328_ap_ready,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read => GenericBPC_row_idx_v_reg_234,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read => GenericBPC_row_idx_v_1_reg_246,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read => GenericBPC_row_idx_v_2_reg_258,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read => GenericBPC_row_idx_v_3_reg_270,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read => GenericBPC_row_idx_v_4_reg_282,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_q0 => GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_q0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_q0 => GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_q0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_q0 => GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_q0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_q0 => GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_q0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_q0 => GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_q0,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1 => grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_num_clks_per_row_read => tmp_32_reg_532,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_rd_ptr_read => GenericBPC_rd_ptr_reg_294,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_wr_ptr_read => GenericBPC_wr_ptr_0_reg_304,
        r => r3_0_reg_316,
        p_src_rows_read => p_src_rows_read,
        p_src_data_V_V_dout => p_src_data_V_V_dout,
        p_src_data_V_V_empty_n => p_src_data_V_V_empty_n,
        p_src_data_V_V_read => grp_process_row_fu_328_p_src_data_V_V_read,
        p_dst_data_V_V_din => grp_process_row_fu_328_p_dst_data_V_V_din,
        p_dst_data_V_V_full_n => p_dst_data_V_V_full_n,
        p_dst_data_V_V_write => grp_process_row_fu_328_p_dst_data_V_V_write,
        ap_return_0 => grp_process_row_fu_328_ap_return_0,
        ap_return_1 => grp_process_row_fu_328_ap_return_1);

    call_ret5_update_row_idx_fu_364 : component update_row_idx
    port map (
        ap_ready => call_ret5_update_row_idx_fu_364_ap_ready,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_0_read => GenericBPC_row_idx_v_reg_234,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_1_read => GenericBPC_row_idx_v_1_reg_246,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_2_read => GenericBPC_row_idx_v_2_reg_258,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_3_read => GenericBPC_row_idx_v_3_reg_270,
        GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_row_idx_val_4_read => GenericBPC_row_idx_v_4_reg_282,
        ap_return_0 => call_ret5_update_row_idx_fu_364_ap_return_0,
        ap_return_1 => call_ret5_update_row_idx_fu_364_ap_return_1,
        ap_return_2 => call_ret5_update_row_idx_fu_364_ap_return_2,
        ap_return_3 => call_ret5_update_row_idx_fu_364_ap_return_3,
        ap_return_4 => call_ret5_update_row_idx_fu_364_ap_return_4);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then 
                    ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state2);
                elsif ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then 
                    ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then 
                    ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state5) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                    ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
            else
                if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state5))) then 
                    ap_enable_reg_pp1_iter1 <= (ap_const_logic_1 xor ap_condition_pp1_exit_iter0_state5);
                elsif ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then 
                    ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
                elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                    ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    grp_process_row_fu_328_ap_start_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                grp_process_row_fu_328_ap_start_reg <= ap_const_logic_0;
            else
                if (((ap_const_logic_1 = ap_CS_fsm_state12) and (icmp_ln325_fu_487_p2 = ap_const_lv1_1))) then 
                    grp_process_row_fu_328_ap_start_reg <= ap_const_logic_1;
                elsif ((grp_process_row_fu_328_ap_ready = ap_const_logic_1)) then 
                    grp_process_row_fu_328_ap_start_reg <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    GenericBPC_rd_ptr_reg_294_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_rd_ptr_reg_294 <= zext_ln301_reg_541;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_rd_ptr_reg_294 <= grp_process_row_fu_328_ap_return_0;
            end if; 
        end if;
    end process;

    GenericBPC_row_idx_v_1_reg_246_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_row_idx_v_1_reg_246 <= ap_const_lv8_1;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_row_idx_v_1_reg_246 <= GenericBPC_row_idx_v_6_reg_593;
            end if; 
        end if;
    end process;

    GenericBPC_row_idx_v_2_reg_258_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_row_idx_v_2_reg_258 <= ap_const_lv8_2;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_row_idx_v_2_reg_258 <= GenericBPC_row_idx_v_7_reg_598;
            end if; 
        end if;
    end process;

    GenericBPC_row_idx_v_3_reg_270_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_row_idx_v_3_reg_270 <= ap_const_lv8_3;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_row_idx_v_3_reg_270 <= GenericBPC_row_idx_v_8_reg_603;
            end if; 
        end if;
    end process;

    GenericBPC_row_idx_v_4_reg_282_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_row_idx_v_4_reg_282 <= ap_const_lv8_4;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_row_idx_v_4_reg_282 <= GenericBPC_row_idx_v_9_reg_608;
            end if; 
        end if;
    end process;

    GenericBPC_row_idx_v_reg_234_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_row_idx_v_reg_234 <= ap_const_lv8_0;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_row_idx_v_reg_234 <= GenericBPC_row_idx_v_5_reg_588;
            end if; 
        end if;
    end process;

    GenericBPC_wr_ptr_0_reg_304_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                GenericBPC_wr_ptr_0_reg_304 <= ap_const_lv32_0;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                GenericBPC_wr_ptr_0_reg_304 <= grp_process_row_fu_328_ap_return_1;
            end if; 
        end if;
    end process;

    c2_0_0_reg_212_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state7)) then 
                c2_0_0_reg_212 <= ap_const_lv15_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (icmp_ln314_fu_442_p2 = ap_const_lv1_0))) then 
                c2_0_0_reg_212 <= add_ln314_fu_447_p2;
            end if; 
        end if;
    end process;

    c2_0_1_reg_223_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state9)) then 
                c2_0_1_reg_223 <= ap_const_lv15_0;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state10) and (icmp_ln314_1_fu_458_p2 = ap_const_lv1_0))) then 
                c2_0_1_reg_223 <= add_ln314_1_fu_463_p2;
            end if; 
        end if;
    end process;

    c_0_0_reg_188_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln303_reg_546 = ap_const_lv1_0))) then 
                c_0_0_reg_188 <= add_ln303_reg_550;
            elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then 
                c_0_0_reg_188 <= ap_const_lv15_0;
            end if; 
        end if;
    end process;

    c_0_1_reg_200_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state4)) then 
                c_0_1_reg_200 <= ap_const_lv15_0;
            elsif (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln303_1_reg_555 = ap_const_lv1_0))) then 
                c_0_1_reg_200 <= add_ln303_1_reg_559;
            end if; 
        end if;
    end process;

    r3_0_reg_316_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then 
                r3_0_reg_316 <= ap_const_lv16_2;
            elsif (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then 
                r3_0_reg_316 <= r_reg_613;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state12) and (icmp_ln325_fu_487_p2 = ap_const_lv1_1))) then
                GenericBPC_row_idx_v_5_reg_588 <= call_ret5_update_row_idx_fu_364_ap_return_0;
                GenericBPC_row_idx_v_6_reg_593 <= call_ret5_update_row_idx_fu_364_ap_return_1;
                GenericBPC_row_idx_v_7_reg_598 <= call_ret5_update_row_idx_fu_364_ap_return_2;
                GenericBPC_row_idx_v_8_reg_603 <= call_ret5_update_row_idx_fu_364_ap_return_3;
                GenericBPC_row_idx_v_9_reg_608 <= call_ret5_update_row_idx_fu_364_ap_return_4;
                r_reg_613 <= r_fu_512_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
                add_ln303_1_reg_559 <= add_ln303_1_fu_431_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
                add_ln303_reg_550 <= add_ln303_fu_415_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
                add_ln325_reg_580 <= add_ln325_fu_477_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then
                icmp_ln303_1_reg_555 <= icmp_ln303_1_fu_426_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
                icmp_ln303_reg_546 <= icmp_ln303_fu_410_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
                tmp_32_reg_532 <= add_ln113_fu_382_p2(16 downto 2);
                    zext_ln301_reg_541(15 downto 1) <= zext_ln301_fu_406_p1(15 downto 1);
            end if;
        end if;
    end process;
    zext_ln301_reg_541(0) <= '0';
    zext_ln301_reg_541(31 downto 16) <= "0000000000000000";

    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, icmp_ln303_fu_410_p2, ap_enable_reg_pp0_iter0, icmp_ln303_1_fu_426_p2, ap_enable_reg_pp1_iter0, ap_CS_fsm_state8, ap_CS_fsm_state10, ap_CS_fsm_state12, icmp_ln325_fu_487_p2, ap_CS_fsm_state13, grp_process_row_fu_328_ap_done, ap_block_pp0_stage0_subdone, ap_block_pp1_stage0_subdone, icmp_ln314_fu_442_p2, icmp_ln314_1_fu_458_p2)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_pp0_stage0 => 
                if (not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (icmp_ln303_fu_410_p2 = ap_const_lv1_1)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (icmp_ln303_fu_410_p2 = ap_const_lv1_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state4;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state4 => 
                ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
            when ap_ST_fsm_pp1_stage0 => 
                if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (icmp_ln303_1_fu_426_p2 = ap_const_lv1_1)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (icmp_ln303_1_fu_426_p2 = ap_const_lv1_1))) then
                    ap_NS_fsm <= ap_ST_fsm_state7;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
                end if;
            when ap_ST_fsm_state7 => 
                ap_NS_fsm <= ap_ST_fsm_state8;
            when ap_ST_fsm_state8 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state8) and (icmp_ln314_fu_442_p2 = ap_const_lv1_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state8;
                else
                    ap_NS_fsm <= ap_ST_fsm_state9;
                end if;
            when ap_ST_fsm_state9 => 
                ap_NS_fsm <= ap_ST_fsm_state10;
            when ap_ST_fsm_state10 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state10) and (icmp_ln314_1_fu_458_p2 = ap_const_lv1_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state10;
                else
                    ap_NS_fsm <= ap_ST_fsm_state11;
                end if;
            when ap_ST_fsm_state11 => 
                ap_NS_fsm <= ap_ST_fsm_state12;
            when ap_ST_fsm_state12 => 
                if (((ap_const_logic_1 = ap_CS_fsm_state12) and (icmp_ln325_fu_487_p2 = ap_const_lv1_0))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_state13;
                end if;
            when ap_ST_fsm_state13 => 
                if (((grp_process_row_fu_328_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state13))) then
                    ap_NS_fsm <= ap_ST_fsm_state12;
                else
                    ap_NS_fsm <= ap_ST_fsm_state13;
                end if;
            when others =>  
                ap_NS_fsm <= "XXXXXXXXXXX";
        end case;
    end process;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address0;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1_assign_proc : process(ap_CS_fsm_state8, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1, zext_ln317_fu_453_p1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 <= zext_ln317_fu_453_p1(10 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_address1 <= "XXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0_assign_proc : process(ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1_assign_proc : process(ap_CS_fsm_state8, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1_assign_proc : process(ap_CS_fsm_state8, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state8)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 <= ap_const_lv40_0;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1_assign_proc : process(ap_CS_fsm_state8, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1, icmp_ln314_fu_442_p2)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state8) and (icmp_ln314_fu_442_p2 = ap_const_lv1_0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_0_V_we1 <= ap_const_logic_0;
        end if; 
    end process;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address0;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1_assign_proc : process(ap_CS_fsm_state10, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1, zext_ln317_1_fu_469_p1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 <= zext_ln317_1_fu_469_p1(10 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_address1 <= "XXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0_assign_proc : process(ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1_assign_proc : process(ap_CS_fsm_state10, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1_assign_proc : process(ap_CS_fsm_state10, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state10)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 <= ap_const_lv40_0;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1_assign_proc : process(ap_CS_fsm_state10, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1, icmp_ln314_1_fu_458_p2)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state10) and (icmp_ln314_1_fu_458_p2 = ap_const_lv1_0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_1_V_we1 <= ap_const_logic_0;
        end if; 
    end process;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address0;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1, zext_ln306_fu_421_p1)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 <= zext_ln306_fu_421_p1(10 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_address1 <= "XXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0_assign_proc : process(ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1_assign_proc : process(p_src_data_V_V_dout, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 <= p_src_data_V_V_dout;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln303_reg_546, ap_block_pp0_stage0_11001, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln303_reg_546 = ap_const_lv1_0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_2_V_we1 <= ap_const_logic_0;
        end if; 
    end process;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address0;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1, zext_ln306_1_fu_437_p1)
    begin
        if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 <= zext_ln306_1_fu_437_p1(10 - 1 downto 0);
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_address1 <= "XXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0_assign_proc : process(ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce0 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_11001, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1)
    begin
        if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_ce1 <= ap_const_logic_0;
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1_assign_proc : process(p_src_data_V_V_dout, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1)
    begin
        if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 <= p_src_data_V_V_dout;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
        end if; 
    end process;


    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, icmp_ln303_1_reg_555, ap_block_pp1_stage0_11001, ap_CS_fsm_state13, grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1)
    begin
        if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln303_1_reg_555 = ap_const_lv1_0))) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1;
        else 
            GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_3_V_we1 <= ap_const_logic_0;
        end if; 
    end process;

    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address0;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_address1;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce0;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_ce1;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_d1;
    GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1 <= grp_process_row_fu_328_GenericBPC_xf_cv_BPC_13_4_13_2160_3840_5_5_4_0_0_buff_val_4_V_we1;
    add_ln113_fu_382_p2 <= std_logic_vector(unsigned(zext_ln113_fu_378_p1) + unsigned(ap_const_lv17_3));
    add_ln303_1_fu_431_p2 <= std_logic_vector(unsigned(ap_phi_mux_c_0_1_phi_fu_204_p4) + unsigned(ap_const_lv15_1));
    add_ln303_fu_415_p2 <= std_logic_vector(unsigned(ap_phi_mux_c_0_0_phi_fu_192_p4) + unsigned(ap_const_lv15_1));
    add_ln314_1_fu_463_p2 <= std_logic_vector(unsigned(c2_0_1_reg_223) + unsigned(ap_const_lv15_1));
    add_ln314_fu_447_p2 <= std_logic_vector(unsigned(c2_0_0_reg_212) + unsigned(ap_const_lv15_1));
    add_ln325_fu_477_p2 <= std_logic_vector(unsigned(zext_ln325_fu_474_p1) + unsigned(ap_const_lv17_2));
    and_ln_fu_398_p3 <= (tmp_32_fu_388_p4 & ap_const_lv1_0);
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
    ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(3);
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state10 <= ap_CS_fsm(7);
    ap_CS_fsm_state11 <= ap_CS_fsm(8);
    ap_CS_fsm_state12 <= ap_CS_fsm(9);
    ap_CS_fsm_state13 <= ap_CS_fsm(10);
    ap_CS_fsm_state4 <= ap_CS_fsm(2);
    ap_CS_fsm_state7 <= ap_CS_fsm(4);
    ap_CS_fsm_state8 <= ap_CS_fsm(5);
    ap_CS_fsm_state9 <= ap_CS_fsm(6);
        ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_V_V_empty_n, ap_enable_reg_pp0_iter1, icmp_ln303_reg_546)
    begin
                ap_block_pp0_stage0_11001 <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (icmp_ln303_reg_546 = ap_const_lv1_0));
    end process;


    ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_V_V_empty_n, ap_enable_reg_pp0_iter1, icmp_ln303_reg_546)
    begin
                ap_block_pp0_stage0_subdone <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (icmp_ln303_reg_546 = ap_const_lv1_0));
    end process;

        ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_pp1_stage0_11001_assign_proc : process(p_src_data_V_V_empty_n, ap_enable_reg_pp1_iter1, icmp_ln303_1_reg_555)
    begin
                ap_block_pp1_stage0_11001 <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (icmp_ln303_1_reg_555 = ap_const_lv1_0));
    end process;


    ap_block_pp1_stage0_subdone_assign_proc : process(p_src_data_V_V_empty_n, ap_enable_reg_pp1_iter1, icmp_ln303_1_reg_555)
    begin
                ap_block_pp1_stage0_subdone <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (icmp_ln303_1_reg_555 = ap_const_lv1_0));
    end process;

        ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state3_pp0_stage0_iter1_assign_proc : process(p_src_data_V_V_empty_n, icmp_ln303_reg_546)
    begin
                ap_block_state3_pp0_stage0_iter1 <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (icmp_ln303_reg_546 = ap_const_lv1_0));
    end process;

        ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));

    ap_block_state6_pp1_stage0_iter1_assign_proc : process(p_src_data_V_V_empty_n, icmp_ln303_1_reg_555)
    begin
                ap_block_state6_pp1_stage0_iter1 <= ((p_src_data_V_V_empty_n = ap_const_logic_0) and (icmp_ln303_1_reg_555 = ap_const_lv1_0));
    end process;


    ap_condition_pp0_exit_iter0_state2_assign_proc : process(icmp_ln303_fu_410_p2)
    begin
        if ((icmp_ln303_fu_410_p2 = ap_const_lv1_1)) then 
            ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
        else 
            ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
        end if; 
    end process;


    ap_condition_pp1_exit_iter0_state5_assign_proc : process(icmp_ln303_1_fu_426_p2)
    begin
        if ((icmp_ln303_1_fu_426_p2 = ap_const_lv1_1)) then 
            ap_condition_pp1_exit_iter0_state5 <= ap_const_logic_1;
        else 
            ap_condition_pp1_exit_iter0_state5 <= ap_const_logic_0;
        end if; 
    end process;


    ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state12, icmp_ln325_fu_487_p2)
    begin
        if ((((ap_const_logic_1 = ap_CS_fsm_state12) and (icmp_ln325_fu_487_p2 = ap_const_lv1_0)) or ((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_const_logic_0;
        end if; 
    end process;

    ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
    ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);

    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then 
            ap_idle_pp0 <= ap_const_logic_1;
        else 
            ap_idle_pp0 <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
    begin
        if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then 
            ap_idle_pp1 <= ap_const_logic_1;
        else 
            ap_idle_pp1 <= ap_const_logic_0;
        end if; 
    end process;


    ap_phi_mux_c_0_0_phi_fu_192_p4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln303_reg_546, c_0_0_reg_188, add_ln303_reg_550)
    begin
        if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (icmp_ln303_reg_546 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then 
            ap_phi_mux_c_0_0_phi_fu_192_p4 <= add_ln303_reg_550;
        else 
            ap_phi_mux_c_0_0_phi_fu_192_p4 <= c_0_0_reg_188;
        end if; 
    end process;


    ap_phi_mux_c_0_1_phi_fu_204_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln303_1_reg_555, c_0_1_reg_200, add_ln303_1_reg_559)
    begin
        if (((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln303_1_reg_555 = ap_const_lv1_0))) then 
            ap_phi_mux_c_0_1_phi_fu_204_p4 <= add_ln303_1_reg_559;
        else 
            ap_phi_mux_c_0_1_phi_fu_204_p4 <= c_0_1_reg_200;
        end if; 
    end process;


    ap_ready_assign_proc : process(ap_CS_fsm_state12, icmp_ln325_fu_487_p2)
    begin
        if (((ap_const_logic_1 = ap_CS_fsm_state12) and (icmp_ln325_fu_487_p2 = ap_const_lv1_0))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    grp_process_row_fu_328_ap_start <= grp_process_row_fu_328_ap_start_reg;
    icmp_ln303_1_fu_426_p2 <= "1" when (ap_phi_mux_c_0_1_phi_fu_204_p4 = tmp_32_reg_532) else "0";
    icmp_ln303_fu_410_p2 <= "1" when (ap_phi_mux_c_0_0_phi_fu_192_p4 = tmp_32_reg_532) else "0";
    icmp_ln314_1_fu_458_p2 <= "1" when (c2_0_1_reg_223 = tmp_32_reg_532) else "0";
    icmp_ln314_fu_442_p2 <= "1" when (c2_0_0_reg_212 = tmp_32_reg_532) else "0";
    icmp_ln325_fu_487_p2 <= "1" when (unsigned(zext_ln325_1_fu_483_p1) < unsigned(add_ln325_reg_580)) else "0";
    p_dst_data_V_V_din <= grp_process_row_fu_328_p_dst_data_V_V_din;

    p_dst_data_V_V_write_assign_proc : process(ap_CS_fsm_state13, grp_process_row_fu_328_p_dst_data_V_V_write)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            p_dst_data_V_V_write <= grp_process_row_fu_328_p_dst_data_V_V_write;
        else 
            p_dst_data_V_V_write <= ap_const_logic_0;
        end if; 
    end process;


    p_src_data_V_V_blk_n_assign_proc : process(p_src_data_V_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, icmp_ln303_reg_546, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, icmp_ln303_1_reg_555)
    begin
        if ((((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (icmp_ln303_reg_546 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (icmp_ln303_1_reg_555 = ap_const_lv1_0)))) then 
            p_src_data_V_V_blk_n <= p_src_data_V_V_empty_n;
        else 
            p_src_data_V_V_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    p_src_data_V_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, icmp_ln303_reg_546, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, icmp_ln303_1_reg_555, ap_block_pp0_stage0_11001, ap_block_pp1_stage0_11001, ap_CS_fsm_state13, grp_process_row_fu_328_p_src_data_V_V_read)
    begin
        if ((((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (icmp_ln303_reg_546 = ap_const_lv1_0)) or ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (icmp_ln303_1_reg_555 = ap_const_lv1_0)))) then 
            p_src_data_V_V_read <= ap_const_logic_1;
        elsif ((ap_const_logic_1 = ap_CS_fsm_state13)) then 
            p_src_data_V_V_read <= grp_process_row_fu_328_p_src_data_V_V_read;
        else 
            p_src_data_V_V_read <= ap_const_logic_0;
        end if; 
    end process;

    r_fu_512_p2 <= std_logic_vector(unsigned(r3_0_reg_316) + unsigned(ap_const_lv16_1));
    tmp_32_fu_388_p4 <= add_ln113_fu_382_p2(16 downto 2);
    zext_ln113_fu_378_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_src_cols_read),17));
    zext_ln301_fu_406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(and_ln_fu_398_p3),32));
    zext_ln306_1_fu_437_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c_0_1_reg_200),64));
    zext_ln306_fu_421_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c_0_0_reg_188),64));
    zext_ln317_1_fu_469_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c2_0_1_reg_223),64));
    zext_ln317_fu_453_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c2_0_0_reg_212),64));
    zext_ln325_1_fu_483_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r3_0_reg_316),17));
    zext_ln325_fu_474_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_src_rows_read),17));
end behav;
