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// IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7
// IP Revision: 8

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
coldata_rx your_instance_name (
  .gtwiz_userclk_tx_reset_in(gtwiz_userclk_tx_reset_in),                    // input wire [0 : 0] gtwiz_userclk_tx_reset_in
  .gtwiz_userclk_tx_srcclk_out(gtwiz_userclk_tx_srcclk_out),                // output wire [0 : 0] gtwiz_userclk_tx_srcclk_out
  .gtwiz_userclk_tx_usrclk_out(gtwiz_userclk_tx_usrclk_out),                // output wire [0 : 0] gtwiz_userclk_tx_usrclk_out
  .gtwiz_userclk_tx_usrclk2_out(gtwiz_userclk_tx_usrclk2_out),              // output wire [0 : 0] gtwiz_userclk_tx_usrclk2_out
  .gtwiz_userclk_tx_active_out(gtwiz_userclk_tx_active_out),                // output wire [0 : 0] gtwiz_userclk_tx_active_out
  .gtwiz_userclk_rx_reset_in(gtwiz_userclk_rx_reset_in),                    // input wire [0 : 0] gtwiz_userclk_rx_reset_in
  .gtwiz_userclk_rx_srcclk_out(gtwiz_userclk_rx_srcclk_out),                // output wire [0 : 0] gtwiz_userclk_rx_srcclk_out
  .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out),                // output wire [0 : 0] gtwiz_userclk_rx_usrclk_out
  .gtwiz_userclk_rx_usrclk2_out(gtwiz_userclk_rx_usrclk2_out),              // output wire [0 : 0] gtwiz_userclk_rx_usrclk2_out
  .gtwiz_userclk_rx_active_out(gtwiz_userclk_rx_active_out),                // output wire [0 : 0] gtwiz_userclk_rx_active_out
  .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in),                  // input wire [0 : 0] gtwiz_reset_clk_freerun_in
  .gtwiz_reset_all_in(gtwiz_reset_all_in),                                  // input wire [0 : 0] gtwiz_reset_all_in
  .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in),  // input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in
  .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in),                  // input wire [0 : 0] gtwiz_reset_tx_datapath_in
  .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in),  // input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in
  .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in),                  // input wire [0 : 0] gtwiz_reset_rx_datapath_in
  .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out),            // output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out
  .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out),                        // output wire [0 : 0] gtwiz_reset_tx_done_out
  .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out),                        // output wire [0 : 0] gtwiz_reset_rx_done_out
  .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in),                              // input wire [255 : 0] gtwiz_userdata_tx_in
  .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out),                            // output wire [255 : 0] gtwiz_userdata_rx_out
  .gtrefclk00_in(gtrefclk00_in),                                            // input wire [3 : 0] gtrefclk00_in
  .qpll0outclk_out(qpll0outclk_out),                                        // output wire [3 : 0] qpll0outclk_out
  .qpll0outrefclk_out(qpll0outrefclk_out),                                  // output wire [3 : 0] qpll0outrefclk_out
  .gthrxn_in(gthrxn_in),                                                    // input wire [15 : 0] gthrxn_in
  .gthrxp_in(gthrxp_in),                                                    // input wire [15 : 0] gthrxp_in
  .rx8b10ben_in(rx8b10ben_in),                                              // input wire [15 : 0] rx8b10ben_in
  .rxcommadeten_in(rxcommadeten_in),                                        // input wire [15 : 0] rxcommadeten_in
  .rxmcommaalignen_in(rxmcommaalignen_in),                                  // input wire [15 : 0] rxmcommaalignen_in
  .rxpcommaalignen_in(rxpcommaalignen_in),                                  // input wire [15 : 0] rxpcommaalignen_in
  .rxpolarity_in(rxpolarity_in),                                            // input wire [15 : 0] rxpolarity_in
  .rxprbssel_in(rxprbssel_in),                                              // input wire [63 : 0] rxprbssel_in
  .tx8b10ben_in(tx8b10ben_in),                                              // input wire [15 : 0] tx8b10ben_in
  .txctrl0_in(txctrl0_in),                                                  // input wire [255 : 0] txctrl0_in
  .txctrl1_in(txctrl1_in),                                                  // input wire [255 : 0] txctrl1_in
  .txctrl2_in(txctrl2_in),                                                  // input wire [127 : 0] txctrl2_in
  .txpd_in(txpd_in),                                                        // input wire [31 : 0] txpd_in
  .gthtxn_out(gthtxn_out),                                                  // output wire [15 : 0] gthtxn_out
  .gthtxp_out(gthtxp_out),                                                  // output wire [15 : 0] gthtxp_out
  .gtpowergood_out(gtpowergood_out),                                        // output wire [15 : 0] gtpowergood_out
  .rxbyteisaligned_out(rxbyteisaligned_out),                                // output wire [15 : 0] rxbyteisaligned_out
  .rxbyterealign_out(rxbyterealign_out),                                    // output wire [15 : 0] rxbyterealign_out
  .rxcommadet_out(rxcommadet_out),                                          // output wire [15 : 0] rxcommadet_out
  .rxctrl0_out(rxctrl0_out),                                                // output wire [255 : 0] rxctrl0_out
  .rxctrl1_out(rxctrl1_out),                                                // output wire [255 : 0] rxctrl1_out
  .rxctrl2_out(rxctrl2_out),                                                // output wire [127 : 0] rxctrl2_out
  .rxctrl3_out(rxctrl3_out),                                                // output wire [127 : 0] rxctrl3_out
  .rxpmaresetdone_out(rxpmaresetdone_out),                                  // output wire [15 : 0] rxpmaresetdone_out
  .rxprbserr_out(rxprbserr_out),                                            // output wire [15 : 0] rxprbserr_out
  .txpmaresetdone_out(txpmaresetdone_out)                                  // output wire [15 : 0] txpmaresetdone_out
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file coldata_rx.v when simulating
// the core, coldata_rx. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

