-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.3
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity process_frame is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    nofSample : IN STD_LOGIC_VECTOR (31 downto 0);
    incr_V : IN STD_LOGIC_VECTOR (31 downto 0);
    m_axi_cos_out_V_AWVALID : OUT STD_LOGIC;
    m_axi_cos_out_V_AWREADY : IN STD_LOGIC;
    m_axi_cos_out_V_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_cos_out_V_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_cos_out_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_cos_out_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_cos_out_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_WVALID : OUT STD_LOGIC;
    m_axi_cos_out_V_WREADY : IN STD_LOGIC;
    m_axi_cos_out_V_WDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
    m_axi_cos_out_V_WSTRB : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_WLAST : OUT STD_LOGIC;
    m_axi_cos_out_V_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_ARVALID : OUT STD_LOGIC;
    m_axi_cos_out_V_ARREADY : IN STD_LOGIC;
    m_axi_cos_out_V_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_cos_out_V_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_cos_out_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_cos_out_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_cos_out_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_cos_out_V_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_RVALID : IN STD_LOGIC;
    m_axi_cos_out_V_RREADY : OUT STD_LOGIC;
    m_axi_cos_out_V_RDATA : IN STD_LOGIC_VECTOR (15 downto 0);
    m_axi_cos_out_V_RLAST : IN STD_LOGIC;
    m_axi_cos_out_V_RID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_BVALID : IN STD_LOGIC;
    m_axi_cos_out_V_BREADY : OUT STD_LOGIC;
    m_axi_cos_out_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_cos_out_V_BID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_cos_out_V_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_AWVALID : OUT STD_LOGIC;
    m_axi_sin_out_V_AWREADY : IN STD_LOGIC;
    m_axi_sin_out_V_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_sin_out_V_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_sin_out_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_sin_out_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_sin_out_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_WVALID : OUT STD_LOGIC;
    m_axi_sin_out_V_WREADY : IN STD_LOGIC;
    m_axi_sin_out_V_WDATA : OUT STD_LOGIC_VECTOR (15 downto 0);
    m_axi_sin_out_V_WSTRB : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_WLAST : OUT STD_LOGIC;
    m_axi_sin_out_V_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_ARVALID : OUT STD_LOGIC;
    m_axi_sin_out_V_ARREADY : IN STD_LOGIC;
    m_axi_sin_out_V_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_sin_out_V_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
    m_axi_sin_out_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_sin_out_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
    m_axi_sin_out_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
    m_axi_sin_out_V_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_RVALID : IN STD_LOGIC;
    m_axi_sin_out_V_RREADY : OUT STD_LOGIC;
    m_axi_sin_out_V_RDATA : IN STD_LOGIC_VECTOR (15 downto 0);
    m_axi_sin_out_V_RLAST : IN STD_LOGIC;
    m_axi_sin_out_V_RID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_BVALID : IN STD_LOGIC;
    m_axi_sin_out_V_BREADY : OUT STD_LOGIC;
    m_axi_sin_out_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
    m_axi_sin_out_V_BID : IN STD_LOGIC_VECTOR (0 downto 0);
    m_axi_sin_out_V_BUSER : IN STD_LOGIC_VECTOR (0 downto 0) );
end;


architecture behav of process_frame is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
    constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (2 downto 0) := "010";
    constant ap_ST_fsm_state27 : STD_LOGIC_VECTOR (2 downto 0) := "100";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
    constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
    constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
    constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_boolean_1 : BOOLEAN := true;

    signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0);
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal cos_out_V_blk_n_AW : STD_LOGIC;
    signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
    signal cos_out_V_blk_n_W : STD_LOGIC;
    signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
    signal cos_out_V_blk_n_B : STD_LOGIC;
    signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
    signal sin_out_V_blk_n_AW : STD_LOGIC;
    signal sin_out_V_blk_n_W : STD_LOGIC;
    signal sin_out_V_blk_n_B : STD_LOGIC;
    signal i_cast6_reg_98 : STD_LOGIC_VECTOR (30 downto 0);
    signal tmp4_fu_120_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal i_cast6_cast_fu_126_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_pp0_stage0 : STD_LOGIC_VECTOR (0 downto 0);
    attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
    signal ap_sig_ioackin_m_axi_cos_out_V_AWREADY : STD_LOGIC;
    signal ap_sig_ioackin_m_axi_sin_out_V_AWREADY : STD_LOGIC;
    signal ap_sig_ioackin_m_axi_cos_out_V_WREADY : STD_LOGIC;
    signal ap_sig_ioackin_m_axi_sin_out_V_WREADY : STD_LOGIC;
    signal ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
    signal i_fu_130_p2 : STD_LOGIC_VECTOR (30 downto 0);
    signal i_reg_185 : STD_LOGIC_VECTOR (30 downto 0);
    signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
    signal tmp_fu_140_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal tmp_reg_190 : STD_LOGIC_VECTOR (0 downto 0);
    signal dds_cos_V_reg_194 : STD_LOGIC_VECTOR (15 downto 0);
    signal dds_sin_V_reg_199 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
    signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
    signal grp_process_r_fu_109_ap_start : STD_LOGIC;
    signal grp_process_r_fu_109_ap_done : STD_LOGIC;
    signal grp_process_r_fu_109_ap_idle : STD_LOGIC;
    signal grp_process_r_fu_109_ap_ready : STD_LOGIC;
    signal grp_process_r_fu_109_ap_ce : STD_LOGIC;
    signal grp_process_r_fu_109_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
    signal grp_process_r_fu_109_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
    signal i_cast6_phi_fu_102_p4 : STD_LOGIC_VECTOR (30 downto 0);
    signal ap_reg_grp_process_r_fu_109_ap_start : STD_LOGIC := '0';
    signal ap_reg_ioackin_m_axi_cos_out_V_AWREADY : STD_LOGIC := '0';
    signal ap_reg_ioackin_m_axi_cos_out_V_WREADY : STD_LOGIC := '0';
    signal ap_reg_ioackin_m_axi_sin_out_V_AWREADY : STD_LOGIC := '0';
    signal ap_reg_ioackin_m_axi_sin_out_V_WREADY : STD_LOGIC := '0';
    signal i_cast_fu_136_p1 : STD_LOGIC_VECTOR (31 downto 0);
    signal ap_CS_fsm_state27 : STD_LOGIC_VECTOR (0 downto 0);
    attribute fsm_encoding of ap_CS_fsm_state27 : signal is "none";
    signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
    signal ap_condition_425 : BOOLEAN;
    signal ap_condition_182 : BOOLEAN;
    signal ap_condition_431 : BOOLEAN;
    signal ap_condition_434 : BOOLEAN;
    signal ap_condition_437 : BOOLEAN;

    component process_r IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        ap_ce : IN STD_LOGIC;
        incr_V : IN STD_LOGIC_VECTOR (31 downto 0);
        ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
        ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
    end component;



begin
    grp_process_r_fu_109 : component process_r
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_process_r_fu_109_ap_start,
        ap_done => grp_process_r_fu_109_ap_done,
        ap_idle => grp_process_r_fu_109_ap_idle,
        ap_ready => grp_process_r_fu_109_ap_ready,
        ap_ce => grp_process_r_fu_109_ap_ce,
        incr_V => incr_V,
        ap_return_0 => grp_process_r_fu_109_ap_return_0,
        ap_return_1 => grp_process_r_fu_109_ap_return_1);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
            else
                if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and (ap_const_lv1_0 = tmp_fu_140_p2))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
                elsif (((ap_CS_fsm_state1 = ap_const_lv1_1) and not((ap_start = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp4_fu_120_p2)))) then 
                    ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
            else
                if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))))) then 
                    ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
                elsif (((ap_CS_fsm_state1 = ap_const_lv1_1) and not((ap_start = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp4_fu_120_p2)))) then 
                    ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
                elsif (((ap_CS_fsm_state1 = ap_const_lv1_1) and not((ap_start = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp4_fu_120_p2)))) then 
                    ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
                end if; 
            end if;
        end if;
    end process;


    ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
            else
                if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then 
                    ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_grp_process_r_fu_109_ap_start_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_grp_process_r_fu_109_ap_start <= ap_const_logic_0;
            else
                if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then 
                    ap_reg_grp_process_r_fu_109_ap_start <= ap_const_logic_1;
                elsif ((ap_const_logic_1 = grp_process_r_fu_109_ap_ready)) then 
                    ap_reg_grp_process_r_fu_109_ap_start <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_ioackin_m_axi_cos_out_V_AWREADY_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_enable_reg_pp0_iter18)) then
                    if ((ap_condition_182 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= ap_const_logic_0;
                    elsif ((ap_condition_425 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_cos_out_V_AWREADY <= ap_const_logic_1;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_ioackin_m_axi_cos_out_V_WREADY_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_ioackin_m_axi_cos_out_V_WREADY <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_enable_reg_pp0_iter19)) then
                    if ((ap_condition_182 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_cos_out_V_WREADY <= ap_const_logic_0;
                    elsif ((ap_condition_431 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_cos_out_V_WREADY <= ap_const_logic_1;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_ioackin_m_axi_sin_out_V_AWREADY_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_enable_reg_pp0_iter18)) then
                    if ((ap_condition_182 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= ap_const_logic_0;
                    elsif ((ap_condition_434 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_sin_out_V_AWREADY <= ap_const_logic_1;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    ap_reg_ioackin_m_axi_sin_out_V_WREADY_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_reg_ioackin_m_axi_sin_out_V_WREADY <= ap_const_logic_0;
            else
                if ((ap_const_logic_1 = ap_enable_reg_pp0_iter19)) then
                    if ((ap_condition_182 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_sin_out_V_WREADY <= ap_const_logic_0;
                    elsif ((ap_condition_437 = ap_const_boolean_1)) then 
                        ap_reg_ioackin_m_axi_sin_out_V_WREADY <= ap_const_logic_1;
                    end if;
                end if; 
            end if;
        end if;
    end process;


    i_cast6_reg_98_assign_proc : process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_CS_fsm_state1 = ap_const_lv1_1) and not((ap_start = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp4_fu_120_p2)))) then 
                i_cast6_reg_98 <= ap_const_lv31_0;
            elsif (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and not((ap_const_lv1_0 = tmp_reg_190)))) then 
                i_cast6_reg_98 <= i_reg_185;
            end if; 
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))))) then
                    ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179(30 downto 0);
                    ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179(30 downto 0) <= ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179(30 downto 0);
                dds_cos_V_reg_194 <= grp_process_r_fu_109_ap_return_0;
                dds_sin_V_reg_199 <= grp_process_r_fu_109_ap_return_1;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))))) then
                    ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179(30 downto 0) <= i_cast6_cast_reg_179(30 downto 0);
                    i_cast6_cast_reg_179(30 downto 0) <= i_cast6_cast_fu_126_p1(30 downto 0);
                tmp_reg_190 <= tmp_fu_140_p2;
            end if;
        end if;
    end process;
    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
                i_reg_185 <= i_fu_130_p2;
            end if;
        end if;
    end process;
    i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter1_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter2_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter3_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter4_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter5_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter6_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter7_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter8_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter9_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter10_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter11_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter12_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter13_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter14_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter15_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter16_i_cast6_cast_reg_179(31) <= '0';
    ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179(31) <= '0';

    ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, tmp4_fu_120_p2, ap_sig_ioackin_m_axi_cos_out_V_AWREADY, ap_sig_ioackin_m_axi_sin_out_V_AWREADY, ap_sig_ioackin_m_axi_cos_out_V_WREADY, ap_sig_ioackin_m_axi_sin_out_V_WREADY, ap_enable_reg_pp0_iter23)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if ((not((ap_start = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp4_fu_120_p2)))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif ((not((ap_start = ap_const_logic_0)) and (ap_const_lv1_0 = tmp4_fu_120_p2))) then
                    ap_NS_fsm <= ap_ST_fsm_state27;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_pp0_stage0 => 
                if (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and not((ap_const_logic_1 = ap_enable_reg_pp0_iter23))))) then
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))) and not((ap_const_logic_1 = ap_enable_reg_pp0_iter23)))) then
                    ap_NS_fsm <= ap_ST_fsm_state27;
                else
                    ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
                end if;
            when ap_ST_fsm_state27 => 
                ap_NS_fsm <= ap_ST_fsm_state1;
            when others =>  
                ap_NS_fsm <= "XXX";
        end case;
    end process;
    ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1 downto 1);
    ap_CS_fsm_state1 <= ap_CS_fsm(0 downto 0);
    ap_CS_fsm_state27 <= ap_CS_fsm(2 downto 2);

    ap_condition_182_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_sig_ioackin_m_axi_cos_out_V_AWREADY, ap_sig_ioackin_m_axi_sin_out_V_AWREADY, ap_sig_ioackin_m_axi_cos_out_V_WREADY, ap_sig_ioackin_m_axi_sin_out_V_WREADY)
    begin
                ap_condition_182 <= not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))));
    end process;


    ap_condition_425_assign_proc : process(m_axi_cos_out_V_AWREADY, m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
                ap_condition_425 <= ((ap_const_logic_1 = m_axi_cos_out_V_AWREADY) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))));
    end process;


    ap_condition_431_assign_proc : process(m_axi_cos_out_V_WREADY, m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
                ap_condition_431 <= (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_1 = m_axi_cos_out_V_WREADY));
    end process;


    ap_condition_434_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_AWREADY, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
                ap_condition_434 <= (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_1 = m_axi_sin_out_V_AWREADY));
    end process;


    ap_condition_437_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_WREADY, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
                ap_condition_437 <= (not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_1 = m_axi_sin_out_V_WREADY));
    end process;


    ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, ap_CS_fsm_state27)
    begin
        if ((((ap_const_logic_0 = ap_start) and (ap_CS_fsm_state1 = ap_const_lv1_1)) or ((ap_const_lv1_1 = ap_CS_fsm_state27)))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_const_logic_0;
        end if; 
    end process;


    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_const_logic_0 = ap_start) and (ap_CS_fsm_state1 = ap_const_lv1_1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(ap_CS_fsm_state27)
    begin
        if (((ap_const_lv1_1 = ap_CS_fsm_state27))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;


    ap_sig_ioackin_m_axi_cos_out_V_AWREADY_assign_proc : process(m_axi_cos_out_V_AWREADY, ap_reg_ioackin_m_axi_cos_out_V_AWREADY)
    begin
        if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_cos_out_V_AWREADY)) then 
            ap_sig_ioackin_m_axi_cos_out_V_AWREADY <= m_axi_cos_out_V_AWREADY;
        else 
            ap_sig_ioackin_m_axi_cos_out_V_AWREADY <= ap_const_logic_1;
        end if; 
    end process;


    ap_sig_ioackin_m_axi_cos_out_V_WREADY_assign_proc : process(m_axi_cos_out_V_WREADY, ap_reg_ioackin_m_axi_cos_out_V_WREADY)
    begin
        if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_cos_out_V_WREADY)) then 
            ap_sig_ioackin_m_axi_cos_out_V_WREADY <= m_axi_cos_out_V_WREADY;
        else 
            ap_sig_ioackin_m_axi_cos_out_V_WREADY <= ap_const_logic_1;
        end if; 
    end process;


    ap_sig_ioackin_m_axi_sin_out_V_AWREADY_assign_proc : process(m_axi_sin_out_V_AWREADY, ap_reg_ioackin_m_axi_sin_out_V_AWREADY)
    begin
        if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_sin_out_V_AWREADY)) then 
            ap_sig_ioackin_m_axi_sin_out_V_AWREADY <= m_axi_sin_out_V_AWREADY;
        else 
            ap_sig_ioackin_m_axi_sin_out_V_AWREADY <= ap_const_logic_1;
        end if; 
    end process;


    ap_sig_ioackin_m_axi_sin_out_V_WREADY_assign_proc : process(m_axi_sin_out_V_WREADY, ap_reg_ioackin_m_axi_sin_out_V_WREADY)
    begin
        if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_sin_out_V_WREADY)) then 
            ap_sig_ioackin_m_axi_sin_out_V_WREADY <= m_axi_sin_out_V_WREADY;
        else 
            ap_sig_ioackin_m_axi_sin_out_V_WREADY <= ap_const_logic_1;
        end if; 
    end process;


    cos_out_V_blk_n_AW_assign_proc : process(m_axi_cos_out_V_AWREADY, ap_enable_reg_pp0_iter18)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter18)) then 
            cos_out_V_blk_n_AW <= m_axi_cos_out_V_AWREADY;
        else 
            cos_out_V_blk_n_AW <= ap_const_logic_1;
        end if; 
    end process;


    cos_out_V_blk_n_B_assign_proc : process(m_axi_cos_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter24)) then 
            cos_out_V_blk_n_B <= m_axi_cos_out_V_BVALID;
        else 
            cos_out_V_blk_n_B <= ap_const_logic_1;
        end if; 
    end process;


    cos_out_V_blk_n_W_assign_proc : process(m_axi_cos_out_V_WREADY, ap_enable_reg_pp0_iter19)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter19)) then 
            cos_out_V_blk_n_W <= m_axi_cos_out_V_WREADY;
        else 
            cos_out_V_blk_n_W <= ap_const_logic_1;
        end if; 
    end process;


    grp_process_r_fu_109_ap_ce_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_CS_fsm_pp0_stage0, ap_sig_ioackin_m_axi_cos_out_V_AWREADY, ap_sig_ioackin_m_axi_sin_out_V_AWREADY, ap_sig_ioackin_m_axi_cos_out_V_WREADY, ap_sig_ioackin_m_axi_sin_out_V_WREADY)
    begin
        if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))))) then 
            grp_process_r_fu_109_ap_ce <= ap_const_logic_1;
        else 
            grp_process_r_fu_109_ap_ce <= ap_const_logic_0;
        end if; 
    end process;

    grp_process_r_fu_109_ap_start <= ap_reg_grp_process_r_fu_109_ap_start;
    i_cast6_cast_fu_126_p1 <= std_logic_vector(resize(unsigned(i_cast6_phi_fu_102_p4),32));

    i_cast6_phi_fu_102_p4_assign_proc : process(i_cast6_reg_98, ap_CS_fsm_pp0_stage0, i_reg_185, tmp_reg_190, ap_enable_reg_pp0_iter1)
    begin
        if (((ap_const_lv1_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and not((ap_const_lv1_0 = tmp_reg_190)))) then 
            i_cast6_phi_fu_102_p4 <= i_reg_185;
        else 
            i_cast6_phi_fu_102_p4 <= i_cast6_reg_98;
        end if; 
    end process;

    i_cast_fu_136_p1 <= std_logic_vector(resize(unsigned(i_fu_130_p2),32));
    i_fu_130_p2 <= std_logic_vector(unsigned(i_cast6_phi_fu_102_p4) + unsigned(ap_const_lv31_1));
    m_axi_cos_out_V_ARADDR <= ap_const_lv32_0;
    m_axi_cos_out_V_ARBURST <= ap_const_lv2_0;
    m_axi_cos_out_V_ARCACHE <= ap_const_lv4_0;
    m_axi_cos_out_V_ARID <= ap_const_lv1_0;
    m_axi_cos_out_V_ARLEN <= ap_const_lv32_0;
    m_axi_cos_out_V_ARLOCK <= ap_const_lv2_0;
    m_axi_cos_out_V_ARPROT <= ap_const_lv3_0;
    m_axi_cos_out_V_ARQOS <= ap_const_lv4_0;
    m_axi_cos_out_V_ARREGION <= ap_const_lv4_0;
    m_axi_cos_out_V_ARSIZE <= ap_const_lv3_0;
    m_axi_cos_out_V_ARUSER <= ap_const_lv1_0;
    m_axi_cos_out_V_ARVALID <= ap_const_logic_0;
    m_axi_cos_out_V_AWADDR <= ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;
    m_axi_cos_out_V_AWBURST <= ap_const_lv2_0;
    m_axi_cos_out_V_AWCACHE <= ap_const_lv4_0;
    m_axi_cos_out_V_AWID <= ap_const_lv1_0;
    m_axi_cos_out_V_AWLEN <= ap_const_lv32_1;
    m_axi_cos_out_V_AWLOCK <= ap_const_lv2_0;
    m_axi_cos_out_V_AWPROT <= ap_const_lv3_0;
    m_axi_cos_out_V_AWQOS <= ap_const_lv4_0;
    m_axi_cos_out_V_AWREGION <= ap_const_lv4_0;
    m_axi_cos_out_V_AWSIZE <= ap_const_lv3_0;
    m_axi_cos_out_V_AWUSER <= ap_const_lv1_0;

    m_axi_cos_out_V_AWVALID_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter24, ap_reg_ioackin_m_axi_cos_out_V_AWREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_cos_out_V_AWREADY))) then 
            m_axi_cos_out_V_AWVALID <= ap_const_logic_1;
        else 
            m_axi_cos_out_V_AWVALID <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_cos_out_V_BREADY_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_sig_ioackin_m_axi_cos_out_V_AWREADY, ap_sig_ioackin_m_axi_sin_out_V_AWREADY, ap_sig_ioackin_m_axi_cos_out_V_WREADY, ap_sig_ioackin_m_axi_sin_out_V_WREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))))) then 
            m_axi_cos_out_V_BREADY <= ap_const_logic_1;
        else 
            m_axi_cos_out_V_BREADY <= ap_const_logic_0;
        end if; 
    end process;

    m_axi_cos_out_V_RREADY <= ap_const_logic_0;
    m_axi_cos_out_V_WDATA <= dds_cos_V_reg_194;
    m_axi_cos_out_V_WID <= ap_const_lv1_0;
    m_axi_cos_out_V_WLAST <= ap_const_logic_0;
    m_axi_cos_out_V_WSTRB <= ap_const_lv2_3;
    m_axi_cos_out_V_WUSER <= ap_const_lv1_0;

    m_axi_cos_out_V_WVALID_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_reg_ioackin_m_axi_cos_out_V_WREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_cos_out_V_WREADY))) then 
            m_axi_cos_out_V_WVALID <= ap_const_logic_1;
        else 
            m_axi_cos_out_V_WVALID <= ap_const_logic_0;
        end if; 
    end process;

    m_axi_sin_out_V_ARADDR <= ap_const_lv32_0;
    m_axi_sin_out_V_ARBURST <= ap_const_lv2_0;
    m_axi_sin_out_V_ARCACHE <= ap_const_lv4_0;
    m_axi_sin_out_V_ARID <= ap_const_lv1_0;
    m_axi_sin_out_V_ARLEN <= ap_const_lv32_0;
    m_axi_sin_out_V_ARLOCK <= ap_const_lv2_0;
    m_axi_sin_out_V_ARPROT <= ap_const_lv3_0;
    m_axi_sin_out_V_ARQOS <= ap_const_lv4_0;
    m_axi_sin_out_V_ARREGION <= ap_const_lv4_0;
    m_axi_sin_out_V_ARSIZE <= ap_const_lv3_0;
    m_axi_sin_out_V_ARUSER <= ap_const_lv1_0;
    m_axi_sin_out_V_ARVALID <= ap_const_logic_0;
    m_axi_sin_out_V_AWADDR <= ap_pipeline_reg_pp0_iter17_i_cast6_cast_reg_179;
    m_axi_sin_out_V_AWBURST <= ap_const_lv2_0;
    m_axi_sin_out_V_AWCACHE <= ap_const_lv4_0;
    m_axi_sin_out_V_AWID <= ap_const_lv1_0;
    m_axi_sin_out_V_AWLEN <= ap_const_lv32_1;
    m_axi_sin_out_V_AWLOCK <= ap_const_lv2_0;
    m_axi_sin_out_V_AWPROT <= ap_const_lv3_0;
    m_axi_sin_out_V_AWQOS <= ap_const_lv4_0;
    m_axi_sin_out_V_AWREGION <= ap_const_lv4_0;
    m_axi_sin_out_V_AWSIZE <= ap_const_lv3_0;
    m_axi_sin_out_V_AWUSER <= ap_const_lv1_0;

    m_axi_sin_out_V_AWVALID_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter24, ap_reg_ioackin_m_axi_sin_out_V_AWREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_sin_out_V_AWREADY))) then 
            m_axi_sin_out_V_AWVALID <= ap_const_logic_1;
        else 
            m_axi_sin_out_V_AWVALID <= ap_const_logic_0;
        end if; 
    end process;


    m_axi_sin_out_V_BREADY_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_sig_ioackin_m_axi_cos_out_V_AWREADY, ap_sig_ioackin_m_axi_sin_out_V_AWREADY, ap_sig_ioackin_m_axi_cos_out_V_WREADY, ap_sig_ioackin_m_axi_sin_out_V_WREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and not((((ap_const_logic_1 = ap_enable_reg_pp0_iter18) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_AWREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_AWREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and ((ap_const_logic_0 = ap_sig_ioackin_m_axi_cos_out_V_WREADY) or (ap_const_logic_0 = ap_sig_ioackin_m_axi_sin_out_V_WREADY))) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0))))))) then 
            m_axi_sin_out_V_BREADY <= ap_const_logic_1;
        else 
            m_axi_sin_out_V_BREADY <= ap_const_logic_0;
        end if; 
    end process;

    m_axi_sin_out_V_RREADY <= ap_const_logic_0;
    m_axi_sin_out_V_WDATA <= dds_sin_V_reg_199;
    m_axi_sin_out_V_WID <= ap_const_lv1_0;
    m_axi_sin_out_V_WLAST <= ap_const_logic_0;
    m_axi_sin_out_V_WSTRB <= ap_const_lv2_3;
    m_axi_sin_out_V_WUSER <= ap_const_lv1_0;

    m_axi_sin_out_V_WVALID_assign_proc : process(m_axi_cos_out_V_BVALID, m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter24, ap_reg_ioackin_m_axi_sin_out_V_WREADY)
    begin
        if (((ap_const_logic_1 = ap_enable_reg_pp0_iter19) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter24) and ((m_axi_cos_out_V_BVALID = ap_const_logic_0) or (m_axi_sin_out_V_BVALID = ap_const_logic_0)))) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_sin_out_V_WREADY))) then 
            m_axi_sin_out_V_WVALID <= ap_const_logic_1;
        else 
            m_axi_sin_out_V_WVALID <= ap_const_logic_0;
        end if; 
    end process;


    sin_out_V_blk_n_AW_assign_proc : process(m_axi_sin_out_V_AWREADY, ap_enable_reg_pp0_iter18)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter18)) then 
            sin_out_V_blk_n_AW <= m_axi_sin_out_V_AWREADY;
        else 
            sin_out_V_blk_n_AW <= ap_const_logic_1;
        end if; 
    end process;


    sin_out_V_blk_n_B_assign_proc : process(m_axi_sin_out_V_BVALID, ap_enable_reg_pp0_iter24)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter24)) then 
            sin_out_V_blk_n_B <= m_axi_sin_out_V_BVALID;
        else 
            sin_out_V_blk_n_B <= ap_const_logic_1;
        end if; 
    end process;


    sin_out_V_blk_n_W_assign_proc : process(m_axi_sin_out_V_WREADY, ap_enable_reg_pp0_iter19)
    begin
        if ((ap_const_logic_1 = ap_enable_reg_pp0_iter19)) then 
            sin_out_V_blk_n_W <= m_axi_sin_out_V_WREADY;
        else 
            sin_out_V_blk_n_W <= ap_const_logic_1;
        end if; 
    end process;

    tmp4_fu_120_p2 <= "1" when (signed(nofSample) > signed(ap_const_lv32_0)) else "0";
    tmp_fu_140_p2 <= "1" when (signed(i_cast_fu_136_p1) < signed(nofSample)) else "0";
end behav;
