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// IP VLNV: xilinx.labs:hls:icmp_server:1.67
// IP Revision: 1804061221

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
icmp_server_ip your_instance_name (
  .dataIn_TVALID(dataIn_TVALID),    // input wire dataIn_TVALID
  .dataIn_TREADY(dataIn_TREADY),    // output wire dataIn_TREADY
  .dataIn_TDATA(dataIn_TDATA),      // input wire [63 : 0] dataIn_TDATA
  .dataIn_TKEEP(dataIn_TKEEP),      // input wire [7 : 0] dataIn_TKEEP
  .dataIn_TLAST(dataIn_TLAST),      // input wire [0 : 0] dataIn_TLAST
  .udpIn_TVALID(udpIn_TVALID),      // input wire udpIn_TVALID
  .udpIn_TREADY(udpIn_TREADY),      // output wire udpIn_TREADY
  .udpIn_TDATA(udpIn_TDATA),        // input wire [63 : 0] udpIn_TDATA
  .udpIn_TKEEP(udpIn_TKEEP),        // input wire [7 : 0] udpIn_TKEEP
  .udpIn_TLAST(udpIn_TLAST),        // input wire [0 : 0] udpIn_TLAST
  .ttlIn_TVALID(ttlIn_TVALID),      // input wire ttlIn_TVALID
  .ttlIn_TREADY(ttlIn_TREADY),      // output wire ttlIn_TREADY
  .ttlIn_TDATA(ttlIn_TDATA),        // input wire [63 : 0] ttlIn_TDATA
  .ttlIn_TKEEP(ttlIn_TKEEP),        // input wire [7 : 0] ttlIn_TKEEP
  .ttlIn_TLAST(ttlIn_TLAST),        // input wire [0 : 0] ttlIn_TLAST
  .dataOut_TVALID(dataOut_TVALID),  // output wire dataOut_TVALID
  .dataOut_TREADY(dataOut_TREADY),  // input wire dataOut_TREADY
  .dataOut_TDATA(dataOut_TDATA),    // output wire [63 : 0] dataOut_TDATA
  .dataOut_TKEEP(dataOut_TKEEP),    // output wire [7 : 0] dataOut_TKEEP
  .dataOut_TLAST(dataOut_TLAST),    // output wire [0 : 0] dataOut_TLAST
  .ap_clk(ap_clk),                  // input wire ap_clk
  .ap_rst_n(ap_rst_n)              // input wire ap_rst_n
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

