// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ==============================================================


//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
AxiLiteExampleCore  your_instance_name (
  .ap_clk(ap_clk),       // input  ap_clk
  .ap_rst_n(ap_rst_n),       // input  ap_rst_n
  .s_axi_BUS_A_AWVALID(s_axi_BUS_A_AWVALID),       // input  s_axi_BUS_A_AWVALID
  .s_axi_BUS_A_AWREADY(s_axi_BUS_A_AWREADY),       // output  s_axi_BUS_A_AWREADY
  .s_axi_BUS_A_AWADDR(s_axi_BUS_A_AWADDR),       // input [5:0] s_axi_BUS_A_AWADDR
  .s_axi_BUS_A_WVALID(s_axi_BUS_A_WVALID),       // input  s_axi_BUS_A_WVALID
  .s_axi_BUS_A_WREADY(s_axi_BUS_A_WREADY),       // output  s_axi_BUS_A_WREADY
  .s_axi_BUS_A_WDATA(s_axi_BUS_A_WDATA),       // input [31:0] s_axi_BUS_A_WDATA
  .s_axi_BUS_A_WSTRB(s_axi_BUS_A_WSTRB),       // input [3:0] s_axi_BUS_A_WSTRB
  .s_axi_BUS_A_ARVALID(s_axi_BUS_A_ARVALID),       // input  s_axi_BUS_A_ARVALID
  .s_axi_BUS_A_ARREADY(s_axi_BUS_A_ARREADY),       // output  s_axi_BUS_A_ARREADY
  .s_axi_BUS_A_ARADDR(s_axi_BUS_A_ARADDR),       // input [5:0] s_axi_BUS_A_ARADDR
  .s_axi_BUS_A_RVALID(s_axi_BUS_A_RVALID),       // output  s_axi_BUS_A_RVALID
  .s_axi_BUS_A_RREADY(s_axi_BUS_A_RREADY),       // input  s_axi_BUS_A_RREADY
  .s_axi_BUS_A_RDATA(s_axi_BUS_A_RDATA),       // output [31:0] s_axi_BUS_A_RDATA
  .s_axi_BUS_A_RRESP(s_axi_BUS_A_RRESP),       // output [1:0] s_axi_BUS_A_RRESP
  .s_axi_BUS_A_BVALID(s_axi_BUS_A_BVALID),       // output  s_axi_BUS_A_BVALID
  .s_axi_BUS_A_BREADY(s_axi_BUS_A_BREADY),       // input  s_axi_BUS_A_BREADY
  .s_axi_BUS_A_BRESP(s_axi_BUS_A_BRESP),       // output [1:0] s_axi_BUS_A_BRESP
  .interrupt(interrupt)        // output  interrupt
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

