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// IP VLNV: analog.com:user:util_i2c_mixer:1.0
// IP Revision: 3

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
system_sys_i2c_mixer_0 your_instance_name (
  .upstream_scl_T(upstream_scl_T),      // input wire upstream_scl_T
  .upstream_scl_I(upstream_scl_I),      // input wire upstream_scl_I
  .upstream_scl_O(upstream_scl_O),      // output wire upstream_scl_O
  .upstream_sda_T(upstream_sda_T),      // input wire upstream_sda_T
  .upstream_sda_I(upstream_sda_I),      // input wire upstream_sda_I
  .upstream_sda_O(upstream_sda_O),      // output wire upstream_sda_O
  .downstream_scl_T(downstream_scl_T),  // output wire downstream_scl_T
  .downstream_scl_I(downstream_scl_I),  // input wire [1 : 0] downstream_scl_I
  .downstream_scl_O(downstream_scl_O),  // output wire [1 : 0] downstream_scl_O
  .downstream_sda_T(downstream_sda_T),  // output wire downstream_sda_T
  .downstream_sda_I(downstream_sda_I),  // input wire [1 : 0] downstream_sda_I
  .downstream_sda_O(downstream_sda_O)  // output wire [1 : 0] downstream_sda_O
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

