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// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
zc702_processing_system7_1_0 your_instance_name (
  .ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),      // output wire ENET0_PTP_DELAY_REQ_RX
  .ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),      // output wire ENET0_PTP_DELAY_REQ_TX
  .ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),    // output wire ENET0_PTP_PDELAY_REQ_RX
  .ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),    // output wire ENET0_PTP_PDELAY_REQ_TX
  .ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),  // output wire ENET0_PTP_PDELAY_RESP_RX
  .ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),  // output wire ENET0_PTP_PDELAY_RESP_TX
  .ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),    // output wire ENET0_PTP_SYNC_FRAME_RX
  .ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),    // output wire ENET0_PTP_SYNC_FRAME_TX
  .ENET0_SOF_RX(ENET0_SOF_RX),                          // output wire ENET0_SOF_RX
  .ENET0_SOF_TX(ENET0_SOF_TX),                          // output wire ENET0_SOF_TX
  .USB0_PORT_INDCTL(USB0_PORT_INDCTL),                  // output wire [1 : 0] USB0_PORT_INDCTL
  .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),            // output wire USB0_VBUS_PWRSELECT
  .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),              // input wire USB0_VBUS_PWRFAULT
  .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),                // output wire M_AXI_GP0_ARVALID
  .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),                // output wire M_AXI_GP0_AWVALID
  .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),                  // output wire M_AXI_GP0_BREADY
  .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),                  // output wire M_AXI_GP0_RREADY
  .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),                    // output wire M_AXI_GP0_WLAST
  .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),                  // output wire M_AXI_GP0_WVALID
  .M_AXI_GP0_ARID(M_AXI_GP0_ARID),                      // output wire [11 : 0] M_AXI_GP0_ARID
  .M_AXI_GP0_AWID(M_AXI_GP0_AWID),                      // output wire [11 : 0] M_AXI_GP0_AWID
  .M_AXI_GP0_WID(M_AXI_GP0_WID),                        // output wire [11 : 0] M_AXI_GP0_WID
  .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),                // output wire [1 : 0] M_AXI_GP0_ARBURST
  .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),                  // output wire [1 : 0] M_AXI_GP0_ARLOCK
  .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),                  // output wire [2 : 0] M_AXI_GP0_ARSIZE
  .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),                // output wire [1 : 0] M_AXI_GP0_AWBURST
  .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),                  // output wire [1 : 0] M_AXI_GP0_AWLOCK
  .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),                  // output wire [2 : 0] M_AXI_GP0_AWSIZE
  .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),                  // output wire [2 : 0] M_AXI_GP0_ARPROT
  .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),                  // output wire [2 : 0] M_AXI_GP0_AWPROT
  .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),                  // output wire [31 : 0] M_AXI_GP0_ARADDR
  .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),                  // output wire [31 : 0] M_AXI_GP0_AWADDR
  .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),                    // output wire [31 : 0] M_AXI_GP0_WDATA
  .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),                // output wire [3 : 0] M_AXI_GP0_ARCACHE
  .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),                    // output wire [3 : 0] M_AXI_GP0_ARLEN
  .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),                    // output wire [3 : 0] M_AXI_GP0_ARQOS
  .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),                // output wire [3 : 0] M_AXI_GP0_AWCACHE
  .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),                    // output wire [3 : 0] M_AXI_GP0_AWLEN
  .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),                    // output wire [3 : 0] M_AXI_GP0_AWQOS
  .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),                    // output wire [3 : 0] M_AXI_GP0_WSTRB
  .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),                      // input wire M_AXI_GP0_ACLK
  .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),                // input wire M_AXI_GP0_ARREADY
  .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),                // input wire M_AXI_GP0_AWREADY
  .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),                  // input wire M_AXI_GP0_BVALID
  .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),                    // input wire M_AXI_GP0_RLAST
  .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),                  // input wire M_AXI_GP0_RVALID
  .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),                  // input wire M_AXI_GP0_WREADY
  .M_AXI_GP0_BID(M_AXI_GP0_BID),                        // input wire [11 : 0] M_AXI_GP0_BID
  .M_AXI_GP0_RID(M_AXI_GP0_RID),                        // input wire [11 : 0] M_AXI_GP0_RID
  .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),                    // input wire [1 : 0] M_AXI_GP0_BRESP
  .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),                    // input wire [1 : 0] M_AXI_GP0_RRESP
  .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),                    // input wire [31 : 0] M_AXI_GP0_RDATA
  .S_AXI_ACP_ARREADY(S_AXI_ACP_ARREADY),                // output wire S_AXI_ACP_ARREADY
  .S_AXI_ACP_AWREADY(S_AXI_ACP_AWREADY),                // output wire S_AXI_ACP_AWREADY
  .S_AXI_ACP_BVALID(S_AXI_ACP_BVALID),                  // output wire S_AXI_ACP_BVALID
  .S_AXI_ACP_RLAST(S_AXI_ACP_RLAST),                    // output wire S_AXI_ACP_RLAST
  .S_AXI_ACP_RVALID(S_AXI_ACP_RVALID),                  // output wire S_AXI_ACP_RVALID
  .S_AXI_ACP_WREADY(S_AXI_ACP_WREADY),                  // output wire S_AXI_ACP_WREADY
  .S_AXI_ACP_BRESP(S_AXI_ACP_BRESP),                    // output wire [1 : 0] S_AXI_ACP_BRESP
  .S_AXI_ACP_RRESP(S_AXI_ACP_RRESP),                    // output wire [1 : 0] S_AXI_ACP_RRESP
  .S_AXI_ACP_BID(S_AXI_ACP_BID),                        // output wire [2 : 0] S_AXI_ACP_BID
  .S_AXI_ACP_RID(S_AXI_ACP_RID),                        // output wire [2 : 0] S_AXI_ACP_RID
  .S_AXI_ACP_RDATA(S_AXI_ACP_RDATA),                    // output wire [63 : 0] S_AXI_ACP_RDATA
  .S_AXI_ACP_ACLK(S_AXI_ACP_ACLK),                      // input wire S_AXI_ACP_ACLK
  .S_AXI_ACP_ARVALID(S_AXI_ACP_ARVALID),                // input wire S_AXI_ACP_ARVALID
  .S_AXI_ACP_AWVALID(S_AXI_ACP_AWVALID),                // input wire S_AXI_ACP_AWVALID
  .S_AXI_ACP_BREADY(S_AXI_ACP_BREADY),                  // input wire S_AXI_ACP_BREADY
  .S_AXI_ACP_RREADY(S_AXI_ACP_RREADY),                  // input wire S_AXI_ACP_RREADY
  .S_AXI_ACP_WLAST(S_AXI_ACP_WLAST),                    // input wire S_AXI_ACP_WLAST
  .S_AXI_ACP_WVALID(S_AXI_ACP_WVALID),                  // input wire S_AXI_ACP_WVALID
  .S_AXI_ACP_ARID(S_AXI_ACP_ARID),                      // input wire [2 : 0] S_AXI_ACP_ARID
  .S_AXI_ACP_ARPROT(S_AXI_ACP_ARPROT),                  // input wire [2 : 0] S_AXI_ACP_ARPROT
  .S_AXI_ACP_AWID(S_AXI_ACP_AWID),                      // input wire [2 : 0] S_AXI_ACP_AWID
  .S_AXI_ACP_AWPROT(S_AXI_ACP_AWPROT),                  // input wire [2 : 0] S_AXI_ACP_AWPROT
  .S_AXI_ACP_WID(S_AXI_ACP_WID),                        // input wire [2 : 0] S_AXI_ACP_WID
  .S_AXI_ACP_ARADDR(S_AXI_ACP_ARADDR),                  // input wire [31 : 0] S_AXI_ACP_ARADDR
  .S_AXI_ACP_AWADDR(S_AXI_ACP_AWADDR),                  // input wire [31 : 0] S_AXI_ACP_AWADDR
  .S_AXI_ACP_ARCACHE(S_AXI_ACP_ARCACHE),                // input wire [3 : 0] S_AXI_ACP_ARCACHE
  .S_AXI_ACP_ARLEN(S_AXI_ACP_ARLEN),                    // input wire [3 : 0] S_AXI_ACP_ARLEN
  .S_AXI_ACP_ARQOS(S_AXI_ACP_ARQOS),                    // input wire [3 : 0] S_AXI_ACP_ARQOS
  .S_AXI_ACP_AWCACHE(S_AXI_ACP_AWCACHE),                // input wire [3 : 0] S_AXI_ACP_AWCACHE
  .S_AXI_ACP_AWLEN(S_AXI_ACP_AWLEN),                    // input wire [3 : 0] S_AXI_ACP_AWLEN
  .S_AXI_ACP_AWQOS(S_AXI_ACP_AWQOS),                    // input wire [3 : 0] S_AXI_ACP_AWQOS
  .S_AXI_ACP_ARBURST(S_AXI_ACP_ARBURST),                // input wire [1 : 0] S_AXI_ACP_ARBURST
  .S_AXI_ACP_ARLOCK(S_AXI_ACP_ARLOCK),                  // input wire [1 : 0] S_AXI_ACP_ARLOCK
  .S_AXI_ACP_ARSIZE(S_AXI_ACP_ARSIZE),                  // input wire [2 : 0] S_AXI_ACP_ARSIZE
  .S_AXI_ACP_AWBURST(S_AXI_ACP_AWBURST),                // input wire [1 : 0] S_AXI_ACP_AWBURST
  .S_AXI_ACP_AWLOCK(S_AXI_ACP_AWLOCK),                  // input wire [1 : 0] S_AXI_ACP_AWLOCK
  .S_AXI_ACP_AWSIZE(S_AXI_ACP_AWSIZE),                  // input wire [2 : 0] S_AXI_ACP_AWSIZE
  .S_AXI_ACP_ARUSER(S_AXI_ACP_ARUSER),                  // input wire [4 : 0] S_AXI_ACP_ARUSER
  .S_AXI_ACP_AWUSER(S_AXI_ACP_AWUSER),                  // input wire [4 : 0] S_AXI_ACP_AWUSER
  .S_AXI_ACP_WDATA(S_AXI_ACP_WDATA),                    // input wire [63 : 0] S_AXI_ACP_WDATA
  .S_AXI_ACP_WSTRB(S_AXI_ACP_WSTRB),                    // input wire [7 : 0] S_AXI_ACP_WSTRB
  .IRQ_F2P(IRQ_F2P),                                    // input wire [0 : 0] IRQ_F2P
  .FCLK_CLK0(FCLK_CLK0),                                // output wire FCLK_CLK0
  .FCLK_CLK1(FCLK_CLK1),                                // output wire FCLK_CLK1
  .FCLK_CLK2(FCLK_CLK2),                                // output wire FCLK_CLK2
  .FCLK_CLK3(FCLK_CLK3),                                // output wire FCLK_CLK3
  .FCLK_RESET0_N(FCLK_RESET0_N),                        // output wire FCLK_RESET0_N
  .MIO(MIO),                                            // inout wire [53 : 0] MIO
  .DDR_CAS_n(DDR_CAS_n),                                // inout wire DDR_CAS_n
  .DDR_CKE(DDR_CKE),                                    // inout wire DDR_CKE
  .DDR_Clk_n(DDR_Clk_n),                                // inout wire DDR_Clk_n
  .DDR_Clk(DDR_Clk),                                    // inout wire DDR_Clk
  .DDR_CS_n(DDR_CS_n),                                  // inout wire DDR_CS_n
  .DDR_DRSTB(DDR_DRSTB),                                // inout wire DDR_DRSTB
  .DDR_ODT(DDR_ODT),                                    // inout wire DDR_ODT
  .DDR_RAS_n(DDR_RAS_n),                                // inout wire DDR_RAS_n
  .DDR_WEB(DDR_WEB),                                    // inout wire DDR_WEB
  .DDR_BankAddr(DDR_BankAddr),                          // inout wire [2 : 0] DDR_BankAddr
  .DDR_Addr(DDR_Addr),                                  // inout wire [14 : 0] DDR_Addr
  .DDR_VRN(DDR_VRN),                                    // inout wire DDR_VRN
  .DDR_VRP(DDR_VRP),                                    // inout wire DDR_VRP
  .DDR_DM(DDR_DM),                                      // inout wire [3 : 0] DDR_DM
  .DDR_DQ(DDR_DQ),                                      // inout wire [31 : 0] DDR_DQ
  .DDR_DQS_n(DDR_DQS_n),                                // inout wire [3 : 0] DDR_DQS_n
  .DDR_DQS(DDR_DQS),                                    // inout wire [3 : 0] DDR_DQS
  .PS_SRSTB(PS_SRSTB),                                  // inout wire PS_SRSTB
  .PS_CLK(PS_CLK),                                      // inout wire PS_CLK
  .PS_PORB(PS_PORB)                                    // inout wire PS_PORB
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file zc702_processing_system7_1_0.v when simulating
// the core, zc702_processing_system7_1_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

