-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.2
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
-- 
-- ===========================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity gaincontrol is
port (
    ap_clk : IN STD_LOGIC;
    ap_rst : IN STD_LOGIC;
    ap_start : IN STD_LOGIC;
    ap_done : OUT STD_LOGIC;
    ap_continue : IN STD_LOGIC;
    ap_idle : OUT STD_LOGIC;
    ap_ready : OUT STD_LOGIC;
    src1_rows_dout : IN STD_LOGIC_VECTOR (15 downto 0);
    src1_rows_empty_n : IN STD_LOGIC;
    src1_rows_read : OUT STD_LOGIC;
    src1_cols_dout : IN STD_LOGIC_VECTOR (15 downto 0);
    src1_cols_empty_n : IN STD_LOGIC;
    src1_cols_read : OUT STD_LOGIC;
    src1_data_V_V_dout : IN STD_LOGIC_VECTOR (39 downto 0);
    src1_data_V_V_empty_n : IN STD_LOGIC;
    src1_data_V_V_read : OUT STD_LOGIC;
    dst_data_V_V_din : OUT STD_LOGIC_VECTOR (39 downto 0);
    dst_data_V_V_full_n : IN STD_LOGIC;
    dst_data_V_V_write : OUT STD_LOGIC );
end;


architecture behav of gaincontrol is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_logic_0 : STD_LOGIC := '0';
    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_boolean_1 : BOOLEAN := true;

    signal ap_done_reg : STD_LOGIC := '0';
    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
    attribute fsm_encoding : string;
    attribute fsm_encoding of ap_CS_fsm : signal is "none";
    signal ap_CS_fsm_state1 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
    signal src1_rows_blk_n : STD_LOGIC;
    signal src1_cols_blk_n : STD_LOGIC;
    signal src1_rows_read_reg_64 : STD_LOGIC_VECTOR (15 downto 0);
    signal ap_block_state1 : BOOLEAN;
    signal trunc_ln_reg_69 : STD_LOGIC_VECTOR (13 downto 0);
    signal grp_gaincontrolkernel_fu_42_ap_start : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_ap_done : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_ap_idle : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_ap_ready : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_src1_data_V_V_read : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_dst_data_V_V_din : STD_LOGIC_VECTOR (39 downto 0);
    signal grp_gaincontrolkernel_fu_42_dst_data_V_V_write : STD_LOGIC;
    signal grp_gaincontrolkernel_fu_42_ap_start_reg : STD_LOGIC := '0';
    signal ap_block_state1_ignore_call7 : BOOLEAN;
    signal ap_CS_fsm_state2 : STD_LOGIC;
    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);

    component gaincontrolkernel IS
    port (
        ap_clk : IN STD_LOGIC;
        ap_rst : IN STD_LOGIC;
        ap_start : IN STD_LOGIC;
        ap_done : OUT STD_LOGIC;
        ap_idle : OUT STD_LOGIC;
        ap_ready : OUT STD_LOGIC;
        src1_data_V_V_dout : IN STD_LOGIC_VECTOR (39 downto 0);
        src1_data_V_V_empty_n : IN STD_LOGIC;
        src1_data_V_V_read : OUT STD_LOGIC;
        dst_data_V_V_din : OUT STD_LOGIC_VECTOR (39 downto 0);
        dst_data_V_V_full_n : IN STD_LOGIC;
        dst_data_V_V_write : OUT STD_LOGIC;
        height : IN STD_LOGIC_VECTOR (15 downto 0);
        width : IN STD_LOGIC_VECTOR (13 downto 0) );
    end component;



begin
    grp_gaincontrolkernel_fu_42 : component gaincontrolkernel
    port map (
        ap_clk => ap_clk,
        ap_rst => ap_rst,
        ap_start => grp_gaincontrolkernel_fu_42_ap_start,
        ap_done => grp_gaincontrolkernel_fu_42_ap_done,
        ap_idle => grp_gaincontrolkernel_fu_42_ap_idle,
        ap_ready => grp_gaincontrolkernel_fu_42_ap_ready,
        src1_data_V_V_dout => src1_data_V_V_dout,
        src1_data_V_V_empty_n => src1_data_V_V_empty_n,
        src1_data_V_V_read => grp_gaincontrolkernel_fu_42_src1_data_V_V_read,
        dst_data_V_V_din => grp_gaincontrolkernel_fu_42_dst_data_V_V_din,
        dst_data_V_V_full_n => dst_data_V_V_full_n,
        dst_data_V_V_write => grp_gaincontrolkernel_fu_42_dst_data_V_V_write,
        height => src1_rows_read_reg_64,
        width => trunc_ln_reg_69);





    ap_CS_fsm_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_CS_fsm <= ap_ST_fsm_state1;
            else
                ap_CS_fsm <= ap_NS_fsm;
            end if;
        end if;
    end process;


    ap_done_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                ap_done_reg <= ap_const_logic_0;
            else
                if ((ap_continue = ap_const_logic_1)) then 
                    ap_done_reg <= ap_const_logic_0;
                elsif (((grp_gaincontrolkernel_fu_42_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
                    ap_done_reg <= ap_const_logic_1;
                end if; 
            end if;
        end if;
    end process;


    grp_gaincontrolkernel_fu_42_ap_start_reg_assign_proc : process(ap_clk)
    begin
        if (ap_clk'event and ap_clk =  '1') then
            if (ap_rst = '1') then
                grp_gaincontrolkernel_fu_42_ap_start_reg <= ap_const_logic_0;
            else
                if ((not(((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
                    grp_gaincontrolkernel_fu_42_ap_start_reg <= ap_const_logic_1;
                elsif ((grp_gaincontrolkernel_fu_42_ap_ready = ap_const_logic_1)) then 
                    grp_gaincontrolkernel_fu_42_ap_start_reg <= ap_const_logic_0;
                end if; 
            end if;
        end if;
    end process;

    process (ap_clk)
    begin
        if (ap_clk'event and ap_clk = '1') then
            if ((not(((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                src1_rows_read_reg_64 <= src1_rows_dout;
                trunc_ln_reg_69 <= src1_cols_dout(15 downto 2);
            end if;
        end if;
    end process;

    ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, src1_rows_empty_n, src1_cols_empty_n, grp_gaincontrolkernel_fu_42_ap_done, ap_CS_fsm_state2)
    begin
        case ap_CS_fsm is
            when ap_ST_fsm_state1 => 
                if ((not(((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
                    ap_NS_fsm <= ap_ST_fsm_state2;
                else
                    ap_NS_fsm <= ap_ST_fsm_state1;
                end if;
            when ap_ST_fsm_state2 => 
                if (((grp_gaincontrolkernel_fu_42_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
                    ap_NS_fsm <= ap_ST_fsm_state1;
                else
                    ap_NS_fsm <= ap_ST_fsm_state2;
                end if;
            when others =>  
                ap_NS_fsm <= "XX";
        end case;
    end process;
    ap_CS_fsm_state1 <= ap_CS_fsm(0);
    ap_CS_fsm_state2 <= ap_CS_fsm(1);

    ap_block_state1_assign_proc : process(ap_start, ap_done_reg, src1_rows_empty_n, src1_cols_empty_n)
    begin
                ap_block_state1 <= ((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
    end process;


    ap_block_state1_ignore_call7_assign_proc : process(ap_start, ap_done_reg, src1_rows_empty_n, src1_cols_empty_n)
    begin
                ap_block_state1_ignore_call7 <= ((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
    end process;


    ap_done_assign_proc : process(ap_done_reg, grp_gaincontrolkernel_fu_42_ap_done, ap_CS_fsm_state2)
    begin
        if (((grp_gaincontrolkernel_fu_42_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
            ap_done <= ap_const_logic_1;
        else 
            ap_done <= ap_done_reg;
        end if; 
    end process;


    ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
    begin
        if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            ap_idle <= ap_const_logic_1;
        else 
            ap_idle <= ap_const_logic_0;
        end if; 
    end process;


    ap_ready_assign_proc : process(grp_gaincontrolkernel_fu_42_ap_done, ap_CS_fsm_state2)
    begin
        if (((grp_gaincontrolkernel_fu_42_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
            ap_ready <= ap_const_logic_1;
        else 
            ap_ready <= ap_const_logic_0;
        end if; 
    end process;

    dst_data_V_V_din <= grp_gaincontrolkernel_fu_42_dst_data_V_V_din;

    dst_data_V_V_write_assign_proc : process(grp_gaincontrolkernel_fu_42_dst_data_V_V_write, ap_CS_fsm_state2)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
            dst_data_V_V_write <= grp_gaincontrolkernel_fu_42_dst_data_V_V_write;
        else 
            dst_data_V_V_write <= ap_const_logic_0;
        end if; 
    end process;

    grp_gaincontrolkernel_fu_42_ap_start <= grp_gaincontrolkernel_fu_42_ap_start_reg;

    src1_cols_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, src1_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            src1_cols_blk_n <= src1_cols_empty_n;
        else 
            src1_cols_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    src1_cols_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, src1_rows_empty_n, src1_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            src1_cols_read <= ap_const_logic_1;
        else 
            src1_cols_read <= ap_const_logic_0;
        end if; 
    end process;


    src1_data_V_V_read_assign_proc : process(grp_gaincontrolkernel_fu_42_src1_data_V_V_read, ap_CS_fsm_state2)
    begin
        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
            src1_data_V_V_read <= grp_gaincontrolkernel_fu_42_src1_data_V_V_read;
        else 
            src1_data_V_V_read <= ap_const_logic_0;
        end if; 
    end process;


    src1_rows_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, src1_rows_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            src1_rows_blk_n <= src1_rows_empty_n;
        else 
            src1_rows_blk_n <= ap_const_logic_1;
        end if; 
    end process;


    src1_rows_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, src1_rows_empty_n, src1_cols_empty_n)
    begin
        if ((not(((ap_start = ap_const_logic_0) or (src1_cols_empty_n = ap_const_logic_0) or (src1_rows_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
            src1_rows_read <= ap_const_logic_1;
        else 
            src1_rows_read <= ap_const_logic_0;
        end if; 
    end process;

end behav;
