import * as assert from 'assert' ; import { ZSimRemote } from '../src/remotes/zsimulator/zsimremote' ; import { Settings } from '../src/settings' ; import { Utility } from '../src/misc/utility' ; import { Z80RegistersClass } from '../src/remotes/z80registers' ; suite ( 'ZSimRemote' , ( ) => { let zsim ; suite ( '48k' , ( ) => { setup ( ( ) => { Utility . setExtensionPath ( '.' ) ; const cfg = { remoteType : 'zsim' , zsim : { zxKeyboard : true , visualMemory : true , ulaScreen : true , cpuLoadInterruptRange : 1 , Z80N : false , vsyncInterrupt : false , memoryModel : "ZX48K" } , history : { reverseDebugInstructionCount : 0 , spotCount : 0 , codeCoverageEnabled : false } } ; Settings . launch = Settings . Init ( cfg ) ; Z80RegistersClass . createRegisters ( ) ; zsim = new ZSimRemote ( ) ; } ) ; test ( 'Check ROM' , ( ) => { zsim . configureMachine ( Settings . launch . zsim ) ; let value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0xAF , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x42 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x3C , value ) ; } ) ; } ) ; suite ( 'memoryPagingControl' , ( ) => { setup ( ( ) => { Utility . setExtensionPath ( '.' ) ; const cfg = { zsim : { zxKeyboard : true , visualMemory : true , ulaScreen : true , cpuLoadInterruptRange : 1 , Z80N : false , vsyncInterrupt : false , memoryModel : "ZX128K" } , history : { reverseDebugInstructionCount : 0 , spotCount : 0 , codeCoverageEnabled : false } } ; Settings . launch = Settings . Init ( cfg ) ; Z80RegistersClass . createRegisters ( ) ; zsim = new ZSimRemote ( ) ; zsim . configureMachine ( Settings . launch . zsim ) ; } ) ; test ( 'Check ROM 0' , ( ) => { zsim . ports . write ( 0x7FFD , 0 ) ; let value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0x01 , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x00 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x01 , value ) ; zsim . ports . write ( 0x7FFD , 0b010000 ) ; zsim . ports . write ( 0x7FFD , 0 ) ; value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0x01 , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x00 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x01 , value ) ; } ) ; test ( 'Check ROM 1' , ( ) => { let value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0xAF , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x42 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x3C , value ) ; zsim . ports . write ( 0x7FFD , 0 ) ; zsim . ports . write ( 0x7FFD , 0b010000 ) ; value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0xAF , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x42 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x3C , value ) ; } ) ; test ( 'bank switching' , ( ) => { const address = 0xC000 ; for ( let bank = 0 ; bank < 8 ; bank ++ ) { zsim . ports . write ( 0x7FFD , bank ) ; zsim . memory . write8 ( address , 10 + bank ) ; } for ( let bank = 0 ; bank < 8 ; bank ++ ) { zsim . ports . write ( 0x7FFD , bank ) ; const value = zsim . memory . read8 ( address ) ; assert . equal ( 10 + bank , value ) ; } const value = zsim . memory . read8 ( address + 0x4000 - 0xC000 ) ; assert . equal ( 10 + 5 , value ) ; } ) ; test ( 'ula switching' , ( ) => { let address = zsim . ulaScreenAddress ; assert . equal ( 5 * 0x4000 , address ) ; zsim . ports . write ( 0x7FFD , 0b01000 ) ; address = zsim . ulaScreenAddress ; assert . equal ( 7 * 0x4000 , address ) ; zsim . ports . write ( 0x7FFD , 0 ) ; address = zsim . ulaScreenAddress ; assert . equal ( 5 * 0x4000 , address ) ; } ) ; test ( 'paging disable' , ( ) => { zsim . ports . write ( 0x7FFD , 0b0100000 ) ; zsim . ports . write ( 0x7FFD , 0b010000 ) ; let value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0x01 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x01 , value ) ; } ) ; } ) ; suite ( 'tbblueMemoryManagementSlots' , ( ) => { setup ( ( ) => { Utility . setExtensionPath ( '.' ) ; const cfg = { remoteType : 'zsim' , zsim : { zxKeyboard : true , visualMemory : true , ulaScreen : true , cpuLoadInterruptRange : 1 , Z80N : false , vsyncInterrupt : false , memoryModel : "ZXNEXT" } , history : { reverseDebugInstructionCount : 0 , spotCount : 0 , codeCoverageEnabled : false } } ; Settings . launch = Settings . Init ( cfg ) ; Z80RegistersClass . createRegisters ( ) ; zsim = new ZSimRemote ( ) ; zsim . configureMachine ( Settings . launch . zsim ) ; } ) ; test ( 'bank switching RAM' , ( ) => { let bank = 0 ; for ( let slot = 0 ; slot < 8 ; slot ++ ) { const address = slot * 0x2000 ; for ( let i = 0 ; i < 8 ; i ++ ) { bank ++ ; zsim . ports . write ( 0x243B , 0x50 + slot ) ; zsim . ports . write ( 0x253B , bank ) ; zsim . memory . write8 ( address , 100 + 10 * slot + bank ) ; } } bank = 0 ; for ( let slot = 0 ; slot < 8 ; slot ++ ) { const address = slot * 0x2000 ; for ( let i = 0 ; i < 8 ; i ++ ) { bank ++ ; zsim . ports . write ( 0x243B , 0x50 + slot ) ; zsim . ports . write ( 0x253B , bank ) ; const value = zsim . memory . read8 ( address ) ; assert . equal ( 100 + 10 * slot + bank , value ) ; } } } ) ; test ( 'bank switching ROM' , ( ) => { zsim . ports . write ( 0x243B , 0x50 + 0 ) ; zsim . ports . write ( 0x253B , 10 ) ; zsim . ports . write ( 0x243B , 0x50 + 1 ) ; zsim . ports . write ( 0x253B , 11 ) ; zsim . memory . write8 ( 0x0000 , 100 ) ; zsim . memory . write8 ( 0x0001 , 101 ) ; zsim . memory . write8 ( 0x3FFE , 102 ) ; zsim . memory . write8 ( 0x3FFF , 103 ) ; zsim . ports . write ( 0x243B , 0x50 + 0 ) ; zsim . ports . write ( 0x253B , 0xFF ) ; zsim . ports . write ( 0x243B , 0x50 + 1 ) ; zsim . ports . write ( 0x253B , 0xFF ) ; let value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 0xF3 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 0xAF , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 0x42 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 0x3C , value ) ; zsim . ports . write ( 0x243B , 0x50 + 0 ) ; zsim . ports . write ( 0x253B , 10 ) ; zsim . ports . write ( 0x243B , 0x50 + 1 ) ; zsim . ports . write ( 0x253B , 11 ) ; value = zsim . memory . read8 ( 0x0000 ) ; assert . equal ( 100 , value ) ; value = zsim . memory . read8 ( 0x0001 ) ; assert . equal ( 101 , value ) ; value = zsim . memory . read8 ( 0x3FFE ) ; assert . equal ( 102 , value ) ; value = zsim . memory . read8 ( 0x3FFF ) ; assert . equal ( 103 , value ) ; } ) ; } ) ; } ) ;