Add check __riscv_flen in generator.
@@ -227,9 +227,12 @@ static inline struct all_gen_ctx **all_gen_ctx_loc (MIR_context_t ctx) {
#elif defined(__s390x__)
#include "mir-gen-s390x.c"
#elif defined(__riscv)
-#if __riscv_xlen != 64 || !__riscv_float_abi_double || !__riscv_mul || !__riscv_div \
- || !__riscv_compressed
-#error "only 64-bit RISCV supported (at least rv64imafdc)"
+#if __riscv_xlen != 64 || __riscv_flen < 64 || !__riscv_float_abi_double || !__riscv_mul \
+ || !__riscv_div || !__riscv_compressed
+#error "only 64-bit RISCV supported (at least rv64imafd)"
+#endif
+#if __riscv_flen == 128
+#error "RISCV 128-bit floats (Q set) is not supported"
#endif
#include "mir-gen-riscv64.c"
#else
