Slight clarification added
@@ -13,7 +13,8 @@ supported operations, and the datapath interconnection network.
The internal processor template of OpenASIP is based on the energy efficient and
modular Transport Triggered Architecture (TTA), which is still its default
-target programming model for static multi-issue designs. OpenASIP, however, also has initial support for other programming models such
+target programming model for static multi-issue designs. OpenASIP, however,
+also has initial support for other programming models such
as standard operation-based VLIW (demonstrated in Blocks CGRA) and since 2.0
it received the first features to support customizing RISC-V ISA based
processors.
@@ -24,10 +25,11 @@ since the early 2003.
License:
* OpenASIP project source code is licensed with LGPL v2.1.
- * Generated hardware description files are licensed with a more permissive MIT license.
+ * Generated hardware description files are licensed with a more
+permissive MIT license, to allow the designer more freedom to
+choose the licensing of the produced processors.
* Read more in [LICENSE.txt](https://github.com/cpc/openasip/blob/main/LICENSE.txt)
-
Links:
* [The toolset web pages](http://openasip.org)
