tests: clock_control: stm32h7: pll2: Fix test configuration
In test spi1_pll2p_1, pll2 should be enabled instead of pll3.
* It is assumed that it is applied after core_init.overlay file.
*/
-&pll3 {
+&pll2 {
clocks = <&clk_hse>;
div-m = <1>;
mul-n = <24>;
