Clarified the state of 64b support
Notable changes and features
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- Experimental support for 64-bit little-endian TTA processors.
+ Please note that the support is at the architecture level yet;
+ compilation and simulation is implemented, but RTL generation is
+ still incomplete (HDB for 64b FUs not yet added).
- New instruction scheduler which is much more aggressive at
performing software bypasses, which reduces register pressure.
Creates considerably faster code with processor architectures with
