include: dt-bindings: clocks: stm32wb_clock: Add RFWKP_SEL()
Add macros and defines related to the ability to select RFWK domain
clock.
#define STM32_SRC_LSE 0x003
#define STM32_SRC_LSI 0x004
#define STM32_SRC_MSI 0x005
+#define STM32_SRC_HSE 0x006
/** System clock */
-#define STM32_SRC_SYSCLK 0x006
+#define STM32_SRC_SYSCLK 0x007
/** Bus clock */
-#define STM32_SRC_PCLK 0x007
+#define STM32_SRC_PCLK 0x008
/** PLL clock outputs */
-#define STM32_SRC_PLL_P 0x008
-#define STM32_SRC_PLL_Q 0x009
-#define STM32_SRC_PLL_R 0x00a
+#define STM32_SRC_PLL_P 0x009
+#define STM32_SRC_PLL_Q 0x00a
+#define STM32_SRC_PLL_R 0x00b
/* TODO: PLLSAI clocks */
#define STM32_CLOCK_REG_MASK 0xFFU
/** @brief RCC_BDCR register offset */
#define BDCR_REG 0x90
+/** @brief RCC_CSR register offset */
+#define CSR_REG 0x94
+
/** @brief Device domain clocks selection helpers */
/** CCIPR devices */
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
#define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
/** BDCR devices */
#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
+/** CSR devices */
+#define RFWKP_SEL(val) STM32_CLOCK(val, 3, 14, CSR_REG)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */
