Ferroelectric memories employ ferroelectric capacitors as memory cells to retain information during the time the power is off. In ferroelectric memories, writing is performed by polarizing a ferroelectric capacitor upon applying positive or negative voltage thereto. Reading is performed by detecting the presence or absence of polarization inversion current observed upon applying positive voltage to the ferroelectric capacitor.
FIG. 1 is a drawing illustrating an example of the configuration of a memory cell of a ferroelectric memory. The memory cell illustrated in FIG. 1 includes a cell selection transistor 10, a ferroelectric capacitor 11, a word line WL, a bit line BL, and a plate line PL. This memory cell serves to store one-bit information by use of one transistor and one capacitor, and is referred to as a 1T1C-type memory cell.
In a write operation, the word line WL is placed in a selected state (HIGH), thereby turning on the cell selection transistor 10. Upon positive or negative voltage being applied between the bit line BL and the plate line PL, such voltage is applied to the ferroelectric capacitor 11, thereby writing desired data. In the case of writing “0” data, the bit line BL is set to LOW, and the plate line PL is set to HIGH. In the case of writing “1” data, the bit line BL is set to HIGH, and the plate line PL is set to LOW. Even after removal of the applied voltage upon completion of the write operation, polarization of the ferroelectric capacitor remains so that the written data is retained as nonvolatile data.
In a read operation, the word line WL is selected to turn on the cell selection transistor 10, and the plate line PL is set to HIGH. The bit line BL is kept to LOW, so that positive voltage is applied to the ferroelectric capacitor 11. In the case of “0” being stored in the ferroelectric capacitor 11, no polarization inversion occurs because the voltage applied to the ferroelectric capacitor 11 has the same polarization as during the write operation. As a result, a relatively small amount of electric charge flows into the bit line BL. In the case of “1” being stored in the ferroelectric capacitor 11, polarization inversion occurs because the voltage applied to the ferroelectric capacitor has the opposite polarization to the voltage applied during the write operation. As a result, a large amount of electric charge flows into the bit line BL. A sense amplifier senses this current to detect data.
FIG. 2 is a drawing illustrating the signal waveforms of the ferroelectric memory cell illustrated in FIG. 1. The read operation of a ferroelectric memory is a destructive read operation that destroys the stored data. In the ferroelectric memory, a read operation is first performed regardless of whether a read operation or a write operation is intended to be performed.
As illustrated in FIG. 2, the word line WL is set to HIGH to make conductive the cell selection transistor 10 illustrated in FIG. 1. Subsequently, the plate line PL is raised to HIGH, thereby causing the electric charge of the ferroelectric capacitor 11 to be output to the bit line BL. After this read operation, a write operation is performed.
In the write operation, the plate line PL is lowered to LOW. In order to write “0”, thereafter, the bit line BL and the plate line PL are both maintained at LOW. In order to write “1”, the plate line PL is maintained at LOW while the bit line BL is changed to HIGH. After this, in the case of a RTZ-method ferroelectric memory, the bit line BL is lowered to LOW at the time of completing the write operation.
A change from HIGH to LOW in the bit line BL for the purpose of writing “1” results in the potential of the plate line PL being temporarily lowered by being pulled down by the bit line BL because of the capacitive coupling provided by the ferroelectric capacitor 11 between the plate line PL and the bit line BL. As a result, an undershoot waveform 15 as illustrated in FIG. 2 appears in the plate line PL.
In a memory array, the word line WL and the plate line PL are generally connected to a plurality of ferroelectric memory cells arranged in a single row. Among the ferroelectric capacitors 11 connected to the same plate line PL, a large number of ferroelectric capacitors 11 may have data “1” written therein. In such a case, a large potential drop due to undershooting is observed with respect to the plate line PL. Consequently, a disturb phenomenon occurs in which the amount of polarization is reduced in the ferroelectric capacitors 11 having “0” written therein and connected to the plate line PL of interest. As a result, the reliability of the ferroelectric memory is undermined.
FIGS. 3A through 3C are drawings illustrating the mechanism by which a ferroelectric capacitor having “0” written therein suffers disturbance.
A ferroelectric capacitor having “0” written therein is placed in the state in which no voltage is applied. In such a state, the ferroelectric capacitor has a polarization state indicated by the position of a polarization state 16 on the curves indicative of hysteresis characteristics illustrated in FIG. 3A. Thereafter, a write operation to write “1” to another ferroelectric capacitor that shares the same plate line PL comes to an end, which results in an undershoot being generated on the plate line PL. Due to this undershooting, the voltage state changes toward a state in which applied voltage is negative, i.e., moves toward the left-hand side in FIG. 3A. Consequently, the polarization state of the ferroelectric capacitor having “0” written therein moves to the position of a polarization state 17 illustrated in FIG. 3B. Upon the plate line PL returning to its original potential, the polarization state changes in accordance with the minor loop characteristics of the hysteresis of the ferroelectric capacitor. The polarization state of the ferroelectric capacitor having “0” written therein thus ends up moving to the position of a polarization state 18 illustrated in FIG. 3C. In this manner, the amount of polarization of data “0” decreases as indicated by the position of the polarization state 18 compared with the original polarization state 16.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-135488
[Patent Document 2] Japanese Laid-open Patent Publication No. 2007-80343
[Patent Document 3] Japanese Laid-open Patent Publication No. 2009-64440
[Patent Document 4] Japanese Laid-open Patent Publication No. 2004-227686