In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The downscaling of CMOS devices imposes scaling constraints on the gate dielectric material. The thickness of the standard SiO2 gate dielectric oxide is approaching a level (˜10 angstrom (A)) at which tunneling currents may significantly impact transistor performance. To increase device reliability and reduce electron leakage from the gate electrode to the transistor channel, semiconductor transistor technology is using high-k gate dielectric materials that allow increased physical thickness of the gate dielectric layer while maintaining an equivalent gate oxide thickness (EOT) of less than about 10 A.
Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrate (e.g., SiO2, SiOxNy). High-k materials may incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO, HfO2 (k˜25)).
Integration of high-k materials into gate electrode applications can require a dielectric interfacial layer at the surface of the Si substrate to preserve interface state characteristics and form an interface with good electrical properties. However, the presence of an oxide interfacial layer lowers the overall dielectric constant of the microstructure and, therefore, the oxide interfacial layer may need to be thin. The quality of the interfacial oxide dielectric layer can affect device performance, as the oxide layer is intimately connected to the channel of the transistor.