1. Field
The disclosure relates generally to an improved data processing system, and more specifically to providing a write-back coherency data cache for temporarily holding cache lines in the process of being written back to main memory to resolve read/write conflicts and improve system performance.
2. Description of the Related Art
Memory bandwidth is a limiting factor with many modem microprocessors, and caches are typically employed to reduce the amount of memory traffic and decrease average access times in central processing unit (CPU) memory hierarchies, file systems, and so on. A cache is a smaller, faster memory bank that stores copies of the data from the most frequently used main memory locations. As many programs tend to access the same data or instructions over and over, maintaining as much of this information as possible in a cache allows the processor to avoid having to access the slower main memory of the data processing system to obtain the information.
Instructions and data are transferred from main memory to the cache in blocks, using some kind of look-ahead algorithm. The more sequential the instructions in the routine being executed or the more sequential the data being read or written, the greater chance the next required item will already be in the cache, resulting in better performance. When the processor needs to read from or write to a location in main memory, the processor first checks whether a copy of that data is in the cache. If so, the processor immediately reads from or writes to the cache, which is faster than reading from or writing to main memory.