Q:

circular shift left of indexes - verilog

I want to connect two modules so that
 output_module1[i] --> input_module2[circular_shift_left(i)]
for example :
output_module1[100] --> input_module2[001] // (output no. 5 to input no. 2)

output_module1[011] --> input_module2[110] // (output no. 4 to input no. 7)

the length of both modules is generic.
what's the most efficient (and easiest) way to implement it in verilog?
Thanks.

A:

Probably the easiest way to make a circular shift would be to combine the part select and concatenation operators.
wire [7:0] in;
wire [7:0] out;

assign out = {in[6:0], in[7]};

