1. Field of the Invention
The present invention relates to semiconductor manufacturing. More particularly, the present invention relates to the manufacture of field effect transistors (FETs) having vertical fins (FinFETs).
2. Description of the Prior Art
A FinFET is known in the art to be the simplest double gate structure to manufacture. Hence, the FinFET is a promising candidate to achieve ultimate device scaling.
In a FinFET, a vertical fin is defined to form the body of a transistor. Gates can be formed on one or both sides of the vertical fin. When both sides of the vertical fin have a gate formed thereon, the transistor is generally referred to as a double-gate FinFET. A double-gate FinFET helps suppress short channel effects (SCE), reduce leakage, and enhance switching behavior. Also, a double-gate FinFET can increase gate area, which can in turn improve current control, without increasing gate length.
Current FinFET process technology suffers from certain drawbacks. One significant drawback stems from the sacrificial oxidation and pre-gate oxide clean processes. These processes are used to remove/heal the significant damage that results from the techniques or processes used to form the vertical fin of the FinFET. The sacrificial oxidation is typically used to heal etching damage and the pre-gate oxide clean is used to remove sacrificial oxidation. These processes may also be used to prepare a surface channel for a gate oxidation process.
FIGS. 1a through 1f illustrate an example method of forming a FinFet in the prior art. As shown in FIG. 1a, a semiconductor substrate such as, for example, a silicon-on-insulator (SOI) substrate 100 can have a first semiconductor layer 102, an overlying insulating layer 104, and an overlying second semiconductor layer 106. As shown in FIG. 1b, an overlying hard mask 108 may be provided with a patterned photoresist layer 110 thereon. As shown in FIG. 1c, the photoresist layer 110 may be trimmed or patterned using a hard mask etching. As shown in FIG. 1d, in combination, the photoresist layer 110 and the second semiconductor layer 106 may be selectively etched using the hard mask 108, for example, to form a vertical fin structure from the second semiconductor layer 106. As shown in FIG. 1e, an oxide, 112 formed by a sacrificial oxidation process may be used to heal any etching damage. As shown in FIG. 1f, a pre-gate oxide clean may be used to remove the sacrificial oxidation. Over-etching may be required to ensure that all of the sacrificial oxide is removed.
As a consequence of the etching processes, undercuts 114 may be formed at the base of the vertical fin structure. Hence, substantially thin fins, which are commonly used for gate-length scaling, can be undercut to such an extent that the integrity of the fin becomes compromised and the fin can be susceptible to collapse. Whereas, with ticker fins, the undercut can trap gate electrode material, which can cause gate shorts when several gates share the same fin.
The present invention is directed to an improved structure and method for fabricating FinFET devices that overcomes at least the above noted drawback.