1. Field of the Invention
The present invention relates to a driving method suitable for an active matrix type display which uses a display medium such as a liquid crystal and has a built-in driving circuit, and particularly to an alternating drive method of a liquid crystal panel.
2. Description of the Related Art
FIG. 7 is a block diagram of a conventional liquid crystal display device.
A liquid crystal panel 1 includes a plurality of scanning lines 2 extending in parallel with each other in the horizontal direction, a plurality of signal lines 3 extending in parallel with each other in the vertical direction intersecting the scanning lines at right angles, TFTs (thin film transistors) disposed near the intersecting portions of the scanning lines and the signal lines, and pixel electrodes connected to the TFTs. One end of each of the scanning lines 2 is connected to a gate electrode of each of the TFTs and the other end thereof is connected to a gate driver circuit 4 (scanning line drive circuit). One end of each of the signal lines 3 is connected to a source electrode of each of the TFTs and the other end thereof is connected to a source driver circuit 5 (signal line drive circuit).
A video signal from a signal processing circuit 6, and a start pulse signal, a clock signal, a horizontal synchronizing signal, etc. from a control circuit 7 are inputted to the source driver circuit 5.
The signal processing circuit 6 includes an analog/digital (A/D) conversion circuit 14, a correcting circuit 8, a digital/analog (D/A) conversion circuit 9, a reversal process circuit 10, and the like.
The control circuit 7 is a circuit for forming, on the basis of a video signal, pulses (start pulse, clock pulse, synchronizing signal, polarity reversal signal, etc.) necessary for the gate driver circuit 4, the source driver circuit 5, the signal processing circuit 6, and the like and for outputting the pulses.
The operation of the conventional liquid crystal display device structured as described above will be described.
First, while using an inputted synchronizing signal as a reference, the control circuit 7 repeats an operation (frequency division) of counting a predetermined count number (frequency division ratio) of clocks, with an oscillation clock signal (OSC) outputted from a phase synchronized oscillator as a basic oscillation. The control circuit 7 counts the clocks at the same time as the frequency division, and forms a start pulse 23 (SPD) in the screen horizontal direction, a start pulse 24 (SPS) in the screen vertical direction, a clock pulse 25 (CLD) in the screen horizontal direction, a clock pulse 26 (CLS) in the screen vertical direction, and a polarity reversal signal 22 (FRP). There is also a case where a horizontal synchronizing signal (HYS) and a vertical synchronizing signal (VSY) are formed. In this case, the HSY and the VSY are used as references in the horizontal and vertical directions when, for example, characters are displayed on the screen.
An input video signal 20 includes such signals that picture signals of one screen (frame) are divided by the number of lines in the longitudinal direction (vertical direction), and the signals the number of which is equal to the number of lines in the longitudinal direction are continuous. Data in one pixel unit, that is, respective data of red (R), green (G), and blue (B) are made one set and are transmitted every unit time to an input video signal line.
Correspondingly to the input video signal 20, in a pixel region 11, pixels of R, G, and B corresponding to different three colors of red, green, and blue are sequentially repeatedly arranged in the lateral direction (horizontal direction) of the panel to make up a pixel row, and a pixel column is made up in the longitudinal direction (vertical direction). For example, if the pixel region 11 is made up of 640 pixels in the horizontal and 400 pixels in the vertical, a video signal of one screen includes such signals that lines in the horizontal direction, each including information signals of 640 pixels in the horizontal, are continuous by the number (400 columns) of lines in the vertical direction. In general, the input video signal is a signal corresponding to a CRT, and is not a signal suitable for liquid crystal panel display, so that it is necessary to carry out various signal processes.
In the signal processing circuit 6, a γ correcting process in view of liquid crystal characteristics, an analog/digital signal (A/D) converting process, a digital/analog signal (D/A) converting process, an alternating process to improve the reliability of liquid crystal, and the like are performed to the input video signal from an external device.
In this signal processing circuit 6, for the purpose of obtaining excellent display, various corrections are carried out to the input video signal inputted from the outside. For the corrections, analog RGB signals are first converted into digital RGB signals by the analog/digital signal (A/D) conversion circuit 14. The γ correcting process in view of the liquid crystal characteristics and the like are performed to the video signal converted into digital signals and corrections are made. The corrected video signals are again converted into analog RGB signals by the digital/analog signal (D/A) conversion circuit 9.
Next, by the reversal process circuit 10, the video signals are subjected to the alternating process and the like to improve the reliability of liquid crystal. A polarity reversal signal 22 (FRP) as a signal to determine the timing for carrying out polarity reversal necessary for driving the liquid crystal panel is inputted to the reversal process circuit 10 from the control circuit 7. The reversal process circuit 10 is a circuit for inverting the video signal in accordance with the polarity reversal signal 22 (FRP).
In this way, the signal processing circuit 6 processes the input video signal 20 into an analog video signal 27 suitable for display of the liquid crystal panel. This video signal (subjected to the γ correction, alternating process, and the like) is inputted to the liquid crystal panel 1.
Next, this video signal 27, the SPD 23 formed in the control circuit 7, and the CLD 25 are inputted to the source driver circuit 5 provided in the liquid crystal panel 1. The SPD 23 is a signal regulating the timing in one horizontal period when display is started. The CLD 25 is a signal corresponding to the respective pixels in the horizontal direction, and in accordance with this signal, the source driver circuit samples the video signal from the signal processing circuit and outputs a voltage (video signal) corresponding to the respective pixels to the signal line 3. FIG. 9 is a timing chart in the source driver circuit.
The SPS 24 and the CLS 26 formed in the control circuit 7 are inputted to the gate driver circuit 4. The SPS 24 is a signal regulating the timing in one vertical period when display is started. The CLS 26 is a signal corresponding to the respective pixels in the vertical direction, and it is designed such that in accordance with this signal, scanning is carried out every one horizontal period from the upper portion of the screen and the screen is displayed.
The design of displaying the screen will be described in detail with reference to FIGS. 8A and 8B.
First, in accordance with a signal from a shift register, with respect to the signal line (1), only one portion (pixel A1) of a lateral direction (horizontal direction) line of the video signal 27 is selected and sampled, and its potential is applied to the entire of the signal line (1). A signal voltage (turning on a TFT provided in the vicinity of an intersecting portion) is applied to only a scanning line A. Then, only the TFT provided in the vicinity of the intersecting portion of the signal line (1) and the scanning line A is turned on and the potential of the signal line (1) is applied to the pixel A1. In this way, part of picture image information is written in the pixel A1.
Next, while the state where the pixel A1 has been written is held by auxiliary capacitance or the like, at a next instance, only one portion (pixel A2) in the lateral direction (horizontal direction) line of the video signal is selected and sampled, and its potential is applied to a signal line (2) adjacent to the signal line (1). In this way, part of the picture image information is written also in the pixel A2 similarly to the pixel A1. This process is sequentially repeated, so that part of the picture image information is sequentially written in the first pixel line (A row) in the lateral direction. During this, the signal turning on the TFT provided in the vicinity of the intersecting portion is applied to the scanning line A.
After writing in all of the first pixel row A in the lateral direction is ended, a signal voltage (turning on a TFT provided in the vicinity of an intersecting portion) is next applied to only a scanning line B. In the signal line (1), only one portion (pixel B1) of the video signal is sampled, and its potential is held. Similarly to the above, only pixel row (B row) corresponding to the second row in the lateral direction is sequentially written. Such operations are repeated n times, n being the number of pixel rows (n rows), so that one screen is displayed.
In general, in a liquid crystal display using TFTs, for the purpose of preventing deterioration of a liquid crystal material, eliminating display blur, and keeping display quality, voltages that the polarities of which are inverted every one frame or predetermined period are applied (alternated) to the respective pixels.
One of conventional typical alternating drive methods in a liquid crystal display panel will be described with reference to FIG. 10 and FIG. 11. Here, for simplification, an example is shown while using a model screen (FIG. 11A) of display pixels of 6 rows×6 columns as part of a display region.
First, the polarity reversal signal 22 (FRP) for inverting the polarity of the input video signal 20 is formed by the control circuit. The waveform of this polarity reversal signal 22 is shown in FIG. 10. On the basis of such polarity reversal signal (FRP), the polarity of the video signal is inverted. This video signal has a signal waveform in which the polarity is inverted from the positive to the negative or from the negative to the positive every one pixel.
Thus, the panel display as shown in FIG. 11B is obtained. The video signals having the same polarity (positive or negative) are applied to the pixel electrodes denoted by A1, B1, C1, . . . , A3, B3, C3, . . . , and A5, B5, C5, . . . . Similarly, although the video signals having the same polarity (negative or positive) are applied to the pixel electrodes denoted by A2, B2, C2, . . . , A4, B4, C4, . . . , and A6, B6, C6, . . . , the polarity is opposite to the pixel electrode A1. That is, the video signals having opposite polarities between adjacent pixels in the lateral (horizontal) direction are applied to the respective pixels. Besides, as shown in FIG. 11C, in the next screen (frame), the video signals having polarities opposite to the previous screen (frame) are applied to the respective pixels. By repeating this operation, alternating drive is carried out. Such an alternating method is called a source line inversion (or reversal), or a column inrevrsion.
As other alternating drive methods of display of a liquid crystal display panel, as shown in a display pattern view of FIG. 12A, there is proposed an alternating ethod (frame reversal method) in which the polarity of a video signal is inverted at each time when one screen (frame) is written and the video signal is applied to the pixels.
However, in this method, a polarity reversal period is as long as one frame, and becomes a frequency region (about 30 Hz) which can be recognized by human eyes, so that an observer recognizes a subtle difference between the display where the polarity of the video signal is positive and the display where the polarity of the video signal is negative, as a flicker.
Moreover, as another alternating drive method to lower the flicker produced by the above frame reversal method, as shown in a display pattern view of FIG. 12B, there is proposed an alternating method (gate line reversal method) in which the polarity of a video signal is inverted every writing of adjacent one scanning line and the video signal is applied to the pixel. In this method, the video signals having opposite polarities between adjacent pixels in the longitudinal (vertical) direction are applied to the respective pixels. In this method, the polarity of the video signal is inverted from the positive to the negative or from the negative to the positive every one horizontal scanning period.
In addition, as an alternating drive method where it is hardest to produce a flicker, as shown in a display pattern view of FIG. 12C, there is proposed an alternating method (dot reversal method) in which the polarity of a video signal is inverted at each time of writing of adjacent all pixels and the video signal is applied to the pixel. In this method, a video signal having a polarity opposite to adjacent pixels in the lateral (horizontal) direction and the longitudinal (vertical) direction is applied to the respective pixels. Also in this method, like the source line reversal, the polarity of the video signal is inverted from the positive to the negative or from the negative to the positive every one pixel. However, this alternating drive method can not be applied to all cases, and it has been impossible to carry out this method in interlace drive which is the main current at present, for example, in a two-line simultaneous writing method.
Like this, in the conventional alternating methods, as shown in FIG. 10, in order to invert the polarity of a video signal every one pixel or one horizontal period from the positive to the negative or from the negative to the positive, it is necessary to newly charge the capacitance of the video signal line every one pixel or every one horizontal scanning period, so that its consumed electric power is large.
Moreover, in the conventional structure, there are problems that if the polarity reversal period of the video signal is long, lowering (color shift, flicker, etc.) of display characteristics occurs, and if the polarity reversal period of the video signal is short, a phase shift, a noise, dulling of a signal waveform, and the like occur and inaccurate alternating drive is caused.
The number of display pixels of a display increases year-by-year, and in a panel having a high number of pixels, a drive frequency becomes very high. For example, in the NTSC standard, it is necessary that the number of pixels is about 400 thousands, and in the HDTV standard, it is necessary that the number of pixels is about 2 millions. Thus, the maximum frequency of an inputted video signal is about 6 MHz for the NTSC standard, and about 20 MHz to 30 MHz for the HDTV standard. In order to accurately display this video signal, it is necessary that the clock signal has a frequency (for example, about 50 MHz to 60 MHz) several times the video signal. In future, it is expected that fine and high quality display is still more required, and a video signal having a very fast dot clock comes to be processed.
Conventionally, it has been difficult to drive a liquid crystal panel while accurately alternating a video signal and a clock signal having such a high frequency band region. And also, it has been very difficult to constitute a circuit operating at a high frequency band region by TFTs using, for example, amorphous silicon or polycrystalline silicon.