1. Field of Invention
The present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) transistor. More particularly, the present invention relates to a method of fabricating a MOS having selective epitaxial growth (SEG) silicon.
2. Description of Related Art
As the line width of MOS is reduced to or less than 0.1 .mu.m according to the reduced design rule, in order to increase the margin for patterning a contact window, the SEG Si is gradually applied to the process of contact window where the source/drain region is exposed. However, there are still several problems with regard to the SEG Si that need to be overcome.
FIG. 1 is a schematic, cross-sectional view of a MOS having SEG Si. A gate 102 is formed on the substrate 100. The gate 102 is isolated from the substrate 100 by a gate oxide layer 104 and has an insulating spacer 106 formed on its sidewall. A source/drain region 108 is formed in the substrate 100, close to the gate 102, and a lightly doped region 110 is formed in the substrate 100 between the gate 102 and the source/drain region 108. After the formation of the above structure, SEG Si 112a, 112b is then formed on the gate 102 and the source/drain region 108.
Normally, the epitaxial silicon 112a, 112b should grow with the same orientation as that of the substrate 102 when the chemical reactants and the system parameters are controlled well. The epitaxial silicon 112a, 112b, however, becomes a polysilicon layer because of dopants in the source/drain region 108. Polysilicon is silicon composed of many, randomly arranged crystal unit cells, usually leading to a rough surface. Therefore, when the silicide is subsequently formed on SEG Si 112a, 112b, the silicide has an orientation similar to the polysilicon. As a result, the SEG Si 112a, 112b having sharp grains induces current leakage between the silicide and the substrate 100, which is known as the `dopant effect`. Accordingly, one of the troubles of SEG Si 112a, 112b is that the quality of the SEG Si 112a, 112b is varied with the dopants in the source/drain region 108, as illustrated in FIG. 1. Such phenomenon causes difficulty in the subsequent processes and leads to poor device quality, especially when the SEG Si is formed on a PMOS.
In addition, the SEG Si 112a, 112b grows at a high temperature and is formed after the formation of the lightly doped region 110. Such a high temperature, as is required to form the SEG 112a, 112b, makes the lightly doped region 110 diffuse outwardly so that the channel length becomes shorter when the line width is reduced. As a result, the short channel effect or the hot carrier effect are induced and cause device failure.