Q:

Pipelined Datapath

What does it mean to have a pipelined datapath in MIPS architecture?
All the examples I have read include doing laundry and waiting for certain tasks to finish, before moving on to other ones are fairly simple to comprehend.
I was hoping for a more in depth technical explanation of how exactly a pipelined datapath helps MIPS architecture run faster and how stalls work.

A:

I suppose the best explanation is in your textbook, StackOverflow is a little narrow to go into in-depth explanations, but anyhow -
A pipeline is simply a way to break down a chain of tasks into sequential steps. A pipelined CPU has special latches between the steps that synchronize with the clock, so that on every clock cycle, each of the steps can perform its task, and send the results to the next one. The big benefit from pipelining comes from the fact that once you fed the first element into the pipe (be that an instruction, or a bag of laundry, or whateve), the next cycle it's free to accept the next one, long before the previous elements finished the complete datapath (as a multi-cycle MIPS would do). 
This allows you, in a steady-state, to feed one element into the pipe per cycle, assuming no control/data hazards are detected. Therefore, the peak throughput of the machine remains 1 element per cycle (IPC=1 in the CPU nomenclature), while you have virtually no restriction on the length of the cycle! Theoretically, you can divide the work into more stages that are simpler and shorter, and shorten the cycle time (raising frequency, and overall throughput of work per time).
Of course there are limits, as the CPU industry has discovered not so long ago - once the pipe becomes too large, the penalty of a flushes (we ignored earlier) become a huge penalty, so it's not all roses. Finding the sweetspot of depth and complexity is basically the key point in pipeline design.

