The technology disclosed herein relates to semiconductor devices and methods for fabricating the semiconductor devices, and more particularly, to laterally diffused metal oxide semiconductor (LDMOS) transistors, which have a low on resistance while keeping a sufficient breakdown voltage, and methods for fabricating the LDMOS transistors.
In recent years, as the performance, multi-functionality, and power consumption of electronic apparatuses have been improved, there has been a demand for semiconductor devices incorporated in the electronic apparatus which have a higher breakdown voltage, higher power, a smaller size, lower power consumption, etc. Among the semiconductor devices, even in the fields of driver IC, power supply IC, etc., there has been a demand for MOS electric field effect transistors (MOSFETs) which have a lower on resistance while keeping the breakdown voltage at a predetermined level in order to achieve lower power consumption.
To meet the demand, an LDMOS transistor has been proposed in which the channel region is formed by ion implantation and thermal treatment, whereby a short-channel device can be formed independently of the accuracy of a mask. In the LDMOS transistor, the on resistance can be reduced by decreasing the channel resistance component. Note that there is typically a trade-off between the on resistance and the breakdown voltage, and this also holds true for the LDMOS transistor. Therefore, a LOCOS offset LDMOS transistor has been proposed in which, in order to keep a sufficient breakdown voltage, a thick oxide film is formed by LOCOS between the drain region and an end portion of the gate electrode so that the gate electrode end portion is offset from the drain region (the position of the effective gate end portion is shifted), whereby an electric field concentrated at the gate electrode end portion can be reduced.
FIG. 17 is a cross-sectional view of a typical LDMOS transistor. Here, the LDMOS transistor (semiconductor device) is of N-channel type.
As shown in FIG. 17, the typical semiconductor device includes an LOCOS oxide film 303, a p-type body diffusion region 302, an n-type source diffusion region 306, and an n-type drain diffusion region 307 which are formed in an upper portion of an n-type semiconductor substrate 301. The source diffusion region 306 is formed in an upper portion of the body diffusion region 302. The LOCOS oxide film 303 is formed between the source diffusion region 306 and the drain diffusion region 307, and is spaced apart from the body diffusion region 302.
A gate insulating film 304 is formed on the semiconductor substrate 301 including the body diffusion region 302. A gate electrode 305 is formed on the gate insulating film 304, extending onto the LOCOS oxide film 303. An interlayer insulating film 323 is formed on the gate electrode 305, the LOCOS oxide film 303, and the semiconductor substrate 301 with openings being formed above the source diffusion region 306 and the drain diffusion region 307. A source electrode 316 is formed on a portion of the source diffusion region 306 above which an opening of the interlayer insulating film 323 is provided. A drain electrode 317 is formed on a portion of the drain diffusion region 307 above which an opening of the interlayer insulating film 323 is provided.
In the semiconductor device (LDMOS transistor) of FIG. 17, the channel is a portion of the body diffusion region 302 which is located directly below the gate electrode 305 and closer to the LOCOS oxide film 303 below the gate electrode 305 as viewed from the source diffusion region 306.
In the LDMOS transistor of FIG. 17, the breakdown voltage is determined by an electric field concentrated at an end portion closer to the source diffusion region 306 of the LOCOS oxide film 303 or at a region where a bottom corner portion of the body diffusion region 302 and an n-type portion of the semiconductor substrate 301 are joined together.
In the LDMOS transistor, the concentration of an n-type impurity is lower at a portion of a surface portion (a gap region 309) of the semiconductor substrate 301 which is located between the body diffusion region 302 and the LOCOS oxide film 303 than at a portion of the semiconductor substrate 301 which is located below the LOCOS oxide film 303. As a result, the concentration of an electric field is reduced at a bird's beak portion of an end portion closer to the source diffusion region 306 of the LOCOS oxide film 303, and therefore, the breakdown voltage can be improved compared to a semiconductor device in which the impurity concentration of the gap region 309 is not reduced.