1. Field of the Invention
This invention relates to a method of fabricating semiconductor devices and, more specifically, to a method of fabricating MIM (Metal-Insulator-Metal) capacitors.
2. Description of the Related Art
It is required that a large capacitance capacitor is formed in a narrow space accompanying with the scaling down of the semiconductor device, especially for DRAM. MIM (Metal-insulator-metal) capacitor structure having top and lower electrodes made of metal has been developed for increasing capacitance. Japanese Patent Application Laid-Open No. 2006-303063 and Japanese Patent Application Laid-Open No. 2001-210787 disclose technology to process a lower electrode of such an MIM capacitor with a photoresist to control the interface where a metal lower electrode film contacts a dielectric film. Japanese Patent Application Laid-Open No. 2002-373945 discloses to integrate an MIM capacitor on an embedded DRAM (Logic mixed DRAM).
Oxidation of the metal lower electrode still gives rise to a problem during process of the lower electrode in an attempt to enhance capacitance while further scaling down semiconductor devices. Most of metal oxides have an insulating property. Therefore, formation of oxide film on the electrode surface thickens the capacitor film substantially so as to decrease capacitance. However, the present inventors get aware of following prior art problems. Removal of photoresist takes place with gas containing oxygen as described in Japanese Patent Application Laid-Open No. 2001-210787 so that oxygen oxidizes the lower electrode. An ashing method for protecting oxidation of a lower electrode is considered to fulfill ashing conditions for lowering the ashing temperature and halting oxidation. In such a case, the ashing rate drops. In order to compensate for the decrease in ashing rate, extension of time for the portion of the decrease of ashing rate is time consuming and cannot sufficiently prevent the lower electrode from being oxidized. In contrast, an attempt to attain high ashing rate (ashing rate for actual use) without using oxygen as in Japanese Patent Application Laid-Open No. 2006-303063 requires fulfillment of high bias conditions which damages devices.