The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a semiconductor chip including an electrode pad, an internal connecting terminal provided on the electrode pad, and a wiring pattern which is electrically connected to the internal connecting terminal.
A conventional semiconductor device includes a semiconductor device (for example, see FIG. 1) referred to as a chip size package which includes a semiconductor chip including an electrode pad, an internal connecting terminal provided on the electrode pad, and a wiring pattern which is electrically connected to the internal connecting terminal, and has an almost equal size to the size of the semiconductor chip as seen on a plane.
FIG. 1 is a sectional view showing a conventional semiconductor device.
Referring to FIG. 1, a conventional semiconductor device 100 has a semiconductor chip 101, an internal connecting terminal 102, a resin layer 103, a wiring pattern 104, a solder resist 106, and an external connecting terminal 107.
The semiconductor chip 101 has a semiconductor substrate 110 formed like a thin plate, a semiconductor integrated circuit 111, a plurality of electrode pads 112, and a protective film 113. The semiconductor integrated circuit 111 is provided on a surface side of the semiconductor substrate 110. The semiconductor integrated circuit 111 is constituted by a diffusion layer, an insulating layer and a wiring pattern (not shown). The electrode pads 112 are provided on the semiconductor integrated circuit 111. The electrode pads 112 are electrically connected to a wiring pattern provided on the semiconductor integrated circuit 111. The protective film 113 is provided on the semiconductor integrated circuit 111. The protective film 113 serves to protect the semiconductor integrated circuit 111.
The internal connecting terminal 102 is provided on the electrode pad 112. An upper end of the internal connecting terminal 102 is exposed from the resin layer 103. The upper end of the internal connecting terminal 102 is connected to the wiring pattern 104. The resin layer 103 is provided to cover the semiconductor chip 101 on a side where the internal connecting terminal 102 is disposed.
The wiring pattern 104 is provided on the resin layer 103. The wiring pattern 104 is connected to the internal connecting terminal 102. The wiring pattern 104 is electrically connected to the electrode pad 112 through the internal connecting terminal 102. The wiring pattern 104 has a pad 104A provided with an external connecting terminal 107. The solder resist 106 is provided on the resin layer 103 to cover the wiring pattern 104 in a portion excluding the pad 104A.
FIGS. 2 to 10 are views showing a process for manufacturing the conventional semiconductor device. In FIGS. 2 to 10, the same components as those in the conventional semiconductor device 100 shown in FIG. 1 have the same reference numerals.
First of all, at a step shown in FIG. 2, there is formed the semiconductor chip 101 having the semiconductor integrated circuit 111, the electrode pads 112 and the protective film 113 on the surface side of the semiconductor substrate 110 which has not been formed into a thin plate. At a step shown in FIG. 3, next, the internal connecting terminal 102 is formed on the electrode pads 112. In this stage, the internal connecting terminals 102 have a variation in a height.
At a step shown in FIG. 4, subsequently, a flat plate 115 is pressed against the internal connecting terminals 102 to cause the heights of the internal connecting terminals 102 to be equal to each other. Consequently, upper surfaces 102A of the internal connecting terminals 102 are formed to be almost flat surfaces. At a step shown in FIG. 5, then, the resin layer 103 is formed to cover the semiconductor chip 101 on the side where the internal connecting terminal 102 is formed and the internal connecting terminal 102.
At a step shown in FIG. 6, next, the resin layer 103 is polished until the upper surface 102A of the internal connecting terminal 102 is exposed from the resin layer 103. At this time, the polishing is carried out in such a manner that an upper surface 103A of the resin layer 103 is almost on the level with the upper surface 102A of the internal connecting terminal 102. Consequently, an upper surface of the structure shown in FIG. 6 (more specifically, the upper surface 103A of the resin layer 103 and the upper surface 102A of the internal connecting terminal 102) is flat.
At a step shown in FIG. 7, then, the wiring pattern 104 is formed on the upper surface of the structure illustrated in FIG. 6 which is flat. More specifically, a metal foil (not shown) is stuck to the upper surface of the structure shown in FIG. 6 and a resist (not shown) is then applied to cover the metal foil, and subsequently, the resist is exposed and developed to form a resist film (not shown) on the metal foil in a part corresponding to the region in which the wiring pattern 104 is formed. Thereafter, the metal foil is etched by using the resist film as a mask so that the wiring pattern 104 is formed (a subtractive method). Then, the resist film is removed. An exposing region of the resist is determined by detecting a position of an alignment mark (not shown) formed on the semiconductor integrated circuit 111 through an exposing device (not shown) having infrared rays or an X-ray transmitting function.
At a step shown in FIG. 8, subsequently, the solder resist 106 covering the wiring pattern 104 in a portion other than the pad 104A is formed on the resin layer 103.
At a step shown in FIG. 9, next, the semiconductor substrate 110 is polished from the back side of the semiconductor substrate 110 so that the semiconductor substrate 110 is made thin. At a step shown in FIG. 10, then, the external connecting terminal 107 is formed on the pad 104A. Consequently, the semiconductor device 100 is manufactured (for example, see Patent Document 1).
[Patent Document 1] Japanese Patent No. 3614828
In the method of manufacturing the conventional semiconductor device 100, however, it is necessary to provide the step of causing the heights of the internal connecting terminals 102 to be equal to each other and the step of polishing the resin layer 103 to expose the upper surfaces 102A of the internal connecting terminals 102 from the resin layer 103. For this reason, there is a problem in that a manufacturing cost of the semiconductor device 100 is increased with an increase in the number of the steps.
Moreover, the exposing device having the infrared rays or X-ray transmitting function which is to be used in the formation of the resist film for forming the wiring pattern 104 is expensive. For this reason, there is a problem in that the manufacturing cost of the semiconductor device 100 is increased.
In the case in which the exposing device having the infrared rays or X-ray transmitting function is used, furthermore, precision in the detection of the alignment mark is not sufficient. For this reason, there is a problem in that precision in the position of the wiring pattern 104 with respect to the internal connecting terminal 102 is reduced.