This invention relates generally to digital-to-analog converters (DAC), and more particularly the invention relates to multi-channel DACs.
Most DAC implementations use a single network to translate all of the digital data bits to analog levels. However, the feasibility of such an approach becomes limited as the number of bits, and therefore the network size and accuracy, increase. Furthermore, the feasibility of implementing multiple DACs which match each other is even further reduced since all of the channels use completely independent networks. One solution shown in prior art uses a single DAC whose output feeds multiple sample and hold amplifiers. This implementation gives excellent matching between channels but requires a systematic updating of each channel which causes glitches in the DAC outputs, as well as calibration wait cycle problems and slow digital update rate characteristics. Furthermore, only one DAC channel can be updated at a particular time.
The accuracy of a DAC is dominated by the network which maps the most significant bits (MSB) of the digital value to an analog value. It is known that a DAC can be split into two or more independent parts, one accurate network for the MSBs and one or more less accurate networks for LSBs. The outputs of these separate networks are then summed together. Where all of the networks output a current, the outputs can be tied together to produce a sum. Where all of the networks output a voltage, the outputs can be summed together with resistors. Prior art also shows that an output voltage can be created using an operational amplifier with resistive feedback by applying voltage to the positive terminal of the amplifier and a high output impedance current source to the negative terminal of the operational amplifier. See U.S. Pat. No. 4,811,017.