Q:

What should be considered when sizing trace widths for digital logic signals?

For traces that carry a static DC current, it's pretty easy to calculate the minimum trace width based on the required ampacity of the trace.  However, I'm not sure what should be considered when sizing a trace for CMOS, TTL, etc.
For example, if you've got flexibility in the board stackup and can make the trace thinner or wider and still meet the impedance requirements, what are the reasons for making the trace wider/thinner?
Do different logic families require different considerations for trace widths?
Are there reasons not to make digital logic traces as thin as possible to allow higher routing density with less crosstalk?

A:

Unless you're doing high frequency stuff, where you need to start worrying about
transmission-lining your traces and properly controlling impedances, you should generally be fine with whatever size you prefer.
Thinner traces have higher resistance, thicker traces have more capacitance (particularly when over ground planes).  The capacitive loading of thick traces over a closely spaced ground plane could potentially be an issue, though generally to encounter such problems, you are likely edging into the RF domain anyways.
Most modern logic devices have very high-impedance inputs, so higher trace resistance isn't that much of a problem. Realistically, there is a fairly broad range of trace-widths that would work fine in most low-speed logic applications. As such, I tend to just go with whatever seems to look best, but that's an entirely subjective measure. One advantage to slightly thicker traces is they're easier to cut and solder to, if you need to make board-hacks at some point, but anything can be modified if you have the time.

