// *********************************************************
// *                                                       *
// *     Automatically generated file => do not edit!      *
// *                                                       *
// *********************************************************
// *                                                       *
// *       https://github.com/MahdiSafsafi/Azote           *
// *                                                       *
// *********************************************************

{ This file provides necessary info to decodes instruction operands.
  For each operand, it provides decoding info such where the operand is stored (field), sign position,... }

type
  TOperandKind = (
    None,
    Barrier,
    Cm,
    Cn,
    Cnst0,
    CnstFP0,
    Cnst_CSYNC,
    Cond,
    Dd,
    Dm,
    Dn,
    Ed,
    Em,
    Em_4B,
    En,
    FBits,
    FBitsR,
    Fa,
    Fd,
    Fm,
    Fn,
    Ha,
    Hd,
    Hm,
    Hn,
    Imm16,
    Imm5,
    Imm6,
    Imm8Sft,
    ImmA,
    ImmFP,
    ImmFP8,
    ImmHint,
    ImmLog,
    ImmLong,
    ImmSys,
    ImmTest,
    ImmWide,
    Immr,
    Imms,
    Index,
    LEt,
    LVn,
    LVt,
    Lsb,
    LsbR,
    NZCV,
    Nd,
    Nd_P1,
    Nd_P2,
    Nm,
    Nm_P2,
    Nn,
    Nn_P1,
    Nn_P2,
    Nt,
    Od,
    Op1,
    Op2,
    Ot,
    Ot2,
    Pair,
    Prfop,
    Pstatefield,
    Qd,
    Qn,
    Ra,
    Rd,
    Rd_SP,
    Rel14,
    Rel19,
    Rel26,
    RelLong,
    Rm,
    Rm_EXT,
    Rm_SFT,
    Rn,
    Rn_SP,
    Rot1,
    Rot2,
    Rot3,
    Rs,
    Rt,
    Rt2,
    Sd,
    ShiftImmr,
    ShiftImms,
    ShiftLL,
    ShiftLeft,
    ShiftRight,
    Sn,
    SysReg_AT,
    SysReg_DC,
    SysReg_IC,
    SysReg_TLBI,
    Systemreg,
    Va,
    Va_P2,
    Vd,
    Vd_N2,
    Vd_N4,
    Vd_N6,
    Vd_P1,
    Vd_P2,
    Vd_P3,
    Vd_P4,
    Vd_P5,
    Vd_P6,
    Vd_S,
    Vm,
    Vm_N2,
    Vm_N4,
    Vm_N6,
    Vm_P2,
    Vm_P3,
    Vm_P4,
    Vn,
    Vn_2H,
    Vn_N1,
    Vn_N2,
    Vn_N4,
    Vn_N6,
    Vn_P2,
    Vn_P3,
    Vn_P4,
    Vn_P5,
    Vn_S,
    Wd,
    Width,
    Wm,
    Wn,
    Ws,
    Wt,
    Xa,
    Xd,
    Xm,
    Xm_SP,
    Xn,
    Xn_SP,
    Xt,
    Xt2,
    addr,
    addr_regoff,
    addr_simm10s,
    addr_simm7s,
    addr_simm9u,
    addr_struct,
    addr_uimm12s
);

const
  OperandsInfo: array [TOperandKind] of TOperandInfo = (
    { None } (),
    { Barrier      } (OperandClass: CLASS_BARRIER     ;  Fields: (FLD_CRm, FLD_None, FLD_None)),
    { Cm           } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_CRm, FLD_None, FLD_None)),
    { Cn           } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_CRn, FLD_None, FLD_None)),
    { Cnst0        } (OperandClass: CLASS_CONST       ;  Data: NativeInt(DATA_IMM0)),
    { CnstFP0      } (OperandClass: CLASS_CONST       ;  Data: NativeInt(DATA_IMM_FP0)),
    { Cnst_CSYNC   } (OperandClass: CLASS_CONST       ;  Data: NativeInt(DATA_CSYNC)),
    { Cond         } (OperandClass: CLASS_COND        ;  Fields: (FLD_cond, FLD_None, FLD_None)),
    { Dd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_D ; RegNo: FLD_Rd)),
    { Dm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_D ; RegNo: FLD_Rm)),
    { Dn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_D ; RegNo: FLD_Rn)),
    { Ed           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_E ; RegNo: FLD_Rd)),
    { Em           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_E ; RegNo: FLD_Rm)),
    { Em_4B        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_E ; RegNo: FLD_Rm ; T: T_4B)),
    { En           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_E ; RegNo: FLD_Rn)),
    { FBits        } (OperandClass: CLASS_FBITS       ;  Fields: (FLD_scale, FLD_None, FLD_None)),
    { FBitsR       } (OperandClass: CLASS_FBITS       ;  Fields: (FLD_immh, FLD_immb, FLD_None)),
    { Fa           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_F ; RegNo: FLD_Ra)),
    { Fd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_F ; RegNo: FLD_Rd)),
    { Fm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_F ; RegNo: FLD_Rm)),
    { Fn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_F ; RegNo: FLD_Rn)),
    { Ha           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_H ; RegNo: FLD_Ra)),
    { Hd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_H ; RegNo: FLD_Rd)),
    { Hm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_H ; RegNo: FLD_Rm)),
    { Hn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_H ; RegNo: FLD_Rn)),
    { Imm16        } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_imm16, FLD_None, FLD_None))),
    { Imm5         } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_imm5, FLD_None, FLD_None))),
    { Imm6         } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_imm6, FLD_None, FLD_None))),
    { Imm8Sft      } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Shift: FLD_cmode ; Fields: (FLD_abc, FLD_defgh, FLD_None))),
    { ImmA         } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Shift: FLD_shift ; Fields: (FLD_imm12, FLD_None, FLD_None))),
    { ImmFP        } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_abc, FLD_defgh, FLD_None))),
    { ImmFP8       } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_imm8, FLD_None, FLD_None))),
    { ImmHint      } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_CRm, FLD_op2, FLD_None))),
    { ImmLog       } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_N, FLD_immr, FLD_imms))),
    { ImmLong      } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_abc, FLD_defgh, FLD_None))),
    { ImmSys       } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_CRm, FLD_None, FLD_None))),
    { ImmTest      } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_b5, FLD_b40, FLD_None))),
    { ImmWide      } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Shift: FLD_hw ; Fields: (FLD_imm16, FLD_None, FLD_None))),
    { Immr         } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_immr, FLD_None, FLD_None))),
    { Imms         } (OperandClass: CLASS_IMMEDIATE   ;  Immediate: (Fields: (FLD_imms, FLD_None, FLD_None))),
    { Index        } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_Q, FLD_imm4, FLD_None)),
    { LEt          } (OperandClass: CLASS_LIST        ;  List: (Base: FLD_Rt; Element: True)),
    { LVn          } (OperandClass: CLASS_LIST        ;  List: (Base: FLD_Rn; Element: False)),
    { LVt          } (OperandClass: CLASS_LIST        ;  List: (Base: FLD_Rt; Element: False)),
    { Lsb          } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_imms, FLD_None, FLD_None)),
    { LsbR         } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_immr, FLD_None, FLD_None)),
    { NZCV         } (OperandClass: CLASS_NZCV        ;  Fields: (FLD_nzcv, FLD_None, FLD_None)),
    { Nd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rd)),
    { Nd_P1        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rd ; Patch: 1)),
    { Nd_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rd ; Patch: 2)),
    { Nm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rm)),
    { Nm_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rm ; Patch: 2)),
    { Nn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rn)),
    { Nn_P1        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rn ; Patch: 1)),
    { Nn_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rn ; Patch: 2)),
    { Nt           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_N ; RegNo: FLD_Rt)),
    { Od           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_O ; RegNo: FLD_Rd)),
    { Op1          } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op1, FLD_None, FLD_None)),
    { Op2          } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op2, FLD_None, FLD_None)),
    { Ot           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_O ; RegNo: FLD_Rt)),
    { Ot2          } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_O ; RegNo: FLD_Rt2)),
    { Pair         } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_PAIR)),
    { Prfop        } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_Rt, FLD_None, FLD_None)),
    { Pstatefield  } (OperandClass: CLASS_PSTATEFIELD ;  Fields: (FLD_op1, FLD_op2, FLD_None)),
    { Qd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_Q ; RegNo: FLD_Rd)),
    { Qn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_Q ; RegNo: FLD_Rn)),
    { Ra           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Ra)),
    { Rd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rd)),
    { Rd_SP        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rd ; SP: True)),
    { Rel14        } (OperandClass: CLASS_LABEL       ;  RelPC: (Imm: (FLD_imm14, FLD_None); Sign: 14)),
    { Rel19        } (OperandClass: CLASS_LABEL       ;  RelPC: (Imm: (FLD_imm19, FLD_None); Sign: 19)),
    { Rel26        } (OperandClass: CLASS_LABEL       ;  RelPC: (Imm: (FLD_imm26, FLD_None); Sign: 26)),
    { RelLong      } (OperandClass: CLASS_LABEL       ;  RelPC: (Imm: (FLD_immhi, FLD_immlo); Sign: 21)),
    { Rm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rm)),
    { Rm_EXT       } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rm ; Extend: FLD_option)),
    { Rm_SFT       } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rm ; Shift: FLD_shift)),
    { Rn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rn)),
    { Rn_SP        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rn ; SP: True)),
    { Rot1         } (OperandClass: CLASS_ROTATE      ;  Fields: (FLD_rot1, FLD_None, FLD_None)),
    { Rot2         } (OperandClass: CLASS_ROTATE      ;  Fields: (FLD_rot2, FLD_None, FLD_None)),
    { Rot3         } (OperandClass: CLASS_ROTATE      ;  Fields: (FLD_rot3, FLD_None, FLD_None)),
    { Rs           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rs)),
    { Rt           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rt)),
    { Rt2          } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_R ; RegNo: FLD_Rt2)),
    { Sd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_S ; RegNo: FLD_Rd)),
    { ShiftImmr    } (OperandClass: CLASS_SHIFT       ;  Fields: (FLD_immr, FLD_None, FLD_None)),
    { ShiftImms    } (OperandClass: CLASS_SHIFT       ;  Fields: (FLD_imms, FLD_None, FLD_None)),
    { ShiftLL      } (OperandClass: CLASS_SHIFT       ;  Fields: (FLD_size, FLD_None, FLD_None)),
    { ShiftLeft    } (OperandClass: CLASS_SHIFT       ;  Fields: (FLD_immh, FLD_immb, FLD_None)),
    { ShiftRight   } (OperandClass: CLASS_SHIFT       ;  Fields: (FLD_immh, FLD_immb, FLD_None)),
    { Sn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_S ; RegNo: FLD_Rn)),
    { SysReg_AT    } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op1, FLD_CRm, FLD_op2)),
    { SysReg_DC    } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op1, FLD_CRm, FLD_op2)),
    { SysReg_IC    } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op1, FLD_CRm, FLD_op2)),
    { SysReg_TLBI  } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_op1, FLD_CRm, FLD_op2)),
    { Systemreg    } (OperandClass: CLASS_SYSREG      ; ),
    { Va           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Ra)),
    { Va_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Ra ; Patch: 2)),
    { Vd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd)),
    { Vd_N2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: -2)),
    { Vd_N4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: -4)),
    { Vd_N6        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: -6)),
    { Vd_P1        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 1)),
    { Vd_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 2)),
    { Vd_P3        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 3)),
    { Vd_P4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 4)),
    { Vd_P5        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 5)),
    { Vd_P6        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; Patch: 6)),
    { Vd_S         } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rd ; T: T_S)),
    { Vm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm)),
    { Vm_N2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: -2)),
    { Vm_N4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: -4)),
    { Vm_N6        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: -6)),
    { Vm_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: 2)),
    { Vm_P3        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: 3)),
    { Vm_P4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rm ; Patch: 4)),
    { Vn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn)),
    { Vn_2H        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; T: T_2H)),
    { Vn_N1        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: -1)),
    { Vn_N2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: -2)),
    { Vn_N4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: -4)),
    { Vn_N6        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: -6)),
    { Vn_P2        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: 2)),
    { Vn_P3        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: 3)),
    { Vn_P4        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: 4)),
    { Vn_P5        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; Patch: 5)),
    { Vn_S         } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_V ; RegNo: FLD_Rn ; T: T_S)),
    { Wd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_W ; RegNo: FLD_Rd)),
    { Width        } (OperandClass: CLASS_PSEUDOIMM   ;  Fields: (FLD_imms, FLD_None, FLD_None)),
    { Wm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_W ; RegNo: FLD_Rm)),
    { Wn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_W ; RegNo: FLD_Rn)),
    { Ws           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_W ; RegNo: FLD_Rs)),
    { Wt           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_W ; RegNo: FLD_Rt)),
    { Xa           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Ra)),
    { Xd           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rd)),
    { Xm           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rm)),
    { Xm_SP        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rm ; SP: True)),
    { Xn           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rn)),
    { Xn_SP        } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rn ; SP: True)),
    { Xt           } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rt)),
    { Xt2          } (OperandClass: CLASS_REGISTER    ;  Register: (RegClass: REG_CLASS_X ; RegNo: FLD_Rt2)),
    { addr         } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_None, FLD_None); Sign: -1; Flags: 0)),
    { addr_regoff  } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_None, FLD_None); Sign: -1; Flags: MEM_REGOFF)),
    { addr_simm10s } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_S, FLD_imm9); Sign: 10; Flags: MEM_SCALED)),
    { addr_simm7s  } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_imm7, FLD_None); Sign: 7; Flags: MEM_SCALED)),
    { addr_simm9u  } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_imm9, FLD_None); Sign: 9; Flags: 0)),
    { addr_struct  } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_None, FLD_None); Sign: -1; Flags: 0)),
    { addr_uimm12s } (OperandClass: CLASS_MEMORY      ;  Memory: (Imm: (FLD_imm12, FLD_None); Sign: -1; Flags: MEM_SCALED))
);

