def create_serial_add_op(names, op_code, shifts, BW_in, BW_out, module_name,
    reset_name, depth):
    """
    Creates an add or subtract operation ( input c is not allowed, no shifts allowed )
    names = [ out_name, a_name, b_name, c_name ]
    op_code = 0 -> - a - b - c ( not allowed in this implementation )
    op_code = 1 -> - a - b + c ( not allowed in this implementation )
    op_code = 2 -> - a + b - c
    op_code = 3 -> - a + b + c
    op_code = 4 ->   a - b - c
    op_code = 5 ->   a - b + c
    op_code = 6 ->   a + b - c
    op_code = 7 ->   a + b + c
    shifts = [ shift_a, shift_b, shift_c ] ( not allowed in this implementation )
    BW_in -> the bitwidth of the input
    BW_out -> the bitwidth of the output
    module_name -> the name to call the adder
    reset_name -> the reset to use, will assert the reset on the cycle before use
    depth -> how deep the op is down the tree, inputs have a depth of 0 ( not used in this op )
    """
    assert names[3] == str(BW_out
        ) + "'h0", 'Three inputs not implemented in this adder'
    assert shifts[0] == 0 and shifts[1
        ] == 0, 'Shift registers not implemented in this adder'
    op_code = op_code >> 1
    if names[2] == str(BW_out) + "'h0" and op_code == 0:
        op_code = 1
    assert op_code != 0, 'Cannot be both negative inputs for serial adder for module ' + module_name
    neg_b = (op_code != 3) * 1
    if op_code == 1:
        names[1], names[2] = names[2], names[1]
    ser_add_module = ('wire [' + str(BW_in - 1) + ':0] ' + names[0] +
        """;
serial_adder #(
  .neg_b(""" + str(neg_b) + '),\n  .BW(' + str
        (BW_in) + ')\n) ' + module_name + """ (
 .clk(clock),
 .reset(""" +
        reset_name + '),\n .a(' + names[1] + '),\n .b(' + names[2] +
        '),\n .c(' + names[0] + ')\n);\n')
    return ser_add_module, BW_in
