def gen_signal_init_c(s, name, port):
    """Return C port variable initialization."""
    ret = []
    c_dim = s._get_c_dim(port)
    nbits = s._get_c_nbits(port)
    deference = '&' if nbits <= 64 else ''
    name = s._verilator_name(name)
    if c_dim:
        n_dim_size = s._get_c_n_dim(port)
        sub = ''
        for_template = (
            'for ( int i_{idx} = 0; i_{idx} < {dim_size}; i_{idx}++ )\n')
        assign_template = 'm->{name}{sub} = {deference}model->{name}{sub};\n'
        for idx, dim_size in enumerate(n_dim_size):
            ret.append(for_template.format(**locals()))
            sub += f'[i_{idx}]'
        ret.append(assign_template.format(**locals()))
        for start, dim_size in enumerate(n_dim_size):
            for idx in range(start + 1, len(n_dim_size) + 1):
                ret[idx] = '  ' + ret[idx]
    else:
        ret.append(f'm->{name} = {deference}model->{name};')
    return ret
