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shailja
/
fine-tuned-codegen-2B-Verilog
like
6
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
Inference Endpoints
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
Files and versions
Community
2
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main
fine-tuned-codegen-2B-Verilog
Commit History
Update README.md
f4e84b6
shailja
commited on
Aug 30, 2023
Update README.md
65ad462
shailja
commited on
Aug 30, 2023
Update README.md
d12d01d
shailja
commited on
Aug 30, 2023
Create README.md
0f48bb0
shailja
commited on
Aug 30, 2023
Create LICENSE
29c4f4e
shailja
commited on
Feb 10, 2023
Upload fine-tuned-codegen-2B-2gpu.tar.zst
09b74e1
shailja
commited on
Nov 24, 2022
Upload fine-tuned-codegen-2B-1gpu.tar.zst
da2b574
shailja
commited on
Nov 24, 2022
Upload fine-tuned-codegen-2B-2gpu.tar.zst
451fc30
shailja
commited on
Nov 16, 2022
Upload fine-tuned-codegen-2B-1gpu.tar.zst
0589afb
shailja
commited on
Nov 16, 2022
Upload 4 files
5c9b902
shailja
commited on
Nov 15, 2022
Upload CodeGenForCausalLM
80a77a9
shailja
commited on
Sep 18, 2022
initial commit
dde7640
shailja
commited on
Sep 18, 2022
shailja
commited on
