A memory architecture with the capability of self-test and self-repair is presented. The contributions of this memory architecture are twofold. First, it incorporates self-testing and self-repairing structures in the memory. As a result, the memory chips can perform tests, locate faults, and repair themselves without any external assistance, greatly improving the functional yield and reducing the production cost. Second, the architecture uses a hierarchical organization to achieve optimal conditions for memory access time. The hierarchical organization also increases the efficiency of the self-testing and self-repairing structures. >
['Tom Chen', 'Glen Sunada']
An ultra-large capacity single-chip memory architecture with self-testing and self-repairing