The objective of the SHA-3 NIST competition is to select, from multiple competing candidates, a standard algorithm for cryptographic hashing. The selected winner must have adequate cryptographic properties and good implementation characteristics over a wide range of target platforms, including both software and hardware. Performance evaluation in hardware is particularly challenging because of the large design space, wide range of target technologies, and multitude of optimization criteria. We describe the efforts of three research groups to evaluate SHA-3 candidates using a common prototyping platform. Using a SASEBO-GII FPGA board as a starting point, we evaluate the performance of the 14 remaining SHA-3 candidates with respect to area, throughput, and power consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specifications for the SHA-3 module on the SASEBO testing board.
['Kazuyuki Kobayashi', 'Jun Ikegami', 'Miroslav Knezevic', 'Eric Xu Guo', "Shin'ichiro Matsuo", 'Sinan Huang', 'Leyla Nazhandali', 'Ünal Koçabas', 'Junfeng Fan', 'Akashi Satoh', 'Ingrid Verbauwhede', 'Kazuo Sakiyama', 'Kazuo Ohta']
Prototyping platform for performance evaluation of SHA-3 candidates