Among the various tasks performed by software radios is the reconfiguration of the error control coding algorithm to match the requirement of the radio personality. In the digital radio processor, proper assignment of tasks between DSPs and FPGAs provides performance improvements over the use of DSPs alone. Error control coding functions are good candidates to reside on the FPGA side of this functional partition. Unfortunately, good VLSI designs for codes using BCH or Reed-Solomon codes do not map well to FPGAs. Good FPGA designs must parallelize at every opportunity, minimize timing delays through intelligent floor planning, and use each logic block to its fullest. We demonstrate the merits of these concepts by comparing the performance of popular finite field multiplier designs.
['Gregory C. Ahlquist', 'Michael Rice', 'Brent E. Nelson']
Error control coding in software radios: an FPGA approach