The deep sub micron era has brought numerous signal integrity and reliability issues to the forefront. The analysis of signal integrity and reliability problems increases the design cycle time. In this paper we present a common framework to analyze two important DSM issues, crosstalk glitch and gate oxide integrity. We describe many important features of the flow such as timing based pruning, glitch propagation, overshoot and undershoot glitch analysis techniques. Finally, we also present the crosstalk analysis results on some of the ASIC designs.
['N.V. Arviad', 'P.R. Suresh', 'V. Sivakumar', 'C. Pal', 'D. Das']
Integrated crosstalk and oxide integrity analysis in DSM designs