The past few years have witnessed high-end processors with increasing numbers of cores and larger dies. With limited instruction-level parallelism, chip power constraints, and technology-scaling limitations, designers have embraced multiple cores rather than single-core performance scaling to improve chip throughput. This article examines whether this approach is sustainable by scaling from a state-of-the-art big-chip design point using analytical models.
['Wei Huang', 'Karthick Rajamani', 'Mircea R. Stan', 'Kevin Skadron']
Scaling with Design Constraints: Predicting the Future of Big Chips