This paper presents a novel design for double-edge triggered flip-flops (DETFF). Detailed analysis of the transistors used in the DETFF was presented to find out those on the critical path. Therefore, the proposed DETFF employs low-V th  transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V th  transistors can be resolved at the same time. The proposed DETFF, thus, fully utilizes the multi-V  th  scheme provided by advanced CMOS processes without paying the price of large area, slow clocking frequency, and poor noise immunity. The proposed design is implemented using TSMC 0.18 mum 1P6M CMOS process. Post-layout simulation results reveal that the proposed DETFF saves at least 33 % power and 39 % power-delay product (i.e., the dissipated energy) at all PVT (process, supply voltage, temperature) corners
['Chua-Chin Wang', 'Gang-Neng Sung', 'Ming-Kai Chang', 'Ying-Yu Shen']
Engery-Efficient Double-Edge Triggered Flip-Flop Design