The contribution of this paper is twofold. We firstly show that an augmented diminished-1 adder can be used for the modulo 2 n  +1 addition of two n-bit operands in the weighted representation, if it is driven by operands whose sum has been decreased by 1. This scheme outperforms solutions that are based on the use of binary adders and/or weighted modulo 2 n  + 1 adders in both area and delay terms. We then apply this scheme in the design of residue generators (RGs) and multi-operand modulo adders (MOMAs). The resulting arithmetic components remove at least a whole parallel adder out of the critical path of the currently most efficient proposals. Experimental results indicate savings of more than 30% in execution time and of approximately 19% in implementation area when the proposed architectures are used.
['Haridimos T. Vergos', 'Dimitris Bakalis']
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components