In some computer network architectures a process communicates with another process across the network by establishing a virtual circuit. Consider a virtual circuit from node S to node D connected by multiple links. The delay suffered by the packets of the virtual circuit has three components: waiting time or queueing delay, service time or transmission delay, and resequencing delay. The sum of these is called the total delay. The author presents the distribution of the total delay for three different queuing models of node S: G/M/m model, G/M/ infinity model, and M/H/sub K// infinity model. >
['Shyamal K. Chowdhury']
Distribution of the total delay of packets in virtual circuits