A thorough and detailed analysis of an asynchronous 4-phase transfer protocol with early-zero reset is presented. The protocol is implemented by a micro-pipeline controller whose register-fixative (pipeline register) is implemented by dynamic (Edge) flip-flops, writing data by the rising edge of the signal. Based on this analysis two original results are obtained. The first one: the possible time interval for the reset of the micro-pipeline controller is defined. The second one is about the possibility of false switching of the controller. Different variants of logic schemes are commented in relations with the findings of the analysis. Technical requirements which the logical synthesis is based on are defined for both problems. The principle logical circuit of the pipeline controller is presented.  It's functioning is explained in details by a timing diagram.
['Dimitar Tyanev', 'Yulka Petkova']
Early-zero 4-phase micro-pipeline controller with protection