This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.
['Adrijean Adriahantenaina', 'Herve Charlery', 'Alain Greiner', 'Laurent Mortiez', 'Cesar Albenes Zeferino']
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network