In this paper, we describe an asynchronous (async) dual-rail 13 times 13-bit multiplier based on the single-track full-buffer (STFB) template. We propose several techniques to improve the energy-efficiency of the template. Firstly, we propose a new output driver sub-cell for the template suitable for driving smaller loads with higher energy efficiency. Secondly, we propose non-handshaking channels in order to reduce the pipeline stages in our design to trade-off throughput for higher energy-efficiency and smaller area. Lastly we propose using non weak-condition AND, 3-to-2 and 2-to-2 compressor cells to achieve lower forward latency. The performance of the proposed multiplier design is simulated using the TSMC 0.18 mum library at the transistor level. The proposed design is 15% more energy-efficient, has 14% lower latency and 34% smaller as compared to the same implementation using the STFB template.
['Kok-Leong Chang', 'Bah-Hwee Gwee', 'Yuanjin Zheng']
An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates