Processor core power is primarily consumed in a data path consisting of high-activity functional modules. We propose low-power/energy BIST schemes for data path architectures built around the most common combinations of multipliers, adders, ALUs, and shifters.
['Nektarios Kranitis', 'Dimitris Gizopoulos', 'Antonis M. Paschalis', 'Mihalis Psarakis', 'Yervant Zorian']
Power-/energy-efficient BIST schemes for processor data paths