Clock compensation for process variations and manufacturing defects is a key strategy to achieve high performance of processors and high end ASIC. However, with the increase in process variations and defect densities, clock compensation is becoming increasingly challenging. A clock distribution system also consumes over 30% of the overall chip level power, so every little bit counts, including compensation schemes. In this paper we propose a new scheme for the compensation of undesirable skews and duty-cycle variations of local clocks of high performance microprocessors and high end ASICs. Our scheme performs compensation continuously, during the microprocessor operation, thus allowing also compensation to clock jitters due to environmental influences during operation. Compared to alternate solutions for local clock compensation, our scheme features lower power consumption, smaller compensation error, and a lower or comparable area overhead, while allowing compensation to be accomplished within the same clock cycle of skew or duty-cycle variation.
['Cecilia Metra', 'Martin Omana', 'T. M. Mak', 'S. Tarn']
Novel compensation scheme for local clocks of high performance microprocessors