The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a fine cost-performance ratio comparator design. Based on modified 1's complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay. Post-layout simulations based on TSMC 0.6/spl mu/m 1P3M CMOS process has completed. It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 4.2ns.
['Shun-Wen Cheng']
A high-speed magnitude comparator with small transistor count