This paper provides a comprehensive symbol synchronization architecture for deployment in configurable digital receivers. While this is a well researched topic for static symbol rate conditions, significant work remains to be done in determining how to best implement variable data rates and training sequences while maintaining functionality. The synchronizer architecture is a modified version of the basic analog architecture for DSSS synchronizers making it applicable to both wideband and narrowband signals. A known training sequence is received and synchronized to within a half chip accuracy by delaying the generated sequence by half of a chip every sequence period and comparing the correlation to a set threshold. A delay-locked loop (DLL) uses the difference between early and late correlations to drive fine synchronization process. This process is made configurable with the knowledge of the number of samples per symbol, training sequence, sequence length, data rate, and coarse correlation threshold.
['W.J. Barnes', 'Yahia Tachwali', 'Hakki H. Refai']
A Configurable Symbol Synchronizer for Digital Systems