We present a new scan built-in self-test (BIST) approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test, and it is especially suitable for faults that are detected by a relatively small number of pseudorandom test patterns. Two multiple-input signature registers are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and fault-free intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We propose a signature-analysis method based on overlapping sections and the principle of superposition to effectively prune the candidate set. We present analytical results to determine an appropriate interval length and the degree of overlap, as well as upper and lower bounds on the size of S. We also determine a lower bound on the number of true failing vectors through a simple graph model. Finally, we present experimental results for the ISCAS'89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.
['Chunsheng Liu', 'Krishnendu Chakrabarty']
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment