We propose a power-driven flip-flop (FF) merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption while controlling the switching power of the nets connected to the FFs by selectively merging FFs into multibit FFs and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the switching capacitance of clock network by 36%-43% after gated clock tree synthesis. Finally, the total switching capacitance of clock network and nets connected to the FFs is reduced by 24%-29%.
['Shao-Huan Wang', 'Yu-Yi Liang', 'Tien-Yu Kuo', 'Wai-Kei Mak']
Power-Driven Flip-Flop Merging and Relocation