AMD's 6th generation “Carrizo” APU, targeted at 12–35 W mobile computing form factors, contains 3.1 billion transistors, occupies 250.04 mm  $^{2}$   and is implemented in a 28 nm HKMG planar dual-oxide FET technology with 12 metal layers. The design achieves a 29% improvement in transistor density compared to the 5th generation “Kaveri” APU, also a 28 nm design, and implements several power management features resulting in area and power improvements similar to a technology shrink. Increased power density makes meeting the thermal limits required for reliability and power distribution to the APU's processors substantial design challenges. Pre-silicon thermal analysis is used to understand and take advantage of thermal gradients. Adaptive voltage-frequency scaling in the processor core as well as wordline and bitline assist techniques in the L2 cache enable lower minimum voltage requirements.
['Benjamin Munger', 'David Akeson', 'Srikanth Arekapudi', 'Tom Burd', 'Harry R. Fair', 'Jim Farrell', 'Dave Johnson', 'Guhan Krishnan', 'Hugh McIntyre', 'Edward McLellan', 'Samuel Naffziger', 'Russell Schreiber', 'Sriram Sundaram', 'Jonathan White', 'Kathryn Wilcox']
Carrizo: A High Performance, Energy Efficient 28 nm APU