Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. Unfortunately, a growing amount of leakage on each new process is distorting these low yield analysis (LYA) testmode l-V curves, making it increasingly difficult to find and differentiate defects. The goal of This work is to discuss the simulation and silicon results of a concept on-die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.
['Benjamin M. Mauck', 'Vishnumohan Ravichandran', 'Usman Azeez Mughal']
A design for test technique for parametric analysis of SRAM: on-die low yield analysis