A major problem facing the computer and semiconductor industries is the increasing amount of CMOS process variability. Variability in low-level circuit parameters, such as transistor gate length and gate oxide thickness, complicates system design by introducing uncertainty about how a fabricated system will perform. Although a circuit or chip is designed to run at a nominal clock frequency, the fabricated implementation may vary far from this expected performance. We have developed three architectural techniques for mitigating the impact of process variability. All three of our approaches enable us to aggressively clock the processor with only minor degradation in IPC (instructions per cycle), thus achieving an overall performance improvement. Our work combines several ideas prefetching, LO caching, and criticality that were previously developed for other purposes. Our contributions are using and combining these ideas to overcome the effects of process variability.
['Bogdan F. Romanescu', 'Michael E. Bauer', 'Daniel J. Sorin', 'Sule Ozev']
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation