Threshold logic gates (TLG) are prone to manufacturing defects that impact weight values which inadvertently affect the functionality of the gate. A method is presented for the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extend. A novel solution is presented for the problem of identifying a fault tolerant k-input TLG for any value of k
['Manoj Kumar Goparaju', 'Spyros Tragoudas']
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations