For H.264/AVC decoder system, the motion compensation bandwidth comes from two parts, the reference data loading bandwidth and the equivalent bandwidth from DRAM access overhead latency. In this paper, a bandwidth-efficient cache-based MC architecture is proposed. It exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared to conventional scheme. To reduce the equivalent bandwidth from DRAM access overhead latency, the DRAM-friendly data mapping and access control scheme are proposed. They can reduce averagely 89.8% of equivalent DRAM access overhead bandwidth. The average MC burst length can be improved to 9.59 words/burst. The total bandwidth reduction can be up to 32∼71% compared to previous works.
['Tzu-Der Chuang', 'Lo-Mei Chang', 'Tsai-Wei Chiu', 'Yi-Hau Chen', 'Liang-Gee Chen']
Bandwidth-efficient cache-based motion compensation architecture with DRAM-friendly data access control