In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy. >
['Claude Thibeault', 'Yvon Savaria', 'J.L. Houle']
Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits