A 25Gb/s silicon photonics receiver comprising an Electronic Integrated Circuit and a Photonic Integrated Circuit fabricated in 65nm CMOS and in PIC25G technologies respectively is presented. The two chips are 3D-integrated using copper pillars. The front-end amplifier introduces low-noise techniques, realizing record-low input-referred noise current of 0.91pArms, leading to the highest sensitivity (OMA = −11.3dBm) among 25Gb/s silicon photonics receivers reported to date.
['Dan Li', 'Gabriele Minoia', 'Matteo Repossi', 'Daniele Baldi', 'Andrea Ghilioni', 'Enrico Temporiti', 'Francesco Svelto']
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links