The integer, floating-point, and on-chip memory subsystems of the Motorola 68040 microprocessor operate in parallel to achieve four times the performance of a 68020 microprocessor and ten times the performance of a 68882 floating-point coprocessor. The integer and floating-point units are described in terms of their performance, internal architecture, and methods used to obtain this performance. The 68040 integer unit (IU) is optimized to execute the most common instructions in a single cycle while maintaining user code compatibly with the 68000 family. To increase performance, the 68040 reduces both the number of arithmetic logic unit (ALU) cycles per instruction (CPI) and the ALU cycle time. The 68040 has a six-stage pipe consisting of an instruction prefetch stage, a program counter calculation and decode stage, an effective address calculation stage for operands, a data execute stage, and a write-back stage. The 68040 floating-point unit (FPU) conforms to the IEEE 754 floating-point standard via a software envelope. >
['Bill Ledbetter', 'Ralph McGarity', 'Eric E. Quintana', 'Russel A. Reininger']
The 68040 integer and floating-point units