This paper discusses a two-stage low noise amplifier (LNA) implemented in a 45nm CMOS SOI process that operates between 43 and 53 GHz. The LNA stages are based on a cascode amplifier with simultaneous noise and input power matching. The LNA exhibits a minimum noise figure (NF) of 2.9 dB at 47 GHz and measured gain of 18.5 dB at 49 GHz. The output P 1dB  compression power is 3 dBm and saturation output power is 7 dBm to reach a peak efficiency of 22%. The measured OIP3 is 14 dBm. The LNA occupies an area of 0.35mm 2  with pads and consumes 19 mA from 1.2 V supply. The results present the lowest noise figure for a silicon-based millimeter-wave LNA.
['Mehmet Parlak', 'James F. Buckwalter']
A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA