In this paper, a CMOS constant current reference over PVT (process, voltage and temperature) variations is presented. The drain current of a MOS device gives the reference current, which is compensated for process variations by exploiting the physical relationship between K'(/spl mu/C/sub ox/) and V/sub T/ across various process corners. It is also compensated for power supply and temperature variations by a PTAT voltage reference, which aids in the generation of the reference current. In order to prove the proposed concept, simulation results from 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm CMOS processes are presented.
['Susanta Sengupta', 'Kanan Saurabh', 'Phillip E. Allen']
A process, voltage, and temperature compensated CMOS constant current reference