The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.
['Yi-Shing Chang', 'Sreejit Chakravarty', 'Hiep Hoang', 'Nick Thorpe', 'Khen Wee']
Transition tests for high performance microprocessors