This paper presents a set of tools for generation, simulation, evaluation and synthesis of VHDL models of test logic for macrocell based embedded microcontroller based systems. The generated models are described at behavioural level so they fit with system descriptions suited for fast simulation. An IEEE 1149.1 boundary scan implementation is used, providing manufacturing test, online test and monitoring capabilities.
['E. de la Torre', 'J. Calvo', 'Javier Uceda']
Model generation of test logic for macrocell based designs