This paper presents a new design for SoC clocking based on open-loop frequency multiplication. The architecture, fully implemented in 28nm FD-SOI standard cells, achieves frequency tracking within one input reference period making it a promising candidate for Dynamic Voltage and Frequency Scaling (DVFS) schemes. A calibration scheme is implemented for wide voltage range (0.6–1.2V) operation and to offset P&R and variability induced mismatch. Measurements at 0.6V (0.8/0.4V FBB) show a Fmax of 93MHz with a power of 2.91mW/MHz and a jitter of 2.7 % UI.
['Martin Cochet', 'Sylvain Clerc', 'Mehdi Naceur', 'Pierre Schamberger', 'Damien Croain', 'Jean-Luc Autran', 'Philippe Roche']
A 28nm FD-SOI standard cell 0.6–1.2V open-loop frequency multiplier for low power SoC clocking