This work presents a low-power 50% duty cycle corrector. A single-ended structure is adopted. The gain-boosting charge pump raises the loop performance and decreases the voltage ripples for increasing accuracy. The input duty range and operational frequency range are increased. The parameters of the design are optimized by loop analysis. A test chip is implemented in a 0.18 mum CMOS process. It's successfully verified to obtain 50% output duty from 20 MHz to 2.5 GHz with wide input duty cycle range. The power consumption is 0.36 mW and measured jitter is 18.4 ps at 1 GHz.
['Hong-Yi Huang', 'Chia-Ming Liang', 'Shi-Jia Sun']
Low-power 50% duty cycle corrector