This paper presents a parameterized router design which can be applied to build large network-on-chips (NoCs) based on a Perfect Recursive Diagonal Torus (PKDT) or mesh/torus topology. In specific, the router is designed to support two routing algorithms (conventional vector routing and a newly proposed Johnson coded vector routing) and wormhole switching. Along these lines, special considerations for the router design are given to different design options concerning scheduling, buffering strategy, and flow control. Correspondingly, the router is partitioned into four components (input channel module, output channel module, crossbar switch, and scheduler) organized to form a three-stage pipeline, and their Verilog models are designed and implemented in a modular fashion with key parameters specified upon instantiations. A 4times4 PRDT-based NoC incorporating multiple copies of the proposed router design is synthesized using TSMC 0.18 mum CMOS technology.
['Shankar Neelkrishnan', 'Mei Yang', 'Yingtao Jiang', 'Lei Zhang', 'Yulu Yang', 'Enyue Lu', 'Xiaochun Yun']
Design and Implementation of a Parameterized NoC Router and its Application to Build PRDT-Based NoCs