This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance, routability, and ease-of-use, it supports variable-granularity logic blocks, dedicated wide multiplexers, and variable-length bypassing interconnects with a symmetrical structure. Due to its many unconventional architectural features, the amorphous FPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new placement algorithm and a modified delay-based routing procedure. It is shown that, on average, an FPGA with the amorphous architecture can achieve a 1.35 times improvement in logic density, 9% improvement in average net delay, and 4% improvement in the critical-path delay for the largest 20 MCNC benchmark circuits over an island-style baseline
['Mingjie Lin']
The amorphous FPGA architecture