This paper presents and analyzes a phase-locked loop (PLL) based on digital signal processing (DSP) and random sampling (RS). Traditional DSP techniques based on uniform sampling require sampling at more than twice the PLL frequency to avoid spectrum aliasing. This requirement makes difficult the implementation of high-frequency software-based PLLs. RS techniques allow significantly reducing the sampling speed requirements without aliasing effects. Lower speed requirements in the analog-to-digital converter (ADC) and the processing device enable the implementation of software PLLs for much higher frequencies than traditional techniques. The proposed PLL is mathematically analyzed to describe its operation and characterize its performance. A field-programmable gate array (FPGA)-based PLL prototype is presented to validate the theoretical analysis.
['Maximiliano O. Sonnaillon', 'Raúl Urteaga', 'F. Bonetto']
Software PLL Based on Random Sampling