In this brief, a frequency-to-current conversion-based fractional frequency synthesizer is implemented in 32-nm technology utilizing a high-density deep trench capacitor. The technique proposed here can replace the use of multiple crystal oscillators or a phase-locked loop for medium accuracy clock generation with very low chip area and power consumption. In addition to exploiting the inherently low variation of capacitors as compared to that of transistors, the proposed circuit generates an output frequency proportional to the capacitor ratio, canceling out any small process-voltage-temperature (PVT) dependences of the capacitor. The performance of the fractional synthesizer is verified from chip measurement results. An output frequency range of 16–156 MHz is covered with a frequency resolution of 0.8 MHz using a 4-MHz reference clock. The total area of the frequency synthesizer core is only 0.0054 mm 2 , and it consumes 116    $\mu\mbox{W}$   of power from a 0.9-V supply while generating an output frequency of 48 MHz. The output frequency variation is ±0.14% at 48 MHz for a temperature sweep from −40 °C to 90 °C. Periodic jitter measured from an on-chip high-resolution jitter measurement circuit is 115 ps (rms) at 76 MHz.
['Somnath Kundu', 'Chris H. Kim']
A 0.0054-mm 2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor