Rapid advances of silicon and parallel processing technologies allow the building of multiprocessor systems-on-chip (MPSoCs). Cache coherency problem becomes one of the major design issues to improve the performance of multiprocessor. We first realize a directory based cache coherency scheme of Network on Chip (NoC) based MPSOC implemented on FPGA using the industrial standard protocol of OCP-IP. In this paper we present the system architecture and implementation results which shows that NoC based coherency system is well scalable. JTAG and PCI based debug system are developed for visualizing the application execution of our NoC based MPSoC cache coherency system.
['Omar Hammami', 'Xinyu Li']
NOC based MPSOC directory based cache coherency with OCP-IP protocol