RRAM-based memory is a promising emerging technology for both on-chip and stand-alone non-volatile data storage in advanced technologies. In addition to its small dimensions, the RRAM device has many technological advantages including its low-programming voltages, high speed, low power, CMOS-compatible fabrication process, and potentially monolithic 3D integration. However, one of the critical challenges for RRAM technology is the reliability concerns due to retention and endurance failures. In this paper, we propose a novel Refresh circuit for 1T1R RRAM array which detects and distinguishes soft and hard errors from retention and endurance failures, as well as corrects the soft errors through refreshing. Using the  HfO 2 /Hf  RRAM array, our simulation results show that the proposed solution increases the resilience to soft-error of an 8Gb RRAM-based memory by 80% with a small penalty on the energy and delay of the Read operations (6% and 0.4% respectively). The proposed methodology can be used for other RRAM arrays with minor modifications to the design parameters depending on the characteristics of RRAM cell.
['Amr M.S. Tosson', 'Mohab Anis', 'Lan Wei']
RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO 2 /Hf 1T1R RRAM Memory Cell