The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its H-tree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance.
['Xu Zhang', 'Xiaohong Jiang', 'Susumu Horiguchi']
A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects