This paper presents a reconfigurable Viterbi fabric with efficient track-back unit in a system on chip device. The proposed reconfigurable fabric can support Viterbi implementations with constraint lengths ranging from 3 to 9, and code rates in the range 1/2-1/3. Our results illustrate that the proposed architecture has superior power consumption and throughput characteristics compared with a generic field programmable gate array (FPGA) and a digital signal processor (DSP), respectively.
['Cheng Zhan', 'Sami Khawam', 'T. Arslan', 'Lord Lindsay']
Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric