There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate these effects. These techniques do not scale very well. Protection methods use capacitors in SRAM cells to absorb the excessive charge. Although they provide sufficient protection, they affect adversely the write time.
['Yuriy Shiyanovskii', 'Francis G. Wolff', 'Christos A. Papachristou']
SRAM Cell Design Protected from SEU Upsets