State-of-the-art speech recognition, speech analysis as well as music modeling have approached Mel-Frequency Cepstral Coefficient (MFCC) and confirmed great performance in comparison to other feature extractions. Based on obtained software performance, a wide range of hardware designs are applied to highly increasing integrated systems achieving real-time performance and ability of mobility. Nevertheless, most hardware approaches witnessing certain configurations have experienced limitation of functions due to fixed-point format, strict silicon requirements or exact applications, which is reasonable for low ability of reusing and high cost of product. As regards MFCC method, there are various concerning parameters such as number of samples, range of filter bands, Fast Fourier Transform (FFT) number, number of cepstrums or even different level of delta coefficients, which significantly affect final performance of entire applications. As a result, a dynamic ASIC-based MFCC hardware architecture is proposed in this paper in order to meet real-time system requiring high performance as well as confirm superiorities regarding to ability of reconfiguration feasibly through an Advance High-performance Bus (AHB) interface in chip level instead of modifying at Register Transfer Level (RTL) in developed duration. Besides, have not only experiments on 130nm technology with full ASIC design flow witnessed high frequency at 500MHz but applying IEEE 754 floating-point format has also confirmed great accuracy between hardware design and software design, which apply in certain application towards Vietnam automatic speech recognition (ASR).
['Tam Chi Nguyen', 'Lam Dang Pham', 'Hieu Minh Nguyen', 'Bao Gia Bui', 'Dat Thanh Ngo', 'Trang Hoang']
A High Performance Dynamic ASIC-Based Audio Signal Feature Extraction (MFCC)