This paper proposes a low power 10-bit single-slope analog-to-digital converter (SS-ADC) for CMOS image sensors (CISs) with a column-parallel readout structure. The power consumption of the proposed SS-ADC is reduced by using a power gating scheme for the comparator and multi-clocks having different frequencies. The proposed SS-ADC was designed using a 0.13μm CIS process technology. The simulation results show that the power consumption of the proposed SS-ADC is 9.7 μW, which is 59.4 % less than that of the conventional SS-ADC.
['Byoung-Kwan Jeon', 'Seong-Kwan Hong', 'Oh-Kyong Kwon']
A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors