Real-time, low-latency, image processing with high throughput is vital for many time-critical applications in fields such as medical imaging, robotics, and wearable computers. Traditionally, FPGAs have often been employed to meet these requirements. However, due to the productivity challenges, using FPGAs may not be viable in some cases. Alternatively, the typical approach of processing an image on a CPU device at a frame level increases the processing latency of the computer-vision system. In this paper, we explore the feasibility of processing an input image at a sub-frame level on a multi-core SoC device, the 66AK2H12 from TI. Using sub-frame processing, we optimize and evaluate the performance of four kernels commonly used in image-processing pipelines. Our results show, for all four kernels in our study, that real-time, low-latency image processing with high throughput for HD-resolution images can be achieved using the multiple DSP cores available in the 66AK2H12 device.
['Barath Ramesh', 'Alan D. George', 'Herman Lam']
Real-time, low-latency image processing with high throughput on a multi-core SoC