In this paper we propose an innovative three-layered 3-D IC structure with unequal die areas. It provides flexibility to a circuit block at the bottom or top layer to simultaneously connect to blocks assigned to other layers. Previously with regular structure, only a block at the middle layer used to be provided with this advantage. Based on the planned structure, a partitioning and layer assignment algorithm is developed that plans (or transforms) a standard GSRC benchmark netlist into the proposed 3-D structure. Experiments are conducted with Python using this algorithm to show reduced effective area, number of TSVs and CPU execution times. Comparative results on TSV count are found to be better over many prior techniques.
['Arko Dutt', 'Pranab Roy', 'Hafizur Rahaman']
TSV-aware 3-D IC structural planning with irregular die-size