This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of memories with various specifications, fail patterns and test algorithms. The proposed method has been implemented in 0.18 /spl mu/ CMOS IC.
['J. Chen', 'Janusz Rajski', 'Jitendra Khare', 'O. Kebichi', 'Wojciech Maly']
Enabling embedded memory diagnosis via test response compression