In this paper we present several algorithms used to construct a tool that automatically optimizes static dataflow graphs for the purpose of high level hardware synthesis. Our target is to automatically merge multiple dataflow graphs in order to create a single structure implementing all distinct operations with minimal area overhead by time-slicing hardware resources. We show that a combination of dedicated optimizations and a simple greedy approach for graph merging reduces the overall area by up to 4x compared to a naive hardware implementation.
['Nils Voss', 'Stephen Girdlestone', 'Oskar Mencer', 'Georgi Gaydadjiev']
Automated dataflow graph merging