Numerical analysis on real numbers is performed using either pointwise arithmetic or interval arithmetic. Today, interval analysis is a mature discipline and finds use not only in error analysis but also control applications such as robotics. The interval arithmetic hardware architecture proposed in the work [W. Edmonson, R. Gupte, J. Gianchandani, S. Ocloo, W. Alexander, Interval arithmetic logic unit for signal processing and control applications, Workshop on Reliable Engineering Computing, Savannah, GA, USA, 2006] for Digital Signal Processors (DSP) is prone to unreliability owing to overflow errors resulting from the small dynamic range offered by fixed point computations. In this paper, we present a solution to this problem in the form of a fixed point interval ALU that utilizes the concept of Block Floating Point (BFP) presented in [K. Kalliojarvi, J. Astola, [Roundoff errors in block-floating-point systems, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 44, pp. 783–790, 1996] to attain a higher dynamic range for interval as well as point-wise computations. We add block floating point support to the ALU in the form of special instructions such as Exponent Detection and Normalization that aid the change of the dynamic range of the input. We also provide additional hardware to perform Conditional Block Floating-point Scaling (CBFS) on the output endpoints of the interval result. We explore the design space across varying pipeline depths for best throughput which is characterized as the highest number of output samples processed per second. Our results show that the four-stage highly-pipelined architecture provides the highest throughput of about 86.1 Msamples/sec for interval operations.
['Sandeep Hattangady', 'William W. Edmonson', 'Winser E. Alexander']
Block Floating Point Interval ALU for Digital Signal Processing