Classical dimensional scaling faces challenges from growing on-chip interconnect time delays, and escalating lithography costs and layout limitations. In this paper, we present practical integration schemes for developing cost-efficient 3D ICs in a monolithic fashion, which employ fully depleted transistor channels and laser annealing to achieve sharper junction definition.
['Bipin Rajendran', 'Albert K. Henning', 'Brian Cronquist', 'Zvi Or-Bach']
Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC