Cost has been a major driving force in the development of the flash memory technology, but has also introduced serious challenges on reliability and performance for future products. In this work, we propose a commitment-based management strategy to resolve the reliability problem of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of multi-level-cell flash memory chips.
['Yuan-Hao Chang', 'Tei-Wei Kuo']
A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems