This paper describes a proposed approach to optimise cell library logic functions for improved performance when future-generation transistor models are used. A multi-objective Genetic Algorithm is used to determine optimal values for transistor widths and supply voltages, utilising multiple supply rails within each cell. Circuits are assessed for their area, power consumption, worst-case delay, and balance of switching delay. The results suggest that this method of optimisation can produce circuits which offer improvements in variability tolerance whilst matching the delay and power-consumption characteristics of conventional designs.
['James A. Hilder', 'James Alfred Walker', 'Andy M. Tyrrell']
Optimisation of variability tolerant logic cells using multiple voltage supplies