The discrete cosine transform (DCT) is a Fourier related transform which is widely used in digital signal processing specially for signal compression due to its capability of energy compaction and because it also approaches the statistically optimal transform. Implementing the DCT in an ASIC is a design solution that meets the real-time processing requirements but it lacks flexibility. Implementation on FPGAs is a more flexible solution that also achieves the real-time requirements. This paper shows the implementation of a recursive algorithm to compute the fast cosine transform for variable-length sequences, into a Xilinx reg  Spartan trade -3 XC3S200 FPGA. The VHDL core was initially developed for a 1024-point DCT, however, due to the utilized structure, it was later modified to compute N-point DCT, being N a power of 2
['U.S. Mendoza-Camarena', 'R. de J. Romero-Troncoso']
VHDL Core for the Computation of the One-Dimensional Discrete Cosine Transform