There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients HOG algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328i¾?fps which represents a 146i¾?% speed improvement over the original realization and a tenfold reduction in energy.
['Colm Kelly', 'Fahad Manzoor Siddiqui', 'Burak Bardak', 'Yun Wu', 'Roger F. Woods', 'Karen Rafferty']
FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG