Spin-based memory devices offer multiple benefits, like, zero standby power, fast operation speed and high write endurance. Besides for storage applications, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic operations, especially in the context of in-memory computing and neuromorphic architectures. In this paper, we propose spin-based design of encoder/decoder which can be used to reduce the power consumption of interconnect architectures in digital systems. Encoding schemes provide a useful way to reduce the power consumption in interconnects and buses. Realizing these schemes require the use of encoders and decoders. Our proposed design can be reconfigured to implement different encoding schemes. Also, the same design can be reconfigured to function either as encoder or as decoder. Our simulations show a 49.65% reduction in dynamic power consumption for 6-bit proposed reconfigurable design when compared with CMOS-only implementation. Compared to the CMOS implementations, the RM-based non-reconfigurable designs show improvements upto 1.8X and 17.34X in leakage and dynamic power respectively.
['Suman Deb', 'Leibin Nit', 'Hao Yu', 'Anupam Chattopadhyay']
Racetrack memory-based encoder/decoder for low-power interconnect architectures