In this paper, a framework of designing a low-error and power-efficient two's-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product is proposed. The design methodology of the framework involving four steps results in one better error-compensation bias. The better error-compensation bias can be mapped to a simple low-error fixed-width Booth multiplier with a little penalty in power consumption. For the benchmark of 8/spl times/8 multipliers, the simulation results show that a reduction of 82.04% average error compared to that using the direct-truncated fixed-width Booth multiplier can be obtained. Moreover, the power consumption can be reduced by 40.68% compared to that of full-precision Booth multiplier design.
['Min An Song', 'Lan-Da Van', 'Chih-Chyau Yang', 'Shih-Chieh Chiu', 'Sy-Yen Kuo']
A framework for the design of error-aware power-efficient fixed-width Booth multipliers