Dynamic scheduling algorithms have been successfully used for parallel computations of nested loops in traditional parallel computers and clusters. In this paper we propose a new architecture, implementing a coarse grain dynamic loop scheduling, suitable for reconfigurable hardware platforms. We use an analytical model and a case study to evaluate the performance of the proposed architecture. This approach makes efficient memory and processing elements use and thus gives better results than previous approaches.
['Ioannis Riakiotakis', 'George K. Papakonstantinou', 'Anthony T. Chronopoulos']
Implementation of dynamic loop scheduling in reconfigurable platforms