A flexible and all digital CMOS phase interpolator is proposed in this paper suitable for high speed multi-Gigabit serial transceivers applications. The topology is constructed by a parallel combination of identical CMOS inverters grouped in two segments, a phase multiplexer and a capacitive tank. The proposed phase interpolator is quite simple and generic and can be easily fitted in a clock and data recovery system. The circuit is designed in a 65nm CMOS technology node under 1V supply voltage. The circuit robustness is verified through its application to the most updated M-PHY serial interface standard requirements supporting multiple data rates of 1.5/3/6Gbps. It is capable to deliver two orthogonal (I/Q) output phases with 5-bit phase resolution resulting in 32 equally spaced discrete steps of 11.25°. Post-layout simulation results confirm less than 1.7° worst case phase step error, settling time less than 2 clock cycles and power consumption 0.6mW at 6Gbps.
['Andreas Tsimpos', 'Andreas Christos Demartinos', 'George Souliotis', 'Spiros Vlassis']
Multi-rate phase interpolator for high speed serial interfaces