HyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced.This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is a popular bus protocol in SOC architectures. Furthermore, this HyperTransport interface provides dedicated hardware support for cache coherence protocol. Through this HyperTransport interface, Godson-3A multi-core processor chips can be interconnected together to forma 4-16 core CC-NUMA system or a large-scale NCCNUMA system. The verification of the HyperTransport interface is also presented.
['Huandong Wang', 'Dan Tang', 'Xiang Gao', 'Yunji Chen']
An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP