Clock overlap is an important issue in the design of sequential circuits and is typically avoided. In this paper we present a new power-efficient edge-triggered D flip-flop in which we have benefited from the overlap period of the clock signal. The design procedure of the proposed D flip-flop is presented. The performance of the flip-flop is compared with several state of the art flip-flops in a shift register and a pipeline adder in 0.18?m CMOS technology. The proposed flip-flop has the lowest power-delay-product and consumes less area compared to others.
['O. Sarbishei', 'Mohammad Maymandi-Nejad']
Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops