We address the problem of designing switch modules for FPGAs and FPICs to maximize routability under area and delay constraints. The switch module design problem is closely related to two-dimensional segmentation design for FPGAs and FPICs. We study the properties of switch modules and present an algorithm for switch module design. We also present an algorithm to analyze the routability of a given switch module.
['Kai Zhu', 'D. F. Wong', 'Yao- Wen Chang']
Switch module design with application to two-dimensional segmentation design