A linear time-invariant phase-domain Phase-Locked Loop (PLL) model including the effects of thermal and flicker (1/f) noise sources is devised. Phase noise from the frequency dividers, loop oscillators, and oscillator buffering is modeled. Flicker noise is shown to be of major significance for the accurate characterization of DVB-T/H terminals integrated in contemporary CMOS processes. For obtaining an optimal voltage-controlled oscillator (VCO) in a PLL loop for DVB-T/H receivers, a phase noise trade-off for the VCO thermal and flicker noise contributions is derived. Link-level performance evaluation is carried out to validate the stipulated trade-off.
['Nikolay N. Tchamov', 'Jukka Rinne', 'Ville Syrjala', 'Mikko Valkama', 'Yaning Zou', 'Markku Renfors']
VCO phase noise trade-offs in PLL design for DVB-T/H receivers