We present efficient architectures for the discrete Hadamard transform based on two techniques, namely offset binary coding and ROM decomposition. The proposed architectures do not require large size ROMs in comparison to a recently proposed solution. Results of FPGA implementation show that the solutions have a low slice-delay product.
['B.W.Sandeep Kumar', 'Vikramkumar Pudi', 'K. Sridharan']
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition