Instead of a single die per chip (package) multiple dies stacked vertically (3D) and placed on an interposer (2.5D), is emerging as the building block for the future in both mobile and high-performance applications. We identify that bandwidth, energy per bit, and the ability to support a large amount of memory, are the key requirements of the inter-die Network on Chip (NoC). We propose to use an interposer with optical interconnections exploiting AWGR (Arrayed Waveguide Grating Router) wavelength routing to realize a 16x16 photonic NoC with a bisection bandwidth of 16 Tb/s. We propose a baseline network, which consumes 2.81 pJ/bit assuming 100% utilization. We show that the power is dominated by the electro-optical interface of the transmitter, which can be reduced by a more aggressive design that improves the energy per bit to 0.437 pJ/bit at 100% utilization. The networks exhibit very low latency as they are based on an optical crossbar topology and are scalable to multiple chips to support 1 TB of memory or more to meet the requirements of Exascale computing.
['Paolo Grani', 'Roberto Proietti', 'Venkatesh Akella', 'S. J. Ben Yoo']
Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip