Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design has increased exponentially. While those challenges carry across the spectrum of the manufacturing stages we believe it is the responsibility and the goal of the EDA industry to deal with those issues as thoroughly and as seamlessly as possible to make those challenges transparent to the designer. In this paper we expose and analyze three major DFM challenges: random defects, metal and oxide thickness (z) variation, and printability (x-y) variation. We also briefly go over the solutions EDA tools are offering for dealing with them. The solutions covered are wire spreading and wire widening for random defects, model based dummy fill for thickness variation, and printability solutions for printability variation.
['Charles Chiang', 'Jamil Kawa']
Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation