Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network sizes have increased, the complexity of these techniques has grown as well, particularly in the case of multi-hop networks.   In this paper, we propose an efficient QoS implementation for a single-stage, high-radix switch, which is readily scalable to 64 nodes. In addition to best effort and guaranteed throughput services, we implement a guaranteed latency traffic class with a latency bound. Our implementation allows systems significantly larger than most current multi-core chips to be implemented without the need for difficult and complex multi-hop QoS.
['Nilmini Abeyratne', 'Supreet Jeloka', 'Yiping Kang', 'David Blaauw', 'Ronald G. Dreslinski', 'Reetuparna Das', 'Trevor N. Mudge']
Quality-of-Service for a High-Radix Switch