As LSI manufacturing technology improves and the time-to-market for products becomes stricter, more and more circuit designs have multiple clock domains due to concerns such as design re-use, power reduction and temperature control. It is not uncommon for these designs to have multi-cycle paths which are untestable. The rapid identification of these untestable paths reduces test generation time as well as over-testing due to design for testability (DFT). For current and future designs, this has already become impractical at the gate-level. This paper presents a method to identify nonrobust untestable multi-cycle paths at the register transfer level (RTL) and the details in a case study of a benchmark circuit.
['Thomas Edison Yu', 'Tomokazu Yoneda', 'Satoshi Ohtake', 'Hideo Fujiwara']
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths