The move to low-k1 lithography makes it increasingly difficult to print feature sizes which are a small fraction of the wavelength of light. Manufacturing processes currently treat a target layout as a fixed requirement for lithography. However, in reality layout features may vary within certain bounds without violating design constraints. The knowledge of such tolerances, coupled with models for process variability, can help improve the manufacturability of layout features while still meeting design requirements.   In this paper, we propose a methodology to convert electrical slack in a design to  shape slack  or tolerances on individual layout shapes using a two-phase approach. In the first step, we redistribute delay slack to generate delay bounds on individual cells using linear programming. In the second phase, which is solved as a quadratic program, we convert these delay bounds to shape tolerances to maximize the process window of each shape. The shape tolerances produced by our methodology can be used within a process-window optical proximity correction (PWOPC) flow to reduce delay errors arising from variations in the lithographic process. Our experiments on 45nm SOI cells using accurate process models show that the use of our shape slack generation in conjunction with PWOPC reduces delay errors from 3.6% to 1.4%, on average, compared to the simplistic way of tolerance band generation.
['Shayak Banerjee', 'Kanak B. Agarwal', 'Chin Ngai Sze', 'Sani R. Nassif', 'Michael Orshansky']
A methodology for propagating design tolerances to shape tolerances for use in manufacturing