This work presents an architectural solution for the IEEE 802.11a MAC layer on-chip implementation. The complete implementation flow is presented as well as some unique solutions implemented using an architecture that exploits dedicated hardware for timing critical tasks. The system is completely integrated into a single chip and the implementation results are presented.
['Goran Panic', 'Daniel Dietterle', 'Zoran Stamenkovic', 'Klaus Tittelbach-Helmrich']
A system-on-chip implementation of the IEEE 802.11a MAC layer