In this paper, we present a low cost, pipelined FPGA architecture of a Harris Corner Detector. The platform is Altera Cyclone IV on a DE2-115 development board. The pipeline is composed of multiple stages, between which data flows without temporary full-frame buffering. The architecture was tested using a System Verilog test-bench, enveloped by a MATLAB test-bench, to benefit from the latter's image processing capabilities. The accuracy of the results obtained was tested visually and compared with the results of the same algorithm implemented in MATLAB. The results show a balance between resources utilization and timing performance, compared with recent works.
['Hammam Orabi', 'Nasir Shaikh-Husin', 'Usman Ullah Sheikh']
Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications