A design method is presented for testing of analog iterative decoders using digital built-in self-test (BIST). Mixed-signal BIST schemes are often complex and demand larger than acceptable hardware cost. By using a digital BIST scheme, analog iterative decoders can easily be tested in the digital domain. A BIST was designed and simulated for an (8,4,4) extended Hamming decoder using 0.18 /spl mu/m CMOS. It is capable of detecting transistor faults in the decoder. A decoding rate of 444 kbps is achieved. The digital BIST scheme is suitable for any iterative decoder using the sum-product algorithm.
['Mimi Yiu', 'Vincent C. Gaudet', 'Christian Schlegel', 'Chris Winstead']
Digital built-in self-test of CMOS analog iterative decoders