We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of SystemC designs. The core tools are 1) ParSyC, a parser for SystemC designs that has also some synthesis options, 2) CheckSyC, a verification tool for formal equivalence checking, property checking and generating checkers for simulation or synthesis, 3) DeSyC, a tool for automatic debugging and error location in netlists, and 4) ViSyC, a visualization tool for schematic and source code view supporting cross-probing and annotation of simulation and debugging results. The tools fully support hierarchy and interact tightly. Designs can be described at different levels of abstraction.
['Rolf Drechsler', 'G. Fey', 'Christian Genz', 'Daniel Grosse']
SyCE: an integrated environment for system design in SystemC