As chip design complexity scales, completing routes of all nets has become a tough work under limited routing resources and increasing number of design rules. Besides, wirelength and crosstalk greatly affect the chip's performance. This paper presents a novel fine-grain track routing approach to optimize routability and crosstalk. The proposed track router is performed in a GRC-by-GRC fine-grain manner, which, along with efficient cost metrics, significantly improves the QOR in terms of total wirelength and routing completion rate. Heuristic approaches including dummy obstacle insertion and net jogging are proposed to optimize capacitive crosstalk. Experimental results are promising and show 100% routing completion rate with significant reduction of wirelength and total coupling capacitance, as well as no crosstalk violations. 1
['Zhongdong Qi', 'Qiang Zhou', 'Yanming Jia', 'Yici Cai', 'Zhuoyuan Li', 'Hailong Yao']
A novel fine-grain track routing approach for routability and crosstalk optimization