The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip's delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other. >
['Jacob Savir']
AC product defect level and yield loss