We present novel fast parallel multiplier schemes. In contrast to the full adder binary logic based traditional designs, we use (incomplete) large parallel counters and large shift switch compressors, which are built based on shift switch logic, a logic with shift switches as logic elements performing modulo arithmetic operations on (non-binary) state signals. With the unique feature of shift switch logic our parallel multiplier schemes have shown superiority in speed and in area compactness. This is provided through the use of a stage-reduced partial product reduction network, the efficient signal interconnection and the simplified final carry lookahead adder. Compared to the well-known designs, our approach possesses higher regularity and simplicity on circuit structures, characterized by both the recursive shift switch networks which localize the major part of partial product reduction and the deliberated utilization of uneven arrival signals which minimize the delay of the multipliers.
['Rong Lin']
Fast multiplier schemes using large parallel counters and shift switches