SUMMARY An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1 × 1. 4m m2 in a 90 nm CMOS technology.
['Yukio Mitsuyama', 'Kazuma Takahashi', 'Rintaro Imai', 'Masanori Hashimoto', 'Takao Onoye', 'Isao Shirakawa']
Area-Efficient Reconfigurable Architecture for Media Processing