Presents an architecture for the efficient encoding of Reed-Solomon codes, with or without interleaving. This architecture utilizes a clock whose rate is r times the symbol rate, where r is the redundancy of the code. The finite field operations are performed in a sequential manner, requiring only one finite field multiplier and one finite field adder. All memory elements (except one symbol register) are consolidated into a discrete-time delay line, which can be easily implemented with a random access memory. This approach alleviates the clock skew problem and leads to significant hardware savings over the usual parallel approach, when the redundancy and/or interleaving depth are large. The architecture can be easily reconfigured for changes in the generator polynomial of the code, the amount of redundancy, and the interleaving depth. >
['Po Tong', 'Peter A. Ruetz']
Sequential encoding of Reed-Solomon codes using discrete-time delay lines