This paper proposes a novel approximate computing algorithm for the Sum of Absolute Transformed Differences (SATD) to meet energy efficiency in CMOS accelerator circuits. It is based on the pruning of least significant coefficients in the 2-D Hadamard Transform (HT) which is the most compute intensive kernel in the SATD. The SATD is a metric for block matching that is used in video coding standards like the new High Efficiency Video Coding (HEVC). This metric is used to provide better results in mode decision when compared to the Sum of Absolute Differences (SAD) at the expense of larger amount of arithmetic operations as well as higher energy consumption. We present 6 different approximate SATD 4×4 architectures that were synthesized for a 45 nm PDK. Results for the approximate architecture with 10 discarded HT coefficients show energy per operation reduction of 70.7% and BD-PSNR reduction of just −0.008 dB, for a 1080p video sequence.
['Leonardo Bandeira Soares', 'Cláudio Machado Diniz', 'Eduardo A. C. da Costa', 'Sergio Bampi']
A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding