An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140   $\mu$  m   $\times$   170   $\mu$  m.
['Soon-Won Kwon', 'Joon-Yeong Lee', 'Jin-Hee Lee', 'Kwangseok Han', 'Taeho Kim', 'Sangeun Lee', 'Jeong-Sup Lee', 'Taehun Yoon', 'Hyosup Won', 'Jinho Park', 'Hyeon-Min Bae']
An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs