This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of-band phase noise, respectively. To save battery life, dual-step-mixing injection-locked frequency divider (ILFD) enhances locking range for high division ratio. Moreover, tail cross-coupling technique in a QILO helps boost negative transconductance   $({{-g}}_{m})$   of the 60 GHz QILO which allows the use of larger inductance for power reduction. Implemented in 65 nm CMOS, it can cover required channels from 58.32 to 64.80 GHz with quadrature outputs. It consumes 24.2 and 7.8 mW from 20 GHz SS-PLL and QILO, respectively. The proposed synthesizer achieves   $-78.5\; \text{dBc/Hz}$   at 100 kHz offset,   $-122\text{dBc/Hz}$   at 10 MHz offset, and a figure-of-merit (FoM) of   $-236\text{dB}$  .
['Teerachot Siriburanon', 'Satoshi Kondo', 'Makihiko Katsuragi', 'Hanli Liu', 'Kento Kimura', 'Wei Deng', 'Kenichi Okada', 'Akira Matsuzawa']
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad