This paper presents a complete electrical analysis of address decoder delay faults "ADFs" caused by resistive opens in RAMs. A classification between inter and intragate opens is made. A systematic way is introduced to explore the space of possible tests to detect these faults; it is based on generating appropriate sensitizing address transitions and the corresponding sensitizing operation sequences. DFT features are given to facilitate the BIST implementation of the new tests
['Said Hamdioui', 'Zaid Al-Ars', 'A. J. van de Goor']
Opens and Delay Faults in CMOS RAM Address Decoders