Symbol timing recovery is of paramount importance in digital receivers. But instead of expensive heterodyne architectures, direct-conversion solutions are an increasingly attractive alternative, which is mainly due to small package sizes and reduced power consumption. Annoying impairments, introduced by DC offset and IQ mismatch, might be compensated by intelligent DSP techniques. In this context, numerous aspects and issues were investigated in the open literature, typically based on the assumption that the symbol timing has been perfectly established in advance. Motivated by this background, the Cramer-Rao lower bound (CRLB) for symbol timing recovery in direct-conversion receivers is derived in the current paper. This figure represents the theoretical limit of the jitter performance such that different estimator algorithms can be benchmarked with respect to this bound. Due to reasons of mathematical tractability, the focus is on the computation of the modified CRLB, which is in general much easier to analyze than the true bound. Finally, a low-complex estimator is developed, which performs close to the modified bound.
['Wilfried Gappmair', 'Otto Koudelka']
Modified CRLB and low-complex estimator for symbol timing recovery in direct-conversion receivers