This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test pattern generation algorithm show nearly 100% fault coverage for complex arithmetic logic circuits. Moreover we achieved 99.99% fault coverage applying this algorithm with a weighted random pattern generator to the LSIs (100-450 kgates) of Hitachi MP5800 mainframe computer.
['Miyako Tandai', 'Takao Shinsha']
A redundant fault identification algorithm with Exclusive-OR circuit reduction