Scheduling of concurrent processors in a real-time image processing system on FPGA (field programmable gate array) hardware is a not a trivial task. We propose a number of graphical representations for scheduling which were evaluated for use in a visual language for image processing on FPGAs. The proposed representations are illustrated and their strengths and weakness discussed and the reasons for adoption of the state chart notation are given.
['Christopher T. Johnston', 'Paul J. Lyons', 'Donald G. Bailey']
A Visual Notation for Processor and Resource Scheduling