Designs using advanced low power techniques like Multi- Supply Multi-Voltage and Power Shutoff bring with them a new set of challenges that manufacturing test must deal with carefully. These designs have low power components – isolation cells, retention flops, level shifters, power switches, etc., – that must be tested not only structurally but also addressing their behavior across multiple power modes. This paper describes the challenges in testing the key low power components and proposes novel solutions. The defective behavior of state retention logic is modeled to enable fault grading. ATPG modeling of defective behavior of isolation logic and level shifters is described for designs that support multiple supply voltages and power shutoff. The solutions are supported by experimental results on industrial designs.
['Krishna Chakravadhanula', 'Vivek Chickermane', 'Brion L. Keller', 'R Patrick Gallagher', 'Anis Uzzaman']
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs