Frequency analysis using discrete cosine transform is being used in a large variety of algorithms such as image processing algorithms. This paper proposes a new high throughput architecture for the DCT processor. This system has got a 2level architecture which uses parallelism and pipelining and has been synthesized on Xilinx Virtex5 FPGA. Synthesis results show that this system works at 150MHz. Applying DCT on each 8x8 matrix of image take 67 clock pulses. In other words, applying DCT on each pixel takes approximately one clock pulse.
['Azad Fakhari', 'Mahmood Fathy']
A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGA