Signal processing in analog domain is an attractive technique for achieving low-power coherent optical link receivers as opposed to DSP (digital signal processing) based receivers. The linear equalizer is one of the most important building blocks in these receivers. An analog domain equalizer requires wideband delay circuits for providing a constant delay with the desired bandwidth. This paper discusses the delay-bandwidth-area trade-off encountered while designing these delay circuits with low power consumption. A novel topology of a wideband active delay cell for a 100 Gb/s dual-polarization quadrature phase shift keying (DP-QPSK) receivers has been presented. As the delay cell has a 60 GHz bandwidth, several such delay cells can be cascaded to obtain larger delay with an overall acceptable bandwidth (for example, a delay of 100 ps with 20 GHz bandwidth). With this delay circuit designed in a 130 nm BiCMOS technology, we are able to achieve a delay × bandwidth/power product that is about 3 times better than the available state-of-the-art.
['Saurabh R. Anmadwar', 'Nandakumar Nambath', 'Shalabh Gupta']
Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver