As integrated circuit (IC) manufacturing entered the nano-scale era, defect observability has greatly diminished. As a result, test-fail data diagnosis and mining are playing an indispensable role in providing feedback for yield learning. Accurate simulation of defect behavior is vital to this process but, unfortunately, cannot be achieved with simulation at the logic-level alone. This work proposes a framework to enable fast and accurate defect simulation, by making use of existing and well-developed mixed-signal simulation technology (traditionally used for design verification). While previous work has considered this topic before, the innovation here centers on two aspects: (i) accuracy resulting from defect injection taking place at the layout level, (ii) speedup resulting from careful and automatic partitioning of the circuit into digital and analog domains for mixed-signal simulation, and (iii) complete automation that involves defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The mixed-signal framework developed can be applied in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and virtual failure data creation. Experiments demonstrate that the proposed framework is scalable to handle large designs efficiently. A second set of experiments demonstrates how defect localization can be dramatically improved (> 53%) by more accurate defect simulation.
['Wing Chiu Tam', 'Ronald D. Blanton']
SLIDER: A fast and accurate defect simulation framework