This paper presents an approach to using commercial digital signal processors to develop a high performance multiprocessing system for block data processing. We use a restricted dataflow multiprocessor architecture and block data processing to achieve high performance. We call this architecture the Block Data Flow Architecture (BDFA). Block data processing algorithms for many applications have been developed by other researchers. Although many of these algorithms were developed for single processor systems, the algorithms can be mapped onto the BDFA because of its inherent support for block data processing. This paper highlights a few of these algorithms and presents the BDFA as a high performance architecture to implement these algorithms. In addition, we evaluate the potential of using Texas Instruments' TMS320C40 (C40) as a node processor in the BDFA.
['Kenneth N. Ellis', 'Winser E. Alexander']
Block Data Processing Using Commercial Processors