The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in-first-out (FIFO) device. A method to recover the source clock, called synchronous residual time stamp (SRTS), is implemented. The designed AAL1 SAR FPGA is properly tested in a prototype circuit board.
['Yih-chang Lee', 'Tain-Lieng Kao', 'Kou-Tan Wu']
Design of ATM AAL1 SAR for circuit emulation