A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.
['J.S. Matos', 'F.S. Pinto', 'J.M.M. Ferreira']
A boundary scan test controller for hierarchical BIST