This paper describes an effective technique for the optimization of the clock recovery circuit in an all-digital modem for linearly modulated signals. Starting from the concept of prefiltering of the data signal (already pursued by these authors in the context of analog data receivers), it is shown how to design an optimum digital prefilter for the minimization of jitter due to both Gaussian and pattern noise in the closed-loop clock recovery scheme by Gardner (1986). The numerical results of the theoretical analysis, obtained after iterative resolution of a constrained-minimum problem via the Lagrange multiplier method, are checked by simulation and can be nicely justified by the consideration of the frequency response of the optimum prefilter. The key outcome of such an approach is the demonstration of a substantial performance improvement in terms of steady-state clock jitter, even with remarkably simple FIR prefilters with a small number of taps.
["A. D'Andrea", 'Marco Luise']
Optimization of symbol timing recovery for QAM data demodulators