TThe increase of power consumption in recent VLSI chip has led to uneven thermal distribution and high temperature on the chip. This brings inappropriate distribution of wire delay and may adversely effect the behavior of the chip by the increase of clock skew. The rise of local temperature causes the electro migration which brings wire disconnections. Therefore, some module placement methods considering the thermal distribution were proposed so far. However, these conventional methods require much time for obtaining the placement. In this paper, we propose a method to quickly obtain a module placement with good thermal distribution. We confirmed that the proposed method with simulated annealing can obtain good placements in shorter time
['Norihide Okada', 'Chikaaki Kodama', 'Takashi Sato', 'Kunihiro Fujiyoshi']
Thermal Driven Module Placement Using Sequence-pair