This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.
['Ruben Salvador', 'Andres Otero', 'Javier Mora', 'Eduardo de la Torre', 'Teresa Riesgo', 'Lukas Sekanina']
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support