This paper addresses system-level design of time- interleaved analog-to-digital converters (TI-ADCs) for ultra-wide band communications. Design space exploration of a TI successive approximation architecture is performed via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing the main ADC blocks in a 90-nm 1-V CMOS technology. Different speed/resolution scenarios are efficiently investigated and the impact of parallelism on system performance, yield and power consumption is assessed starting from the early design phases, finally enabling the selection of two candidate implementations (a 6-bit 4.6- mW and a 7-bit 8.1-mW ADC targeting 1 GS/s) that effectively trade accuracy for energy efficiency and area.
['Pierluigi Nuzzo', 'Claudio Nani', 'Luca Fanucci', 'Sergio Saponara', 'Geert Van der Plas']
Mixed-signal design space exploration of time-interleaved A/D converters for ultra-wide band applications