A pare to optimal temporal partition methodology was developed for splitting and mapping large data flow graph (DFG) to the coarse-grained reconfigurable architecture (CGRA). A multi-objective genetic algorithm (MOGA) derived from the SPEA-II algorithm was first time introduced to the temporal partition realm for simultaneously optimizing multiple mutually exclusive objectives. Experiments carried out on the ESL (electronic system level) model of the REmus processor show that MOGA based temporal partition algorithms is superior than heuristic algorithm by reducing execution delay 5%-28%, communication overheads 16%-37% without degradation the resource efficiency. Furthermore, comparisons with weight-based multi-objective simulated annealing algorithm show the pare to optimal algorithm can achieve slight better latency objective (3%), while dramatically decrease the communication overheads by at most 21% and the resource efficiency doesn't get worse.
['Weiguang Sheng', 'Weifeng He', 'Jianfei Jiang', 'Zhigang Mao']
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm