This paper proposed a high-radix scalable Montgomery multiplier with the efficient data-path and half latency. By using new algorithm proposed by this paper, it achieves shorter critical path by calculating coefficient q/sub Y/ and q/sub M/ in parallel. The algorithm can also provide half latency by changing pipeline dataflow through operands dynamic extending during calculation. This design can be used to accept any input precision up to the size of the on-chip memory. An ASIC implementation in 0.25 /spl mu/n CMOS technology can perform 1024-bit RSA encryption with 390k bps under 180MHz frequency.
['Yibo Fan', 'Xiaoyang Zeng', 'Yu Yu', 'Gang Wang', 'Qianling Zhang']
A modified high-radix scalable Montgomery multiplier