A technique for improving the linearity of CMOS class-AB power amplifiers (PAs) is introduced. The technique is based on compensating for the voltage-dependent nonlinear gate-source capacitance of the input transistor of the PA. This compensation is achieved through using an NMOS capacitor, i.e., an NMOS transistor with its source and drain shorted, as a predistortion stage. To enhance cancellation of the nonlinearity, body biasing is incorporated as an additional control scheme into the predistortion stage. As a proof-of-concept, a 2.4-GHz class-AB power amplifier with the proposed predistortion stage has been designed and laid out in a 0.13-μm CMOS technology. Post-layout simulation results show that the third-order input-referred intercept point (IIP3) of the designed PA improves by more than 3-dB when the bulk voltage of the predistortion device is biased appropriately. The PA achieves unsaturated output power of +20 dBm while drawing 125 mA from a 1.2 V supply voltage.
['Hooman Rashtian', 'Shahriar Mirabbasi']
Improving linearity in class-AB power amplifiers using a body-biased NMOS predistortion stage