This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (ultra-wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 V supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 times 2 mm 2 .
['Joon Sung Park', 'Young-Gun Pu', 'Young-Shin Kim', 'Chul Nam', 'Kang-Yoon Lee']
A design of sub-band generator for MB-OFDM UWB application in 0.13 μm RF CMOS process