In the VLSI design process, a design implementation often needs to be corrected because of new specifications or design constraint violations. This correction process is referred to as  engineering change (EC) . Usually, an EC problem is resolved by using spare cells, which have been inserted into the unused spaces of a chip. In this paper, we propose an iterative method to generate feasible mapping solutions for an EC problem considering spare cells whose inputs may be tied to  Vdd  or  Gnd , called  constant insertion . Applying constant insertion can increase a cell's flexibility in aspect of functionalities, so far-away spare cells need not be used just for some specific functionality. Our experimental results show that the area in which there are enough spare cells for a mapping solution with constant insertion is only 82% of the area without constant insertion.
['Yu-Min Kuo', 'Ya-Ting Chang', 'Shih-Chieh Chang', 'M. Marek-Sadovvska']
Engineering change using spare cells with constant insertion