Semiconductor supply chain is increasingly getting exposed to Reverse Engineering (RE) of Intellectual Property (IP). Camouflaging of gates are typically employed to hide the gate functionality to prevent RE. Adversaries perform RE by developing custom software to determine test patterns and analyze the outputs. In this paper, we show that RE of camouflaged design can be performed by exploiting the test features of commercial/publicly available Automatic Test Pattern Generation (ATPG) tools. We also propose a controllability/observability and Hamming Distance sensitivity based metric to select target gates for camouflaging. Our simulation shows that the proposed techniques can increase the RE effort significantly by camouflaging small fraction of gates.
['Deepakreddy Vontela', 'Swaroop Ghosh']
Methodologies to exploit ATPG tools for de-camouflaging