The large performance gap between traditional storage and the rest of the memory hierarchy calls for a storage class memory (SCM) to fill the need. Phase change memory (PCM) is an emerging memory candidate for SCM with the advantages of scalability, bit-alterability, non-volatility, and high program speed. Previous publications demonstrated high-density single-level-cell (SLC) PCMs using circuits and architectural techniques for expanding memory capacity, increasing bandwidth, and enabling embedded applications [1–4]. For PCM to be a true contender, a multi-level-cell (MLC) topology with at least a moderate data retention time is required. However, the resistance-drift (R-drift) effect causes cell resistance (RCELL) to increase with time, exceeding the ECC correction ability within hours of being programmed. Conventional R-drift mitigation approaches using reference-cell-based resistance tracking (RCRT) [5] and DRAM-like refresh (DR) [6] are feasible, but at the cost of compromising distinguished PCM traits: random write, low latency, and low power. This paper proposes a resistance drift compensation (RDC) scheme to mitigate against R-drift without such compromises, while minimizing the speed and power consumption penalties. The MLC-PCM fixed-threshold retention (FTR) raw-bit-error-rate (RBER) has been suppressed by over two orders of magnitude, reducing it below practical ECC capability limits.
['Win-San Khwa', 'Meng-Fan Chang', 'Jau-Yi Wu', 'Ming-Hsiu Lee', 'Tzu-Hsiang Su', 'Keng-Hao Yang', 'Tien-Fu Chen', 'Tien-Yen Wang', 'Hsiang-Pang Li', 'Matthew BrightSky', 'SangBum Kim', 'Hsiang-Lam Lung', 'Chung Lam']
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications