Power maskable units have been proposed as a viable solution for preventing side-channel attacks to cryptoprocessors. This paper presents a novel architecture for the implementation of a class of such kinds of units, namely arithmetic components, which find wide usage in cryptographic applications and which are not suitable to traditional masking techniques. Results of extensive exploration and architectural trade-off analysis show the viability of the proposed solution.
['Luca Benini', 'Alberto Macii', 'Enrico Macii', 'Elvira Omerbegovic', 'Massimo Poncino', 'Fabrizio Pro']
A novel architecture for power maskable arithmetic units