In this paper a new, flexible and a very accurate crosstalk fault model is developed which considers the capacitive coupling noise between the aggressor and the victim interconnect in deep sub-micron chips. The proposed crosstalk model is based on the distributed ABCD model of a long on-chip interconnect and takes into account the CMOS driver and receiver parameters of both aggressor and victim interconnects, besides the consideration of usual distributed per-unit-length RLGC parasitic elements and coupling capacitance, and interconnects length. Simulations are all carried out using the Philips CMOS12 (130nm) technology parameters and the model accuracy is found very much close to PSPICE simulation result. The same model can further be utilized to analyze/estimate the influence of interconnect parasitics on various signal integrity losses such as delay, glitch, overshoot, or crosstalk hazards (if any).
['Ajoy Kumar Palit', 'Lei Wu', 'Kishore K. Duganapalli', 'Walter Anheier', 'Juergen Schloeffel']
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips