Rigel is a single-chip accelerator architecture with 1,024 independent processing cores targeted at a broad class of data- and task-parallel computation. This article discusses Rigel's motivation, evaluates its performance scalability as well as power and area requirements, and explores memory systems in the context of 1,024-core single-chip accelerators. The authors also consider future opportunities and challenges for large-scale designs.
['Daniel R. Johnson', 'Matthew R. Johnson', 'John H. Kelm', 'William Tuohy', 'Steven S. Lumetta', 'Sanjay J. Patel']
Rigel: A 1,024-Core Single-Chip Accelerator Architecture