Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as basic operations. Hence, improving the additions characteristics will improve the performance of almost all arithmetic modules. Several HRSD adders have been introduced in literatures. In this paper a new maximally redundant HRSD adder is proposed. This adder is compared to some most efficient HRSD adders previously published. The proposed adder is fabricated using a standard TSMC 65nm CMOS technology at 1volt supply voltage. The adder consumes 2.5% less power than the best previous published HRSD design. These implementations are also synthesized with FPGA flow on Xilinx Virtex2. The experimental result shows 5% and 6% decreases in the area and delay, respectively.
['Somayeh Timarchi', 'Keivan Navi', 'Omid Kavehei']
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation