This paper presents a quarter-rate pseudo-random binary sequence generator (PRBSG) using interleaved half-rate architecture followed by a multiplexer. Existing interleaved architecture can only generate a pseudo-random binary sequence (PRBS) at double the clock rate. In this work, a 2:1 multiplexer is used for further doubling the sequence rate. In general, both inputs of the multiplexer have the same maximum length sequence (MLS) and both of them are half of the MLS apart for doubling the data-rate. In the proposed architecture, the first input of the multiplexer is taken from interleaved PRBSG core and a circuit is incorporated into the PRBSG core for generating the other input of the multiplexer. Delay calculation method, for achieving this second input, is also explained in detail. The proposed architecture reduces area and power significantly as compared to the existing quarter-rate PRBSG architectures. For verifying the concept, a 2 7-1 quarter-rate PRBSG is designed with standard 65 nm CMOS technology. Post layout simulations confirm operation of the circuit at a data-rate of 14 Gbps with peak to peak jitter of 2 ps, while consuming 22 mW off a 1 V supply. Area (and power) of the PRBSG can be reduced by 26%, 8.5% and 38%, as compared to quarter-rate series, series-parallel and full-rate implementations, respectively.
['Mahendra Sakare']
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture