This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns
['Younggap You', 'Yong Dae Kim', 'Jong Hwa Choi']
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead