Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing. >
['Heinrich Theodor Vierhaus', 'Wolfgang Meyer', 'Uwe Gläser']
CMOS bridges and resistive transistor faults: IDDQ versus delay effects