We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also allows us to omit some flip-flops in the scan chain. By leaving flip-flops that need less control out of the scan chain, we can reduce transitions on those flip-flops, thereby reducing the overall power and energy. The omission of flip-flops are done in a way that the fault coverage is unaffected. Furthermore, reordering of the flip-flops in the scan chain allows the generated patterns to be more compatible with the state sequence necessary for exciting the random-pattern-resistant faults. Our experiments show that the same or higher fault coverage can be achieved with less energy (and average power) - average power of 48.5% is reduced, with the maximum reduction of 73%.
['Xiaoding Chen', 'Michael S. Hsiao']
Energy-efficient logic BIST based on state correlation analysis