In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively.
['Khosrov Dabbagh Sadeghipour']
A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs