We define a new transition fault model to guide the generation of n-detection test sets for transition faults. The model is referred to as the cut delay fault model. Under a cut delay fault, a transition fault on a line c/sub 0/ is detected while certain other lines in the circuit assume specific values. The lines involved in a cut delay fault form a cut or a subset of a cut. Each transition fault is associated with several combinations of values on the cut, and it is thus detected by several different tests.
['Irith Pomeranz', 'Sudhakar M. Reddy']
The cut delay fault model for guiding the generation of n-detection test sets for transition faults