In this work, a strategy to improve the detectability of interconnection open defects applying proper logic levels at the coupled lines is proposed. A framework called OPVEG which uses layout information and a commercial ATPG under the stuck-at model has been developed. Those signal values at the coupled lines which favor the detection of the opens using a Boolean based test are attempted to be generated. The strategy is applied to four ISCAS'85 benchmark circuits. It has been found that a significant number of considered coupled signals can be forced to a proper logic value. Hence, the likelihood of detection of interconnection opens is increased. Furthermore, those lines difficult to test are identified.
['Roberto Sánchez Gómez', 'Alejandro Girón', 'Víctor H. Champac']
Test of interconnection opens considering coupling signals