A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the power-delay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18-mum CMOS process
['Massimo Alioto', 'Rosario Mita', 'Gaetano Palumbo']
Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers