This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.
['Dai Zhang', 'Atila Alvandpour']
A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s