Intellectual property theft by reverse engineering leads to loss of revenue and threatens security of integrated circuits. A number of design obfuscation techniques been proposed to counter IC reverse engineering. Most such techniques rely on functional misdirection at gate or module level but, do not prevent leakage of visual information about design characteristics from the physical layout. For example, capitalizing on relative difference in sizes among various functional units and their pin counts, an attacker may still be able to hypothesize about function of a unit, irrespective of any obfuscation performed on them. Hence, we propose meta-obfuscation techniques to harden other obfuscation mechanisms against physical information leakage. Our aim is to add complexity in the visual domain so that the physical characteristics of a design do not have notable correlation to its functionality. We explore various metrics to quantify the quality of the proposed meta-obfuscation and apply them in design automation. Experimental results show improvement in metrics used and also, highlight relevant overheads for meta-obfuscation.
['Vinay C. Patil', 'Arunkumar Vijayakumar', 'Sandip Kundu']
On meta-obfuscation of physical layouts to conceal design characteristics