We propose an interconnect-driven framework that performs an efficient and effective design space exploration for deep submicron processor architecture design. At the heart of our framework, named AMPLE (adaptive microarchitectural planning engine), are wire delay-driven microarchitectural floorplanning and adaptive parameter tuning schemes that address interconnect issues with high exploration efficiency and accuracy. Our framework significantly outperforms the commonly used brute-force and simulated annealing methods in terms of exploration time efficiency as well as the performance and area quality for a large design space.
['Mongkol Ekpanyapong', 'Sung Kyu Lim', 'Chinnakrishnan S. Ballapuram', 'Hsien-Hsin S. Lee']
Wire-driven microarchitectural design space exploration