It is shown that interconnect testing for boards that mix boundary scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a scan circuitry integrity test, a fairly conventional boundary scan interconnect test, and a test for shorts between the boundary scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains boundary scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor boundary scan access, and that may even repeatedly not be detectable. >
['Gordon D. Robinson', 'John G. Deshayes']
Interconnect testing of boards with partial boundary scan