Timing- and constraint-oriented placement procedures are proposed to reduce design time and cost. These goals are (1) optimizing the intra and inter LSI delays, (2) observance of several electrical constraints such as simultaneous switching, and (3) high precision and high speed delay calculation. Hierarchical pin assignment, timing-driven placement, and high speed and precision timing analysis are proposed for achieving the above goals. Such algorithms are applied to a physical hierarchy containing 12 thousand gate ECL gate-array LSIs for the Hitachi M-880, a newly developed high-end mainframe computer. Using such algorithms, the physical design is greatly improved by optimizing timing and guaranteeing high wirability, i.e., by reducing the errors and time of error corrections.
['Y. Ogawa', 'Tsutomu Itoh', 'Yoshio Miki', 'Tatsuki Ishii', 'Yasuo Sato', 'Reiji Toyoshima']
Timing- and constraint-oriented placement for interconnected LSIs in mainframe design