Capable of only solving the read-stability issue, many 8T-10T static RAM (SRAM) cells require extra write-assist circuits to achieve low supply voltage operation. This brief proposes a novel 10T SRAM cell and a hybrid-divided-block array to enhance the read-and-write stability while achieving a higher operating speed with a smaller area overhead for sub-0.5 V applications. A 16-Kb 128-row 10T flowthrough SRAM macro is fabricated using a 90-nm bulk-CMOS process. The 10T cell area is only 1.7 times the size of a 6T cell. The measured VDDmin for the 10T 16-Kb macro is 240 mV. The proposed 16-Kb macro can achieve 300-MHz random access operation at 0.45 V for a 0.5 V system platform.
['Meng-Fan Chang', 'Yung-Chi Chen', 'Chien-Fu Chen']
A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips