In modern VLSI and SoC circuits, the minimum power supply voltage is often constrained by data storage elements on the chip. Using an ALU, we show that redistributing the current draw pattern using a delay element within the evaluation period (after known clock skewing techniques have been implemented), can further improve the worst case voltage droop in the power supply by ∼27% at a minimal cost to area (∼3%) and power (∼3%). Reducing the worst case droop is shown to reduce the on-chip decoupling capacitance requirements by 3X for a given voltage dip. In addition, the overall voltage level at which the chip can be operated can be reduced since the smaller droop allows storage elements to remain stable at the lower supply voltage.
['Tasreen Charania', 'Pierce Chuang', 'Ajoy Opal', 'Manoj Sachdev']
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block