In this paper, A novel architecture of an Application Specific Instruction Processor (ASIP) for scalable DFT/IDFT DCT/IDCT 1D (N-point) and 2D (N × M point) engine is proposed. An in place configurable radix 2/3/4 butterfly, makes possible the implementation of two radix N/M is varied in the form of 2 x  × 3 y . Therefore the engine can support different communication and signal processing applications. A new address generator scheme is proposed which achieves conflict-free memory access. This scheme is based on partitioning the memory to 4 dual-port memory banks with a continuous address generator to accommodate high-speed requirements. Using same reduction techniques, the twiddle factors memory size is reduced to 28%. By taking advantage of programmability, the engine provides more configurability and flexibility in switching between modes in run-time. Moreover it can be easily adapt to new applications. The DFT/DCT engine requires only 1280 clock cycles for a 1024-point DFT-1D and runs at 120 MHz with SQNR 75.2 dB.
['Hanan M. Hassan', 'Ahmed F. Shalash', 'Karim Mohamed']
FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine