This paper presents a hardware implementation of a detector for spatial modulation multiple-input multiple-output (SM-MIMO) communication systems. The proposed detector employs the signal-vector-based list detection method, but the original method is modified to realize a low-complexity implementation. In addition, the proposed detector is designed based on the dual data path architecture, in which antenna selection and the symbol detection are performed separately with different precision in order to reduce the hardware complexity while achieving a near-optimal error-rate performance. The proposed detector is implemented with 87.4K logic gates in a 0.18-um CMOS technology, and its throughput is 858 Mbps for 8 × 4 64 QAM SM-MIMO systems when the operating frequency is 286 MHz.
['Gwang-Ho Lee', 'Hye-Yeon Yun', 'Tae-Hwan Kim']
A near-optimal detector for spatial modulation MIMO systems