An even-wiring router for the BGA package is presented to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be practically applied to VLSI packaging.
['Shuenn-Shi Chen', 'Jong-Jang Chen', 'Chia-Chun Tsai', 'Sao-Jie Chen']
An even wiring approach to the ball grid array package routing