This paper presents a 4T asymmetric single-ended (ASE) SRAM cell in sub-32 nm CMOS fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar self-aligned gates. Both independent- and connected- gates operation is analyzed either with symmetrical or asymmetrical transistors which have been adjusted according to the current and future process possibilities. The proposed cell is compared with the conventional 6T and an efficient 4T cell. A second version of the new cell is also proposed to improve the write operation. Both novel cells take advantage of the additional gate, offered by the DG technology, to improve stability and write criteria. The results of read-, retention- and write margins, power consumption, access time, write disturb and area are displayed for all cells.
['Bastien Giraud', 'Amara Amara']
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology