This paper proposes the design of the embedded average of an interval type-2 fuzzy inference system (EAT2-FIS); four type-1 fuzzy inference systems are considered to model the footprint of uncertainty of inference process. The EAT2-FIS is designed in high level code, and this high level code is Very High Description Language (VHDL) for Field Programmable Gate Array (FPGA) applications. The goal is regulating the speed of a DC motor using Xilinx Spartan 3AN. The results obtained with the EAT2-FIS using different number bits are compared. The main contribution of the paper is the design and implementation of EAT2-FIS in VHDL, with the advantage of resolution change (bits number) of the EAT2-FIS for FPGA.
['Yazmin Maldonado', 'Oscar Castillo', 'Patricia Melin']
Embedded Average of an Interval Type-2 Fuzzy Systems for Applications in FPGAs