We have investigated the impact of inverse narrow width effect on the threshold voltage and drain current in the near/sub-threshold region at three technology nodes (90 nm, 65 nm and 40 nm) and proposed a new sub-threshold device sizing method which is inverse-narrow-width-effect-aware to reduce the gate area, power consumption and delay. We applied the proposed sizing method in designing a 40 nm sub-threshold standard cell library. Compared with the sub-threshold standard cell library designed using the conventional sizing method, the proposed library has up to 20% less delay, up to 34% less power consumption and up to 47% less area. We used the proposed library for designing a digital base-band processor and achieved a total power consumption of around 5 µw with 6 MHz at 0.5 V, which is 17% better than the counterpart design.
['Jun Zhou', 'Senthil Jayapal', 'Ben Busze', 'Li Huang', 'Jan Stuyt']
A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library