A pipelined analog-to-digital converter (ADC) that exhibits both power and area efficiencies is presented in this paper for ZigBee receiver applications. A combined opamp- and capacitor-sharing technique which presents a novel method to eliminate the memory effect is proposed. Fabricated in a 0.13-μm CMOS process, the prototype 7-bit 16-MS/s ADC occupies 0.16mm2 active die area and achieves 41.9dB signal-to-noise-and-distortion ratio (SNDR), 52.1dB spurious-free dynamic rage (SFDR). The experimental results show that the figure of merit (FOM) is 1.12pJ/step and power dissipation is 1.82mW from a 1.2V supply.
['Zuochen Shi', 'Yintang Yang', 'Di Li', 'Yang Liu']
A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications