We investigate a binary code, which is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to a binary turbo encoder. To achieve improved convergence behavior, we modify the binary code by passing only a fraction of the bits in the turbo code through the multilevel delay processor and the signal mapper. Two decoding methods are discussed and their performances are evaluated.
['Chia Jung Yeh', 'Yeong Luh Ueng', 'Mao Chao Lin', 'Ming Che Lu']
Interblock memory for turbo coding