Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are reported. Verified to be accurate with published SRAMs, these models enable the design of optimal array architectures to minimize total access time by balancing communication distance limited wire delays with fan-out and area limited gate delays.
['Azeez Bhavnagarwala', 'Stephen V. Kosonocky', 'James D. Meindl']
Interconnect-centric array architectures for minimum SRAM access time