Growing demand for more powerful yet smaller devices has resulted in continuous scaling of fabrication technologies. While this approach supports aggressive design specifications, it has resulted in tighter constraints for circuit designers who face yield losses in analog / RF ICs due to process variation. Over the last few years, several statistical techniques have, therefore, been proposed to counter these losses and to recover yield through individual post-manufacturing calibration of each fabricated chip using tuning knobs. These techniques can be broadly classified as iterative or one-shot calibration methods, with the latter having the benefit of being faster and, therefore, more likely to be cost-effective in a high volume manufacturing (HVM) environment. In this paper, we first put three previously proposed one-shot statistical calibration methods to the test using a custom-designed tunable LNA, which was fabricated in IBM's 130nm RF CMOS process. We, then, introduce an improvement to the tuning knob selection criterion, which applies to all three methods, increasing their effectiveness. Finally, we demonstrate the efficacy of a previously proposed approach which uses simulation data and Bayesian model fusion in order to reduce the number of chips required for training the statistical models employed by the three one-shot calibration methods.
['Yichuan Lu', 'Kiruba S. Subramani', 'He Huang', 'Nathan Kupp', 'Ke Huang', 'Yiorgos Makris']
A comparative study of one-shot statistical calibration methods for analog / RF ICs