Two dimensional (2D) integer transforms are used in all the profiles of H.264/MPEG-4 Advanced Video Coding (AVC) standard. This paper presents a resource shared architecture of 2D 4 × 4 and 8 × 8 integer transforms in H.264/MPEG-4 AVC coders. Existing architectures use separate designs to compute 2D 4 × 4 and 8 × 8 forward/inverse integer transform. Shared resource architectures for 4 × 4 and 8 × 8 transforms can be used to reduce the implementation area without sacrificing high throughput. Matrix decomposition is used to show that the 2D 4 × 4 forward/inverse integer transform of two independent data blocks can be obtained from one 2D 8 × 8 forward/inverse integer transform circuit. A high throughput architecture is used as the base design for the implementation of 2D 8 × 8 forward/inverse transform. Data rearrangement stages are added to the base design to compute the 2D 4 × 4 forward/inverse transform. The proposed dual-clock pipelined architecture does not require any transpose memory. As compared to existing designs, the proposed design operates on two independent 4 × 4 sub-blocks. Hence, the overall throughput of the 2D 4 × 4 forward/inverse transform computation increases by approximately 200% with less than a 5% increase in the gate count. The proposed design operates at a clock frequency of approximately 1.25 GHz and achieves a throughput of 7 G and 18.7 G pixels/sec for each block of 4 × 4 and 8 × 8 forward integer transforms, respectively. Due to resource shared implementation and high throughput, the proposed design can be used for real-time H.264/MPEG-4 AVC processing. Parallel processing of two independent blocks of 4 × 4 data.High circuit utilization ratio during 2D 8 × 8 and 4 × 4 integer transform computation.Data stream processing capability.High throughput.Small gate count.
['Honey Durga Tiwari', 'Meeturani Sharma', 'Harsh Durga Tiwari']
High throughput resource shared 2D integer transform computation for H.264/MPEG-4 AVC