The gain reduction of nanometer-size MOS transistors due to the high output conductance of the devices is already discussed in the literature. This paper discusses an additional issue which leads to further gain reduction - the gate-leakage current. On the basis of the example of a regulated cascode in 130 nm CMOS and in 65 nm CMOS it is estimated that this shrinking step decreases the gain due to gate-leakage current by about 30 to 40 dB.
['Franz Schlögl', 'Kerstin Schneider-Hornstein', 'Horst Zimmermann']
Gain reduction by gate-leakage currents in regulated cascodes