A high-speed and low-power Field Programmable Gate Array (FPGA) is the dream of digital designers. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz FPGAs [3, 4]. In the past, high static power consumption discouraged the significant scale-up of bipolar FPGAs. This paper details new ideas to reduce power and layout area in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize novel serial dual configuration planes to achieve an efficient programmability. In addition, new layout techniques are developed to reduce the bipolar areas. Several SiGe FPGA test chips based on Xilinx 6200 and Virtex Configurable Logic Blocks (CLBs) have been fabricated for demonstration.
['Kuan Zhou', 'John F. McDonald']
Multi-GHz SiGe design methodologies for reconfigurable computing