A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective. >
['Somchai Prasitjutrakul', 'William J. Kubitz']
A timing-driven global router for custom chip design