In this paper, we present a study of the implication based functional constraint extraction techniques to generate pseudo-functional scan tests. Novel algorithms to extract pair-wise and multi-node constraints as Boolean expressions on arbitrary gates in the design are presented. We analyze its impact on reducing the overkill in testing, and report the trade-offs in coverage and scan-loads for a number of fault models. In the case of path-delay fault model, we show that the longest paths contribute most to the over-testing problem, raising the question about scan testing of the longest paths. Finally, our evaluation of the functional constraints on large industrial circuits show that the proposed constraint generation algorithm generate a powerful set of constraints most of which are not captured in the constraints extracted by designers for design-verification purposes.
['Manan Syal', 'Kameshwar Chandrasekar', 'Vishnu C. Vimjam', 'Michael S. Hsiao', 'Yi-Shing Chang', 'Sreejit Chakravarty']
A Study of Implication Based Pseudo Functional Testing