A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm 2  with average cell size of 0.7191 μm 2 .
['Katsuhiko Hoya', 'Daisaburo Takashima', 'Shinichiro Shiratake', 'Ryu Ogiwara', 'Tadashi Miyakawa', 'Hidehiro Shiga', 'Sumiko Doumae', 'S. Ohtsuki', 'Yoshinori Kumura', 'Susumu Shuto', 'Tohru Ozaki', 'Koji Yamakawa', 'I. Kunishima', 'Akihiro Nitayama', 'Shuso Fujii']
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode