The dual-frequency dual-inductor multiple-output (DF-DIMO) buck converter topology is presented. The topology employs a dual-phase 20 MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-output 100 MHz comparator-controlled fully integrated output stage to reduce the capacitance required per output to 10 nF. In order to enable each output to handle up to 250 mA load with less than 40 mV voltage ripple, a third-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency and dynamic performance, and high-gain error amplifier in the output feedback loop to enhance DC load regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65 nm CMOS technology with 1.8 V input, and outputs in the range of 0.6– 1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40 mV output voltage ripple, 0.5 V/70 ns dynamic voltage scaling (DVS), and settling time of less than 85 ns for 125 mA load steps; all with no observable cross-regulation transients.
['Yongjie Jiang', 'Ayman Fayed']
A 1 A, Dual-Inductor 4-Output Buck Converter With 20 MHz/100 MHz Dual-Frequency Switching and Integrated Output Filters in 65 nm CMOS