In this paper, given a set of n terminals including some current sources and some current sinks in a signal net, the maximum current density and the minimum wire width, a current-driven routing tree can be constructed to satisfy the current flow in Kirchhoffpsilas current laws. Furthermore, all the area-driven Steiner points are assigned to reduce the total wiring area based on the determination of current-driven wire widths. Finally, an electromigration-aware rectilinear Steiner tree (ERST) is constructed by assigning all the physical paths with current driven wire widths. Compared with the Lienigpsilas approach[7], the experimental results show that our proposed approach reduces 5.3%~10.4% total routing area for tested examples in reasonable CPU time.
['Jin-Tai Yan', 'Zhi-Wei Chen']
Electromigration-aware rectilinear Steiner tree construction for analog circuits