A semidynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow.
['Kenji Shimazaki', 'Mitsuya Fukazawa', 'Makoto Nagata', 'Shingo Miyahara', 'Masaaki Hirata', 'Kazuhiro Sato', 'Hiroyuki Tsujikawa']
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs