The authors propose a novel test CAD (computer-aided-design) system for ASIC (application-specific integrated circuits), including megacells which automatically insert high-testability logic. The strategy is to access megacells directly and independently. The overhead is only 2% to 3% of the total number of gates. With the proposed system, hierarchically designed logic data can be converted to high-testability logic. It is not necessary for the designers to have specialized knowledge about design-for-testability. >
['Michiaki Emori', 'Takashi Aikyo', 'Yasuhide Machida', 'Jun-ichi Shikatani']
ASIC CAD system based on hierarchical design-for-testability