We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The methodology is based on rule composition, and relies on the fact that a rule derived by the composition of two rules behaves as if the two rules were scheduled simultaneously. Rule composition is a well understood transformation in the TRS theoretical framework; however, previous rule composition approaches resulted in an explosion of the number of rules during synthesis, making them impractical for realistic designs. We avoid this problem through composition of conditional actions which generates one rule instead of 2/sup n/ rules when we combine n rules. We then show how this conditional composition of rules can be compiled into an efficient hardware structure which introduces new but derived interfaces in modules. We demonstrate the approach via a small circuit example (GCD) and then show its impact on the methodology to implement pipelined processors in Bluespec. Many ways of dealing with branches in pipelined processors or bypassing values can be expressed simply as different schedules. The results show improvements in performance over previous rule-based synthesis approaches as well as the ease of performance-related architectural exploration. In a somewhat surprising result, we show that simply by specifying a different schedule, one can automatically transform a single-issue processor pipeline into a superscalar pipeline.
['Daniel L. Rosenband', 'Arvind']
Hardware synthesis from guarded atomic actions with performance specifications