We present a system-level co-synthesis tool as part of a methodology for the co-design of dataflow dominated systems. The co-synthesis tool uses an applicational model that supports iterative dataflow graphs with hierarchical tasks and feedback, and an architectural model that considers extended interconnection and memory topologies and takes into account reconfigurable computing units. We describe new co-synthesis techniques that deal effectively with these extended models while applying retiming and unrolling loops to optimize the execution time. The preliminary results indicate that the new approach proposed is able to efficiently handle real problems.
['Mário P. Véstias', 'Horácio C. Neto']
System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures