This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.
['Sai Rahul Chalamalasetti', 'Sohan Purohit', 'Martin Margala', 'Wim Vanderbauwhede']
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor