With the advent of deep sub-micron technologies, interconnect loads and delays are becoming significant, and layout-driven synthesis has become the need of the day. However, given the tight constraints imposed by the layout (e.g., area availability, congestion), only those synthesis transforms can be made layout-driven that are local and layout-friendly. Examples of such transforms are net buffering, gate resizing, and gate replication.In this paper, we address the problem of minimizing the delay of a mapped, roughly placed, and globally-routed design by buffer insertion and/or deletion without violating the local area constraints imposed by the layout and without overloading any buffer/cell pins.  We believe this is the one of the most fundamental problems in layout-driven buffer optimization. To the best of our knowledge, no technique has been published to date that solves this problem.  The concept of local (or block) area constraints we use in this paper is more powerful than that of the total design area traditionally-used in logic synthesis.Our main contributions are the following: 1. We propose an exact, layout-driven net buffering algorithm to minimize the delay of an extended net under the area constraint of each block in the design. 2. We propose a simple yet effective scheme for applying the single-net algorithm to an entire design. 3. We apply our technique successfully on three real, large, industrial designs. The largest design (172K gates and 211K nets) could be optimized in about 20 minutes. The technique is remarkably effective when the available area in the design is small: it generates 6-9 times better delay improvements than the unconstrained delay minimization technique [8] modified to handle area constraints. Over an entire range of available areas, it gives about 115% better delay improvements.
['Rajeev Murgai']
Layout-driven area-constrained timing optimization by net buffering