In this extended abstract we sketch the employment of programmable logic for the acceleration of the simulation of pulsed neural networks. We compare our approach to solutions which are based on DSPs and digital neuroprocessors. Our solution is a rapid prototyping accelerator board which is based on a data flow concept. The accelerator provides three module sockets with a rather simple 32Bit interface. The design is focused on a maximal data through-put to and from each module. Due to the architecture a very high parallelism between the modules can be achieved Two programmable devices on each module are supported by the on-board programming and test unit, which provides in-circuit programming by the host during operation. As a result the accelerator delivers a high performance and flexibility without introducing a complex interface or handling. Any programmable device, FPGA, CPLD or special architectures like Kress-Arrays may be used on a module of this accelerator board, hence coarse and fine grain architectures can be used.
['Cyprian Grassmann', 'Joachim K. Anlauf']
RACER - a rapid prototyping accelerator for pulsed neural networks