This paper presents a low-voltage compatible 120 dB gain two-stage amplifier in standard digital CMOS with /spl les/3 transistors between V/sub DD/ and V/sub SS/. The first stage uses positive feedback to increase the output impedance and DC gain. A MOS precision voltage attenuator, output level monitoring circuits (OLMC) and a digital tuning network are used to achieve conductance cancellation over large output swings and process and temperature variations. The first stage was fabricated and tested, achieving /spl ges/76 dB DC gains over 2Vpp output swings. A modest-gain 2nd stage eliminates the need for OLMC and significantly improves linearity. The two stage amplifier can achieve /spl ges/120 dB DC gains (by simulation, or 110 dB projected from test results) over 2Vpp output swings with PM /spl ges/56/spl deg/ at UGF /spl ges/ 120 MHz when VDD = 3.5V.
['Chengming He', 'Degang Chen', 'Randall L. Geiger']
A low-voltage compatible two-stage amplifier with /spl ges/120 dB gain in standard digital CMOS