The VLSI layout designing is a highly complex process and hence a layout is often subjected to Layout Verication that includes (a) Design Rule Checking to check if the layout satises various design rules and (b) Connectivity Extraction to check if the components of the layout are properly electrically connected. In this work we study two geometric query problems which have applications in the above layout verication phase.
['Ananda Swarup Das', 'Prosenjit Gupta', 'Kannan Srinathan']
Detecting VLSI Layout, Connectivity Errors in a Query Window.