Rise in bandwidth requirement for multimedia processing is forcing designers to use complex or wider buses in SOCs. Compression schemes using bit serial codes offer a low complexity encoding solution to such problems. However, their inherent sequential nature makes it challenging to achieve real time throughput at the decoder end. Conventionally, this problem is addressed by high frequency application processors or LUT based hardware, both of which are power hungry solutions. In this paper, we present a novel hardware architecture capable of decoding image bit planes encoded using bit serial codes, while overcoming the above limitation. It achieves parallelism without the use of any markers between bit planes. The architecture is also able to decode interleaved RAW data with minimal header information. The area of proposed architecture scales linearly with output bitrate, making it suitable for use cases involving high resolution and/or high frame rates.
['Atif Iqbal Ahangar', 'Rajat Agarwal', 'Kartik Lakhotia']
Real time low complexity VLSI decoder for prefix coded images