An efficient pre-traceback architecture is proposed for the survivor path memory unit (SMU) of a Viterbi decoder (VD) targeting wireless communication applications. Compared to the conventional traceback approach, which is based on three kinds of memory access operations (decision bits write, traceback read and decode read), the proposed architecture exploits the inherent parallelism between the decision bit write and the decode traceback operation by introducing a pre-traceback operation. The proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback approach achieves up to 11% energy efficiency and 21% area saving compared to the conventional traceback architecture for typical wireless applications.
['Yao Gang', 'Tughrul Arslan', 'Ahmet T. Erdogan']
An efficient pre-traceback approach for Viterbi decoding in wireless communication