With recent advancements in SoC integration, modern SoC architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between −226dB and −234dB from 0.8GHz to 5GHz is presented. The PLL features a modular implementation and therefore could be used as the local clock source or as part of a clock-generation hub. The hub provides reference clocks to subsystems from a single platform crystal oscillator through a combination of divisions and distributions.
['Kuan-Yueh James Shen', 'Syed Feruz Syed Farooq', 'Yongping Fan', 'Khoa Minh Nguyen', 'Qi Wang', 'Amr Elshazly', 'Nasser A. Kurd']
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS