This paper presents FPGA implementation of low complexity Maximum Likelihood multiple input multiple output detection algorithm. FPGA Implementation of Maximum Likelihood detection for Multiple Input Multiple Output systems remains to be a great challenge. Devices which operate with battery power enforce severe silicon area and power limitations while trying for definite performance over a wide range of operating circumstances. First, multiple input multiple output system structure, mathematical model and Maximum Likelihood detection algorithm is presented. Performance of Maximum Likelihood Detection algorithm and its characteristics are studied. Next the developed system is implemented using MATLAB. Simulations are carried out and results are analyzed in terms of complexity and error performance. Finally, the low complexity Maximum Likelihood detector for multiple input multiple output is synthesized, and implemented on XC4VLX15SF363-12 device using Xilinx ISE tool. The results show that it is possible to implement Maximum Likelihood detector with a low power of 0.156W in a single FPGA chip.
['Vakulabharanam Ramakrishna', 'Tipparti Anil Kumar']
VLSI Implementation of Maximum Likelihood MIMO Detection Algorithm