Impact of backside thinning damages and topside device structures on the elastic stress distributions in ultra-thinned Si substrates were studied using µ-Raman spectroscopy and TEM observations. The compressive and tensile stresses due to the backside damages and the top-side device structures, respectively, are in equilibrium. The variations in elastic stress depend on the topside device structures such as shallow trench isolations (STIs) and memory-cell transistors, and to a lesser extent on the backside damages. Even for DRAM samples thinner than 4 microns, the elastic deformations underneath STIs and memory-cell transistors areas are considered to be no leakage current degradations, because the relation between retention time and pass rate shows little difference before and after thinning.
['Tomoji Nakamura', 'Yoriko Mizushima', 'Young Suk Kim', 'Ryuichi Sugie', 'Takayuki Ohba']
Characterization of stress distribution in ultra-thinned DRAM wafer