A scalable all-digital power supply noise analyzer with 20 GHz sampling bandwidth and 1 mV resolution is demonstrated in 32 nm CMOS technology for enabling low-cost low-power in-situ power supply noise measurements without dedicated clean supplies and clock sources. This subsampled averaging-based analyzer measures power supply noise in both the equivalent-time and frequency domains with low-resolution VCO-based ADCs. For equivalent-time measurements, the accurate impedance characterization of power delivery networks is simply done by measuring a clock-synchronized current-step response. For frequency-domain measurements, the digital random phase-noise accumulation technique is analyzed and verified to overcome the clock-and-noise correlation issue in autocorrelation measurements. In general large scale integrated circuits and systems, the entire power supply noise analyzer consumes negligible active and leakage powers because of the MHz-range sampling clock frequency and fully digital implementation with only hundreds of logic gates.
['Tzu-Chien Hsueh', "Frank O'Mahony", 'Mozhgan Mansuri', 'Bryan K. Casper']
An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements