3D NoC (Network on Chip) technology has opened a new opportunity for the development of Network on Chip, which is a promising solution by distributing the network on multiple silicon layers. Comparing to the 2D designs, 3D NoC synthesis becomes even more complicated with stacking layers. The power consumption and network resources should be optimized with the consideration of the third dimension especially with Through-Silicon Vias (TSVs) among different layers. In this paper, by focusing on the network topology generation, we propose an incremental algorithm to optimize the network by merging the adjacent routers properly in 3D designs, so that many physical design issues could be optimized at the same time. Experimental results show that our algorithm can on average achieve 33% reduction in power consumption and 41% reduction in network resource area over the original 3D implementation, and the number of TSVs would be reduced by 11% on average.
['Yuanyuan Li', 'Ning Xu', 'Yuchun Ma', 'Jinian Bian']
Incremental 3D NoC synthesis based on physical-aware router merging algorithm