A scalable and easy to design solution for the continuing demand of high performance chip multiprocessors paved the way for Hybrid Wireless Network on Chip (WiNoC) architectures which comprises of both wired and wireless channel interconnects for communication. The simulation results of this emerging communication architecture outperforms other traditional interconnects in performance gain for multicore systems. Besides simulation, statistical modelling is another way to measure system performance. This paper proposes a statistical model based on queuing theory to measure performance of scalable Hybrid Wireless Network on Chip (WiNoC) architecture. The statistical model studies the transition state distribution and steady state distribution of flits in the input channel and analyzes average number of flits and average waiting time of flits in the wireless channel. The proposed statistical model predictions have been verified with the simulation results which shows that the relative error between the two results to determine the average latency of the flits and the number of flits lies within 5%. The statistical model also determines the critical value when the network enters into the state of congestion. Thus the proposed statistical model has been verified and validated accurately with the simulation results.
['Priyanka Mitra']
A Statistical Model for Hybrid Wireless Network on Chip