The authors describe an efficient procedure for translating stuck-at faults in a gate level implementation into state-table faults in a state-table description of the circuit. Based on this fault procedure, a test generation approach is presented for stuck-at faults, which results in short test sequences and achieves complete coverage of stuck-at faults. Experimental results are given for both MCNC and ISCAS-89 benchmark circuits, to demonstrate the applicability of the method. >
['Irith Pomeranz', 'Sudhakar M. Reddy']
Test generation for synchronous sequential circuits based on fault extraction