Stochastic local search methods such as GSAT, WalkSAT and their variants have been used successfully at solving propositional satisfiability problems (SAT). The key operation in these local search algorithms is the speed of variable flipping. We present a parallel FPGA designs for CSAT capable of one flip per clock cycle which is achieved by exploiting maximal parallelism and "multi-try" pipelining. Experimental results show that a speedup of two orders of magnitude over software implementations can be achieved.
['Martin Henz', 'Edgar Tan', 'Roland H. C. Yap']
Implementing CSAT Local Search on FPGAs