Substrate noise is a major impediment to mixed-signal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 480 MHz digital PLL implemented in a 90 nm CMOS process on a high resistivity substrate.
['Nisha Checka', 'Anantha P. Chandrakasan', 'Rafael Reif']
Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL