The paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2/sup nd/ order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35 /spl mu/m BSim3v3 CMOS models of two PLL designs (10 MHz FSK demodulator, 500 MHz frequency synthesizer) are included.
['Reuben Wilcock', 'Peter R. Wilson', 'Bashir M. Al-Hashimi']
A novel switched-current phase locked loop