4-bit 2-Gsample/s flash A/D converter is presented. It is realized in a digital 0.13 um CMOS technology. To compensate for timing skew and delay problem at comparator outputs, a new latched-skewed-logic is introduced; the proposed latched-skewed-logic improves the performance of the A/D converter with negligible increase in power consumption. The simulation results show that the implemented A/D converter, operating with a sampling frequency of 2 GHz, has an effective number of bits (ENOB) of 3.92 with an input frequency of 100 MHz and 3.81 with a Nyquist input while consuming only 1 8 mW. This corresponds to a figure-of-merit (FoM) of 0.6 pJ/convstep at Nyquist. The active area is 0.035 mm 2 .
['Jong Ho Lee', 'Yun Jeong Kim', 'Suki Kim', 'Kwang Hyun Baek']
4-bit 2-Gsample/s flash A/D converter using latched-skewed-logic in 0.13um CMOS