Large single-die system chips are designed in a modular fashion, including and reusing pre-designed and pre-verified design blocks. Modular testing is required for embedded non-logic modules and black-boxed IP cores. Also, modular testing is attractive for other blocks, as it supports 'divide-n-conquer' test generation and test reuse. Modular testing requires an on-chip infrastructure. This tutorial paper gives insight in the principles behind modular testing and its need for a dedicated on-chip test infrastructure. The paper describes the IEEE standard 1500 test wrapper for embedded modules and the basics of SOC-level test architecture design in relation to test time optimization. In addition, two application examples are given to illustrate current industrial practices.
['Erik Jan Marinissen', 'Tom Waayers']
Infrastructure for modular SOC testing