Binary multiplication is one of the fundamental arithmetic operations, and it is used in digital filters and signal processing applications. The continuous valued number system (CVNS) is a recently introduced number system that allows digital arithmetic, with arbitrary precision, to be implemented with analog circuitry. Due to the analog nature of the numbers system, CVNS reduces the total system and cross talk noise. An 8 times 8 digital multiplier is proposed, using CVNS compressors for reducing the digital partial products. A new definition for the CVNS compressor for the first time is introduced, along with a novel CMOS current mode circuit. The multiplier is realized in TSMC CMOS 0.18mum technology, with a maximum delay of 900ps, static power consumption of 19mW and a core area of 11200 mum 2 . The example demonstrates that CVNS designs can yield fast, low power arithmetic circuits using low noise analog circuitry.
['Mitra Mirhassani', 'Majid Ahmadi', 'Graham A. Jullien']
Digital Multiplication using Continuous Valued Digits