This paper presents the architecture, design and implementation of a 16 point FFT processor for a high speed wireless local area network. The 110000-transistor chip is implemented in 0.6 /spl mu/m TLM CMOS, operates worst case at 50 MHz at a supply voltage of 2.5 volts, and consumes 80 mW.
['M. Bickerstaff', 'T. Arivoli', 'Philip J. Ryan', 'Neil Weste', 'D.J. Skellern']
A low power 50 MHz FFT processor with cyclic extension and shaping filter