This paper presents the design and study of circuit architecture able to perform 16 Gbps GFP frame delineation with single bit error correction using UMC 130 nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms.
['Ciaran Toal', 'Sakir Sezer', 'Xin Yang']
A VLSI GFP frame delineation circuit