A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained. >
['Beena Vasudevan', 'Don E. Ross', 'Murali M. R. Gala', 'Karan Watson']
LFSR based deterministic hardware for at-speed BIST