Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.
['H. Speek', 'Hans G. Kerkhoff', 'M. Shashaani', 'Manoj Sachdev']
A low-speed BIST framework for high-performance circuit testing