A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier is proposed here. Secondly, digital correction technique is adopted for eliminating the error induced by offset voltage of comparator. As long as the offset voltage is less than 1/16 Vref, the offset voltage can be corrected. Thirdly, digital calibration technique is used to calibrate the gain errors due to capacitor mismatch, finite open-loop gain and finite gain band width (GBW) of residue amplifier and so on. The prototype chip was fabricated in a 0.35 µm CMOS process and occupies a core area of 960×1260 µm 2 . The proposed pipleined SAR ADC achieves 55.6 dB SNDR at 1 MS/s sampling rate and consumes 8.2 mW power. The FOM of the proposed ADC is 17.2pJ/conversion-step.
['Feifei Xue', 'X. Wei', 'W. Gao', 'Y. Hu']
Design of a 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system