An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules. >
['Xinghao Chen', 'Michael L. Bushnell']
A module area estimator for VLSI layout