In this paper, a corner block list -- a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a corner block list, it takes only linear time to construct the floorplan. Unlike the O-tree structure, which determines the exact floorplan based on given block sizes, corner block list defines the floorplan independent of the block sizes. Thus, the structure is better suited for floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks and the aspect ratio of the chip are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising.
['Xianlong Hong', 'Gang Huang', 'Yici Cai', 'Jiangchun Gu', 'Sheqin Dong', 'Chung Kuan Cheng', 'Jun Gu']
Corner block list: an effective and efficient topological representation of non-slicing floorplan