We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a fight upper bound of the execution time, and many useful hints to the designer.
['Junhee Yoo', 'Xingguang Feng', 'Kiyoung Choi', 'Eui-young Chung', 'Kyu-Myung Choi']
Worst case execution time analysis for synthesized hardware