This paper describes CLARION, a circuit reorganization subsystem of the USC­Test system. Most digital circuit designs are described as netlists of hundreds of thousands of gates and flip­flops, and CAD tools and engineers often do not have knowledge of the high­level structure of the design. Starting from only a flat description of a circuit, CLARION constructs a 2­level hierarchy of the dataflow structure of the circuit consisting of registers and blocks of connected combinational logic. This circuit reorganization capability has applications in CAD areas such as floorplanning, placement, routing, retiming and logic resynthesis. An application to the high­ level design­for­testability (DFT) and built­in self­test (BIST) tools in the USC­Test system is presented.
['Ishwar Parulkar', 'Melvin A. Breuer', 'Charles A. Njinda']
Extraction of a High&#173;level Structural Representation from Circuit Descriptions with Applications to DFT/BIST "Lambda