Two hardware architectures for implementing lifting-based discrete wavelet transform (DWT) suitable for implantable, real-time operation of high-density sensor array neuroprosthetic devices. A core computational node (CN) is designed for use in both architectures to yield maximum processor usage. The first uses multiple pipelined replicas of the CN, requiring fewer clock cycles. The second architecture reuses a single CN, thus requires less chip area but longer time delay. By utilizing the difference between the data sampling rate and available computation bandwidth, the novelty of both designs lies in the scalability to an arbitrary number of channels by interleaving the DWT computation without affecting the real-time operability. Performance comparison and overall considerations of both designs are presented in details.
['K. Thomson', 'Yasir Suhail', 'Karim G. Oweiss']
Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices