We show that rising and falling delays in gates can differ considerably. Simulation data, using 40 nm and 65 nm process technology, shows an increasing trend and that the slow transition delay could be two times of the faster transition delay. This translates to an asymmetry between the rise and fall delays along a path. Based on this we propose refinements to the following delay test methodology: (i) selection of robust path delay tests for delay characterization; (ii) refinements to small delay defects coverage metric; and (iii) an alternative to the inline resistance fault (IRF) model for selecting TDF tests.
['Sean H. Wu', 'Sreejit Chakravarty', 'Alexander Tetelbaum', 'Li-C. Wang']
Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay