Speed-independent fused multiply-add unit as a coprocessor is represented. It purely conforms to IEEE 754 Standard. For minimization hardware and power consumption, a number of pipeline stages is reduced down to two. Wallace tree in the multiplier utilizes redundant self-timed code. Represented unit is developed on a base of standard 65-nm CMOS bulk process. It provides a performance up to 0.54 Gflops, and power consumption at level of 450 m W/Gflops.
['Y. A. Stepchenkov', 'V. N. Zakharov', 'Yuri Rogdestvenski', 'Yuri Diachenko', 'N. V. Morozov', 'Dmitri Stepchenkov']
Speed-independent floating point coprocessor