This paper presents a new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan. The scheme is based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits. The paper analyzes the effectiveness of this novel approach both theoretically and through extensive experiments. A modular design of the decompression hardware re-uses the same LFSR used for pseudo-random vector generation and scan registers to minimize the area overhead.
['Nadime Zacharia', 'Janusz Rajski', 'Jerzy Tyszer']
Decompression of test data using variable-length seed LFSRs