The rapid advance of VLSI and packaging technologies has a significant impact on system architecture. In this paper, an analytical model is used to explore the design space of interconnection networks for a 4,096 node processing system incorporating multi-node chips packaged on a single MCM substrate. Possible designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for intrachip and interchip communication. An analysis of the impact several architectural and technological parameters have on the optimal network implementation (based on average no-load latency) is presented.
['J.L. Cruz-Rivera', 'D. Scott Wills', 'Thomas K. Gaylord', 'Elias N. Glytsis']
Modeling the technology impact on the design of a two-level multicomputer interconnection network