In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.
['Mummaneni Kavicharan', 'N. S. Murthy', 'N. Bheema Rao']
EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT