The main goal of this work is to describe a scalable and reusable architecture useful for the construction of Ethernet switches, named MOTIM. The main requirement of MOTIM is to allow achieving low latency and high throughput with a generic structure that can be easily scaled. In order to make the architecture scalable, its design is based on the use of a network on chip (NoC), a concept recently proposed for enhancing SoC interconnect design (Benini, 2002). NoCs stand as a good compromise between silicon cost and performance scalability, easing to attain design requirements. Minkenberg et al. recently identified a set of trends arising in packet switch design and discussed their consequences (Minkenberg, 2003). The most important of these trends indicates that the aggregate throughput grow by increasing the amount of ports in switches, rather than by increasing port speed. This imposes a demand for larger crossbars, a structure that do not scale well. Scalable NoCs are a feasible alternative to implement switches with fully interconnected ports.
['Érico Nunes Ferreira Bastos', 'Everton Alceu Carara', 'Daniel V. Pigatto', 'Ney Laert Vilar Calazans', 'Fernando Gehm Moraes']
MOTIM - A Scalable Architecture for Ethernet Switches