This paper presents the hardware realization of a recurrent scalable sorting network based on Batcher's bitonic algorithm, which is very suitable for concurrently accessible data. Firstly, preserving the time complexity of the original bitonic sorter, the recurrent network yields a lower area complexity by reducing the communication within the network and minimizes the cost in terms of hardware resources. Secondly, an enhancement of the input registers allows the reuse of the same architecture for different input widths, where the role of each comparator level is redistributed over the network. Finally, the implementation of such a sorter has been realized in an FPGA (Field Programmable Gate Array) and shows how applications treating data block-wise can benefit from this architecture.
['Christophe Layer', 'Hans-Jörg Pfleiderer']
A reconfigurable recurrent bitonic sorting network for concurrently accessible data