This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 µA and 2 GHz frequency with a good accuracy. The proposed topology relies on the output voltage difference of transient sensors. Thus, it can be scalable as the technology shrinks and still be an effective method to detect new emerging faults.
['O. Kubilay Ekekon', 'Samed Maltabas', 'Martin Margala']
A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies