An efficient algorithm and the VLSI-architecture for fast soft-decision permutation decoding of the (24,12) extended Golay code are presented. The new decoding technique consists of an optimized permutation decoding with look-ahead error-correction and a modified parity-check soft-decision decoding with reduced test patterns based on the Chase's (1972) algorithm-2. The simulation results for the Gaussian fading channel were found to be only slightly inferior to Chase's algorithm-2 although performing only four test patterns. A parallel VLSI-architecture is also proposed, which will allow for data rates reaching in the hundreds of Mbit/s.
['Weixun Cao']
High-speed parallel hard and soft-decision Golay decoder: algorithm and VLSI-architecture