In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty.
['Prashant S. Parikh', 'Miron Abramovici']
On combining design for testability techniques