This paper presents a DES/3DES core that will support cipher block chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.
['Chin Mun Wee', 'Peter Sutton', 'Neil W. Bergmann']
An FPGA network architecture for accelerating 3DES - CBC