The paper presents the results of an investigation into the efficient implementation of reduction operations for cluster-based parallel computing across asynchronous transfer mode (ATM) local area networks. The study combines graph theoretical analysis with experimentation on an ATM network. Different reduction algorithms are analyzed in terms of the amount of message traffic produced and the number of message-passing steps required. This analysis, which indicates how to take advantage of switch-based interconnects and hardware multicast communication, is applied to the development of both N/1 and N/K reduction protocols. Performance measurements from implementations on a three-switch ATM testbed are presented to support the analytical results. >
['Chengchang Huang', 'Philip K. McKinley']
Design and implementation of global reduction operations across ATM networks