A low cost, high performance implementation of Hewlett-Packard's PA-RISC 1.1 architecture is described. This chipset is used in HP's 9000 series 700 workstations. The processor consists of two VLSI chips, a CPU and a floating point coprocessor, which are tightly coupled to large, off-chip instruction and data caches accessed at up to 66 MHz. The CPU is implemented in HP's 1.0 mu m CMOS26 technology and the FPC in Texas Instruments' 0.8 mu m EPIC II CMOS. The caches are implemented using standard asynchronous static RAMs. Features added to improve workstation performance in the areas of graphics and floating point are also described. >
['Craig Gleason', 'Mark E. Forsyth', 'Charlie Kohlhardt', 'Steve Mangelsdorf', 'Barry J. Arnold', 'Rick Luebs']
CMOS processor circuit design in Hewlett-Packard's series 700 workstations