This paper presents a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.
['Yang Qu', 'Kari Tiensyrjä', 'Juha-Pekka Soininen', 'Jari Nurmi']
System-Level Design for Partially Reconfigurable Hardware