As the number of tiles in a System-on-Chip SoC increase, Network-on-Chip NoC becomes the favored interconnect. With an increased number of tiles, applications are subject to being partitioned and distributed to multiple tiles as well. To deal with the resulting traffic efficiently, the NoC needs to support network multicasts. On the other hand, advanced techniques like aggressive voltage scaling and feature size reduction in technology generations of 22i¾źnm and below introduce new variability challenges to SoC designers in general. Especially for Network-on-Chip NoC as on-Chip communication backbone, the impact of bit flips in registers and on wires is of high importance. This paper focuses on the expected end-to-end bit and packet error rates for multicast groups. The estimations are based on the probabilities of single bit flips of NoC entities such as buffers or links. Being based on binary-symmetric-channels BSCs, the proposed approach abstracts technology details and allows for fast design space exploration during early phases of HW/SW system design to assess the reliability of NoC including different application partitionings without time-consuming network simulations.
['Michael Vonbun', 'Thomas Wild', 'Andreas Herkersdorf']
Estimation of End-to-End Packet Error Rates for NoC Multicasts