An all-digital DLL is designed to generate low jittery 40 phases in a continuous lock range of 110 MHz to 1.4 GHz. The DLL is driven by dual loops-one for phase lock and the other for offset calibration. The two loops are updated by a chopping PD which adaptively extracts valid information for each loop, one at a time. For the optimal 1-bit delay resolution in the entire lock range, a piecewise profiling of delay line is also proposed. The DLL, fabricated in a 0.13 CMOS, reveals the best linearity performance compared with previously reported works, showing a DNL of less than 0.3 LSB and a INL of less than 0.8 LSB in the entire lock range up to 1.4 GHz. With the piecewise-fitted delay line, the amount of peak-to-peak and rms jitters induced by DLL operation is controlled to be less than 0.825% and 0.2% of the clock period, respectively. Power consumption was 74.4 mW at the supply voltage of 1.2 V.
['Young-Sang Kim', 'Seon-Kyoo Lee', 'Hong-June Park', 'Jae-Yoon Sim']
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL