In this paper we report the monolithic integration of two single grain silicon layers for SRAM and image sensor applications. A 12 × 28 silicon lateral photodiode array with a 25_μm pixel size prepared on top of a three transistor readout circuit with individual outputs for every pixel is demonstrated. 6T SRAM cells with two layers of stacked transistors were prepared to compare the performance and area of each cell in different configurations.
['Negin Golshani', 'J. Derakhshandeh', 'Ryoichi Ishihara', 'C.I.M. Beenakker', 'M. D. Robertson', 'Thomas William Morrison']
Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon