Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper the authors investigate the critical charge (Q crit ) required to upset a 6T SRAM cell designed in a commercial 90nm process. The authors characterize Q crit  using different current models and show that there are significant differences in Q crit  values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAM's associated soft error rate as large as two orders of magnitude. For accurate Q crit  calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.
['Riaz Naseer', 'Younes Boulghassoul', 'Jeff Draper', 'Sandeepan DasGupta', 'Art Witulski']
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM