Power consumption is a critical aspect in today's mobile environment, while high-throughput remains a major design goal. To satisfy both low-power and high-throughput requirements, parallelism has been employed. In this paper we present an approach to reducing power dissipation in the design of sum-of-products operation by utilizing parallel hardware while maintaining high-throughput. The proposed design reduces about 46% of execution time with about 12% energy penalty compared to the ARM7TDMI-S multipliers in benchmark programs.
['Seok Won Heo', 'Suk Joong Huh', 'Milos D. Ercegovac']
Power optimization of sum-of-products design for signal processing applications