As VHDL spreads widely, its usage for abstract modeling and synthesis is limited by the simulation semantics, which necessitates the specification of the interface signal transitions at bit level with exact timing. This paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the transformations to generate a RT data path while holding the exact simulation semantics at the interface.
['Peter Pius Gutberlet', 'Wolfgang Rosenstiel']
Timing preserving interface transformations for the synthesis of behavioral VHDL