A VLSI implementation of a multistage self-routing ATM switch fabric is presented. The size of the switch is 16/spl times/16 and can handle the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16/spl times/16 switch is implemented using four identical chips. The switch hits multiple paths, created by a randomizer in front of the routing stages between each input-output pair. The switch uses an input/output-buffering scheme and contains no buffers inside the fabric. A priority structure, which supports four levels, allows the delay sensitive ATM cells to be switched with the shortest latency. It also enables the noninterleaving routing scheme of IP cells. The switch fabric was designed and fabricated using MOSIS 0.8 /spl mu/m technology and was tested to run at 93 MHz with 3.3 V supply voltage.
['Chi-Ying Tsui', 'Louis Chung-Yin Kwan', 'Chin-Tau Lea']
VLSI implementation of a switch fabric for mixed ATM and IP traffic