An efficient pipeline analog-to-digital converter (ADC) self-calibration implementation is presented. The technique uses a highly linear on-chip analog ramp generator, performs a simplified on-chip integral nonlinearity (INL) measurement, and extracts the compensation coefficients. Except for the ramp generator, the whole calibration is performed in the digital domain and is done at the nominal ADC speed (at-speed). The approach does not require any modification to the original analog section of the ADC. The INL measurement can be carried off-chip to simplify the production testing or to perform performance verification in the application environment. Simulation and measurement results show an INL improvement of more than 2 bits (from /spl plusmn/2.1 LSB to /spl plusmn/0.5 LSB).
['Benoit Provost', 'Edgar Sánchez-Sinencio']
A practical self-calibration scheme implementation for pipeline ADC