In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (Gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65nm standard models are used for simulations.
['Farshad Moradi', 'Dag T. Wisland', 'Hamid Mahmoodi', 'Snorre Aunet', 'Tuan Vu Cao', 'Ali Peiravi']
Ultra low power full adder topologies