This paper gives an overview of methods proposed for implementing multi-valued logic in CMOS and then describes Intrinsity's patented Fast 14 reg Technology as a mature methodology for silicon implementation of multi-valued logic. To the authors' knowledge, no previous method of implementing multi-valued logic has been demonstrated with a design of the complexity of a microprocessor core. Fast 14  Technology is based upon three fundamental characteristics including the use of (1) footed NMOS transistor domino logic, (2) multi-phased overlapping clocks, and (3) 1-of-N encoding of MVL signals. To provide additional opportunities for power optimization, the concepts of null value and mutex properties are introduced, presenting additional challenges for MVL representation and synthesis.
['Mark H. Nodine', 'Craig M. Files']
A Mature Methodology for Implementing Multi-Valued Logic in Silicon