One of the main bottlenecks when designing a network system is very often its memory subsystem. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we describe the architecture and performance of a memory manager, the QMS that is tailored to FPGA technology and can provide up to 6.2 Gbps of aggregate throughput, while handling 32 K independent queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable networking system. It also supports a large number of different interfaces, and it is designed in a very scalable way. The QMS uses a double data rate DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimizing the system’s cost. In order to deal with the problems of refreshing and bank conflicts in the DRAM, several optimization techniques have been employed. In this paper we also present the architecture of a network-processing device that fully utilizes the advanced feature of the QMS. The QMS consists of 8500 Slices in a XILINX FPGA and works at 125 MHz. q 2004 Elsevier B.V. All rights reserved.
['Aristides Nikologiannis', 'Ioannis Papaefstathiou', 'George Kornaros', 'Christopher Kachris']
An FPGA-based queue management system for high speed networking devices