This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of Rao et al. (2004) is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the /spl alpha/-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objective function is O(|N|/sup 2/) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.
['Sarvesh Bhardwaj', 'Sarma B. K. Vrudhula']
Leakage minimization of nano-scale circuits in the presence of systematic and random variations