A 65-nm all-digital Class-S transmitter with an entire digital frontend (DFE) and a current-mode Class-D (CMCD) power amplifier (PA) is presented. To realize the high operation rate and performance of the DFE, which includes a 1-bit band-pass    $\Sigma \Delta $    modulator, a mixer, and interpolation filters, approaches, such as time-interleaving algorithm and modified Manchester encoding, are adopted. The main blocks in the DFE are implemented using standard cells with electronic design automation tools for synthesis and place and route. A CMCD PA with an ON-chip transformer is designed and integrated. This Class-S transmitter exhibits a 40-MHz bandwidth at up to a 1.6 GHz output carrier frequency. Measurements with a 1-MHz channel-spacing    $\pi $   /4 quadrature phase shift keying signal show a power control range of −18.66 to −4.65 dBm, and the power consumption of the    $\Sigma \Delta $    modulator core is 7 mW.
['Yang Zhao', 'Yilei Shen', 'Pan Xue', 'Zhiwei Ma', 'Zhenfei Peng', 'Baoxing Chen', 'Zhiliang Hong']
An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS