This paper describes a ratio-independent algorithmic ADC architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40 kS/s ADC with an active die area of 0.041 mm 2  is implemented in a 0.13 mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4 muW power dissipation, the ADC achieves 80.2 dB SFDR and 63.3 dB SNDR.
['Jere A. M. Järvinen', 'Mikko Saukoski', 'Kari Halonen']
A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface