This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences. To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured. This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead. Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach.
['Arno Kunzmann', 'Frank Boehland']
Self-test of sequential circuits with deterministic test pattern sequences