With transistor counts increasing at a rate of 58% per year and design productivity only growing at 21% per year, there is an important need to develop new design approaches to close this gap. This paper outlines the process by which IP cores are generated and shows how the design methodology can be improved to enhance their usability. The process is demonstrated using a recursive least squares (RLS) adaptive filter example.
['Gaye Lightbody', 'Roger F. Woods']
QR Recursive Least Squares IP Core Example