In this paper, we propose a Field Programmable Gate Array (FPGA) platform for spike time dependent encoder and dynamic reservoir in neuromorphic computing processors. Neuromorphic computing processors represent a type of non-traditional architecture encompassing evolutionary systems and hold great promise for many important engineering and scientific applications. The reservoir computing approach with dynamic reservoir is a paradigm in machine learning whose processing capabilities rely on the dynamical behavior of Recurrent Neural Networks (RNNs). It has made swift progress and development in both the theoretical realm and its subsequent implementations. However, most of the implementations are based on software, due to the difficulties in performing real-time training of the output weights on hardware platforms. The reservoir computing approach implemented in this paper utilizes the Echo State Network (ESN) architecture which includes a reservoir and its consequent training process. It can be trained and implemented in FPGA without any software cooperation. As FPGA is a digital logic platform and the information entered into a RNN is analog, we also propose an encoding circuit and an Analog to Digital Converter (ADC) to bridge this divide. The proposed method given for the realization of the neuromorphic computing chips, therefore, provides a viable option.
['Yang Yi', 'Yongbo Liao', 'Bin Wang', 'Xin Fu', 'Fangyang Shen', 'Hongyan Hou', 'Lingjia Liu']
FPGA based spike-time dependent encoder and reservoir design in neuromorphic computing processors