The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock tree design algorithm which is driven by the tolerance towards process variations. We consider tolerance to process variation in various stages of clock tree synthesis which include clock skew scheduling, abstract tree generation and layout embedding. The primary objective of this work is to minimize the maximum skew violation and a layout embedding technique specifically targeting this objective is detailed. Experimental results indicate that our proposed procedure leads to significant reduction in maximum skew violation due to process variation with negligible change in wire length.
['Ganesh Venkataraman', 'Cliff C. N. Sze', 'Jiang Hu']
Skew scheduling and clock routing for improved tolerance to process variations