Track-and-hold (TH) circuits in the front end of high-speed high-resolution analog-to-digital converters (ADCs) typically limit ADC performance at high input signal frequencies. This paper develops mathematical models for THs implemented in both bipolar and MOS technologies. The models are derived by analyzing the sampling instant error and reveal that the nonlinear behavior is dependent on the input signal and it's derivatives. A digital post compensation method is then presented with it's coefficients estimated using an energy-free method in a background calibration configuration. Simulation results on a nonlinear TH model show that the proposed method achieves a significant improvement in the spurious free dynamic range (SFDR). The method is also applied to a commercially available ADC to demonstrate it's effectiveness.
['Kun Shi', 'Arthur J. Redfern']
Digital compensation of sampling instant errors in the track-and-hold portion of an ADC