Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages and suitability of different design techniques utilizing forward body bias (FBB) capability available for FDSOI CMOS. Measured silicon results show >9dB performance improvement with FBB voltage range of 0–1.8V. Integrated body bias generator (BBGEN) ensures required voltages for FBB. This work measures the 60.7dB SINAD at Nyquist frequency achieving Walden FOM of 37.2fJ/conv-step and Schreier FOM of 162.5dB at 600MS/s. It is also achieving 57dB SINAD at 800Ms/s, >50dB SINAD up to 950MS/s and 58.5dB SINAD till 500Mhz input frequency.
['Ashish Kumar', 'Chandrajit Debnath', 'Pratap Narayan Singh', 'Vivek Bhatia', 'Shivani Chaudhary', 'Vigyan Jain', 'Stephane Le Tual', 'Rakesh Malik']
A 0.065mm 2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB