This paper presents a method to address the automatic testing of analog ICs for catastrophic defects. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automatically by a workflow based on DC simulations and optimization algorithms. Adopting a defect-oriented methodology, this approach maximizes the fault coverage while minimizing the silicon area overhead and test time. The proposed method is applied to two industrial circuits in order to generate optimal test infrastructures combining controllability and observability. These case studies show that, with a silicon area overhead of less than 10%, a fault coverage of 94.1% can be reached.
['Anthony Coyette', 'Baris Esen', 'Wim Dobbelaere', 'Ronny Vanhooren', 'Georges Gielen']
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization