This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The temporal channel for the Viterbi receiver and the beamformer weights for the CCI rejection are estimated jointly by optimizing a suitable cost function for separable space-time channels. By taking into account of the current integration capabilities provided by the FPGA (field programmable gate array), the feasibility of a single chip JSTE solution based on a three-processor architecture for carrier beamforming, equalization and demodulation is demonstrated.
['Uberto Girola', 'Agostino Picciriello', 'David Vincenzoni']
Smart antenna receiver for GSM/DCS system based on single chip solution