The paper introduces a novel methodology to obtain the entire area/power consumption versus delay tradeoff curve for the critical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the tradeoff curve, in this work only a subset of the Boolean network representing the circuit is optimized each time. Performance comparison and results based on the MCNC'91 set of two-level benchmark circuits are given. It is demonstrated that the proposed methodology produces tradeoff curves for large circuits of thousands of gates greatly reducing the computation complexity (measured in number of variables of an equivalent linear programming problem) by a factor up to 16 times.
['Javier Sosa', 'Juan A. Montiel-Nelson', 'Saeid Nooshabadi']
Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization