In this paper, we present an in-depth analysis of transient behavior, mainly glitches, in the parallel encoding and decoding circuits of error correcting codes. First, we found that the probability of a given number of glitches that may accumulate in the encoding/decoding circuit exhibits a Gaussian-like distribution. An estimation methodology was developed so the transient behavior of an ECC for very long word length can be predicted. We confirm that the principle of minimum-equal-weight construction of H-matrix is the best design strategy. Two potential solutions are proposed and examined to reduce the accumulation of glitches. Finally, we present the calculation methods and provide examples of odd-weight-column SEG-DED codes for up to 1024 information bits.
['Jien-Chung Lo', 'Yu-Lun Wan', 'Eiji Fujiwara']
Transient behavior of the encoding/decoding circuits of error correcting codes