Efforts to improve the resolution and power-efficiency of ADCs continue unabated, as is well documented in [2]. Although the number of new switched-capacitor (SC) ADC publications has declined over the years in favor of continuous-time designs, these circuits still remain attractive owing to their superior immunity to clock jitter and process variations. In this paper, we present three independent power optimization techniques realized by splitting the sampling capacitors, which are implemented in the first stage of the single-bit SC ΔΣ modulator shown in Fig. 15.8.1.
['Matthias Steiner', 'Nigel Greer']
15.8 A 22.3b 1kHz 12.7mW switched-capacitor ΔΣ modulator with stacked split-steering amplifiers