Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A compact, low por, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5/spl mu/m CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature variations. For this purpose, an accurate delayed clock is generated. Very simple structure besides MOSFET capacitors offers a compact and low por circuit. The area of the circuit is 0.08mm/sup 2/ while consumes 380/spl mu/A/sub rms/ from 5V por supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from the desired nominal value.
['Armin Tajalli', 'Abbas Khodaverdi', 'Seyed Mojtaba Atarodi']
I am writing a research paper on a idea A compact, low power, fully integrated clock frequency doubler
[{"from": "human", "value": "I am writing a research paper on a idea A compact, low power, fully integrated clock frequency doubler"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A compact, low por, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5/spl mu/m CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature variations. For this purpose, an accurate delayed clock is generated. Very simple structure besides MOSFET capacitors offers a compact and low por circuit. The area of the circuit is 0.08mm/sup 2/ while consumes 380/spl mu/A/sub rms/ from 5V por supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from the desired nominal value."}]