Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs).  review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems.  then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking   $\mu {\rm P}$   and high density cache memory, with   $> 2~{\rm GHz}$   operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50   $\mu{\rm m}$    pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1   $\mu{\rm m}$  . The paper concludes with comments on the challenges for future 3D DRAMs.
['Toshiaki Kirihata', 'John Golz', 'Matthew R. Wordeman', 'Pooja Batra', 'Gary Maier', 'Norman Robson', 'Troy Graves-Abe', 'Daniel Berger', 'Subramanian S. Iyer']
I am writing a research paper on a idea Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
[{"from": "human", "value": "I am writing a research paper on a idea Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs).  review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems.  then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking   $\\mu {\\rm P}$   and high density cache memory, with   $> 2~{\\rm GHz}$   operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50   $\\mu{\\rm m}$    pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1   $\\mu{\\rm m}$  . The paper concludes with comments on the challenges for future 3D DRAMs."}]