Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  focuses on compact and configurable multiple-valued (MV) encoders. For this purpose, a new cyclic D/A converter circuit using semi floating-gate (SFG) inverters is proposed. Slow conversion rates are considered a problem in cyclic D/A converters. A new algorithm called Dual Data Rate (DDR) mode of operation is introduced allowing two iterations per clock cycle instead of only one when using SFG inverters. The proposed converter is implemented in a double poly 0.35 mum process. Experimental results are provided for radix 4, 8 and 16. Operation of both clock edges using DDR mode of operation is demonstrated. This gives a significant improvement in terms of conversion rate and noise-margins.
['Renè Jensen', 'Yngvar Berg']
I am writing a research paper on a idea Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices
[{"from": "human", "value": "I am writing a research paper on a idea Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  focuses on compact and configurable multiple-valued (MV) encoders. For this purpose, a new cyclic D/A converter circuit using semi floating-gate (SFG) inverters is proposed. Slow conversion rates are considered a problem in cyclic D/A converters. A new algorithm called Dual Data Rate (DDR) mode of operation is introduced allowing two iterations per clock cycle instead of only one when using SFG inverters. The proposed converter is implemented in a double poly 0.35 mum process. Experimental results are provided for radix 4, 8 and 16. Operation of both clock edges using DDR mode of operation is demonstrated. This gives a significant improvement in terms of conversion rate and noise-margins."}]