Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Complicated approaches to fault-tolerant voltage-scalable (FTVS) SRAM cache architectures can suffer from high overheads.  propose static (SPCS) and dynamic (DPCS) variants of por/capacity scaling, a simple and low-overhead fault-tolerant cache architecture that utilizes insights gained from our 45nm SOI test chip. Our mechanism combines multi-level voltage scaling with por gating of blocks that become faulty at each voltage level. The SPCS policy sets the runtime cache VDD statically such that almost all of the cache blocks are not faulty. The DPCS policy opportunistically reduces the voltage further to save more por than SPCS while limiting the impact on performance caused by additional faulty blocks. Through an analytical evaluation,  show that our approach can achieve lor static por for all effective cache capacities than a recent complex FTVS work. This is due to significantly lor overheads, despite the failure of our approach to match the min-VDD of the competing work at fixed yield. Through architectural simulations,  find that the average energy saved by SPCS is 55%, while DPCS saves an average of 69% of energy with respect to baseline caches at 1 V. Our approach incurs no more than 4% performance and 5% area penalties in the worst case cache configuration.
['Mark Gottscho', 'Abbas BanaiyanMofrad', 'Nikil Dutt', 'Alex Nicolau', 'Puneet Gupta']
I am writing a research paper on a idea Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches
[{"from": "human", "value": "I am writing a research paper on a idea Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Complicated approaches to fault-tolerant voltage-scalable (FTVS) SRAM cache architectures can suffer from high overheads.  propose static (SPCS) and dynamic (DPCS) variants of por/capacity scaling, a simple and low-overhead fault-tolerant cache architecture that utilizes insights gained from our 45nm SOI test chip. Our mechanism combines multi-level voltage scaling with por gating of blocks that become faulty at each voltage level. The SPCS policy sets the runtime cache VDD statically such that almost all of the cache blocks are not faulty. The DPCS policy opportunistically reduces the voltage further to save more por than SPCS while limiting the impact on performance caused by additional faulty blocks. Through an analytical evaluation,  show that our approach can achieve lor static por for all effective cache capacities than a recent complex FTVS work. This is due to significantly lor overheads, despite the failure of our approach to match the min-VDD of the competing work at fixed yield. Through architectural simulations,  find that the average energy saved by SPCS is 55%, while DPCS saves an average of 69% of energy with respect to baseline caches at 1 V. Our approach incurs no more than 4% performance and 5% area penalties in the worst case cache configuration."}]