Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies.  presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low por consumption would continue to be an important design goal.  first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low por NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times.  next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize por as the primary goal, and minimize the number of routers (area) as a secondary goal.  present an analysis of the quality of the results and the solution times of the proposed techniques by extensive experimentation with the realistic benchmarks. The clustering based heuristic generates results whose por consumption is within 11% of the MILP solutions and its average run time is 171.1 seconds. The average run time of the relaxation and rounding based techniques is less than 2 seconds, and the por consumption of their solutions is within 58% of the MILP result.
['Krishnan Srinivasan', 'Karam S. Chatha', 'Goran Konjevod']
I am writing a research paper on a idea Linear programming based techniques for synthesis of network-on-chip architectures
[{"from": "human", "value": "I am writing a research paper on a idea Linear programming based techniques for synthesis of network-on-chip architectures"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Network-on-chip (NoC) has been proposed as a solution for the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies.  presents novel linear programming based techniques for synthesis of custom NoC architectures. In the nanoscale regime, low por consumption would continue to be an important design goal.  first discuss an optimal mixed integer linear programming (MILP) formulation that synthesizes a low por NoC architecture subject to the performance constraints. The MILP formulation is limited by large run times.  next present heuristic techniques that exploit clustering, and 0-1 constraint relaxation to reduce the run times of the formulation. The techniques minimize por as the primary goal, and minimize the number of routers (area) as a secondary goal.  present an analysis of the quality of the results and the solution times of the proposed techniques by extensive experimentation with the realistic benchmarks. The clustering based heuristic generates results whose por consumption is within 11% of the MILP solutions and its average run time is 171.1 seconds. The average run time of the relaxation and rounding based techniques is less than 2 seconds, and the por consumption of their solutions is within 58% of the MILP result."}]