Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: On-chip L1 and L2 caches represent a sizeable fraction of the total por consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage por is becoming one of the dominant total por consumption components of those caches. In this study,  present optimization techniques to reduce the subthreshold leakage por of on-chip caches assuming that there are multiple threshold voltages, V/sub T/'s, available. First,  show a cache leakage optimization technique that examines the tradeoff beten access time and subthreshold leakage por by assigning distinct V/sub T/'s to each of the four main cache components-address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second,  show optimization techniques to reduce the leakage por of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high V/sub T/'s are enough to minimize leakage in a single cache-3 V/sub T/'s if  include a nominal low V/sub T/ for microprocessor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lor leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lor leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic por reduction without affecting the average memory access time.
['Nam Sung Kim', 'David Blaauw', 'Trevor N. Mudge']
I am writing a research paper on a idea Quantitative analysis and optimization techniques for on-chip cache leakage power
[{"from": "human", "value": "I am writing a research paper on a idea Quantitative analysis and optimization techniques for on-chip cache leakage power"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: On-chip L1 and L2 caches represent a sizeable fraction of the total por consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage por is becoming one of the dominant total por consumption components of those caches. In this study,  present optimization techniques to reduce the subthreshold leakage por of on-chip caches assuming that there are multiple threshold voltages, V/sub T/'s, available. First,  show a cache leakage optimization technique that examines the tradeoff beten access time and subthreshold leakage por by assigning distinct V/sub T/'s to each of the four main cache components-address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second,  show optimization techniques to reduce the leakage por of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high V/sub T/'s are enough to minimize leakage in a single cache-3 V/sub T/'s if  include a nominal low V/sub T/ for microprocessor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lor leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lor leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic por reduction without affecting the average memory access time."}]