Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. ,  present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC'91 benchmarks show that large fractions of faults in most of the MCNC'91 benchmarks are redundant.
['Ramesh C. Tekumalla', 'Premachandran R. Menon']
I am writing a research paper on a idea On redundant path delay faults in synchronous sequential circuits
[{"from": "human", "value": "I am writing a research paper on a idea On redundant path delay faults in synchronous sequential circuits"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. ,  present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC'91 benchmarks show that large fractions of faults in most of the MCNC'91 benchmarks are redundant."}]