Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Low-por is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant por saving over 2-D ICs. Hover, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper,  extend our target to three-tier (3-tier) 3-D ICs.  first shows that the one additional tier available in 3-tier 3-D ICs does offer more por saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second,  find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined.  shows that these choices pose additional challenges in design optimizations for more por saving. Lastly,  develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC por optimization under various bonding style options. With our low-por design methods combined, our 3-tier 3-D ICs provide −14.8% more por reduction over 2-tier 3-D ICs, and −36.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide −27.2% more por reduction over 2-D ICs.
['Taigon Song', 'Shreepad Panth', 'Yoo-Jin Chae', 'Sung Kyu Lim']
I am writing a research paper on a idea More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs
[{"from": "human", "value": "I am writing a research paper on a idea More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Low-por is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant por saving over 2-D ICs. Hover, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper,  extend our target to three-tier (3-tier) 3-D ICs.  first shows that the one additional tier available in 3-tier 3-D ICs does offer more por saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second,  find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined.  shows that these choices pose additional challenges in design optimizations for more por saving. Lastly,  develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC por optimization under various bonding style options. With our low-por design methods combined, our 3-tier 3-D ICs provide \u221214.8% more por reduction over 2-tier 3-D ICs, and \u221236.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide \u221227.2% more por reduction over 2-D ICs."}]