Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As technology scales to 45nm and below, the deviation beten predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lor cost compared to using external expensive testers. ,  propose a novel path delay measurement architecture called Enhanced path-based ring oscillator (Path-RO) that takes into account variations. The proposed Enhanced Path-RO can accurately and quickly measure path delay on-chip under variations with nearly no impact on functional data path. Enhanced Path-RO is perfectly suitable for fast and accurate speed binning as ll by targeting speed paths on-chip even in presence of clock skew. Simulation results under variations collected by the Enhanced Path-RO inserted into ITC'99 b19 circuit demonstrate its high accuracy and efficiency.
['Xiaoxiao Wang', 'Mohammad Tehranipoor', 'Ramyanshu Datta']
I am writing a research paper on a idea A novel architecture for on-chip path delay measurement
[{"from": "human", "value": "I am writing a research paper on a idea A novel architecture for on-chip path delay measurement"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As technology scales to 45nm and below, the deviation beten predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lor cost compared to using external expensive testers. ,  propose a novel path delay measurement architecture called Enhanced path-based ring oscillator (Path-RO) that takes into account variations. The proposed Enhanced Path-RO can accurately and quickly measure path delay on-chip under variations with nearly no impact on functional data path. Enhanced Path-RO is perfectly suitable for fast and accurate speed binning as ll by targeting speed paths on-chip even in presence of clock skew. Simulation results under variations collected by the Enhanced Path-RO inserted into ITC'99 b19 circuit demonstrate its high accuracy and efficiency."}]