Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as ll as por efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in por dissipation and 2X (approximately) in leakage.
['Jawar Singh', 'Jimson Mathew', 'Saraju P. Mohanty', 'Dhiraj K. Pradhan']
I am writing a research paper on a idea A nano-CMOS process variation induced read failure tolerant SRAM cell
[{"from": "human", "value": "I am writing a research paper on a idea A nano-CMOS process variation induced read failure tolerant SRAM cell"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as ll as por efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in por dissipation and 2X (approximately) in leakage."}]