Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The authors present a testability strategy for complex VLSI devices which is implemented in the PIRAMID Digital Signal Processor Silicon Compiler. The macrotest methodology supports built-in self-test, scan test, bus test control, restricted partial scan and test control logic at various levels in the design hierarchy. A set of testability design rules is developed and implemented automatically in the design. The design hierarchy is closely follod, resulting in a hierarchical set of testable macros. The complete process from design to final test program is guided by software tools. As an example, the synthesis of a large industrial circuit is presented for comparing the proposed approach with the traditional approaches. The additional overhead due to testability is within reasonable limits (roughly 8%), and the software run time figures show that it is possible to generate a test program with an excellent fault coverage within a very short period of time. >
['F. P. M. Beenker', 'R. Dekker', 'R. Stans', 'M. van der Star']
I am writing a research paper on a idea A testability strategy for silicon compilers
[{"from": "human", "value": "I am writing a research paper on a idea A testability strategy for silicon compilers"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The authors present a testability strategy for complex VLSI devices which is implemented in the PIRAMID Digital Signal Processor Silicon Compiler. The macrotest methodology supports built-in self-test, scan test, bus test control, restricted partial scan and test control logic at various levels in the design hierarchy. A set of testability design rules is developed and implemented automatically in the design. The design hierarchy is closely follod, resulting in a hierarchical set of testable macros. The complete process from design to final test program is guided by software tools. As an example, the synthesis of a large industrial circuit is presented for comparing the proposed approach with the traditional approaches. The additional overhead due to testability is within reasonable limits (roughly 8%), and the software run time figures show that it is possible to generate a test program with an excellent fault coverage within a very short period of time. >"}]