Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A memory bandwidth efficient architecture for AVS encoder is proposed in this paper. First, simplified ME (motion estimation) algorithms are designed to reduce the memory and bandwidth cost. Then a data reuse method with simple control mechanism is proposed to increase the utilization of on-chip memory. The proposed architecture efficiently reduces the bandwidth and memory consumption with acceptable degradation in coding performance. The encoder is implemented with 640 K logic gates in 0.18 mu m 2  CMOS technology and can satisfy real time encoding of 720 times576 4:2:0 25 fps AVS video at the working frequency of 108 MHz.
['Dandan Ding', 'Shuo Yao', 'Lu Yu']
I am writing a research paper on a idea Memory bandwidth efficient hardware architecture for AVS encoder
[{"from": "human", "value": "I am writing a research paper on a idea Memory bandwidth efficient hardware architecture for AVS encoder"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A memory bandwidth efficient architecture for AVS encoder is proposed in this paper. First, simplified ME (motion estimation) algorithms are designed to reduce the memory and bandwidth cost. Then a data reuse method with simple control mechanism is proposed to increase the utilization of on-chip memory. The proposed architecture efficiently reduces the bandwidth and memory consumption with acceptable degradation in coding performance. The encoder is implemented with 640 K logic gates in 0.18 mu m 2  CMOS technology and can satisfy real time encoding of 720 times576 4:2:0 25 fps AVS video at the working frequency of 108 MHz."}]