Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lor the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm 2 . The measured por consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively.
['Chi-Nan Chuang', 'Shen-Iuan Liu']
I am writing a research paper on a idea A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop
[{"from": "human", "value": "I am writing a research paper on a idea A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 20-MHz to 3-GHz wide-range multiphase delay-locked loop (DLL) has been realized in 90-nm CMOS technology. The proposed delay cell extends the operation frequency range. A scaling circuit is adopted to lor the large delay gain when the frequency of the input clock is low. The core area of this DLL is 0.005 mm 2 . The measured por consumption values are 0.4 and 3.6 mW for input clocks of 20 MHz and 3 GHz, respectively. The measured peak-to-peak and root-mean-square jitters are 2.3 and 16 ps at 3 GHz, respectively."}]