Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Connected component labeling of a binary image is an indispensable task for image segmentation and analysis. For real time video object segmentation, total processing time to label all the objects of an entire image is critical as it is constrained by inter frame temporal difference. Parallel dedicated hardware is necessary to solve this problem in real time.   have proposed a parallel VLSI architecture for fast connected component labeling of a binary video frame image.  have adopted a seeded region-growing algorithm, which is implemented in a state machine based cell network. The design is verified in XILINX FPGA with real time video image data containing different objects with different shapes and sizes. The worst-case labeling time for a full video frame is 5 ms (using a 32 MHz clock), which is ll below the required inter frame timing interval of 40 ms.
['P. K. Roy', 'Prabir Kumar Biswas']
I am writing a research paper on a idea VLSI Implementation of Fast Connected Component Labeling Using Finite State Machine Based Cell Network
[{"from": "human", "value": "I am writing a research paper on a idea VLSI Implementation of Fast Connected Component Labeling Using Finite State Machine Based Cell Network"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Connected component labeling of a binary image is an indispensable task for image segmentation and analysis. For real time video object segmentation, total processing time to label all the objects of an entire image is critical as it is constrained by inter frame temporal difference. Parallel dedicated hardware is necessary to solve this problem in real time.   have proposed a parallel VLSI architecture for fast connected component labeling of a binary video frame image.  have adopted a seeded region-growing algorithm, which is implemented in a state machine based cell network. The design is verified in XILINX FPGA with real time video image data containing different objects with different shapes and sizes. The worst-case labeling time for a full video frame is 5 ms (using a 32 MHz clock), which is ll below the required inter frame timing interval of 40 ms."}]