Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Advance Encryption Standard (AES) hardware implementation in FPGA as ll as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). Hover, low area designs have also been investigated in recent years for the embedded hardware applications.  presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.
['Chi Jeng Chang', 'Chi Wu Huang', 'Kuo Huang Chang', 'Yi G. Chen', 'Chung Cheng Hsieh']
I am writing a research paper on a idea High throughput 32-bit AES implementation in FPGA
[{"from": "human", "value": "I am writing a research paper on a idea High throughput 32-bit AES implementation in FPGA"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Advance Encryption Standard (AES) hardware implementation in FPGA as ll as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). Hover, low area designs have also been investigated in recent years for the embedded hardware applications.  presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature."}]