Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes and explores the design space of a four por-supply rail methodology (called Mixed Swing QuadRail) for performing low voltage logic in a high threshold voltage CMOS fabrication process. Por and delay trade-offs are studied to suggest approaches for efficient selection of voltage levels and buffer transistor sizes. Polynomial models for QuadRail por and delay are derived to show that at reduced I/O swings (sub-1 V), both under- and over-sizing of transistors can lead to steeply increased delays. Transistor sizing techniques are proposed for optimizing delay and energy per logic operation as a function of load capacitance and voltage levels. Experimental results from detailed HSPICE simulations and an And-Or-Invert (AOI222) QuadRail test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to support the models and demonstrate significant por reduction compared to static CMOS.
['Ram K. Krishnamurthy', 'Ihor A. Lys', 'L.R. Carley']
I am writing a research paper on a idea Static power driven voltage scaling and delay driven buffer sizing in Mixed Swing QuadRail for sub-1 V I/O swings
[{"from": "human", "value": "I am writing a research paper on a idea Static power driven voltage scaling and delay driven buffer sizing in Mixed Swing QuadRail for sub-1 V I/O swings"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes and explores the design space of a four por-supply rail methodology (called Mixed Swing QuadRail) for performing low voltage logic in a high threshold voltage CMOS fabrication process. Por and delay trade-offs are studied to suggest approaches for efficient selection of voltage levels and buffer transistor sizes. Polynomial models for QuadRail por and delay are derived to show that at reduced I/O swings (sub-1 V), both under- and over-sizing of transistors can lead to steeply increased delays. Transistor sizing techniques are proposed for optimizing delay and energy per logic operation as a function of load capacitance and voltage levels. Experimental results from detailed HSPICE simulations and an And-Or-Invert (AOI222) QuadRail test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to support the models and demonstrate significant por reduction compared to static CMOS."}]