Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or ar out in the field would potentially also cripple the clock distribution network. Consequently,  should start considering also path (min) delay faults when designing on-line testable circuits, similar to what  currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults.
['Cecilia Metra', 'Martin Omana', 'Daniele Rossi', 'José Manuel Cazeaux', 'T. M. Mak']
I am writing a research paper on a idea Path (min) delay faults and their impact on self-checking circuits operation
[{"from": "human", "value": "I am writing a research paper on a idea Path (min) delay faults and their impact on self-checking circuits operation"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently, as burn-in becomes ineffective and process variations become more of an issue, latent defects, device degradation or ar out in the field would potentially also cripple the clock distribution network. Consequently,  should start considering also path (min) delay faults when designing on-line testable circuits, similar to what  currently do for path (max) delay faults. The challenges that this poses to the existing on-line testing strategies are discussed. Examples showing the possible incorrect behavior of a self-checking circuit as a result of this kind of faults are given. New on-line testing strategies should consequently be devised to deal with these faults."}]