Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (DeltaSigma) fractional-N PLL. The proposed method improves the PLL linearity by forcing the PFD/CP to operate in a linear part of its transfer characteristic; while the CP circuit minimizes the current mismatch beten the up and down currents by feedback. These circuit techniques are employed in the design of a 2.4-GHz DeltaSigma fractional-N PLL. This chip has been fabricated in the TSMC 0.18-mum CMOS process. The experimental results demonstrate that the proposed techniques considerably improve the fractional-N PLL performance. This fully-integrated PLL dissipate 22 mW under a 1.8-V supply.
['Ching-Lung Ti', 'Yao-Hong Liu', 'Tsung-Hsien Lin']
I am writing a research paper on a idea A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit
[{"from": "human", "value": "I am writing a research paper on a idea A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (DeltaSigma) fractional-N PLL. The proposed method improves the PLL linearity by forcing the PFD/CP to operate in a linear part of its transfer characteristic; while the CP circuit minimizes the current mismatch beten the up and down currents by feedback. These circuit techniques are employed in the design of a 2.4-GHz DeltaSigma fractional-N PLL. This chip has been fabricated in the TSMC 0.18-mum CMOS process. The experimental results demonstrate that the proposed techniques considerably improve the fractional-N PLL performance. This fully-integrated PLL dissipate 22 mW under a 1.8-V supply."}]