Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  reports a high-performance low-por and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADC's ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any por consuming Vcm generation circuit, making it more suitable for low-por System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-um CMOS technology. Operating at 1.0 V por supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average por consumption is 1.72 μW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step.
['Chao Yuan', 'Kian Ann Ng', 'Yong Ping Xu', 'Shih Cheng Yen', 'Nitish V. Thakor']
I am writing a research paper on a idea A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition
[{"from": "human", "value": "I am writing a research paper on a idea A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  reports a high-performance low-por and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADC's ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any por consuming Vcm generation circuit, making it more suitable for low-por System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-um CMOS technology. Operating at 1.0 V por supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average por consumption is 1.72 \u03bcW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step."}]