Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present two major extensions to the implementation of simulated annealing for row-based placement which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation time ever reported for remotely comparable results. Our results indicate that chip area reductions up to 16% can be expected, compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement program yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. In comparison to the Gordian/Domino program, our new program yields total wire lengths which are always lor (up to 9% lor) and our program is always faster for circuits with more than 5000 cells (which represents the range of circuit sizes of interest).
['Wern-Jieh Sun', 'Carl Sechen']
I am writing a research paper on a idea Efficient and effective placement for very large circuits
[{"from": "human", "value": "I am writing a research paper on a idea Efficient and effective placement for very large circuits"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present two major extensions to the implementation of simulated annealing for row-based placement which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation time ever reported for remotely comparable results. Our results indicate that chip area reductions up to 16% can be expected, compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement program yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. In comparison to the Gordian/Domino program, our new program yields total wire lengths which are always lor (up to 9% lor) and our program is always faster for circuits with more than 5000 cells (which represents the range of circuit sizes of interest)."}]