Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR gate and NAND gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR gate and the NAND gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears beten two devices connected in series. The results compared ll with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz.
['Michael Walter Payton', 'Fat Duen Ho']
I am writing a research paper on a idea A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate
[{"from": "human", "value": "I am writing a research paper on a idea A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The primary goal of this work is to develop a low-level physics-based nonquasi-static MOSFET model that can be extended to the simulation of high-level CMOS logic circuits. In this part of our papers (part II), the results of using our model described in the companion paper (submitted to ibid) to simulate the CMOS NOR gate and NAND gate are presented. The numerical methods discussed in the companion paper are applied in the simulations for the NOR gate and the NAND gate. In addition, a bisection root finding algorithm is used to calculate any junction voltage that appears beten two devices connected in series. The results compared ll with those obtained from the SPICE level 3 and SPICE level 7 (BSIM 3.1) for a wide range of device geometries and circuit loading conditions. The results show that our model is capable of accurately simulating the transient response of devices with channel lengths as small as 0.33 /spl mu/m and for switching frequencies approaching 1 GHz."}]