Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm/sup 2/.
['Janusz A. Starzyk', 'Russell P. Mohn', 'Liang Jing']
I am writing a research paper on a idea A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell
[{"from": "human", "value": "I am writing a research paper on a idea A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-/spl mu/m six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm/sup 2/."}]