Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low por personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Por consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm × 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error.
['Ji-Hoon Park', 'Brian C. Richards', 'Borivoje Nikolic']
I am writing a research paper on a idea A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band
[{"from": "human", "value": "I am writing a research paper on a idea A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The wide unlicensed bandwidth of a 60 GHz channel presents an attractive opportunity for high data rate and low por personal area networks (PANs). The use of single-carrier modulation can yield energy-efficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a significant challenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Por consumption is minimized by using a parallelized distributed arithmetic (DA) architecture. A 2 mm \u00d7 2 mm test chip in 65nm CMOS implements a 6 tap feedforward and 32 tap feedback equalizer that can be configured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip also includes a channel estimator based on a Golay correlator for setting the equalizer coefficients and estimating frequency and timing error."}]