Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Previously suggested transistor sizing algorithms assume that all input transitions are equally important. In this work  show that this is not an accurate assumption as input transitions appear in different frequencies.  take advantage from this phenomenon and introduce Application Specific Transistor Sizing. In Application Specific Transistor Sizing higher priority is given to more frequent transitions.  apply our technique to two modern and low-por full adders (i.e., hybrid-CMOS and TFA) and show that it is possible to further reduce por dissipation and PDP. By using our technique  improve average PDP by 6% and 9% for TFA and hybrid-CMOS adders respectively.  reduce ALU energy consumption for ALU designs using TFA and hybrid-CMOS FAs by 2.7% and 4 % respectively.
['Fatemeh Eslami', 'Amirali Baniasadi', 'Mostafa Farahani']
I am writing a research paper on a idea Application Specific Transistor Sizing for Low Power Full Adders
[{"from": "human", "value": "I am writing a research paper on a idea Application Specific Transistor Sizing for Low Power Full Adders"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Previously suggested transistor sizing algorithms assume that all input transitions are equally important. In this work  show that this is not an accurate assumption as input transitions appear in different frequencies.  take advantage from this phenomenon and introduce Application Specific Transistor Sizing. In Application Specific Transistor Sizing higher priority is given to more frequent transitions.  apply our technique to two modern and low-por full adders (i.e., hybrid-CMOS and TFA) and show that it is possible to further reduce por dissipation and PDP. By using our technique  improve average PDP by 6% and 9% for TFA and hybrid-CMOS adders respectively.  reduce ALU energy consumption for ALU designs using TFA and hybrid-CMOS FAs by 2.7% and 4 % respectively."}]