Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison beten the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lor fault coverage, in particular when considering circuits with hard to detect faults.
['Fabrizio Ferrandi', 'Franco Fummi', 'Donatella Sciuto']
I am writing a research paper on a idea Implicit test generation for behavioral VHDL models
[{"from": "human", "value": "I am writing a research paper on a idea Implicit test generation for behavioral VHDL models"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison beten the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lor fault coverage, in particular when considering circuits with hard to detect faults."}]