Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits with feedback (finite state machines). Operating on the delay critical paths of the circuit,  perform a set of controlled local retimings of registers across fanout stems and logic gates, follod by local node simplifications.  guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification.  strive to minimize the increase in number of registers without sacrificing the cycle-time performance. The results demonstrate a favourable performance/area trade-off when compared with optimally retimed circuits.
['Priyank Kalla', 'Maciej J. Ciesielski']
I am writing a research paper on a idea Performance driven resynthesis by exploiting retiming-induced state register equivalence
[{"from": "human", "value": "I am writing a research paper on a idea Performance driven resynthesis by exploiting retiming-induced state register equivalence"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits with feedback (finite state machines). Operating on the delay critical paths of the circuit,  perform a set of controlled local retimings of registers across fanout stems and logic gates, follod by local node simplifications.  guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification.  strive to minimize the increase in number of registers without sacrificing the cycle-time performance. The results demonstrate a favourable performance/area trade-off when compared with optimally retimed circuits."}]