Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to ∼4nm.
['T. Chiarella', 'S. Kubicek', 'Erik Rosseel', 'Romain Ritzenthaler', 'Andriy Hikavyy', 'Pierre Eyben', 'A. De Keersgieter', 'L.-A. Ragnarsson', 'Min-Soo Kim', 'Soon Aik Chew', 'Tom Schram', 'S. Demuynck', 'M. Cupak', 'L. Rijnders', 'Morin Dehan', 'Naoto Horiguchi', 'Jerome Mitard', 'D. Mocuta', 'Anda Mocuta', 'A. V-Y. Thean']
I am writing a research paper on a idea Towards high performance sub-10nm finW bulk FinFET technology
[{"from": "human", "value": "I am writing a research paper on a idea Towards high performance sub-10nm finW bulk FinFET technology"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to \u223c4nm."}]