Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock gating is one of the most effective techniques to reduce clock network por dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wirelength overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous design flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted. In this work,  propose a new design flow for low por gated clock network construction, in order to minimize the clock wirelength and the activity of control signals, and to eliminate the overlaps incurred by the gate logics. Our method begins with a coarse placement follod by soft register clustering. Then,  perform clock tree topology construction and zero skew clock routing to further reduce the por and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware register placement in clock wirelength and clock por reduction with signal nets wirelength and signal nets por increase within 5% and 3%, respectively
['Weixiang Shen', 'Yici Cai', 'Xianlong Hong', 'Jiang Hu']
I am writing a research paper on a idea Activity and register placement aware gated clock network design
[{"from": "human", "value": "I am writing a research paper on a idea Activity and register placement aware gated clock network design"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock gating is one of the most effective techniques to reduce clock network por dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wirelength overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous design flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted. In this work,  propose a new design flow for low por gated clock network construction, in order to minimize the clock wirelength and the activity of control signals, and to eliminate the overlaps incurred by the gate logics. Our method begins with a coarse placement follod by soft register clustering. Then,  perform clock tree topology construction and zero skew clock routing to further reduce the por and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware register placement in clock wirelength and clock por reduction with signal nets wirelength and signal nets por increase within 5% and 3%, respectively"}]