Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing.  also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed.  present results on synthetic stacks created from ITC’99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and por overhead. Results show that the overhead due to BIST is negligible.  also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and por constraints, and use two algorithms based on bin packing for solving the problem.
['Mukesh Agrawal', 'Krishnendu Chakrabarty', 'Bill Eklow']
I am writing a research paper on a idea A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs
[{"from": "human", "value": "I am writing a research paper on a idea A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing.  also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed.  present results on synthetic stacks created from ITC\u201999 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and por overhead. Results show that the overhead due to BIST is negligible.  also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and por constraints, and use two algorithms based on bin packing for solving the problem."}]