Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency when applying a known in situ error-detection and correction technique, called Razor, to DSP datapaths. Timing errors are detected using Razor flip-flops at critical-path endpoints and the error-rate feedback is used to control a dynamic voltage scaling (DVS) control loop.  propose a new approach to bound the magnitude of intermittent timing errors at the circuit level by introducing a guard-band over which timing errors are safely mitigated. The guard-band is achieved by shaping the path delay distribution such that the critical paths correspond to a group of LSB result registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder and by using tool-based device sizing. Hence, timing violations lead to akly correlated logical errors of small magnitude in a mean-squared-error sense.  applied this approach to a digital filter in 32nm CMOS. Por saving compared to a conventional design was 23%, over worst-case process and temperature corners. © 2011 ACM.
['Paul N. Whatmough', 'Shidhartha Das', 'David Michael Bull', 'Izzat Darwazeh']
I am writing a research paper on a idea Error-resilient low-power DSP via path-delay shaping
[{"from": "human", "value": "I am writing a research paper on a idea Error-resilient low-power DSP via path-delay shaping"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency when applying a known in situ error-detection and correction technique, called Razor, to DSP datapaths. Timing errors are detected using Razor flip-flops at critical-path endpoints and the error-rate feedback is used to control a dynamic voltage scaling (DVS) control loop.  propose a new approach to bound the magnitude of intermittent timing errors at the circuit level by introducing a guard-band over which timing errors are safely mitigated. The guard-band is achieved by shaping the path delay distribution such that the critical paths correspond to a group of LSB result registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder and by using tool-based device sizing. Hence, timing violations lead to akly correlated logical errors of small magnitude in a mean-squared-error sense.  applied this approach to a digital filter in 32nm CMOS. Por saving compared to a conventional design was 23%, over worst-case process and temperature corners. \u00a9 2011 ACM."}]