Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Physical-synthesis tools are responsible for achieving timing closure. Starting with 130-nm designs, multiple cycles are required to cross the chip, making latch placement critical to success.  present a new physical-synthesis optimization for latch placement called Rip Up and Move Boxes with Linear Evaluation (RUMBLE) that uses a linear timing model to optimize timing by simultaneously replacing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: Our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design.
['David A. Papa', 'Tao Luo', 'Michael D. Moffitt', 'Chin Ngai Sze', 'Zhuo Li', 'Gi-Joon Nam', 'Charles J. Alpert', 'Igor L. Markov']
I am writing a research paper on a idea RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
[{"from": "human", "value": "I am writing a research paper on a idea RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Physical-synthesis tools are responsible for achieving timing closure. Starting with 130-nm designs, multiple cycles are required to cross the chip, making latch placement critical to success.  present a new physical-synthesis optimization for latch placement called Rip Up and Move Boxes with Linear Evaluation (RUMBLE) that uses a linear timing model to optimize timing by simultaneously replacing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effectiveness of the approach: Our techniques improve slack by 41.3% of cycle time on average for a large commercial ASIC design."}]