Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO)  would like to get fast and accurate estimations of different performance measures of the chip, namely area, delay and por consumption. These measures cannot be estimated with high accuracy unless a fairly detailed layout of the chip, including the floorplan and routing is available, which in turn are very costly processes in terms of running time. As  have entered the deep sub-micron era,  have to deal with designs which contain million gates and up. Not only  should consider the area occupied by the modules, but  also have to consider the wiring congestion.   propose a cost function that is, in addition to other parameters, a function of the wiring area.  also propose a method, to avoid running the floorplanning process after  every  change in the design, by considering the possible changes in advance and generating a floorplan which is  tolerant  to these modifications, i.e., the changes in the netlist does not dramatically change the performance measures of the chip. Experiments are done in the high-level synthesis domain, but the method can be applied to logic synthesis and ECO as ll.  gain speedups of 184% on the average over the traditional estimation methods used in HLS.
['Kiarash Bazargan', 'Abhishek Ranjan', 'Majid Sarrafzadeh']
I am writing a research paper on a idea Fast and accurate estimation of floorplans in logic/high-level synthesis
[{"from": "human", "value": "I am writing a research paper on a idea Fast and accurate estimation of floorplans in logic/high-level synthesis"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO)  would like to get fast and accurate estimations of different performance measures of the chip, namely area, delay and por consumption. These measures cannot be estimated with high accuracy unless a fairly detailed layout of the chip, including the floorplan and routing is available, which in turn are very costly processes in terms of running time. As  have entered the deep sub-micron era,  have to deal with designs which contain million gates and up. Not only  should consider the area occupied by the modules, but  also have to consider the wiring congestion.   propose a cost function that is, in addition to other parameters, a function of the wiring area.  also propose a method, to avoid running the floorplanning process after  every  change in the design, by considering the possible changes in advance and generating a floorplan which is  tolerant  to these modifications, i.e., the changes in the netlist does not dramatically change the performance measures of the chip. Experiments are done in the high-level synthesis domain, but the method can be applied to logic synthesis and ECO as ll.  gain speedups of 184% on the average over the traditional estimation methods used in HLS."}]