Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Demands for the low por VLSI have been pushing the aggressive design methodologies to reduce the por consumption drastically. To meet the growing demand,  propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion.  achieved 26% por improvement on a 128-bit CSA prototype over a conventional design with same performance.
['Hiroaki Suzuki', 'Woopyo Jeong', 'Kaushik Roy']
I am writing a research paper on a idea Low-power carry-select adder using adaptive supply voltage based on input vector patterns
[{"from": "human", "value": "I am writing a research paper on a idea Low-power carry-select adder using adaptive supply voltage based on input vector patterns"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Demands for the low por VLSI have been pushing the aggressive design methodologies to reduce the por consumption drastically. To meet the growing demand,  propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion.  achieved 26% por improvement on a 128-bit CSA prototype over a conventional design with same performance."}]