Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Por consumption during scan-based test becomes a concern in nanometer technologies. Previous test por reduction techniques that insert additional logic in gate-level circuits may result in timing violations. ,  show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously,  identify por-sensitive scan cells at the prototyping gate level, and  map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these por- sensitive bits in order to reduce scan shift por consumption. Experimental results on ITC99 benchmarks show that on average more than 22% por reduction can be achieved when  only freeze the top 1% of por-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.
['Elif Alpaslan', 'Yu Huang', 'Xijiang Lin', 'Wu-Tung Cheng', 'Jennifer Dworak']
I am writing a research paper on a idea Reducing Scan Shift Power at RTL
[{"from": "human", "value": "I am writing a research paper on a idea Reducing Scan Shift Power at RTL"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Por consumption during scan-based test becomes a concern in nanometer technologies. Previous test por reduction techniques that insert additional logic in gate-level circuits may result in timing violations. ,  show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously,  identify por-sensitive scan cells at the prototyping gate level, and  map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these por- sensitive bits in order to reduce scan shift por consumption. Experimental results on ITC99 benchmarks show that on average more than 22% por reduction can be achieved when  only freeze the top 1% of por-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level."}]