Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. ,  present a production-friendly method that takes the circuit topology into account while generating patterns for SDDs. Experimental results on several IWLS’05 benchmark and six industrial circuits show that compared to the default timing-aware pattern set, the proposed method reduces pattern count an average of 172% for IWLS benchmarks and an average of 105% for industrial circuits.  demonstrate the production-worthiness of our approach by using several quality metrics and showing that the proposed method provides similar or higher coverage for SDDs compared to the default timing-aware ATPG, but only with a significantly small number of test patterns and in significantly small run time.
['Sandeep Kumar Goel', 'Krishnendu Chakrabarty', 'Mahmut Yilmaz', 'Ke Peng', 'Mohammad Tehranipoor']
I am writing a research paper on a idea Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
[{"from": "human", "value": "I am writing a research paper on a idea Circuit Topology-Based Test Pattern Generation for Small-Delay Defects"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. ,  present a production-friendly method that takes the circuit topology into account while generating patterns for SDDs. Experimental results on several IWLS\u201905 benchmark and six industrial circuits show that compared to the default timing-aware pattern set, the proposed method reduces pattern count an average of 172% for IWLS benchmarks and an average of 105% for industrial circuits.  demonstrate the production-worthiness of our approach by using several quality metrics and showing that the proposed method provides similar or higher coverage for SDDs compared to the default timing-aware ATPG, but only with a significantly small number of test patterns and in significantly small run time."}]