Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified Bit-Parallel Word-Serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion multiplier architecture. The proposed multiplier achieves a throughput of one multiplication every N + 1 clock cycles, in contrast with at least N + 3 clock cycles required in the recent other designs, where N is the ratio of field size to word size. Another contribution of this work is to explore parallelism at the instruction level in the proposed processor. Separated hardware modules for finite field multiplication, squaring and addition makes it possible that up to three finite field arithmetic operations be executed in parallel. At a higher level, data dependencies are detected at compile-time by analysing the data interdependency when performing elliptic curve point operations. Implemented using a CMOS 0.18 μm chip, which runs at 125MHz and performs one scalar multiplication in 62 μs.
['Bijan Ansari', 'Huapeng Wu']
I am writing a research paper on a idea Efficient finite field processor for GF(2 163 ) and its implementation
[{"from": "human", "value": "I am writing a research paper on a idea Efficient finite field processor for GF(2 163 ) and its implementation"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified Bit-Parallel Word-Serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion multiplier architecture. The proposed multiplier achieves a throughput of one multiplication every N + 1 clock cycles, in contrast with at least N + 3 clock cycles required in the recent other designs, where N is the ratio of field size to word size. Another contribution of this work is to explore parallelism at the instruction level in the proposed processor. Separated hardware modules for finite field multiplication, squaring and addition makes it possible that up to three finite field arithmetic operations be executed in parallel. At a higher level, data dependencies are detected at compile-time by analysing the data interdependency when performing elliptic curve point operations. Implemented using a CMOS 0.18 \u03bcm chip, which runs at 125MHz and performs one scalar multiplication in 62 \u03bcs."}]