Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As the size of parallel computing systems inexorably increases, the proportion of resource consumption (design effort, operating por, communication and calculation latency) absorbed by ‘non-computing’ tasks (communication and housekeeping) increases disproportionally. The SpiNNaker (Spiking neural net architecture) engine [1,2] sidesteps many of these issues with a novel architectural model: it is an isotropic ‘mesh’ of (ARM9) cores, connected via a hardware communication network. The topology allows uniform scalability up to a hard limit of just over a million cores, and the communications network – hardware handling packets of 72 bits – achieves a bisection bandwidth of 5 billion packets/s. The state of the machine is maintained in over 8TB of 32-bit memory, physically distributed throughout the system. There is no central processing ‘overseer’ or synchronised clock.  discusses opportunities and challenges in applying the SpiNNaker architecture, within neural simulation and beyond.
['J. Reeve', 'A.D. Brown', 'Rob Mills', 'Kier Dugan', 'Steve Furber']
I am writing a research paper on a idea Atomic computing - a different perspective on massively parallel problems
[{"from": "human", "value": "I am writing a research paper on a idea Atomic computing - a different perspective on massively parallel problems"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As the size of parallel computing systems inexorably increases, the proportion of resource consumption (design effort, operating por, communication and calculation latency) absorbed by \u2018non-computing\u2019 tasks (communication and housekeeping) increases disproportionally. The SpiNNaker (Spiking neural net architecture) engine [1,2] sidesteps many of these issues with a novel architectural model: it is an isotropic \u2018mesh\u2019 of (ARM9) cores, connected via a hardware communication network. The topology allows uniform scalability up to a hard limit of just over a million cores, and the communications network \u2013 hardware handling packets of 72 bits \u2013 achieves a bisection bandwidth of 5 billion packets/s. The state of the machine is maintained in over 8TB of 32-bit memory, physically distributed throughout the system. There is no central processing \u2018overseer\u2019 or synchronised clock.  discusses opportunities and challenges in applying the SpiNNaker architecture, within neural simulation and beyond."}]