Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In a fine-grain leakage saving technique to por gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off por switches. To get gain in energy savings, the pored-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware por-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far.  proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure.  applied this methodology to the leakage monitors and a CPU including a por-gated multiplier implemented in 65nm CMOS technology. Results shod that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique.
['Kimiyoshi Usami', 'Yuya Goto', 'Kensaku Matsunaga', 'Satoshi Koyama', 'Daisuke Ikebuchi', 'Hideharu Amano', 'Hiroshi Nakamura']
I am writing a research paper on a idea On-chip detection methodology for break-even time of power gated function units
[{"from": "human", "value": "I am writing a research paper on a idea On-chip detection methodology for break-even time of power gated function units"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In a fine-grain leakage saving technique to por gate function units, the efficiency is sensitive to overhead energy dissipating at turning on/off por switches. To get gain in energy savings, the pored-off period has to be longer than the minimum required time i.e. the break-even time (BET). While effectiveness of BET-aware por-gating control has been described in literatures, how to actually detect BET that fluctuates with the temperature and process variation has not been reported so far.  proposes an on-chip detection methodology for BET using pMOS/nMOS leakage monitors with MTCMOS circuit structure.  applied this methodology to the leakage monitors and a CPU including a por-gated multiplier implemented in 65nm CMOS technology. Results shod that our methodology detects BET at 5%-17% difference from that of the conventional simulation-based off-line technique."}]