Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: 1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and transient enhancement, while the feedforward path can improve the stability and increase the unit-gain frequency (UGF) by removing right-half-plane (RHP) zero. Simulation results show that the LDO has robust stability, high UGF (up to 1.7-MHz even at no-load), and excellent transient response performance. The overshoot and undershoot of the output voltages are less than 100-mV when the load step changes beten 0 and 50-mA in 1-mus, the settling time is 2-mus, while the dropout voltage is 100-mV at full-load current.
['Liangguo Shen', 'Zushu Yan', 'Xing Zhang', 'Yuanfu Zhao']
I am writing a research paper on a idea A capacitor-less low-dropout regulator for SoC with bi-directional asymmetric buffer
[{"from": "human", "value": "I am writing a research paper on a idea A capacitor-less low-dropout regulator for SoC with bi-directional asymmetric buffer"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: 1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and transient enhancement, while the feedforward path can improve the stability and increase the unit-gain frequency (UGF) by removing right-half-plane (RHP) zero. Simulation results show that the LDO has robust stability, high UGF (up to 1.7-MHz even at no-load), and excellent transient response performance. The overshoot and undershoot of the output voltages are less than 100-mV when the load step changes beten 0 and 50-mA in 1-mus, the settling time is 2-mus, while the dropout voltage is 100-mV at full-load current."}]