Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a design-for-testability (DFT) technique to test open defects in otherwise undetectable faulty branches in fully static CMOS latches and flip-flops is proposed. The main benefits of our proposal are: 1) it is able to detect a parametric range of resistive opens defects and 2) the performance degradation is very low. The testability of the added DFT circuitry is also addressed. The cost of the proposed technique in terms of speed degradation, area overhead, and extra pins is analyzed. Comparison with other previously proposed testable latches is carried out. Circuits with the proposed technique have been designed and fabricated. Good agreement is observed beten the analytical analysis, simulations and experimental measures performed on the fabricated circuits.
['Antonio Zenteno Ramirez', 'Guillermo Espinosa', 'Víctor H. Champac']
I am writing a research paper on a idea Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops
[{"from": "human", "value": "I am writing a research paper on a idea Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a design-for-testability (DFT) technique to test open defects in otherwise undetectable faulty branches in fully static CMOS latches and flip-flops is proposed. The main benefits of our proposal are: 1) it is able to detect a parametric range of resistive opens defects and 2) the performance degradation is very low. The testability of the added DFT circuitry is also addressed. The cost of the proposed technique in terms of speed degradation, area overhead, and extra pins is analyzed. Comparison with other previously proposed testable latches is carried out. Circuits with the proposed technique have been designed and fabricated. Good agreement is observed beten the analytical analysis, simulations and experimental measures performed on the fabricated circuits."}]