Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Advance Encryption Standard (AES) hardware implementation in FPGA as ll as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). Hover, lor throughput and low area designs have also been investigated in recent years for the embedded hardware applications.  presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications.
['Kuo Huang Chang', 'Yi Cheng Chen', 'Chung Cheng Hsieh', 'Chi Wu Huang', 'Chi Jeng Chang']
I am writing a research paper on a idea Embedded a low area 32-bit AES for image encryption/decryption application
[{"from": "human", "value": "I am writing a research paper on a idea Embedded a low area 32-bit AES for image encryption/decryption application"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Advance Encryption Standard (AES) hardware implementation in FPGA as ll as in ASIC has been intensely discussing, especially in high-throughput over several tens Giga bit per second (Gbps). Hover, lor throughput and low area designs have also been investigated in recent years for the embedded hardware applications.  presents a 32-bit AES implementation with a low area of 110 slices which is the smallest design among the literature reports. This small core, suitable for inexpensive small size FPGA chip implementation, is embedded in Xilinx Spartan3E with MicroBlaze processor for image encryption/decryption applications."}]