Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bit-vectors that have differing bit-widths. Such designs are found in many DSP applications where the widths of input and output bit-vectors are dictated by the desired precision. A bit-vector of size n can represent integer values from 0 to 2/sup n/ - 1; i.e. integers reduced modulo 2/sup n/. Therefore, to verify bit-vector arithmetic over multiple word-length operands,  model the RTL datapath as a polynomial function from Z/sub 2n1/ /spl times/ Z/sub 2n2/ /spl times/ ... Z/sub 2nd/ to Z/sub 2m/. Subsequently, RTL equivalence f /spl equiv/ g is solved by proving whether (f - g) /spl equiv/ 0 over such mappings. Exploiting concepts from number theory and commutative algebra, a systematic, complete algorithmic procedure is derived for this purpose. Experimentally,  demonstrate how this approach can be applied within a practical CAD setting. Using our approach,  verify a set of arithmetic datapaths at RTL where contemporary approaches prove to be in feasible.
['Namrata Shekhar', 'Priyank Kalla', 'Florian Enescu']
I am writing a research paper on a idea Equivalence verification of arithmetic datapaths with multiple word-length operands
[{"from": "human", "value": "I am writing a research paper on a idea Equivalence verification of arithmetic datapaths with multiple word-length operands"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bit-vectors that have differing bit-widths. Such designs are found in many DSP applications where the widths of input and output bit-vectors are dictated by the desired precision. A bit-vector of size n can represent integer values from 0 to 2/sup n/ - 1; i.e. integers reduced modulo 2/sup n/. Therefore, to verify bit-vector arithmetic over multiple word-length operands,  model the RTL datapath as a polynomial function from Z/sub 2n1/ /spl times/ Z/sub 2n2/ /spl times/ ... Z/sub 2nd/ to Z/sub 2m/. Subsequently, RTL equivalence f /spl equiv/ g is solved by proving whether (f - g) /spl equiv/ 0 over such mappings. Exploiting concepts from number theory and commutative algebra, a systematic, complete algorithmic procedure is derived for this purpose. Experimentally,  demonstrate how this approach can be applied within a practical CAD setting. Using our approach,  verify a set of arithmetic datapaths at RTL where contemporary approaches prove to be in feasible."}]