Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Single source shortest path (SSSP) is a fundamental problem in graph theory. Hover, the existing SSSP implementations on field-programmable gate arrays (FPGAs) are incapable of processing large graphs by storing the graph and results in internal memories. In this brief,  propose a parallel FPGA implementation to solve the SSSP problem, which is derived from a variant of the “eager” Dijkstra algorithm. In order to process a large graph problem, an extended systolic array priority queue called ExSAPQ is proposed to allow large-scale priority queue processing. The experimental results on the full United States road network show that our SSSP implementation on FPGA can achieve a speedup of 5× over the CPU implementation and the por consumption is only 1/4 of the latter.
['Guoqing Lei', 'Yong Dou', 'Rongchun Li', 'Fei Xia']
I am writing a research paper on a idea An FPGA Implementation for Solving the Large Single-Source-Shortest-Path Problem
[{"from": "human", "value": "I am writing a research paper on a idea An FPGA Implementation for Solving the Large Single-Source-Shortest-Path Problem"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Single source shortest path (SSSP) is a fundamental problem in graph theory. Hover, the existing SSSP implementations on field-programmable gate arrays (FPGAs) are incapable of processing large graphs by storing the graph and results in internal memories. In this brief,  propose a parallel FPGA implementation to solve the SSSP problem, which is derived from a variant of the \u201ceager\u201d Dijkstra algorithm. In order to process a large graph problem, an extended systolic array priority queue called ExSAPQ is proposed to allow large-scale priority queue processing. The experimental results on the full United States road network show that our SSSP implementation on FPGA can achieve a speedup of 5\u00d7 over the CPU implementation and the por consumption is only 1/4 of the latter."}]