Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Dynamic critical path analysis in modern processors is needed to reduce margins typically determined by the static timing analysis. Dynamic path analysis, hover, is cost-prohibitive. ,  propose WILD, a supervised learning model to predict dynamic delay of functional units (FUs) based on the input workload during execution.  measure the dynamic delay using switching activity generated through gate-level simulation of a post place-and-route design in TSMC 45nm process.  then look for ‘features’ in the input data that influence dynamic path sensitization. Using these features  apply a logistic regression (LR) method to construct a predictive model trained and tested using three datasets: random, Sobel filter and Gaussian filter.  classify dynamic delay into five distinct classes. For a given test input, WILD predicts the class of output dynamic delay. On average across several FUs, 98.0% of WILD predictions are consistent with gate-level simulation. Using WILD-directed dynamic frequency scaling can improve instruction-level performance by 13%–44% compared to the state-of-the-art instruction-level timing model.
['Xun Jiao', 'Yu Jiang', 'Abbas Rahimi', 'Rajesh K. Gupta']
I am writing a research paper on a idea WILD: A workload-based learning model to predict dynamic delay of functional units
[{"from": "human", "value": "I am writing a research paper on a idea WILD: A workload-based learning model to predict dynamic delay of functional units"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Dynamic critical path analysis in modern processors is needed to reduce margins typically determined by the static timing analysis. Dynamic path analysis, hover, is cost-prohibitive. ,  propose WILD, a supervised learning model to predict dynamic delay of functional units (FUs) based on the input workload during execution.  measure the dynamic delay using switching activity generated through gate-level simulation of a post place-and-route design in TSMC 45nm process.  then look for \u2018features\u2019 in the input data that influence dynamic path sensitization. Using these features  apply a logistic regression (LR) method to construct a predictive model trained and tested using three datasets: random, Sobel filter and Gaussian filter.  classify dynamic delay into five distinct classes. For a given test input, WILD predicts the class of output dynamic delay. On average across several FUs, 98.0% of WILD predictions are consistent with gate-level simulation. Using WILD-directed dynamic frequency scaling can improve instruction-level performance by 13%\u201344% compared to the state-of-the-art instruction-level timing model."}]