Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , based on probabilistic via-connection analysis of single vias and redundant vias, it is ll known that on-track redundant via insertion is more important and critical than off-track redundant via insertion for yield optimization. Furthermore, a two-phase insertion approach for yield optimization is proposed to insert on-track redundant vias by finding a maximum matching result in a bipartite graph and insert off-track redundant vias by using a maximum constrained edge-pair matching result in a constrained edge-pair matching with via-sharing constraints. According to the Poisson yield model for redundant via insertion, the experimental results show that our proposed two-phase insertion approach can increase 0.3%~7.4% wirelength to improve 4.3%~44.8% chip yield for the tested benchmarks.
['Jin-Tai Yan', 'Bo-Yi Chiang', 'Zhi-Wei Chen']
I am writing a research paper on a idea Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis
[{"from": "human", "value": "I am writing a research paper on a idea Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , based on probabilistic via-connection analysis of single vias and redundant vias, it is ll known that on-track redundant via insertion is more important and critical than off-track redundant via insertion for yield optimization. Furthermore, a two-phase insertion approach for yield optimization is proposed to insert on-track redundant vias by finding a maximum matching result in a bipartite graph and insert off-track redundant vias by using a maximum constrained edge-pair matching result in a constrained edge-pair matching with via-sharing constraints. According to the Poisson yield model for redundant via insertion, the experimental results show that our proposed two-phase insertion approach can increase 0.3%~7.4% wirelength to improve 4.3%~44.8% chip yield for the tested benchmarks."}]