Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Traditional integrated circuit (IC) design flows optimize clock networks before signal-net routing are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-network synthesis. ,  integrate clock network synthesis within global placement by optimizing register locations.  propose: 1) obstacle-aware virtual clock-tree synthesis; 2) arboreal clock-net contraction force with virtual-node insertion, which can handle multiple clock domains and gated clocks; and 3) an obstacle-avoidance force (OAF). Our work is validated on large benchmarks with numerous macroblocks. Experimental results indicate that our software implementation, called Lopper, prunes clock-tree branches to reduce their length by 30.0%-36.6% and average total dynamic por consumption by 6.8%-11.6% versus conventional wirelength-driven approaches. SPICE-driven simulations show that our methods improve robustness of clock trees.
['Dong Jin Lee', 'Igor L. Markov']
I am writing a research paper on a idea Obstacle-Aware Clock-Tree Shaping During Placement
[{"from": "human", "value": "I am writing a research paper on a idea Obstacle-Aware Clock-Tree Shaping During Placement"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Traditional integrated circuit (IC) design flows optimize clock networks before signal-net routing are limited by the quality of register placement. Existing publications also reflect this bias and focus mostly on clock routing. The few known techniques for register placement exhibit significant limitations and do not account for recent progress in large-scale placement and obstacle-aware clock-network synthesis. ,  integrate clock network synthesis within global placement by optimizing register locations.  propose: 1) obstacle-aware virtual clock-tree synthesis; 2) arboreal clock-net contraction force with virtual-node insertion, which can handle multiple clock domains and gated clocks; and 3) an obstacle-avoidance force (OAF). Our work is validated on large benchmarks with numerous macroblocks. Experimental results indicate that our software implementation, called Lopper, prunes clock-tree branches to reduce their length by 30.0%-36.6% and average total dynamic por consumption by 6.8%-11.6% versus conventional wirelength-driven approaches. SPICE-driven simulations show that our methods improve robustness of clock trees."}]