Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  considers the problem of testing VLSI integrated circuits without exceeding their por ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak por dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by loring the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application.
['Patrick Girard', 'Loïs Guiller', 'Christian Landrault', 'Serge Pravossoudovitch']
I am writing a research paper on a idea A test vector ordering technique for switching activity reduction during test operation
[{"from": "human", "value": "I am writing a research paper on a idea A test vector ordering technique for switching activity reduction during test operation"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  considers the problem of testing VLSI integrated circuits without exceeding their por ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak por dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by loring the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application."}]