Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  propose a data-aware por cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover,  propose an adaptive data-aware keeper (DAK) to lor the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.
['Yi-Wei Chiu', 'Yu-Hao Hu', 'Jun-Kai Zhao', 'Shyh-Jye Jou', 'Ching-Te Chuang']
I am writing a research paper on a idea A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper
[{"from": "human", "value": "I am writing a research paper on a idea A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  propose a data-aware por cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover,  propose an adaptive data-aware keeper (DAK) to lor the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages."}]