Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Equtivalence checking is one of the most important issues in VLSI designs to guarantee that bugs do not enter the design during optimization steps or synthesis steps. ,  propose a new word-level equivalence checking method beten two models before and after high-level synthesis or behavioral optimization. Our method converts two given designs into RTL models which have the same datapath so that the two designs have the same bit-level accuracy. Then the word-level equivalence checking techniques can be applied satisfying the bit-level accuracy. Also, as our method propagates equivalences from inputs to outputs with the equivalence rules of control structures, name correspondences among registers or variables are not requtired. By those rules, designs which have loops can be verified without unrolling. Experimental results with realistic examples show that our method can verify those designs in practical periods.
['Tasuku Nishihara', 'Takeshi Matsumoto', 'Masahiro Fujita']
I am writing a research paper on a idea Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis
[{"from": "human", "value": "I am writing a research paper on a idea Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Equtivalence checking is one of the most important issues in VLSI designs to guarantee that bugs do not enter the design during optimization steps or synthesis steps. ,  propose a new word-level equivalence checking method beten two models before and after high-level synthesis or behavioral optimization. Our method converts two given designs into RTL models which have the same datapath so that the two designs have the same bit-level accuracy. Then the word-level equivalence checking techniques can be applied satisfying the bit-level accuracy. Also, as our method propagates equivalences from inputs to outputs with the equivalence rules of control structures, name correspondences among registers or variables are not requtired. By those rules, designs which have loops can be verified without unrolling. Experimental results with realistic examples show that our method can verify those designs in practical periods."}]