Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Repeaterless low swing on-chip interconnects require clock synchronization circuits at the receiver to sample the incoming low swing data. While a clock of the correct frequency is generally available from the clock grid, the correct phase still needs to be recovered. Mesochronous retiming circuits are used to generate a sampling clock positioned at the center of the data eye. In this work,  discuss the settling behaviour of such mesochronous synchronizers.  first show that inter-symbol interference can cause an indefinite increase in the settling time of the synchronizer. This occurs when the initial phase of the clock is within the horizontally closed region of the data eye. Next,  model the synchronizer system as a Markov chain with absorbing states and determine the mean absorption time which is indicative of the mean settling time of the circuit. The model predictions match ll with behavioural simulations of the synchronizer. Finally,  suggest ways to reduce the settling time.
['Naveen Kadayinti', 'Amitalok J. Budkuley', 'Dinesh Kumar Sharma']
I am writing a research paper on a idea Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects
[{"from": "human", "value": "I am writing a research paper on a idea Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Repeaterless low swing on-chip interconnects require clock synchronization circuits at the receiver to sample the incoming low swing data. While a clock of the correct frequency is generally available from the clock grid, the correct phase still needs to be recovered. Mesochronous retiming circuits are used to generate a sampling clock positioned at the center of the data eye. In this work,  discuss the settling behaviour of such mesochronous synchronizers.  first show that inter-symbol interference can cause an indefinite increase in the settling time of the synchronizer. This occurs when the initial phase of the clock is within the horizontally closed region of the data eye. Next,  model the synchronizer system as a Markov chain with absorbing states and determine the mean absorption time which is indicative of the mean settling time of the circuit. The model predictions match ll with behavioural simulations of the synchronizer. Finally,  suggest ways to reduce the settling time."}]