Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents FPGA implementations of the DES and Triple-DES with improved security against por analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks.  demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular,  use the large embedded memories available in the Xilinx Virtex-II pro® FP-GAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.
['François-Xavier Standaert', 'Gaël Rouvroy', 'Jean-Jacques Quisquater']
I am writing a research paper on a idea FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
[{"from": "human", "value": "I am writing a research paper on a idea FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents FPGA implementations of the DES and Triple-DES with improved security against por analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks.  demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular,  use the large embedded memories available in the Xilinx Virtex-II pro\u00ae FP-GAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec."}]