Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 63.5dB, 2MHz bandwidth ΔΣ ADC using two ICOs pseudo-differentially as an integrator/quantizer and a combined front-end switched-capacitor V-I converter and feedback DAC in 0.18μm without performance-enhancing calibration is presented. A novel high-linearity, temperature-independent, and voltage-independent ring oscillator architecture provides a high resolution quantizer output, and a digital ΔΣ loop truncates this for a 17-level feedback DAC. The custom portion of the design consumes 6.08mW of analog por from a 1.8V supply and occupies 0.152mm 2 .
['Joseph Hamilton', 'Shouli Yan', 'T. R. Viswanathan']
I am writing a research paper on a idea An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC
[{"from": "human", "value": "I am writing a research paper on a idea An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based \u0394\u03a3 ADC"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 63.5dB, 2MHz bandwidth \u0394\u03a3 ADC using two ICOs pseudo-differentially as an integrator/quantizer and a combined front-end switched-capacitor V-I converter and feedback DAC in 0.18\u03bcm without performance-enhancing calibration is presented. A novel high-linearity, temperature-independent, and voltage-independent ring oscillator architecture provides a high resolution quantizer output, and a digital \u0394\u03a3 loop truncates this for a 17-level feedback DAC. The custom portion of the design consumes 6.08mW of analog por from a 1.8V supply and occupies 0.152mm 2 ."}]