Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Networks-on-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures.  presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage por consumption of NoC based interconnection architectures.  implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (iii) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and por versus performance trade-off analysis of 4/spl times/4 mesh based NoC architecture.
['Nilanjan Banerjee', 'Praveen Vellanki', 'Karam S. Chatha']
I am writing a research paper on a idea A power and performance model for network-on-chip architectures
[{"from": "human", "value": "I am writing a research paper on a idea A power and performance model for network-on-chip architectures"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Networks-on-chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures.  presents a VHDL based cycle accurate register transfer level model for evaluating the latency, throughput, dynamic, and leakage por consumption of NoC based interconnection architectures.  implemented a parameterized register transfer level design of the NoC architecture elements. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (iii) number, and depth of virtual channels, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various NoC components. The paper presents results obtained by application of the model towards design space exploration, and por versus performance trade-off analysis of 4/spl times/4 mesh based NoC architecture."}]