Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With ongoing advances of semiconductor technology, por dissipation has been moving higher on the list of VLSI design constraints. In most high-performance synchronous VLSI designs, the distribution of low-skew global clock signals approaching GigaHertz range is the single largest source of por consumption. GALS design style offers a solution to this issue by dividing synchronous design into smaller locally synchronous sub-blocks. Smaller sub-blocks reduce capacitance in clock distribution networks because they need less H-tree levels. Hover, this implies a large number of sub-blocks, which increases the asynchronous por overhead. This work investigates these GALS por tradeoffs. This is, to our knowledge, the first paper to propose closed form models for optimum number of partitions that gives minimum por for a GALS array of identical processors. The models can serve as a useful firsthand guideline for designers in initial design stages. Experimental results verify the effectiveness of the model.
['Adhir Upadhyay', 'Syed Rafay Hasan', 'Mohamed Nekili']
I am writing a research paper on a idea Optimal partitioning of globally asychronous locally synchronous processor arrays
[{"from": "human", "value": "I am writing a research paper on a idea Optimal partitioning of globally asychronous locally synchronous processor arrays"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With ongoing advances of semiconductor technology, por dissipation has been moving higher on the list of VLSI design constraints. In most high-performance synchronous VLSI designs, the distribution of low-skew global clock signals approaching GigaHertz range is the single largest source of por consumption. GALS design style offers a solution to this issue by dividing synchronous design into smaller locally synchronous sub-blocks. Smaller sub-blocks reduce capacitance in clock distribution networks because they need less H-tree levels. Hover, this implies a large number of sub-blocks, which increases the asynchronous por overhead. This work investigates these GALS por tradeoffs. This is, to our knowledge, the first paper to propose closed form models for optimum number of partitions that gives minimum por for a GALS array of identical processors. The models can serve as a useful firsthand guideline for designers in initial design stages. Experimental results verify the effectiveness of the model."}]