Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at frequencies greater to that found in a ring of three unloaded inverters. Tokens spread evenly through FIFO rings built from this control under certain conditions. The tokens are locked into an equally separated pattern by a classical feedback control where the actuator is the FIFO control stage. The actuating variable is the stage latency which varies according to the temporal separation of its inputs. When the tokens in the FIFO ring are equally spaced, the relative phases of the nodes in the system assume predictable values. This technique allows the division of a better than three gate delay cycle time into an arbitrarily large number of phases whose precision is limited only by the limits of the fabrication process and noise. Applications that need a precise time reference can benefit from this technique. A/D conversion, clock recovery, and multi-phase clocking solutions are briefly sketched.
['Scott Fairbanks', 'Simon W. Moore']
I am writing a research paper on a idea Analog micropipeline rings for high precision timing
[{"from": "human", "value": "I am writing a research paper on a idea Analog micropipeline rings for high precision timing"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: I use asynchronous FIFO stages that are connected in rings to generate and deliver highly precise timing signals. I introduce a Micropipeline FIFO control stage that oscillates at frequencies greater to that found in a ring of three unloaded inverters. Tokens spread evenly through FIFO rings built from this control under certain conditions. The tokens are locked into an equally separated pattern by a classical feedback control where the actuator is the FIFO control stage. The actuating variable is the stage latency which varies according to the temporal separation of its inputs. When the tokens in the FIFO ring are equally spaced, the relative phases of the nodes in the system assume predictable values. This technique allows the division of a better than three gate delay cycle time into an arbitrarily large number of phases whose precision is limited only by the limits of the fabrication process and noise. Applications that need a precise time reference can benefit from this technique. A/D conversion, clock recovery, and multi-phase clocking solutions are briefly sketched."}]