Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper,  propose an algorithm of a single-layer zero skew clock routing in X-architecture (Planar-CRX). Our method integrates the extended deferred-merge embedding algorithm (DME-X, which extends DME to X-architecture) with modified Ohtsuki's line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wire-length on average, and fer bends. Experimental results also indicate that our solution is comparable with previous non-planar zero skew clock routing algorithm
['Weixiang Shen', 'Yici Cai', 'Xianlong Hong', 'Jiang Hu', 'Bing Lu']
I am writing a research paper on a idea Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
[{"from": "human", "value": "I am writing a research paper on a idea Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper,  propose an algorithm of a single-layer zero skew clock routing in X-architecture (Planar-CRX). Our method integrates the extended deferred-merge embedding algorithm (DME-X, which extends DME to X-architecture) with modified Ohtsuki's line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wire-length on average, and fer bends. Experimental results also indicate that our solution is comparable with previous non-planar zero skew clock routing algorithm"}]