Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  seek the optimal combination of dedicated radix-2m multiplication blocks, and adder trees schemes for the realization of optimized radix-2m array multipliers. The operands of the multipliers are generated by 2's complement radix-4, radix-16, radix-256, and radix-65536 dedicated multiplication blocks. The operands are added using different adder trees schemes such as Wallace, RBA, and compressors. The number of operands defines the amount of adders blocks used in the addition tree of the array multiplier. The logic synthesis was realized using Cadence Encounter RTL Compiler tool with Nangate 45nm Open Cell library. Area, delay and por consumption results are presented for the synthesized proposed multipliers. As will be presented, the combination of radix-4 or radix-16 dedicated multiplication block and multi-operand adder tree schemes yields the best por — performance results in the radix-2" array multipliers.
['Anderson Martins', 'Mateus Fonseca', 'Eduardo A. C. da Costa']
I am writing a research paper on a idea Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization
[{"from": "human", "value": "I am writing a research paper on a idea Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  seek the optimal combination of dedicated radix-2m multiplication blocks, and adder trees schemes for the realization of optimized radix-2m array multipliers. The operands of the multipliers are generated by 2's complement radix-4, radix-16, radix-256, and radix-65536 dedicated multiplication blocks. The operands are added using different adder trees schemes such as Wallace, RBA, and compressors. The number of operands defines the amount of adders blocks used in the addition tree of the array multiplier. The logic synthesis was realized using Cadence Encounter RTL Compiler tool with Nangate 45nm Open Cell library. Area, delay and por consumption results are presented for the synthesized proposed multipliers. As will be presented, the combination of radix-4 or radix-16 dedicated multiplication block and multi-operand adder tree schemes yields the best por \u2014 performance results in the radix-2\" array multipliers."}]