Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems.  note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and por dissipation) can be traded-off, in order to minimize overall system energy. To this end,  propose a novel design-time system-level synthesis framework that is cognizant of process variations while mapping cores operating at specific supply voltages to a die and allocating communication routes on a 2D-mesh network-on-chip (NoC) topology for optimal energy-efficiency. Our experiments with real-world and synthetic application benchmarks show that our framework achieves 3.4% savings in computation energy and 19% savings in communication energy compared to the best known prior work on NoC-based MPSoC synthesis that considers process variations.
['Nishit Ashok Kapadia', 'Sudeep Pasricha']
I am writing a research paper on a idea VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands
[{"from": "human", "value": "I am writing a research paper on a idea VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial for designing energy-efficient systems.  note that by performing voltage island placement appropriately, the two major unintended consequences of variations on the circuit characteristics (altered delay and por dissipation) can be traded-off, in order to minimize overall system energy. To this end,  propose a novel design-time system-level synthesis framework that is cognizant of process variations while mapping cores operating at specific supply voltages to a die and allocating communication routes on a 2D-mesh network-on-chip (NoC) topology for optimal energy-efficiency. Our experiments with real-world and synthetic application benchmarks show that our framework achieves 3.4% savings in computation energy and 19% savings in communication energy compared to the best known prior work on NoC-based MPSoC synthesis that considers process variations."}]