Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either beten microstrips or beten microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach.
['Errikos Lourandakis', 'Stefanos Stefanou', 'Konstantinos Nikellis', 'Sotiris Bantas']
I am writing a research paper on a idea RF passive device modeling and characterization in 65nm CMOS technology
[{"from": "human", "value": "I am writing a research paper on a idea RF passive device modeling and characterization in 65nm CMOS technology"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1-M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either beten microstrips or beten microstrips and silicon substrate. Good correlation to silicon data is achieved for the fabricated test structures. The validity of the proposed model is also investigated for complex passive devices such as inductors and interdigitated capacitors. Device metrics for both types of passive devices are investigated and compared to measured silicon data. Good agreement is achieved in all cases proving the accuracy of the proposed modeling approach."}]