Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Dynamic voltage scaling (DVS) is a very effective low-por design technique in modem digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system.  presents a new adaptive DC/DC converter design, which adopts a delay-line controller for voltage regulation. With a proposed adaptive pulse-train technique, ripple voltages are reduced by 50%, while the converter still maintains satisfying transient response. With a supply voltage of 3.3V, the output of the converter is ll regulated from 1.7 to 3.0V. Por consumption of the controller is below 100 /spl mu/W. Maximum efficiency of 92% is achieved with output por of 125mW. Chip area is 0.8 /spl times/ 1.2mm/sup 2/ in 1.5 /spl mu/m standard CMOS process.
['Chuang Zhang', 'Dongsheng Ma', 'Ashok Srivastava']
I am writing a research paper on a idea Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation
[{"from": "human", "value": "I am writing a research paper on a idea Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Dynamic voltage scaling (DVS) is a very effective low-por design technique in modem digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system.  presents a new adaptive DC/DC converter design, which adopts a delay-line controller for voltage regulation. With a proposed adaptive pulse-train technique, ripple voltages are reduced by 50%, while the converter still maintains satisfying transient response. With a supply voltage of 3.3V, the output of the converter is ll regulated from 1.7 to 3.0V. Por consumption of the controller is below 100 /spl mu/W. Maximum efficiency of 92% is achieved with output por of 125mW. Chip area is 0.8 /spl times/ 1.2mm/sup 2/ in 1.5 /spl mu/m standard CMOS process."}]