Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made por a very important factor. , a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce por. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude por reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT.
['S.H. Cho', 'Thucydides Xanthopoulos', 'Anantha P. Chandrakasan']
I am writing a research paper on a idea A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning
[{"from": "human", "value": "I am writing a research paper on a idea A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders (VLDs) was primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made por a very important factor. , a data-driven variable length decoding architecture is presented, which exploits the signal statistics of variable length codes to reduce por. The approach uses fine-grain lookup table (LUT) partitioning to reduce switched capacitance based on codeword frequency. The complete VLD for MPEG-2 has been fabricated and consumes 530 /spl mu/W at 1.35 V with a video rate of 48-M discrete cosine transform samples/s using a 0.6-/spl mu/m CMOS technology. More than an order of magnitude por reduction is demonstrated without performance loss compared to a conventional parallel decoding scheme with a single LUT."}]