Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lor. It spends only 12, 20, and 26 clocks cycles in the best, average, and worst case, respectively. The HA-CORDIC exploits some design techniques such as resource sharing, pipeline, and parallel processing to achieve low-resource and low-latency. In 65nm SOTB CMOS technology, this design is able to operate at 50 MHz frequency with 0.5 V supply voltage, 0.36 mA current, and 0.058 mm2 area. Its por consumption of HA-CORDIC is 0.251 mW, about three times lor than the one in conventional CMOS technology. Its leakage current is about 0.492 μA if the supply voltage VDD is 0.4 V and the bias voltage VBB is −1.5 V. This leakage current is about four times lor than that of HA-CORDIC implementing in conventional CMOS.
['Trong-Thuc Hoang', 'Duc-Hung Le', 'Hong-Thu Nguyen', 'Xuan-Thuan Nguyen', 'Cong-Kha Pham']
I am writing a research paper on a idea A hybrid adaptive CORDIC in 65nm SOTB CMOS process
[{"from": "human", "value": "I am writing a research paper on a idea A hybrid adaptive CORDIC in 65nm SOTB CMOS process"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lor. It spends only 12, 20, and 26 clocks cycles in the best, average, and worst case, respectively. The HA-CORDIC exploits some design techniques such as resource sharing, pipeline, and parallel processing to achieve low-resource and low-latency. In 65nm SOTB CMOS technology, this design is able to operate at 50 MHz frequency with 0.5 V supply voltage, 0.36 mA current, and 0.058 mm2 area. Its por consumption of HA-CORDIC is 0.251 mW, about three times lor than the one in conventional CMOS technology. Its leakage current is about 0.492 \u03bcA if the supply voltage VDD is 0.4 V and the bias voltage VBB is \u22121.5 V. This leakage current is about four times lor than that of HA-CORDIC implementing in conventional CMOS."}]