Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Low-density parity-check codes using the belief-propagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical structures, such as the so-called trapping sets, exist in the corresponding Tanner graph.  presents a joint row-column decoding algorithm to lor the error floor, in which the column processing is combined with the processing of each row. By gradually updating the pseudo-posterior probabilities of all bit nodes, the proposed algorithm minimizes the propagation of erroneous information from trapping sets into the whole graph. The simulation indicates that the proposed joint decoding algorithm improves the performance in the waterfall region and lors the error floor. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed joint decoder increases the decoding speed by a factor of eight, compared to the traditional decoder.
['Zhiyong He', 'Sébastien Roy', 'Paul Fortier']
I am writing a research paper on a idea Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
[{"from": "human", "value": "I am writing a research paper on a idea Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Low-density parity-check codes using the belief-propagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical structures, such as the so-called trapping sets, exist in the corresponding Tanner graph.  presents a joint row-column decoding algorithm to lor the error floor, in which the column processing is combined with the processing of each row. By gradually updating the pseudo-posterior probabilities of all bit nodes, the proposed algorithm minimizes the propagation of erroneous information from trapping sets into the whole graph. The simulation indicates that the proposed joint decoding algorithm improves the performance in the waterfall region and lors the error floor. Implementation results into field programmable gate array (FPGA) devices indicate that the proposed joint decoder increases the decoding speed by a factor of eight, compared to the traditional decoder."}]