Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and por consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW por consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low por consumption for 5-6-GHz wireless LAN applications.
['Xiao Peng Yu', 'Manh Anh Do', 'Lin Jia', 'Jianguo Ma', 'Kiat Seng Yeo']
I am writing a research paper on a idea Design of a low power wide-band high resolution programmable frequency divider
[{"from": "human", "value": "I am writing a research paper on a idea Design of a low power wide-band high resolution programmable frequency divider"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and por consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW por consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low por consumption for 5-6-GHz wireless LAN applications."}]