Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 1.5V(A)/0.8V(D) high dynamic range (HDR) readout integrated circuit (ROIC) with tunable sensitive range and fixed pattern noise (FPN) reduction for infrared focal plane arrays (IR FPAs) is presented. A pulse width modulation (PWM) readout with capacitive trans-impedance amplifier (CTIA) front end, dual-exposure extended-counting (DEEC) [1], and aligned time-control ramp (ATCR) generator are developed for dynamic range boost. Auto-zeroing and offset cancellation (AZOC) mechanisms are implemented to reduce readout noise and FPN. The digital supply voltage of logic part is decreased to 0.8V for por reduction. The ROIC prototype with an embedded test CMOS image sensor array of 64×64 and 15μm×15μm pixel pitch has been designed and fabricated in 0.18μm CMOS technology. The experimental results show an achieved high dynamic range of 132dB, a FPN in dark of 0.02%, a frame rate of 230fps, and an iFOM of 1.27 nW/frame.pix at 1.5V(A)/0.8V(D) operation.
['Chia-Chi Kuo', 'Chih-Cheng Hsieh']
I am writing a research paper on a idea A 132dB DR readout IC with pulse width modulation for IR focal plane arrays
[{"from": "human", "value": "I am writing a research paper on a idea A 132dB DR readout IC with pulse width modulation for IR focal plane arrays"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 1.5V(A)/0.8V(D) high dynamic range (HDR) readout integrated circuit (ROIC) with tunable sensitive range and fixed pattern noise (FPN) reduction for infrared focal plane arrays (IR FPAs) is presented. A pulse width modulation (PWM) readout with capacitive trans-impedance amplifier (CTIA) front end, dual-exposure extended-counting (DEEC) [1], and aligned time-control ramp (ATCR) generator are developed for dynamic range boost. Auto-zeroing and offset cancellation (AZOC) mechanisms are implemented to reduce readout noise and FPN. The digital supply voltage of logic part is decreased to 0.8V for por reduction. The ROIC prototype with an embedded test CMOS image sensor array of 64\u00d764 and 15\u03bcm\u00d715\u03bcm pixel pitch has been designed and fabricated in 0.18\u03bcm CMOS technology. The experimental results show an achieved high dynamic range of 132dB, a FPN in dark of 0.02%, a frame rate of 230fps, and an iFOM of 1.27 nW/frame.pix at 1.5V(A)/0.8V(D) operation."}]