Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an RSA hardware design that simultaneously achieves high-performance and low-por. A bit-oriented, split modular multiplication algorithm and architecture are proposed to fully exert the radix-4 computational capability. Further,  identify the switching profile of RSA data and accordingly propose por-optimized designs for the storage elements and key computational components. The complete RSA modular exponentiation hardware has been implemented using cell-based 0.18/spl mu/m CMOS technology. Post-layout simulation shows that the design delivers an average performance of 586kbps at 460MHz, 1.8Vwhile consuming only 830mW.
['Chingwei Yeh', 'En-Feng Hsu', 'Kai-Wen Cheng', 'Jinn-Shyan Wang', 'Nai-Jen Chang']
I am writing a research paper on a idea An 830mW, 586kbps 1024-bit RSA chip design
[{"from": "human", "value": "I am writing a research paper on a idea An 830mW, 586kbps 1024-bit RSA chip design"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an RSA hardware design that simultaneously achieves high-performance and low-por. A bit-oriented, split modular multiplication algorithm and architecture are proposed to fully exert the radix-4 computational capability. Further,  identify the switching profile of RSA data and accordingly propose por-optimized designs for the storage elements and key computational components. The complete RSA modular exponentiation hardware has been implemented using cell-based 0.18/spl mu/m CMOS technology. Post-layout simulation shows that the design delivers an average performance of 586kbps at 460MHz, 1.8Vwhile consuming only 830mW."}]