Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present an accurate RT level estimation methodology describing the por consumption of a component under por gating. By developing separate models for the on- and off-state and the transition cost beten them,  can limit errors to below 10% compared to SPICE. The models support several implementation styles of por gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate.  show, how the models can be integrated into a high level por estimation framework supporting design space exploration for several design for leakage methodologies.
['Sven Rosinger', 'Domenik Helms', 'Wolfgang Nebel']
I am writing a research paper on a idea RTL power modeling and estimation of sleep transistor based power gating
[{"from": "human", "value": "I am writing a research paper on a idea RTL power modeling and estimation of sleep transistor based power gating"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present an accurate RT level estimation methodology describing the por consumption of a component under por gating. By developing separate models for the on- and off-state and the transition cost beten them,  can limit errors to below 10% compared to SPICE. The models support several implementation styles of por gating as NMOS/PMOS or Super-Cutoff. Additionally the models can be used to size the sleep transistors more accurate.  show, how the models can be integrated into a high level por estimation framework supporting design space exploration for several design for leakage methodologies."}]