Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follor (FVF) which replaces the source follor input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lor currents and lor por dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a por supply of 1.8 V. Propagation delay, por dissipation, and por delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.
['Veepsa Bhatia', 'Neeta Pandey']
I am writing a research paper on a idea Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs
[{"from": "human", "value": "I am writing a research paper on a idea Modified Tang and Pun\u2019s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follor (FVF) which replaces the source follor input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lor currents and lor por dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18\u2009\u03bcm TSMC CMOS technology at a por supply of 1.8\u2009V. Propagation delay, por dissipation, and por delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated."}]