Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a hybrid CMOS pulse width modulation (PWM) digital pixel sensor (DPS) is proposed. In order to reduce the pixel area, the proposed architecture requires only a two bit on-pixel memory while placing the remaining six bits outside the array, assuming a common resolution of eight bits. This new architecture reduces the size of the pixel significantly as the memory requirement at pixel level is divided by 4. The eight bit resolution is maintained by scanning the array of pixels periodically during the integration period. In addition, a conditional data readout scheme is proposed in order to reduce the unnecessary read operations of pixel-level memories. Therefore, switching activity of data buses and dynamic por are kept under control. In our implementation, the pixel contains only 21 transistors and occupies an area of about 9μm x 9μm, with a fill factor of 12% using a 0.18μm CMOS process. Simulation results show a 50% reduction of read bit-lines switching activity at low illumination conditions, using our conditional readout scheme.
['Ka Lai Lau', 'Sylvain Leomant', 'Amine Bermak']
I am writing a research paper on a idea A Hybrid CMOS DPS with Conditional Data Readout Scheme
[{"from": "human", "value": "I am writing a research paper on a idea A Hybrid CMOS DPS with Conditional Data Readout Scheme"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a hybrid CMOS pulse width modulation (PWM) digital pixel sensor (DPS) is proposed. In order to reduce the pixel area, the proposed architecture requires only a two bit on-pixel memory while placing the remaining six bits outside the array, assuming a common resolution of eight bits. This new architecture reduces the size of the pixel significantly as the memory requirement at pixel level is divided by 4. The eight bit resolution is maintained by scanning the array of pixels periodically during the integration period. In addition, a conditional data readout scheme is proposed in order to reduce the unnecessary read operations of pixel-level memories. Therefore, switching activity of data buses and dynamic por are kept under control. In our implementation, the pixel contains only 21 transistors and occupies an area of about 9\u03bcm x 9\u03bcm, with a fill factor of 12% using a 0.18\u03bcm CMOS process. Simulation results show a 50% reduction of read bit-lines switching activity at low illumination conditions, using our conditional readout scheme."}]