Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With the arrival of crosspoint based memories on the consumer market, high-density resistive memories could be introduced as flash memories replacement or as storage class memory. Hover, transistor-Less Resistive memory architectures using 1Selector-1resistance bitcells suffer from performances loss due to sneaking current through unselected bitcells. Beyond the back end of line selector design, circuit design solutions have to be pushed in order to improve precision during programming steps.   propose a novel capacitor based 2-steps SneakPath compensation circuit for transistor-less architectures of resistive memories. Compared to standard SneakPath compensation circuits, it ensures up to 20× of area improvement and more than 3× reduction of the variability effects for a 28nm CMOS node.
['A. Levisse', 'Bastien Giraud', 'Jean-Philippe Noel', 'Mathieu Moreau', 'Jean Michel Portal']
I am writing a research paper on a idea Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures
[{"from": "human", "value": "I am writing a research paper on a idea Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With the arrival of crosspoint based memories on the consumer market, high-density resistive memories could be introduced as flash memories replacement or as storage class memory. Hover, transistor-Less Resistive memory architectures using 1Selector-1resistance bitcells suffer from performances loss due to sneaking current through unselected bitcells. Beyond the back end of line selector design, circuit design solutions have to be pushed in order to improve precision during programming steps.   propose a novel capacitor based 2-steps SneakPath compensation circuit for transistor-less architectures of resistive memories. Compared to standard SneakPath compensation circuits, it ensures up to 20\u00d7 of area improvement and more than 3\u00d7 reduction of the variability effects for a 28nm CMOS node."}]