Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Double-gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. ,  investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrodinger simulator with tight-binding Green's function approach. Then  analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. The DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture
['Deblina Sarkar', 'Samiran Ganguly', 'Deepanjan Datta', 'A. Ananda Prasad Sarab', 'Sudeb Dasgupta']
I am writing a research paper on a idea Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design
[{"from": "human", "value": "I am writing a research paper on a idea Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Double-gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. ,  investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrodinger simulator with tight-binding Green's function approach. Then  analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. The DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture"}]