Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock networks account for a significant fraction of the por dissipation of a chip and are critical to performance.  presents theory and algorithms for building a low-por clock tree by distributing the clock signal at a lor voltage and translating it to a higher voltage at the utilization points. Two low-por schemes are used: reduced swing and multiple-supply voltages.  analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that por savings of an average of 45% are possible for a 0.25 /spl mu/m technology using multiple supply voltages, and about 32% using a single external supply voltage.
['Jatuchai Pangjun', 'Sachin S. Sapatnekar']
I am writing a research paper on a idea Low-power clock distribution using multiple voltages and reduced swings
[{"from": "human", "value": "I am writing a research paper on a idea Low-power clock distribution using multiple voltages and reduced swings"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock networks account for a significant fraction of the por dissipation of a chip and are critical to performance.  presents theory and algorithms for building a low-por clock tree by distributing the clock signal at a lor voltage and translating it to a higher voltage at the utilization points. Two low-por schemes are used: reduced swing and multiple-supply voltages.  analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that por savings of an average of 45% are possible for a 0.25 /spl mu/m technology using multiple supply voltages, and about 32% using a single external supply voltage."}]