Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes a new floating-point divider (FDIV) using redundant binary circuits on an asynchronous clock scheme for an internal iterative operation. The redundant binary representation of +1=(1,0), 0=(0,0), -1+(0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the asynchronous clock reduces a clock margin overhead. The architecture design avoids post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42.1 ns with 0.35 /spl mu/m CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in 730 /spl mu/m/spl times/910 /spl mu/m area.
['Hiroaki Suzuki', 'Hiroshi Makino', 'Koichiro Mashiko', 'Hisanori Hamano']
I am writing a research paper on a idea A floating-point divider using redundant binary circuits and an asynchronous clock scheme
[{"from": "human", "value": "I am writing a research paper on a idea A floating-point divider using redundant binary circuits and an asynchronous clock scheme"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes a new floating-point divider (FDIV) using redundant binary circuits on an asynchronous clock scheme for an internal iterative operation. The redundant binary representation of +1=(1,0), 0=(0,0), -1+(0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the asynchronous clock reduces a clock margin overhead. The architecture design avoids post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42.1 ns with 0.35 /spl mu/m CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in 730 /spl mu/m/spl times/910 /spl mu/m area."}]