Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a time-mode analog signal accumulator that produces two digital signal edges whose time difference is an accumulation of sequence of time difference inputs. Our accumulator holds the time variable by the time interval of two pulses which propagate on a single ring buffers Consisting of even stages of gated inverters, eliminating calibration f drift error due to the delay mismatch beten the two pulses. The propagation of the two pulses are controlled independently o as to accumulate the input time difference into the time interval of the two pulses. Since both input and output are time difference variables and the output sample rate is synchronous t the input rate, it is easy to cascade the accumulator with other time-mode circuits as a fundamental block for time-mode signal processing. Our accumulator designed by a standard 0.18 yum MOS technology consists of only digital logic cells. Silicon measurement results show that it operates in 40 MS/s, the output is ranging from −2.9 ns to +3.2 ns with accumulated jitter of 8.8 ps for 50 times output and the average input-referred offset is −4.2 ps.
['Tomohiko Yano', 'Toru Nakura', 'Tetsuya Iizuka', 'Kunihiro Asada']
I am writing a research paper on a idea A calibration-free time difference accumulator using two pulses propagating on a single buffer ring
[{"from": "human", "value": "I am writing a research paper on a idea A calibration-free time difference accumulator using two pulses propagating on a single buffer ring"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a time-mode analog signal accumulator that produces two digital signal edges whose time difference is an accumulation of sequence of time difference inputs. Our accumulator holds the time variable by the time interval of two pulses which propagate on a single ring buffers Consisting of even stages of gated inverters, eliminating calibration f drift error due to the delay mismatch beten the two pulses. The propagation of the two pulses are controlled independently o as to accumulate the input time difference into the time interval of the two pulses. Since both input and output are time difference variables and the output sample rate is synchronous t the input rate, it is easy to cascade the accumulator with other time-mode circuits as a fundamental block for time-mode signal processing. Our accumulator designed by a standard 0.18 yum MOS technology consists of only digital logic cells. Silicon measurement results show that it operates in 40 MS/s, the output is ranging from \u22122.9 ns to +3.2 ns with accumulated jitter of 8.8 ps for 50 times output and the average input-referred offset is \u22124.2 ps."}]