Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The advancement in wireless telecommunication technologies like 3G, 4G and now 5G enrich the demand of high performance portable devices, operating at high frequencies i.e. from few hundred MHz to several GHz. High performance can only be achieved at the cost of high por dissipation. Nowadays, the use of FPGAs is rapidly increasing due to its low cost and smaller time to market. Today’s high end FPGAs are capable of implementing high performance designs such as transceivers for RF application, signal processing and image processing applications etc. This is only possible due to their complex designs that includes on chip dedicated multipliers, Dual RAM blocks, Ethernet and DCMs etc. Since FPGAs consume large amount of por, it becomes a challenge for the designers to implement low por battery operated communication systems. Several por estimation models are available in literature for early stage por estimation of FPGAs in the synthesis design flow but they provide less accuracy (high percentage error) for the designs incorporated with low por reduction technique.  presents the limitation of existing por estimation model proposed by Deng. The given model is converted into a script using MATLAB. The por values estimated from the por model (script) are compared with the high level synthesis tool: Xpor Analyzer targeted to Virtex FPGA. For estimation of por values, an embedded multiplier is synthesized for two different configurations: one with ‘CE’ (low por) and another without ‘CE’ for different I/O vector length. The results suggested that the given low level por estimation models provide less accuracy (high % error) for the designs incorporated with low por reduction technique i.e. with ‘CE’. Further, there is a scope of remodel the existing model for the observed shortcoming.
['Gaurav Verma', 'Manish Kumar', 'Vijay Khare']
I am writing a research paper on a idea Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems
[{"from": "human", "value": "I am writing a research paper on a idea Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The advancement in wireless telecommunication technologies like 3G, 4G and now 5G enrich the demand of high performance portable devices, operating at high frequencies i.e. from few hundred MHz to several GHz. High performance can only be achieved at the cost of high por dissipation. Nowadays, the use of FPGAs is rapidly increasing due to its low cost and smaller time to market. Today\u2019s high end FPGAs are capable of implementing high performance designs such as transceivers for RF application, signal processing and image processing applications etc. This is only possible due to their complex designs that includes on chip dedicated multipliers, Dual RAM blocks, Ethernet and DCMs etc. Since FPGAs consume large amount of por, it becomes a challenge for the designers to implement low por battery operated communication systems. Several por estimation models are available in literature for early stage por estimation of FPGAs in the synthesis design flow but they provide less accuracy (high percentage error) for the designs incorporated with low por reduction technique.  presents the limitation of existing por estimation model proposed by Deng. The given model is converted into a script using MATLAB. The por values estimated from the por model (script) are compared with the high level synthesis tool: Xpor Analyzer targeted to Virtex FPGA. For estimation of por values, an embedded multiplier is synthesized for two different configurations: one with \u2018CE\u2019 (low por) and another without \u2018CE\u2019 for different I/O vector length. The results suggested that the given low level por estimation models provide less accuracy (high % error) for the designs incorporated with low por reduction technique i.e. with \u2018CE\u2019. Further, there is a scope of remodel the existing model for the observed shortcoming."}]