Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , an efficient yet accurate model for extracting analytical expressions for throughput and latency of asynchronous pipeline styles is presented. The model is then applied to ten styles including GasP, MOUSETRAP, IPCMOS, LP/sub SR/2/1, LP/sub HC/, STFB, LDA, LP2/1, RSPCFB and NCL. The first five designs are based on the bundled-data (BD) category while the last five are based on the data-driven (DD) category. The performance of the styles are compared in terms of throughput, latency, por dissipation and transistor count. A figure of merit for the energy consumption and the performance is used to determine the better styles. The results of the analytical model are compared with (pre-layout) HSPICE simulation with a 0.18 /spl mu/m CMOS technology revealing a very good accuracy for the proposed model.
['Mohammad Ali Gholipour', 'K. Shojaee', 'Ali Afzali-Kusha', 'Ahmad Khademzadeh', 'M. Nourani']
I am writing a research paper on a idea An efficient model for performance analysis of asynchronous pipeline design methods
[{"from": "human", "value": "I am writing a research paper on a idea An efficient model for performance analysis of asynchronous pipeline design methods"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , an efficient yet accurate model for extracting analytical expressions for throughput and latency of asynchronous pipeline styles is presented. The model is then applied to ten styles including GasP, MOUSETRAP, IPCMOS, LP/sub SR/2/1, LP/sub HC/, STFB, LDA, LP2/1, RSPCFB and NCL. The first five designs are based on the bundled-data (BD) category while the last five are based on the data-driven (DD) category. The performance of the styles are compared in terms of throughput, latency, por dissipation and transistor count. A figure of merit for the energy consumption and the performance is used to determine the better styles. The results of the analytical model are compared with (pre-layout) HSPICE simulation with a 0.18 /spl mu/m CMOS technology revealing a very good accuracy for the proposed model."}]