Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: High performance integrated circuits are now reaching the 100-plus watt regime, and por delivery and por grid signal integrity have become critical. Analyzing the performance of the por delivery system requires knowledge of the the current drawn by the functional blocks that comprise a typical hierarchical design. Hover, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location.  uses information about the por dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact ILP method is first developed, follod by an effective heuristic to speed up the exact method. A circuit of 43K nodes is analyzed within 70 seconds, and the worst-case scenarios found correlate ll with the results from an ILP solver.
['Haifeng Qian', 'Sani R. Nassif', 'Sachin S. Sapatnekar']
I am writing a research paper on a idea Early-stage power grid analysis for uncertain working modes
[{"from": "human", "value": "I am writing a research paper on a idea Early-stage power grid analysis for uncertain working modes"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: High performance integrated circuits are now reaching the 100-plus watt regime, and por delivery and por grid signal integrity have become critical. Analyzing the performance of the por delivery system requires knowledge of the the current drawn by the functional blocks that comprise a typical hierarchical design. Hover, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location.  uses information about the por dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact ILP method is first developed, follod by an effective heuristic to speed up the exact method. A circuit of 43K nodes is analyzed within 70 seconds, and the worst-case scenarios found correlate ll with the results from an ILP solver."}]