Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low por. When these interconnects are used in large scale and high volume digital systems their testability becomes very important.  discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a ak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.
['K. Naveen', 'Dinesh Kumar Sharma']
I am writing a research paper on a idea Testable design of repeaterless low swing on-chip interconnect
[{"from": "human", "value": "I am writing a research paper on a idea Testable design of repeaterless low swing on-chip interconnect"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low por. When these interconnects are used in large scale and high volume digital systems their testability becomes very important.  discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a ak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology."}]