Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a novel VLSI architecture for computing the N-point discrete Fourier transform (DFT) based on a radix-2 fast algorithm, where N is a por of two. The architecture consists of one complex multiplier, two complex adders, and some special memory units. It can compute one transform sample every log/sub 2/N+1 clock cycles in average. For the case of N=512, the chip area required is about 5742/spl times/5222 /spl mu/m/sup 2/ and the throughput is up to 4 M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes the proposed design rather attractive for use in long-length DFT applications, such as ADSL and OFDM systems.
['Ching-Hsien Chang', 'Chin-Liang Wang', 'Yu-Tai Chang']
I am writing a research paper on a idea A novel memory-based FFT processor for DMT/OFDM applications
[{"from": "human", "value": "I am writing a research paper on a idea A novel memory-based FFT processor for DMT/OFDM applications"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a novel VLSI architecture for computing the N-point discrete Fourier transform (DFT) based on a radix-2 fast algorithm, where N is a por of two. The architecture consists of one complex multiplier, two complex adders, and some special memory units. It can compute one transform sample every log/sub 2/N+1 clock cycles in average. For the case of N=512, the chip area required is about 5742/spl times/5222 /spl mu/m/sup 2/ and the throughput is up to 4 M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes the proposed design rather attractive for use in long-length DFT applications, such as ADSL and OFDM systems."}]