Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC por and performance. Migrating to fine-grained 3-D, to advance scaling, has been elusive due to incompatibility of CMOS in 3-D.  propose a new 3-D IC fabric, called Skybridge that addresses device, circuit, connectivity, heat management and manufacturing requirements in integrated 3D compatible manner. Our bottom-up evaluations accounting for material structures, manufacturing process, device, and circuit parasitics, reveal 60.5x density, and 16.5x performance/Watts benefits compared to CMOS for a 16-bit CLA. Experimental demonstration of the core device concept and key manufacturing steps mitigate technology risks.
['Mostafizur Rahman', 'Santosh Khasanvis', 'Jiajun Shi', 'Mingyu Li', 'Csaba Andras Moritz']
I am writing a research paper on a idea Fine-grained 3-D integrated circuit fabric using vertical nanowires
[{"from": "human", "value": "I am writing a research paper on a idea Fine-grained 3-D integrated circuit fabric using vertical nanowires"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Continuous scaling of CMOS to sub-20nm technologies is proving to be challenging as MOSFETs are reaching fundamental limits and interconnection bottleneck is dominating IC por and performance. Migrating to fine-grained 3-D, to advance scaling, has been elusive due to incompatibility of CMOS in 3-D.  propose a new 3-D IC fabric, called Skybridge that addresses device, circuit, connectivity, heat management and manufacturing requirements in integrated 3D compatible manner. Our bottom-up evaluations accounting for material structures, manufacturing process, device, and circuit parasitics, reveal 60.5x density, and 16.5x performance/Watts benefits compared to CMOS for a 16-bit CLA. Experimental demonstration of the core device concept and key manufacturing steps mitigate technology risks."}]