Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN – IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB.
['Vikram Arkalgud Chandrasetty', 'Syed Mahfuzul Aziz']
I am writing a research paper on a idea FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm
[{"from": "human", "value": "I am writing a research paper on a idea FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN \u2013 IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB."}]