Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In order to cope with the increasing leakage por and the increasing device variability in VLSI’s, the required control size of both the space-domain and the time-domain is decreasing.  shows the several recent fine-grain voltage engineerings for the low por VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain por supply voltage with 3D-structured on-chip buck converters with the maximum por efficiency up to 71.3% in 0.35-µm CMOS and the fine-grain body bias control to reduce por supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the por supply voltage hopping with a 5-ns transition time in 0.18-µm CMOS, the por supply noise canceller with the 32% por supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS.
['Makoto Takamiya', 'Takayasu Sakurai']
I am writing a research paper on a idea Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering
[{"from": "human", "value": "I am writing a research paper on a idea Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In order to cope with the increasing leakage por and the increasing device variability in VLSI\u2019s, the required control size of both the space-domain and the time-domain is decreasing.  shows the several recent fine-grain voltage engineerings for the low por VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain por supply voltage with 3D-structured on-chip buck converters with the maximum por efficiency up to 71.3% in 0.35-\u00b5m CMOS and the fine-grain body bias control to reduce por supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the por supply voltage hopping with a 5-ns transition time in 0.18-\u00b5m CMOS, the por supply noise canceller with the 32% por supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS."}]