Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes a design of a fine-grain multiple-valued field-programmable VLSI (MV-FPVLSI) based on multiple-valued source-coupled logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35 /spl mu/m standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized por consumption better performance can be achieved if the linear summation with ight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.
['Haque Mohammad Munirul', 'Tomoaki Hasegawa', 'Michitaka Kameyama']
I am writing a research paper on a idea Implementation and evaluation of a fine-grain multiple-valued field programmable VLSI based on source-coupled logic
[{"from": "human", "value": "I am writing a research paper on a idea Implementation and evaluation of a fine-grain multiple-valued field programmable VLSI based on source-coupled logic"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describes a design of a fine-grain multiple-valued field-programmable VLSI (MV-FPVLSI) based on multiple-valued source-coupled logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35 /spl mu/m standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized por consumption better performance can be achieved if the linear summation with ight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint."}]