Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Decomposition of a matrix into lor and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications, and the block LU decomposition algorithm is an approach ll suited to parallel hardware implementation.  presents an approach to speed up implementation of the block LU decomposition algorithm using FPGA hardware. Unlike most previous approaches reported in the literature, the approach does not assume the matrix can be stored entirely on chip. The memory accesses are studied for various FPGA configurations, and a schedule of operations for scaling ll is shown. The design has been synthesized for FPGA targets and can be easily retargeted. The design outperforms previous hardware implementations, as ll as tuned software implementations including the ATLAS and MKL libraries on workstations.
['Manish Kumar Jaiswal', 'Nitin Chandrachoodan']
I am writing a research paper on a idea FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture
[{"from": "human", "value": "I am writing a research paper on a idea FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Decomposition of a matrix into lor and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications, and the block LU decomposition algorithm is an approach ll suited to parallel hardware implementation.  presents an approach to speed up implementation of the block LU decomposition algorithm using FPGA hardware. Unlike most previous approaches reported in the literature, the approach does not assume the matrix can be stored entirely on chip. The memory accesses are studied for various FPGA configurations, and a schedule of operations for scaling ll is shown. The design has been synthesized for FPGA targets and can be easily retargeted. The design outperforms previous hardware implementations, as ll as tuned software implementations including the ATLAS and MKL libraries on workstations."}]