Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working.  focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. ,  design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching.
['Ryo Tamura', 'Masayuki Honma', 'Nozomu Togawa', 'Masao Yanagisawa', 'Tatsuo Ohtsuki', 'Makoto Satoh']
I am writing a research paper on a idea FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm
[{"from": "human", "value": "I am writing a research paper on a idea FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working.  focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. ,  design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching."}]