Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The article describes a Fault-Tolerant Reconfigurable Low-por pseudoRandom number Generator (FT_RLRG) which integrates both Fibonacci and Galois LFSRs into a single hardware core. The design of FT_RLRG is of practical interest in testing triple modular fault-tolerant systems in the presence of single event upsets (SEUs), especially in case when the system is SRAM based. The main idea is to design a low-cost and low-por hardware structure which is able to adapt to any standard operating at high-speed with different polynomials (currently up to 32 nd  order). Proposed FT_RLRG design was implemented as an ASIC in the IHP's 130 nm CMOS technology.
['Vladimir Petrovic', 'Zoran Stamenkovic', 'Mile K. Stojcev', 'Tatjana R. Nikolic', 'Goran Jovanović']
I am writing a research paper on a idea Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator
[{"from": "human", "value": "I am writing a research paper on a idea Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The article describes a Fault-Tolerant Reconfigurable Low-por pseudoRandom number Generator (FT_RLRG) which integrates both Fibonacci and Galois LFSRs into a single hardware core. The design of FT_RLRG is of practical interest in testing triple modular fault-tolerant systems in the presence of single event upsets (SEUs), especially in case when the system is SRAM based. The main idea is to design a low-cost and low-por hardware structure which is able to adapt to any standard operating at high-speed with different polynomials (currently up to 32 nd  order). Proposed FT_RLRG design was implemented as an ASIC in the IHP's 130 nm CMOS technology."}]