Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A synchronous DC-DC buck converter with integrated por switches is realized in a 65 nm CMOS technology, operating with a por inductor of 350 nH and an output capacitor of 470 nF as a chip-on-board prototype. The converter is designed for loads up to 120 mA and is targeted as replacement for LDOs in VLSI systems where multiple supplies must be provided. A dead time optimization algorithm continuously adjusts the dead times of the por switches in order to minimize body diode conduction losses. The whole converter occupies 0.088 mm 2  chip area.
['Gerhard Maderbacher', 'Thomas Jackum', 'Wolfgang Pribyl', 'Michael Wassermann', 'Andreas Petschar', 'Christoph Sandner']
I am writing a research paper on a idea Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS
[{"from": "human", "value": "I am writing a research paper on a idea Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A synchronous DC-DC buck converter with integrated por switches is realized in a 65 nm CMOS technology, operating with a por inductor of 350 nH and an output capacitor of 470 nF as a chip-on-board prototype. The converter is designed for loads up to 120 mA and is targeted as replacement for LDOs in VLSI systems where multiple supplies must be provided. A dead time optimization algorithm continuously adjusts the dead times of the por switches in order to minimize body diode conduction losses. The whole converter occupies 0.088 mm 2  chip area."}]