Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS is presented. Single-ended comparators are formed using digital inverters and resistors. The comparators are designed for compatibility with nanoscale CMOS lithography. A single-ended flash architecture was used without a front-end sample-and-hold. The ADC achieves a low frequency effective number of bits (ENOB) beten 4.08 bits and 4.45 bits without calibration. Voltage scaling is demonstrated by 60 MS/s, 300 MS/s, and 600 MS/s operation at 0.6 V, 0.8 V, and 1 V, respectively. Por scales from 1.3 mW to 6.7 mW.
['Jonathan E. Proesel', 'Lawrence T. Pileggi']
I am writing a research paper on a idea A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS
[{"from": "human", "value": "I am writing a research paper on a idea A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 0.6-to-1 V inverter-based 5-bit flash ADC in 90 nm digital CMOS is presented. Single-ended comparators are formed using digital inverters and resistors. The comparators are designed for compatibility with nanoscale CMOS lithography. A single-ended flash architecture was used without a front-end sample-and-hold. The ADC achieves a low frequency effective number of bits (ENOB) beten 4.08 bits and 4.45 bits without calibration. Voltage scaling is demonstrated by 60 MS/s, 300 MS/s, and 600 MS/s operation at 0.6 V, 0.8 V, and 1 V, respectively. Por scales from 1.3 mW to 6.7 mW."}]