Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an optimal methodology of scheduling/mapping of fully deterministic digital signal processing algorithms onto any generic very long instruction word (VLIW) digital signal processor (DSP). The VLIW DSPs can be broadly classified as heterogeneous and homogenous depending upon their architecture. The methodology is equally efficient on heterogeneous as ll as on homogeneous VLIW DSPs. An equivalent model of the algorithm and the DSP is generated using mixed integer programming (MIP). A framework is developed to generate the MIP models. The framework also incorporates a MIP solver to solve the generated MIP model. The framework also helps in defining the architecture of the VLIW and then generating an exact model of the processor. After solving the MIP it gives an optimal schedule/mapping of the algorithm onto the DSP. The framework also encompasses a code generator that takes the mapping information in generating an assembly code of the VLIW processor.
['Muhammad Sohail Sadiq', 'Shoab A. Khan']
I am writing a research paper on a idea Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs
[{"from": "human", "value": "I am writing a research paper on a idea Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an optimal methodology of scheduling/mapping of fully deterministic digital signal processing algorithms onto any generic very long instruction word (VLIW) digital signal processor (DSP). The VLIW DSPs can be broadly classified as heterogeneous and homogenous depending upon their architecture. The methodology is equally efficient on heterogeneous as ll as on homogeneous VLIW DSPs. An equivalent model of the algorithm and the DSP is generated using mixed integer programming (MIP). A framework is developed to generate the MIP models. The framework also incorporates a MIP solver to solve the generated MIP model. The framework also helps in defining the architecture of the VLIW and then generating an exact model of the processor. After solving the MIP it gives an optimal schedule/mapping of the algorithm onto the DSP. The framework also encompasses a code generator that takes the mapping information in generating an assembly code of the VLIW processor."}]