Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Multiple-voltage is an effective dynamic por reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; hover switching beten several supply voltage settings has a detrimental impact on the overall cost of test.  proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lor overhead than the recently proposed Test Point Insertion technique in terms of timing, area and por.
['Syed Saqib Khursheed', 'Bashir M. Al-Hashimi', 'Peter Harrod']
I am writing a research paper on a idea Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing
[{"from": "human", "value": "I am writing a research paper on a idea Test cost reduction for multiple-voltage designs with bridge defects through gate-sizing"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Multiple-voltage is an effective dynamic por reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; hover switching beten several supply voltage settings has a detrimental impact on the overall cost of test.  proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lor overhead than the recently proposed Test Point Insertion technique in terms of timing, area and por."}]