Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the por at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the por consumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74%of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns.
['Jochen Preiss', 'Maarten Boersma', 'Silvia Melitta Mueller']
I am writing a research paper on a idea Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
[{"from": "human", "value": "I am writing a research paper on a idea Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the por at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the por consumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74%of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns."}]