Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, por, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. It is empirical to consider the system-on-chip (SoC) context to choose the most critical process knobs since most of processing budget to scale a technology node is already consumed by increasing process steps due to multiple patterning.   will show that the device parasitics and the interconnect resistance are the most critical performance scaling barriers for technology nodes beyond 7 nm (N7).  will demonstrate the impact of process and design knobs enabling performance and por improvements for the N7 node as defined in ITRS 2015 edition while still continuing to scale the area to limit the cost.
['Mustafa Badaroglu', 'Jeff Xu']
I am writing a research paper on a idea Interconnect-aware device targeting from PPA perspective
[{"from": "human", "value": "I am writing a research paper on a idea Interconnect-aware device targeting from PPA perspective"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, por, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. It is empirical to consider the system-on-chip (SoC) context to choose the most critical process knobs since most of processing budget to scale a technology node is already consumed by increasing process steps due to multiple patterning.   will show that the device parasitics and the interconnect resistance are the most critical performance scaling barriers for technology nodes beyond 7 nm (N7).  will demonstrate the impact of process and design knobs enabling performance and por improvements for the N7 node as defined in ITRS 2015 edition while still continuing to scale the area to limit the cost."}]