Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the spike sorting on chips. To support realtime spike sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic por in data caching.  propose to use the parallel-folding structure to optimally tradeoff the area and por. Our 128-channel spike sorting processor consumes 1.36 mm 2  area and 1.87 mW por in 90 nm process. 91.1% and 63.4% of the hardware resources (area×por) are reduced compared to the fully parallel and the fully folding approaches respectively.
['Tung-Chien Chen', 'Wentai Liu', 'Liang-Gee Chen']
I am writing a research paper on a idea 128-channel spike sorting processor with a parallel-folding structure in 90nm process
[{"from": "human", "value": "I am writing a research paper on a idea 128-channel spike sorting processor with a parallel-folding structure in 90nm process"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: An emerging class of neural prostheses aims to provide more aggressive performance by realizing advanced realtime signal processing algorithms in particular the spike sorting on chips. To support realtime spike sorting for 128 channels, the traditional fully parallel approach duplicating 128 processing units results in a large burden on chip area. The fully folding approach sharing one processor over 128 channels consumes large dynamic por in data caching.  propose to use the parallel-folding structure to optimally tradeoff the area and por. Our 128-channel spike sorting processor consumes 1.36 mm 2  area and 1.87 mW por in 90 nm process. 91.1% and 63.4% of the hardware resources (area\u00d7por) are reduced compared to the fully parallel and the fully folding approaches respectively."}]