Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  proposes a new technique of por-aware test pattern generation, wherein the test mode por constraints are specified using pseudo hardware logic functions (referred to as por constraint circuits) that augment the target circuit fed to the ATPG tool. The novelty of this approach is three-fold: (i) The ATPG tool only sees the enhanced circuit. This influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) Pattern generation can be driven to minimize test por according to a programmable switching activity threshold, and hence, is scalable. (iii) The same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. Additionally, the proposed method does not require any changes to the pattern generation tool or process.  describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. Experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach.
['Srivaths Ravi', 'V. R. Devanathan', 'Rubin A. Parekhji']
I am writing a research paper on a idea Methodology for low power test pattern generation using activity threshold control logic
[{"from": "human", "value": "I am writing a research paper on a idea Methodology for low power test pattern generation using activity threshold control logic"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  proposes a new technique of por-aware test pattern generation, wherein the test mode por constraints are specified using pseudo hardware logic functions (referred to as por constraint circuits) that augment the target circuit fed to the ATPG tool. The novelty of this approach is three-fold: (i) The ATPG tool only sees the enhanced circuit. This influences the generation of the test cubes themselves, as against post-processing of these cubes for a given pattern. (ii) Pattern generation can be driven to minimize test por according to a programmable switching activity threshold, and hence, is scalable. (iii) The same constraint circuit can also be effectively used for pattern filtering to isolate patterns which cause high switching activity. Additionally, the proposed method does not require any changes to the pattern generation tool or process.  describes the methodology, together with techniques for realizing the hardware circuit and specifying thresholds. Experimental results on various benchmark circuits (including an industrial design) are presented to show the effectiveness of this approach."}]