Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration beten devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work  present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in por regarding the whole chip design.
['Cezar Reinbrecht', 'Altamiro Amadeu Susin', 'Lilian Bossuet', 'Johanna Sepúlveda']
I am writing a research paper on a idea Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management
[{"from": "human", "value": "I am writing a research paper on a idea Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration beten devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work  present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in por regarding the whole chip design."}]