Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was reduced by adjusting the charge pump current and the loop filter capacitor. There was a trade-off beten the lock time, loop filter capacitor, and ripples on the output of the VCO. Design procedures and simulation results are illustrated.
['Harshitha Janardhan']
I am writing a research paper on a idea Design of a 1GHz Digital PLL Using 0.18\mu m CMOS Technology
[{"from": "human", "value": "I am writing a research paper on a idea Design of a 1GHz Digital PLL Using 0.18\\mu m CMOS Technology"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was reduced by adjusting the charge pump current and the loop filter capacitor. There was a trade-off beten the lock time, loop filter capacitor, and ripples on the output of the VCO. Design procedures and simulation results are illustrated."}]