Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A ll-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently, as ll as how to bridge the gap beten the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths. ,  will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PorPC/spl trade/ instruction set architecture.
['Jing Zeng', 'Magdy S. Abadir', 'Jacob A. Abraham']
I am writing a research paper on a idea False timing path identification using ATPG techniques and delay-based information
[{"from": "human", "value": "I am writing a research paper on a idea False timing path identification using ATPG techniques and delay-based information"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A ll-known problem in timing verification of VLSI circuits using static timing analysis tools is the generation of false timing paths. This leads to a pessimistic estimation of the processor speed and wasted engineering effort spent optimizing unsensitizable paths. Earlier results have shown how ATPG techniques can be used to identify false paths efficiently, as ll as how to bridge the gap beten the physical design on which the static timing analysis is based and the test view on which ATPG technique is applied to identify false paths. ,  will demonstrate efficient techniques to identify more false timing paths by utilizing information from an ordered list of timing paths according to the delay information. More than 10% of additional false timing paths out of the total timing paths analyzed are identified compared to earlier results on the MPC7455, a Motorola processor executing to the PorPC/spl trade/ instruction set architecture."}]