Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs re processed on chip backside after oxide bonding and substrate thinning. The results re compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400°C. This demonstration is the first step to validate the industrial compatibility beten high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mOhm and a capacitance of about 30 fF, 3 µm-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs.
['Patrick Leduc', 'Myriam Assous', 'Lea Di Cioccio', 'Marc Zussy', 'Thomas Signamarcheix', 'Antonio Roman', 'Maxime Rousseau', 'S. Verrun', 'Laurent Bally', 'David Bouchu', 'Lionel Cadix', 'A. Farcy', 'N. Sillon']
I am writing a research paper on a idea First integration of Cu TSV using die-to-wafer direct bonding and planarization
[{"from": "human", "value": "I am writing a research paper on a idea First integration of Cu TSV using die-to-wafer direct bonding and planarization"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Copper-filled Through-Si Vias (TSV) with diameters from 2 \u00b5m to 5 \u00b5m have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs re processed on chip backside after oxide bonding and substrate thinning. The results re compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400\u00b0C. This demonstration is the first step to validate the industrial compatibility beten high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mOhm and a capacitance of about 30 fF, 3 \u00b5m-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs."}]