Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flip-flops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flip-flop can reduce up to 48% por consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.
['Govinda Sannena', 'Bishnu Prasad Das']
I am writing a research paper on a idea A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance
[{"from": "human", "value": "I am writing a research paper on a idea A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flip-flops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flip-flop can reduce up to 48% por consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design."}]