Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:   present a local strategy for sizing CMOS circuits.  show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed / area performances are given for a linear matrix style layout implementation.
['Daniel Auvergne', 'Nadine Azémard', 'Vincent Bonzom', 'Denis Deschacht', 'Michel Robert']
I am writing a research paper on a idea Formal sizing rules of CMOS circuits
[{"from": "human", "value": "I am writing a research paper on a idea Formal sizing rules of CMOS circuits"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:   present a local strategy for sizing CMOS circuits.  show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed / area performances are given for a linear matrix style layout implementation."}]