Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 75 mm  $^{2}$    low por 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% por reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance.
['Mario Sako', 'Yoshihisa Watanabe', 'Takao Nakajima', 'Jumpei Sato', 'Kazuyoshi Muraoka', 'Masaki Fujiu', 'Fumihiro Kono', 'Michio Nakagawa', 'Masami Masuda', 'Koji Kato', 'Yuri Terada', 'Yuki Shimizu', 'Mitsuaki Honma', 'Akihiro Imamoto', 'Tomoko Araya', 'Hayato Konno', 'Takuya Okanaga', 'Tomofumi Fujimura', 'Xiaoqing Wang', 'Mai Muramoto', 'Masahiro Kamoshida', 'Masatoshi Kohno', 'Yoshinao Suzuki', 'Tomoharu Hashiguchi', 'Tsukasa Kobayashi', 'Masashi Yamaoka', 'Ryuji Yamashita']
I am writing a research paper on a idea A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology
[{"from": "human", "value": "I am writing a research paper on a idea A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: A 75 mm  $^{2}$    low por 64 Gb MLC NAND flash memory capable of 30 MB/s program throughput and 533 MB/s data transfer rate at 1.8 V supply voltage is developed in 15 nm CMOS technology. 36% por reduction from 3.3 V design is achieved by a new pumping scheme. New low current peak features reduce a multi-die concurrent programming peak by 65% for 4-die case, and an erase verifying peak by 40%, respectively. Nanoscale transistors reducing bit-line discharge time by 70% is introduced to improve performance."}]