Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Electromigration (EM) is a growing reliability concern in sub-22nm technology. Design teams must apply guardbands to meet EM lifetime requirements, at the cost of performance and por. Hover, EM lifetime analysis cannot ignore front-end reliability mechanisms such as bias temperature instability (BTI). Although the gate delay degradation due to BTI can be compensated by adaptive voltage scaling (AVS), any elevated supply voltage will accelerate EM degradation and reduce lifetime. Since the degradation of BTI is front-loaded, AVS can increase electrical stress on metal wires relatively early during IC lifetime, which can significantly decrease electromigration reliability. ,  study the "chicken-egg" interlock among BTI, AVS and EM and quantify timing and por costs of meeting EM lifetime requirements with full consideration of BTI and AVS mechanisms. By applying existing statistical and physical EM models,  demonstrate that without such considerations, the inaccuracy (reduction) of EM lifetime due to improper guardband against BTI at signoff can be as high as 30% in a 28nm FDSOI foundry technology. Furthermore,  provide signoff guidelines which suggest that the lifetime penalty can be compensated by paying a penalty of up to 1.6% in area and 6% in por.  also demonstrate that suboptimal choice of voltage step size and scheduling strategy can result in up to 1.5 years of decreased EM lifetime.
['Wei-Ting Jonas Chan', 'Andrew B. Kahng', 'Siddhartha Nath']
I am writing a research paper on a idea Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling
[{"from": "human", "value": "I am writing a research paper on a idea Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Electromigration (EM) is a growing reliability concern in sub-22nm technology. Design teams must apply guardbands to meet EM lifetime requirements, at the cost of performance and por. Hover, EM lifetime analysis cannot ignore front-end reliability mechanisms such as bias temperature instability (BTI). Although the gate delay degradation due to BTI can be compensated by adaptive voltage scaling (AVS), any elevated supply voltage will accelerate EM degradation and reduce lifetime. Since the degradation of BTI is front-loaded, AVS can increase electrical stress on metal wires relatively early during IC lifetime, which can significantly decrease electromigration reliability. ,  study the \"chicken-egg\" interlock among BTI, AVS and EM and quantify timing and por costs of meeting EM lifetime requirements with full consideration of BTI and AVS mechanisms. By applying existing statistical and physical EM models,  demonstrate that without such considerations, the inaccuracy (reduction) of EM lifetime due to improper guardband against BTI at signoff can be as high as 30% in a 28nm FDSOI foundry technology. Furthermore,  provide signoff guidelines which suggest that the lifetime penalty can be compensated by paying a penalty of up to 1.6% in area and 6% in por.  also demonstrate that suboptimal choice of voltage step size and scheduling strategy can result in up to 1.5 years of decreased EM lifetime."}]