Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in  heterogeneous  computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency.  report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms.
['Alessandro Marongiu', 'Paolo Palazzari', 'Vittorio Rosato']
I am writing a research paper on a idea Parallel Dedicated Hardware Devices for Heterogeneous Computations
[{"from": "human", "value": "I am writing a research paper on a idea Parallel Dedicated Hardware Devices for Heterogeneous Computations"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  describe a design methodology which allows a fast design and prototyping of dedicated hardware devices to be used in  heterogeneous  computations. The platforms used in heterogeneous computations consist of a general-purpose COTS architecture which hosts a dedicated hardware device; parts of the computation are mapped onto the former, parts onto the latter, in a way to improve the overall computation efficiency.  report the design and the prototyping of a FPGA-based hardware board to be used in the search of low-autocorrelation binary sequences. The circuit has been designed by using a recently developed Parallel Hardware Generator (PHG) package which produces a synthesizable VHDL code starting from the specific algorithm expressed as a System of Affine Recurrence Equations (SARE). The performance of the realized devices has been compared to those obtained on the same numerical application on several computational platforms."}]