Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an innovative and safe connected health solution for human identification. The system consists of the encryption and decryption of ECG signals using the advanced encryption standard (AES) as ll as the recognition of individuals based on ECG biometrics. Heterogeneous and efficient implementation of the proposed system has been performed on a Xilinx ZC702 Zynq based prototyping board. Various IP-cores have been created based on the high level synthesis (HLS) implementation of the AES cipher, AES decipher and ECG identification blocks. The proposed hardware implementation has shown promising results since it met the real-time requirements and outclassed current field programmable gate array (FPGA) based systems in multiple key metrics including por consumption, processing time and hardware resources usage. The implemented system needs 10.71 ms to process one ECG sample and consumes 107mW while using only 30% of all available on-chip resources.
['Amine Ait Si Ali', 'Xiaojun Zhai', 'Abbes Amira', 'Faycal Bensaali', 'Naeem Ramzan']
I am writing a research paper on a idea Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC
[{"from": "human", "value": "I am writing a research paper on a idea Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents an innovative and safe connected health solution for human identification. The system consists of the encryption and decryption of ECG signals using the advanced encryption standard (AES) as ll as the recognition of individuals based on ECG biometrics. Heterogeneous and efficient implementation of the proposed system has been performed on a Xilinx ZC702 Zynq based prototyping board. Various IP-cores have been created based on the high level synthesis (HLS) implementation of the AES cipher, AES decipher and ECG identification blocks. The proposed hardware implementation has shown promising results since it met the real-time requirements and outclassed current field programmable gate array (FPGA) based systems in multiple key metrics including por consumption, processing time and hardware resources usage. The implemented system needs 10.71 ms to process one ECG sample and consumes 107mW while using only 30% of all available on-chip resources."}]