Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: An efficient layout-level optimization technique based on NN+TLBO algorithm is presented to maximize the quality factor of on-chip spiral inductors at a given frequency. A multi-layer artificial neural network (ANN) is developed to model the on-chip inductors. TLBO algorithm is used in order to optimize the layout space for the on-chip spiral inductors considering constraints of design specifications and desired accuracy level. A four-way K-band lumped-element por divider (PD) is designed in 0.18m CMOS technology to validate the characterized spiral inductor. The PD achieves an insertion loss less than 2.1 dB, an input return loss better than 10 dB, an output return loss less than 12 dB, and a port-to-port isolation higher than 14 dB from 18 to 26 GHz (K-Band). The chip area is about 0.415 mm 2 including bonding pads.
['Mehdi Askari', 'Hooman Kaabi', 'Yousef S. Kavian']
I am writing a research paper on a idea Optimization of on-chip spiral inductors using coupled NN and TLBO algorithms for low-loss lumped-element CMOS power dividers
[{"from": "human", "value": "I am writing a research paper on a idea Optimization of on-chip spiral inductors using coupled NN and TLBO algorithms for low-loss lumped-element CMOS power dividers"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: An efficient layout-level optimization technique based on NN+TLBO algorithm is presented to maximize the quality factor of on-chip spiral inductors at a given frequency. A multi-layer artificial neural network (ANN) is developed to model the on-chip inductors. TLBO algorithm is used in order to optimize the layout space for the on-chip spiral inductors considering constraints of design specifications and desired accuracy level. A four-way K-band lumped-element por divider (PD) is designed in 0.18m CMOS technology to validate the characterized spiral inductor. The PD achieves an insertion loss less than 2.1 dB, an input return loss better than 10 dB, an output return loss less than 12 dB, and a port-to-port isolation higher than 14 dB from 18 to 26 GHz (K-Band). The chip area is about 0.415 mm 2 including bonding pads."}]