Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Aggressive silicon process scaling over the last years has made transistors faster and less por consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors. In this work,  present CASTED, a Core-Adaptive Soft- ware Transient Error Detection methodology that focuses on improving the impact of error detection overhead on single- chip scalable architectures that are composed of tightly coupled cores. The proposed compiler methodology adaptively distributes the error detection overhead to the available resources across multiple cores, fully exploiting the abundant ILP of these architectures. CASTED adapts to a wide range of architecture configurations (issue-width, inter-core delay).  evaluate our technique on a range of architecture configurations using the MediabenchII video and SPEC CINT2000 benchmark suites. Our approach successfully adapts to (and regularly outperforms by up to 21.2%) the best fixed state-of- the-art approach while maintaining the same fault coverage.
['Konstantina Mitropoulou', 'Vasileios Porpodas', 'Marcelo Cintra']
I am writing a research paper on a idea CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores
[{"from": "human", "value": "I am writing a research paper on a idea CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Aggressive silicon process scaling over the last years has made transistors faster and less por consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors. In this work,  present CASTED, a Core-Adaptive Soft- ware Transient Error Detection methodology that focuses on improving the impact of error detection overhead on single- chip scalable architectures that are composed of tightly coupled cores. The proposed compiler methodology adaptively distributes the error detection overhead to the available resources across multiple cores, fully exploiting the abundant ILP of these architectures. CASTED adapts to a wide range of architecture configurations (issue-width, inter-core delay).  evaluate our technique on a range of architecture configurations using the MediabenchII video and SPEC CINT2000 benchmark suites. Our approach successfully adapts to (and regularly outperforms by up to 21.2%) the best fixed state-of- the-art approach while maintaining the same fault coverage."}]