Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a design for testability and minimum leakage pattern generation technique to reduce static por during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage por are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static por is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static por without changing the manufacturing process or library cells.
['Wei-Chung Kao', 'Wei-Shun Chuang', 'Hsiu-Ting Lin', 'James Chien-Mo Li', 'Vasco M. Manquinho']
I am writing a research paper on a idea DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In
[{"from": "human", "value": "I am writing a research paper on a idea DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a design for testability and minimum leakage pattern generation technique to reduce static por during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage por are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static por is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static por without changing the manufacturing process or library cells."}]