Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The current work is focused towards the development of algorithms and CAD tools for the design of digital circuits with on line testing capability. The methodology is based on the theory of fault detection and diagnosis of discrete event systems. The paper deals with optimization of the algorithms of fault detection to alleviate the problem of state explosion based on symbolic techniques like "ordered binary decision diagrams" and "abstraction". With the help of these algorithms a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capabilities and can handle generic digital circuits with cell count as high as 15,000 and about 2500 states. Further, this methodology provides the designer with a wide range of tradeoffs in detector design: fault coverage and detection latency vs. area and por overhead.
['Santosh Biswas', 'Siddhartha Mukhopadhyay', 'Amit Patra']
I am writing a research paper on a idea A discrete event systems approach to online testing of digital VLSI circuits
[{"from": "human", "value": "I am writing a research paper on a idea A discrete event systems approach to online testing of digital VLSI circuits"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The current work is focused towards the development of algorithms and CAD tools for the design of digital circuits with on line testing capability. The methodology is based on the theory of fault detection and diagnosis of discrete event systems. The paper deals with optimization of the algorithms of fault detection to alleviate the problem of state explosion based on symbolic techniques like \"ordered binary decision diagrams\" and \"abstraction\". With the help of these algorithms a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capabilities and can handle generic digital circuits with cell count as high as 15,000 and about 2500 states. Further, this methodology provides the designer with a wide range of tradeoffs in detector design: fault coverage and detection latency vs. area and por overhead."}]