Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The automatic test equipment (ATE) is an instrument used to apply a set of pre-defined test pattern to analyze the response from the semiconductor chip. Automatic test pattern generation and selection for a pre-defined pattern are popular research topics to improve the overall fault coverage (Bushnell and Agrawal, 2000) of the design. This process is normally based on a very time consuming fault simulation approach. ,  propose an ATE to teach neural networks (NN) to correctly classify a set of worst case input pattern with respect to the maximum instantaneous current, which can be thought of as learning a behavior of chip por consumption change due to different input patterns applied.  then further optimize this set of worst case pattern using genetic algorithms (GA). A final set of worst case pattern is expected to detect a small critical sequence of high switching current leads to worst case por supply noise. To the best of our knowledge, this is the first NN&GA implementation using industrial semiconductor ATE in practical application of semiconductor silicon analysis.
['Eric Liau', 'Doris Schmitt-Landsiedel']
I am writing a research paper on a idea Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise
[{"from": "human", "value": "I am writing a research paper on a idea Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The automatic test equipment (ATE) is an instrument used to apply a set of pre-defined test pattern to analyze the response from the semiconductor chip. Automatic test pattern generation and selection for a pre-defined pattern are popular research topics to improve the overall fault coverage (Bushnell and Agrawal, 2000) of the design. This process is normally based on a very time consuming fault simulation approach. ,  propose an ATE to teach neural networks (NN) to correctly classify a set of worst case input pattern with respect to the maximum instantaneous current, which can be thought of as learning a behavior of chip por consumption change due to different input patterns applied.  then further optimize this set of worst case pattern using genetic algorithms (GA). A final set of worst case pattern is expected to detect a small critical sequence of high switching current leads to worst case por supply noise. To the best of our knowledge, this is the first NN&GA implementation using industrial semiconductor ATE in practical application of semiconductor silicon analysis."}]