Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Spin-transfer torque RAM (STT-RAM)-based main memory can suffer from a security problem due to its non-volatility. Data encryption, which can be applied to resolve this problem, can give significant performance degradation due to the additional latency of decryption/encryption in main memory accesses.  propose an STT-RAM architecture where two regions have different retention times. A small short retentiontime region, which works as a write-through cache, keeps data unencrypted thereby avoiding the additional latency. The short retention time also makes the memory chip secure by decaying data fast in case of sudden por off. The large long retentiontime region contains the original version of main memory data in the encrypted form thereby providing full security. Experimental results, with SPEC2006 benchmarks, show that the proposed method offers 17.1%∼36.3% improvement in memory access latency. For 10 memory-intensive programs,  can obtain average 15.3% improvement in total execution cycles.
['Taemin Lee', 'Sungjoo Yoo']
I am writing a research paper on a idea A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem
[{"from": "human", "value": "I am writing a research paper on a idea A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Spin-transfer torque RAM (STT-RAM)-based main memory can suffer from a security problem due to its non-volatility. Data encryption, which can be applied to resolve this problem, can give significant performance degradation due to the additional latency of decryption/encryption in main memory accesses.  propose an STT-RAM architecture where two regions have different retention times. A small short retentiontime region, which works as a write-through cache, keeps data unencrypted thereby avoiding the additional latency. The short retention time also makes the memory chip secure by decaying data fast in case of sudden por off. The large long retentiontime region contains the original version of main memory data in the encrypted form thereby providing full security. Experimental results, with SPEC2006 benchmarks, show that the proposed method offers 17.1%\u223c36.3% improvement in memory access latency. For 10 memory-intensive programs,  can obtain average 15.3% improvement in total execution cycles."}]