Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a 2 7 −1 pseudo-random bit sequence (PRBS) generator with built-in clock is designed in 0.18-μm CMOS technology. The MOS current mode logic (CML) is used in the PRBS generator for high-speed operation. The clock circuit is realized using a three-stage ring voltage controlled oscillator (VCO). The frequency of the clock can be from 3.3 to 2.7 GHz, while the controlled voltage of the VCO is varied from 0 to 1.1 V. The periodic jitter of the clock can be also controlled, while a sinusoidal wave is added in the controlled voltage of the VCO. The maximum sinusoidal jitter amplitude of our 3-Gb/s PRBS signal can be adjusted to about 0.9-UI.
['Hong-Jhih Chen', 'Jau-Ji Jou', 'Tien-Tsorng Shih']
I am writing a research paper on a idea Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter
[{"from": "human", "value": "I am writing a research paper on a idea Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a 2 7 \u22121 pseudo-random bit sequence (PRBS) generator with built-in clock is designed in 0.18-\u03bcm CMOS technology. The MOS current mode logic (CML) is used in the PRBS generator for high-speed operation. The clock circuit is realized using a three-stage ring voltage controlled oscillator (VCO). The frequency of the clock can be from 3.3 to 2.7 GHz, while the controlled voltage of the VCO is varied from 0 to 1.1 V. The periodic jitter of the clock can be also controlled, while a sinusoidal wave is added in the controlled voltage of the VCO. The maximum sinusoidal jitter amplitude of our 3-Gb/s PRBS signal can be adjusted to about 0.9-UI."}]