Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present a design-for-testability method for asynchronous circuits based on partial scan. More specifically,  investigate how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and  show that asynchronous partial scan design can be approached as a high-level design activity. The method is demonstrated on an asynchronous error corrector for the DCC player. It has been used effectually in the production and application-mode tests of this 155 k transistor chip-set. In particular, it has led to high 99.9% stuck-at output fault coverage in short 64 msec test time at the expense of less than 3% additional area.
['Marly Roncken']
I am writing a research paper on a idea Partial scan test for asynchronous circuits illustrated on a DCC error corrector
[{"from": "human", "value": "I am writing a research paper on a idea Partial scan test for asynchronous circuits illustrated on a DCC error corrector"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present a design-for-testability method for asynchronous circuits based on partial scan. More specifically,  investigate how the partial scan principles from the synchronous test world can be adapted to asynchronous circuits, and  show that asynchronous partial scan design can be approached as a high-level design activity. The method is demonstrated on an asynchronous error corrector for the DCC player. It has been used effectually in the production and application-mode tests of this 155 k transistor chip-set. In particular, it has led to high 99.9% stuck-at output fault coverage in short 64 msec test time at the expense of less than 3% additional area."}]