Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The author presents a systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding. Multiple input changes are allod. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. This approach avoids the extra delay elements often necessary in self-clocked circuits. The method is illustrated by its application to the design of a VMEbus requester. >
['Farhad Aghadasi']
I am writing a research paper on a idea Asynchronous state machine synthesis using data driven clocks
[{"from": "human", "value": "I am writing a research paper on a idea Asynchronous state machine synthesis using data driven clocks"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The author presents a systematic approach to the design of asynchronous state machines with minimum state variables and arbitrary state encoding. Multiple input changes are allod. Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. This approach avoids the extra delay elements often necessary in self-clocked circuits. The method is illustrated by its application to the design of a VMEbus requester. >"}]