Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In this study, a low-por, high-speed, layout-efficient 8b × 8b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 µm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average por dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.
['Aloke Saha', 'Dipankar Pal', 'Mahesh Chandra']
I am writing a research paper on a idea Low-power 6-GHz wave-pipelined 8b x 8b multiplier
[{"from": "human", "value": "I am writing a research paper on a idea Low-power 6-GHz wave-pipelined 8b x 8b multiplier"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: In this study, a low-por, high-speed, layout-efficient 8b \u00d7 8b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 \u00b5m single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average por dissipation of 18.54 mW and overall latency of 3.24 ns at 25\u00b0C temperature and at 2 V supply rail."}]