Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased por and area consumption in VLSI architecture.  proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented channel matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% por and 31% area reduction compared to previous architecture without degrading the BER performance.
['Zahid Khan', 'Tughrul Arslan', 'John S. Thompson', 'Ahmet T. Erdogan']
I am writing a research paper on a idea Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system
[{"from": "human", "value": "I am writing a research paper on a idea Enhanced dual strategy based VLSI architecture for computing pseudo inverse of channel matrix in a MIMO wireless system"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased por and area consumption in VLSI architecture.  proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented channel matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% por and 31% area reduction compared to previous architecture without degrading the BER performance."}]