Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The computational cost of finite impulse response (FIR) filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of the coefficient multipliers. Previous works have focused on minimizing the number of adders employed in the coefficient multipliers. These works have not considered reducing the complexity of each adder, which is significant in SDR applications that require low por and high-speed. ,  present a coefficientpartitioning algorithm for minimizing the complexity of adders used in the multipliers. Our algorithm exploits the fact that when multiplication is realized using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. Design examples show that the proposed method offers an average full adder reduction of 20% over the common subexpression elimination (CSE) methods.
['A. P. Vinod', 'E.M.-K. Lai', 'Sabu Emmanuel']
I am writing a research paper on a idea Complexity reduction of software defined radio channelizers using filter coefficient-partitioning
[{"from": "human", "value": "I am writing a research paper on a idea Complexity reduction of software defined radio channelizers using filter coefficient-partitioning"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The computational cost of finite impulse response (FIR) filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of the coefficient multipliers. Previous works have focused on minimizing the number of adders employed in the coefficient multipliers. These works have not considered reducing the complexity of each adder, which is significant in SDR applications that require low por and high-speed. ,  present a coefficientpartitioning algorithm for minimizing the complexity of adders used in the multipliers. Our algorithm exploits the fact that when multiplication is realized using shifts and adds, the adder width can be minimized by limiting the shifts of the operands to shorter lengths. Design examples show that the proposed method offers an average full adder reduction of 20% over the common subexpression elimination (CSE) methods."}]