Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  present a low por implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also implemented. The DBF hardware implementation works at 72 MHz in a Xilinx Virtex II FPGA and it can code 30 CIF frames (352times288) per second. The por consumption of DBF hardware is analyzed and up to 13% por savings is achieved by applying clock gating and glitch reduction techniques to DBF datapath.
['Mustafa Parlak', 'Ilker Hamzaoglu']
I am writing a research paper on a idea A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm
[{"from": "human", "value": "I am writing a research paper on a idea A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  present a low por implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implemented using Verilog HDL. An AHB bus interface is designed and integrated into DBF hardware in order to communicate with ARM processor and SRAM through AHB bus. An efficient memory hierarchy and data transfer scheme is also implemented. The DBF hardware implementation works at 72 MHz in a Xilinx Virtex II FPGA and it can code 30 CIF frames (352times288) per second. The por consumption of DBF hardware is analyzed and up to 13% por savings is achieved by applying clock gating and glitch reduction techniques to DBF datapath."}]