Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a Viterbi Decoder (VD) architecture for a reprogrammable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on user request and capable to provide agility in choosing beten different standards. UMTS and GPRS standards decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, beten them guarantees a high degree of reconfigurability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, to provide a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupation of 45%, due to the efficient resource reuse.
['Lucia Bissi', 'P. Placidi', 'Giuseppe Baruffa', 'A. Scorzoni']
I am writing a research paper on a idea A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks
[{"from": "human", "value": "I am writing a research paper on a idea A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a Viterbi Decoder (VD) architecture for a reprogrammable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a Software Defined Radio (SDR) mobile transceiver, reconfigurable on user request and capable to provide agility in choosing beten different standards. UMTS and GPRS standards decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, beten them guarantees a high degree of reconfigurability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA, to provide a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupation of 45%, due to the efficient resource reuse."}]