Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  a new Boolean equation for the orthogonalization of Boolean functions respectively of Ternary-Vector-Lists of disjunctive normal form is presented. It provides the mathematical solution of orthogonalization for the first time. The new equation is based on the new method of orthogonalizing difference-building ?. In contrast to other methods the new method has a faster computation time. Another advantage is the smaller number of product terms respectively of Ternary-Vectors in the orthogonalized result in contrast to other methods. Furthermore, the new equation can be used as a part in the calculation procedure of getting suitable test patterns for combinatorial circuits for verifying feasible logical faults.
['Yavuz Can', 'Hassen Kassim', 'Georg Fischer']
I am writing a research paper on a idea New Boolean Equation for Orthogonalizing of Disjunctive Normal Form based on the Method of Orthogonalizing Difference-Building
[{"from": "human", "value": "I am writing a research paper on a idea New Boolean Equation for Orthogonalizing of Disjunctive Normal Form based on the Method of Orthogonalizing Difference-Building"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  a new Boolean equation for the orthogonalization of Boolean functions respectively of Ternary-Vector-Lists of disjunctive normal form is presented. It provides the mathematical solution of orthogonalization for the first time. The new equation is based on the new method of orthogonalizing difference-building ?. In contrast to other methods the new method has a faster computation time. Another advantage is the smaller number of product terms respectively of Ternary-Vectors in the orthogonalized result in contrast to other methods. Furthermore, the new equation can be used as a part in the calculation procedure of getting suitable test patterns for combinatorial circuits for verifying feasible logical faults."}]