Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As double patterning technology (DPT) becomes the only solution for 32-nm lithography process,  need to investigate how DPT affects the performance of a chip. ,  present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results in coupling capacitance variation,  first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. To verify our work,  use identical interconnects having different positions and different layout decompositions. Experimental result shows that the delay has a variation from 7.8% to 9.1% depending on their locations. The ll decomposed structure shows only 2.7% delay variation.
['Jae-Seok Yang', 'David Z. Pan']
I am writing a research paper on a idea Overlay aware interconnect and timing variation modeling for double patterning technology
[{"from": "human", "value": "I am writing a research paper on a idea Overlay aware interconnect and timing variation modeling for double patterning technology"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As double patterning technology (DPT) becomes the only solution for 32-nm lithography process,  need to investigate how DPT affects the performance of a chip. ,  present an efficient modeling of timing variation with overlay which is inevitable for DPT. Our work makes it possible to analyze timing with overlay variables. Since the variation of metal space caused by overlay results in coupling capacitance variation,  first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. To verify our work,  use identical interconnects having different positions and different layout decompositions. Experimental result shows that the delay has a variation from 7.8% to 9.1% depending on their locations. The ll decomposed structure shows only 2.7% delay variation."}]