Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Binary symmetric channels (BSC) like the interchip buses and the intrachip buses are gaining a lot of attention due to their widespread use with multimedia storage devices and on system-on-chips (SoC) respectively. While the audio and video traffic beten systems has increased manyfold over the years, SoC is a reality due to the advances in technology as predicted by Moore's law. These buses are prone to error arising from crosstalk beten wires, propagation delay etc. Due to low latency requirements, re-transmission is undesirable in the event of an error and forward error correction (FEC) becomes more and more desirable is a necessity.  focuses on the low density parity check (LDPC) codes as a means of FEC. Several quantization schemes to reduce the size of the decoder, and the associated code performance, are presented herein. The reduction in size due to the quantization schemes is made apparent via implementation on a Xilinx Virtex FPGA.
['Rohit Singhal', 'Gwan Choi', 'R. Mahapatra']
I am writing a research paper on a idea Quantized LDPC decoder design for binary symmetric channels
[{"from": "human", "value": "I am writing a research paper on a idea Quantized LDPC decoder design for binary symmetric channels"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Binary symmetric channels (BSC) like the interchip buses and the intrachip buses are gaining a lot of attention due to their widespread use with multimedia storage devices and on system-on-chips (SoC) respectively. While the audio and video traffic beten systems has increased manyfold over the years, SoC is a reality due to the advances in technology as predicted by Moore's law. These buses are prone to error arising from crosstalk beten wires, propagation delay etc. Due to low latency requirements, re-transmission is undesirable in the event of an error and forward error correction (FEC) becomes more and more desirable is a necessity.  focuses on the low density parity check (LDPC) codes as a means of FEC. Several quantization schemes to reduce the size of the decoder, and the associated code performance, are presented herein. The reduction in size due to the quantization schemes is made apparent via implementation on a Xilinx Virtex FPGA."}]