Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: At the integration scale of System-On-Chips (SOCs), the conflicts beten communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. ,  explore retiming to pipeline long interconnect wires in SOC designs., Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate level netlist and is formulated as a wire retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results shod the benefits and effectiveness of our approach.
['Chuan Lin', 'Hai Zhou']
I am writing a research paper on a idea Retiming for Wire Pipelining in System-On-Chip
[{"from": "human", "value": "I am writing a research paper on a idea Retiming for Wire Pipelining in System-On-Chip"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: At the integration scale of System-On-Chips (SOCs), the conflicts beten communication and computation will become prominent even on a chip. A big fraction of system time will shift from computation to communication. In synchronous systems, a large amount of communication time is spent on multiple-clock period wires. ,  explore retiming to pipeline long interconnect wires in SOC designs., Behaviorally, it means that both computation and communication are rescheduled for parallelism. The retiming is applied to a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be able to be inserted on some wire segments. This problem is different from that on a gate level netlist and is formulated as a wire retiming problem. Theoretical treatment and a polynomial time algorithm are presented in the paper. Experimental results shod the benefits and effectiveness of our approach."}]