Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This work presents a novel technique for a high-speed implementation of the newly selected cryptographic hash function, Secure Hash Algorithm-3 (SHA-3) on Xilinx’s Virtex-5 and Virtex-6 Field Programmable Gate Arrays (FPGAs). The proposed technique consists of a two-phase implementation approach. In the first phase, all steps of the SHA-3 core are logically combined, which helps to eliminate the intermediate states of core function, these states utilize more area and also slow the execution. The second phase deals with the hardware implementation of the first phase equations using Xilinx Look-Up-Table (LUT) primitives. This two phase implementation technique results in a throughput of 19.241Gbps on a Virtex-6 FPGA; this is the highest reported throughput to date for an FPGA implementation of SHA-3. This high throughput makes this technique ideally suited for the provision of Bump In The Wire (BITW) security for Internet of Things (IoT) applications.
['Muzaffar Rao', 'Thomas Newe', 'Ian Grout', 'Avijit Mathur']
I am writing a research paper on a idea High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs
[{"from": "human", "value": "I am writing a research paper on a idea High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This work presents a novel technique for a high-speed implementation of the newly selected cryptographic hash function, Secure Hash Algorithm-3 (SHA-3) on Xilinx\u2019s Virtex-5 and Virtex-6 Field Programmable Gate Arrays (FPGAs). The proposed technique consists of a two-phase implementation approach. In the first phase, all steps of the SHA-3 core are logically combined, which helps to eliminate the intermediate states of core function, these states utilize more area and also slow the execution. The second phase deals with the hardware implementation of the first phase equations using Xilinx Look-Up-Table (LUT) primitives. This two phase implementation technique results in a throughput of 19.241Gbps on a Virtex-6 FPGA; this is the highest reported throughput to date for an FPGA implementation of SHA-3. This high throughput makes this technique ideally suited for the provision of Bump In The Wire (BITW) security for Internet of Things (IoT) applications."}]