Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a new method for random jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test patterns that can sensitize its critical paths, the proposed method constructs a cumulative distribution function (CDF) whose standard deviation represents the root mean square (RMS) value of the random jitter of the clock signals used in the microprocessor. By leveraging tester period resolution with a frequency multiplying phase-locked loop (PLL) in the SoC, the shmoo plot with a fine period step size can detect the jitter component in the clock signal, which reflects the actual jitter that most critical paths undergo. The proposed idea was verified with circuit-level simulations, and was validated by silicon measurements using one of the latest SoC products.
['Jae Wook Lee', 'Ji Hwan (Paul) Chun', 'Jacob A. Abraham']
I am writing a research paper on a idea Indirect method for random jitter measurement on SoCs using critical path characterization
[{"from": "human", "value": "I am writing a research paper on a idea Indirect method for random jitter measurement on SoCs using critical path characterization"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a new method for random jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test patterns that can sensitize its critical paths, the proposed method constructs a cumulative distribution function (CDF) whose standard deviation represents the root mean square (RMS) value of the random jitter of the clock signals used in the microprocessor. By leveraging tester period resolution with a frequency multiplying phase-locked loop (PLL) in the SoC, the shmoo plot with a fine period step size can detect the jitter component in the clock signal, which reflects the actual jitter that most critical paths undergo. The proposed idea was verified with circuit-level simulations, and was validated by silicon measurements using one of the latest SoC products."}]