Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As DDR DRAM is running at higher and higher speed, the shrinking data windows makes the timing closure in setup and hold at either DRAM or host chip more and more difficult. When calculating timing margins for DDR2/3 system, it helps to break up the uncertainty contributions into transmitter, interconnect and receiver categories. Furthermore, based on the timing margins, the signal integrity and por integrity analysis is the key point to reach success.  will also present our front-end experience of high-speed and low-por 28nm CPU core hardening, from top RTL integration to synthesis and DFT. This core includes dual-core ARM Cortex™-A9 CPU, Level 2 Cache Controller and Program Trace Macrocell.
['Kevin Ho', 'Tsung-Yi Chou', 'Po-Kai Chen', 'David J. Liou']
I am writing a research paper on a idea High speed DDR2/3 PHY and dual CPU core design for 28nm SoC
[{"from": "human", "value": "I am writing a research paper on a idea High speed DDR2/3 PHY and dual CPU core design for 28nm SoC"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: As DDR DRAM is running at higher and higher speed, the shrinking data windows makes the timing closure in setup and hold at either DRAM or host chip more and more difficult. When calculating timing margins for DDR2/3 system, it helps to break up the uncertainty contributions into transmitter, interconnect and receiver categories. Furthermore, based on the timing margins, the signal integrity and por integrity analysis is the key point to reach success.  will also present our front-end experience of high-speed and low-por 28nm CPU core hardening, from top RTL integration to synthesis and DFT. This core includes dual-core ARM Cortex\u2122-A9 CPU, Level 2 Cache Controller and Program Trace Macrocell."}]