Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock-gating has been introduced as the primary means of dynamic por management in recent high-end commercial microprocessors. The temperature drop resulting from active por reduction can result in additional leakage por savings in future processors.   first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4/spl trade/ or POWER5/spl trade/ class).  then look beyond classical clock-gating:  examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular,  examine the por reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating. Based on our experiences with current designs,  try to bound the practical limits of clock gating efficiency in future microprocessors.
['Hans M. Jacobson', 'Pradip Bose', 'Zhigang Hu', 'Alper Buyuktosunoglu', 'Victor Zyuban', 'Richard J. Eickemeyer', 'Lee Evan Eisen', 'John Barry Griswell', 'D. Logan', 'Balaram Sinharoy', 'Joel M. Tendler']
I am writing a research paper on a idea Stretching the limits of clock-gating efficiency in server-class processors
[{"from": "human", "value": "I am writing a research paper on a idea Stretching the limits of clock-gating efficiency in server-class processors"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Clock-gating has been introduced as the primary means of dynamic por management in recent high-end commercial microprocessors. The temperature drop resulting from active por reduction can result in additional leakage por savings in future processors.   first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4/spl trade/ or POWER5/spl trade/ class).  then look beyond classical clock-gating:  examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular,  examine the por reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating. Based on our experiences with current designs,  try to bound the practical limits of clock gating efficiency in future microprocessors."}]