Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a por of two. The first part of this work presents a linear systolic array that requires log/sub 2/ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed,  further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log/sub 2/ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lor throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742/spl times/5222 /spl mu/m/sup 2/, and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems.
['Ching-Hsien Chang', 'Chin-Liang Wang', 'Yu-Tai Chang']
I am writing a research paper on a idea Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse
[{"from": "human", "value": "I am writing a research paper on a idea Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: ,  propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a por of two. The first part of this work presents a linear systolic array that requires log/sub 2/ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed,  further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log/sub 2/ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lor throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742/spl times/5222 /spl mu/m/sup 2/, and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 /spl mu/m CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems."}]