Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the   $X/Y$   Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences beten the   $X$   and   $Y$   phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.
['Ping Lu', 'Ying Wu', 'Pietro Andreani']
I am writing a research paper on a idea A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration
[{"from": "human", "value": "I am writing a research paper on a idea A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the   $X/Y$   Vernier branches. The already small Vernier quantization noise (\u223c10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences beten the   $X$   and   $Y$   phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC."}]