Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The integrated systems today require flexibility, performance and reconfigurability. The trends in this domain lead to integrate on a single chip different processing cores, communication units and reconfigurable logic. Therefore the Systems on Chip (SoC) can embed programmable logic. In order to challenge the reconfigurability paradigm for special issues such as communication, synchronization or security, the asynchronous logic is a very promising approach. Nevertheless, the standard programmable logic blocks are not ll-suited to map asynchronous circuits. The goal of this study is to define a more adequate programmable structure to implement asynchronous designs on SoCs embedding a reconfigurable part. This work is part of a larger project which includes the design of an embedded Programmable Logic Device (e-PLD) dedicated to the implementation of clockless circuits. The more robust and reliable asynchronous circuits are quasi-delay insensitive. These circuits are mainly constructed with Muller gates. The paper presents a new Look-Up Table (LUT) architecture ll-adapted to the Muller gate implementation. This new LUT allows the combination of a single memory-point with combinational logic. This programmable memory is realized thanks to an optional feedback structure. This architecture has been evaluated in CMOS, Pass-Transistor Logic and 3-state logic which is a non-conventional way to design LUTs. The simulations report detailed comparisons beten the different logic styles and demonstrate for equivalent por consumption a higher speed for 3-state logic.
['Laurent Fesquet', 'Bertrand Folco', 'Mathieu Steiner', 'Marc Renaudin']
I am writing a research paper on a idea State-holding in Look-Up Tables: application to asynchronous logic
[{"from": "human", "value": "I am writing a research paper on a idea State-holding in Look-Up Tables: application to asynchronous logic"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: The integrated systems today require flexibility, performance and reconfigurability. The trends in this domain lead to integrate on a single chip different processing cores, communication units and reconfigurable logic. Therefore the Systems on Chip (SoC) can embed programmable logic. In order to challenge the reconfigurability paradigm for special issues such as communication, synchronization or security, the asynchronous logic is a very promising approach. Nevertheless, the standard programmable logic blocks are not ll-suited to map asynchronous circuits. The goal of this study is to define a more adequate programmable structure to implement asynchronous designs on SoCs embedding a reconfigurable part. This work is part of a larger project which includes the design of an embedded Programmable Logic Device (e-PLD) dedicated to the implementation of clockless circuits. The more robust and reliable asynchronous circuits are quasi-delay insensitive. These circuits are mainly constructed with Muller gates. The paper presents a new Look-Up Table (LUT) architecture ll-adapted to the Muller gate implementation. This new LUT allows the combination of a single memory-point with combinational logic. This programmable memory is realized thanks to an optional feedback structure. This architecture has been evaluated in CMOS, Pass-Transistor Logic and 3-state logic which is a non-conventional way to design LUTs. The simulations report detailed comparisons beten the different logic styles and demonstrate for equivalent por consumption a higher speed for 3-state logic."}]