Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  have reported previously (Pong-Fei Lu et al., 2004) a low-swing latch (LSL) with superior performance-por tradeoff compared to the conventional pass-gate master-slave latch. , hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system por in high-frequency microprocessors.  have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle beten two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system por saving can be achieved in pulsed mode compared to non-pulsed mode. Por contribution from individual components is also presented
['Pong-Fei Lu', 'Nianzheng Cao', 'Leon J. Sigal', 'P. J. M. Woltgens', 'R. P. Robertazzi', 'David F. Heidel']
I am writing a research paper on a idea A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors
[{"from": "human", "value": "I am writing a research paper on a idea A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  have reported previously (Pong-Fei Lu et al., 2004) a low-swing latch (LSL) with superior performance-por tradeoff compared to the conventional pass-gate master-slave latch. , hardware results are presented for the proposed LSL with pulsed clock waveforms. The motivation is to combine low-voltage swing with pulsed signals to further reduce overall system por in high-frequency microprocessors.  have designed a 65-bit accumulator loop experiment to mimic a microprocessor pipeline stage. The local clock buffer design features a mode switch to toggle beten two-phase (c1/c2) master-slave clocking and one-phase pulsed (c2 only) clocking. Our data show that 15-25% system por saving can be achieved in pulsed mode compared to non-pulsed mode. Por contribution from individual components is also presented"}]