Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a physics based impact ionization model for silicon MOSFETs is proposed. The proposed impact ionization model specially addresses the physics for the low Vds or sub band gap impact ionization (thermally assisted) along with the conventional (channel field assisted) high Vds impact ionization. The proposed model is implemented in industry standard BSIMSOI model and verified by comparison with experimental data of partially depleted silicon-on-insulator MOSFET. Model shows excellent agreement with the experimental data for low as ll as high Vds impact ionization. The proposed unified impact ionization model shows improved convergence problem in standard test circuit simulation.
['Chandan Yadav', 'Anupam Dutta', 'Saurabh Sirohi', 'Tamilmani Ethirajan', 'Yogesh Singh Chauhan']
I am writing a research paper on a idea Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence
[{"from": "human", "value": "I am writing a research paper on a idea Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: , a physics based impact ionization model for silicon MOSFETs is proposed. The proposed impact ionization model specially addresses the physics for the low Vds or sub band gap impact ionization (thermally assisted) along with the conventional (channel field assisted) high Vds impact ionization. The proposed model is implemented in industry standard BSIMSOI model and verified by comparison with experimental data of partially depleted silicon-on-insulator MOSFET. Model shows excellent agreement with the experimental data for low as ll as high Vds impact ionization. The proposed unified impact ionization model shows improved convergence problem in standard test circuit simulation."}]