Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are  hitting capacity and performance  bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper,  address a solution, involving the introduction of test models in a traditional DFT synthesis flow, that  term  Hierarchical DFT Synthesis  ( HDS ).  discuss the use of Core Test Language (CTL) based test models combined with physical and timing models to provide a complete flow for  chip-level DFT . In doing so  address some challenges the new flow presents such as Design Rule Checking (DRC), DFT architecting and optimization.  describe methods to overcome these challenges thereby presenting a new methodology to handle  complex next generation designs .
['Sanjay Ramnath', 'Frederic Neuveux', 'Mokhtar Hirech', 'Felix Ng']
I am writing a research paper on a idea Test-model based hierarchical DFT synthesis
[{"from": "human", "value": "I am writing a research paper on a idea Test-model based hierarchical DFT synthesis"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are  hitting capacity and performance  bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper,  address a solution, involving the introduction of test models in a traditional DFT synthesis flow, that  term  Hierarchical DFT Synthesis  ( HDS ).  discuss the use of Core Test Language (CTL) based test models combined with physical and timing models to provide a complete flow for  chip-level DFT . In doing so  address some challenges the new flow presents such as Design Rule Checking (DRC), DFT architecting and optimization.  describe methods to overcome these challenges thereby presenting a new methodology to handle  complex next generation designs ."}]