Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Built-In Self Test (BIST) consists of integrating totally or partially a Test Pattern Generator (TPG) and/or a Response Analyzer (RA) in the same chip with the Circuit Under Test (CUT). Generally, an efficient analog test requires the monitoring of several performances by applying different frequencies as test stimuli. For BIST application, the integration of a frequency TPG and RA can not be economically viable for most applications because of their corresponding area overhead and complexity. BIST techniques based on frequency analysis are very expensive for the silicon area. On the other hand, BIST solutions based on a DC test remain poor concerning the fault coverage. This is true if no Design For Testability (DFT) elements are used in conjunction with a DC BIST to eliminate this problem. Exactly, our approach consists of using some DFT means so as all defects of SC circuits become detectable in the DC domain. Then a DC stimulus as an existing voltage source Vdd, Gnd and Vss corresponds to a simple TPG while the RA is a small window comparator. Finally, the addition of these DFT elements allows to decrease considerably the DC BIST hardware and corresponds in fact to a tradeoff beten BIST complexity and DFT resources. With this mixed BIST/DFT technique  obtain a comparable fault coverage than frequency based approaches and this for a lor hardware cost.
['Hassan Ihs', 'Christian Dufaza']
I am writing a research paper on a idea Test synthesis for DC test of switched-capacitors circuits
[{"from": "human", "value": "I am writing a research paper on a idea Test synthesis for DC test of switched-capacitors circuits"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Built-In Self Test (BIST) consists of integrating totally or partially a Test Pattern Generator (TPG) and/or a Response Analyzer (RA) in the same chip with the Circuit Under Test (CUT). Generally, an efficient analog test requires the monitoring of several performances by applying different frequencies as test stimuli. For BIST application, the integration of a frequency TPG and RA can not be economically viable for most applications because of their corresponding area overhead and complexity. BIST techniques based on frequency analysis are very expensive for the silicon area. On the other hand, BIST solutions based on a DC test remain poor concerning the fault coverage. This is true if no Design For Testability (DFT) elements are used in conjunction with a DC BIST to eliminate this problem. Exactly, our approach consists of using some DFT means so as all defects of SC circuits become detectable in the DC domain. Then a DC stimulus as an existing voltage source Vdd, Gnd and Vss corresponds to a simple TPG while the RA is a small window comparator. Finally, the addition of these DFT elements allows to decrease considerably the DC BIST hardware and corresponds in fact to a tradeoff beten BIST complexity and DFT resources. With this mixed BIST/DFT technique  obtain a comparable fault coverage than frequency based approaches and this for a lor hardware cost."}]