Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as ll as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mum 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm 2  silicon area, and the average core por consumption is 68.1 mW.
['Hsie-Chia Chang', 'Chien-Ching Lin', 'Fu-Ke Chang', 'Chen-Yi Lee']
I am writing a research paper on a idea A Universal VLSI Architecture for Reed–Solomon Error-and-Erasure Decoders
[{"from": "human", "value": "I am writing a research paper on a idea A Universal VLSI Architecture for Reed\u2013Solomon Error-and-Erasure Decoders"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as ll as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mum 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm 2  silicon area, and the average core por consumption is 68.1 mW."}]