Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Instruction-driven clock scheduling is a mechanism that minimizes clock por in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallor pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic por. Experimentally measured results from a 130 nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic por for shallor pipelines. While higher glitch por can severely diminish the por savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover por savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net por savings of 15% compared to an aggressively clock-gated design.
['Gu-Yeon Wei', 'David M. Brooks', 'Ali Durlov Khan', 'Xiaoyao Liang']
I am writing a research paper on a idea Instruction-driven clock scheduling with glitch mitigation
[{"from": "human", "value": "I am writing a research paper on a idea Instruction-driven clock scheduling with glitch mitigation"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely: Instruction-driven clock scheduling is a mechanism that minimizes clock por in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallor pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic por. Experimentally measured results from a 130 nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic por for shallor pipelines. While higher glitch por can severely diminish the por savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover por savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net por savings of 15% compared to an aggressively clock-gated design."}]