Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for m-out-of-n code, where m/spl ges/3, 2m+1/spl les/n/spl les/4m. The checker is composed of four special adders which sum the 1s in the primary inputs added by appropriate constants, two ripple carry adders which sum the outputs of the biased-adders, and a t-variable two-rail code checker tree which compares the outputs of the two ripple carry adders, where k=[log/sub 2/(n-m)+1]. All the modules are composed of 2-input gates and inverters. Compared with previous nonmodular methods, our TSC checker has a lor hardware and time complexity. Our method reduces the hardware complexity and circuit delay of the checker from O(n/sup 2/) to O(n) and from O(n) to O(log/sub 2/n), respectively. Compared with recent modular methods, our TSC checker has about the same hardware and time complexity, but is applicable to a much broader range of n. In summary, our method is superior to existing methods for the considered range of n. In addition, our TSC checker can easily be tested (the test set size of our TSC checker is relatively small) and implemented in VLSI for its modular structure.
['Wen-Feng Chang', 'Cheng-Wen Wu']
I am writing a research paper on a idea Low-cost modular totally self-checking checker design for m-out-of-n code
[{"from": "human", "value": "I am writing a research paper on a idea Low-cost modular totally self-checking checker design for m-out-of-n code"}, {"from": "gpt", "value": "Thats a unique idea.You should consider the following idea to enhance your idea so that it would impact uniquely:  present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for m-out-of-n code, where m/spl ges/3, 2m+1/spl les/n/spl les/4m. The checker is composed of four special adders which sum the 1s in the primary inputs added by appropriate constants, two ripple carry adders which sum the outputs of the biased-adders, and a t-variable two-rail code checker tree which compares the outputs of the two ripple carry adders, where k=[log/sub 2/(n-m)+1]. All the modules are composed of 2-input gates and inverters. Compared with previous nonmodular methods, our TSC checker has a lor hardware and time complexity. Our method reduces the hardware complexity and circuit delay of the checker from O(n/sup 2/) to O(n) and from O(n) to O(log/sub 2/n), respectively. Compared with recent modular methods, our TSC checker has about the same hardware and time complexity, but is applicable to a much broader range of n. In summary, our method is superior to existing methods for the considered range of n. In addition, our TSC checker can easily be tested (the test set size of our TSC checker is relatively small) and implemented in VLSI for its modular structure."}]