# This is testbench creator version 1.0

import sys

print("----------------------------------------------------------------------------------\n"
			+ "-- Company: \n"
			+ "-- Engineer: \n"
			+ "-- \n"
			+ "-- Create Date: \n"
			+ "-- Design Name: \n"
			+ "-- Module Name: \n"
			+ "-- Project Name: \n"
			+ "-- Target Devices: \n"
			+ "-- Tool Versions: \n"
			+ "-- Description: \n"
			+ "-- \n"
			+ "-- Dependencies: \n"
			+ "-- \n"
			+ "-- Revision: \n"
			+ "-- Revision 0.01 - File Created\n"
			+ "-- Additional Comments: \n"
			+ "-- \n"
			+ "----------------------------------------------------------------------------------\n\n")


entity = "??"

while True:
    entity = sys.stdin.readline()
    
    try:
        if entity.split()[0] == "entity":
            break
    except:
        pass

class signal:
    def __init__(self) -> None:
        pass

entity = entity.split()[1]

print('library ieee;\nuse ieee.std_logic_1164.all;\n\nentity ' + entity + '_testbench is\nend ' + entity + '_testbench;\n')

print('architecture Behavioral of ' + entity + '_testbench is\n\ncomponent ' + entity + ' is\n\tport (')

sys.stdin.readline()

signals = []

while True:
    sig = sys.stdin.readline()

    

    if sig.strip() == ");":
        break

    print(sig, end = "")

print('\t);\nend component;\n')
