A compact aVLSI conductance-based silicon neuron
Runchun Wang, Chetan Singh Thakur, Tara Julia Hamilton, Jonathan Tapson, André van Schaik
The MARCS Institute, University of Western Sydney, Sydney, NSW, Australia
mark.wang@uws.edu.au
Abstract—We present an analogue Very Large Scale
Integration (aVLSI) implementation that uses first-order lowpass filters to implement a conductance-based silicon neuron for
high-speed neuromorphic systems. The aVLSI neuron consists
of a soma (cell body) and a single synapse, which is capable of
linearly summing both the excitatory and inhibitory postsynaptic potentials (EPSP and IPSP) generated by the spikes
arriving from different sources. Rather than biasing the silicon
neuron with different parameters for different spiking patterns,
as is typically done, we provide digital control signals, generated
by an FPGA, to the silicon neuron to obtain different spiking
behaviours. The proposed neuron is only ~26.5 µm2 in the IBM
130nm process and thus can be integrated at very high density.
Circuit simulations show that this neuron can emulate different
spiking behaviours observed in biological neurons.

I. BACKGROUND
Conductance-based neuron models [1] are easier to
implement in hardware than the full Hodgkin-Huxley model
[2], while still being rich in behaviours observed in biological
neurons. The log-domain LPF neuron [3] and the Diff-Pair
Integrator neuron [3] represent good examples of
conductance-based silicon neurons. These neurons operate in
the log-domain and use only a few transistors and are capable
of reproducing a variety of spiking behaviours, such as regular
spiking, spiking frequency adaptation and bursting.
In our previous work [4], we have presented an aVLSI
conductance-based silicon neuron that occupies ~170 µm2 and
is rich in dynamic behaviours that are similar to its biological
counterpart. Here we present an improved aVLSI
conductance-based silicon neuron, which occupies only ~26.5
µm2 without sacrificing any performance. A test chip
containing 0.5 million of these neurons has been fabricated
using the IBM 130nm technology. In this paper, we present
the structure of the proposed silicon neuron along with circuit
simulation results. The outline for this paper is as follows. The
CMOS implementation is presented in Section II. In Section
III we present the simulation results and we conclude in
Section IV.
II. CMOS IMPLEMENTATION
A. Motivation
Most of the implementations of existing conductancebased silicon neurons have to be tuned with specified
parameters, some of which are very sensitive to the error, to

model the dynamics of the neuron’s membrane voltage for
different types of biological neurons. In this way, these silicon
neurons will reproduce different firing patterns. This approach
is time consuming and inefficient; it is only an option for a
system with a small number of neurons, e.g., less than one
hundred neurons. Due to process variation and device
mismatch, especially for deep sub-micron technologies, it is
impractical to tune all the neurons in large-scale spiking neural
networks with the individual parameters needed to obtain the
required behaviour. An ideal silicon neuron should be able to
work with one and only one set of fixed but configurable
parameters for instantiations on the Integrated Circuit (IC).
Programmable devices such as FPGAs may be employed
for the generation of control signals that could be used by the
neurons for achieving different firing patterns. Moreover, this
scheme significantly reduces the size of the silicon neuron
since it removes the on-chip feedback generating circuits,
which usually need large capacitors to operate on biological
time scales with typical time constants in the order of tens to
hundreds of milliseconds. Our proposed scheme does,
however, require a controller implemented on an FPGA. This
does not increase the cost of the system significantly as, in
state-of-the-art neuromorphic systems, an FPGA is needed
anyway to carry out other tasks such as routing the spikes
between analogue computation modules and other
miscellaneous tasks.
B. Design choices
In deep sub-micron technologies, generally, there are two
types of devices: thin- and thick-oxide transistors. The latter
have larger feature sizes, can use a higher power supply, have
a lower switching speed, and are less sensitive to process
variations than the former and are therefore usually used in
aVLSI circuits. We used these in our previous
implementation [4] and we achieved a density of 5882
neurons/mm2. To further increase the density, we chose to use
the thin-oxide transistors in the work reported here. The
smaller feature size leads to a higher density, but these
transistors are unsuitable to subthreshold circuits [5], which
are most sensitive to process variation whether they are used
in voltage or current mode [6]. Therefore, we use voltage
mode low-pass filters in strong-inversion [5] to implement
the neuron. Hence the proposed implementation is more
robust than the log-domain implementations. Furthermore,

Figure 1. Schematic of the conductance-based neuron.
this implementation uses fewer transistors than our previous
work [4], which increases the density of neurons we can
achieve. By leveraging the thin-oxide low-power devices of
the IBM 130nm technology, a ~100 times leakage current
reduction was achieved compared to the design with regular
thin-oxide devices.
The schematic of the proposed silicon neuron is shown in
Figure 1. The circuit comprises a conductance-based synapse
(blue, M1-M7 and a MOS capacitor Csyn), a conductancebased soma (green, M8-M12 and a MOS capacitor Cmem) and
an AER interface circuit (red, M13-M16). The proposed
silicon neuron is placed in a neuron array and therefore
requires selecting signals (Scan_en and Scan_en_n). For
simplicity, we will assume the neuron in Figure 1 is always
being selected and the transistors controlled by these signals
are all ON in the following descriptions.
C. Synapse
The conductance-based synapse is implemented using a
truly linear low-pass filter circuit, which can be shared to
linearly sum the post-synaptic potentials (PSP) generated by
the spikes arriving from different sources. Hence, only one
such synaptic circuit is needed per neuron, which can save a
significant amount of area on a chip. Synaptic plasticity, e.g.
Spike Timing Dependent Plasticity (STDP) [7], could be
carried out as in [8], which modifies the weights of the
incoming spikes externally. Instead of using a separate lowpass filter for excitatory and inhibitory inputs, we proposed a
conductance-based synapse that consists of one and only one
synapse capacitor Csyn, a charge circuit (M1-M3), a discharge
circuit (M4-M6) and M7 that models the neuron’s
conductance leak. This makes the circuit even more compact,
but the drawback is that the time constant of the EPSP and
IPSP will have to be identical.
The synapse behaves as an RC-filter. The voltage at node
Vsyn will be increased/decreased by the current Iexc and Iinh that
are generated by incoming excitatory and inhibitory spikes.
The durations of excitatory and inhibitory spikes are

modulated according to their weights with a gain set by the
gate bias voltages Vpu_lim and Vpd_lim respectively. The current
In (~2 pA, depending on Vsyn due to channel length modulation
[5]) is a leakage current set by the gate bias voltage Vn and
Ishift is a current from the soma circuit, which will be
presented in the next section. Kirchhoff’s current law on the
Vsyn node yields:
(1)

=

After being increased or decreased by incoming spikes,
Vsyn will be pulled up/down to a steady state such that In = Ishift.
This is a self-balanced procedure since the value of In will
increase when Vsyn increases and vice versa.
D. Soma
The soma is implemented using another low-pass filter to
model the neuron’s leak conductance and the neuron’s
membrane capacitance (represented by Cmem). To feed the
post-synaptic potential Vsyn to the soma circuit, we connect
these two nodes via a level shifter circuit (a diode-connected
transistor M8) such that the membrane voltage follows the
first-order dynamics of the synapse. The current Ip (~2 pA,
depending on Vmem due to channel length modulation) is a
leakage current set by the gate bias voltage Vp. Ignoring the
effect of the current from M10, Kirchhoff’s current law on
the Vmem node yields:
=

(2)

When Vsyn is charged by incoming excitatory spikes, M8
will be OFF (Ishift = 0) and Ip will begin to pull Vmem up until Ip
= Ishift again (M8 will be ON again since meanwhile Vsyn is
being pulled down by In). After that, Vmem will be pulled down
by Ishift - Ip, while Vsyn is being pulled down by In - Ishift, to the
steady state such that Ip = Ishift = In. When Vsyn is discharged
by incoming inhibitory spikes, Vmem will be pulled down by
Ishift very quickly (since Vsyn will be much smaller than Vmem
and hence Ishift >> Ip) until Vmem is low enough such that Ishift is
equal to Ip (M8 is almost OFF). After that, Vmem will be pulled

up by Ip - Ishift, meanwhile Vsyn is being pulled up by Ishift - In,
to the steady state such that Ip = Ishift = In.
The AER interface below will create spikes when Vmem
crosses a threshold. To model resetting oof the membrane
potential after a spike, the circuit of M110-M12 has been
added. Vmem will be pulled down by an incooming RST signal,
the duration of which is modulated accordiing to its strength
with a gain set by the gate bias voltage Vpd_limm.

E. AER interface
In our previous work [9]–[11], we hhave presented a
synchronous AER protocol optimised for a ttime-multiplexing
architecture, which uses a collision-free serial scanning
scheme with one active signal and ann address. This
synchronous scheme eliminates the overheead of an arbiter,
which consumes a significant amount of siilicon area in the
standard AER protocol [12]. Hence we will apply this
synchronous AER protocol to the proposeed neuron with a
scanning period of 1 ms, given that a milliseecond resolution is
generally acceptable for neural simulations.
when a neuron is
The AER interface works as follows: w
selected, the voltage at node Vmem in the som
ma circuit of that
neuron will pull the output signal of this neurron, Iactive, either up
to Vdd (inactive) or down to ground (activee) via an inverter
(M15-M16, for increasing driving capabiliity) and switches
(M13-M14). M13 is added to limit the poower consumption
when the neuron is not selected. When thhis neuron is not
selected (M14 is OFF), the output node off this neuron will
have high impedance, which releases the AER bus to be
driven by other neurons in the neuron array. Once the off-chip
FPGA reads the output signal as active, it w
will send feedback
signals, e.g., the RST signal, back to the neuuron depending on
what firing pattern this neuron is configured ffor.
F. Layout
All transistors are 280 nm wide and 2800 nm long (M1-2,
M5-6, M11-12 are 120 nm long). The inveerter and switches
(M13-M16) use transistors that are 720 nm wide and 120 nm
long. The MOS capacitor values are: Csyn = 11.4 µm x 1.42 µm
(~22 fF), Cmem = 1.4 µm x 1.22 µm (~
~18 fF). For the
maximum utilisation of silicon area, a neuroon should share as
many resources with its neighbouring ones aas possible. Based
on this principle, all the pMOS and nMOS transistors of one
neuron are located in the left and right sidde respectively. In
this way the neurons can share their bbulk connections
(especially the ones of the MOS capacitors)) with each other.

The effective size of one neuron
n (see the white dashed
rectangle in Figure 2) is ~26.5 µm2 and the density that we
achieved is 37,735 neurons/mm2.
E
III. SIMULATION RESULTS

We have run post-layout simu
ulations for the proposed
silicon neuron. In the simulations, the leak current Ip and In are
set by biasing the gate voltage Vp = 1.172 V and Vn = 166.2
mV respectively. Vdd was 1.2 V. The amplitude of the
inhibitory and excitatory spikes aree both set to 550 nA by
biasing the gate voltages Vpd_lim = 645
6 mV and Vpu_lim = 628
mV respectively. These settings willl remain the same for all
spiking patterns shown below.
Figure 3 shows the simulation results. In Figure 3a the
circuit behaves as a simple leaky--integrate-and-fire neuron
without adaptation. Note that thee glitches, which appear
periodically (every 1 ms) on Vsyn (th
he green curve) and Vmem
(the magenta curve), are caused by
y digital noise introduced
through capacitive coupling by thee serial scanning signals
(scan_en and scan_en_n, the duration
ns of which were set to 32
ns). The EPSPs generated by four co
onsecutive excitatory input
spikes (the red curve, each with a duration
d
of 24 ns and the
inter-spike interval is set to 1 ms) are just enough to cause the
neuron to spike (the blue curve, an inverted version of Iactive).
This spike will be scanned by an FPG
GA, and in simulation, we
used a HDL model for this. The FPG
GA will then send the RST
signal, the duration of which was sett to 24 ns, to the neuron to
reset Vmem and to implement the refraactory period.
Figure 3b shows bursting behavio
our. Here, the durations of
the four excitatory spikes were set to
t 32 ns and the EPSP is
strong enough to cause tonic bursting
g. Vmem is only reset by the
FPGA once five consecutive spik
kes have been received.
Figure 3c shows spike frequenccy adaptation. Here, an
excitatory spike is sent to the neuron
n
every 1 ms for
continuous stimulation. When an output spike is created, Vmem
is reset by sending RST to the neurron, which initially lasts 3
ns. Spike frequency adaptation is obtained
o
by incrementing
the duration of the RST pulse by 3 nss each time until it reaches
a maximum duration of 32 ns. Figu
ure 3d shows the effect of
inhibitory spikes (at a finer time ressolution than the previous
results). In this case, the first and thee third spikes received are
excitatory, whereas the second and fourth spikes are
inhibitory, all with equal weight (i.e., a duration of 24 ns). The
synapse is excited first, then inhibited, excited again and
finally inhibited. The spike threshold
d is never reached.
IV. CONCLUSIO
ONS

Figure 2. Layout of one conductance-basedd neuron.

We have presented an aVLS
SI implementation of a
conductance-based silicon neuron baased on a first-order lowpass filter core. This neuron achiieves an extremely high
density, measuring only 26.5 µm2 in a 130 nm technology.
Besides the high density, the propo
osed neuron can be easily
reconfigured via a digital controller on an FPGA for different
firing patterns observed in biologicaal neurons, allowing great
flexibility in spiking behaviour, even after fabrication.
Another major advantage of the prop
posed neuron over existing
solutions [3] is that it uses only one fixed set of biases, which

will makes it practical for being used in mixed-signal
platforms for reconfigurable large-scale neuraal networks.

V. ACKNOWLEDGMENT
This work has been supported by the Auustralian Research
Council Grant DP140103001. This work waas inspired by the
Capo Caccia Cognitive Neuromorphic Enginneering Workshop
2014 and Telluride Neuromorphic workshop 2014.
VI. REFERENCES
[1] R. Jolivet, T. J. Lewis, and W. Gerstner, “Generaliized integrate-and-fire
models of neuronal activity approximate spikee trains of a detailed
model to a high degree of accuracy.,” J. Neurophhysiol., vol. 92, no. 2,
pp. 959–76, Aug. 2004.
[2] A. Hodgkin and A. Huxley, “A quantitative desccription of membrane
current and its application to conduction and exxcitation in nerve,” J.
Physiol., pp. 500–544, 1952.
[3] G. Indiveri, B. Linares-Barranco, T. J. Hamilton, A. van Schaik, R.
Dudek, P. Häfliger, S.
Etienne-Cummings, T. Delbruck, S.-C. Liu, P. D
Renaud, J. Schemmel, G. Cauwenberghs, J. A
Arthur, K. Hynna, F.
Folowosele, S. Saighi, T. Serrano-Gotarredona, J.. Wijekoon, Y. Wang,
and K. Boahen, “Neuromorphic silicon neurron circuits.,” Front.
Neurosci., vol. 5, no. May, p. 73, Jan. 2011.
Schaik, “A generalised
[4] R. Wang, T. J. Hamilton, J. Tapson, and A. van S
conductance-based silicon neuron for large-sscale spiking neural
networks,” in 2014 IEEE International Sympossium on Circuits and
Systems (ISCAS), 2014, pp. 1564–1567.

[5] S. Liu, J. Kramer, G. Indiveri, T. Delb
brück, and R. Douglas, Analog
VLSI: circuits and principles. Cambridg
ge, MA: MIT Press, 2002.
[6] C.-S. Poon and K. Zhou, “Neuromorp
phic silicon neurons and largescale neural networks: challenges and opportunities.,” Front. Neurosci.,
vol. 5, no. September, p. 108, Jan. 2011..
[7] W. Gerstner, R. Kempter, J. L. van Hemmen, and H. Wagner, “A
neuronal learning rule for sub-millisecond temporal coding.,” Nature,
vol. 383, no. 6595, pp. 76–81, Oct. 1996
6.
[8] R. J. Vogelstein, U. Mallik, J. T. Vog
gelstein, and G. Cauwenberghs,
“Dynamically reconfigurable silicon array
a
of spiking neurons with
conductance-based synapses.,” IEEE Trrans. Neural Netw., vol. 18, no.
1, pp. 253–65, Jan. 2007.
a A. van Schaik, “An FPGA
[9] R. Wang, T. J. Hamilton, J. Tapson, and
design framework for large-scale spik
king neural networks,” in 2014
IEEE International Symposium on Circu
uits and Systems (ISCAS), 2014,
pp. 457–460.
T
and A. van Schaik, “A
[10] R. M. Wang, T. J. Hamilton, J. C. Tapson,
mixed-signal implementation of a polycchronous spiking neural network
with delay adaptation.,” Front. Neuroscci., vol. 8, no. March, p. 51, Jan.
2014.
a A. van Schaik, “A compact
[11] R. Wang, T. J. Hamilton, J. Tapson, and
reconfigurable mixed-signal implemen
ntation of synaptic plasticity in
spiking neurons,” in 2014 IEEE Intern
national Symposium on Circuits
and Systems (ISCAS), 2014, pp. 862–865
5.
[12] K. Boahen, “Point-to-point connectivitty between neuromorphic chips
using address events,” IEEE Trans. Circuits
C
Syst. II Analog Digit.
Signal Process., vol. 47, no. 5, pp. 416–434, May 2000.

Figure 3. Simulation Results. (a) Tonic Fiiring; (b) Bursting; (c) Spike Frequency Adaptation; (d) Effect of inhibitory spikes.
The red curve represents the excitatory sppikes, the orange curve is the inhibitory spikes, the green
n curve represents Vsyn, the
pink curve represents Vmem and the blue currve represents the spike generated by Iactive.

