Complex Block Floating-Point Format with Box Encoding For
Wordlength Reduction in Communication Systems
Yeong Foong Choo∗ , Brian L. Evans∗ and Alan Gatherer†

arXiv:1705.05217v2 [] 25 Oct 2017

∗ Wireless

Networking and Communications Group, The University of Texas at Austin, Austin, TX USA
† Wireless Access Laboratory, Huawei Technologies, Plano, TX USA
∗ yeongfoong.choo@utexas.edu, bevans@ece.utexas.edu † alan.gatherer@huawei.com

Abstract—We propose a new complex block floating-point
format to reduce implementation complexity. The new format
achieves wordlength reduction by sharing an exponent across
the block of samples, and uses box encoding for the shared
exponent to reduce quantization error. Arithmetic operations are
performed on blocks of samples at time, which can also reduce
implementation complexity. For a case study of a baseband
quadrature amplitude modulation (QAM) transmitter and receiver, we quantify the tradeoffs in signal quality vs. implementation complexity using the new approach to represent IQ samples.
Signal quality is measured using error vector magnitude (EVM)
in the receiver, and implementation complexity is measured in
terms of arithmetic complexity as well as memory allocation and
memory input/output rates. The primary contributions of this
paper are (1) a complex block floating-point format with box
encoding of the shared exponent to reduce quantization error,
(2) arithmetic operations using the new complex block floatingpoint format, and (3) a QAM transceiver case study to quantify
signal quality vs. implementation complexity tradeoffs using the
new format and arithmetic operations.
Index Terms—Complex block floating-point, discrete-time
baseband QAM.

I. I NTRODUCTION
Energy-efficient data representation in application specific
baseband transceiver hardware are in demand resulting from
energy costs involved in baseband signal processing [1]. In
macrocell base stations, about ten percent of energy cost
contribute towards digital signal processing (DSP) modules
while power amplification and cooling processes consume
more than 70% of total energy [2]. The energy consumption
by DSP modules relative to power amplification and cooling
will increase in future designs of small cell systems because
low-powered cellular radio access nodes handle a shorter radio
range [2]. The design of energy-efficient number representation will reduce overall energy consumption in base stations.
In similar paper, baseband signal compression techniques
have been researched for both uplink and downlink. The methods in [3], [4], and [5] suggest resampling baseband signals
to Nyquist rate, block scaling, and non-linear quantization.
All three papers report transport data rate gain of 3x to 5x
with less than 2% EVM loss. In [5], cyclic prefix replacement
technique is used to counter the effect of resampling, which
would add processing overhead to the system. In [4] and
[6], noise shaping technique shows improvement of in-band
signal-to-noise ratio (SNR). In [7], transform coding technique
is suggested for block compression of baseband signals in

Fig. 1.

32-bit equivalent SIMD ALU in Exponent Box Encoding format

the settings of multiple users and multi-antenna base station.
Transform coding technique reports potential of 8x transport
data rate gain with less than 3% EVM loss. The above methods
achieve end-to-end compression in a transport link and incur
delay and energy cost for the compression and decompression
at the entry and exit points, respectively. The overall energy
cost reduction is not well quantified. This motivates the design
of energy-efficient data representation and hardware arithmetic
units with low implementation complexity.
In [8], Common Exponent Encoding is proposed to represent 32-bit complex floating-point data by only 29-bit
wordlength in hardware to achieve 3-bit savings. The method
in [8] shows 10% reduction of registers and memory footprints
with a tradeoff of 10% increase in arithmetic units. In [9],
exponential coefficient scaling is proposed to allocate 6 bits
to represent real-valued floating-point data. The method in [9]
achieves 37x reduction in quantization errors, 1.2x reduction in
logic gates, and 1.4x reduction in energy per cycle compared
to 6-bit fixed-point representation. Both papers report less than
2 dB of signal-to-quantization-noise ratio (SQNR).
Contributions: Our method applies the Common Exponent
Encoding proposed by [8] and adds a proposed Exponent
Box Encoding to retain high magnitude-phase resolution. This
paper identifies the computational complexity of complex
block addition, multiplication, and convolution and computes
reference EVM on the arithmetic output. We apply the new
complex block floating-point format to case study of baseband
QAM transmitter chain and receiver chain. We also reduce
implementation complexity in terms of memory reads/writes
rates, and multiply-accumulate operations. We base the sig-

TABLE I
D EFINITION & B IT W IDTHS U NDER IEEE-754 N UMBER F ORMAT [10]
Components
Wordlength, W
Sign, S
Exponent, E
Mantissa, M

Definition
Nw
Ns
Ne
Nm

Bit Widths, B
{16, 32, 64}
{1}
{5, 8, 11}
{10, 23, 52}

TABLE III
D EFINITION & B IT W IDTHS U NDER E XPONENT B OX E NCODING
Components
Common Exponent, E
Real / Imaginary Sign, S
Real / Imaginary Lead, L
Real / Imaginary Box Shift, X
Real / Imaginary Mantissa, M

Definition
Ne
NsR,I
NlR,I
NxR,I
R,I
Nm

Bit Widths , B
{5, 8, 11}
{1}
{1}
{1}
{10, 23, 52}

TABLE II
D EFINITION & B IT W IDTHS U NDER C OMMON E XPONENT E NCODING [8]
Components
Common Exponent, E
Real / Imaginary, S
Real / Imaginary Lead, L
Real / Imaginary Mantissa, M

Definition
Ne
NsR,I
NlR,I
R,I
Nm

Bit Widths, B
{5, 8, 11}
{1}
{1}
{10, 23, 52}

nal quality of our method on the measurement of EVM at
the receiver. Our method achieves end-to-end complex block
floating-point representation.
II. M ETHODS
This section describes the data structure used in new representation of complex block floating-point [8] and suggests a
new mantissa scaling method in reducing quantization error. In
IEEE 754 format, the exponents of complex-valued floatingpoint data are separately encoded. Common Exponent Encoding technique [8] allows common exponent sharing that has
weak encoding of phase resolution.
A. Common Exponent Encoding Technique
Table I summarizes the wordlength precision of real-valued
floating-point data in IEEE-754 encoding [10]. We define Bw bit as the wordlength of scalar floating-point data. A complexvalued floating-point data requires 2Bw -bit and a complex
block floating-point of Nv samples requires 2Nv Bw -bit.

Fig. 2. Scatter plot of N = 25 complex-valued exponent pairs X ∼
N (130, 122 ) ( ) and potential candidate for common exponent ( )

The method in [11] assumes only magnitude correlation in
the oversampled complex block floating-point data. This assumption allows common exponent be jointly encoded across
complex block floating-point of Nv samples defined in Table
II. The implied leading bit of 1 of each floating-point data
is first uncovered. The common exponent is selected from
the largest unsigned exponent across the complex block. All
mantissa values are successively scaled down by the difference between common exponent and its original exponent.
Therefore, each floating-point data with smaller exponents
value loses leading bit of 1. The leading bit of complex block
floating-point is explicitly coded as Nl , using Bl -bit. The sign
bits are left unchanged. A complex block floating-point of Nv
samples requires {2Nv (Bs + Bl + Bm ) + Be }-bit.
We derive the maximum allowed exponent difference under
Common Exponent Encoding in Appendix A. Mantissa values
could be reduced to zero as a result of large phase difference.
Figure 2 shows the Effective Encoding Region (EER) under
Common Exponent Encoding technique ( ). Exponent pairs
outside the EER will have corresponding mantissa values
reduce to zero.
B. Exponent Box Encoding Technique
The Common Exponent Encoding technique suffers high
quantization and phase error in the complex block floatingpoint of high dynamic range. Exponent Box Encoding is
suggested to reduce quantization error of complex-valued
floating-point pairs by allocating 2Nv -bit per complex block.
Figure 2 shows the Effective Encoding Region under Exponent
Box Encoding technique ( ) which has four times larger the
area of EER of Common Exponent Encoding technique ( ).
The use of 2-bit per complex sample replaces the mantissas
rescaling operation with exponents addition/ subtraction. We
are able to preserve more leading bits of mantissas values
which improve the accuracy of complex block multiplication
and complex block convolution results. A complex block
floating-point of Nv samples requires {2Nv (Bs + Bl + Bx +
Bm ) + Be }-bit.
Arithmetic Logic Unit (ALU) hardware is designed to
perform Single-Instruction Multiple-Data (SIMD) operation
on complex block floating-point data. The Exponent Box
Encoding is performed when converting to Exponent Box
Encoding format. The Exponent Box Decoding is performed
at the pre-processing of mantissas in Complex Block Addition
and pre-processing of exponents in Complex Block Multiply.

TABLE IV
W ORDLENGTH R EQUIREMENT BY Nv C OMPLEX -VALUED S AMPLES
Encoding
Complex IEEE754
Common Exponent
Exponent Box

Bit Widths
2Nv (Bs + Be + Bm )
2Nv (Bs + Bl + Bm ) + Be
2Nv (Bs + Bl + Bx + Bm ) + Be

Fig. 4. Pre-Scale exponents in Complex Block Multiply

A. Complex Block Addition
Figure 3 shows simplified block diagram for Complex Block
Addition. Let X1 , X2 , Y ∈ C1×N be complex-valued row
vectors, such that,
Fig. 3. Pre-Scale mantissas in Complex Block Add

<{Y } = <{X1 } + <{X2 }
Table IV summarizes the wordlength analysis required by
complex block floating-point of Bv samples. The Exponent
Box Encoding and Exponent Box Decoding algorithms are
described as follows:
Algorithm 1 Exponent Box Encoding
Let U ← max{E{s}} − Bm
for ith ∈ Nv {R/I} samples do
if NeR {i} < U then
NeR {i} ← NeR {i} + Bm
NxR {i} ← 1
if NeI {i} < U then
NeI {i} ← NeI {i} + Bm
NxI {i} ← 1

Algorithm 2 Exponent Box Decoding
for ith ∈ Nv {R/I} samples do
if NxR {i} ≡ 1 then
NeR {i} ← NeR {i} − Bm
if NxI {i} ≡ 1 then
NeI {i} ← NeI {i} − Bm

={Y } = ={X1 } + ={X2 }

In IEEE-754 encoding format, complex block addition is
implemented as two real-valued addition. There are four
exponents to the two complex inputs and two exponents to the
complex output. Each real-valued addition block requires one
mantissa pre-scaling, one mantissa post-scaling, and one exponent arithmetic. Therefore, complex block addition requires
two mantissas pre-scaling, two mantissas post-scaling, and two
exponents arithmetic per sample.
In Common Exponent and Exponent Box Encoding, there
are two shared exponents to the two complex block inputs and
one shared exponent to the complex block output. Complexity
on shared exponent arithmetic is O(1). We pre-scale the mantissas corresponding to the smaller exponent and post-scale
the mantissas of the complex block output. With Exponent
Box Encoding in the worst case, we require two mantissas
pre-scaling and one mantissas post-scaling.
B. Complex Block Multiplication
Figure 4 shows simplified block diagram for Complex Block
Multiplication. Let X1 , X2 , Y ∈ C1×N be complex-valued
row vectors, where • denotes element-wise multiply, such that,
<{Y } = <{X1 } • <{X2 } − ={X1 } • ={X2 }
={Y } = <{X1 } • ={X2 } + ={X1 } • <{X2 }

III. A RITHMETIC U NIT
We identify the arithmetic units predominantly used on
complex block floating-point data. Complex-valued multiplication and addition are two primary ALU required in convolution operation. This section identifies the complexity of
pre-processing and post-processing mantissas and exponents
in the complex block addition, multiplication, and convolution arithmetic. Table V describes the worst-case complexity
analysis of complex block ALU on encoding format described
in Section II.

(1)

(2)

In IEEE-754 encoding format, complex block multiplication
is implemented as four real-valued multiplication and two
real-valued addition. Each real-valued multiplication requires
one mantissa post-scaling and one exponent arithmetic. Each
real-valued addition requires one mantissa pre-scaling, one
mantissa post-scaling, and one exponent arithmetic. Complex
block multiply requires two mantissas pre-scaling, six mantissas post-scaling, and six exponent arithmetic per sample.
In Common Exponent and Exponent Box Encoding, we
need two exponent arithmetic for multiply and normalization

TABLE V
M ANTISSAS AND E XPONENT P RE /P OST P ROCESSING C OMPLEXITY OF C OMPLEX B LOCK ALU
Block Addition
Complex IEEE754
Common Exponent
Exponent Box
Block Multiplication
Complex IEEE754
Common Exponent
Exponent Box
Convolution
Complex IEEE754
Common Exponent
Exponent Box

Mantissas Scaling
4∗N
4∗N
8∗N
Mantissas Scaling
8∗N
8∗N
16 ∗ N
Mantissas Scaling
6 ∗ N1 N2 + 4 ∗ (N1 − 1)(N2 − 1)
6 ∗ N1 N2 + 4 ∗ (N1 − 1)(N2 − 1)
10 ∗ N1 N2 + 8 ∗ (N1 − 1)(N2 − 1)

Exponents Arithmetic
2∗N
2
4
Exponents Arithmetic
6∗N
2
5
Exponents Arithmetic
6 ∗ N1 N2 + 2 ∗ (N1 − 1)(N2 − 1)
3 ∗ (N1 + N2 − 1) + 1
3 ∗ (N1 + N2 − 1) + 1

of the complex block output. With Exponent Box Encoding
in the worst case, we need eight more mantissas post-scaling.
Also, the Shift Vectors allow for four possible intermediate
exponent values instead of one intermediate exponent value in
Common Exponent Encoding.

QAM Parameters
Constellation Order
Transceiver Parameters

Definition
M
Definition

Values / Types
1024
Values / Types

C. Complex Convolution
Let X1 ∈ C1×N1 , X2 ∈ C1×N2 , and Y ∈ C1×(N1 +N2 −1)
be complex-valued row vectors, where ∗ denotes convolution,
such that,

Up-sample Factor
Symbol Rate (Hz)
Filter Order
Pulse Shape
Excess Bandwidth Factor

LT X , LRX
fsym
N T X , N RX
g T X , g RX
αT x , αRX

4
2400
32th
Root-Raised Cosine
0.2

<{Y } = <{X1 ∗ X2 }
={Y } = ={X1 ∗ X2 }

TABLE VI
QAM T RANSMITTER , R ECEIVER S PECIFICATIONS

(3)

We assume N1 < N2 for practical reason where the model
of channel impulse response has shorter sequence than the
discrete-time samples. Each term in the complex block output
is complex inner product of two complex block input of
varying length between 1 and min{N1 , N2 }. Complex convolution is implemented as complex block multiplication and
accumulation of intermediate results. We derive the processing
complexity of mantissas and exponents in Appendix B.
IV. S YSTEM M ODEL
We apply Exponent Box Encoding to represent IQ components in baseband QAM transmitter in Figure 5 and baseband
QAM receiver in Figure 6. The simulated channel model is
Additive White Gaussian Noise (AWGN). Table VI contains
the parameter definitions and values used in MATLAB simulation and Table VII summarizes the memory input/output rates
(bits/sec) and multiply-accumulate rates required by discretetime complex QAM transmitter and receiver chains.
A. Discrete-time Complex Baseband QAM Transmitter
We encode complex block IQ samples in Exponent Box
Encoding and retain the floating-point resolution in 32-bit
IEEE-754 precision in our model. For simplicity, we select
block size to be, Nv = LT X fsym . The symbol mapper
generates a LT X fsym -size of complex block IQ samples that
shares common exponent. Pulse shape filter is implemented
as Finite Impulse Response (FIR) filter of N T X -order and
requires complex convolution on the upsampled complex block
IQ samples.

Fig. 5. Block diagram of discrete-time complex baseband QAM transmitter

B. Discrete-time Complex Baseband QAM Receiver
Due to the channel effect such as fading in practice, the
received signals will have larger span in magnitude-phase response. The Common Exponent Encoding applied on sampled
complex block IQ samples is limited to selecting window
size of minimum phase difference. The Common Exponent
Encoding must update its block size at the update rate of gain
by the Automatic Gain Control (AGC). Instead, our Exponent
Box Encoding could lift the constraint and selects fixed block
size, Nv = LRX fsym in this simulation. We simulate matched
filter of N RX -order.

Fig. 6. Block diagram of discrete-time complex baseband QAM receiver

TABLE VII
M EMORY I NPUT / O UTPUT AND C OMPUTATIONAL R ATES ON E XPONENT B OX S HIFTING T ECHNIQUE
Transmitter Chain
Symbol Mapper
Upsampler
Pulse Shape Filter
Receiver Chain

Memory Reads Rate (bits/sec)
Jfsym
2fsym (Nw + Nl + Nb − Ne ) + Ne
(3LT x NgT x + 1)(LT x fsym )(Nw + Nl + Nb − Ne ) + 2Ne
Memory Reads Rate (bits/sec)

Memory Writes Rate (bits/sec)
2fsym (Nw + Nl + Nb − Ne ) + Ne
2LT x fsym (Nw + Nl + Nb − Ne ) + Ne
2LT x fsym (Nw + Nl + Nb − Ne ) + Ne
Memory Writes Rate (bits/sec)

MACs / sec
0
0
(LT x )2 NgT x fsym
MACs / sec

Matched Filter
Downsampler
Symbol Demapper

(3LRx NgRx + 1)(LRx fsym )(Nw + Nl + Nb − Ne ) + 2Ne
2LRx fsym (Nw + Nl − Ne ) + Ne + (Nw + Nl + Nb )
2fsym (Nw + Nl − Ne ) + Ne + J2 (Nw + Nl )

2LRx fsym (Nw + Nl + Nb − Ne ) + Ne
2fsym (Nw + Nl + Nb − Ne ) + Ne
Jfsym

(LRx )2 NgRx fsym
0
0

Fig. 7. Error vector magnitude of 32-bit complex block arithmetic

Fig. 8. Dynamic range of 32-bit RRC filter impulse response as function of
roll-off factor

V. S IMULATION R ESULTS

B. Error Vector Magnitude on Single-Carrier Transceiver

A. Error Vector Magnitude on Complex Block (32-bit) ALU
Let X, X̄ ∈ C1×N be complex-valued row vectors, such
that X is the reference results in IEEE-754 Encoding and X̄
is the simulated results in Complex Block Encoding.
The signal quality is measured on the complex block
arithmetic results. We truncate the arithmetic results to 32bit precision to make fair comparison. We use the RootMean-Squared (RMS) EVM measurement as described in the
following, with k • k2 as the Euclidean Norm,

Figure 8 shows the dynamic range of Root-Raised Cosine
(RRC) filter at transmitter and receiver and overall pulse
shape response as a function of α. Figure 9 shows the EVM
introduced by Complex Block Encoding under system model
defined in Section IV. The EVM plot is indistinguishable
between IEEE-754 Encoding and Complex Block Encoding.
The reasons are the selection of RRC Roll-off factor and
energy-normalized constellation map.
VI. C ONCLUSION

k X − X̄ k2
EV M =
∗ 100
k X k2

(4)

Figure 7 shows the EVM of complex block arithmetic
in Section III on Inputs Ratio ∈ (0, 200) dB. In complex
block addition, the Exponent Box Encoding does not show
significant advantage over Common Exponent Encoding because the mantissas addition emphasizes on magnitude over
phase. In complex block multiplication and convolution, the
Exponent Box Encoding achieves significant reduction in
encoding error over Common Exponent Encoding particularly
on Inputs Ratio ∈ (70, 140) dB where the improvement is
between (0, 99.999)%.

Our work has identified the processing overhead of the
mantissas and shared exponent in complex block floating-point
arithmetic. The common exponent encoding would slightly
lower the overhead in complex-valued arithmetic. The box
encoding of the shared exponent gives the same quantization
errors as common exponent encoding in our case study,
which is a 32-bit complex baseband transmitter and receiver.
Our work has also quantified memory read/write rates and
multiply-accumulate rates in our case study. Future work could
extend a similar approach to representing and processing IQ
samples in multi-carrier and multi-antenna communication
systems.

terms from X1 , X2 and requires (N2 − N1 )((N1 )(Nmult ) +
(N1 − 1)(Nadd )).
Overall Multiplication Requirement (Nmult ):
1
1
(N1 )(N1 + 1) + (N2 − N1 )(N1 ) + (N1 − 1)(N1 )
2
2
1 2
1 2
2
= (N1 + N1 ) + (N2 N1 − N1 ) + (N1 − N1 )
2
2
1
2
2
= (2N1 ) + (N2 N1 − N1 )
2
= N12 + (N2 N1 − N12 )

(6)

= N2 N1
Overall Addition Requirement (Nadd ):

Fig. 9. Error vector magnitude between encoding techniques on complexvalued IQ samples

A PPENDIX A
D ERIVATION OF M AXIMUM E XPONENT D IFFERENCE
U NDER C OMMON E XPONENT E NCODING T ECHNIQUE

= (N1 − 1)(N1 − 1) + (N2 − N1 )(N1 − 1)
= (N1 − 1)(N1 − 1 + N2 − N1 )

Let i, j be two bounded positive real numbers, representable
in floating point precision. Assume that i has larger magnitude
than j, |j| < |i|. Define E{k} as exponent and M {k} as
mantissa to k, and F (k) = 2E{k}−1 − 1 as exponent offset,
where k = {i, j}. Let E{∆} be the difference between two
exponents, (E{i} − E{j}) > 0.
j<i
(1.M {j} ∗ 2E{j}−F (j) ) < (1.M {i} ∗ 2E{i}−F (i) )
(1.M {j} ∗ 2E{j} ) < (1.M {i} ∗ 2E{i} )
(1.M {j} ∗ 2E{j}−E{i}+E{i} ) < (1.M {i} ∗ 2E{i} )
(1.M {j} ∗ 2E{j}−E{i} ) < (1.M {i})

1
1
(N1 − 1)(N1 ) + (N2 − N1 )(N1 − 1) + (N1 − 2)(N1 − 1)
2
2
1
= (N12 − N1 + N12 − 3N1 + 2) + (N2 − N1 )(N1 − 1)
2
= (N12 − 2N1 + 1) + (N2 − N1 )(N1 − 1)

(5)

(1.M {j} ∗ 2−E{∆} ) < (1.M {i})
(0.M {j 0 }) < (1.M {i})
1.M {j}
where M {j 0 } = E{∆}
2
0
The mantissa bits in M (j ) are truncated in practice, therefore, E{∆} must be less than M (j). The quantization error is
the largest when the M (j 0 ) gets zero when M (j) is nonzero.
A PPENDIX B
D ERIVATION OF P RE / P OST P ROCESSING C OMPLEXITY OF
C OMPLEX - VALUED C ONVOLUTION
exp
exp
mant
mant
Let Nmult
, Nadd
, Nmult
, Nadd
be processing complexity
of mantissas and exponents determined in Section III.
Among the first and last N1 terms of Y , they are computed by complex inner product of i ∈ {1, ..., N1 } input
1 +1)
(Nmult ) and
terms from X1 , X2 and requires (N1 )(N
2
(N1 −1)(N1 )
(Nadd ). Among the centering N2 − N1 terms of
2
Y , they are computed by complex inner product of N1 input

= (N1 − 1)(N2 − 1)
(7)
mant
Mantissa processing requirement is (Nmult
)(N2 N1 ) +
mant
(Nadd
)(N1 − 1)(N2 − 1) and exponent processing requireexp
exp
ment is (Nmult
)(N2 N1 ) + (Nadd
)(N1 − 1)(N2 − 1).

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