THE ANALYSIS OF SELF-TIMED FULL-ADDER IN TERMS OF FAULT-TOLERANCE
Reviewed and analyzed the self-timed implementation of a binary adder at the level of CVR transistors made in the Institute of Informatics Problems of the Russian Academy of Sciences (IPI RAS). Compendium self-timed elements prepared by the research team led by Y. Stepchenkov. The proposed variants are compared with the realization in the functionally complete tolerant element (FCT - logic element with the redundancy basis). Shows the advantages of transistor implementation of the proposed fault-tolerant implementation.