Methods for implementing the Kuznyechik algorithm on FPGAs
Increased volumes and speed of data transmission over computer networks, and also the need to protect the transmitted data, require accordingly to increase the speed of cryptographic data processing. One of the ways to achieve high performance is implementation of FPGAs-based cryptographic equipment. Therewith, to cut the cost of equipment, it is important that encryption modules shall consume a minimum possible hardware resources. The work aims to find the most compact high-speed solution for FPGA-based Kuznyechik block cipher. Several methods for hardware implementation of linear transformation, which is used in Kuznyechik cipher, have been reviewed. Various aspects of implementation of these methods taking into account the architecture of target FPGAs are investigated. We also consider aspects of the FPGA implementation of nonlinear transformation, which is used in Kuznyechik block cipher. Resource consumption by various implemented solutions of linear transformation has been estimated. A relatively compact high-speed implemented solution of Kuznyechik block cipher has been obtained and tested on the real equipment. The achieved values of speed for iterative and fully pipelined implementations of the algorithm have been presented.