Adaptation Process of System-on-a-Chip RTL-Description for Distributed Emulation System
Multi-FPGA distributed emulation systems are commonly used for functional verification of System-on-a-Chip. However, using such systems poses a problem of adaptation RTL-description for use in multi-FPGA system. This article outlines common issues for transition process towards functional verification of System-on-a-Chip using multi-FPGA distributed emulation system from the developer point of view. Article also introduces a method of adaptation, currently used in JCT “MCST”. Adaptation process presents following problems: distributing SoC description across multiple FPGAs, configuring inter-FPGA connections according to RTL logic, generating FPGA firmware. Proposed method solves these problems. It consists of five stages. The first stage: preparation - setting up runtime for implementation and limited flattening of SoC hierarchy. The second stage - partition and assembly - creating interconnected logic modules containing original RTL, FPGA wrappers and top-level modules. Model generation -generating RTL model of distributed emulation system. Postprocessing - correcting of CAD artifacts and making generated RTL more human-readable for further modification. FPGA project generation - creating FPGA projects from project templates for further firmware generation.