Performance Analysis of Microcontrollers with Core Cortex-M3
Analytical and practical methods for evaluating the computational performance of microcontrollers (MC) are known. Analytical methods are based on information about the architecture of the MC under study (the list of MC instructions, their execution time, pipeline design, memory size). While practical methods are devoted to solving classical algorithmic problems. At the same time, the performance of MC, in addition to the characteristics of the MC core, is affected by a number of other factors that are not taken into account when using analytical methods. In this paper, a comparative analysis of the performance of MCs with the Cortex-M3 core is performed. Estimates of the speed and efficiency of performing operations of domestic MCs K1986BE92QI K1986BE91T and their foreign counterparts STM32F103C8, STM32F100RBT6 are presented. Test programs have been developed to measure performance when performing arithmetic operations with integers and floating point numbers. Comparison of the speed of access to I/O ports using the libraries CMSIS, SPL "Milandr" and "STMicroelectronics" was carried out. The program code of tests for calculating the number п and numbers of the Fibonacci series is presented. When performing arithmetic operations on integers, STM32 MCs use fewer machine instructions than domestic MCs. The greatest difference was found when performing a test with integer division for K1986BE91T and STM32F100RBT6 MCs. A load test was performed in the form of calculating the number of machine instructions spent by the MC to calculate numbers from the Fibonacci series, which performs a direct calculation of each next number of the series in a cycle using a recursive function call and a linear algorithm. When compiled without code optimization, MK K1986BE92QI and K1986BE91T performed 1.57 times more machine instructions when calculating the "number п" than STM32F100. When using code optimization in the process of compiling the firmware, domestic MCs performed 4.85 million fewer machine instructions to calculate the "number π" than without using code optimization. Thus, the computational efficiency of the MC largely depends on the level of optimization of machine instructions, and the use of different MCs with an identical core does not guarantee identical performance characteristics of the MC when executing a reference task. According to the test results, it can be seen that the performance of the MCs is determined not only by the architecture of the MC core, but also by peripheral devices.