ALGORITHM OF GENERATION CLOCK SIGNAL FOR SDRAM MEMORY
An algorithm for generating a clock signal of SDRAM chips is considered to increase the reliability of read and write operations under the influence of the external environment. The idea of the algorithm is a sequential write and read operations. First, the constant value is written to the memory, and then read from it. If the writing operation was successful, the delay value is stored in the internal register. Next we need to find a value that the algorithm cannot read. The algorithm will try to find this value until a working option is found, or the delay limit elements is over. When the first working delay value is found and stored, the algorithm will continue to perform a write-read cycle, simultaneously increasing the delay value until the read value coincides with the recorded value. Thus, the minimum and maximum delay values will be found, the average delay value is calculated and set as the main one. The description of the algorithm is performed by means of the VHDL language. The FPGA from Xilinx of the Virtex 5 family, model XC5VLX110, is used as a development platform