THE IMPLEMENTING OF PARALLEL ARRAY SORTING USING THE HOAR`S METHOD IN FPGA-ARCHITECTURE
In the article the problem of parallel implementation of the Hoar sorting method adapted to the FPGA-architecture are deals. The implementation is involves determining the index of an element in the input array, which, if the array is ordered in ascending, occupies the specified position in it. Estimates of the hardware and time complexity of the specified parallel implementation method based on the number and time delay of functioning, respectively, of hardware IP-cores defined in the FPGA-architecture are obtained.