Simulation of Processor Data Paths with VLIW Architecture at the System Level
This article describes an approach to modeling data paths for VLIW processors. Such processors are characterized by the use of a complex structure of the data path, which may include several arithmetic logic devices and auxiliary computing and switching devices that provide various characteristics of performance, space and power consumption. In view of the inconsistency of these parameters, to achieve a qualitative design result, it is required to formulate optimality criteria, which can be obtained only on the basis of an analysis of model problems of a certain target class. In order to quickly check the characteristics of the processor when solving such problems, it is required to simulate it at a high level (for example, at the transaction level) by analyzing the code generated by the cross-assembler. The article discusses an approach to the development of a cross-assembler and a modeling system at the transaction level, implemented consistently on the basis of a regular grammar. As a prototype of the modeling and assembly system, a virtual Forth machine has been implemented, within which examples of the description of assembler instructions of the designed processors and the transaction level model consistent with them are demonstrated.