THEORETICAL-GRAPH MODEL OF IP-BLOCKS FOR CMOS TECHNOLOGY WITH 3D STRUCTURE OF THE TRANSISTOR
The paper is devoted to research and development of methods of designing custom IP- blocks in the basis elements with regular topological structure in layers of polysilicon and diffusion. For today the leading developers of microelectronic devices continue to work out the key modules of microelectronic systems, such as core microprocessors, microcontrollers completely custom-made in a mode in which the final composition of library elements is not known beforehand, and the design is extremely low at the transistor level. However, automation of process logic and topology synthesis for a completely custom design is difficult due to significant increase in the complexity of the problem with increasing integration of microelectronic systems and decreasing the size of the basic elements of technology to 22 nm and below. Proposed methods of the formation of topological designs of various FinFET structures for topology synthesis of elements with a regular topological structure in layers of polysilicon and diffusion.