Towards Fast Implementation of Complex RNS Components on FPGAs
The efficient hardware implementation of RNS particularly on field program-mable gate array (FPGA) is very important due to the use of FPGAs in some modern computing systems to achieve flexibility and low time-to-market. The residue number system (RNS) with its inherent parallelism can also be used to enhance the performance of implementation of comput-ing algorithms on FPGAs. However, complex RNS operations such as residue to binary (reverse) conversion, sign detection, scaling, magnitude comparison and overflow detection have not been efficiently implemented on FPGAs until now. In this work, we try to address an approach to increase the speed of residue to binary conversion implementation on FPGAs using parallel-prefix adders. This can be a first step towards fast implementation of complex RNS operations on FPGAs, since residue to binary conversion can also be used to solve other difficult RNS operations.