Method of combined redundancy for self-timed technology
One of the current problems concerning self-timed circuits (STC) is the issue of providing fault tolerance. The main attention is given to active fault tolerance. To provide passive fault tolerance of a STC, one could apply, e.g., so called triplication - three channels of a digital machine whose bit outputs are connected with three inputs of the majority element, implementing the majority function (choice "2-of-3" > 2). However, in this case the basic principle of self-timed technology -its semimodularity - is violated, which is registered by the existing tools for analyzing a STC correctness. The authors propose a method of combined redundancy based on transistor structures, rejecting faults of some transistors resulting from exposure to radiation and other negative factors. However, such redundancy is not always possible and is subject to limitations of Mead and Conway. The article presents a method of combined redundancy for STC with the use of transistors, allowing one to achieve a set probability of failure-free performance.