Designing a Configurable 32-Bit RISC-V Microprocessor
Implementation of a configurable 32-bit microprocessor based on RISC-V instruction set architecture for embedded applications and integration into systems on a chip is presented. Processor core can also be used in field-programmable gate arrays (FPGA). Advantages of using RISC-V architecture include common availability and free use, including for commercial purposes, as well as architecture modularity. The processor can be configured to use 16 (RV32E instruction set) or 32 registers (RV32I instruction set) with a 32-bit width. The following architecture extensions are available as well: Standard Extension for Integer Multiplication and Division in 32 clock cycles (extension M), Standard Extension for 16-bit Compressed Instructions to save memory (extension C), two privileged modes (Machine and User), as well as a set of control and status registers (CSR) required for them. The processor has 5-stage instruction pipeline. Branch predictors, bypass and instruction cache can be added as options. Capability to flexibly configure the processor core depending on the tasks and limitations imposed on the developed chip is demonstrated. Performance and area occupied on the chip indicators of various processor core configurations are defined. One of the microprocessor configurations with RV32IMC instruction set, branch predictors, bypass, as well as hardware integer multiplication and division was implemented in CMOS SOI 0.6 pm technology using the Cadence EDA Tools. Various parameters of this CMOS chip containing the processor core under development were simulated. In particular, power consumption and the voltage drop (IR drop) on the power lines were analyzed. The software tests performed on the processor demonstrated its full compatibility with the RISC-V instruction set architecture and allowed to evaluate its performance against other processor cores and microcontrollers. The results of the CoreMark benchmark for various microprocessor configurations are also presented. Comparison of the performance of the developed processor core with other processors and microcontrollers is shown.