10GHz Bang-Bang All Digital Phase-Locked Loop with Jitter Reduction Circuit
10GHz all-digital phase-locked loop implementation is presented in the article. Frequency of output signal is 10GHz with rms jitter 315fs. Built-in automatic loop gain control circuit reduces rms jitter of output signal by 43%. Algorithm of jitter reduction is based on incremental change of proportional gain achieving stochastic resonance in binary phase detector output sequence. ADPLL lock time is 12ps. Frequency acquisition and gear shifting methods are used to boost lock process.