ASSESMENT OF EFFECTIVITY OF PARALLEL DIRECTIONAL INTERPOLATION ALGORITM IN DIGITAL IMAGE SCALING MODULE
This article deals with digital image scaling and optimizing of calculations by means of parallel processing. It is argued that the most efficient structure for this task is that of many-staged processing. Ii proposed to use FPGA as the hardware basis. The main velocity advantage of pipelined approach as compared with one-pass processing is the merit of fast zooming algorithms with a certain factor (in our case, 2) where majority of preliminary image analysis algorithms belong. Combination of targeted interpolation algorithm and pipeline mode allows elimination of consuming multiplication and division processes, using exclusively fast integer addition, diminution and shift operations of modern PLD equal in fast performance to VLSI. With modern PLD-aided scaling, higher response rate as compared to software-only approach is achievable along with the option of system modification.