Combinatorial Test Program Generation for Microprocessors Based on Formal Specifications of Instruction Set Architecture
Test program generation and simulation is the most widely used approach to functional verification of microprocessors. Functional verification is a quite time consuming process. According to various estimates, it accounts for more than 70% of overall resources spent on designing a new microprocessor. This can be explained by the fact that modern hardware designs have an enormous state space and covering all the states demands significant efforts. Most of modern test program generation tools create test stimuli either using random methods or by resolving constraints that specify conditions to be hold to reach certain states. Both approaches do not guarantee that all states will be covered since they are targeted at random or predefined situations. The present work proposes an approach to test program generation that helps improve test coverage by strengthening constraint-based generation with combinatorial methods. The key idea is to construct fixed-length instruction combinations and to apply various combinations of constraints to them. Information used as a basis for creating tests is automatically extracted from formal specifications of the instruction set architecture.