Ethernet Switch IP-Core for Wireless Backhaul Systems
This article presents design of a 3-port Ethernet switch IP-core for a point-to-point wireless backhaul system. The IP-core is dedicated for implementation of in-band management via switching of Ethernet frames between the external Ethernet interface, the data interface of the radio modem and the network interface of the CPU. The switch supports 10/100/1000 Mbps data rates and routes Layer-2 frames based on their Ethernet MAC addresses, virtual network identifiers (IEEE 802.1Q VLAN ID) and logical inter-connections between Ethernet MAC interfaces (port-based VLANs). The switch architecture and FPGA hardware implementation features are presented. The switch architecture is optimized for specific requirements of the in-band management application and characteristics of the transmitted traffic. The following main requirements are taken into account: • Switching of the Ethernet frames between three ports based on MAC addresses 0. • The major part of traffic is transmitted between the Ethernet interface and the radio modem. Therefore, frame commutation is based on a hybrid scheme that combines a “cut-through” approach for most frames and full buffering in the cases of a flooding or a target output port occupation by another transmission. • The maximum input data rate for each port is 1 Gbps with independent support on different ports of 10 and 100 Mbps. • The receiver of the radio modem includes a buffer for input data therefore the size of ingress port buffers can be decreased up to several maximum frame lengths. • Ethernet Flow Control standard 0 is supported for lossless data transmission in case of exceeding the egresses port maximum bandwidth that protects input buffers against an overflow and received frames damaging. • The network switch topology can include different virtual LANs and frames are routed between ingress and egress ports via VLAN header information according to • Port-Based VLAN determines a logical interconnection between each switch port pair and allows or denies data transferring in each direction. The switch IP core was prototyped and verified using the Xilinx XC7Z020T FPGA device. The resource utilization estimates are the following: • Flip-Flop count: 5202 (4.89%) • LUT count: 2588 (4.86%) • BRAM count: 21 (12.29%) Presented results that demonstrate efficient hardware resource utilization allow to consider as appropriate for practical implementation.