System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture
In connection with the architectural complexity of modern multi-core structures, more than 60% of the design resources are spent on verification during the development of the processor. Automatic generation of tests is often used to increase test coverage and reduce overall test time. Therefore, the creation of verification test generators to verify the correct operation of microprocessors is becoming increasingly important. This paper describes the technique of development of the several tests generators used for microprocessor verification. The first one is designed for generating VLIW of packets. The second one is for the verification of the control flow. With the help of it creates sequences of assembler instructions are created to check the pipeline. Software and hardware cycles, subprogram calls, conditional and unconditional conversions are possible. The third generator is aimed at checking the cache memory of the processor. It is based on the graph model of the memory subsystem built on its description. In the suggested approach, the source code of the tests is constructed by using combinatorial techniques, that is all possible combinations of instructions, situations, and dependencies are sorted taking into account the constraints that direct the tests to check certain situations and also exclude the possibility of generating infinite cycles. The generated test sequences allow for various tests. To create the more complex tests possible integration of generators into each other is considered since the interaction of different devices of the processor generates a large number of critical situations. The proposed approach makes it possible to improve the efficiency of microprocessor testing.