Testing the Performance of the Embedded Gigabit Ethernet Controller’s FPGA Prototype when Working with TCP
Modern microprocessors have one or more cores. Also they can contain embedded controllers of peripheral interfaces. Field-programmable gate arrays (FPGAs) used for testing designs of microcircuits as their electric prototypes with reduced frequency, which is usually 100-200 MHz. The microprocessor with KOMDIV64 architecture includes an embedded Gigabit Ethernet controller. Performance evaluation of the FPGA-prototype of that controller was one of the testing tasks. The consequence of the high bandwidth of Gigabit Ethernet is the CPU loading, which can become a "bottle neck" for the entire system. At the beginning of the article, information is presented to understand the factors which affects the Ethernet performance, based on the of the English-language materials. Also, some information about software and hardware CPU offloading methods is given. The task is an experimental performance evaluation of the Gigabit Ethernet Controller’s FPGA proto-type to confirm the absence of internal delays in the project. In addition, efficiency of hardware CPU offloading features is of interest. The direct including of the Ethernet controller project into FPGA prototype of whole microprocessor can’t provide for good results due to limited core frequency. It is proposed to evaluate the performance of the Gigabit Ethernet controller project by installing a board with its FPGA prototype into the PCI slot of an IBM-PC compatible computer. For brevity, only the results of netperf TCP_STREAM test under Linux are given. The CPU load was estimated with the "gnome-system-monitor" program, or the netperf built-in function. The results are presented, in comparison with an analog by Marvell and with a microprocessor after its manufacturing. As a result, the receive speed of the CPU embedded Ethernet is almost equal to the FPGA prototype on IBM PC, but the transmission speed is much higher.