FEATURES OF THE XILINX FPGA VIRTEX MAJORITY VOTE CIRCUITS
Analyzed Triple Module Redundancy Design Techniques with the majority element of the three-state buffers used when creating projects for the programmable logic Xilinx FPGAs Virtex type to reduce radiation-induced switching of logic elements (Single Event Tran-sients-SET) and memory elements (Single Event Upset -SEU). Evaluated the results of the simulation of the majority elements on the transistor level and at a logical level. The paper proposed a method of modeling at the logical level of majority elements of the tri-state buffers, avoiding inappropriate undefined states in the process of analysis of the project, created in VHDL.