GENETIC ALGORITHM PLANNING THE VLSI PLACEMENT
The paper deals with the problem of solving the problem of placement in the design of electronic equipment. The task belongs to the class NP-complete and for it there is no exact polynomial algorithm. The purpose of this work is to find ways to optimize the planning of the placement of VLSI using a modified genetic algorithm. The relevance of the work lies in the fact that the modified genetic algorithm used allows to improve the quality of placement planning. Scientific novelty is the development of a modified genetic algorithm. The modified genetic algorithm uses knowledge about the problem being solved, which makes it possible to quickly obtain effective local solutions. The statement of the problem in this paper is as follows: to optimize the placement of the VLSI by applying the genetic algorithm, to minimize empty space, thereby reducing the size of the site for placement. The principal difference from the known algorithms in the use of new genetic operators: segregation, cross-switching. The results of the work are confirmed by an experiment conducted on test functions for optimization algorithms. Based on the experiments performed, it should be noted that such an algorithm has the best performance when optimizing the VLSI layout. The placement area decreased from 9.14 μm2 to 7.56 μm2. The practical applicability of this algorithm is relevant in search and optimization problems.