HARDWARE IMPLEMENTATION OF THE OPTIMAL LDPC DECODER
Low Density Parity Check (LDPC) codes become more useful in modern infocommunication systems because of their error-correcting capability. At the present time, LDPC codes have reached Shannon’s limit. Moreover, the application of such codes unlike the turbo codes don’t have any license limitations. These factors have become the cause of growing interest to LDPC codes. Despite an easy way of the codec implementation, soft decoding of LDPC codes is a complex computational process. This article deals in more detail with the main problems concerning the hardware implementation of LDPC decoder and the ways of their solving. It also demonstrates the simulation results of different ways to decoder implementation and the comparison of these ways. Furthermore, the article presents the method of LDPC codes list decoding that reduces materially computational load on decoder and speeds up its work operation. The use of various procedures and mechanisms described in the article will help to generate the optimal LDPC code decoder designed for a certain task.