// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module image_filter_FAST_t_opr (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        p_src_rows_V_read,
        p_src_cols_V_read,
        p_src_data_stream_V_dout,
        p_src_data_stream_V_empty_n,
        p_src_data_stream_V_read,
        p_mask_data_stream_V_din,
        p_mask_data_stream_V_full_n,
        p_mask_data_stream_V_write
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 4'b1;
parameter    ap_ST_st2_fsm_1 = 4'b10;
parameter    ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter    ap_ST_st39_fsm_3 = 4'b1000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv1_0 = 1'b0;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv11_0 = 11'b00000000000;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv8_0 = 8'b00000000;
parameter    ap_const_lv11_4 = 11'b100;
parameter    ap_const_lv11_1 = 11'b1;
parameter    ap_const_lv11_5 = 11'b101;
parameter    ap_const_lv11_6 = 11'b110;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv9_0 = 9'b000000000;
parameter    ap_const_lv9_14 = 9'b10100;
parameter    ap_const_lv9_1EC = 9'b111101100;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv2_2 = 2'b10;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv4_8 = 4'b1000;
parameter    ap_const_lv4_9 = 4'b1001;
parameter    ap_const_lv4_6 = 4'b110;
parameter    ap_const_lv4_7 = 4'b111;
parameter    ap_const_lv4_4 = 4'b100;
parameter    ap_const_lv4_5 = 4'b101;
parameter    ap_const_lv4_2 = 4'b10;
parameter    ap_const_lv4_3 = 4'b11;
parameter    ap_const_lv4_1 = 4'b1;
parameter    ap_const_lv5_1 = 5'b1;
parameter    ap_const_lv5_8 = 5'b1000;
parameter    ap_const_lv5_2 = 5'b10;
parameter    ap_const_lv32_14 = 32'b10100;
parameter    ap_const_lv8_14 = 8'b10100;
parameter    ap_const_lv32_FFFFFFEC = 32'b11111111111111111111111111101100;
parameter    ap_const_lv8_FF = 8'b11111111;
parameter    ap_const_lv16_0 = 16'b0000000000000000;
parameter    ap_true = 1'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [11:0] p_src_rows_V_read;
input  [11:0] p_src_cols_V_read;
input  [7:0] p_src_data_stream_V_dout;
input   p_src_data_stream_V_empty_n;
output   p_src_data_stream_V_read;
output  [7:0] p_mask_data_stream_V_din;
input   p_mask_data_stream_V_full_n;
output   p_mask_data_stream_V_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_data_stream_V_read;
reg p_mask_data_stream_V_write;
reg    ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg   [3:0] ap_CS_fsm = 4'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_23;
reg   [10:0] p_2_reg_515;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it1;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg    ap_sig_bdd_48;
reg    ap_reg_ppiten_pp0_it0 = 1'b0;
reg   [0:0] exitcond_reg_5147;
reg   [0:0] or_cond_reg_5156;
reg    ap_sig_bdd_61;
reg    ap_reg_ppiten_pp0_it1 = 1'b0;
reg    ap_reg_ppiten_pp0_it2 = 1'b0;
reg    ap_reg_ppiten_pp0_it3 = 1'b0;
reg    ap_reg_ppiten_pp0_it4 = 1'b0;
reg    ap_reg_ppiten_pp0_it5 = 1'b0;
reg    ap_reg_ppiten_pp0_it6 = 1'b0;
reg    ap_reg_ppiten_pp0_it7 = 1'b0;
reg    ap_reg_ppiten_pp0_it8 = 1'b0;
reg    ap_reg_ppiten_pp0_it9 = 1'b0;
reg    ap_reg_ppiten_pp0_it10 = 1'b0;
reg    ap_reg_ppiten_pp0_it11 = 1'b0;
reg    ap_reg_ppiten_pp0_it12 = 1'b0;
reg    ap_reg_ppiten_pp0_it13 = 1'b0;
reg    ap_reg_ppiten_pp0_it14 = 1'b0;
reg    ap_reg_ppiten_pp0_it15 = 1'b0;
reg    ap_reg_ppiten_pp0_it16 = 1'b0;
reg    ap_reg_ppiten_pp0_it17 = 1'b0;
reg    ap_reg_ppiten_pp0_it18 = 1'b0;
reg    ap_reg_ppiten_pp0_it19 = 1'b0;
reg    ap_reg_ppiten_pp0_it20 = 1'b0;
reg    ap_reg_ppiten_pp0_it21 = 1'b0;
reg    ap_reg_ppiten_pp0_it22 = 1'b0;
reg    ap_reg_ppiten_pp0_it23 = 1'b0;
reg    ap_reg_ppiten_pp0_it24 = 1'b0;
reg    ap_reg_ppiten_pp0_it25 = 1'b0;
reg    ap_reg_ppiten_pp0_it26 = 1'b0;
reg    ap_reg_ppiten_pp0_it27 = 1'b0;
reg    ap_reg_ppiten_pp0_it28 = 1'b0;
reg    ap_reg_ppiten_pp0_it29 = 1'b0;
reg    ap_reg_ppiten_pp0_it30 = 1'b0;
reg    ap_reg_ppiten_pp0_it31 = 1'b0;
reg    ap_reg_ppiten_pp0_it32 = 1'b0;
reg    ap_reg_ppiten_pp0_it33 = 1'b0;
reg    ap_reg_ppiten_pp0_it34 = 1'b0;
reg   [0:0] or_cond4_reg_5201;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it34;
reg    ap_sig_bdd_136;
reg    ap_reg_ppiten_pp0_it35 = 1'b0;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it2;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it3;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it4;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it5;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it6;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it7;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it8;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it9;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it10;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it11;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it12;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it13;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it14;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it15;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it16;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it17;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it18;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it19;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it20;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it21;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it22;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it23;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it24;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it25;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it26;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it27;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it28;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it29;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it30;
reg   [10:0] ap_reg_ppstg_p_2_reg_515_pp0_it31;
wire   [10:0] tmp_fu_782_p1;
reg   [10:0] tmp_reg_5098;
reg    ap_sig_bdd_180;
wire   [10:0] tmp_15_fu_786_p1;
reg   [10:0] tmp_15_reg_5103;
wire   [10:0] tmp_s_fu_790_p2;
reg   [10:0] tmp_s_reg_5108;
wire   [10:0] tmp_5_fu_796_p2;
reg   [10:0] tmp_5_reg_5113;
wire   [0:0] exitcond1_fu_802_p2;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_196;
wire   [10:0] i_V_fu_807_p2;
reg   [10:0] i_V_reg_5122;
wire   [0:0] tmp_7_fu_813_p2;
reg   [0:0] tmp_7_reg_5127;
wire   [0:0] tmp_8_fu_818_p2;
reg   [0:0] tmp_8_reg_5132;
wire   [0:0] tmp_9_fu_824_p2;
reg   [0:0] tmp_9_reg_5137;
wire   [0:0] icmp_fu_840_p2;
reg   [0:0] icmp_reg_5142;
wire   [0:0] exitcond_fu_846_p2;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
reg   [0:0] ap_reg_ppstg_exitcond_reg_5147_pp0_it33;
wire   [10:0] j_V_fu_851_p2;
reg   [10:0] j_V_reg_5151;
wire   [0:0] or_cond_fu_862_p2;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
reg   [0:0] ap_reg_ppstg_or_cond_reg_5156_pp0_it33;
reg   [10:0] k_buf_val_0_V_addr_reg_5161;
reg   [10:0] k_buf_val_1_V_addr_reg_5167;
reg   [10:0] k_buf_val_2_V_addr_reg_5173;
reg   [10:0] k_buf_val_3_V_addr_reg_5179;
reg   [10:0] k_buf_val_4_V_addr_reg_5185;
reg   [10:0] k_buf_val_5_V_addr_reg_5191;
wire   [0:0] or_cond1_fu_883_p2;
reg   [0:0] or_cond1_reg_5197;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
reg   [0:0] ap_reg_ppstg_or_cond1_reg_5197_pp0_it32;
wire   [0:0] or_cond4_fu_904_p2;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
reg   [0:0] ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
reg   [7:0] win_val_0_V_2_1_reg_5205;
reg   [7:0] win_val_1_V_4_3_reg_5210;
reg   [7:0] win_val_2_V_5_3_reg_5215;
reg   [7:0] win_val_3_V_2_3_reg_5220;
reg   [7:0] win_val_4_V_5_3_reg_5225;
reg   [7:0] win_val_5_V_4_3_reg_5230;
reg   [7:0] win_val_6_V_2_2_reg_5235;
wire   [8:0] lhs_V_fu_1252_p1;
reg   [8:0] lhs_V_reg_5240;
wire   [8:0] r_V_fu_1260_p2;
reg   [8:0] r_V_reg_5252;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_reg_5252_pp0_it14;
wire   [1:0] phitmp1_fu_1278_p3;
reg   [1:0] phitmp1_reg_5261;
wire   [0:0] tmp_20_fu_1286_p2;
reg   [0:0] tmp_20_reg_5266;
wire   [8:0] r_V_s_fu_1296_p2;
reg   [8:0] r_V_s_reg_5271;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_s_reg_5271_pp0_it23;
wire   [1:0] phitmp_1_fu_1314_p3;
reg   [1:0] phitmp_1_reg_5280;
wire   [0:0] tmp_24_fu_1322_p2;
reg   [0:0] tmp_24_reg_5285;
wire   [8:0] r_V_2_fu_1332_p2;
reg   [8:0] r_V_2_reg_5290;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_2_reg_5290_pp0_it16;
wire   [1:0] phitmp_2_fu_1350_p3;
reg   [1:0] phitmp_2_reg_5299;
wire   [0:0] tmp_27_fu_1358_p2;
reg   [0:0] tmp_27_reg_5304;
wire   [8:0] r_V_3_fu_1368_p2;
reg   [8:0] r_V_3_reg_5309;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
reg   [8:0] ap_reg_ppstg_r_V_3_reg_5309_pp0_it25;
wire   [1:0] phitmp_3_fu_1386_p3;
reg   [1:0] phitmp_3_reg_5318;
wire   [0:0] tmp_29_fu_1394_p2;
reg   [0:0] tmp_29_reg_5323;
wire   [8:0] r_V_4_fu_1404_p2;
reg   [8:0] r_V_4_reg_5328;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_4_reg_5328_pp0_it18;
wire   [0:0] tmp_176_4_fu_1410_p2;
reg   [0:0] tmp_176_4_reg_5337;
wire   [0:0] tmp_177_4_fu_1416_p2;
reg   [0:0] tmp_177_4_reg_5343;
wire   [8:0] r_V_5_fu_1426_p2;
reg   [8:0] r_V_5_reg_5348;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
reg   [8:0] ap_reg_ppstg_r_V_5_reg_5348_pp0_it27;
wire   [0:0] tmp_176_5_fu_1432_p2;
reg   [0:0] tmp_176_5_reg_5357;
wire   [0:0] tmp_177_5_fu_1438_p2;
reg   [0:0] tmp_177_5_reg_5363;
wire   [8:0] r_V_6_fu_1448_p2;
reg   [8:0] r_V_6_reg_5368;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_6_reg_5368_pp0_it20;
wire   [0:0] tmp_176_6_fu_1454_p2;
reg   [0:0] tmp_176_6_reg_5377;
wire   [0:0] tmp_177_6_fu_1460_p2;
reg   [0:0] tmp_177_6_reg_5383;
wire   [8:0] r_V_7_fu_1470_p2;
reg   [8:0] r_V_7_reg_5388;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
reg   [8:0] ap_reg_ppstg_r_V_7_reg_5388_pp0_it29;
wire   [0:0] tmp_176_7_fu_1476_p2;
reg   [0:0] tmp_176_7_reg_5397;
wire   [0:0] tmp_177_7_fu_1482_p2;
reg   [0:0] tmp_177_7_reg_5403;
wire   [8:0] r_V_1_fu_1516_p2;
reg   [8:0] r_V_1_reg_5408;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_1_reg_5408_pp0_it22;
wire   [1:0] flag_val_V_assign_load_1_s_fu_1521_p3;
reg   [1:0] flag_val_V_assign_load_1_s_reg_5417;
reg   [1:0] ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
reg   [1:0] ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5;
wire   [1:0] phitmp3_fu_1539_p3;
reg   [1:0] phitmp3_reg_5422;
wire   [0:0] tmp_23_fu_1547_p2;
reg   [0:0] tmp_23_reg_5427;
wire   [8:0] r_V_1_1_fu_1557_p2;
reg   [8:0] r_V_1_1_reg_5432;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15;
wire   [0:0] tmp_182_1_fu_1568_p2;
reg   [0:0] tmp_182_1_reg_5441;
wire   [0:0] tmp_184_1_fu_1574_p2;
reg   [0:0] tmp_184_1_reg_5447;
wire   [8:0] r_V_1_2_fu_1584_p2;
reg   [8:0] r_V_1_2_reg_5452;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24;
wire   [0:0] tmp_182_2_fu_1595_p2;
reg   [0:0] tmp_182_2_reg_5461;
wire   [0:0] tmp_184_2_fu_1601_p2;
reg   [0:0] tmp_184_2_reg_5467;
wire   [8:0] r_V_1_3_fu_1611_p2;
reg   [8:0] r_V_1_3_reg_5472;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17;
wire   [8:0] r_V_1_4_fu_1626_p2;
reg   [8:0] r_V_1_4_reg_5483;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
reg   [8:0] ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26;
wire   [8:0] r_V_1_5_fu_1654_p2;
reg   [8:0] r_V_1_5_reg_5494;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19;
wire   [8:0] r_V_1_6_fu_1682_p2;
reg   [8:0] r_V_1_6_reg_5505;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
reg   [8:0] ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28;
wire   [8:0] r_V_1_7_fu_1710_p2;
reg   [8:0] r_V_1_7_reg_5516;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
reg   [8:0] ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21;
wire   [1:0] flag_val_V_assign_load_1_13_fu_1726_p3;
reg   [1:0] flag_val_V_assign_load_1_13_reg_5527;
wire   [0:0] tmp_39_fu_1740_p2;
reg   [0:0] tmp_39_reg_5532;
reg   [0:0] ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_39_reg_5532_pp0_it5;
wire   [0:0] or_cond5_fu_1746_p2;
reg   [0:0] or_cond5_reg_5537;
reg   [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond5_reg_5537_pp0_it7;
wire   [0:0] or_cond6_fu_1764_p2;
reg   [0:0] or_cond6_reg_5543;
reg   [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond6_reg_5543_pp0_it7;
wire   [0:0] or_cond7_fu_1782_p2;
reg   [0:0] or_cond7_reg_5548;
reg   [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond7_reg_5548_pp0_it7;
wire   [0:0] or_cond8_fu_1800_p2;
reg   [0:0] or_cond8_reg_5553;
reg   [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond8_reg_5553_pp0_it8;
wire   [0:0] or_cond9_fu_1818_p2;
reg   [0:0] or_cond9_reg_5559;
reg   [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond9_reg_5559_pp0_it8;
wire   [0:0] tmp_181_5_not_fu_1824_p2;
reg   [0:0] tmp_181_5_not_reg_5566;
wire   [0:0] tmp_183_5_fu_1830_p2;
reg   [0:0] tmp_183_5_reg_5572;
wire   [0:0] tmp_181_6_not_fu_1836_p2;
reg   [0:0] tmp_181_6_not_reg_5578;
wire   [0:0] tmp_183_6_fu_1842_p2;
reg   [0:0] tmp_183_6_reg_5584;
wire   [3:0] count_1_i_0_op_op87_op_fu_1848_p3;
reg   [3:0] count_1_i_0_op_op87_op_reg_5590;
wire   [3:0] phitmp43_op_op_cast_cast_cast_fu_1856_p3;
reg   [3:0] phitmp43_op_op_cast_cast_cast_reg_5595;
wire   [0:0] tmp_40_fu_1864_p2;
reg   [0:0] tmp_40_reg_5600;
wire   [0:0] not_or_cond6_demorgan_fu_1870_p2;
reg   [0:0] not_or_cond6_demorgan_reg_5605;
reg   [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
reg   [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7;
wire   [0:0] not_or_cond7_demorgan_fu_1876_p2;
reg   [0:0] not_or_cond7_demorgan_reg_5610;
reg   [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
reg   [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8;
wire   [0:0] not_or_cond8_demorgan_fu_1882_p2;
reg   [0:0] not_or_cond8_demorgan_reg_5615;
reg   [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
reg   [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8;
wire   [0:0] not_or_cond9_demorgan_fu_1888_p2;
reg   [0:0] not_or_cond9_demorgan_reg_5620;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
reg   [0:0] ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9;
wire   [1:0] flag_val_V_assign_load_1_3_fu_1930_p3;
reg   [1:0] flag_val_V_assign_load_1_3_reg_5625;
wire   [1:0] flag_val_V_assign_load_1_5_fu_1962_p3;
reg   [1:0] flag_val_V_assign_load_1_5_reg_5631;
wire   [0:0] tmp_182_4_fu_1970_p2;
reg   [0:0] tmp_182_4_reg_5638;
wire   [0:0] tmp_184_4_fu_1975_p2;
reg   [0:0] tmp_184_4_reg_5644;
wire   [0:0] tmp_182_5_fu_1980_p2;
reg   [0:0] tmp_182_5_reg_5649;
wire   [0:0] tmp_184_5_fu_1985_p2;
reg   [0:0] tmp_184_5_reg_5655;
wire   [0:0] or_cond2_fu_1990_p2;
reg   [0:0] or_cond2_reg_5660;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_5660_pp0_it9;
wire   [3:0] count_1_i_6_fu_2036_p3;
reg   [3:0] count_1_i_6_reg_5665;
wire   [0:0] or_cond10_fu_2055_p2;
reg   [0:0] or_cond10_reg_5670;
wire   [3:0] count_1_i_7_fu_2061_p3;
reg   [3:0] count_1_i_7_reg_5675;
wire   [0:0] or_cond11_fu_2075_p2;
reg   [0:0] or_cond11_reg_5681;
wire   [0:0] tmp_181_9_fu_2081_p2;
reg   [0:0] tmp_181_9_reg_5687;
wire   [0:0] tmp_183_9_fu_2087_p2;
reg   [0:0] tmp_183_9_reg_5693;
wire   [0:0] not_or_cond10_demorgan_fu_2093_p2;
reg   [0:0] not_or_cond10_demorgan_reg_5699;
reg   [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
reg   [0:0] ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9;
wire   [0:0] not_or_cond11_demorgan_fu_2097_p2;
reg   [0:0] not_or_cond11_demorgan_reg_5704;
reg   [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
reg   [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
reg   [0:0] ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9;
wire   [1:0] flag_val_V_assign_load_1_10_fu_2131_p3;
reg   [1:0] flag_val_V_assign_load_1_10_reg_5709;
wire   [1:0] flag_val_V_assign_load_1_12_fu_2163_p3;
reg   [1:0] flag_val_V_assign_load_1_12_reg_5715;
wire   [0:0] tmp_182_7_fu_2171_p2;
reg   [0:0] tmp_182_7_reg_5722;
wire   [0:0] tmp_184_7_fu_2176_p2;
reg   [0:0] tmp_184_7_reg_5728;
wire   [0:0] not_or_cond_fu_2186_p2;
reg   [0:0] not_or_cond_reg_5733;
reg   [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
reg   [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
reg   [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
reg   [0:0] ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9;
wire   [0:0] p_iscorner_0_i_9_fu_2251_p2;
reg   [0:0] p_iscorner_0_i_9_reg_5738;
wire   [3:0] count_1_i_9_fu_2257_p3;
reg   [3:0] count_1_i_9_reg_5743;
wire   [0:0] not_or_cond3_demorgan_fu_2286_p2;
reg   [0:0] not_or_cond3_demorgan_reg_5748;
wire   [3:0] count_1_i_s_fu_2292_p3;
reg   [3:0] count_1_i_s_reg_5753;
wire   [0:0] or_cond14_fu_2310_p2;
reg   [0:0] or_cond14_reg_5759;
wire   [0:0] not_or_cond4_demorgan_fu_2316_p2;
reg   [0:0] not_or_cond4_demorgan_reg_5764;
wire   [0:0] tmp_181_2_fu_2322_p2;
reg   [0:0] tmp_181_2_reg_5769;
wire   [0:0] tmp_183_10_fu_2328_p2;
reg   [0:0] tmp_183_10_reg_5775;
wire   [0:0] tmp5_fu_2334_p2;
reg   [0:0] tmp5_reg_5781;
reg   [0:0] ap_reg_ppstg_tmp5_reg_5781_pp0_it6;
wire   [0:0] p_iscorner_0_i_1_fu_2391_p2;
reg   [0:0] p_iscorner_0_i_1_reg_5786;
wire   [0:0] p_iscorner_0_i_2_fu_2435_p2;
reg   [0:0] p_iscorner_0_i_2_reg_5791;
wire   [0:0] tmp_185_3_fu_2464_p2;
reg   [0:0] tmp_185_3_reg_5796;
wire   [0:0] not_or_cond13_demorgan_fu_2470_p2;
reg   [0:0] not_or_cond13_demorgan_reg_5801;
wire   [3:0] count_1_i_3_fu_2476_p3;
reg   [3:0] count_1_i_3_reg_5806;
wire   [0:0] or_cond17_fu_2494_p2;
reg   [0:0] or_cond17_reg_5811;
wire   [0:0] not_or_cond14_demorgan_fu_2500_p2;
reg   [0:0] not_or_cond14_demorgan_reg_5816;
wire   [0:0] or_cond18_fu_2511_p2;
reg   [0:0] or_cond18_reg_5821;
wire   [0:0] tmp6_fu_2516_p2;
reg   [0:0] tmp6_reg_5827;
wire   [0:0] p_iscorner_0_i_5_fu_2581_p2;
reg   [0:0] p_iscorner_0_i_5_reg_5832;
wire   [4:0] count_3_fu_2594_p2;
reg   [4:0] count_3_reg_5837;
wire   [4:0] phitmp8_fu_2600_p2;
reg   [4:0] phitmp8_reg_5842;
wire   [0:0] tmp4_fu_2606_p2;
reg   [0:0] tmp4_reg_5847;
wire   [0:0] tmp8_fu_2610_p2;
reg   [0:0] tmp8_reg_5852;
wire   [0:0] tmp9_fu_2614_p2;
reg   [0:0] tmp9_reg_5857;
wire   [0:0] p_iscorner_0_i_7_fu_2653_p2;
reg   [0:0] p_iscorner_0_i_7_reg_5862;
wire   [4:0] count_4_fu_2666_p2;
reg   [4:0] count_4_reg_5867;
wire   [4:0] count_1_i_12_fu_2678_p3;
reg   [4:0] count_1_i_12_reg_5872;
wire   [0:0] tmp3_fu_2689_p2;
reg   [0:0] tmp3_reg_5878;
reg   [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
reg   [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
reg   [0:0] ap_reg_ppstg_tmp3_reg_5878_pp0_it11;
wire   [0:0] tmp12_fu_2694_p2;
reg   [0:0] tmp12_reg_5883;
reg   [0:0] ap_reg_ppstg_tmp12_reg_5883_pp0_it9;
wire   [0:0] p_iscorner_0_i_11_fu_2725_p2;
reg   [0:0] p_iscorner_0_i_11_reg_5888;
wire   [0:0] tmp_185_13_fu_2743_p2;
reg   [0:0] tmp_185_13_reg_5893;
wire   [4:0] count_1_i_14_fu_2755_p3;
reg   [4:0] count_1_i_14_reg_5898;
wire   [0:0] tmp13_fu_2762_p2;
reg   [0:0] tmp13_reg_5904;
wire   [0:0] p_iscorner_0_i_13_fu_2787_p2;
reg   [0:0] p_iscorner_0_i_13_reg_5909;
wire   [0:0] tmp_185_15_fu_2805_p2;
reg   [0:0] tmp_185_15_reg_5914;
wire   [0:0] not_or_cond11_fu_2817_p2;
reg   [0:0] not_or_cond11_reg_5919;
wire   [0:0] tmp_185_16_fu_2822_p2;
reg   [0:0] tmp_185_16_reg_5924;
wire   [0:0] tmp2_fu_2828_p2;
reg   [0:0] tmp2_reg_5929;
wire   [0:0] tmp11_fu_2833_p2;
reg   [0:0] tmp11_reg_5934;
reg   [0:0] ap_reg_ppstg_tmp11_reg_5934_pp0_it11;
wire   [0:0] tmp15_fu_2837_p2;
reg   [0:0] tmp15_reg_5939;
wire   [0:0] tmp14_fu_2861_p2;
reg   [0:0] tmp14_reg_5944;
wire   [0:0] iscorner_2_i_s_fu_2870_p2;
reg   [0:0] iscorner_2_i_s_reg_5949;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
reg   [0:0] ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32;
wire   [31:0] grp_image_filter_reg_int_s_fu_542_ap_return;
reg   [31:0] flag_d_min2_1_reg_5953;
reg   [31:0] ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
reg   [31:0] ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15;
wire   [31:0] grp_image_filter_reg_int_s_fu_547_ap_return;
reg   [31:0] flag_d_max2_1_reg_5959;
reg   [31:0] ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
reg   [31:0] ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15;
wire   [31:0] grp_image_filter_reg_int_s_fu_572_ap_return;
reg   [31:0] flag_d_min2_7_reg_5965;
reg   [31:0] ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14;
wire   [31:0] grp_image_filter_reg_int_s_fu_577_ap_return;
reg   [31:0] flag_d_max2_7_reg_5971;
reg   [31:0] ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14;
wire   [31:0] tmp_200_3_fu_3031_p3;
reg   [31:0] tmp_200_3_reg_5977;
reg   [31:0] ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
wire   [31:0] tmp_213_3_fu_3045_p3;
reg   [31:0] tmp_213_3_reg_5982;
reg   [31:0] ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
wire   [31:0] grp_image_filter_reg_int_s_fu_582_ap_return;
reg   [31:0] flag_d_min4_1_reg_5987;
reg   [31:0] ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
reg   [31:0] ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16;
wire   [31:0] grp_image_filter_reg_int_s_fu_587_ap_return;
reg   [31:0] flag_d_max4_1_reg_5993;
reg   [31:0] ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
reg   [31:0] ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16;
wire   [31:0] grp_image_filter_reg_int_s_fu_592_ap_return;
reg   [31:0] flag_d_min4_5_reg_5999;
reg   [31:0] ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
reg   [31:0] ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16;
wire   [31:0] grp_image_filter_reg_int_s_fu_597_ap_return;
reg   [31:0] flag_d_max4_5_reg_6005;
reg   [31:0] ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
reg   [31:0] ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16;
wire  signed [31:0] flag_d_assign_fu_3143_p1;
reg  signed [31:0] flag_d_assign_reg_6011;
wire   [31:0] grp_image_filter_reg_int_s_fu_602_ap_return;
reg   [31:0] flag_d_min2_9_reg_6017;
wire   [31:0] grp_image_filter_reg_int_s_fu_607_ap_return;
reg   [31:0] flag_d_max2_9_reg_6023;
wire   [31:0] grp_image_filter_reg_int_s_fu_612_ap_return;
reg   [31:0] flag_d_min8_1_reg_6029;
wire   [31:0] grp_image_filter_reg_int_s_fu_617_ap_return;
reg   [31:0] flag_d_max8_1_reg_6036;
wire   [0:0] tmp_43_fu_3262_p2;
reg   [0:0] tmp_43_reg_6043;
wire   [0:0] tmp_67_fu_3268_p2;
reg   [0:0] tmp_67_reg_6048;
wire   [31:0] grp_image_filter_reg_int_s_fu_652_ap_return;
reg   [31:0] flag_d_min4_3_reg_6053;
wire   [31:0] grp_image_filter_reg_int_s_fu_657_ap_return;
reg   [31:0] flag_d_max4_3_reg_6059;
wire   [31:0] grp_image_filter_reg_int_s_fu_662_ap_return;
reg   [31:0] flag_d_min4_7_reg_6065;
wire   [31:0] grp_image_filter_reg_int_s_fu_667_ap_return;
reg   [31:0] flag_d_max4_7_reg_6071;
wire   [7:0] p_a_0_flag_d_assign_load_5_fu_3434_p3;
reg   [7:0] p_a_0_flag_d_assign_load_5_reg_6077;
wire   [31:0] tmp_47_fu_3447_p3;
reg   [31:0] tmp_47_reg_6083;
wire   [7:0] tmp_48_fu_3454_p1;
reg   [7:0] tmp_48_reg_6088;
wire   [8:0] b0_fu_3473_p3;
reg   [8:0] b0_reg_6093;
wire   [31:0] tmp_71_fu_3486_p3;
reg   [31:0] tmp_71_reg_6099;
wire   [8:0] tmp_81_fu_3493_p1;
reg   [8:0] tmp_81_reg_6104;
wire  signed [31:0] flag_d_assign_2_fu_3497_p1;
reg  signed [31:0] flag_d_assign_2_reg_6109;
wire   [31:0] grp_image_filter_reg_int_s_fu_712_ap_return;
reg   [31:0] flag_d_min8_3_reg_6115;
wire   [31:0] grp_image_filter_reg_int_s_fu_717_ap_return;
reg   [31:0] flag_d_max8_3_reg_6122;
wire   [31:0] tmp_210_5_fu_3505_p3;
reg   [31:0] tmp_210_5_reg_6129;
wire   [31:0] tmp_225_5_fu_3517_p3;
reg   [31:0] tmp_225_5_reg_6134;
wire   [31:0] tmp_210_7_fu_3529_p3;
reg   [31:0] tmp_210_7_reg_6139;
reg   [31:0] ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
wire   [31:0] tmp_225_7_fu_3541_p3;
reg   [31:0] tmp_225_7_reg_6144;
reg   [31:0] ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
wire   [31:0] tmp_210_9_fu_3554_p3;
reg   [31:0] tmp_210_9_reg_6149;
reg   [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
wire   [31:0] tmp_225_9_fu_3568_p3;
reg   [31:0] tmp_225_9_reg_6154;
reg   [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
wire   [31:0] tmp_210_s_fu_3582_p3;
reg   [31:0] tmp_210_s_reg_6159;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
wire   [31:0] tmp_225_s_fu_3596_p3;
reg   [31:0] tmp_225_s_reg_6164;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
wire   [31:0] tmp_210_2_fu_3609_p3;
reg   [31:0] tmp_210_2_reg_6169;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
reg   [31:0] ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
wire   [31:0] tmp_225_2_fu_3621_p3;
reg   [31:0] tmp_225_2_reg_6174;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
reg   [31:0] ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
wire   [31:0] tmp_210_4_fu_3633_p3;
reg   [31:0] tmp_210_4_reg_6179;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
reg   [31:0] ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
wire   [31:0] tmp_225_4_fu_3645_p3;
reg   [31:0] tmp_225_4_reg_6184;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
reg   [31:0] ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
wire   [7:0] p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
reg   [7:0] p_a_0_flag_d_assign_load_5_tmp_s_reg_6189;
wire   [0:0] tmp_209_1_fu_3666_p2;
reg   [0:0] tmp_209_1_reg_6195;
wire   [8:0] b0_tmp_s_fu_3680_p3;
reg   [8:0] b0_tmp_s_reg_6200;
wire   [0:0] tmp_221_1_fu_3686_p2;
reg   [0:0] tmp_221_1_reg_6206;
wire   [7:0] a0_s_fu_3713_p3;
reg   [7:0] a0_s_reg_6211;
wire   [31:0] tmp_232_1_fu_3725_p3;
reg   [31:0] tmp_232_1_reg_6217;
wire   [7:0] tmp_57_fu_3732_p1;
reg   [7:0] tmp_57_reg_6222;
wire   [8:0] b0_s_fu_3754_p3;
reg   [8:0] b0_s_reg_6227;
wire   [31:0] tmp_239_1_fu_3766_p3;
reg   [31:0] tmp_239_1_reg_6233;
wire   [8:0] tmp_83_fu_3773_p1;
reg   [8:0] tmp_83_reg_6238;
wire  signed [31:0] flag_d_assign_4_fu_3777_p1;
reg  signed [31:0] flag_d_assign_4_reg_6243;
wire   [31:0] grp_image_filter_reg_int_s_fu_722_ap_return;
reg   [31:0] flag_d_min8_5_reg_6249;
wire   [31:0] grp_image_filter_reg_int_s_fu_727_ap_return;
reg   [31:0] flag_d_max8_5_reg_6256;
wire   [7:0] a0_tmp_232_1_fu_3788_p3;
reg   [7:0] a0_tmp_232_1_reg_6263;
wire   [0:0] tmp_209_2_fu_3794_p2;
reg   [0:0] tmp_209_2_reg_6269;
wire   [8:0] b0_tmp_239_1_fu_3808_p3;
reg   [8:0] b0_tmp_239_1_reg_6274;
wire   [0:0] tmp_221_2_fu_3814_p2;
reg   [0:0] tmp_221_2_reg_6280;
wire   [7:0] a0_2_fu_3841_p3;
reg   [7:0] a0_2_reg_6285;
wire   [31:0] tmp_232_2_fu_3853_p3;
reg   [31:0] tmp_232_2_reg_6291;
wire   [7:0] tmp_59_fu_3860_p1;
reg   [7:0] tmp_59_reg_6296;
wire   [8:0] b0_2_fu_3882_p3;
reg   [8:0] b0_2_reg_6301;
wire   [31:0] tmp_239_2_fu_3894_p3;
reg   [31:0] tmp_239_2_reg_6307;
wire   [8:0] tmp_85_fu_3901_p1;
reg   [8:0] tmp_85_reg_6312;
wire  signed [31:0] flag_d_assign_6_fu_3905_p1;
reg  signed [31:0] flag_d_assign_6_reg_6317;
wire   [31:0] grp_image_filter_reg_int_s_fu_732_ap_return;
reg   [31:0] flag_d_min8_7_reg_6323;
wire   [31:0] grp_image_filter_reg_int_s_fu_737_ap_return;
reg   [31:0] flag_d_max8_7_reg_6330;
wire   [7:0] a0_2_tmp_232_2_fu_3916_p3;
reg   [7:0] a0_2_tmp_232_2_reg_6337;
wire   [0:0] tmp_209_3_fu_3922_p2;
reg   [0:0] tmp_209_3_reg_6343;
wire   [8:0] b0_2_tmp_239_2_fu_3936_p3;
reg   [8:0] b0_2_tmp_239_2_reg_6348;
wire   [0:0] tmp_221_3_fu_3942_p2;
reg   [0:0] tmp_221_3_reg_6354;
wire   [7:0] a0_3_fu_3969_p3;
reg   [7:0] a0_3_reg_6359;
wire   [31:0] tmp_232_3_fu_3981_p3;
reg   [31:0] tmp_232_3_reg_6365;
wire   [7:0] tmp_61_fu_3988_p1;
reg   [7:0] tmp_61_reg_6370;
wire   [8:0] b0_3_fu_4010_p3;
reg   [8:0] b0_3_reg_6375;
wire   [31:0] tmp_239_3_fu_4022_p3;
reg   [31:0] tmp_239_3_reg_6381;
wire   [8:0] tmp_87_fu_4029_p1;
reg   [8:0] tmp_87_reg_6386;
wire  signed [31:0] flag_d_assign_8_fu_4033_p1;
reg  signed [31:0] flag_d_assign_8_reg_6391;
wire   [31:0] grp_image_filter_reg_int_s_fu_742_ap_return;
reg   [31:0] flag_d_min8_9_reg_6397;
wire   [31:0] grp_image_filter_reg_int_s_fu_747_ap_return;
reg   [31:0] flag_d_max8_9_reg_6404;
wire   [7:0] a0_3_tmp_232_3_fu_4044_p3;
reg   [7:0] a0_3_tmp_232_3_reg_6411;
wire   [0:0] tmp_209_4_fu_4050_p2;
reg   [0:0] tmp_209_4_reg_6417;
wire   [8:0] b0_3_tmp_239_3_fu_4064_p3;
reg   [8:0] b0_3_tmp_239_3_reg_6422;
wire   [0:0] tmp_221_4_fu_4070_p2;
reg   [0:0] tmp_221_4_reg_6428;
wire   [7:0] a0_4_fu_4097_p3;
reg   [7:0] a0_4_reg_6433;
wire   [31:0] tmp_232_4_fu_4109_p3;
reg   [31:0] tmp_232_4_reg_6439;
wire   [7:0] tmp_63_fu_4116_p1;
reg   [7:0] tmp_63_reg_6444;
wire   [8:0] b0_4_fu_4138_p3;
reg   [8:0] b0_4_reg_6449;
wire   [31:0] tmp_239_4_fu_4150_p3;
reg   [31:0] tmp_239_4_reg_6455;
wire   [8:0] tmp_89_fu_4157_p1;
reg   [8:0] tmp_89_reg_6460;
wire  signed [31:0] flag_d_assign_s_fu_4161_p1;
reg  signed [31:0] flag_d_assign_s_reg_6465;
wire   [31:0] grp_image_filter_reg_int_s_fu_752_ap_return;
reg   [31:0] tmp_211_s_reg_6471;
wire   [31:0] grp_image_filter_reg_int_s_fu_757_ap_return;
reg   [31:0] tmp_226_s_reg_6478;
wire   [7:0] a0_4_tmp_232_4_fu_4172_p3;
reg   [7:0] a0_4_tmp_232_4_reg_6485;
wire   [0:0] tmp_209_5_fu_4178_p2;
reg   [0:0] tmp_209_5_reg_6491;
wire   [8:0] b0_4_tmp_239_4_fu_4192_p3;
reg   [8:0] b0_4_tmp_239_4_reg_6496;
wire   [0:0] tmp_221_5_fu_4198_p2;
reg   [0:0] tmp_221_5_reg_6502;
wire   [7:0] a0_5_fu_4225_p3;
reg   [7:0] a0_5_reg_6507;
wire   [31:0] tmp_232_5_fu_4237_p3;
reg   [31:0] tmp_232_5_reg_6513;
wire   [7:0] tmp_65_fu_4244_p1;
reg   [7:0] tmp_65_reg_6518;
wire   [8:0] b0_5_fu_4266_p3;
reg   [8:0] b0_5_reg_6523;
wire   [31:0] tmp_239_5_fu_4278_p3;
reg   [31:0] tmp_239_5_reg_6529;
wire   [8:0] tmp_91_fu_4285_p1;
reg   [8:0] tmp_91_reg_6534;
wire  signed [31:0] flag_d_assign_11_fu_4289_p1;
reg  signed [31:0] flag_d_assign_11_reg_6539;
wire   [31:0] grp_image_filter_reg_int_s_fu_762_ap_return;
reg   [31:0] tmp_211_1_reg_6545;
wire   [31:0] grp_image_filter_reg_int_s_fu_767_ap_return;
reg   [31:0] tmp_226_1_reg_6552;
wire   [7:0] a0_5_tmp_232_5_fu_4300_p3;
reg   [7:0] a0_5_tmp_232_5_reg_6559;
wire   [0:0] tmp_209_6_fu_4306_p2;
reg   [0:0] tmp_209_6_reg_6565;
wire   [8:0] b0_5_tmp_239_5_fu_4320_p3;
reg   [8:0] b0_5_tmp_239_5_reg_6570;
wire   [0:0] tmp_221_6_fu_4326_p2;
reg   [0:0] tmp_221_6_reg_6576;
wire   [7:0] a0_6_fu_4353_p3;
reg   [7:0] a0_6_reg_6581;
wire   [31:0] tmp_232_6_fu_4365_p3;
reg   [31:0] tmp_232_6_reg_6587;
wire   [7:0] tmp_75_fu_4372_p1;
reg   [7:0] tmp_75_reg_6592;
wire   [8:0] b0_6_fu_4394_p3;
reg   [8:0] b0_6_reg_6597;
wire   [31:0] tmp_239_6_fu_4406_p3;
reg   [31:0] tmp_239_6_reg_6603;
wire   [8:0] tmp_93_fu_4413_p1;
reg   [8:0] tmp_93_reg_6608;
wire  signed [31:0] flag_d_assign_13_fu_4417_p1;
reg  signed [31:0] flag_d_assign_13_reg_6613;
wire   [31:0] grp_image_filter_reg_int_s_fu_772_ap_return;
reg   [31:0] tmp_211_2_reg_6619;
wire   [31:0] grp_image_filter_reg_int_s_fu_777_ap_return;
reg   [31:0] tmp_226_2_reg_6626;
wire   [7:0] a0_6_tmp_232_6_fu_4428_p3;
reg   [7:0] a0_6_tmp_232_6_reg_6633;
wire   [0:0] tmp_209_7_fu_4434_p2;
reg   [0:0] tmp_209_7_reg_6639;
wire   [8:0] b0_6_tmp_239_6_fu_4448_p3;
reg   [8:0] b0_6_tmp_239_6_reg_6644;
wire   [0:0] tmp_221_7_fu_4454_p2;
reg   [0:0] tmp_221_7_reg_6650;
wire   [7:0] a0_7_fu_4481_p3;
reg   [7:0] a0_7_reg_6655;
wire   [31:0] tmp_232_7_fu_4493_p3;
reg   [31:0] tmp_232_7_reg_6661;
wire   [7:0] tmp_78_fu_4500_p1;
reg   [7:0] tmp_78_reg_6666;
wire   [8:0] b0_7_fu_4522_p3;
reg   [8:0] b0_7_reg_6671;
wire   [31:0] tmp_239_7_fu_4534_p3;
reg   [31:0] tmp_239_7_reg_6676;
wire   [7:0] tmp_95_fu_4541_p1;
reg   [7:0] tmp_95_reg_6681;
wire   [7:0] tmp_96_fu_4545_p1;
reg   [7:0] tmp_96_reg_6686;
wire   [7:0] a0_7_tmp_232_7_fu_4557_p3;
reg   [7:0] a0_7_tmp_232_7_reg_6691;
wire   [7:0] tmp_79_fu_4571_p3;
reg   [7:0] tmp_79_reg_6697;
reg   [10:0] core_buf_val_0_V_addr_reg_6702;
reg   [10:0] core_buf_val_1_V_addr_reg_6708;
reg   [10:0] ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
wire   [7:0] tmp_100_v_fu_4593_p3;
reg   [7:0] tmp_100_v_reg_6714;
wire   [0:0] tmp_53_fu_4600_p2;
reg   [0:0] tmp_53_reg_6719;
reg   [0:0] ap_reg_ppstg_tmp_53_reg_6719_pp0_it33;
wire   [7:0] core_buf_val_0_V_q0;
reg   [7:0] core_buf_val_0_V_load_reg_6724;
wire   [7:0] core_buf_val_1_V_q0;
reg   [7:0] core_buf_val_1_V_load_reg_6729;
wire   [7:0] phitmp2_fu_4606_p2;
wire   [0:0] tmp19_fu_4701_p2;
reg   [0:0] tmp19_reg_6739;
wire   [0:0] tmp20_fu_4712_p2;
reg   [0:0] tmp20_reg_6744;
wire   [0:0] tmp23_fu_4723_p2;
reg   [0:0] tmp23_reg_6749;
wire   [0:0] tmp25_fu_4735_p2;
reg   [0:0] tmp25_reg_6754;
wire   [10:0] k_buf_val_0_V_address0;
reg    k_buf_val_0_V_ce0;
wire   [7:0] k_buf_val_0_V_q0;
wire   [10:0] k_buf_val_0_V_address1;
reg    k_buf_val_0_V_ce1;
reg    k_buf_val_0_V_we1;
wire   [7:0] k_buf_val_0_V_d1;
wire   [10:0] k_buf_val_1_V_address0;
reg    k_buf_val_1_V_ce0;
wire   [7:0] k_buf_val_1_V_q0;
wire   [10:0] k_buf_val_1_V_address1;
reg    k_buf_val_1_V_ce1;
reg    k_buf_val_1_V_we1;
wire   [7:0] k_buf_val_1_V_d1;
wire   [10:0] k_buf_val_2_V_address0;
reg    k_buf_val_2_V_ce0;
wire   [7:0] k_buf_val_2_V_q0;
wire   [10:0] k_buf_val_2_V_address1;
reg    k_buf_val_2_V_ce1;
reg    k_buf_val_2_V_we1;
wire   [7:0] k_buf_val_2_V_d1;
wire   [10:0] k_buf_val_3_V_address0;
reg    k_buf_val_3_V_ce0;
wire   [7:0] k_buf_val_3_V_q0;
wire   [10:0] k_buf_val_3_V_address1;
reg    k_buf_val_3_V_ce1;
reg    k_buf_val_3_V_we1;
wire   [7:0] k_buf_val_3_V_d1;
wire   [10:0] k_buf_val_4_V_address0;
reg    k_buf_val_4_V_ce0;
wire   [7:0] k_buf_val_4_V_q0;
wire   [10:0] k_buf_val_4_V_address1;
reg    k_buf_val_4_V_ce1;
reg    k_buf_val_4_V_we1;
wire   [7:0] k_buf_val_4_V_d1;
wire   [10:0] k_buf_val_5_V_address0;
reg    k_buf_val_5_V_ce0;
wire   [7:0] k_buf_val_5_V_q0;
wire   [10:0] k_buf_val_5_V_address1;
reg    k_buf_val_5_V_ce1;
reg    k_buf_val_5_V_we1;
wire   [7:0] k_buf_val_5_V_d1;
wire   [10:0] core_buf_val_0_V_address0;
reg    core_buf_val_0_V_ce0;
wire   [10:0] core_buf_val_0_V_address1;
reg    core_buf_val_0_V_ce1;
reg    core_buf_val_0_V_we1;
wire   [7:0] core_buf_val_0_V_d1;
wire   [10:0] core_buf_val_1_V_address0;
reg    core_buf_val_1_V_ce0;
wire   [10:0] core_buf_val_1_V_address1;
reg    core_buf_val_1_V_ce1;
reg    core_buf_val_1_V_we1;
wire   [7:0] core_buf_val_1_V_d1;
wire   [31:0] grp_image_filter_reg_int_s_fu_542_in_r;
reg    grp_image_filter_reg_int_s_fu_542_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_547_in_r;
reg    grp_image_filter_reg_int_s_fu_547_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_552_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_552_ap_return;
reg    grp_image_filter_reg_int_s_fu_552_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_557_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_557_ap_return;
reg    grp_image_filter_reg_int_s_fu_557_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_562_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_562_ap_return;
reg    grp_image_filter_reg_int_s_fu_562_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_567_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_567_ap_return;
reg    grp_image_filter_reg_int_s_fu_567_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_572_in_r;
reg    grp_image_filter_reg_int_s_fu_572_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_577_in_r;
reg    grp_image_filter_reg_int_s_fu_577_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_582_in_r;
reg    grp_image_filter_reg_int_s_fu_582_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_587_in_r;
reg    grp_image_filter_reg_int_s_fu_587_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_592_in_r;
reg    grp_image_filter_reg_int_s_fu_592_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_597_in_r;
reg    grp_image_filter_reg_int_s_fu_597_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_602_in_r;
reg    grp_image_filter_reg_int_s_fu_602_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_607_in_r;
reg    grp_image_filter_reg_int_s_fu_607_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_612_in_r;
reg    grp_image_filter_reg_int_s_fu_612_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_617_in_r;
reg    grp_image_filter_reg_int_s_fu_617_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_622_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_622_ap_return;
reg    grp_image_filter_reg_int_s_fu_622_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_627_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_627_ap_return;
reg    grp_image_filter_reg_int_s_fu_627_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_632_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_632_ap_return;
reg    grp_image_filter_reg_int_s_fu_632_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_637_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_637_ap_return;
reg    grp_image_filter_reg_int_s_fu_637_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_642_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_642_ap_return;
reg    grp_image_filter_reg_int_s_fu_642_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_647_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_647_ap_return;
reg    grp_image_filter_reg_int_s_fu_647_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_652_in_r;
reg    grp_image_filter_reg_int_s_fu_652_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_657_in_r;
reg    grp_image_filter_reg_int_s_fu_657_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_662_in_r;
reg    grp_image_filter_reg_int_s_fu_662_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_667_in_r;
reg    grp_image_filter_reg_int_s_fu_667_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_672_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_672_ap_return;
reg    grp_image_filter_reg_int_s_fu_672_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_677_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_677_ap_return;
reg    grp_image_filter_reg_int_s_fu_677_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_682_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_682_ap_return;
reg    grp_image_filter_reg_int_s_fu_682_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_687_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_687_ap_return;
reg    grp_image_filter_reg_int_s_fu_687_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_692_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_692_ap_return;
reg    grp_image_filter_reg_int_s_fu_692_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_697_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_697_ap_return;
reg    grp_image_filter_reg_int_s_fu_697_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_702_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_702_ap_return;
reg    grp_image_filter_reg_int_s_fu_702_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_707_in_r;
wire   [31:0] grp_image_filter_reg_int_s_fu_707_ap_return;
reg    grp_image_filter_reg_int_s_fu_707_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_712_in_r;
reg    grp_image_filter_reg_int_s_fu_712_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_717_in_r;
reg    grp_image_filter_reg_int_s_fu_717_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_722_in_r;
reg    grp_image_filter_reg_int_s_fu_722_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_727_in_r;
reg    grp_image_filter_reg_int_s_fu_727_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_732_in_r;
reg    grp_image_filter_reg_int_s_fu_732_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_737_in_r;
reg    grp_image_filter_reg_int_s_fu_737_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_742_in_r;
reg    grp_image_filter_reg_int_s_fu_742_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_747_in_r;
reg    grp_image_filter_reg_int_s_fu_747_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_752_in_r;
reg    grp_image_filter_reg_int_s_fu_752_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_757_in_r;
reg    grp_image_filter_reg_int_s_fu_757_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_762_in_r;
reg    grp_image_filter_reg_int_s_fu_762_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_767_in_r;
reg    grp_image_filter_reg_int_s_fu_767_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_772_in_r;
reg    grp_image_filter_reg_int_s_fu_772_ap_ce;
wire   [31:0] grp_image_filter_reg_int_s_fu_777_in_r;
reg    grp_image_filter_reg_int_s_fu_777_ap_ce;
reg   [10:0] p_s_reg_504;
reg    ap_sig_cseq_ST_st39_fsm_3;
reg    ap_sig_bdd_2075;
reg   [10:0] p_2_phi_fu_519_p4;
wire   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it0;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it1;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it2;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it3;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it4;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it5;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it6;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it7;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it8;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it9;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it10;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it11;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it12;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it13;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it14;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it15;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it16;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it17;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it18;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it19;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it20;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it21;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it22;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it23;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it24;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it25;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it26;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it27;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it28;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it29;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it30;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it31;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it32;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it33;
reg   [7:0] ap_reg_phiprechg_core_1_reg_527pp0_it34;
wire   [63:0] tmp_12_fu_867_p1;
wire   [63:0] tmp_14_fu_4577_p1;
reg   [7:0] win_val_6_V_5_fu_132;
reg   [15:0] core_win_val_0_V_0_fu_136;
reg   [15:0] core_win_val_0_V_1_fu_140;
wire   [15:0] core_win_val_0_V_2_fu_4620_p1;
reg   [7:0] win_val_6_V_4_fu_144;
reg   [15:0] core_win_val_1_V_0_fu_148;
reg   [15:0] core_win_val_1_V_1_fu_152;
wire   [15:0] core_win_val_1_V_2_fu_4623_p1;
reg   [7:0] win_val_6_V_3_fu_156;
reg   [15:0] core_win_val_2_V_0_fu_160;
reg   [15:0] core_win_val_2_V_1_fu_164;
wire   [15:0] core_win_val_2_V_1_2_fu_4643_p1;
reg   [7:0] win_val_0_V_2_3_fu_168;
reg   [7:0] win_val_0_V_2_fu_172;
reg   [7:0] win_val_0_V_3_fu_176;
reg   [7:0] win_val_0_V_4_fu_180;
reg   [7:0] win_val_0_V_5_fu_184;
reg   [7:0] win_val_1_V_1_3_fu_188;
reg   [7:0] win_val_1_V_1_fu_192;
reg   [7:0] win_val_1_V_2_fu_196;
reg   [7:0] win_val_1_V_3_fu_200;
reg   [7:0] win_val_1_V_4_fu_204;
reg   [7:0] win_val_1_V_5_fu_208;
reg   [7:0] win_val_2_V_0_3_fu_212;
reg   [7:0] win_val_2_V_0_fu_216;
reg   [7:0] win_val_2_V_1_fu_220;
reg   [7:0] win_val_2_V_2_fu_224;
reg   [7:0] win_val_2_V_3_fu_228;
reg   [7:0] win_val_2_V_4_fu_232;
reg   [7:0] win_val_2_V_5_fu_236;
reg   [7:0] win_val_3_V_0_3_fu_240;
reg   [7:0] win_val_3_V_0_fu_244;
reg   [7:0] win_val_3_V_1_fu_248;
reg   [7:0] win_val_3_V_2_fu_252;
reg   [7:0] win_val_3_V_3_fu_256;
reg   [7:0] win_val_3_V_4_fu_260;
reg   [7:0] win_val_3_V_5_fu_264;
reg   [7:0] win_val_4_V_0_3_fu_268;
reg   [7:0] win_val_4_V_0_fu_272;
reg   [7:0] win_val_4_V_1_fu_276;
reg   [7:0] win_val_4_V_2_fu_280;
reg   [7:0] win_val_4_V_3_fu_284;
reg   [7:0] win_val_4_V_4_fu_288;
reg   [7:0] win_val_4_V_5_fu_292;
reg   [7:0] win_val_5_V_1_3_fu_296;
reg   [7:0] win_val_5_V_1_fu_300;
reg   [7:0] win_val_5_V_2_fu_304;
reg   [7:0] win_val_5_V_3_fu_308;
reg   [7:0] win_val_5_V_4_fu_312;
reg   [7:0] win_val_5_V_5_fu_316;
reg   [7:0] win_val_6_V_2_3_fu_320;
reg   [7:0] win_val_6_V_2_fu_324;
wire   [7:0] core_win_val_2_V_2_fu_4635_p3;
wire   [8:0] tmp_16_fu_830_p4;
wire   [0:0] tmp_11_fu_857_p2;
wire   [0:0] tmp_17_fu_877_p2;
wire   [8:0] tmp_97_fu_888_p4;
wire   [0:0] icmp1_fu_898_p2;
wire   [8:0] rhs_V_fu_1256_p1;
wire   [0:0] tmp_18_fu_1266_p2;
wire   [0:0] tmp_19_fu_1272_p2;
wire   [8:0] rhs_V_s_fu_1292_p1;
wire   [0:0] tmp_176_1_fu_1302_p2;
wire   [0:0] tmp_177_1_fu_1308_p2;
wire   [8:0] rhs_V_2_fu_1328_p1;
wire   [0:0] tmp_176_2_fu_1338_p2;
wire   [0:0] tmp_177_2_fu_1344_p2;
wire   [8:0] rhs_V_3_fu_1364_p1;
wire   [0:0] tmp_176_3_fu_1374_p2;
wire   [0:0] tmp_177_3_fu_1380_p2;
wire   [8:0] rhs_V_4_fu_1400_p1;
wire   [8:0] rhs_V_5_fu_1422_p1;
wire   [8:0] rhs_V_6_fu_1444_p1;
wire   [8:0] rhs_V_7_fu_1466_p1;
wire   [8:0] rhs_V_1_fu_1512_p1;
wire   [0:0] tmp_21_fu_1527_p2;
wire   [0:0] tmp_22_fu_1533_p2;
wire   [8:0] rhs_V_1_1_fu_1553_p1;
wire   [8:0] rhs_V_1_2_fu_1580_p1;
wire   [8:0] rhs_V_1_3_fu_1607_p1;
wire   [8:0] rhs_V_1_4_fu_1622_p1;
wire   [0:0] tmp_31_fu_1638_p2;
wire   [1:0] phitmp_4_fu_1631_p3;
wire   [8:0] rhs_V_1_5_fu_1650_p1;
wire   [0:0] tmp_33_fu_1666_p2;
wire   [1:0] phitmp_5_fu_1659_p3;
wire   [8:0] rhs_V_1_6_fu_1678_p1;
wire   [0:0] tmp_35_fu_1694_p2;
wire   [1:0] phitmp_6_fu_1687_p3;
wire   [8:0] rhs_V_1_7_fu_1706_p1;
wire   [0:0] tmp_37_fu_1722_p2;
wire   [1:0] phitmp_7_fu_1715_p3;
wire   [1:0] flag_val_V_assign_load_1_1_fu_1562_p3;
wire   [0:0] tmp_181_0_not_fu_1734_p2;
wire   [1:0] flag_val_V_assign_load_1_2_fu_1589_p3;
wire   [0:0] tmp_183_1_fu_1758_p2;
wire   [0:0] tmp_181_1_not_fu_1752_p2;
wire   [1:0] flag_val_V_assign_load_1_4_fu_1616_p3;
wire   [0:0] tmp_183_2_fu_1776_p2;
wire   [0:0] tmp_181_2_not_fu_1770_p2;
wire   [1:0] flag_val_V_assign_load_1_6_fu_1642_p3;
wire   [0:0] tmp_183_3_fu_1794_p2;
wire   [0:0] tmp_181_3_not_fu_1788_p2;
wire   [1:0] flag_val_V_assign_load_1_8_fu_1670_p3;
wire   [0:0] tmp_183_4_fu_1812_p2;
wire   [0:0] tmp_181_4_not_fu_1806_p2;
wire   [1:0] flag_val_V_assign_load_1_11_fu_1698_p3;
wire   [0:0] tmp_25_fu_1907_p2;
wire   [1:0] phitmp1_1_fu_1900_p3;
wire   [0:0] tmp_28_fu_1926_p2;
wire   [1:0] phitmp1_2_fu_1919_p3;
wire   [0:0] tmp_182_3_fu_1938_p2;
wire   [0:0] tmp_184_3_fu_1943_p2;
wire   [0:0] tmp_30_fu_1956_p2;
wire   [1:0] phitmp1_3_fu_1948_p3;
wire   [0:0] tmp_41_fu_2010_p2;
wire   [3:0] phitmp42_op_cast_cast_cast_fu_2003_p3;
wire   [3:0] count_1_i_2_op_op_fu_1998_p3;
wire   [0:0] or_cond3_fu_1994_p2;
wire   [0:0] tmp_42_fu_2030_p2;
wire   [3:0] phitmp3_cast_cast_cast_fu_2022_p3;
wire   [3:0] count_1_i_4_op_fu_2014_p3;
wire   [1:0] flag_val_V_assign_load_2_s_fu_1894_p3;
wire   [0:0] tmp_183_7_fu_2049_p2;
wire   [0:0] tmp_181_7_not_fu_2044_p2;
wire   [1:0] flag_val_V_assign_load_1_9_fu_1911_p3;
wire   [0:0] tmp_181_8_fu_2069_p2;
wire   [0:0] tmp_32_fu_2108_p2;
wire   [1:0] phitmp1_4_fu_2101_p3;
wire   [0:0] tmp_34_fu_2127_p2;
wire   [1:0] phitmp1_5_fu_2120_p3;
wire   [0:0] tmp_182_6_fu_2139_p2;
wire   [0:0] tmp_184_6_fu_2144_p2;
wire   [0:0] tmp_36_fu_2157_p2;
wire   [1:0] phitmp1_6_fu_2149_p3;
wire   [0:0] tmp_185_7_fu_2181_p2;
wire   [3:0] count_8_fu_2197_p2;
wire   [0:0] tmp_185_8_fu_2202_p2;
wire   [0:0] not_or_cond1_fu_2213_p2;
wire   [3:0] phitmp4_fu_2208_p2;
wire   [3:0] count_1_i_8_fu_2224_p3;
wire   [0:0] not_or_cond2_demorgan_fu_2241_p2;
wire   [0:0] tmp_185_9_fu_2235_p2;
wire   [0:0] not_or_cond2_fu_2245_p2;
wire   [0:0] or_cond12_fu_2231_p2;
wire   [0:0] tmp_181_s_fu_2265_p2;
wire   [0:0] tmp_183_s_fu_2269_p2;
wire   [0:0] or_cond13_fu_2274_p2;
wire   [3:0] phitmp5_fu_2280_p2;
wire   [1:0] flag_val_V_assign_load_1_7_fu_2112_p3;
wire   [0:0] tmp_181_1_fu_2300_p2;
wire   [0:0] tmp_183_8_fu_2305_p2;
wire   [0:0] iscorner_2_i_7_fu_2191_p2;
wire   [0:0] p_iscorner_0_i_8_fu_2218_p2;
wire   [0:0] tmp_38_fu_2347_p2;
wire   [1:0] phitmp1_7_fu_2340_p3;
wire   [3:0] count_s_fu_2359_p2;
wire   [0:0] tmp_185_s_fu_2364_p2;
wire   [0:0] not_or_cond3_fu_2370_p2;
wire   [0:0] tmp_185_1_fu_2381_p2;
wire   [0:0] not_or_cond4_fu_2386_p2;
wire   [3:0] count_1_i_1_fu_2397_p3;
wire   [3:0] count_1_fu_2407_p2;
wire   [0:0] not_or_cond12_demorgan_fu_2425_p2;
wire   [0:0] tmp_185_2_fu_2413_p2;
wire   [0:0] not_or_cond12_fu_2429_p2;
wire   [0:0] or_cond15_fu_2403_p2;
wire   [3:0] phitmp6_fu_2419_p2;
wire   [0:0] tmp_181_3_fu_2449_p2;
wire   [0:0] tmp_183_11_fu_2453_p2;
wire   [3:0] count_1_i_2_fu_2441_p3;
wire   [0:0] or_cond16_fu_2458_p2;
wire   [1:0] flag_val_V_assign_load_1_14_fu_2351_p3;
wire   [0:0] tmp_181_4_fu_2484_p2;
wire   [0:0] tmp_183_12_fu_2489_p2;
wire   [0:0] tmp_181_5_fu_2506_p2;
wire   [0:0] p_iscorner_0_i_s_fu_2375_p2;
wire   [0:0] not_or_cond13_fu_2521_p2;
wire   [4:0] count_1_i_3_cast_fu_2531_p1;
wire   [4:0] count_2_fu_2534_p2;
wire   [0:0] tmp_185_4_fu_2540_p2;
wire   [0:0] not_or_cond14_fu_2552_p2;
wire   [4:0] phitmp7_fu_2546_p2;
wire   [4:0] count_1_i_4_fu_2563_p3;
wire   [0:0] tmp_185_5_fu_2570_p2;
wire   [0:0] not_or_cond15_fu_2576_p2;
wire   [4:0] count_1_i_5_fu_2587_p3;
wire   [0:0] p_iscorner_0_i_3_fu_2526_p2;
wire   [0:0] p_iscorner_0_i_4_fu_2557_p2;
wire   [0:0] tmp_185_6_fu_2620_p2;
wire   [0:0] not_or_cond5_fu_2625_p2;
wire   [4:0] count_1_i_10_fu_2636_p3;
wire   [0:0] tmp_185_10_fu_2642_p2;
wire   [0:0] not_or_cond6_fu_2648_p2;
wire   [4:0] count_1_i_11_fu_2659_p3;
wire   [4:0] phitmp9_fu_2672_p2;
wire   [0:0] tmp7_fu_2685_p2;
wire   [0:0] p_iscorner_0_i_6_fu_2630_p2;
wire   [0:0] tmp_185_11_fu_2699_p2;
wire   [0:0] not_or_cond7_fu_2704_p2;
wire   [0:0] tmp_185_12_fu_2715_p2;
wire   [0:0] not_or_cond8_fu_2720_p2;
wire   [4:0] count_1_i_13_fu_2731_p3;
wire   [4:0] count_5_fu_2737_p2;
wire   [4:0] phitmp10_fu_2749_p2;
wire   [0:0] p_iscorner_0_i_10_fu_2709_p2;
wire   [0:0] not_or_cond9_fu_2767_p2;
wire   [0:0] tmp_185_14_fu_2777_p2;
wire   [0:0] not_or_cond10_fu_2782_p2;
wire   [4:0] count_1_i_15_fu_2793_p3;
wire   [4:0] count_6_fu_2799_p2;
wire   [4:0] phitmp_fu_2811_p2;
wire   [0:0] p_iscorner_0_i_12_fu_2772_p2;
wire   [0:0] p_iscorner_0_i_14_fu_2842_p2;
wire   [0:0] p_iscorner_0_i_15_fu_2846_p2;
wire   [0:0] tmp17_fu_2850_p2;
wire   [0:0] tmp16_fu_2856_p2;
wire   [0:0] tmp10_fu_2866_p2;
wire   [0:0] tmp_188_1_fu_2875_p2;
wire   [8:0] tmp_193_1_fu_2879_p3;
wire   [0:0] tmp_195_1_fu_2890_p2;
wire   [8:0] tmp_203_1_fu_2894_p3;
wire   [0:0] tmp_188_3_fu_2905_p2;
wire   [8:0] tmp_193_3_fu_2909_p3;
wire   [0:0] tmp_195_3_fu_2920_p2;
wire   [8:0] tmp_203_3_fu_2924_p3;
wire   [0:0] tmp_188_5_fu_2935_p2;
wire   [8:0] tmp_193_5_fu_2939_p3;
wire   [0:0] tmp_195_5_fu_2950_p2;
wire   [8:0] tmp_203_5_fu_2954_p3;
wire   [0:0] tmp_188_7_fu_2965_p2;
wire   [8:0] tmp_193_7_fu_2969_p3;
wire   [0:0] tmp_195_7_fu_2980_p2;
wire   [8:0] tmp_203_7_fu_2984_p3;
wire   [0:0] tmp_192_1_fu_2995_p2;
wire   [0:0] tmp_202_1_fu_3010_p2;
wire   [0:0] tmp_192_3_fu_3025_p2;
wire   [0:0] tmp_202_3_fu_3039_p2;
wire   [0:0] tmp_192_5_fu_3053_p2;
wire   [0:0] tmp_202_5_fu_3068_p2;
wire   [0:0] tmp_188_9_fu_3083_p2;
wire   [8:0] tmp_193_9_fu_3087_p3;
wire   [0:0] tmp_195_9_fu_3098_p2;
wire   [8:0] tmp_203_9_fu_3102_p3;
wire   [0:0] tmp_199_1_fu_3113_p2;
wire   [0:0] tmp_212_1_fu_3128_p2;
wire   [0:0] tmp_188_s_fu_3146_p2;
wire   [8:0] tmp_193_s_fu_3150_p3;
wire   [0:0] tmp_195_s_fu_3161_p2;
wire   [8:0] tmp_203_s_fu_3165_p3;
wire   [0:0] tmp_188_2_fu_3176_p2;
wire   [8:0] tmp_193_2_fu_3180_p3;
wire   [0:0] tmp_195_2_fu_3191_p2;
wire   [8:0] tmp_203_2_fu_3195_p3;
wire   [0:0] tmp_188_4_fu_3206_p2;
wire   [8:0] tmp_193_4_fu_3210_p3;
wire   [0:0] tmp_195_4_fu_3221_p2;
wire   [8:0] tmp_203_4_fu_3225_p3;
wire   [0:0] tmp_192_7_fu_3236_p2;
wire   [0:0] tmp_202_7_fu_3249_p2;
wire   [0:0] tmp_192_9_fu_3277_p2;
wire   [0:0] tmp_202_9_fu_3290_p2;
wire   [0:0] tmp_192_s_fu_3303_p2;
wire   [0:0] tmp_202_s_fu_3318_p2;
wire   [0:0] tmp_192_2_fu_3333_p2;
wire   [0:0] tmp_202_2_fu_3348_p2;
wire   [0:0] tmp_192_4_fu_3363_p2;
wire   [0:0] tmp_202_4_fu_3376_p2;
wire   [0:0] tmp_199_3_fu_3389_p2;
wire   [0:0] tmp_212_3_fu_3404_p2;
wire   [31:0] a_0_flag_d_assign_load_5_fu_3419_p3;
wire   [0:0] tmp_45_fu_3428_p2;
wire   [7:0] tmp_44_fu_3424_p1;
wire  signed [31:0] flag_d_assign_9_fu_3274_p1;
wire   [0:0] tmp_46_fu_3442_p2;
wire   [31:0] tmp_68_fu_3458_p3;
wire   [0:0] tmp_69_fu_3467_p2;
wire   [8:0] tmp_80_fu_3463_p1;
wire   [0:0] tmp_70_fu_3481_p2;
wire   [0:0] tmp_199_5_fu_3500_p2;
wire   [0:0] tmp_212_5_fu_3512_p2;
wire   [0:0] tmp_199_7_fu_3524_p2;
wire   [0:0] tmp_212_7_fu_3536_p2;
wire   [0:0] tmp_199_9_fu_3548_p2;
wire   [0:0] tmp_212_9_fu_3562_p2;
wire   [0:0] tmp_199_s_fu_3576_p2;
wire   [0:0] tmp_212_s_fu_3590_p2;
wire   [0:0] tmp_199_2_fu_3604_p2;
wire   [0:0] tmp_212_2_fu_3616_p2;
wire   [0:0] tmp_199_4_fu_3628_p2;
wire   [0:0] tmp_212_4_fu_3640_p2;
wire   [31:0] p_a_0_flag_d_assign_load_5_cast_fu_3652_p1;
wire   [0:0] tmp_49_fu_3655_p2;
wire  signed [31:0] b0_cast_fu_3672_p1;
wire   [0:0] tmp_72_fu_3675_p2;
wire   [31:0] tmp_216_1_fu_3698_p3;
wire   [31:0] p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1;
wire   [0:0] tmp_217_1_fu_3707_p2;
wire   [7:0] tmp_56_fu_3703_p1;
wire  signed [31:0] flag_d_assign_10_fu_3692_p1;
wire   [0:0] tmp_231_1_fu_3720_p2;
wire   [31:0] tmp_227_1_fu_3739_p3;
wire  signed [31:0] b0_tmp_239_cast_fu_3736_p1;
wire   [0:0] tmp_228_1_fu_3748_p2;
wire   [8:0] tmp_82_fu_3744_p1;
wire   [0:0] tmp_236_1_fu_3761_p2;
wire   [31:0] a0_cast_fu_3780_p1;
wire   [0:0] tmp_233_1_fu_3783_p2;
wire  signed [31:0] b0_cast_50_fu_3800_p1;
wire   [0:0] tmp_240_1_fu_3803_p2;
wire   [31:0] tmp_216_2_fu_3826_p3;
wire   [31:0] a0_tmp_232_1_cast_fu_3823_p1;
wire   [0:0] tmp_217_2_fu_3835_p2;
wire   [7:0] tmp_58_fu_3831_p1;
wire  signed [31:0] flag_d_assign_12_fu_3820_p1;
wire   [0:0] tmp_231_2_fu_3848_p2;
wire   [31:0] tmp_227_2_fu_3867_p3;
wire  signed [31:0] b0_tmp_239_1_cast_fu_3864_p1;
wire   [0:0] tmp_228_2_fu_3876_p2;
wire   [8:0] tmp_84_fu_3872_p1;
wire   [0:0] tmp_236_2_fu_3889_p2;
wire   [31:0] a0_2_cast_fu_3908_p1;
wire   [0:0] tmp_233_2_fu_3911_p2;
wire  signed [31:0] b0_2_cast_fu_3928_p1;
wire   [0:0] tmp_240_2_fu_3931_p2;
wire   [31:0] tmp_216_3_fu_3954_p3;
wire   [31:0] a0_2_tmp_232_2_cast_fu_3951_p1;
wire   [0:0] tmp_217_3_fu_3963_p2;
wire   [7:0] tmp_60_fu_3959_p1;
wire  signed [31:0] flag_d_assign_14_fu_3948_p1;
wire   [0:0] tmp_231_3_fu_3976_p2;
wire   [31:0] tmp_227_3_fu_3995_p3;
wire  signed [31:0] b0_2_tmp_239_2_cast_fu_3992_p1;
wire   [0:0] tmp_228_3_fu_4004_p2;
wire   [8:0] tmp_86_fu_4000_p1;
wire   [0:0] tmp_236_3_fu_4017_p2;
wire   [31:0] a0_3_cast_fu_4036_p1;
wire   [0:0] tmp_233_3_fu_4039_p2;
wire  signed [31:0] b0_3_cast_fu_4056_p1;
wire   [0:0] tmp_240_3_fu_4059_p2;
wire   [31:0] tmp_216_4_fu_4082_p3;
wire   [31:0] a0_3_tmp_232_3_cast_fu_4079_p1;
wire   [0:0] tmp_217_4_fu_4091_p2;
wire   [7:0] tmp_62_fu_4087_p1;
wire  signed [31:0] flag_d_assign_1_fu_4076_p1;
wire   [0:0] tmp_231_4_fu_4104_p2;
wire   [31:0] tmp_227_4_fu_4123_p3;
wire  signed [31:0] b0_3_tmp_239_3_cast_fu_4120_p1;
wire   [0:0] tmp_228_4_fu_4132_p2;
wire   [8:0] tmp_88_fu_4128_p1;
wire   [0:0] tmp_236_4_fu_4145_p2;
wire   [31:0] a0_4_cast_fu_4164_p1;
wire   [0:0] tmp_233_4_fu_4167_p2;
wire  signed [31:0] b0_4_cast_fu_4184_p1;
wire   [0:0] tmp_240_4_fu_4187_p2;
wire   [31:0] tmp_216_5_fu_4210_p3;
wire   [31:0] a0_4_tmp_232_4_cast_fu_4207_p1;
wire   [0:0] tmp_217_5_fu_4219_p2;
wire   [7:0] tmp_64_fu_4215_p1;
wire  signed [31:0] flag_d_assign_3_fu_4204_p1;
wire   [0:0] tmp_231_5_fu_4232_p2;
wire   [31:0] tmp_227_5_fu_4251_p3;
wire  signed [31:0] b0_4_tmp_239_4_cast_fu_4248_p1;
wire   [0:0] tmp_228_5_fu_4260_p2;
wire   [8:0] tmp_90_fu_4256_p1;
wire   [0:0] tmp_236_5_fu_4273_p2;
wire   [31:0] a0_5_cast_fu_4292_p1;
wire   [0:0] tmp_233_5_fu_4295_p2;
wire  signed [31:0] b0_5_cast_fu_4312_p1;
wire   [0:0] tmp_240_5_fu_4315_p2;
wire   [31:0] tmp_216_6_fu_4338_p3;
wire   [31:0] a0_5_tmp_232_5_cast_fu_4335_p1;
wire   [0:0] tmp_217_6_fu_4347_p2;
wire   [7:0] tmp_66_fu_4343_p1;
wire  signed [31:0] flag_d_assign_5_fu_4332_p1;
wire   [0:0] tmp_231_6_fu_4360_p2;
wire   [31:0] tmp_227_6_fu_4379_p3;
wire  signed [31:0] b0_5_tmp_239_5_cast_fu_4376_p1;
wire   [0:0] tmp_228_6_fu_4388_p2;
wire   [8:0] tmp_92_fu_4384_p1;
wire   [0:0] tmp_236_6_fu_4401_p2;
wire   [31:0] a0_6_cast_fu_4420_p1;
wire   [0:0] tmp_233_6_fu_4423_p2;
wire  signed [31:0] b0_6_cast_fu_4440_p1;
wire   [0:0] tmp_240_6_fu_4443_p2;
wire   [31:0] tmp_216_7_fu_4466_p3;
wire   [31:0] a0_6_tmp_232_6_cast_fu_4463_p1;
wire   [0:0] tmp_217_7_fu_4475_p2;
wire   [7:0] tmp_77_fu_4471_p1;
wire  signed [31:0] flag_d_assign_7_fu_4460_p1;
wire   [0:0] tmp_231_7_fu_4488_p2;
wire   [31:0] tmp_227_7_fu_4507_p3;
wire  signed [31:0] b0_6_tmp_239_6_cast_fu_4504_p1;
wire   [0:0] tmp_228_7_fu_4516_p2;
wire   [8:0] tmp_94_fu_4512_p1;
wire   [0:0] tmp_236_7_fu_4529_p2;
wire   [31:0] a0_7_cast_fu_4549_p1;
wire   [0:0] tmp_233_7_fu_4552_p2;
wire  signed [31:0] b0_7_cast_fu_4563_p1;
wire   [0:0] tmp_240_7_fu_4566_p2;
wire   [7:0] tmp_50_fu_4583_p2;
wire   [0:0] tmp_51_fu_4588_p2;
wire   [0:0] tmp_52_fu_4647_p2;
wire   [0:0] tmp_73_fu_4653_p2;
wire   [0:0] tmp_242_1_fu_4659_p2;
wire   [0:0] tmp21_fu_4706_p2;
wire   [0:0] tmp_74_fu_4671_p2;
wire   [0:0] tmp_245_1_fu_4677_p2;
wire   [0:0] tmp24_fu_4717_p2;
wire   [0:0] tmp_242_2_fu_4665_p2;
wire   [0:0] tmp_55_fu_4695_p2;
wire   [0:0] tmp_54_fu_4689_p2;
wire   [0:0] tmp26_fu_4729_p2;
wire   [0:0] tmp_245_2_fu_4683_p2;
wire   [0:0] tmp22_fu_4775_p2;
wire   [0:0] tmp18_fu_4771_p2;
wire   [0:0] tmp_26_fu_4779_p2;
reg   [3:0] ap_NS_fsm;
reg    ap_sig_bdd_2152;
reg    ap_sig_bdd_250;
reg    ap_sig_bdd_2159;
reg    ap_sig_bdd_2108;
reg    ap_sig_bdd_2156;
reg    ap_sig_bdd_1776;


image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_0_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_0_V_address0 ),
    .ce0( k_buf_val_0_V_ce0 ),
    .q0( k_buf_val_0_V_q0 ),
    .address1( k_buf_val_0_V_address1 ),
    .ce1( k_buf_val_0_V_ce1 ),
    .we1( k_buf_val_0_V_we1 ),
    .d1( k_buf_val_0_V_d1 )
);

image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_1_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_1_V_address0 ),
    .ce0( k_buf_val_1_V_ce0 ),
    .q0( k_buf_val_1_V_q0 ),
    .address1( k_buf_val_1_V_address1 ),
    .ce1( k_buf_val_1_V_ce1 ),
    .we1( k_buf_val_1_V_we1 ),
    .d1( k_buf_val_1_V_d1 )
);

image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_2_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_2_V_address0 ),
    .ce0( k_buf_val_2_V_ce0 ),
    .q0( k_buf_val_2_V_q0 ),
    .address1( k_buf_val_2_V_address1 ),
    .ce1( k_buf_val_2_V_ce1 ),
    .we1( k_buf_val_2_V_we1 ),
    .d1( k_buf_val_2_V_d1 )
);

image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_3_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_3_V_address0 ),
    .ce0( k_buf_val_3_V_ce0 ),
    .q0( k_buf_val_3_V_q0 ),
    .address1( k_buf_val_3_V_address1 ),
    .ce1( k_buf_val_3_V_ce1 ),
    .we1( k_buf_val_3_V_we1 ),
    .d1( k_buf_val_3_V_d1 )
);

image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_4_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_4_V_address0 ),
    .ce0( k_buf_val_4_V_ce0 ),
    .q0( k_buf_val_4_V_q0 ),
    .address1( k_buf_val_4_V_address1 ),
    .ce1( k_buf_val_4_V_ce1 ),
    .we1( k_buf_val_4_V_we1 ),
    .d1( k_buf_val_4_V_d1 )
);

image_filter_FAST_t_opr_k_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_val_5_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_val_5_V_address0 ),
    .ce0( k_buf_val_5_V_ce0 ),
    .q0( k_buf_val_5_V_q0 ),
    .address1( k_buf_val_5_V_address1 ),
    .ce1( k_buf_val_5_V_ce1 ),
    .we1( k_buf_val_5_V_we1 ),
    .d1( k_buf_val_5_V_d1 )
);

image_filter_FAST_t_opr_core_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1927 ),
    .AddressWidth( 11 ))
core_buf_val_0_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( core_buf_val_0_V_address0 ),
    .ce0( core_buf_val_0_V_ce0 ),
    .q0( core_buf_val_0_V_q0 ),
    .address1( core_buf_val_0_V_address1 ),
    .ce1( core_buf_val_0_V_ce1 ),
    .we1( core_buf_val_0_V_we1 ),
    .d1( core_buf_val_0_V_d1 )
);

image_filter_FAST_t_opr_core_buf_val_0_V #(
    .DataWidth( 8 ),
    .AddressRange( 1927 ),
    .AddressWidth( 11 ))
core_buf_val_1_V_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( core_buf_val_1_V_address0 ),
    .ce0( core_buf_val_1_V_ce0 ),
    .q0( core_buf_val_1_V_q0 ),
    .address1( core_buf_val_1_V_address1 ),
    .ce1( core_buf_val_1_V_ce1 ),
    .we1( core_buf_val_1_V_we1 ),
    .d1( core_buf_val_1_V_d1 )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_542(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_542_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_542_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_542_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_547(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_547_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_547_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_547_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_552(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_552_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_552_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_552_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_557(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_557_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_557_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_557_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_562(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_562_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_562_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_562_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_567(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_567_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_567_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_567_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_572(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_572_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_572_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_572_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_577(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_577_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_577_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_577_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_582(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_582_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_582_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_582_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_587(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_587_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_587_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_587_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_592(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_592_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_592_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_592_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_597(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_597_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_597_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_597_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_602(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_602_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_602_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_602_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_607(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_607_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_607_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_607_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_612(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_612_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_612_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_612_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_617(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_617_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_617_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_617_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_622(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_622_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_622_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_622_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_627(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_627_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_627_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_627_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_632(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_632_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_632_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_632_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_637(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_637_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_637_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_637_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_642(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_642_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_642_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_642_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_647(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_647_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_647_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_647_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_652(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_652_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_652_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_652_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_657(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_657_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_657_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_657_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_662(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_662_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_662_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_662_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_667(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_667_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_667_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_667_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_672(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_672_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_672_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_672_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_677(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_677_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_677_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_677_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_682(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_682_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_682_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_682_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_687(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_687_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_687_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_687_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_692(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_692_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_692_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_692_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_697(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_697_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_697_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_697_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_702(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_702_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_702_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_702_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_707(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_707_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_707_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_707_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_712(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_712_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_712_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_712_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_717(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_717_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_717_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_717_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_722(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_722_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_722_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_722_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_727(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_727_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_727_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_727_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_732(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_732_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_732_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_732_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_737(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_737_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_737_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_737_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_742(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_742_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_742_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_742_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_747(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_747_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_747_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_747_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_752(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_752_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_752_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_752_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_757(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_757_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_757_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_757_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_762(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_762_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_762_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_762_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_767(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_767_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_767_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_767_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_772(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_772_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_772_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_772_ap_ce )
);

image_filter_reg_int_s grp_image_filter_reg_int_s_fu_777(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .in_r( grp_image_filter_reg_int_s_fu_777_in_r ),
    .ap_return( grp_image_filter_reg_int_s_fu_777_ap_return ),
    .ap_ce( grp_image_filter_reg_int_s_fu_777_ap_ce )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
    if (ap_rst == 1'b1) begin
        ap_done_reg <= ap_const_logic_0;
    end else begin
        if ((ap_const_logic_1 == ap_continue)) begin
            ap_done_reg <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
            ap_done_reg <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_lv1_0 == exitcond_fu_846_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
            ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
        end
    end
end

/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
        end
    end
end

/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
        end
    end
end

/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
        end
    end
end

/// ap_reg_ppiten_pp0_it14 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it14
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
        end
    end
end

/// ap_reg_ppiten_pp0_it15 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it15
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
        end
    end
end

/// ap_reg_ppiten_pp0_it16 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it16
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
        end
    end
end

/// ap_reg_ppiten_pp0_it17 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it17
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
        end
    end
end

/// ap_reg_ppiten_pp0_it18 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it18
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
        end
    end
end

/// ap_reg_ppiten_pp0_it19 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it19
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
        end
    end
end

/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
        end
    end
end

/// ap_reg_ppiten_pp0_it20 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it20
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
        end
    end
end

/// ap_reg_ppiten_pp0_it21 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it21
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
        end
    end
end

/// ap_reg_ppiten_pp0_it22 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it22
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
        end
    end
end

/// ap_reg_ppiten_pp0_it23 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it23
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
        end
    end
end

/// ap_reg_ppiten_pp0_it24 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it24
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
        end
    end
end

/// ap_reg_ppiten_pp0_it25 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it25
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
        end
    end
end

/// ap_reg_ppiten_pp0_it26 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it26
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
        end
    end
end

/// ap_reg_ppiten_pp0_it27 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it27
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
        end
    end
end

/// ap_reg_ppiten_pp0_it28 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it28
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
        end
    end
end

/// ap_reg_ppiten_pp0_it29 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it29
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
        end
    end
end

/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
        end
    end
end

/// ap_reg_ppiten_pp0_it30 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it30
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
        end
    end
end

/// ap_reg_ppiten_pp0_it31 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it31
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
        end
    end
end

/// ap_reg_ppiten_pp0_it32 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it32
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
        end
    end
end

/// ap_reg_ppiten_pp0_it33 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it33
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
        end
    end
end

/// ap_reg_ppiten_pp0_it34 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it34
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
        end
    end
end

/// ap_reg_ppiten_pp0_it35 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it35
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
            ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
        end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2)) | (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33)))) begin
            ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
        end
    end
end

/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
        end
    end
end

/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
        end
    end
end

/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
        end
    end
end

/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
        end
    end
end

/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
            ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (ap_sig_bdd_250) begin
        if (ap_sig_bdd_2152) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_const_lv8_0;
        end else if ((ap_true == ap_true)) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it1 <= ap_reg_phiprechg_core_1_reg_527pp0_it0;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (ap_sig_bdd_2108) begin
        if (ap_sig_bdd_2159) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_const_lv8_0;
        end else if ((ap_true == ap_true)) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it13 <= ap_reg_phiprechg_core_1_reg_527pp0_it12;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (ap_sig_bdd_1776) begin
        if (ap_sig_bdd_2156) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it34 <= phitmp2_fu_4606_p2;
        end else if ((ap_true == ap_true)) begin
            ap_reg_phiprechg_core_1_reg_527pp0_it34 <= ap_reg_phiprechg_core_1_reg_527pp0_it33;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        p_2_reg_515 <= j_V_reg_5151;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
        p_2_reg_515 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st39_fsm_3)) begin
        p_s_reg_504 <= i_V_reg_5122;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_180)) begin
        p_s_reg_504 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))) begin
        a0_2_reg_6285 <= a0_2_fu_3841_p3;
        b0_2_reg_6301 <= b0_2_fu_3882_p3;
        tmp_232_2_reg_6291 <= tmp_232_2_fu_3853_p3;
        tmp_239_2_reg_6307 <= tmp_239_2_fu_3894_p3;
        tmp_59_reg_6296 <= tmp_59_fu_3860_p1;
        tmp_85_reg_6312 <= tmp_85_fu_3901_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) begin
        a0_2_tmp_232_2_reg_6337 <= a0_2_tmp_232_2_fu_3916_p3;
        b0_2_tmp_239_2_reg_6348 <= b0_2_tmp_239_2_fu_3936_p3;
        tmp_209_3_reg_6343 <= tmp_209_3_fu_3922_p2;
        tmp_221_3_reg_6354 <= tmp_221_3_fu_3942_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))) begin
        a0_3_reg_6359 <= a0_3_fu_3969_p3;
        b0_3_reg_6375 <= b0_3_fu_4010_p3;
        tmp_232_3_reg_6365 <= tmp_232_3_fu_3981_p3;
        tmp_239_3_reg_6381 <= tmp_239_3_fu_4022_p3;
        tmp_61_reg_6370 <= tmp_61_fu_3988_p1;
        tmp_87_reg_6386 <= tmp_87_fu_4029_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) begin
        a0_3_tmp_232_3_reg_6411 <= a0_3_tmp_232_3_fu_4044_p3;
        b0_3_tmp_239_3_reg_6422 <= b0_3_tmp_239_3_fu_4064_p3;
        tmp_209_4_reg_6417 <= tmp_209_4_fu_4050_p2;
        tmp_221_4_reg_6428 <= tmp_221_4_fu_4070_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))) begin
        a0_4_reg_6433 <= a0_4_fu_4097_p3;
        b0_4_reg_6449 <= b0_4_fu_4138_p3;
        tmp_232_4_reg_6439 <= tmp_232_4_fu_4109_p3;
        tmp_239_4_reg_6455 <= tmp_239_4_fu_4150_p3;
        tmp_63_reg_6444 <= tmp_63_fu_4116_p1;
        tmp_89_reg_6460 <= tmp_89_fu_4157_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) begin
        a0_4_tmp_232_4_reg_6485 <= a0_4_tmp_232_4_fu_4172_p3;
        b0_4_tmp_239_4_reg_6496 <= b0_4_tmp_239_4_fu_4192_p3;
        tmp_209_5_reg_6491 <= tmp_209_5_fu_4178_p2;
        tmp_221_5_reg_6502 <= tmp_221_5_fu_4198_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))) begin
        a0_5_reg_6507 <= a0_5_fu_4225_p3;
        b0_5_reg_6523 <= b0_5_fu_4266_p3;
        tmp_232_5_reg_6513 <= tmp_232_5_fu_4237_p3;
        tmp_239_5_reg_6529 <= tmp_239_5_fu_4278_p3;
        tmp_65_reg_6518 <= tmp_65_fu_4244_p1;
        tmp_91_reg_6534 <= tmp_91_fu_4285_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) begin
        a0_5_tmp_232_5_reg_6559 <= a0_5_tmp_232_5_fu_4300_p3;
        b0_5_tmp_239_5_reg_6570 <= b0_5_tmp_239_5_fu_4320_p3;
        tmp_209_6_reg_6565 <= tmp_209_6_fu_4306_p2;
        tmp_221_6_reg_6576 <= tmp_221_6_fu_4326_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))) begin
        a0_6_reg_6581 <= a0_6_fu_4353_p3;
        b0_6_reg_6597 <= b0_6_fu_4394_p3;
        tmp_232_6_reg_6587 <= tmp_232_6_fu_4365_p3;
        tmp_239_6_reg_6603 <= tmp_239_6_fu_4406_p3;
        tmp_75_reg_6592 <= tmp_75_fu_4372_p1;
        tmp_93_reg_6608 <= tmp_93_fu_4413_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) begin
        a0_6_tmp_232_6_reg_6633 <= a0_6_tmp_232_6_fu_4428_p3;
        b0_6_tmp_239_6_reg_6644 <= b0_6_tmp_239_6_fu_4448_p3;
        tmp_209_7_reg_6639 <= tmp_209_7_fu_4434_p2;
        tmp_221_7_reg_6650 <= tmp_221_7_fu_4454_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it29) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29))) begin
        a0_7_reg_6655 <= a0_7_fu_4481_p3;
        b0_7_reg_6671 <= b0_7_fu_4522_p3;
        tmp_232_7_reg_6661 <= tmp_232_7_fu_4493_p3;
        tmp_239_7_reg_6676 <= tmp_239_7_fu_4534_p3;
        tmp_78_reg_6666 <= tmp_78_fu_4500_p1;
        tmp_95_reg_6681 <= tmp_95_fu_4541_p1;
        tmp_96_reg_6686 <= tmp_96_fu_4545_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it30) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30))) begin
        a0_7_tmp_232_7_reg_6691 <= a0_7_tmp_232_7_fu_4557_p3;
        tmp_79_reg_6697 <= tmp_79_fu_4571_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))) begin
        a0_s_reg_6211 <= a0_s_fu_3713_p3;
        b0_s_reg_6227 <= b0_s_fu_3754_p3;
        tmp_232_1_reg_6217 <= tmp_232_1_fu_3725_p3;
        tmp_239_1_reg_6233 <= tmp_239_1_fu_3766_p3;
        tmp_57_reg_6222 <= tmp_57_fu_3732_p1;
        tmp_83_reg_6238 <= tmp_83_fu_3773_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) begin
        a0_tmp_232_1_reg_6263 <= a0_tmp_232_1_fu_3788_p3;
        b0_tmp_239_1_reg_6274 <= b0_tmp_239_1_fu_3808_p3;
        tmp_209_2_reg_6269 <= tmp_209_2_fu_3794_p2;
        tmp_221_2_reg_6280 <= tmp_221_2_fu_3814_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it9) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it10 <= ap_reg_phiprechg_core_1_reg_527pp0_it9;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it11 <= ap_reg_phiprechg_core_1_reg_527pp0_it10;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it11) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it12 <= ap_reg_phiprechg_core_1_reg_527pp0_it11;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it13) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it14 <= ap_reg_phiprechg_core_1_reg_527pp0_it13;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it14) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it15 <= ap_reg_phiprechg_core_1_reg_527pp0_it14;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it15) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it16 <= ap_reg_phiprechg_core_1_reg_527pp0_it15;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it16) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it17 <= ap_reg_phiprechg_core_1_reg_527pp0_it16;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it17) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it18 <= ap_reg_phiprechg_core_1_reg_527pp0_it17;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it18) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it19 <= ap_reg_phiprechg_core_1_reg_527pp0_it18;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it2 <= ap_reg_phiprechg_core_1_reg_527pp0_it1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it19) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it20 <= ap_reg_phiprechg_core_1_reg_527pp0_it19;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it20) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it21 <= ap_reg_phiprechg_core_1_reg_527pp0_it20;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it21) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it22 <= ap_reg_phiprechg_core_1_reg_527pp0_it21;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it22) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it23 <= ap_reg_phiprechg_core_1_reg_527pp0_it22;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it23) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it24 <= ap_reg_phiprechg_core_1_reg_527pp0_it23;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it24) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it25 <= ap_reg_phiprechg_core_1_reg_527pp0_it24;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it25) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it26 <= ap_reg_phiprechg_core_1_reg_527pp0_it25;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it26) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it27 <= ap_reg_phiprechg_core_1_reg_527pp0_it26;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it27) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it28 <= ap_reg_phiprechg_core_1_reg_527pp0_it27;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it28) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it29 <= ap_reg_phiprechg_core_1_reg_527pp0_it28;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it3 <= ap_reg_phiprechg_core_1_reg_527pp0_it2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it29) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it30 <= ap_reg_phiprechg_core_1_reg_527pp0_it29;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it30) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it31 <= ap_reg_phiprechg_core_1_reg_527pp0_it30;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it31) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it32 <= ap_reg_phiprechg_core_1_reg_527pp0_it31;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it33 <= ap_reg_phiprechg_core_1_reg_527pp0_it32;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it4 <= ap_reg_phiprechg_core_1_reg_527pp0_it3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it5 <= ap_reg_phiprechg_core_1_reg_527pp0_it4;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it6 <= ap_reg_phiprechg_core_1_reg_527pp0_it5;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it7 <= ap_reg_phiprechg_core_1_reg_527pp0_it6;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it8 <= ap_reg_phiprechg_core_1_reg_527pp0_it7;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it8) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_phiprechg_core_1_reg_527pp0_it9 <= ap_reg_phiprechg_core_1_reg_527pp0_it8;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35)))) begin
        ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33 <= core_buf_val_1_V_addr_reg_6708;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it10 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it9;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it11 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it10;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it12 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it11;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it13 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it12;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it14 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it13;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it15 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it14;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it16 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it15;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it17 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it16;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it18 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it17;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it19 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it18;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it2 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it1;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it20 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it19;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it21 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it20;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it22 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it21;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it23 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it22;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it24 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it23;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it25 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it24;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it26 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it25;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it27 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it26;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it28 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it27;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it29 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it28;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it3 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it2;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it30 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it29;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it31 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it30;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it32 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it31;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it33 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it32;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it4 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it3;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it5 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it4;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it6 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it5;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it7 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it6;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it8 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it7;
        ap_reg_ppstg_exitcond_reg_5147_pp0_it9 <= ap_reg_ppstg_exitcond_reg_5147_pp0_it8;
        ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14 <= flag_d_max2_1_reg_5959;
        ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15 <= ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it14;
        ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14 <= flag_d_max2_7_reg_5971;
        ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15 <= flag_d_max4_1_reg_5993;
        ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16 <= ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it15;
        ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15 <= flag_d_max4_5_reg_6005;
        ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16 <= ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it15;
        ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14 <= flag_d_min2_1_reg_5953;
        ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15 <= ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it14;
        ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14 <= flag_d_min2_7_reg_5965;
        ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15 <= flag_d_min4_1_reg_5987;
        ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16 <= ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it15;
        ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15 <= flag_d_min4_5_reg_5999;
        ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16 <= ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it15;
        ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4 <= flag_val_V_assign_load_1_s_reg_5417;
        ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5 <= ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it4;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 <= iscorner_2_i_s_reg_5949;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it29;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it30;
        ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32 <= ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31;
        ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5 <= not_or_cond10_demorgan_reg_5699;
        ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it5;
        ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it6;
        ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it7;
        ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 <= ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it8;
        ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5 <= not_or_cond11_demorgan_reg_5704;
        ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it5;
        ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it6;
        ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it7;
        ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 <= ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it8;
        ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4 <= not_or_cond6_demorgan_reg_5605;
        ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it4;
        ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it5;
        ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 <= ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it6;
        ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4 <= not_or_cond7_demorgan_reg_5610;
        ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it4;
        ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it5;
        ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it6;
        ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 <= ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it7;
        ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4 <= not_or_cond8_demorgan_reg_5615;
        ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it4;
        ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it5;
        ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it6;
        ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 <= ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it7;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4 <= not_or_cond9_demorgan_reg_5620;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it4;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it5;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it6;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it7;
        ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 <= ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it8;
        ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6 <= not_or_cond_reg_5733;
        ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it6;
        ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it7;
        ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9 <= ap_reg_ppstg_not_or_cond_reg_5733_pp0_it8;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it10 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it9;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it10;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it11;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it12;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it13;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it14;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it15;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it16;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it17;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it18;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it2 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it1;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it19;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it20;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it21;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it22;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it23;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it24;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it25;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it26;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it27;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it29 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it28;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it3 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it2;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it30 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it29;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it31 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it30;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it31;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it4 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it3;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it5 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it4;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it6 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it5;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it7 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it6;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it8 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it7;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it9 <= ap_reg_ppstg_or_cond1_reg_5197_pp0_it8;
        ap_reg_ppstg_or_cond2_reg_5660_pp0_it5 <= or_cond2_reg_5660;
        ap_reg_ppstg_or_cond2_reg_5660_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it5;
        ap_reg_ppstg_or_cond2_reg_5660_pp0_it7 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it6;
        ap_reg_ppstg_or_cond2_reg_5660_pp0_it8 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it7;
        ap_reg_ppstg_or_cond2_reg_5660_pp0_it9 <= ap_reg_ppstg_or_cond2_reg_5660_pp0_it8;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it10 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it9;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it11 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it10;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it12 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it11;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it13 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it12;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it14 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it13;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it15 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it14;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it16 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it15;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it17 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it16;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it18 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it17;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it19 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it18;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it2 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it1;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it20 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it19;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it21 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it20;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it22 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it21;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it23 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it22;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it24 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it23;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it25 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it24;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it26 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it25;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it27 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it26;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it28 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it27;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it29 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it28;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it3 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it2;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it30 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it29;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it31 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it30;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it32 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it31;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it33 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it32;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it33;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it4 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it3;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it5 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it4;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it6 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it5;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it7 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it6;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it8 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it7;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it9 <= ap_reg_ppstg_or_cond4_reg_5201_pp0_it8;
        ap_reg_ppstg_or_cond5_reg_5537_pp0_it4 <= or_cond5_reg_5537;
        ap_reg_ppstg_or_cond5_reg_5537_pp0_it5 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it4;
        ap_reg_ppstg_or_cond5_reg_5537_pp0_it6 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it5;
        ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 <= ap_reg_ppstg_or_cond5_reg_5537_pp0_it6;
        ap_reg_ppstg_or_cond6_reg_5543_pp0_it4 <= or_cond6_reg_5543;
        ap_reg_ppstg_or_cond6_reg_5543_pp0_it5 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it4;
        ap_reg_ppstg_or_cond6_reg_5543_pp0_it6 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it5;
        ap_reg_ppstg_or_cond6_reg_5543_pp0_it7 <= ap_reg_ppstg_or_cond6_reg_5543_pp0_it6;
        ap_reg_ppstg_or_cond7_reg_5548_pp0_it4 <= or_cond7_reg_5548;
        ap_reg_ppstg_or_cond7_reg_5548_pp0_it5 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it4;
        ap_reg_ppstg_or_cond7_reg_5548_pp0_it6 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it5;
        ap_reg_ppstg_or_cond7_reg_5548_pp0_it7 <= ap_reg_ppstg_or_cond7_reg_5548_pp0_it6;
        ap_reg_ppstg_or_cond8_reg_5553_pp0_it4 <= or_cond8_reg_5553;
        ap_reg_ppstg_or_cond8_reg_5553_pp0_it5 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it4;
        ap_reg_ppstg_or_cond8_reg_5553_pp0_it6 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it5;
        ap_reg_ppstg_or_cond8_reg_5553_pp0_it7 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it6;
        ap_reg_ppstg_or_cond8_reg_5553_pp0_it8 <= ap_reg_ppstg_or_cond8_reg_5553_pp0_it7;
        ap_reg_ppstg_or_cond9_reg_5559_pp0_it4 <= or_cond9_reg_5559;
        ap_reg_ppstg_or_cond9_reg_5559_pp0_it5 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it4;
        ap_reg_ppstg_or_cond9_reg_5559_pp0_it6 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it5;
        ap_reg_ppstg_or_cond9_reg_5559_pp0_it7 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it6;
        ap_reg_ppstg_or_cond9_reg_5559_pp0_it8 <= ap_reg_ppstg_or_cond9_reg_5559_pp0_it7;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it10 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it9;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it11 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it10;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it12 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it11;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it13 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it12;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it14 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it13;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it15 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it14;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it16 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it15;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it17 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it16;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it18 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it17;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it19 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it18;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it2 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it1;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it20 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it19;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it21 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it20;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it22 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it21;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it23 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it22;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it24 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it23;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it25 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it24;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it26 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it25;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it27 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it26;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it28 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it27;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it29 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it28;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it3 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it2;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it30 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it29;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it31 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it30;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it32 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it31;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it33 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it32;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it4 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it3;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it5 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it4;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it6 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it5;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it7 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it6;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it8 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it7;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it9 <= ap_reg_ppstg_or_cond_reg_5156_pp0_it8;
        ap_reg_ppstg_p_2_reg_515_pp0_it10 <= ap_reg_ppstg_p_2_reg_515_pp0_it9;
        ap_reg_ppstg_p_2_reg_515_pp0_it11 <= ap_reg_ppstg_p_2_reg_515_pp0_it10;
        ap_reg_ppstg_p_2_reg_515_pp0_it12 <= ap_reg_ppstg_p_2_reg_515_pp0_it11;
        ap_reg_ppstg_p_2_reg_515_pp0_it13 <= ap_reg_ppstg_p_2_reg_515_pp0_it12;
        ap_reg_ppstg_p_2_reg_515_pp0_it14 <= ap_reg_ppstg_p_2_reg_515_pp0_it13;
        ap_reg_ppstg_p_2_reg_515_pp0_it15 <= ap_reg_ppstg_p_2_reg_515_pp0_it14;
        ap_reg_ppstg_p_2_reg_515_pp0_it16 <= ap_reg_ppstg_p_2_reg_515_pp0_it15;
        ap_reg_ppstg_p_2_reg_515_pp0_it17 <= ap_reg_ppstg_p_2_reg_515_pp0_it16;
        ap_reg_ppstg_p_2_reg_515_pp0_it18 <= ap_reg_ppstg_p_2_reg_515_pp0_it17;
        ap_reg_ppstg_p_2_reg_515_pp0_it19 <= ap_reg_ppstg_p_2_reg_515_pp0_it18;
        ap_reg_ppstg_p_2_reg_515_pp0_it2 <= ap_reg_ppstg_p_2_reg_515_pp0_it1;
        ap_reg_ppstg_p_2_reg_515_pp0_it20 <= ap_reg_ppstg_p_2_reg_515_pp0_it19;
        ap_reg_ppstg_p_2_reg_515_pp0_it21 <= ap_reg_ppstg_p_2_reg_515_pp0_it20;
        ap_reg_ppstg_p_2_reg_515_pp0_it22 <= ap_reg_ppstg_p_2_reg_515_pp0_it21;
        ap_reg_ppstg_p_2_reg_515_pp0_it23 <= ap_reg_ppstg_p_2_reg_515_pp0_it22;
        ap_reg_ppstg_p_2_reg_515_pp0_it24 <= ap_reg_ppstg_p_2_reg_515_pp0_it23;
        ap_reg_ppstg_p_2_reg_515_pp0_it25 <= ap_reg_ppstg_p_2_reg_515_pp0_it24;
        ap_reg_ppstg_p_2_reg_515_pp0_it26 <= ap_reg_ppstg_p_2_reg_515_pp0_it25;
        ap_reg_ppstg_p_2_reg_515_pp0_it27 <= ap_reg_ppstg_p_2_reg_515_pp0_it26;
        ap_reg_ppstg_p_2_reg_515_pp0_it28 <= ap_reg_ppstg_p_2_reg_515_pp0_it27;
        ap_reg_ppstg_p_2_reg_515_pp0_it29 <= ap_reg_ppstg_p_2_reg_515_pp0_it28;
        ap_reg_ppstg_p_2_reg_515_pp0_it3 <= ap_reg_ppstg_p_2_reg_515_pp0_it2;
        ap_reg_ppstg_p_2_reg_515_pp0_it30 <= ap_reg_ppstg_p_2_reg_515_pp0_it29;
        ap_reg_ppstg_p_2_reg_515_pp0_it31 <= ap_reg_ppstg_p_2_reg_515_pp0_it30;
        ap_reg_ppstg_p_2_reg_515_pp0_it4 <= ap_reg_ppstg_p_2_reg_515_pp0_it3;
        ap_reg_ppstg_p_2_reg_515_pp0_it5 <= ap_reg_ppstg_p_2_reg_515_pp0_it4;
        ap_reg_ppstg_p_2_reg_515_pp0_it6 <= ap_reg_ppstg_p_2_reg_515_pp0_it5;
        ap_reg_ppstg_p_2_reg_515_pp0_it7 <= ap_reg_ppstg_p_2_reg_515_pp0_it6;
        ap_reg_ppstg_p_2_reg_515_pp0_it8 <= ap_reg_ppstg_p_2_reg_515_pp0_it7;
        ap_reg_ppstg_p_2_reg_515_pp0_it9 <= ap_reg_ppstg_p_2_reg_515_pp0_it8;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it10;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it11;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it12;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it14;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4 <= r_V_1_1_reg_5432;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it4;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it5;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it6;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it7;
        ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it9 <= ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it8;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it10;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it11;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it12;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it14;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it15;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it16;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it17;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it18;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it19;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it20;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it21;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it22;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it23;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4 <= r_V_1_2_reg_5452;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it4;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it5;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it6;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it7;
        ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it9 <= ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it8;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it10;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it11;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it12;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it13;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it15;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it16;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4 <= r_V_1_3_reg_5472;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it4;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it5;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it6;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it7;
        ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it9 <= ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it8;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it10;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it11;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it12;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it13;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it15;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it16;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it17;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it18;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it19;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it20;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it21;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it22;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it23;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it24;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it25;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4 <= r_V_1_4_reg_5483;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it4;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it5;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it6;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it7;
        ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it9 <= ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it8;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it10;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it11;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it12;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it13;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it15;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it16;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it17;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it18;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4 <= r_V_1_5_reg_5494;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it4;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it5;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it6;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it7;
        ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it9 <= ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it8;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it10;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it11;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it12;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it13;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it15;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it16;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it17;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it18;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it19;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it20;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it21;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it22;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it23;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it24;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it25;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it26;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it27;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4 <= r_V_1_6_reg_5505;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it5;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it6;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it7;
        ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it9 <= ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it8;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it10;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it11;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it12;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it13;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it15;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it16;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it17;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it18;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it19;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it20;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4 <= r_V_1_7_reg_5516;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it5;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it6;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it7;
        ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it9 <= ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it8;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it10 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it9;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it11 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it10;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it12 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it11;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it13 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it12;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it14 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it13;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it15 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it14;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it16 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it15;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it17 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it16;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it18 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it17;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it19 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it18;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it20 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it19;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it21 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it20;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it22 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it21;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it4 <= r_V_1_reg_5408;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it5 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it4;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it6 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it5;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it7 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it6;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it8 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it7;
        ap_reg_ppstg_r_V_1_reg_5408_pp0_it9 <= ap_reg_ppstg_r_V_1_reg_5408_pp0_it8;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it10 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it9;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it11 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it10;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it12 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it11;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it13 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it12;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it14 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it13;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it15 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it14;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it16 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it15;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it3 <= r_V_2_reg_5290;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it4 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it3;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it5 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it4;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it6 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it5;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it7 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it6;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it8 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it7;
        ap_reg_ppstg_r_V_2_reg_5290_pp0_it9 <= ap_reg_ppstg_r_V_2_reg_5290_pp0_it8;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it10 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it9;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it11 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it10;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it12 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it11;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it13 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it12;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it14 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it13;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it15 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it14;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it16 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it15;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it17 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it16;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it18 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it17;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it19 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it18;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it20 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it19;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it21 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it20;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it22 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it21;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it23 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it22;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it24 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it23;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it25 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it24;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it3 <= r_V_3_reg_5309;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it4 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it3;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it5 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it4;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it6 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it5;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it7 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it6;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it8 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it7;
        ap_reg_ppstg_r_V_3_reg_5309_pp0_it9 <= ap_reg_ppstg_r_V_3_reg_5309_pp0_it8;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it10 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it9;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it11 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it10;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it12 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it11;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it13 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it12;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it14 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it13;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it15 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it14;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it16 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it15;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it17 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it16;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it18 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it17;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it3 <= r_V_4_reg_5328;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it4 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it3;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it5 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it4;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it6 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it5;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it7 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it6;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it8 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it7;
        ap_reg_ppstg_r_V_4_reg_5328_pp0_it9 <= ap_reg_ppstg_r_V_4_reg_5328_pp0_it8;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it10 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it9;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it11 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it10;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it12 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it11;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it13 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it12;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it14 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it13;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it15 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it14;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it16 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it15;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it17 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it16;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it18 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it17;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it19 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it18;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it20 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it19;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it21 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it20;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it22 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it21;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it23 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it22;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it24 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it23;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it25 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it24;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it26 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it25;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it27 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it26;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it3 <= r_V_5_reg_5348;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it4 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it3;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it5 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it4;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it6 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it5;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it7 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it6;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it8 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it7;
        ap_reg_ppstg_r_V_5_reg_5348_pp0_it9 <= ap_reg_ppstg_r_V_5_reg_5348_pp0_it8;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it10 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it9;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it11 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it10;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it12 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it11;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it13 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it12;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it14 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it13;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it15 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it14;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it16 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it15;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it17 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it16;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it18 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it17;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it19 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it18;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it20 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it19;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it3 <= r_V_6_reg_5368;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it4 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it3;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it5 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it4;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it6 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it5;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it7 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it6;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it8 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it7;
        ap_reg_ppstg_r_V_6_reg_5368_pp0_it9 <= ap_reg_ppstg_r_V_6_reg_5368_pp0_it8;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it10 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it9;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it11 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it10;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it12 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it11;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it13 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it12;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it14 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it13;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it15 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it14;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it16 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it15;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it17 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it16;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it18 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it17;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it19 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it18;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it20 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it19;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it21 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it20;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it22 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it21;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it23 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it22;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it24 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it23;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it25 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it24;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it26 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it25;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it27 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it26;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it28 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it27;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it29 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it28;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it3 <= r_V_7_reg_5388;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it4 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it3;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it5 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it4;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it6 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it5;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it7 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it6;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it8 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it7;
        ap_reg_ppstg_r_V_7_reg_5388_pp0_it9 <= ap_reg_ppstg_r_V_7_reg_5388_pp0_it8;
        ap_reg_ppstg_r_V_reg_5252_pp0_it10 <= ap_reg_ppstg_r_V_reg_5252_pp0_it9;
        ap_reg_ppstg_r_V_reg_5252_pp0_it11 <= ap_reg_ppstg_r_V_reg_5252_pp0_it10;
        ap_reg_ppstg_r_V_reg_5252_pp0_it12 <= ap_reg_ppstg_r_V_reg_5252_pp0_it11;
        ap_reg_ppstg_r_V_reg_5252_pp0_it13 <= ap_reg_ppstg_r_V_reg_5252_pp0_it12;
        ap_reg_ppstg_r_V_reg_5252_pp0_it14 <= ap_reg_ppstg_r_V_reg_5252_pp0_it13;
        ap_reg_ppstg_r_V_reg_5252_pp0_it3 <= r_V_reg_5252;
        ap_reg_ppstg_r_V_reg_5252_pp0_it4 <= ap_reg_ppstg_r_V_reg_5252_pp0_it3;
        ap_reg_ppstg_r_V_reg_5252_pp0_it5 <= ap_reg_ppstg_r_V_reg_5252_pp0_it4;
        ap_reg_ppstg_r_V_reg_5252_pp0_it6 <= ap_reg_ppstg_r_V_reg_5252_pp0_it5;
        ap_reg_ppstg_r_V_reg_5252_pp0_it7 <= ap_reg_ppstg_r_V_reg_5252_pp0_it6;
        ap_reg_ppstg_r_V_reg_5252_pp0_it8 <= ap_reg_ppstg_r_V_reg_5252_pp0_it7;
        ap_reg_ppstg_r_V_reg_5252_pp0_it9 <= ap_reg_ppstg_r_V_reg_5252_pp0_it8;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it10 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it9;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it11 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it10;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it12 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it11;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it13 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it12;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it14 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it13;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it15 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it14;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it16 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it15;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it17 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it16;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it18 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it17;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it19 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it18;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it20 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it19;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it21 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it20;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it22 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it21;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it23 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it22;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it3 <= r_V_s_reg_5271;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it4 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it3;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it5 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it4;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it6 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it5;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it7 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it6;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it8 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it7;
        ap_reg_ppstg_r_V_s_reg_5271_pp0_it9 <= ap_reg_ppstg_r_V_s_reg_5271_pp0_it8;
        ap_reg_ppstg_tmp11_reg_5934_pp0_it11 <= tmp11_reg_5934;
        ap_reg_ppstg_tmp12_reg_5883_pp0_it9 <= tmp12_reg_5883;
        ap_reg_ppstg_tmp3_reg_5878_pp0_it10 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it9;
        ap_reg_ppstg_tmp3_reg_5878_pp0_it11 <= ap_reg_ppstg_tmp3_reg_5878_pp0_it10;
        ap_reg_ppstg_tmp3_reg_5878_pp0_it9 <= tmp3_reg_5878;
        ap_reg_ppstg_tmp5_reg_5781_pp0_it6 <= tmp5_reg_5781;
        ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14 <= tmp_200_3_reg_5977;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18 <= tmp_210_2_reg_6169;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it18;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it19;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it20;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it21;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it22;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it23;
        ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25 <= ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it24;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18 <= tmp_210_4_reg_6179;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it18;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it19;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it20;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it21;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it22;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it23;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it24;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it25;
        ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27 <= ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it26;
        ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18 <= tmp_210_7_reg_6139;
        ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19 <= ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it18;
        ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18 <= tmp_210_9_reg_6149;
        ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it18;
        ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it19;
        ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21 <= ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it20;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18 <= tmp_210_s_reg_6159;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it18;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it19;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it20;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it21;
        ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23 <= ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it22;
        ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14 <= tmp_213_3_reg_5982;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18 <= tmp_225_2_reg_6174;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it18;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it19;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it20;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it21;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it22;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it23;
        ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25 <= ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it24;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18 <= tmp_225_4_reg_6184;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it18;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it19;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it20;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it21;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it22;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it23;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it24;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it25;
        ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27 <= ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it26;
        ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18 <= tmp_225_7_reg_6144;
        ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19 <= ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it18;
        ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18 <= tmp_225_9_reg_6154;
        ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it18;
        ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it19;
        ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21 <= ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it20;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18 <= tmp_225_s_reg_6164;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it18;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it19;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it20;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it21;
        ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23 <= ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it22;
        ap_reg_ppstg_tmp_39_reg_5532_pp0_it4 <= tmp_39_reg_5532;
        ap_reg_ppstg_tmp_39_reg_5532_pp0_it5 <= ap_reg_ppstg_tmp_39_reg_5532_pp0_it4;
        ap_reg_ppstg_tmp_53_reg_6719_pp0_it33 <= tmp_53_reg_6719;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        ap_reg_ppstg_exitcond_reg_5147_pp0_it1 <= exitcond_reg_5147;
        ap_reg_ppstg_or_cond1_reg_5197_pp0_it1 <= or_cond1_reg_5197;
        ap_reg_ppstg_or_cond4_reg_5201_pp0_it1 <= or_cond4_reg_5201;
        ap_reg_ppstg_or_cond_reg_5156_pp0_it1 <= or_cond_reg_5156;
        ap_reg_ppstg_p_2_reg_515_pp0_it1 <= p_2_reg_515;
        exitcond_reg_5147 <= exitcond_fu_846_p2;
        win_val_0_V_2_1_reg_5205 <= win_val_0_V_2_fu_172;
        win_val_1_V_4_3_reg_5210 <= win_val_1_V_4_fu_204;
        win_val_2_V_5_3_reg_5215 <= win_val_2_V_5_fu_236;
        win_val_3_V_2_3_reg_5220 <= win_val_3_V_2_fu_252;
        win_val_4_V_5_3_reg_5225 <= win_val_4_V_5_fu_292;
        win_val_5_V_4_3_reg_5230 <= win_val_5_V_4_fu_312;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it15))) begin
        b0_reg_6093 <= b0_fu_3473_p3;
        p_a_0_flag_d_assign_load_5_reg_6077 <= p_a_0_flag_d_assign_load_5_fu_3434_p3;
        tmp_47_reg_6083 <= tmp_47_fu_3447_p3;
        tmp_48_reg_6088 <= tmp_48_fu_3454_p1;
        tmp_71_reg_6099 <= tmp_71_fu_3486_p3;
        tmp_81_reg_6104 <= tmp_81_fu_3493_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))) begin
        b0_tmp_s_reg_6200 <= b0_tmp_s_fu_3680_p3;
        p_a_0_flag_d_assign_load_5_tmp_s_reg_6189 <= p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3;
        tmp_209_1_reg_6195 <= tmp_209_1_fu_3666_p2;
        tmp_221_1_reg_6206 <= tmp_221_1_fu_3686_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it31))) begin
        core_buf_val_0_V_addr_reg_6702 <= tmp_14_fu_4577_p1;
        core_buf_val_1_V_addr_reg_6708 <= tmp_14_fu_4577_p1;
        tmp_53_reg_6719 <= tmp_53_fu_4600_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) begin
        core_buf_val_0_V_load_reg_6724 <= core_buf_val_0_V_q0;
        core_buf_val_1_V_load_reg_6729 <= core_buf_val_1_V_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
        core_win_val_0_V_0_fu_136[0] <= core_win_val_0_V_1_fu_140[0];
core_win_val_0_V_0_fu_136[1] <= core_win_val_0_V_1_fu_140[1];
core_win_val_0_V_0_fu_136[2] <= core_win_val_0_V_1_fu_140[2];
core_win_val_0_V_0_fu_136[3] <= core_win_val_0_V_1_fu_140[3];
core_win_val_0_V_0_fu_136[4] <= core_win_val_0_V_1_fu_140[4];
core_win_val_0_V_0_fu_136[5] <= core_win_val_0_V_1_fu_140[5];
core_win_val_0_V_0_fu_136[6] <= core_win_val_0_V_1_fu_140[6];
core_win_val_0_V_0_fu_136[7] <= core_win_val_0_V_1_fu_140[7];
        core_win_val_0_V_1_fu_140[0] <= core_win_val_0_V_2_fu_4620_p1[0];
core_win_val_0_V_1_fu_140[1] <= core_win_val_0_V_2_fu_4620_p1[1];
core_win_val_0_V_1_fu_140[2] <= core_win_val_0_V_2_fu_4620_p1[2];
core_win_val_0_V_1_fu_140[3] <= core_win_val_0_V_2_fu_4620_p1[3];
core_win_val_0_V_1_fu_140[4] <= core_win_val_0_V_2_fu_4620_p1[4];
core_win_val_0_V_1_fu_140[5] <= core_win_val_0_V_2_fu_4620_p1[5];
core_win_val_0_V_1_fu_140[6] <= core_win_val_0_V_2_fu_4620_p1[6];
core_win_val_0_V_1_fu_140[7] <= core_win_val_0_V_2_fu_4620_p1[7];
        core_win_val_1_V_0_fu_148[0] <= core_win_val_1_V_1_fu_152[0];
core_win_val_1_V_0_fu_148[1] <= core_win_val_1_V_1_fu_152[1];
core_win_val_1_V_0_fu_148[2] <= core_win_val_1_V_1_fu_152[2];
core_win_val_1_V_0_fu_148[3] <= core_win_val_1_V_1_fu_152[3];
core_win_val_1_V_0_fu_148[4] <= core_win_val_1_V_1_fu_152[4];
core_win_val_1_V_0_fu_148[5] <= core_win_val_1_V_1_fu_152[5];
core_win_val_1_V_0_fu_148[6] <= core_win_val_1_V_1_fu_152[6];
core_win_val_1_V_0_fu_148[7] <= core_win_val_1_V_1_fu_152[7];
        core_win_val_1_V_1_fu_152[0] <= core_win_val_1_V_2_fu_4623_p1[0];
core_win_val_1_V_1_fu_152[1] <= core_win_val_1_V_2_fu_4623_p1[1];
core_win_val_1_V_1_fu_152[2] <= core_win_val_1_V_2_fu_4623_p1[2];
core_win_val_1_V_1_fu_152[3] <= core_win_val_1_V_2_fu_4623_p1[3];
core_win_val_1_V_1_fu_152[4] <= core_win_val_1_V_2_fu_4623_p1[4];
core_win_val_1_V_1_fu_152[5] <= core_win_val_1_V_2_fu_4623_p1[5];
core_win_val_1_V_1_fu_152[6] <= core_win_val_1_V_2_fu_4623_p1[6];
core_win_val_1_V_1_fu_152[7] <= core_win_val_1_V_2_fu_4623_p1[7];
        core_win_val_2_V_0_fu_160[0] <= core_win_val_2_V_1_fu_164[0];
core_win_val_2_V_0_fu_160[1] <= core_win_val_2_V_1_fu_164[1];
core_win_val_2_V_0_fu_160[2] <= core_win_val_2_V_1_fu_164[2];
core_win_val_2_V_0_fu_160[3] <= core_win_val_2_V_1_fu_164[3];
core_win_val_2_V_0_fu_160[4] <= core_win_val_2_V_1_fu_164[4];
core_win_val_2_V_0_fu_160[5] <= core_win_val_2_V_1_fu_164[5];
core_win_val_2_V_0_fu_160[6] <= core_win_val_2_V_1_fu_164[6];
core_win_val_2_V_0_fu_160[7] <= core_win_val_2_V_1_fu_164[7];
        core_win_val_2_V_1_fu_164[0] <= core_win_val_2_V_1_2_fu_4643_p1[0];
core_win_val_2_V_1_fu_164[1] <= core_win_val_2_V_1_2_fu_4643_p1[1];
core_win_val_2_V_1_fu_164[2] <= core_win_val_2_V_1_2_fu_4643_p1[2];
core_win_val_2_V_1_fu_164[3] <= core_win_val_2_V_1_2_fu_4643_p1[3];
core_win_val_2_V_1_fu_164[4] <= core_win_val_2_V_1_2_fu_4643_p1[4];
core_win_val_2_V_1_fu_164[5] <= core_win_val_2_V_1_2_fu_4643_p1[5];
core_win_val_2_V_1_fu_164[6] <= core_win_val_2_V_1_2_fu_4643_p1[6];
core_win_val_2_V_1_fu_164[7] <= core_win_val_2_V_1_2_fu_4643_p1[7];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it2) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it2))) begin
        count_1_i_0_op_op87_op_reg_5590[0] <= count_1_i_0_op_op87_op_fu_1848_p3[0];
        flag_val_V_assign_load_1_13_reg_5527 <= flag_val_V_assign_load_1_13_fu_1726_p3;
        flag_val_V_assign_load_1_s_reg_5417 <= flag_val_V_assign_load_1_s_fu_1521_p3;
        not_or_cond6_demorgan_reg_5605 <= not_or_cond6_demorgan_fu_1870_p2;
        not_or_cond7_demorgan_reg_5610 <= not_or_cond7_demorgan_fu_1876_p2;
        not_or_cond8_demorgan_reg_5615 <= not_or_cond8_demorgan_fu_1882_p2;
        not_or_cond9_demorgan_reg_5620 <= not_or_cond9_demorgan_fu_1888_p2;
        or_cond5_reg_5537 <= or_cond5_fu_1746_p2;
        or_cond6_reg_5543 <= or_cond6_fu_1764_p2;
        or_cond7_reg_5548 <= or_cond7_fu_1782_p2;
        or_cond8_reg_5553 <= or_cond8_fu_1800_p2;
        or_cond9_reg_5559 <= or_cond9_fu_1818_p2;
        phitmp3_reg_5422 <= phitmp3_fu_1539_p3;
        phitmp43_op_op_cast_cast_cast_reg_5595[0] <= phitmp43_op_op_cast_cast_cast_fu_1856_p3[0];
        r_V_1_1_reg_5432 <= r_V_1_1_fu_1557_p2;
        r_V_1_2_reg_5452 <= r_V_1_2_fu_1584_p2;
        r_V_1_3_reg_5472 <= r_V_1_3_fu_1611_p2;
        r_V_1_4_reg_5483 <= r_V_1_4_fu_1626_p2;
        r_V_1_5_reg_5494 <= r_V_1_5_fu_1654_p2;
        r_V_1_6_reg_5505 <= r_V_1_6_fu_1682_p2;
        r_V_1_7_reg_5516 <= r_V_1_7_fu_1710_p2;
        r_V_1_reg_5408 <= r_V_1_fu_1516_p2;
        tmp_181_5_not_reg_5566 <= tmp_181_5_not_fu_1824_p2;
        tmp_181_6_not_reg_5578 <= tmp_181_6_not_fu_1836_p2;
        tmp_182_1_reg_5441 <= tmp_182_1_fu_1568_p2;
        tmp_182_2_reg_5461 <= tmp_182_2_fu_1595_p2;
        tmp_183_5_reg_5572 <= tmp_183_5_fu_1830_p2;
        tmp_183_6_reg_5584 <= tmp_183_6_fu_1842_p2;
        tmp_184_1_reg_5447 <= tmp_184_1_fu_1574_p2;
        tmp_184_2_reg_5467 <= tmp_184_2_fu_1601_p2;
        tmp_23_reg_5427 <= tmp_23_fu_1547_p2;
        tmp_39_reg_5532 <= tmp_39_fu_1740_p2;
        tmp_40_reg_5600 <= tmp_40_fu_1864_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it7) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it7))) begin
        count_1_i_12_reg_5872 <= count_1_i_12_fu_2678_p3;
        count_4_reg_5867 <= count_4_fu_2666_p2;
        p_iscorner_0_i_7_reg_5862 <= p_iscorner_0_i_7_fu_2653_p2;
        tmp12_reg_5883 <= tmp12_fu_2694_p2;
        tmp3_reg_5878 <= tmp3_fu_2689_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it8) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it8))) begin
        count_1_i_14_reg_5898 <= count_1_i_14_fu_2755_p3;
        p_iscorner_0_i_11_reg_5888 <= p_iscorner_0_i_11_fu_2725_p2;
        tmp13_reg_5904 <= tmp13_fu_2762_p2;
        tmp_185_13_reg_5893 <= tmp_185_13_fu_2743_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it5) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it5))) begin
        count_1_i_3_reg_5806 <= count_1_i_3_fu_2476_p3;
        not_or_cond13_demorgan_reg_5801 <= not_or_cond13_demorgan_fu_2470_p2;
        not_or_cond14_demorgan_reg_5816 <= not_or_cond14_demorgan_fu_2500_p2;
        or_cond17_reg_5811 <= or_cond17_fu_2494_p2;
        or_cond18_reg_5821 <= or_cond18_fu_2511_p2;
        p_iscorner_0_i_1_reg_5786 <= p_iscorner_0_i_1_fu_2391_p2;
        p_iscorner_0_i_2_reg_5791 <= p_iscorner_0_i_2_fu_2435_p2;
        tmp6_reg_5827 <= tmp6_fu_2516_p2;
        tmp_185_3_reg_5796 <= tmp_185_3_fu_2464_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it3) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it3))) begin
        count_1_i_6_reg_5665 <= count_1_i_6_fu_2036_p3;
        count_1_i_7_reg_5675 <= count_1_i_7_fu_2061_p3;
        flag_val_V_assign_load_1_3_reg_5625 <= flag_val_V_assign_load_1_3_fu_1930_p3;
        flag_val_V_assign_load_1_5_reg_5631 <= flag_val_V_assign_load_1_5_fu_1962_p3;
        not_or_cond10_demorgan_reg_5699 <= not_or_cond10_demorgan_fu_2093_p2;
        not_or_cond11_demorgan_reg_5704 <= not_or_cond11_demorgan_fu_2097_p2;
        or_cond10_reg_5670 <= or_cond10_fu_2055_p2;
        or_cond11_reg_5681 <= or_cond11_fu_2075_p2;
        or_cond2_reg_5660 <= or_cond2_fu_1990_p2;
        tmp_181_9_reg_5687 <= tmp_181_9_fu_2081_p2;
        tmp_182_4_reg_5638 <= tmp_182_4_fu_1970_p2;
        tmp_182_5_reg_5649 <= tmp_182_5_fu_1980_p2;
        tmp_183_9_reg_5693 <= tmp_183_9_fu_2087_p2;
        tmp_184_4_reg_5644 <= tmp_184_4_fu_1975_p2;
        tmp_184_5_reg_5655 <= tmp_184_5_fu_1985_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it4) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it4))) begin
        count_1_i_9_reg_5743 <= count_1_i_9_fu_2257_p3;
        count_1_i_s_reg_5753 <= count_1_i_s_fu_2292_p3;
        flag_val_V_assign_load_1_10_reg_5709 <= flag_val_V_assign_load_1_10_fu_2131_p3;
        flag_val_V_assign_load_1_12_reg_5715 <= flag_val_V_assign_load_1_12_fu_2163_p3;
        not_or_cond3_demorgan_reg_5748 <= not_or_cond3_demorgan_fu_2286_p2;
        not_or_cond4_demorgan_reg_5764 <= not_or_cond4_demorgan_fu_2316_p2;
        not_or_cond_reg_5733 <= not_or_cond_fu_2186_p2;
        or_cond14_reg_5759 <= or_cond14_fu_2310_p2;
        p_iscorner_0_i_9_reg_5738 <= p_iscorner_0_i_9_fu_2251_p2;
        tmp5_reg_5781 <= tmp5_fu_2334_p2;
        tmp_181_2_reg_5769 <= tmp_181_2_fu_2322_p2;
        tmp_182_7_reg_5722 <= tmp_182_7_fu_2171_p2;
        tmp_183_10_reg_5775 <= tmp_183_10_fu_2328_p2;
        tmp_184_7_reg_5728 <= tmp_184_7_fu_2176_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it6))) begin
        count_3_reg_5837 <= count_3_fu_2594_p2;
        p_iscorner_0_i_5_reg_5832 <= p_iscorner_0_i_5_fu_2581_p2;
        tmp4_reg_5847 <= tmp4_fu_2606_p2;
        tmp8_reg_5852 <= tmp8_fu_2610_p2;
        tmp9_reg_5857 <= tmp9_fu_2614_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26))) begin
        flag_d_assign_11_reg_6539 <= flag_d_assign_11_fu_4289_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28))) begin
        flag_d_assign_13_reg_6613 <= flag_d_assign_13_fu_4417_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16))) begin
        flag_d_assign_2_reg_6109 <= flag_d_assign_2_fu_3497_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18))) begin
        flag_d_assign_4_reg_6243 <= flag_d_assign_4_fu_3777_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20))) begin
        flag_d_assign_6_reg_6317 <= flag_d_assign_6_fu_3905_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22))) begin
        flag_d_assign_8_reg_6391 <= flag_d_assign_8_fu_4033_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14))) begin
        flag_d_assign_reg_6011 <= flag_d_assign_fu_3143_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24))) begin
        flag_d_assign_s_reg_6465 <= flag_d_assign_s_fu_4161_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949))) begin
        flag_d_max2_1_reg_5959 <= grp_image_filter_reg_int_s_fu_547_ap_return;
        flag_d_max2_7_reg_5971 <= grp_image_filter_reg_int_s_fu_577_ap_return;
        flag_d_min2_1_reg_5953 <= grp_image_filter_reg_int_s_fu_542_ap_return;
        flag_d_min2_7_reg_5965 <= grp_image_filter_reg_int_s_fu_572_ap_return;
        tmp_200_3_reg_5977 <= tmp_200_3_fu_3031_p3;
        tmp_213_3_reg_5982 <= tmp_213_3_fu_3045_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) begin
        flag_d_max2_9_reg_6023 <= grp_image_filter_reg_int_s_fu_607_ap_return;
        flag_d_max8_1_reg_6036 <= grp_image_filter_reg_int_s_fu_617_ap_return;
        flag_d_min2_9_reg_6017 <= grp_image_filter_reg_int_s_fu_602_ap_return;
        flag_d_min8_1_reg_6029 <= grp_image_filter_reg_int_s_fu_612_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))) begin
        flag_d_max4_1_reg_5993 <= grp_image_filter_reg_int_s_fu_587_ap_return;
        flag_d_max4_5_reg_6005 <= grp_image_filter_reg_int_s_fu_597_ap_return;
        flag_d_min4_1_reg_5987 <= grp_image_filter_reg_int_s_fu_582_ap_return;
        flag_d_min4_5_reg_5999 <= grp_image_filter_reg_int_s_fu_592_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))) begin
        flag_d_max4_3_reg_6059 <= grp_image_filter_reg_int_s_fu_657_ap_return;
        flag_d_max4_7_reg_6071 <= grp_image_filter_reg_int_s_fu_667_ap_return;
        flag_d_min4_3_reg_6053 <= grp_image_filter_reg_int_s_fu_652_ap_return;
        flag_d_min4_7_reg_6065 <= grp_image_filter_reg_int_s_fu_662_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))) begin
        flag_d_max8_3_reg_6122 <= grp_image_filter_reg_int_s_fu_717_ap_return;
        flag_d_min8_3_reg_6115 <= grp_image_filter_reg_int_s_fu_712_ap_return;
        tmp_210_2_reg_6169 <= tmp_210_2_fu_3609_p3;
        tmp_210_4_reg_6179 <= tmp_210_4_fu_3633_p3;
        tmp_210_5_reg_6129 <= tmp_210_5_fu_3505_p3;
        tmp_210_7_reg_6139 <= tmp_210_7_fu_3529_p3;
        tmp_210_9_reg_6149 <= tmp_210_9_fu_3554_p3;
        tmp_210_s_reg_6159 <= tmp_210_s_fu_3582_p3;
        tmp_225_2_reg_6174 <= tmp_225_2_fu_3621_p3;
        tmp_225_4_reg_6184 <= tmp_225_4_fu_3645_p3;
        tmp_225_5_reg_6134 <= tmp_225_5_fu_3517_p3;
        tmp_225_7_reg_6144 <= tmp_225_7_fu_3541_p3;
        tmp_225_9_reg_6154 <= tmp_225_9_fu_3568_p3;
        tmp_225_s_reg_6164 <= tmp_225_s_fu_3596_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18))) begin
        flag_d_max8_5_reg_6256 <= grp_image_filter_reg_int_s_fu_727_ap_return;
        flag_d_min8_5_reg_6249 <= grp_image_filter_reg_int_s_fu_722_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20))) begin
        flag_d_max8_7_reg_6330 <= grp_image_filter_reg_int_s_fu_737_ap_return;
        flag_d_min8_7_reg_6323 <= grp_image_filter_reg_int_s_fu_732_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22))) begin
        flag_d_max8_9_reg_6404 <= grp_image_filter_reg_int_s_fu_747_ap_return;
        flag_d_min8_9_reg_6397 <= grp_image_filter_reg_int_s_fu_742_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        i_V_reg_5122 <= i_V_fu_807_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
        icmp_reg_5142 <= icmp_fu_840_p2;
        tmp_7_reg_5127 <= tmp_7_fu_813_p2;
        tmp_8_reg_5132 <= tmp_8_fu_818_p2;
        tmp_9_reg_5137 <= tmp_9_fu_824_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11))) begin
        iscorner_2_i_s_reg_5949 <= iscorner_2_i_s_fu_2870_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        j_V_reg_5151 <= j_V_fu_851_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == exitcond_fu_846_p2) & ~(ap_const_lv1_0 == or_cond_fu_862_p2))) begin
        k_buf_val_0_V_addr_reg_5161 <= tmp_12_fu_867_p1;
        k_buf_val_1_V_addr_reg_5167 <= tmp_12_fu_867_p1;
        k_buf_val_2_V_addr_reg_5173 <= tmp_12_fu_867_p1;
        k_buf_val_3_V_addr_reg_5179 <= tmp_12_fu_867_p1;
        k_buf_val_4_V_addr_reg_5185 <= tmp_12_fu_867_p1;
        k_buf_val_5_V_addr_reg_5191 <= tmp_12_fu_867_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it1) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it1))) begin
        lhs_V_reg_5240[0] <= lhs_V_fu_1252_p1[0];
lhs_V_reg_5240[1] <= lhs_V_fu_1252_p1[1];
lhs_V_reg_5240[2] <= lhs_V_fu_1252_p1[2];
lhs_V_reg_5240[3] <= lhs_V_fu_1252_p1[3];
lhs_V_reg_5240[4] <= lhs_V_fu_1252_p1[4];
lhs_V_reg_5240[5] <= lhs_V_fu_1252_p1[5];
lhs_V_reg_5240[6] <= lhs_V_fu_1252_p1[6];
lhs_V_reg_5240[7] <= lhs_V_fu_1252_p1[7];
        phitmp1_reg_5261 <= phitmp1_fu_1278_p3;
        phitmp_1_reg_5280 <= phitmp_1_fu_1314_p3;
        phitmp_2_reg_5299 <= phitmp_2_fu_1350_p3;
        phitmp_3_reg_5318 <= phitmp_3_fu_1386_p3;
        r_V_2_reg_5290 <= r_V_2_fu_1332_p2;
        r_V_3_reg_5309 <= r_V_3_fu_1368_p2;
        r_V_4_reg_5328 <= r_V_4_fu_1404_p2;
        r_V_5_reg_5348 <= r_V_5_fu_1426_p2;
        r_V_6_reg_5368 <= r_V_6_fu_1448_p2;
        r_V_7_reg_5388 <= r_V_7_fu_1470_p2;
        r_V_reg_5252 <= r_V_fu_1260_p2;
        r_V_s_reg_5271 <= r_V_s_fu_1296_p2;
        tmp_176_4_reg_5337 <= tmp_176_4_fu_1410_p2;
        tmp_176_5_reg_5357 <= tmp_176_5_fu_1432_p2;
        tmp_176_6_reg_5377 <= tmp_176_6_fu_1454_p2;
        tmp_176_7_reg_5397 <= tmp_176_7_fu_1476_p2;
        tmp_177_4_reg_5343 <= tmp_177_4_fu_1416_p2;
        tmp_177_5_reg_5363 <= tmp_177_5_fu_1438_p2;
        tmp_177_6_reg_5383 <= tmp_177_6_fu_1460_p2;
        tmp_177_7_reg_5403 <= tmp_177_7_fu_1482_p2;
        tmp_20_reg_5266 <= tmp_20_fu_1286_p2;
        tmp_24_reg_5285 <= tmp_24_fu_1322_p2;
        tmp_27_reg_5304 <= tmp_27_fu_1358_p2;
        tmp_29_reg_5323 <= tmp_29_fu_1394_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it9) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it9))) begin
        not_or_cond11_reg_5919 <= not_or_cond11_fu_2817_p2;
        p_iscorner_0_i_13_reg_5909 <= p_iscorner_0_i_13_fu_2787_p2;
        tmp11_reg_5934 <= tmp11_fu_2833_p2;
        tmp15_reg_5939 <= tmp15_fu_2837_p2;
        tmp2_reg_5929 <= tmp2_fu_2828_p2;
        tmp_185_15_reg_5914 <= tmp_185_15_fu_2805_p2;
        tmp_185_16_reg_5924 <= tmp_185_16_fu_2822_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == exitcond_fu_846_p2))) begin
        or_cond1_reg_5197 <= or_cond1_fu_883_p2;
        or_cond4_reg_5201 <= or_cond4_fu_904_p2;
        or_cond_reg_5156 <= or_cond_fu_862_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond5_reg_5537_pp0_it6))) begin
        phitmp8_reg_5842 <= phitmp8_fu_2600_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it10) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it10))) begin
        tmp14_reg_5944 <= tmp14_fu_2861_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
        tmp19_reg_6739 <= tmp19_fu_4701_p2;
        tmp20_reg_6744 <= tmp20_fu_4712_p2;
        tmp23_reg_6749 <= tmp23_fu_4723_p2;
        tmp25_reg_6754 <= tmp25_fu_4735_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it31) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it31))) begin
        tmp_100_v_reg_6714 <= tmp_100_v_fu_4593_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_180)) begin
        tmp_15_reg_5103 <= tmp_15_fu_786_p1;
        tmp_5_reg_5113 <= tmp_5_fu_796_p2;
        tmp_reg_5098 <= tmp_fu_782_p1;
        tmp_s_reg_5108 <= tmp_s_fu_790_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26))) begin
        tmp_211_1_reg_6545 <= grp_image_filter_reg_int_s_fu_762_ap_return;
        tmp_226_1_reg_6552 <= grp_image_filter_reg_int_s_fu_767_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28))) begin
        tmp_211_2_reg_6619 <= grp_image_filter_reg_int_s_fu_772_ap_return;
        tmp_226_2_reg_6626 <= grp_image_filter_reg_int_s_fu_777_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24))) begin
        tmp_211_s_reg_6471 <= grp_image_filter_reg_int_s_fu_752_ap_return;
        tmp_226_s_reg_6478 <= grp_image_filter_reg_int_s_fu_757_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))) begin
        tmp_43_reg_6043 <= tmp_43_fu_3262_p2;
        tmp_67_reg_6048 <= tmp_67_fu_3268_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it1) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond_reg_5156_pp0_it1))) begin
        win_val_0_V_2_3_fu_168 <= win_val_0_V_2_1_reg_5205;
        win_val_1_V_1_3_fu_188 <= win_val_1_V_1_fu_192;
        win_val_1_V_1_fu_192 <= win_val_1_V_2_fu_196;
        win_val_1_V_2_fu_196 <= win_val_1_V_3_fu_200;
        win_val_1_V_3_fu_200 <= win_val_1_V_4_3_reg_5210;
        win_val_2_V_0_3_fu_212 <= win_val_2_V_0_fu_216;
        win_val_2_V_0_fu_216 <= win_val_2_V_1_fu_220;
        win_val_2_V_1_fu_220 <= win_val_2_V_2_fu_224;
        win_val_2_V_2_fu_224 <= win_val_2_V_3_fu_228;
        win_val_2_V_3_fu_228 <= win_val_2_V_4_fu_232;
        win_val_2_V_4_fu_232 <= win_val_2_V_5_3_reg_5215;
        win_val_3_V_0_3_fu_240 <= win_val_3_V_0_fu_244;
        win_val_3_V_0_fu_244 <= win_val_3_V_1_fu_248;
        win_val_3_V_1_fu_248 <= win_val_3_V_2_3_reg_5220;
        win_val_4_V_0_3_fu_268 <= win_val_4_V_0_fu_272;
        win_val_4_V_0_fu_272 <= win_val_4_V_1_fu_276;
        win_val_4_V_1_fu_276 <= win_val_4_V_2_fu_280;
        win_val_4_V_2_fu_280 <= win_val_4_V_3_fu_284;
        win_val_4_V_3_fu_284 <= win_val_4_V_4_fu_288;
        win_val_4_V_4_fu_288 <= win_val_4_V_5_3_reg_5225;
        win_val_5_V_1_3_fu_296 <= win_val_5_V_1_fu_300;
        win_val_5_V_1_fu_300 <= win_val_5_V_2_fu_304;
        win_val_5_V_2_fu_304 <= win_val_5_V_3_fu_308;
        win_val_5_V_3_fu_308 <= win_val_5_V_4_3_reg_5230;
        win_val_6_V_2_3_fu_320 <= win_val_6_V_2_fu_324;
        win_val_6_V_2_fu_324 <= win_val_6_V_2_2_reg_5235;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        win_val_0_V_2_fu_172 <= win_val_0_V_3_fu_176;
        win_val_0_V_3_fu_176 <= win_val_0_V_4_fu_180;
        win_val_0_V_4_fu_180 <= win_val_0_V_5_fu_184;
        win_val_0_V_5_fu_184 <= k_buf_val_0_V_q0;
        win_val_1_V_4_fu_204 <= win_val_1_V_5_fu_208;
        win_val_1_V_5_fu_208 <= k_buf_val_1_V_q0;
        win_val_2_V_5_fu_236 <= k_buf_val_2_V_q0;
        win_val_3_V_2_fu_252 <= win_val_3_V_3_fu_256;
        win_val_3_V_3_fu_256 <= win_val_3_V_4_fu_260;
        win_val_3_V_4_fu_260 <= win_val_3_V_5_fu_264;
        win_val_3_V_5_fu_264 <= k_buf_val_3_V_q0;
        win_val_4_V_5_fu_292 <= k_buf_val_4_V_q0;
        win_val_5_V_4_fu_312 <= win_val_5_V_5_fu_316;
        win_val_5_V_5_fu_316 <= k_buf_val_5_V_q0;
        win_val_6_V_3_fu_156 <= win_val_6_V_4_fu_144;
        win_val_6_V_4_fu_144 <= win_val_6_V_5_fu_132;
        win_val_6_V_5_fu_132 <= p_src_data_stream_V_dout;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        win_val_6_V_2_2_reg_5235 <= win_val_6_V_3_fu_156;
    end
end

/// ap_done assign process. ///
always @ (ap_done_reg or exitcond1_fu_802_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
    if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2)))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (exitcond1_fu_802_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == exitcond1_fu_802_p2))) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_48)
begin
    if (ap_sig_bdd_48) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
    if (ap_sig_bdd_23) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_196)
begin
    if (ap_sig_bdd_196) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st39_fsm_3 assign process. ///
always @ (ap_sig_bdd_2075)
begin
    if (ap_sig_bdd_2075) begin
        ap_sig_cseq_ST_st39_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st39_fsm_3 = ap_const_logic_0;
    end
end

/// core_buf_val_0_V_ce0 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it32 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        core_buf_val_0_V_ce0 = ap_const_logic_1;
    end else begin
        core_buf_val_0_V_ce0 = ap_const_logic_0;
    end
end

/// core_buf_val_0_V_ce1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        core_buf_val_0_V_ce1 = ap_const_logic_1;
    end else begin
        core_buf_val_0_V_ce1 = ap_const_logic_0;
    end
end

/// core_buf_val_0_V_we1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it32)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32))) begin
        core_buf_val_0_V_we1 = ap_const_logic_1;
    end else begin
        core_buf_val_0_V_we1 = ap_const_logic_0;
    end
end

/// core_buf_val_1_V_ce0 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it32 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it32) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        core_buf_val_1_V_ce0 = ap_const_logic_1;
    end else begin
        core_buf_val_1_V_ce0 = ap_const_logic_0;
    end
end

/// core_buf_val_1_V_ce1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        core_buf_val_1_V_ce1 = ap_const_logic_1;
    end else begin
        core_buf_val_1_V_ce1 = ap_const_logic_0;
    end
end

/// core_buf_val_1_V_we1 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it33)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it33))) begin
        core_buf_val_1_V_we1 = ap_const_logic_1;
    end else begin
        core_buf_val_1_V_we1 = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_542_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_542_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_542_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_547_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_547_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_547_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_552_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_552_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_552_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_557_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_557_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_557_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_562_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_562_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_562_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_567_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_567_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_567_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_572_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_572_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_572_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_577_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or iscorner_2_i_s_fu_2870_p2 or iscorner_2_i_s_reg_5949)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & ~(ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2))))) begin
        grp_image_filter_reg_int_s_fu_577_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_577_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_582_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
        grp_image_filter_reg_int_s_fu_582_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_582_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_587_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
        grp_image_filter_reg_int_s_fu_587_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_587_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_592_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
        grp_image_filter_reg_int_s_fu_592_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_592_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_597_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it12 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it12 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or iscorner_2_i_s_reg_5949 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it12) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it12) & ~(ap_const_lv1_0 == iscorner_2_i_s_reg_5949)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13))))) begin
        grp_image_filter_reg_int_s_fu_597_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_597_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_602_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
        grp_image_filter_reg_int_s_fu_602_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_602_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_607_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
        grp_image_filter_reg_int_s_fu_607_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_607_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_612_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
        grp_image_filter_reg_int_s_fu_612_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_612_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_617_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it13 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it13 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it13) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it13)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14))))) begin
        grp_image_filter_reg_int_s_fu_617_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_617_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_622_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_622_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_622_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_627_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_627_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_627_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_632_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_632_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_632_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_637_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_637_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_637_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_642_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_642_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_642_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_647_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_647_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_647_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_652_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_652_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_652_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_657_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_657_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_657_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_662_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_662_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_662_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_667_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it14 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it14 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it14) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it14)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15))))) begin
        grp_image_filter_reg_int_s_fu_667_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_667_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_672_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_672_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_672_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_677_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_677_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_677_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_682_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_682_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_682_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_687_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_687_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_687_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_692_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_692_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_692_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_697_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_697_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_697_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_702_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_702_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_702_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_707_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_707_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_707_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_712_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_712_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_712_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_717_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it15 or ap_reg_ppstg_exitcond_reg_5147_pp0_it16 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it15 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it16 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it15) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it15)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it16) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it16))))) begin
        grp_image_filter_reg_int_s_fu_717_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_717_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_722_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it17 or ap_reg_ppstg_exitcond_reg_5147_pp0_it18 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))))) begin
        grp_image_filter_reg_int_s_fu_722_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_722_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_727_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it17 or ap_reg_ppstg_exitcond_reg_5147_pp0_it18 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it17 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it18 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it18) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it18)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it17) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it17))))) begin
        grp_image_filter_reg_int_s_fu_727_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_727_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_732_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it19 or ap_reg_ppstg_exitcond_reg_5147_pp0_it20 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))))) begin
        grp_image_filter_reg_int_s_fu_732_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_732_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_737_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it19 or ap_reg_ppstg_exitcond_reg_5147_pp0_it20 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it19 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it20 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it20) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it20)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it19) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it19))))) begin
        grp_image_filter_reg_int_s_fu_737_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_737_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_742_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it21 or ap_reg_ppstg_exitcond_reg_5147_pp0_it22 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))))) begin
        grp_image_filter_reg_int_s_fu_742_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_742_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_747_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it21 or ap_reg_ppstg_exitcond_reg_5147_pp0_it22 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it21 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it22 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it22) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it22)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it21) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it21))))) begin
        grp_image_filter_reg_int_s_fu_747_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_747_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_752_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it23 or ap_reg_ppstg_exitcond_reg_5147_pp0_it24 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))))) begin
        grp_image_filter_reg_int_s_fu_752_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_752_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_757_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it23 or ap_reg_ppstg_exitcond_reg_5147_pp0_it24 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it23 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it24 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it24) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it24)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it23) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it23))))) begin
        grp_image_filter_reg_int_s_fu_757_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_757_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_762_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it25 or ap_reg_ppstg_exitcond_reg_5147_pp0_it26 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))))) begin
        grp_image_filter_reg_int_s_fu_762_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_762_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_767_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it25 or ap_reg_ppstg_exitcond_reg_5147_pp0_it26 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it25 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it26 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it26) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it26)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it25) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it25))))) begin
        grp_image_filter_reg_int_s_fu_767_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_767_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_772_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it27 or ap_reg_ppstg_exitcond_reg_5147_pp0_it28 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))))) begin
        grp_image_filter_reg_int_s_fu_772_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_772_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_reg_int_s_fu_777_ap_ce assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_reg_ppstg_exitcond_reg_5147_pp0_it27 or ap_reg_ppstg_exitcond_reg_5147_pp0_it28 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it27 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it28 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & (((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it28) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it28)) | ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it27) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it27))))) begin
        grp_image_filter_reg_int_s_fu_777_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_reg_int_s_fu_777_ap_ce = ap_const_logic_0;
    end
end

/// k_buf_val_0_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_0_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_0_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_0_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_0_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_0_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_0_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_0_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_0_V_we1 = ap_const_logic_0;
    end
end

/// k_buf_val_1_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_1_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_1_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_1_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_1_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_1_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_1_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_1_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_1_V_we1 = ap_const_logic_0;
    end
end

/// k_buf_val_2_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_2_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_2_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_2_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_2_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_2_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_2_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_2_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_2_V_we1 = ap_const_logic_0;
    end
end

/// k_buf_val_3_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_3_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_3_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_3_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_3_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_3_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_3_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_3_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_3_V_we1 = ap_const_logic_0;
    end
end

/// k_buf_val_4_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_4_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_4_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_4_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_4_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_4_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_4_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_4_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_4_V_we1 = ap_const_logic_0;
    end
end

/// k_buf_val_5_V_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_5_V_ce0 = ap_const_logic_1;
    end else begin
        k_buf_val_5_V_ce0 = ap_const_logic_0;
    end
end

/// k_buf_val_5_V_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_5_V_ce1 = ap_const_logic_1;
    end else begin
        k_buf_val_5_V_ce1 = ap_const_logic_0;
    end
end

/// k_buf_val_5_V_we1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        k_buf_val_5_V_we1 = ap_const_logic_1;
    end else begin
        k_buf_val_5_V_we1 = ap_const_logic_0;
    end
end

/// p_2_phi_fu_519_p4 assign process. ///
always @ (p_2_reg_515 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or ap_reg_ppiten_pp0_it1 or j_V_reg_5151)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
        p_2_phi_fu_519_p4 = j_V_reg_5151;
    end else begin
        p_2_phi_fu_519_p4 = p_2_reg_515;
    end
end

/// p_mask_data_stream_V_write assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppstg_or_cond4_reg_5201_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_lv1_0 == ap_reg_ppstg_or_cond4_reg_5201_pp0_it34) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        p_mask_data_stream_V_write = ap_const_logic_1;
    end else begin
        p_mask_data_stream_V_write = ap_const_logic_0;
    end
end

/// p_src_data_stream_V_read assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or exitcond_reg_5147 or or_cond_reg_5156 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))))) begin
        p_src_data_stream_V_read = ap_const_logic_1;
    end else begin
        p_src_data_stream_V_read = ap_const_logic_0;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_reg_ppiten_pp0_it34 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35 or ap_sig_bdd_180 or exitcond1_fu_802_p2)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~ap_sig_bdd_180) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            if (~(ap_const_lv1_0 == exitcond1_fu_802_p2)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
            end
        end
        ap_ST_pp0_stg0_fsm_2 : 
        begin
            if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33))) begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
            end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it34) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it33))) begin
                ap_NS_fsm = ap_ST_st39_fsm_3;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
            end
        end
        ap_ST_st39_fsm_3 : 
        begin
            ap_NS_fsm = ap_ST_st2_fsm_1;
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign a0_2_cast_fu_3908_p1 = a0_2_reg_6285;
assign a0_2_fu_3841_p3 = ((tmp_217_2_fu_3835_p2)? a0_tmp_232_1_reg_6263: tmp_58_fu_3831_p1);
assign a0_2_tmp_232_2_cast_fu_3951_p1 = a0_2_tmp_232_2_reg_6337;
assign a0_2_tmp_232_2_fu_3916_p3 = ((tmp_233_2_fu_3911_p2)? a0_2_reg_6285: tmp_59_reg_6296);
assign a0_3_cast_fu_4036_p1 = a0_3_reg_6359;
assign a0_3_fu_3969_p3 = ((tmp_217_3_fu_3963_p2)? a0_2_tmp_232_2_reg_6337: tmp_60_fu_3959_p1);
assign a0_3_tmp_232_3_cast_fu_4079_p1 = a0_3_tmp_232_3_reg_6411;
assign a0_3_tmp_232_3_fu_4044_p3 = ((tmp_233_3_fu_4039_p2)? a0_3_reg_6359: tmp_61_reg_6370);
assign a0_4_cast_fu_4164_p1 = a0_4_reg_6433;
assign a0_4_fu_4097_p3 = ((tmp_217_4_fu_4091_p2)? a0_3_tmp_232_3_reg_6411: tmp_62_fu_4087_p1);
assign a0_4_tmp_232_4_cast_fu_4207_p1 = a0_4_tmp_232_4_reg_6485;
assign a0_4_tmp_232_4_fu_4172_p3 = ((tmp_233_4_fu_4167_p2)? a0_4_reg_6433: tmp_63_reg_6444);
assign a0_5_cast_fu_4292_p1 = a0_5_reg_6507;
assign a0_5_fu_4225_p3 = ((tmp_217_5_fu_4219_p2)? a0_4_tmp_232_4_reg_6485: tmp_64_fu_4215_p1);
assign a0_5_tmp_232_5_cast_fu_4335_p1 = a0_5_tmp_232_5_reg_6559;
assign a0_5_tmp_232_5_fu_4300_p3 = ((tmp_233_5_fu_4295_p2)? a0_5_reg_6507: tmp_65_reg_6518);
assign a0_6_cast_fu_4420_p1 = a0_6_reg_6581;
assign a0_6_fu_4353_p3 = ((tmp_217_6_fu_4347_p2)? a0_5_tmp_232_5_reg_6559: tmp_66_fu_4343_p1);
assign a0_6_tmp_232_6_cast_fu_4463_p1 = a0_6_tmp_232_6_reg_6633;
assign a0_6_tmp_232_6_fu_4428_p3 = ((tmp_233_6_fu_4423_p2)? a0_6_reg_6581: tmp_75_reg_6592);
assign a0_7_cast_fu_4549_p1 = a0_7_reg_6655;
assign a0_7_fu_4481_p3 = ((tmp_217_7_fu_4475_p2)? a0_6_tmp_232_6_reg_6633: tmp_77_fu_4471_p1);
assign a0_7_tmp_232_7_fu_4557_p3 = ((tmp_233_7_fu_4552_p2)? a0_7_reg_6655: tmp_78_reg_6666);
assign a0_cast_fu_3780_p1 = a0_s_reg_6211;
assign a0_s_fu_3713_p3 = ((tmp_217_1_fu_3707_p2)? p_a_0_flag_d_assign_load_5_tmp_s_reg_6189: tmp_56_fu_3703_p1);
assign a0_tmp_232_1_cast_fu_3823_p1 = a0_tmp_232_1_reg_6263;
assign a0_tmp_232_1_fu_3788_p3 = ((tmp_233_1_fu_3783_p2)? a0_s_reg_6211: tmp_57_reg_6222);
assign a_0_flag_d_assign_load_5_fu_3419_p3 = ((tmp_43_reg_6043)? flag_d_min8_1_reg_6029: flag_d_assign_reg_6011);
assign ap_reg_phiprechg_core_1_reg_527pp0_it0 = 'bx;

/// ap_sig_bdd_136 assign process. ///
always @ (p_mask_data_stream_V_full_n or ap_reg_ppstg_or_cond4_reg_5201_pp0_it34)
begin
    ap_sig_bdd_136 = ((p_mask_data_stream_V_full_n == ap_const_logic_0) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond4_reg_5201_pp0_it34));
end

/// ap_sig_bdd_1776 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it33 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    ap_sig_bdd_1776 = ((ap_const_logic_1 == ap_reg_ppiten_pp0_it33) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end

/// ap_sig_bdd_180 assign process. ///
always @ (ap_start or ap_done_reg)
begin
    ap_sig_bdd_180 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end

/// ap_sig_bdd_196 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_196 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_2075 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_2075 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_2108 assign process. ///
always @ (ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it12 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    ap_sig_bdd_2108 = ((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end

/// ap_sig_bdd_2152 assign process. ///
always @ (exitcond_fu_846_p2 or or_cond1_fu_883_p2)
begin
    ap_sig_bdd_2152 = ((ap_const_lv1_0 == exitcond_fu_846_p2) & (ap_const_lv1_0 == or_cond1_fu_883_p2));
end

/// ap_sig_bdd_2156 assign process. ///
always @ (ap_reg_ppstg_exitcond_reg_5147_pp0_it32 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it32 or ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32)
begin
    ap_sig_bdd_2156 = ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it32) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it32) & ~(ap_const_lv1_0 == ap_reg_ppstg_iscorner_2_i_s_reg_5949_pp0_it32));
end

/// ap_sig_bdd_2159 assign process. ///
always @ (ap_reg_ppstg_exitcond_reg_5147_pp0_it11 or ap_reg_ppstg_or_cond1_reg_5197_pp0_it11 or iscorner_2_i_s_fu_2870_p2)
begin
    ap_sig_bdd_2159 = ((ap_const_lv1_0 == ap_reg_ppstg_exitcond_reg_5147_pp0_it11) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond1_reg_5197_pp0_it11) & (ap_const_lv1_0 == iscorner_2_i_s_fu_2870_p2));
end

/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_250 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_61 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_136 or ap_reg_ppiten_pp0_it35)
begin
    ap_sig_bdd_250 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_61 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) | (ap_sig_bdd_136 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it35))));
end

/// ap_sig_bdd_48 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_48 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end

/// ap_sig_bdd_61 assign process. ///
always @ (p_src_data_stream_V_empty_n or exitcond_reg_5147 or or_cond_reg_5156)
begin
    ap_sig_bdd_61 = ((p_src_data_stream_V_empty_n == ap_const_logic_0) & (exitcond_reg_5147 == ap_const_lv1_0) & ~(ap_const_lv1_0 == or_cond_reg_5156));
end
assign b0_2_cast_fu_3928_p1 = $signed(b0_2_reg_6301);
assign b0_2_fu_3882_p3 = ((tmp_228_2_fu_3876_p2)? b0_tmp_239_1_reg_6274: tmp_84_fu_3872_p1);
assign b0_2_tmp_239_2_cast_fu_3992_p1 = $signed(b0_2_tmp_239_2_reg_6348);
assign b0_2_tmp_239_2_fu_3936_p3 = ((tmp_240_2_fu_3931_p2)? b0_2_reg_6301: tmp_85_reg_6312);
assign b0_3_cast_fu_4056_p1 = $signed(b0_3_reg_6375);
assign b0_3_fu_4010_p3 = ((tmp_228_3_fu_4004_p2)? b0_2_tmp_239_2_reg_6348: tmp_86_fu_4000_p1);
assign b0_3_tmp_239_3_cast_fu_4120_p1 = $signed(b0_3_tmp_239_3_reg_6422);
assign b0_3_tmp_239_3_fu_4064_p3 = ((tmp_240_3_fu_4059_p2)? b0_3_reg_6375: tmp_87_reg_6386);
assign b0_4_cast_fu_4184_p1 = $signed(b0_4_reg_6449);
assign b0_4_fu_4138_p3 = ((tmp_228_4_fu_4132_p2)? b0_3_tmp_239_3_reg_6422: tmp_88_fu_4128_p1);
assign b0_4_tmp_239_4_cast_fu_4248_p1 = $signed(b0_4_tmp_239_4_reg_6496);
assign b0_4_tmp_239_4_fu_4192_p3 = ((tmp_240_4_fu_4187_p2)? b0_4_reg_6449: tmp_89_reg_6460);
assign b0_5_cast_fu_4312_p1 = $signed(b0_5_reg_6523);
assign b0_5_fu_4266_p3 = ((tmp_228_5_fu_4260_p2)? b0_4_tmp_239_4_reg_6496: tmp_90_fu_4256_p1);
assign b0_5_tmp_239_5_cast_fu_4376_p1 = $signed(b0_5_tmp_239_5_reg_6570);
assign b0_5_tmp_239_5_fu_4320_p3 = ((tmp_240_5_fu_4315_p2)? b0_5_reg_6523: tmp_91_reg_6534);
assign b0_6_cast_fu_4440_p1 = $signed(b0_6_reg_6597);
assign b0_6_fu_4394_p3 = ((tmp_228_6_fu_4388_p2)? b0_5_tmp_239_5_reg_6570: tmp_92_fu_4384_p1);
assign b0_6_tmp_239_6_cast_fu_4504_p1 = $signed(b0_6_tmp_239_6_reg_6644);
assign b0_6_tmp_239_6_fu_4448_p3 = ((tmp_240_6_fu_4443_p2)? b0_6_reg_6597: tmp_93_reg_6608);
assign b0_7_cast_fu_4563_p1 = $signed(b0_7_reg_6671);
assign b0_7_fu_4522_p3 = ((tmp_228_7_fu_4516_p2)? b0_6_tmp_239_6_reg_6644: tmp_94_fu_4512_p1);
assign b0_cast_50_fu_3800_p1 = $signed(b0_s_reg_6227);
assign b0_cast_fu_3672_p1 = $signed(b0_reg_6093);
assign b0_fu_3473_p3 = ((tmp_69_fu_3467_p2)? ap_const_lv9_1EC: tmp_80_fu_3463_p1);
assign b0_s_fu_3754_p3 = ((tmp_228_1_fu_3748_p2)? b0_tmp_s_reg_6200: tmp_82_fu_3744_p1);
assign b0_tmp_239_1_cast_fu_3864_p1 = $signed(b0_tmp_239_1_reg_6274);
assign b0_tmp_239_1_fu_3808_p3 = ((tmp_240_1_fu_3803_p2)? b0_s_reg_6227: tmp_83_reg_6238);
assign b0_tmp_239_cast_fu_3736_p1 = $signed(b0_tmp_s_reg_6200);
assign b0_tmp_s_fu_3680_p3 = ((tmp_72_fu_3675_p2)? b0_reg_6093: tmp_81_reg_6104);
assign core_buf_val_0_V_address0 = tmp_14_fu_4577_p1;
assign core_buf_val_0_V_address1 = core_buf_val_0_V_addr_reg_6702;
assign core_buf_val_0_V_d1 = core_buf_val_1_V_q0;
assign core_buf_val_1_V_address0 = tmp_14_fu_4577_p1;
assign core_buf_val_1_V_address1 = ap_reg_ppstg_core_buf_val_1_V_addr_reg_6708_pp0_it33;
assign core_buf_val_1_V_d1 = core_win_val_2_V_2_fu_4635_p3;
assign core_win_val_0_V_2_fu_4620_p1 = core_buf_val_0_V_load_reg_6724;
assign core_win_val_1_V_2_fu_4623_p1 = core_buf_val_1_V_load_reg_6729;
assign core_win_val_2_V_1_2_fu_4643_p1 = core_win_val_2_V_2_fu_4635_p3;
assign core_win_val_2_V_2_fu_4635_p3 = ((ap_reg_ppstg_or_cond_reg_5156_pp0_it33)? ap_reg_phiprechg_core_1_reg_527pp0_it34: ap_const_lv8_0);
assign count_1_fu_2407_p2 = (count_1_i_1_fu_2397_p3 + ap_const_lv4_1);
assign count_1_i_0_op_op87_op_fu_1848_p3 = ((or_cond5_fu_1746_p2)? ap_const_lv4_8: ap_const_lv4_9);
assign count_1_i_10_fu_2636_p3 = ((ap_reg_ppstg_or_cond5_reg_5537_pp0_it7)? ap_const_lv5_2: phitmp8_reg_5842);
assign count_1_i_11_fu_2659_p3 = ((ap_reg_ppstg_or_cond6_reg_5543_pp0_it7)? ap_const_lv5_1: count_1_i_10_fu_2636_p3);
assign count_1_i_12_fu_2678_p3 = ((ap_reg_ppstg_or_cond7_reg_5548_pp0_it7)? ap_const_lv5_2: phitmp9_fu_2672_p2);
assign count_1_i_13_fu_2731_p3 = ((ap_reg_ppstg_or_cond8_reg_5553_pp0_it8)? ap_const_lv5_1: count_1_i_12_reg_5872);
assign count_1_i_14_fu_2755_p3 = ((ap_reg_ppstg_or_cond9_reg_5559_pp0_it8)? ap_const_lv5_2: phitmp10_fu_2749_p2);
assign count_1_i_15_fu_2793_p3 = ((ap_reg_ppstg_or_cond2_reg_5660_pp0_it9)? ap_const_lv5_1: count_1_i_14_reg_5898);
assign count_1_i_1_fu_2397_p3 = ((or_cond14_reg_5759)? ap_const_lv4_1: count_1_i_s_reg_5753);
assign count_1_i_2_fu_2441_p3 = ((or_cond15_fu_2403_p2)? ap_const_lv4_2: phitmp6_fu_2419_p2);
assign count_1_i_2_op_op_fu_1998_p3 = ((tmp_40_reg_5600)? phitmp43_op_op_cast_cast_cast_reg_5595: count_1_i_0_op_op87_op_reg_5590);
assign count_1_i_3_cast_fu_2531_p1 = count_1_i_3_reg_5806;
assign count_1_i_3_fu_2476_p3 = ((or_cond16_fu_2458_p2)? ap_const_lv4_1: count_1_i_2_fu_2441_p3);
assign count_1_i_4_fu_2563_p3 = ((or_cond17_reg_5811)? ap_const_lv5_2: phitmp7_fu_2546_p2);
assign count_1_i_4_op_fu_2014_p3 = ((tmp_41_fu_2010_p2)? phitmp42_op_cast_cast_cast_fu_2003_p3: count_1_i_2_op_op_fu_1998_p3);
assign count_1_i_5_fu_2587_p3 = ((or_cond18_reg_5821)? ap_const_lv5_1: count_1_i_4_fu_2563_p3);
assign count_1_i_6_fu_2036_p3 = ((tmp_42_fu_2030_p2)? phitmp3_cast_cast_cast_fu_2022_p3: count_1_i_4_op_fu_2014_p3);
assign count_1_i_7_fu_2061_p3 = ((or_cond10_fu_2055_p2)? ap_const_lv4_1: count_1_i_6_fu_2036_p3);
assign count_1_i_8_fu_2224_p3 = ((or_cond11_reg_5681)? ap_const_lv4_2: phitmp4_fu_2208_p2);
assign count_1_i_9_fu_2257_p3 = ((or_cond12_fu_2231_p2)? ap_const_lv4_1: count_1_i_8_fu_2224_p3);
assign count_1_i_s_fu_2292_p3 = ((or_cond13_fu_2274_p2)? ap_const_lv4_2: phitmp5_fu_2280_p2);
assign count_2_fu_2534_p2 = (count_1_i_3_cast_fu_2531_p1 + ap_const_lv5_1);
assign count_3_fu_2594_p2 = (count_1_i_5_fu_2587_p3 + ap_const_lv5_1);
assign count_4_fu_2666_p2 = (count_1_i_11_fu_2659_p3 + ap_const_lv5_1);
assign count_5_fu_2737_p2 = (count_1_i_13_fu_2731_p3 + ap_const_lv5_1);
assign count_6_fu_2799_p2 = (count_1_i_15_fu_2793_p3 + ap_const_lv5_1);
assign count_8_fu_2197_p2 = (count_1_i_7_reg_5675 + ap_const_lv4_1);
assign count_s_fu_2359_p2 = (count_1_i_9_reg_5743 + ap_const_lv4_1);
assign exitcond1_fu_802_p2 = (p_s_reg_504 == tmp_5_reg_5113? 1'b1: 1'b0);
assign exitcond_fu_846_p2 = (p_2_phi_fu_519_p4 == tmp_s_reg_5108? 1'b1: 1'b0);
assign flag_d_assign_10_fu_3692_p1 = $signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it17);
assign flag_d_assign_11_fu_4289_p1 = $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it26);
assign flag_d_assign_12_fu_3820_p1 = $signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it19);
assign flag_d_assign_13_fu_4417_p1 = $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it28);
assign flag_d_assign_14_fu_3948_p1 = $signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it21);
assign flag_d_assign_1_fu_4076_p1 = $signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it23);
assign flag_d_assign_2_fu_3497_p1 = $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it16);
assign flag_d_assign_3_fu_4204_p1 = $signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it25);
assign flag_d_assign_4_fu_3777_p1 = $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it18);
assign flag_d_assign_5_fu_4332_p1 = $signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it27);
assign flag_d_assign_6_fu_3905_p1 = $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it20);
assign flag_d_assign_7_fu_4460_p1 = $signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it29);
assign flag_d_assign_8_fu_4033_p1 = $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it22);
assign flag_d_assign_9_fu_3274_p1 = $signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it15);
assign flag_d_assign_fu_3143_p1 = $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign flag_d_assign_s_fu_4161_p1 = $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it24);
assign flag_val_V_assign_load_1_10_fu_2131_p3 = ((tmp_34_fu_2127_p2)? phitmp1_5_fu_2120_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_11_fu_1698_p3 = ((tmp_35_fu_1694_p2)? phitmp_6_fu_1687_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_12_fu_2163_p3 = ((tmp_36_fu_2157_p2)? phitmp1_6_fu_2149_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_13_fu_1726_p3 = ((tmp_37_fu_1722_p2)? phitmp_7_fu_1715_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_14_fu_2351_p3 = ((tmp_38_fu_2347_p2)? phitmp1_7_fu_2340_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_1_fu_1562_p3 = ((tmp_24_reg_5285)? phitmp_1_reg_5280: ap_const_lv2_0);
assign flag_val_V_assign_load_1_2_fu_1589_p3 = ((tmp_27_reg_5304)? phitmp_2_reg_5299: ap_const_lv2_0);
assign flag_val_V_assign_load_1_3_fu_1930_p3 = ((tmp_28_fu_1926_p2)? phitmp1_2_fu_1919_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_4_fu_1616_p3 = ((tmp_29_reg_5323)? phitmp_3_reg_5318: ap_const_lv2_0);
assign flag_val_V_assign_load_1_5_fu_1962_p3 = ((tmp_30_fu_1956_p2)? phitmp1_3_fu_1948_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_6_fu_1642_p3 = ((tmp_31_fu_1638_p2)? phitmp_4_fu_1631_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_7_fu_2112_p3 = ((tmp_32_fu_2108_p2)? phitmp1_4_fu_2101_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_8_fu_1670_p3 = ((tmp_33_fu_1666_p2)? phitmp_5_fu_1659_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_9_fu_1911_p3 = ((tmp_25_fu_1907_p2)? phitmp1_1_fu_1900_p3: ap_const_lv2_0);
assign flag_val_V_assign_load_1_s_fu_1521_p3 = ((tmp_20_reg_5266)? phitmp1_reg_5261: ap_const_lv2_0);
assign flag_val_V_assign_load_2_s_fu_1894_p3 = ((tmp_23_reg_5427)? phitmp3_reg_5422: ap_const_lv2_0);
assign grp_image_filter_reg_int_s_fu_542_in_r = $signed(tmp_193_1_fu_2879_p3);
assign grp_image_filter_reg_int_s_fu_547_in_r = $signed(tmp_203_1_fu_2894_p3);
assign grp_image_filter_reg_int_s_fu_552_in_r = $signed(tmp_193_3_fu_2909_p3);
assign grp_image_filter_reg_int_s_fu_557_in_r = $signed(tmp_203_3_fu_2924_p3);
assign grp_image_filter_reg_int_s_fu_562_in_r = $signed(tmp_193_5_fu_2939_p3);
assign grp_image_filter_reg_int_s_fu_567_in_r = $signed(tmp_203_5_fu_2954_p3);
assign grp_image_filter_reg_int_s_fu_572_in_r = $signed(tmp_193_7_fu_2969_p3);
assign grp_image_filter_reg_int_s_fu_577_in_r = $signed(tmp_203_7_fu_2984_p3);
assign grp_image_filter_reg_int_s_fu_582_in_r = ((tmp_192_1_fu_2995_p2)? grp_image_filter_reg_int_s_fu_542_ap_return: grp_image_filter_reg_int_s_fu_552_ap_return);
assign grp_image_filter_reg_int_s_fu_587_in_r = ((tmp_202_1_fu_3010_p2)? grp_image_filter_reg_int_s_fu_547_ap_return: grp_image_filter_reg_int_s_fu_557_ap_return);
assign grp_image_filter_reg_int_s_fu_592_in_r = ((tmp_192_5_fu_3053_p2)? grp_image_filter_reg_int_s_fu_562_ap_return: grp_image_filter_reg_int_s_fu_572_ap_return);
assign grp_image_filter_reg_int_s_fu_597_in_r = ((tmp_202_5_fu_3068_p2)? grp_image_filter_reg_int_s_fu_567_ap_return: grp_image_filter_reg_int_s_fu_577_ap_return);
assign grp_image_filter_reg_int_s_fu_602_in_r = $signed(tmp_193_9_fu_3087_p3);
assign grp_image_filter_reg_int_s_fu_607_in_r = $signed(tmp_203_9_fu_3102_p3);
assign grp_image_filter_reg_int_s_fu_612_in_r = ((tmp_199_1_fu_3113_p2)? grp_image_filter_reg_int_s_fu_582_ap_return: grp_image_filter_reg_int_s_fu_592_ap_return);
assign grp_image_filter_reg_int_s_fu_617_in_r = ((tmp_212_1_fu_3128_p2)? grp_image_filter_reg_int_s_fu_587_ap_return: grp_image_filter_reg_int_s_fu_597_ap_return);
assign grp_image_filter_reg_int_s_fu_622_in_r = $signed(tmp_193_s_fu_3150_p3);
assign grp_image_filter_reg_int_s_fu_627_in_r = $signed(tmp_203_s_fu_3165_p3);
assign grp_image_filter_reg_int_s_fu_632_in_r = $signed(tmp_193_2_fu_3180_p3);
assign grp_image_filter_reg_int_s_fu_637_in_r = $signed(tmp_203_2_fu_3195_p3);
assign grp_image_filter_reg_int_s_fu_642_in_r = $signed(tmp_193_4_fu_3210_p3);
assign grp_image_filter_reg_int_s_fu_647_in_r = $signed(tmp_203_4_fu_3225_p3);
assign grp_image_filter_reg_int_s_fu_652_in_r = ap_reg_ppstg_tmp_200_3_reg_5977_pp0_it14;
assign grp_image_filter_reg_int_s_fu_657_in_r = ap_reg_ppstg_tmp_213_3_reg_5982_pp0_it14;
assign grp_image_filter_reg_int_s_fu_662_in_r = ((tmp_192_7_fu_3236_p2)? ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14: grp_image_filter_reg_int_s_fu_602_ap_return);
assign grp_image_filter_reg_int_s_fu_667_in_r = ((tmp_202_7_fu_3249_p2)? ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14: grp_image_filter_reg_int_s_fu_607_ap_return);
assign grp_image_filter_reg_int_s_fu_672_in_r = ((tmp_192_9_fu_3277_p2)? flag_d_min2_9_reg_6017: grp_image_filter_reg_int_s_fu_622_ap_return);
assign grp_image_filter_reg_int_s_fu_677_in_r = ((tmp_202_9_fu_3290_p2)? flag_d_max2_9_reg_6023: grp_image_filter_reg_int_s_fu_627_ap_return);
assign grp_image_filter_reg_int_s_fu_682_in_r = ((tmp_192_s_fu_3303_p2)? grp_image_filter_reg_int_s_fu_622_ap_return: grp_image_filter_reg_int_s_fu_632_ap_return);
assign grp_image_filter_reg_int_s_fu_687_in_r = ((tmp_202_s_fu_3318_p2)? grp_image_filter_reg_int_s_fu_627_ap_return: grp_image_filter_reg_int_s_fu_637_ap_return);
assign grp_image_filter_reg_int_s_fu_692_in_r = ((tmp_192_2_fu_3333_p2)? grp_image_filter_reg_int_s_fu_632_ap_return: grp_image_filter_reg_int_s_fu_642_ap_return);
assign grp_image_filter_reg_int_s_fu_697_in_r = ((tmp_202_2_fu_3348_p2)? grp_image_filter_reg_int_s_fu_637_ap_return: grp_image_filter_reg_int_s_fu_647_ap_return);
assign grp_image_filter_reg_int_s_fu_702_in_r = ((tmp_192_4_fu_3363_p2)? grp_image_filter_reg_int_s_fu_642_ap_return: ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15);
assign grp_image_filter_reg_int_s_fu_707_in_r = ((tmp_202_4_fu_3376_p2)? grp_image_filter_reg_int_s_fu_647_ap_return: ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15);
assign grp_image_filter_reg_int_s_fu_712_in_r = ((tmp_199_3_fu_3389_p2)? grp_image_filter_reg_int_s_fu_652_ap_return: grp_image_filter_reg_int_s_fu_662_ap_return);
assign grp_image_filter_reg_int_s_fu_717_in_r = ((tmp_212_3_fu_3404_p2)? grp_image_filter_reg_int_s_fu_657_ap_return: grp_image_filter_reg_int_s_fu_667_ap_return);
assign grp_image_filter_reg_int_s_fu_722_in_r = tmp_210_5_reg_6129;
assign grp_image_filter_reg_int_s_fu_727_in_r = tmp_225_5_reg_6134;
assign grp_image_filter_reg_int_s_fu_732_in_r = ap_reg_ppstg_tmp_210_7_reg_6139_pp0_it19;
assign grp_image_filter_reg_int_s_fu_737_in_r = ap_reg_ppstg_tmp_225_7_reg_6144_pp0_it19;
assign grp_image_filter_reg_int_s_fu_742_in_r = ap_reg_ppstg_tmp_210_9_reg_6149_pp0_it21;
assign grp_image_filter_reg_int_s_fu_747_in_r = ap_reg_ppstg_tmp_225_9_reg_6154_pp0_it21;
assign grp_image_filter_reg_int_s_fu_752_in_r = ap_reg_ppstg_tmp_210_s_reg_6159_pp0_it23;
assign grp_image_filter_reg_int_s_fu_757_in_r = ap_reg_ppstg_tmp_225_s_reg_6164_pp0_it23;
assign grp_image_filter_reg_int_s_fu_762_in_r = ap_reg_ppstg_tmp_210_2_reg_6169_pp0_it25;
assign grp_image_filter_reg_int_s_fu_767_in_r = ap_reg_ppstg_tmp_225_2_reg_6174_pp0_it25;
assign grp_image_filter_reg_int_s_fu_772_in_r = ap_reg_ppstg_tmp_210_4_reg_6179_pp0_it27;
assign grp_image_filter_reg_int_s_fu_777_in_r = ap_reg_ppstg_tmp_225_4_reg_6184_pp0_it27;
assign i_V_fu_807_p2 = (p_s_reg_504 + ap_const_lv11_1);
assign icmp1_fu_898_p2 = (tmp_97_fu_888_p4 == ap_const_lv9_0? 1'b1: 1'b0);
assign icmp_fu_840_p2 = (tmp_16_fu_830_p4 == ap_const_lv9_0? 1'b1: 1'b0);
assign iscorner_2_i_7_fu_2191_p2 = (tmp_185_7_fu_2181_p2 & not_or_cond_fu_2186_p2);
assign iscorner_2_i_s_fu_2870_p2 = (tmp10_fu_2866_p2 | ap_reg_ppstg_tmp3_reg_5878_pp0_it11);
assign j_V_fu_851_p2 = (p_2_phi_fu_519_p4 + ap_const_lv11_1);
assign k_buf_val_0_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_0_V_address1 = k_buf_val_0_V_addr_reg_5161;
assign k_buf_val_0_V_d1 = k_buf_val_1_V_q0;
assign k_buf_val_1_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_1_V_address1 = k_buf_val_1_V_addr_reg_5167;
assign k_buf_val_1_V_d1 = k_buf_val_2_V_q0;
assign k_buf_val_2_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_2_V_address1 = k_buf_val_2_V_addr_reg_5173;
assign k_buf_val_2_V_d1 = k_buf_val_3_V_q0;
assign k_buf_val_3_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_3_V_address1 = k_buf_val_3_V_addr_reg_5179;
assign k_buf_val_3_V_d1 = k_buf_val_4_V_q0;
assign k_buf_val_4_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_4_V_address1 = k_buf_val_4_V_addr_reg_5185;
assign k_buf_val_4_V_d1 = k_buf_val_5_V_q0;
assign k_buf_val_5_V_address0 = tmp_12_fu_867_p1;
assign k_buf_val_5_V_address1 = k_buf_val_5_V_addr_reg_5191;
assign k_buf_val_5_V_d1 = p_src_data_stream_V_dout;
assign lhs_V_fu_1252_p1 = win_val_3_V_2_fu_252;
assign not_or_cond10_demorgan_fu_2093_p2 = (tmp_183_5_reg_5572 | tmp_181_5_not_reg_5566);
assign not_or_cond10_fu_2782_p2 = (ap_reg_ppstg_not_or_cond10_demorgan_reg_5699_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond11_demorgan_fu_2097_p2 = (tmp_183_6_reg_5584 | tmp_181_6_not_reg_5578);
assign not_or_cond11_fu_2817_p2 = (ap_reg_ppstg_not_or_cond11_demorgan_reg_5704_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond12_demorgan_fu_2425_p2 = (tmp_181_2_reg_5769 | tmp_183_10_reg_5775);
assign not_or_cond12_fu_2429_p2 = (not_or_cond12_demorgan_fu_2425_p2 ^ ap_const_lv1_1);
assign not_or_cond13_demorgan_fu_2470_p2 = (tmp_181_3_fu_2449_p2 | tmp_183_11_fu_2453_p2);
assign not_or_cond13_fu_2521_p2 = (not_or_cond13_demorgan_reg_5801 ^ ap_const_lv1_1);
assign not_or_cond14_demorgan_fu_2500_p2 = (tmp_181_4_fu_2484_p2 | tmp_183_12_fu_2489_p2);
assign not_or_cond14_fu_2552_p2 = (not_or_cond14_demorgan_reg_5816 ^ ap_const_lv1_1);
assign not_or_cond15_fu_2576_p2 = (or_cond18_reg_5821 ^ ap_const_lv1_1);
assign not_or_cond1_fu_2213_p2 = (or_cond11_reg_5681 ^ ap_const_lv1_1);
assign not_or_cond2_demorgan_fu_2241_p2 = (tmp_181_9_reg_5687 | tmp_183_9_reg_5693);
assign not_or_cond2_fu_2245_p2 = (not_or_cond2_demorgan_fu_2241_p2 ^ ap_const_lv1_1);
assign not_or_cond3_demorgan_fu_2286_p2 = (tmp_181_s_fu_2265_p2 | tmp_183_s_fu_2269_p2);
assign not_or_cond3_fu_2370_p2 = (not_or_cond3_demorgan_reg_5748 ^ ap_const_lv1_1);
assign not_or_cond4_demorgan_fu_2316_p2 = (tmp_181_1_fu_2300_p2 | tmp_183_8_fu_2305_p2);
assign not_or_cond4_fu_2386_p2 = (not_or_cond4_demorgan_reg_5764 ^ ap_const_lv1_1);
assign not_or_cond5_fu_2625_p2 = (ap_reg_ppstg_or_cond5_reg_5537_pp0_it7 ^ ap_const_lv1_1);
assign not_or_cond6_demorgan_fu_1870_p2 = (tmp_183_1_fu_1758_p2 | tmp_181_1_not_fu_1752_p2);
assign not_or_cond6_fu_2648_p2 = (ap_reg_ppstg_not_or_cond6_demorgan_reg_5605_pp0_it7 ^ ap_const_lv1_1);
assign not_or_cond7_demorgan_fu_1876_p2 = (tmp_183_2_fu_1776_p2 | tmp_181_2_not_fu_1770_p2);
assign not_or_cond7_fu_2704_p2 = (ap_reg_ppstg_not_or_cond7_demorgan_reg_5610_pp0_it8 ^ ap_const_lv1_1);
assign not_or_cond8_demorgan_fu_1882_p2 = (tmp_183_3_fu_1794_p2 | tmp_181_3_not_fu_1788_p2);
assign not_or_cond8_fu_2720_p2 = (ap_reg_ppstg_not_or_cond8_demorgan_reg_5615_pp0_it8 ^ ap_const_lv1_1);
assign not_or_cond9_demorgan_fu_1888_p2 = (tmp_183_4_fu_1812_p2 | tmp_181_4_not_fu_1806_p2);
assign not_or_cond9_fu_2767_p2 = (ap_reg_ppstg_not_or_cond9_demorgan_reg_5620_pp0_it9 ^ ap_const_lv1_1);
assign not_or_cond_fu_2186_p2 = (or_cond10_reg_5670 ^ ap_const_lv1_1);
assign or_cond10_fu_2055_p2 = (tmp_183_7_fu_2049_p2 | tmp_181_7_not_fu_2044_p2);
assign or_cond11_fu_2075_p2 = (tmp_181_8_fu_2069_p2 | tmp_183_7_fu_2049_p2);
assign or_cond12_fu_2231_p2 = (tmp_181_9_reg_5687 | tmp_183_9_reg_5693);
assign or_cond13_fu_2274_p2 = (tmp_181_s_fu_2265_p2 | tmp_183_s_fu_2269_p2);
assign or_cond14_fu_2310_p2 = (tmp_181_1_fu_2300_p2 | tmp_183_8_fu_2305_p2);
assign or_cond15_fu_2403_p2 = (tmp_181_2_reg_5769 | tmp_183_10_reg_5775);
assign or_cond16_fu_2458_p2 = (tmp_181_3_fu_2449_p2 | tmp_183_11_fu_2453_p2);
assign or_cond17_fu_2494_p2 = (tmp_181_4_fu_2484_p2 | tmp_183_12_fu_2489_p2);
assign or_cond18_fu_2511_p2 = (tmp_181_5_fu_2506_p2 | ap_reg_ppstg_tmp_39_reg_5532_pp0_it5);
assign or_cond1_fu_883_p2 = (tmp_8_reg_5132 & tmp_17_fu_877_p2);
assign or_cond2_fu_1990_p2 = (tmp_183_5_reg_5572 | tmp_181_5_not_reg_5566);
assign or_cond3_fu_1994_p2 = (tmp_183_6_reg_5584 | tmp_181_6_not_reg_5578);
assign or_cond4_fu_904_p2 = (icmp_reg_5142 | icmp1_fu_898_p2);
assign or_cond5_fu_1746_p2 = (tmp_39_fu_1740_p2 | tmp_181_0_not_fu_1734_p2);
assign or_cond6_fu_1764_p2 = (tmp_183_1_fu_1758_p2 | tmp_181_1_not_fu_1752_p2);
assign or_cond7_fu_1782_p2 = (tmp_183_2_fu_1776_p2 | tmp_181_2_not_fu_1770_p2);
assign or_cond8_fu_1800_p2 = (tmp_183_3_fu_1794_p2 | tmp_181_3_not_fu_1788_p2);
assign or_cond9_fu_1818_p2 = (tmp_183_4_fu_1812_p2 | tmp_181_4_not_fu_1806_p2);
assign or_cond_fu_862_p2 = (tmp_7_reg_5127 & tmp_11_fu_857_p2);
assign p_a_0_flag_d_assign_load_5_cast_fu_3652_p1 = p_a_0_flag_d_assign_load_5_reg_6077;
assign p_a_0_flag_d_assign_load_5_fu_3434_p3 = ((tmp_45_fu_3428_p2)? ap_const_lv8_14: tmp_44_fu_3424_p1);
assign p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1 = p_a_0_flag_d_assign_load_5_tmp_s_reg_6189;
assign p_a_0_flag_d_assign_load_5_tmp_s_fu_3660_p3 = ((tmp_49_fu_3655_p2)? p_a_0_flag_d_assign_load_5_reg_6077: tmp_48_reg_6088);
assign p_iscorner_0_i_10_fu_2709_p2 = (tmp_185_11_fu_2699_p2 & not_or_cond7_fu_2704_p2);
assign p_iscorner_0_i_11_fu_2725_p2 = (tmp_185_12_fu_2715_p2 & not_or_cond8_fu_2720_p2);
assign p_iscorner_0_i_12_fu_2772_p2 = (tmp_185_13_reg_5893 & not_or_cond9_fu_2767_p2);
assign p_iscorner_0_i_13_fu_2787_p2 = (tmp_185_14_fu_2777_p2 & not_or_cond10_fu_2782_p2);
assign p_iscorner_0_i_14_fu_2842_p2 = (tmp_185_15_reg_5914 & not_or_cond11_reg_5919);
assign p_iscorner_0_i_15_fu_2846_p2 = (tmp2_reg_5929 & tmp_185_16_reg_5924);
assign p_iscorner_0_i_1_fu_2391_p2 = (tmp_185_1_fu_2381_p2 & not_or_cond4_fu_2386_p2);
assign p_iscorner_0_i_2_fu_2435_p2 = (tmp_185_2_fu_2413_p2 & not_or_cond12_fu_2429_p2);
assign p_iscorner_0_i_3_fu_2526_p2 = (tmp_185_3_reg_5796 & not_or_cond13_fu_2521_p2);
assign p_iscorner_0_i_4_fu_2557_p2 = (tmp_185_4_fu_2540_p2 & not_or_cond14_fu_2552_p2);
assign p_iscorner_0_i_5_fu_2581_p2 = (tmp_185_5_fu_2570_p2 & not_or_cond15_fu_2576_p2);
assign p_iscorner_0_i_6_fu_2630_p2 = (tmp_185_6_fu_2620_p2 & not_or_cond5_fu_2625_p2);
assign p_iscorner_0_i_7_fu_2653_p2 = (tmp_185_10_fu_2642_p2 & not_or_cond6_fu_2648_p2);
assign p_iscorner_0_i_8_fu_2218_p2 = (tmp_185_8_fu_2202_p2 & not_or_cond1_fu_2213_p2);
assign p_iscorner_0_i_9_fu_2251_p2 = (tmp_185_9_fu_2235_p2 & not_or_cond2_fu_2245_p2);
assign p_iscorner_0_i_s_fu_2375_p2 = (tmp_185_s_fu_2364_p2 & not_or_cond3_fu_2370_p2);
assign p_mask_data_stream_V_din = ((tmp_26_fu_4779_p2)? ap_const_lv8_FF: ap_const_lv8_0);
assign phitmp10_fu_2749_p2 = (count_1_i_13_fu_2731_p3 + ap_const_lv5_2);
assign phitmp1_1_fu_1900_p3 = ((tmp_182_1_reg_5441)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_2_fu_1919_p3 = ((tmp_182_2_reg_5461)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_3_fu_1948_p3 = ((tmp_182_3_fu_1938_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_4_fu_2101_p3 = ((tmp_182_4_reg_5638)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_5_fu_2120_p3 = ((tmp_182_5_reg_5649)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_6_fu_2149_p3 = ((tmp_182_6_fu_2139_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_7_fu_2340_p3 = ((tmp_182_7_reg_5722)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp1_fu_1278_p3 = ((tmp_18_fu_1266_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp2_fu_4606_p2 = ($signed(tmp_100_v_reg_6714) + $signed(ap_const_lv8_FF));
assign phitmp3_cast_cast_cast_fu_2022_p3 = ((or_cond3_fu_1994_p2)? ap_const_lv4_2: ap_const_lv4_3);
assign phitmp3_fu_1539_p3 = ((tmp_21_fu_1527_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp42_op_cast_cast_cast_fu_2003_p3 = ((or_cond9_reg_5559)? ap_const_lv4_4: ap_const_lv4_5);
assign phitmp43_op_op_cast_cast_cast_fu_1856_p3 = ((or_cond7_fu_1782_p2)? ap_const_lv4_6: ap_const_lv4_7);
assign phitmp4_fu_2208_p2 = (count_1_i_7_reg_5675 + ap_const_lv4_2);
assign phitmp5_fu_2280_p2 = (count_1_i_9_fu_2257_p3 + ap_const_lv4_2);
assign phitmp6_fu_2419_p2 = (count_1_i_1_fu_2397_p3 + ap_const_lv4_2);
assign phitmp7_fu_2546_p2 = (count_1_i_3_cast_fu_2531_p1 + ap_const_lv5_2);
assign phitmp8_fu_2600_p2 = (count_1_i_5_fu_2587_p3 + ap_const_lv5_2);
assign phitmp9_fu_2672_p2 = (count_1_i_11_fu_2659_p3 + ap_const_lv5_2);
assign phitmp_1_fu_1314_p3 = ((tmp_176_1_fu_1302_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_2_fu_1350_p3 = ((tmp_176_2_fu_1338_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_3_fu_1386_p3 = ((tmp_176_3_fu_1374_p2)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_4_fu_1631_p3 = ((tmp_176_4_reg_5337)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_5_fu_1659_p3 = ((tmp_176_5_reg_5357)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_6_fu_1687_p3 = ((tmp_176_6_reg_5377)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_7_fu_1715_p3 = ((tmp_176_7_reg_5397)? ap_const_lv2_1: ap_const_lv2_2);
assign phitmp_fu_2811_p2 = (count_1_i_15_fu_2793_p3 + ap_const_lv5_2);
assign r_V_1_1_fu_1557_p2 = (lhs_V_reg_5240 - rhs_V_1_1_fu_1553_p1);
assign r_V_1_2_fu_1584_p2 = (lhs_V_reg_5240 - rhs_V_1_2_fu_1580_p1);
assign r_V_1_3_fu_1611_p2 = (lhs_V_reg_5240 - rhs_V_1_3_fu_1607_p1);
assign r_V_1_4_fu_1626_p2 = (lhs_V_reg_5240 - rhs_V_1_4_fu_1622_p1);
assign r_V_1_5_fu_1654_p2 = (lhs_V_reg_5240 - rhs_V_1_5_fu_1650_p1);
assign r_V_1_6_fu_1682_p2 = (lhs_V_reg_5240 - rhs_V_1_6_fu_1678_p1);
assign r_V_1_7_fu_1710_p2 = (lhs_V_reg_5240 - rhs_V_1_7_fu_1706_p1);
assign r_V_1_fu_1516_p2 = (lhs_V_reg_5240 - rhs_V_1_fu_1512_p1);
assign r_V_2_fu_1332_p2 = (lhs_V_fu_1252_p1 - rhs_V_2_fu_1328_p1);
assign r_V_3_fu_1368_p2 = (lhs_V_fu_1252_p1 - rhs_V_3_fu_1364_p1);
assign r_V_4_fu_1404_p2 = (lhs_V_fu_1252_p1 - rhs_V_4_fu_1400_p1);
assign r_V_5_fu_1426_p2 = (lhs_V_fu_1252_p1 - rhs_V_5_fu_1422_p1);
assign r_V_6_fu_1448_p2 = (lhs_V_fu_1252_p1 - rhs_V_6_fu_1444_p1);
assign r_V_7_fu_1470_p2 = (lhs_V_fu_1252_p1 - rhs_V_7_fu_1466_p1);
assign r_V_fu_1260_p2 = (lhs_V_fu_1252_p1 - rhs_V_fu_1256_p1);
assign r_V_s_fu_1296_p2 = (lhs_V_fu_1252_p1 - rhs_V_s_fu_1292_p1);
assign rhs_V_1_1_fu_1553_p1 = win_val_6_V_2_3_fu_320;
assign rhs_V_1_2_fu_1580_p1 = win_val_5_V_1_3_fu_296;
assign rhs_V_1_3_fu_1607_p1 = win_val_4_V_0_3_fu_268;
assign rhs_V_1_4_fu_1622_p1 = win_val_3_V_0_3_fu_240;
assign rhs_V_1_5_fu_1650_p1 = win_val_2_V_0_3_fu_212;
assign rhs_V_1_6_fu_1678_p1 = win_val_1_V_1_3_fu_188;
assign rhs_V_1_7_fu_1706_p1 = win_val_0_V_2_3_fu_168;
assign rhs_V_1_fu_1512_p1 = win_val_6_V_2_fu_324;
assign rhs_V_2_fu_1328_p1 = win_val_1_V_4_fu_204;
assign rhs_V_3_fu_1364_p1 = win_val_2_V_5_fu_236;
assign rhs_V_4_fu_1400_p1 = win_val_3_V_5_fu_264;
assign rhs_V_5_fu_1422_p1 = win_val_4_V_5_fu_292;
assign rhs_V_6_fu_1444_p1 = win_val_5_V_4_fu_312;
assign rhs_V_7_fu_1466_p1 = win_val_6_V_3_fu_156;
assign rhs_V_fu_1256_p1 = win_val_0_V_2_fu_172;
assign rhs_V_s_fu_1292_p1 = win_val_0_V_3_fu_176;
assign tmp10_fu_2866_p2 = (tmp14_reg_5944 | ap_reg_ppstg_tmp11_reg_5934_pp0_it11);
assign tmp11_fu_2833_p2 = (tmp13_reg_5904 | ap_reg_ppstg_tmp12_reg_5883_pp0_it9);
assign tmp12_fu_2694_p2 = (p_iscorner_0_i_5_reg_5832 | p_iscorner_0_i_6_fu_2630_p2);
assign tmp13_fu_2762_p2 = (p_iscorner_0_i_7_reg_5862 | p_iscorner_0_i_10_fu_2709_p2);
assign tmp14_fu_2861_p2 = (tmp16_fu_2856_p2 | tmp15_reg_5939);
assign tmp15_fu_2837_p2 = (p_iscorner_0_i_11_reg_5888 | p_iscorner_0_i_12_fu_2772_p2);
assign tmp16_fu_2856_p2 = (tmp17_fu_2850_p2 | p_iscorner_0_i_13_reg_5909);
assign tmp17_fu_2850_p2 = (p_iscorner_0_i_14_fu_2842_p2 | p_iscorner_0_i_15_fu_2846_p2);
assign tmp18_fu_4771_p2 = (tmp20_reg_6744 & tmp19_reg_6739);
assign tmp19_fu_4701_p2 = (tmp_52_fu_4647_p2 & tmp_9_reg_5137);
assign tmp20_fu_4712_p2 = (tmp21_fu_4706_p2 & ap_reg_ppstg_tmp_53_reg_6719_pp0_it33);
assign tmp21_fu_4706_p2 = (tmp_73_fu_4653_p2 & tmp_242_1_fu_4659_p2);
assign tmp22_fu_4775_p2 = (tmp25_reg_6754 & tmp23_reg_6749);
assign tmp23_fu_4723_p2 = (tmp24_fu_4717_p2 & tmp_242_2_fu_4665_p2);
assign tmp24_fu_4717_p2 = (tmp_74_fu_4671_p2 & tmp_245_1_fu_4677_p2);
assign tmp25_fu_4735_p2 = (tmp26_fu_4729_p2 & tmp_245_2_fu_4683_p2);
assign tmp26_fu_4729_p2 = (tmp_55_fu_4695_p2 & tmp_54_fu_4689_p2);
assign tmp2_fu_2828_p2 = (not_or_cond11_fu_2817_p2 & ap_reg_ppstg_not_or_cond_reg_5733_pp0_it9);
assign tmp3_fu_2689_p2 = (tmp7_fu_2685_p2 | tmp4_reg_5847);
assign tmp4_fu_2606_p2 = (tmp6_reg_5827 | ap_reg_ppstg_tmp5_reg_5781_pp0_it6);
assign tmp5_fu_2334_p2 = (iscorner_2_i_7_fu_2191_p2 | p_iscorner_0_i_8_fu_2218_p2);
assign tmp6_fu_2516_p2 = (p_iscorner_0_i_9_reg_5738 | p_iscorner_0_i_s_fu_2375_p2);
assign tmp7_fu_2685_p2 = (tmp9_reg_5857 | tmp8_reg_5852);
assign tmp8_fu_2610_p2 = (p_iscorner_0_i_1_reg_5786 | p_iscorner_0_i_2_reg_5791);
assign tmp9_fu_2614_p2 = (p_iscorner_0_i_3_fu_2526_p2 | p_iscorner_0_i_4_fu_2557_p2);
assign tmp_100_v_fu_4593_p3 = ((tmp_51_fu_4588_p2)? a0_7_tmp_232_7_reg_6691: tmp_50_fu_4583_p2);
assign tmp_11_fu_857_p2 = (p_2_phi_fu_519_p4 < tmp_15_reg_5103? 1'b1: 1'b0);
assign tmp_12_fu_867_p1 = p_2_phi_fu_519_p4;
assign tmp_14_fu_4577_p1 = ap_reg_ppstg_p_2_reg_515_pp0_it31;
assign tmp_15_fu_786_p1 = p_src_cols_V_read[10:0];
assign tmp_16_fu_830_p4 = {{p_s_reg_504[ap_const_lv32_A : ap_const_lv32_2]}};
assign tmp_176_1_fu_1302_p2 = ($signed(r_V_s_fu_1296_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_2_fu_1338_p2 = ($signed(r_V_2_fu_1332_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_3_fu_1374_p2 = ($signed(r_V_3_fu_1368_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_4_fu_1410_p2 = ($signed(r_V_4_fu_1404_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_5_fu_1432_p2 = ($signed(r_V_5_fu_1426_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_6_fu_1454_p2 = ($signed(r_V_6_fu_1448_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_176_7_fu_1476_p2 = ($signed(r_V_7_fu_1470_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_177_1_fu_1308_p2 = ($signed(r_V_s_fu_1296_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_2_fu_1344_p2 = ($signed(r_V_2_fu_1332_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_3_fu_1380_p2 = ($signed(r_V_3_fu_1368_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_4_fu_1416_p2 = ($signed(r_V_4_fu_1404_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_5_fu_1438_p2 = ($signed(r_V_5_fu_1426_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_6_fu_1460_p2 = ($signed(r_V_6_fu_1448_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_177_7_fu_1482_p2 = ($signed(r_V_7_fu_1470_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_17_fu_877_p2 = (p_2_phi_fu_519_p4 > ap_const_lv11_5? 1'b1: 1'b0);
assign tmp_181_0_not_fu_1734_p2 = (flag_val_V_assign_load_1_s_fu_1521_p3 != flag_val_V_assign_load_1_1_fu_1562_p3? 1'b1: 1'b0);
assign tmp_181_1_fu_2300_p2 = (flag_val_V_assign_load_1_5_reg_5631 != flag_val_V_assign_load_1_7_fu_2112_p3? 1'b1: 1'b0);
assign tmp_181_1_not_fu_1752_p2 = (flag_val_V_assign_load_1_1_fu_1562_p3 != flag_val_V_assign_load_1_2_fu_1589_p3? 1'b1: 1'b0);
assign tmp_181_2_fu_2322_p2 = (flag_val_V_assign_load_1_7_fu_2112_p3 != flag_val_V_assign_load_1_10_fu_2131_p3? 1'b1: 1'b0);
assign tmp_181_2_not_fu_1770_p2 = (flag_val_V_assign_load_1_2_fu_1589_p3 != flag_val_V_assign_load_1_4_fu_1616_p3? 1'b1: 1'b0);
assign tmp_181_3_fu_2449_p2 = (flag_val_V_assign_load_1_10_reg_5709 != flag_val_V_assign_load_1_12_reg_5715? 1'b1: 1'b0);
assign tmp_181_3_not_fu_1788_p2 = (flag_val_V_assign_load_1_4_fu_1616_p3 != flag_val_V_assign_load_1_6_fu_1642_p3? 1'b1: 1'b0);
assign tmp_181_4_fu_2484_p2 = (flag_val_V_assign_load_1_12_reg_5715 != flag_val_V_assign_load_1_14_fu_2351_p3? 1'b1: 1'b0);
assign tmp_181_4_not_fu_1806_p2 = (flag_val_V_assign_load_1_6_fu_1642_p3 != flag_val_V_assign_load_1_8_fu_1670_p3? 1'b1: 1'b0);
assign tmp_181_5_fu_2506_p2 = (flag_val_V_assign_load_1_14_fu_2351_p3 != ap_reg_ppstg_flag_val_V_assign_load_1_s_reg_5417_pp0_it5? 1'b1: 1'b0);
assign tmp_181_5_not_fu_1824_p2 = (flag_val_V_assign_load_1_8_fu_1670_p3 != flag_val_V_assign_load_1_11_fu_1698_p3? 1'b1: 1'b0);
assign tmp_181_6_not_fu_1836_p2 = (flag_val_V_assign_load_1_11_fu_1698_p3 != flag_val_V_assign_load_1_13_fu_1726_p3? 1'b1: 1'b0);
assign tmp_181_7_not_fu_2044_p2 = (flag_val_V_assign_load_1_13_reg_5527 != flag_val_V_assign_load_2_s_fu_1894_p3? 1'b1: 1'b0);
assign tmp_181_8_fu_2069_p2 = (flag_val_V_assign_load_2_s_fu_1894_p3 != flag_val_V_assign_load_1_9_fu_1911_p3? 1'b1: 1'b0);
assign tmp_181_9_fu_2081_p2 = (flag_val_V_assign_load_1_9_fu_1911_p3 != flag_val_V_assign_load_1_3_fu_1930_p3? 1'b1: 1'b0);
assign tmp_181_s_fu_2265_p2 = (flag_val_V_assign_load_1_3_reg_5625 != flag_val_V_assign_load_1_5_reg_5631? 1'b1: 1'b0);
assign tmp_182_1_fu_1568_p2 = ($signed(r_V_1_1_fu_1557_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_2_fu_1595_p2 = ($signed(r_V_1_2_fu_1584_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_3_fu_1938_p2 = ($signed(r_V_1_3_reg_5472) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_4_fu_1970_p2 = ($signed(r_V_1_4_reg_5483) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_5_fu_1980_p2 = ($signed(r_V_1_5_reg_5494) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_6_fu_2139_p2 = ($signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_182_7_fu_2171_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_183_10_fu_2328_p2 = (flag_val_V_assign_load_1_7_fu_2112_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_11_fu_2453_p2 = (flag_val_V_assign_load_1_10_reg_5709 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_12_fu_2489_p2 = (flag_val_V_assign_load_1_12_reg_5715 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_1_fu_1758_p2 = (flag_val_V_assign_load_1_1_fu_1562_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_2_fu_1776_p2 = (flag_val_V_assign_load_1_2_fu_1589_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_3_fu_1794_p2 = (flag_val_V_assign_load_1_4_fu_1616_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_4_fu_1812_p2 = (flag_val_V_assign_load_1_6_fu_1642_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_5_fu_1830_p2 = (flag_val_V_assign_load_1_8_fu_1670_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_6_fu_1842_p2 = (flag_val_V_assign_load_1_11_fu_1698_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_7_fu_2049_p2 = (flag_val_V_assign_load_2_s_fu_1894_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_8_fu_2305_p2 = (flag_val_V_assign_load_1_5_reg_5631 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_9_fu_2087_p2 = (flag_val_V_assign_load_1_9_fu_1911_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_183_s_fu_2269_p2 = (flag_val_V_assign_load_1_3_reg_5625 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_184_1_fu_1574_p2 = ($signed(r_V_1_1_fu_1557_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_2_fu_1601_p2 = ($signed(r_V_1_2_fu_1584_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_3_fu_1943_p2 = ($signed(r_V_1_3_reg_5472) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_4_fu_1975_p2 = ($signed(r_V_1_4_reg_5483) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_5_fu_1985_p2 = ($signed(r_V_1_5_reg_5494) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_6_fu_2144_p2 = ($signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it4) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_184_7_fu_2176_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it4) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_185_10_fu_2642_p2 = (count_1_i_10_fu_2636_p3 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_11_fu_2699_p2 = (count_4_reg_5867 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_12_fu_2715_p2 = (count_1_i_12_reg_5872 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_13_fu_2743_p2 = (count_5_fu_2737_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_14_fu_2777_p2 = (count_1_i_14_reg_5898 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_15_fu_2805_p2 = (count_6_fu_2799_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_16_fu_2822_p2 = (phitmp_fu_2811_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_1_fu_2381_p2 = (count_1_i_s_reg_5753 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_2_fu_2413_p2 = (count_1_fu_2407_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_3_fu_2464_p2 = (count_1_i_2_fu_2441_p3 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_4_fu_2540_p2 = (count_2_fu_2534_p2 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_5_fu_2570_p2 = (count_1_i_4_fu_2563_p3 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_6_fu_2620_p2 = (count_3_reg_5837 > ap_const_lv5_8? 1'b1: 1'b0);
assign tmp_185_7_fu_2181_p2 = (count_1_i_6_reg_5665 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_8_fu_2202_p2 = (count_8_fu_2197_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_9_fu_2235_p2 = (count_1_i_8_fu_2224_p3 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_185_s_fu_2364_p2 = (count_s_fu_2359_p2 > ap_const_lv4_8? 1'b1: 1'b0);
assign tmp_188_1_fu_2875_p2 = ($signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) < $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_2_fu_3176_p2 = ($signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) < $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)? 1'b1: 1'b0);
assign tmp_188_3_fu_2905_p2 = ($signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) < $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_4_fu_3206_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) < $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)? 1'b1: 1'b0);
assign tmp_188_5_fu_2935_p2 = ($signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) < $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_7_fu_2965_p2 = ($signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) < $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)? 1'b1: 1'b0);
assign tmp_188_9_fu_3083_p2 = ($signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) < $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)? 1'b1: 1'b0);
assign tmp_188_s_fu_3146_p2 = ($signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) < $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)? 1'b1: 1'b0);
assign tmp_18_fu_1266_p2 = ($signed(r_V_fu_1260_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_192_1_fu_2995_p2 = ($signed(grp_image_filter_reg_int_s_fu_542_ap_return) < $signed(grp_image_filter_reg_int_s_fu_552_ap_return)? 1'b1: 1'b0);
assign tmp_192_2_fu_3333_p2 = ($signed(grp_image_filter_reg_int_s_fu_632_ap_return) < $signed(grp_image_filter_reg_int_s_fu_642_ap_return)? 1'b1: 1'b0);
assign tmp_192_3_fu_3025_p2 = ($signed(grp_image_filter_reg_int_s_fu_552_ap_return) < $signed(grp_image_filter_reg_int_s_fu_562_ap_return)? 1'b1: 1'b0);
assign tmp_192_4_fu_3363_p2 = ($signed(grp_image_filter_reg_int_s_fu_642_ap_return) < $signed(ap_reg_ppstg_flag_d_min2_1_reg_5953_pp0_it15)? 1'b1: 1'b0);
assign tmp_192_5_fu_3053_p2 = ($signed(grp_image_filter_reg_int_s_fu_562_ap_return) < $signed(grp_image_filter_reg_int_s_fu_572_ap_return)? 1'b1: 1'b0);
assign tmp_192_7_fu_3236_p2 = ($signed(ap_reg_ppstg_flag_d_min2_7_reg_5965_pp0_it14) < $signed(grp_image_filter_reg_int_s_fu_602_ap_return)? 1'b1: 1'b0);
assign tmp_192_9_fu_3277_p2 = ($signed(flag_d_min2_9_reg_6017) < $signed(grp_image_filter_reg_int_s_fu_622_ap_return)? 1'b1: 1'b0);
assign tmp_192_s_fu_3303_p2 = ($signed(grp_image_filter_reg_int_s_fu_622_ap_return) < $signed(grp_image_filter_reg_int_s_fu_632_ap_return)? 1'b1: 1'b0);
assign tmp_193_1_fu_2879_p3 = ((tmp_188_1_fu_2875_p2)? ap_reg_ppstg_r_V_s_reg_5271_pp0_it11: ap_reg_ppstg_r_V_2_reg_5290_pp0_it11);
assign tmp_193_2_fu_3180_p3 = ((tmp_188_2_fu_3176_p2)? ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14: ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14);
assign tmp_193_3_fu_2909_p3 = ((tmp_188_3_fu_2905_p2)? ap_reg_ppstg_r_V_3_reg_5309_pp0_it11: ap_reg_ppstg_r_V_4_reg_5328_pp0_it11);
assign tmp_193_4_fu_3210_p3 = ((tmp_188_4_fu_3206_p2)? ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14: ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign tmp_193_5_fu_2939_p3 = ((tmp_188_5_fu_2935_p2)? ap_reg_ppstg_r_V_5_reg_5348_pp0_it11: ap_reg_ppstg_r_V_6_reg_5368_pp0_it11);
assign tmp_193_7_fu_2969_p3 = ((tmp_188_7_fu_2965_p2)? ap_reg_ppstg_r_V_7_reg_5388_pp0_it11: ap_reg_ppstg_r_V_1_reg_5408_pp0_it11);
assign tmp_193_9_fu_3087_p3 = ((tmp_188_9_fu_3083_p2)? ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13: ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13);
assign tmp_193_s_fu_3150_p3 = ((tmp_188_s_fu_3146_p2)? ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14: ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14);
assign tmp_195_1_fu_2890_p2 = ($signed(ap_reg_ppstg_r_V_s_reg_5271_pp0_it11) > $signed(ap_reg_ppstg_r_V_2_reg_5290_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_2_fu_3191_p2 = ($signed(ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14) > $signed(ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14)? 1'b1: 1'b0);
assign tmp_195_3_fu_2920_p2 = ($signed(ap_reg_ppstg_r_V_3_reg_5309_pp0_it11) > $signed(ap_reg_ppstg_r_V_4_reg_5328_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_4_fu_3221_p2 = ($signed(ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14) > $signed(ap_reg_ppstg_r_V_reg_5252_pp0_it14)? 1'b1: 1'b0);
assign tmp_195_5_fu_2950_p2 = ($signed(ap_reg_ppstg_r_V_5_reg_5348_pp0_it11) > $signed(ap_reg_ppstg_r_V_6_reg_5368_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_7_fu_2980_p2 = ($signed(ap_reg_ppstg_r_V_7_reg_5388_pp0_it11) > $signed(ap_reg_ppstg_r_V_1_reg_5408_pp0_it11)? 1'b1: 1'b0);
assign tmp_195_9_fu_3098_p2 = ($signed(ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13) > $signed(ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13)? 1'b1: 1'b0);
assign tmp_195_s_fu_3161_p2 = ($signed(ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14) > $signed(ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14)? 1'b1: 1'b0);
assign tmp_199_1_fu_3113_p2 = ($signed(grp_image_filter_reg_int_s_fu_582_ap_return) < $signed(grp_image_filter_reg_int_s_fu_592_ap_return)? 1'b1: 1'b0);
assign tmp_199_2_fu_3604_p2 = ($signed(grp_image_filter_reg_int_s_fu_692_ap_return) < $signed(ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16)? 1'b1: 1'b0);
assign tmp_199_3_fu_3389_p2 = ($signed(grp_image_filter_reg_int_s_fu_652_ap_return) < $signed(grp_image_filter_reg_int_s_fu_662_ap_return)? 1'b1: 1'b0);
assign tmp_199_4_fu_3628_p2 = ($signed(grp_image_filter_reg_int_s_fu_702_ap_return) < $signed(flag_d_min4_3_reg_6053)? 1'b1: 1'b0);
assign tmp_199_5_fu_3500_p2 = ($signed(ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16) < $signed(grp_image_filter_reg_int_s_fu_672_ap_return)? 1'b1: 1'b0);
assign tmp_199_7_fu_3524_p2 = ($signed(flag_d_min4_7_reg_6065) < $signed(grp_image_filter_reg_int_s_fu_682_ap_return)? 1'b1: 1'b0);
assign tmp_199_9_fu_3548_p2 = ($signed(grp_image_filter_reg_int_s_fu_672_ap_return) < $signed(grp_image_filter_reg_int_s_fu_692_ap_return)? 1'b1: 1'b0);
assign tmp_199_s_fu_3576_p2 = ($signed(grp_image_filter_reg_int_s_fu_682_ap_return) < $signed(grp_image_filter_reg_int_s_fu_702_ap_return)? 1'b1: 1'b0);
assign tmp_19_fu_1272_p2 = ($signed(r_V_fu_1260_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_200_3_fu_3031_p3 = ((tmp_192_3_fu_3025_p2)? grp_image_filter_reg_int_s_fu_552_ap_return: grp_image_filter_reg_int_s_fu_562_ap_return);
assign tmp_202_1_fu_3010_p2 = ($signed(grp_image_filter_reg_int_s_fu_547_ap_return) > $signed(grp_image_filter_reg_int_s_fu_557_ap_return)? 1'b1: 1'b0);
assign tmp_202_2_fu_3348_p2 = ($signed(grp_image_filter_reg_int_s_fu_637_ap_return) > $signed(grp_image_filter_reg_int_s_fu_647_ap_return)? 1'b1: 1'b0);
assign tmp_202_3_fu_3039_p2 = ($signed(grp_image_filter_reg_int_s_fu_557_ap_return) > $signed(grp_image_filter_reg_int_s_fu_567_ap_return)? 1'b1: 1'b0);
assign tmp_202_4_fu_3376_p2 = ($signed(grp_image_filter_reg_int_s_fu_647_ap_return) > $signed(ap_reg_ppstg_flag_d_max2_1_reg_5959_pp0_it15)? 1'b1: 1'b0);
assign tmp_202_5_fu_3068_p2 = ($signed(grp_image_filter_reg_int_s_fu_567_ap_return) > $signed(grp_image_filter_reg_int_s_fu_577_ap_return)? 1'b1: 1'b0);
assign tmp_202_7_fu_3249_p2 = ($signed(ap_reg_ppstg_flag_d_max2_7_reg_5971_pp0_it14) > $signed(grp_image_filter_reg_int_s_fu_607_ap_return)? 1'b1: 1'b0);
assign tmp_202_9_fu_3290_p2 = ($signed(flag_d_max2_9_reg_6023) > $signed(grp_image_filter_reg_int_s_fu_627_ap_return)? 1'b1: 1'b0);
assign tmp_202_s_fu_3318_p2 = ($signed(grp_image_filter_reg_int_s_fu_627_ap_return) > $signed(grp_image_filter_reg_int_s_fu_637_ap_return)? 1'b1: 1'b0);
assign tmp_203_1_fu_2894_p3 = ((tmp_195_1_fu_2890_p2)? ap_reg_ppstg_r_V_s_reg_5271_pp0_it11: ap_reg_ppstg_r_V_2_reg_5290_pp0_it11);
assign tmp_203_2_fu_3195_p3 = ((tmp_195_2_fu_3191_p2)? ap_reg_ppstg_r_V_1_5_reg_5494_pp0_it14: ap_reg_ppstg_r_V_1_6_reg_5505_pp0_it14);
assign tmp_203_3_fu_2924_p3 = ((tmp_195_3_fu_2920_p2)? ap_reg_ppstg_r_V_3_reg_5309_pp0_it11: ap_reg_ppstg_r_V_4_reg_5328_pp0_it11);
assign tmp_203_4_fu_3225_p3 = ((tmp_195_4_fu_3221_p2)? ap_reg_ppstg_r_V_1_7_reg_5516_pp0_it14: ap_reg_ppstg_r_V_reg_5252_pp0_it14);
assign tmp_203_5_fu_2954_p3 = ((tmp_195_5_fu_2950_p2)? ap_reg_ppstg_r_V_5_reg_5348_pp0_it11: ap_reg_ppstg_r_V_6_reg_5368_pp0_it11);
assign tmp_203_7_fu_2984_p3 = ((tmp_195_7_fu_2980_p2)? ap_reg_ppstg_r_V_7_reg_5388_pp0_it11: ap_reg_ppstg_r_V_1_reg_5408_pp0_it11);
assign tmp_203_9_fu_3102_p3 = ((tmp_195_9_fu_3098_p2)? ap_reg_ppstg_r_V_1_1_reg_5432_pp0_it13: ap_reg_ppstg_r_V_1_2_reg_5452_pp0_it13);
assign tmp_203_s_fu_3165_p3 = ((tmp_195_s_fu_3161_p2)? ap_reg_ppstg_r_V_1_3_reg_5472_pp0_it14: ap_reg_ppstg_r_V_1_4_reg_5483_pp0_it14);
assign tmp_209_1_fu_3666_p2 = ($signed(grp_image_filter_reg_int_s_fu_712_ap_return) < $signed(flag_d_assign_2_fu_3497_p1)? 1'b1: 1'b0);
assign tmp_209_2_fu_3794_p2 = ($signed(grp_image_filter_reg_int_s_fu_722_ap_return) < $signed(flag_d_assign_4_fu_3777_p1)? 1'b1: 1'b0);
assign tmp_209_3_fu_3922_p2 = ($signed(grp_image_filter_reg_int_s_fu_732_ap_return) < $signed(flag_d_assign_6_fu_3905_p1)? 1'b1: 1'b0);
assign tmp_209_4_fu_4050_p2 = ($signed(grp_image_filter_reg_int_s_fu_742_ap_return) < $signed(flag_d_assign_8_fu_4033_p1)? 1'b1: 1'b0);
assign tmp_209_5_fu_4178_p2 = ($signed(grp_image_filter_reg_int_s_fu_752_ap_return) < $signed(flag_d_assign_s_fu_4161_p1)? 1'b1: 1'b0);
assign tmp_209_6_fu_4306_p2 = ($signed(grp_image_filter_reg_int_s_fu_762_ap_return) < $signed(flag_d_assign_11_fu_4289_p1)? 1'b1: 1'b0);
assign tmp_209_7_fu_4434_p2 = ($signed(grp_image_filter_reg_int_s_fu_772_ap_return) < $signed(flag_d_assign_13_fu_4417_p1)? 1'b1: 1'b0);
assign tmp_20_fu_1286_p2 = (tmp_18_fu_1266_p2 | tmp_19_fu_1272_p2);
assign tmp_210_2_fu_3609_p3 = ((tmp_199_2_fu_3604_p2)? grp_image_filter_reg_int_s_fu_692_ap_return: ap_reg_ppstg_flag_d_min4_1_reg_5987_pp0_it16);
assign tmp_210_4_fu_3633_p3 = ((tmp_199_4_fu_3628_p2)? grp_image_filter_reg_int_s_fu_702_ap_return: flag_d_min4_3_reg_6053);
assign tmp_210_5_fu_3505_p3 = ((tmp_199_5_fu_3500_p2)? ap_reg_ppstg_flag_d_min4_5_reg_5999_pp0_it16: grp_image_filter_reg_int_s_fu_672_ap_return);
assign tmp_210_7_fu_3529_p3 = ((tmp_199_7_fu_3524_p2)? flag_d_min4_7_reg_6065: grp_image_filter_reg_int_s_fu_682_ap_return);
assign tmp_210_9_fu_3554_p3 = ((tmp_199_9_fu_3548_p2)? grp_image_filter_reg_int_s_fu_672_ap_return: grp_image_filter_reg_int_s_fu_692_ap_return);
assign tmp_210_s_fu_3582_p3 = ((tmp_199_s_fu_3576_p2)? grp_image_filter_reg_int_s_fu_682_ap_return: grp_image_filter_reg_int_s_fu_702_ap_return);
assign tmp_212_1_fu_3128_p2 = ($signed(grp_image_filter_reg_int_s_fu_587_ap_return) > $signed(grp_image_filter_reg_int_s_fu_597_ap_return)? 1'b1: 1'b0);
assign tmp_212_2_fu_3616_p2 = ($signed(grp_image_filter_reg_int_s_fu_697_ap_return) > $signed(ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16)? 1'b1: 1'b0);
assign tmp_212_3_fu_3404_p2 = ($signed(grp_image_filter_reg_int_s_fu_657_ap_return) > $signed(grp_image_filter_reg_int_s_fu_667_ap_return)? 1'b1: 1'b0);
assign tmp_212_4_fu_3640_p2 = ($signed(grp_image_filter_reg_int_s_fu_707_ap_return) > $signed(flag_d_max4_3_reg_6059)? 1'b1: 1'b0);
assign tmp_212_5_fu_3512_p2 = ($signed(ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16) > $signed(grp_image_filter_reg_int_s_fu_677_ap_return)? 1'b1: 1'b0);
assign tmp_212_7_fu_3536_p2 = ($signed(flag_d_max4_7_reg_6071) > $signed(grp_image_filter_reg_int_s_fu_687_ap_return)? 1'b1: 1'b0);
assign tmp_212_9_fu_3562_p2 = ($signed(grp_image_filter_reg_int_s_fu_677_ap_return) > $signed(grp_image_filter_reg_int_s_fu_697_ap_return)? 1'b1: 1'b0);
assign tmp_212_s_fu_3590_p2 = ($signed(grp_image_filter_reg_int_s_fu_687_ap_return) > $signed(grp_image_filter_reg_int_s_fu_707_ap_return)? 1'b1: 1'b0);
assign tmp_213_3_fu_3045_p3 = ((tmp_202_3_fu_3039_p2)? grp_image_filter_reg_int_s_fu_557_ap_return: grp_image_filter_reg_int_s_fu_567_ap_return);
assign tmp_216_1_fu_3698_p3 = ((tmp_209_1_reg_6195)? flag_d_min8_3_reg_6115: flag_d_assign_2_reg_6109);
assign tmp_216_2_fu_3826_p3 = ((tmp_209_2_reg_6269)? flag_d_min8_5_reg_6249: flag_d_assign_4_reg_6243);
assign tmp_216_3_fu_3954_p3 = ((tmp_209_3_reg_6343)? flag_d_min8_7_reg_6323: flag_d_assign_6_reg_6317);
assign tmp_216_4_fu_4082_p3 = ((tmp_209_4_reg_6417)? flag_d_min8_9_reg_6397: flag_d_assign_8_reg_6391);
assign tmp_216_5_fu_4210_p3 = ((tmp_209_5_reg_6491)? tmp_211_s_reg_6471: flag_d_assign_s_reg_6465);
assign tmp_216_6_fu_4338_p3 = ((tmp_209_6_reg_6565)? tmp_211_1_reg_6545: flag_d_assign_11_reg_6539);
assign tmp_216_7_fu_4466_p3 = ((tmp_209_7_reg_6639)? tmp_211_2_reg_6619: flag_d_assign_13_reg_6613);
assign tmp_217_1_fu_3707_p2 = ($signed(p_a_0_flag_d_assign_load_5_tmp_1_fu_3695_p1) > $signed(tmp_216_1_fu_3698_p3)? 1'b1: 1'b0);
assign tmp_217_2_fu_3835_p2 = ($signed(a0_tmp_232_1_cast_fu_3823_p1) > $signed(tmp_216_2_fu_3826_p3)? 1'b1: 1'b0);
assign tmp_217_3_fu_3963_p2 = ($signed(a0_2_tmp_232_2_cast_fu_3951_p1) > $signed(tmp_216_3_fu_3954_p3)? 1'b1: 1'b0);
assign tmp_217_4_fu_4091_p2 = ($signed(a0_3_tmp_232_3_cast_fu_4079_p1) > $signed(tmp_216_4_fu_4082_p3)? 1'b1: 1'b0);
assign tmp_217_5_fu_4219_p2 = ($signed(a0_4_tmp_232_4_cast_fu_4207_p1) > $signed(tmp_216_5_fu_4210_p3)? 1'b1: 1'b0);
assign tmp_217_6_fu_4347_p2 = ($signed(a0_5_tmp_232_5_cast_fu_4335_p1) > $signed(tmp_216_6_fu_4338_p3)? 1'b1: 1'b0);
assign tmp_217_7_fu_4475_p2 = ($signed(a0_6_tmp_232_6_cast_fu_4463_p1) > $signed(tmp_216_7_fu_4466_p3)? 1'b1: 1'b0);
assign tmp_21_fu_1527_p2 = ($signed(r_V_1_fu_1516_p2) > $signed(9'b10100)? 1'b1: 1'b0);
assign tmp_221_1_fu_3686_p2 = ($signed(grp_image_filter_reg_int_s_fu_717_ap_return) > $signed(flag_d_assign_2_fu_3497_p1)? 1'b1: 1'b0);
assign tmp_221_2_fu_3814_p2 = ($signed(grp_image_filter_reg_int_s_fu_727_ap_return) > $signed(flag_d_assign_4_fu_3777_p1)? 1'b1: 1'b0);
assign tmp_221_3_fu_3942_p2 = ($signed(grp_image_filter_reg_int_s_fu_737_ap_return) > $signed(flag_d_assign_6_fu_3905_p1)? 1'b1: 1'b0);
assign tmp_221_4_fu_4070_p2 = ($signed(grp_image_filter_reg_int_s_fu_747_ap_return) > $signed(flag_d_assign_8_fu_4033_p1)? 1'b1: 1'b0);
assign tmp_221_5_fu_4198_p2 = ($signed(grp_image_filter_reg_int_s_fu_757_ap_return) > $signed(flag_d_assign_s_fu_4161_p1)? 1'b1: 1'b0);
assign tmp_221_6_fu_4326_p2 = ($signed(grp_image_filter_reg_int_s_fu_767_ap_return) > $signed(flag_d_assign_11_fu_4289_p1)? 1'b1: 1'b0);
assign tmp_221_7_fu_4454_p2 = ($signed(grp_image_filter_reg_int_s_fu_777_ap_return) > $signed(flag_d_assign_13_fu_4417_p1)? 1'b1: 1'b0);
assign tmp_225_2_fu_3621_p3 = ((tmp_212_2_fu_3616_p2)? grp_image_filter_reg_int_s_fu_697_ap_return: ap_reg_ppstg_flag_d_max4_1_reg_5993_pp0_it16);
assign tmp_225_4_fu_3645_p3 = ((tmp_212_4_fu_3640_p2)? grp_image_filter_reg_int_s_fu_707_ap_return: flag_d_max4_3_reg_6059);
assign tmp_225_5_fu_3517_p3 = ((tmp_212_5_fu_3512_p2)? ap_reg_ppstg_flag_d_max4_5_reg_6005_pp0_it16: grp_image_filter_reg_int_s_fu_677_ap_return);
assign tmp_225_7_fu_3541_p3 = ((tmp_212_7_fu_3536_p2)? flag_d_max4_7_reg_6071: grp_image_filter_reg_int_s_fu_687_ap_return);
assign tmp_225_9_fu_3568_p3 = ((tmp_212_9_fu_3562_p2)? grp_image_filter_reg_int_s_fu_677_ap_return: grp_image_filter_reg_int_s_fu_697_ap_return);
assign tmp_225_s_fu_3596_p3 = ((tmp_212_s_fu_3590_p2)? grp_image_filter_reg_int_s_fu_687_ap_return: grp_image_filter_reg_int_s_fu_707_ap_return);
assign tmp_227_1_fu_3739_p3 = ((tmp_221_1_reg_6206)? flag_d_max8_3_reg_6122: flag_d_assign_2_reg_6109);
assign tmp_227_2_fu_3867_p3 = ((tmp_221_2_reg_6280)? flag_d_max8_5_reg_6256: flag_d_assign_4_reg_6243);
assign tmp_227_3_fu_3995_p3 = ((tmp_221_3_reg_6354)? flag_d_max8_7_reg_6330: flag_d_assign_6_reg_6317);
assign tmp_227_4_fu_4123_p3 = ((tmp_221_4_reg_6428)? flag_d_max8_9_reg_6404: flag_d_assign_8_reg_6391);
assign tmp_227_5_fu_4251_p3 = ((tmp_221_5_reg_6502)? tmp_226_s_reg_6478: flag_d_assign_s_reg_6465);
assign tmp_227_6_fu_4379_p3 = ((tmp_221_6_reg_6576)? tmp_226_1_reg_6552: flag_d_assign_11_reg_6539);
assign tmp_227_7_fu_4507_p3 = ((tmp_221_7_reg_6650)? tmp_226_2_reg_6626: flag_d_assign_13_reg_6613);
assign tmp_228_1_fu_3748_p2 = ($signed(b0_tmp_239_cast_fu_3736_p1) < $signed(tmp_227_1_fu_3739_p3)? 1'b1: 1'b0);
assign tmp_228_2_fu_3876_p2 = ($signed(b0_tmp_239_1_cast_fu_3864_p1) < $signed(tmp_227_2_fu_3867_p3)? 1'b1: 1'b0);
assign tmp_228_3_fu_4004_p2 = ($signed(b0_2_tmp_239_2_cast_fu_3992_p1) < $signed(tmp_227_3_fu_3995_p3)? 1'b1: 1'b0);
assign tmp_228_4_fu_4132_p2 = ($signed(b0_3_tmp_239_3_cast_fu_4120_p1) < $signed(tmp_227_4_fu_4123_p3)? 1'b1: 1'b0);
assign tmp_228_5_fu_4260_p2 = ($signed(b0_4_tmp_239_4_cast_fu_4248_p1) < $signed(tmp_227_5_fu_4251_p3)? 1'b1: 1'b0);
assign tmp_228_6_fu_4388_p2 = ($signed(b0_5_tmp_239_5_cast_fu_4376_p1) < $signed(tmp_227_6_fu_4379_p3)? 1'b1: 1'b0);
assign tmp_228_7_fu_4516_p2 = ($signed(b0_6_tmp_239_6_cast_fu_4504_p1) < $signed(tmp_227_7_fu_4507_p3)? 1'b1: 1'b0);
assign tmp_22_fu_1533_p2 = ($signed(r_V_1_fu_1516_p2) < $signed(9'b111101100)? 1'b1: 1'b0);
assign tmp_231_1_fu_3720_p2 = ($signed(flag_d_min8_3_reg_6115) < $signed(flag_d_assign_10_fu_3692_p1)? 1'b1: 1'b0);
assign tmp_231_2_fu_3848_p2 = ($signed(flag_d_min8_5_reg_6249) < $signed(flag_d_assign_12_fu_3820_p1)? 1'b1: 1'b0);
assign tmp_231_3_fu_3976_p2 = ($signed(flag_d_min8_7_reg_6323) < $signed(flag_d_assign_14_fu_3948_p1)? 1'b1: 1'b0);
assign tmp_231_4_fu_4104_p2 = ($signed(flag_d_min8_9_reg_6397) < $signed(flag_d_assign_1_fu_4076_p1)? 1'b1: 1'b0);
assign tmp_231_5_fu_4232_p2 = ($signed(tmp_211_s_reg_6471) < $signed(flag_d_assign_3_fu_4204_p1)? 1'b1: 1'b0);
assign tmp_231_6_fu_4360_p2 = ($signed(tmp_211_1_reg_6545) < $signed(flag_d_assign_5_fu_4332_p1)? 1'b1: 1'b0);
assign tmp_231_7_fu_4488_p2 = ($signed(tmp_211_2_reg_6619) < $signed(flag_d_assign_7_fu_4460_p1)? 1'b1: 1'b0);
assign tmp_232_1_fu_3725_p3 = ((tmp_231_1_fu_3720_p2)? flag_d_min8_3_reg_6115: flag_d_assign_10_fu_3692_p1);
assign tmp_232_2_fu_3853_p3 = ((tmp_231_2_fu_3848_p2)? flag_d_min8_5_reg_6249: flag_d_assign_12_fu_3820_p1);
assign tmp_232_3_fu_3981_p3 = ((tmp_231_3_fu_3976_p2)? flag_d_min8_7_reg_6323: flag_d_assign_14_fu_3948_p1);
assign tmp_232_4_fu_4109_p3 = ((tmp_231_4_fu_4104_p2)? flag_d_min8_9_reg_6397: flag_d_assign_1_fu_4076_p1);
assign tmp_232_5_fu_4237_p3 = ((tmp_231_5_fu_4232_p2)? tmp_211_s_reg_6471: flag_d_assign_3_fu_4204_p1);
assign tmp_232_6_fu_4365_p3 = ((tmp_231_6_fu_4360_p2)? tmp_211_1_reg_6545: flag_d_assign_5_fu_4332_p1);
assign tmp_232_7_fu_4493_p3 = ((tmp_231_7_fu_4488_p2)? tmp_211_2_reg_6619: flag_d_assign_7_fu_4460_p1);
assign tmp_233_1_fu_3783_p2 = ($signed(a0_cast_fu_3780_p1) > $signed(tmp_232_1_reg_6217)? 1'b1: 1'b0);
assign tmp_233_2_fu_3911_p2 = ($signed(a0_2_cast_fu_3908_p1) > $signed(tmp_232_2_reg_6291)? 1'b1: 1'b0);
assign tmp_233_3_fu_4039_p2 = ($signed(a0_3_cast_fu_4036_p1) > $signed(tmp_232_3_reg_6365)? 1'b1: 1'b0);
assign tmp_233_4_fu_4167_p2 = ($signed(a0_4_cast_fu_4164_p1) > $signed(tmp_232_4_reg_6439)? 1'b1: 1'b0);
assign tmp_233_5_fu_4295_p2 = ($signed(a0_5_cast_fu_4292_p1) > $signed(tmp_232_5_reg_6513)? 1'b1: 1'b0);
assign tmp_233_6_fu_4423_p2 = ($signed(a0_6_cast_fu_4420_p1) > $signed(tmp_232_6_reg_6587)? 1'b1: 1'b0);
assign tmp_233_7_fu_4552_p2 = ($signed(a0_7_cast_fu_4549_p1) > $signed(tmp_232_7_reg_6661)? 1'b1: 1'b0);
assign tmp_236_1_fu_3761_p2 = ($signed(flag_d_max8_3_reg_6122) > $signed(flag_d_assign_10_fu_3692_p1)? 1'b1: 1'b0);
assign tmp_236_2_fu_3889_p2 = ($signed(flag_d_max8_5_reg_6256) > $signed(flag_d_assign_12_fu_3820_p1)? 1'b1: 1'b0);
assign tmp_236_3_fu_4017_p2 = ($signed(flag_d_max8_7_reg_6330) > $signed(flag_d_assign_14_fu_3948_p1)? 1'b1: 1'b0);
assign tmp_236_4_fu_4145_p2 = ($signed(flag_d_max8_9_reg_6404) > $signed(flag_d_assign_1_fu_4076_p1)? 1'b1: 1'b0);
assign tmp_236_5_fu_4273_p2 = ($signed(tmp_226_s_reg_6478) > $signed(flag_d_assign_3_fu_4204_p1)? 1'b1: 1'b0);
assign tmp_236_6_fu_4401_p2 = ($signed(tmp_226_1_reg_6552) > $signed(flag_d_assign_5_fu_4332_p1)? 1'b1: 1'b0);
assign tmp_236_7_fu_4529_p2 = ($signed(tmp_226_2_reg_6626) > $signed(flag_d_assign_7_fu_4460_p1)? 1'b1: 1'b0);
assign tmp_239_1_fu_3766_p3 = ((tmp_236_1_fu_3761_p2)? flag_d_max8_3_reg_6122: flag_d_assign_10_fu_3692_p1);
assign tmp_239_2_fu_3894_p3 = ((tmp_236_2_fu_3889_p2)? flag_d_max8_5_reg_6256: flag_d_assign_12_fu_3820_p1);
assign tmp_239_3_fu_4022_p3 = ((tmp_236_3_fu_4017_p2)? flag_d_max8_7_reg_6330: flag_d_assign_14_fu_3948_p1);
assign tmp_239_4_fu_4150_p3 = ((tmp_236_4_fu_4145_p2)? flag_d_max8_9_reg_6404: flag_d_assign_1_fu_4076_p1);
assign tmp_239_5_fu_4278_p3 = ((tmp_236_5_fu_4273_p2)? tmp_226_s_reg_6478: flag_d_assign_3_fu_4204_p1);
assign tmp_239_6_fu_4406_p3 = ((tmp_236_6_fu_4401_p2)? tmp_226_1_reg_6552: flag_d_assign_5_fu_4332_p1);
assign tmp_239_7_fu_4534_p3 = ((tmp_236_7_fu_4529_p2)? tmp_226_2_reg_6626: flag_d_assign_7_fu_4460_p1);
assign tmp_23_fu_1547_p2 = (tmp_21_fu_1527_p2 | tmp_22_fu_1533_p2);
assign tmp_240_1_fu_3803_p2 = ($signed(b0_cast_50_fu_3800_p1) < $signed(tmp_239_1_reg_6233)? 1'b1: 1'b0);
assign tmp_240_2_fu_3931_p2 = ($signed(b0_2_cast_fu_3928_p1) < $signed(tmp_239_2_reg_6307)? 1'b1: 1'b0);
assign tmp_240_3_fu_4059_p2 = ($signed(b0_3_cast_fu_4056_p1) < $signed(tmp_239_3_reg_6381)? 1'b1: 1'b0);
assign tmp_240_4_fu_4187_p2 = ($signed(b0_4_cast_fu_4184_p1) < $signed(tmp_239_4_reg_6455)? 1'b1: 1'b0);
assign tmp_240_5_fu_4315_p2 = ($signed(b0_5_cast_fu_4312_p1) < $signed(tmp_239_5_reg_6529)? 1'b1: 1'b0);
assign tmp_240_6_fu_4443_p2 = ($signed(b0_6_cast_fu_4440_p1) < $signed(tmp_239_6_reg_6603)? 1'b1: 1'b0);
assign tmp_240_7_fu_4566_p2 = ($signed(b0_7_cast_fu_4563_p1) < $signed(tmp_239_7_reg_6676)? 1'b1: 1'b0);
assign tmp_242_1_fu_4659_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_1_fu_140)? 1'b1: 1'b0);
assign tmp_242_2_fu_4665_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_2_fu_4620_p1)? 1'b1: 1'b0);
assign tmp_245_1_fu_4677_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_1_fu_164)? 1'b1: 1'b0);
assign tmp_245_2_fu_4683_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_1_2_fu_4643_p1)? 1'b1: 1'b0);
assign tmp_24_fu_1322_p2 = (tmp_176_1_fu_1302_p2 | tmp_177_1_fu_1308_p2);
assign tmp_25_fu_1907_p2 = (tmp_182_1_reg_5441 | tmp_184_1_reg_5447);
assign tmp_26_fu_4779_p2 = (tmp22_fu_4775_p2 & tmp18_fu_4771_p2);
assign tmp_27_fu_1358_p2 = (tmp_176_2_fu_1338_p2 | tmp_177_2_fu_1344_p2);
assign tmp_28_fu_1926_p2 = (tmp_182_2_reg_5461 | tmp_184_2_reg_5467);
assign tmp_29_fu_1394_p2 = (tmp_176_3_fu_1374_p2 | tmp_177_3_fu_1380_p2);
assign tmp_30_fu_1956_p2 = (tmp_182_3_fu_1938_p2 | tmp_184_3_fu_1943_p2);
assign tmp_31_fu_1638_p2 = (tmp_176_4_reg_5337 | tmp_177_4_reg_5343);
assign tmp_32_fu_2108_p2 = (tmp_182_4_reg_5638 | tmp_184_4_reg_5644);
assign tmp_33_fu_1666_p2 = (tmp_176_5_reg_5357 | tmp_177_5_reg_5363);
assign tmp_34_fu_2127_p2 = (tmp_182_5_reg_5649 | tmp_184_5_reg_5655);
assign tmp_35_fu_1694_p2 = (tmp_176_6_reg_5377 | tmp_177_6_reg_5383);
assign tmp_36_fu_2157_p2 = (tmp_182_6_fu_2139_p2 | tmp_184_6_fu_2144_p2);
assign tmp_37_fu_1722_p2 = (tmp_176_7_reg_5397 | tmp_177_7_reg_5403);
assign tmp_38_fu_2347_p2 = (tmp_182_7_reg_5722 | tmp_184_7_reg_5728);
assign tmp_39_fu_1740_p2 = (flag_val_V_assign_load_1_s_fu_1521_p3 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_40_fu_1864_p2 = (or_cond7_fu_1782_p2 | or_cond6_fu_1764_p2);
assign tmp_41_fu_2010_p2 = (or_cond9_reg_5559 | or_cond8_reg_5553);
assign tmp_42_fu_2030_p2 = (or_cond3_fu_1994_p2 | or_cond2_fu_1990_p2);
assign tmp_43_fu_3262_p2 = ($signed(grp_image_filter_reg_int_s_fu_612_ap_return) < $signed(flag_d_assign_fu_3143_p1)? 1'b1: 1'b0);
assign tmp_44_fu_3424_p1 = a_0_flag_d_assign_load_5_fu_3419_p3[7:0];
assign tmp_45_fu_3428_p2 = ($signed(a_0_flag_d_assign_load_5_fu_3419_p3) < $signed(32'b10100)? 1'b1: 1'b0);
assign tmp_46_fu_3442_p2 = ($signed(flag_d_min8_1_reg_6029) < $signed(flag_d_assign_9_fu_3274_p1)? 1'b1: 1'b0);
assign tmp_47_fu_3447_p3 = ((tmp_46_fu_3442_p2)? flag_d_min8_1_reg_6029: flag_d_assign_9_fu_3274_p1);
assign tmp_48_fu_3454_p1 = tmp_47_fu_3447_p3[7:0];
assign tmp_49_fu_3655_p2 = ($signed(p_a_0_flag_d_assign_load_5_cast_fu_3652_p1) > $signed(tmp_47_reg_6083)? 1'b1: 1'b0);
assign tmp_50_fu_4583_p2 = (ap_const_lv8_0 - tmp_79_reg_6697);
assign tmp_51_fu_4588_p2 = (a0_7_tmp_232_7_reg_6691 > tmp_50_fu_4583_p2? 1'b1: 1'b0);
assign tmp_52_fu_4647_p2 = (core_win_val_1_V_1_fu_152 != ap_const_lv16_0? 1'b1: 1'b0);
assign tmp_53_fu_4600_p2 = (ap_reg_ppstg_p_2_reg_515_pp0_it31 > ap_const_lv11_6? 1'b1: 1'b0);
assign tmp_54_fu_4689_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_1_V_0_fu_148)? 1'b1: 1'b0);
assign tmp_55_fu_4695_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_1_V_2_fu_4623_p1)? 1'b1: 1'b0);
assign tmp_56_fu_3703_p1 = tmp_216_1_fu_3698_p3[7:0];
assign tmp_57_fu_3732_p1 = tmp_232_1_fu_3725_p3[7:0];
assign tmp_58_fu_3831_p1 = tmp_216_2_fu_3826_p3[7:0];
assign tmp_59_fu_3860_p1 = tmp_232_2_fu_3853_p3[7:0];
assign tmp_5_fu_796_p2 = (tmp_fu_782_p1 + ap_const_lv11_4);
assign tmp_60_fu_3959_p1 = tmp_216_3_fu_3954_p3[7:0];
assign tmp_61_fu_3988_p1 = tmp_232_3_fu_3981_p3[7:0];
assign tmp_62_fu_4087_p1 = tmp_216_4_fu_4082_p3[7:0];
assign tmp_63_fu_4116_p1 = tmp_232_4_fu_4109_p3[7:0];
assign tmp_64_fu_4215_p1 = tmp_216_5_fu_4210_p3[7:0];
assign tmp_65_fu_4244_p1 = tmp_232_5_fu_4237_p3[7:0];
assign tmp_66_fu_4343_p1 = tmp_216_6_fu_4338_p3[7:0];
assign tmp_67_fu_3268_p2 = ($signed(grp_image_filter_reg_int_s_fu_617_ap_return) > $signed(flag_d_assign_fu_3143_p1)? 1'b1: 1'b0);
assign tmp_68_fu_3458_p3 = ((tmp_67_reg_6048)? flag_d_max8_1_reg_6036: flag_d_assign_reg_6011);
assign tmp_69_fu_3467_p2 = ($signed(tmp_68_fu_3458_p3) > $signed(32'b11111111111111111111111111101100)? 1'b1: 1'b0);
assign tmp_70_fu_3481_p2 = ($signed(flag_d_max8_1_reg_6036) > $signed(flag_d_assign_9_fu_3274_p1)? 1'b1: 1'b0);
assign tmp_71_fu_3486_p3 = ((tmp_70_fu_3481_p2)? flag_d_max8_1_reg_6036: flag_d_assign_9_fu_3274_p1);
assign tmp_72_fu_3675_p2 = ($signed(b0_cast_fu_3672_p1) < $signed(tmp_71_reg_6099)? 1'b1: 1'b0);
assign tmp_73_fu_4653_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_0_V_0_fu_136)? 1'b1: 1'b0);
assign tmp_74_fu_4671_p2 = ($signed(core_win_val_1_V_1_fu_152) > $signed(core_win_val_2_V_0_fu_160)? 1'b1: 1'b0);
assign tmp_75_fu_4372_p1 = tmp_232_6_fu_4365_p3[7:0];
assign tmp_77_fu_4471_p1 = tmp_216_7_fu_4466_p3[7:0];
assign tmp_78_fu_4500_p1 = tmp_232_7_fu_4493_p3[7:0];
assign tmp_79_fu_4571_p3 = ((tmp_240_7_fu_4566_p2)? tmp_95_reg_6681: tmp_96_reg_6686);
assign tmp_7_fu_813_p2 = (p_s_reg_504 < tmp_reg_5098? 1'b1: 1'b0);
assign tmp_80_fu_3463_p1 = tmp_68_fu_3458_p3[8:0];
assign tmp_81_fu_3493_p1 = tmp_71_fu_3486_p3[8:0];
assign tmp_82_fu_3744_p1 = tmp_227_1_fu_3739_p3[8:0];
assign tmp_83_fu_3773_p1 = tmp_239_1_fu_3766_p3[8:0];
assign tmp_84_fu_3872_p1 = tmp_227_2_fu_3867_p3[8:0];
assign tmp_85_fu_3901_p1 = tmp_239_2_fu_3894_p3[8:0];
assign tmp_86_fu_4000_p1 = tmp_227_3_fu_3995_p3[8:0];
assign tmp_87_fu_4029_p1 = tmp_239_3_fu_4022_p3[8:0];
assign tmp_88_fu_4128_p1 = tmp_227_4_fu_4123_p3[8:0];
assign tmp_89_fu_4157_p1 = tmp_239_4_fu_4150_p3[8:0];
assign tmp_8_fu_818_p2 = (p_s_reg_504 > ap_const_lv11_5? 1'b1: 1'b0);
assign tmp_90_fu_4256_p1 = tmp_227_5_fu_4251_p3[8:0];
assign tmp_91_fu_4285_p1 = tmp_239_5_fu_4278_p3[8:0];
assign tmp_92_fu_4384_p1 = tmp_227_6_fu_4379_p3[8:0];
assign tmp_93_fu_4413_p1 = tmp_239_6_fu_4406_p3[8:0];
assign tmp_94_fu_4512_p1 = tmp_227_7_fu_4507_p3[8:0];
assign tmp_95_fu_4541_p1 = b0_7_fu_4522_p3[7:0];
assign tmp_96_fu_4545_p1 = tmp_239_7_fu_4534_p3[7:0];
assign tmp_97_fu_888_p4 = {{p_2_phi_fu_519_p4[ap_const_lv32_A : ap_const_lv32_2]}};
assign tmp_9_fu_824_p2 = (p_s_reg_504 > ap_const_lv11_6? 1'b1: 1'b0);
assign tmp_fu_782_p1 = p_src_rows_V_read[10:0];
assign tmp_s_fu_790_p2 = (tmp_15_fu_786_p1 + ap_const_lv11_4);
always @ (posedge ap_clk)
begin
    lhs_V_reg_5240[8] <= 1'b0;
    count_1_i_0_op_op87_op_reg_5590[3:1] <= 3'b100;
    phitmp43_op_op_cast_cast_cast_reg_5595[3:1] <= 3'b011;
    core_win_val_0_V_0_fu_136[15:8] <= 8'b00000000;
    core_win_val_0_V_1_fu_140[15:8] <= 8'b00000000;
    core_win_val_1_V_0_fu_148[15:8] <= 8'b00000000;
    core_win_val_1_V_1_fu_152[15:8] <= 8'b00000000;
    core_win_val_2_V_0_fu_160[15:8] <= 8'b00000000;
    core_win_val_2_V_1_fu_164[15:8] <= 8'b00000000;
end



endmodule //image_filter_FAST_t_opr

