// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_be_i
//
// Generated
//  by:  wig
//  on:  Sat Mar  3 11:02:57 2007
//  cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_be_i.v,v 1.1 2007/03/03 11:17:34 wig Exp $
// $Date: 2007/03/03 11:17:34 $
// $Log: inst_be_i.v,v $
// Revision 1.1  2007/03/03 11:17:34  wig
// Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp 
//
// Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps

udc: Verilog HEAD HOOK inst_bc2_i

//
//
// Start of Generated Module rtl of inst_be_i
//

// No user `defines in this module


module inst_be_i
//
// Generated Module inst_be_i
//
	(
	);
udc: Verilog PARA HOOK inst_bc2_i
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//


udc: Verilog BODY HOOK inst_bc2_i

	//
	// Generated Instances and Port Mappings
	//


endmodule
//
// End of Generated Module rtl of inst_be_i
//
udc: Verilog FOOT HOOK two lines inst_bc2_i
second line inst_bc2_i, config here inst_be_i_rtl_conf and description no verilog udc here
//
//!End of Module/s
// --------------------------------------------------------------
