// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
//  by:  wig
//  on:  Tue Jun 27 05:12:12 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ad.v,v $
// Revision 1.1  2006/11/15 16:04:10  wig
// Added Files: Testcase for verilog include import
//  	ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
//  	ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6  2006/07/04 09:54:11  wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp 
//
// Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of ent_ad
//

// No user `defines in this module


module ent_ad
//
// Generated Module inst_ad
//
	(
		port_ad_2	// Use internally test2, no port generated
	);

	// Generated Module Outputs:
		output		port_ad_2;
	// Generated Wires:
		wire		port_ad_2;
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//




	//
	// Generated Instances and Port Mappings
	//


endmodule
//
// End of Generated Module rtl of ent_ad
//

//
//!End of Module/s
// --------------------------------------------------------------
