////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 13.1
//  \   \         Application : xaw2verilog
//  /   /         Filename : main_pll.v
// /___/   /\     Timestamp : 06/03/2011 01:58:13
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST

`timescale 1ns / 1ps

module dyn_pll # (parameter SPEED_MHZ = 25 )
	(CLKIN_IN, 
	CLKFX1_OUT, 
	CLKFX2_OUT, 
	CLKDV_OUT,
	DCM_SP_LOCKED_OUT,
	dcm_progclk,
	dcm_progdata,
	dcm_progen,
	dcm_reset,
	dcm_progdone,
	dcm_locked,
	dcm_status);
	
	input CLKIN_IN;
	wire CLKIN_IBUFG_OUT;
	wire CLK0_OUT;
	output CLKFX1_OUT;
	output CLKFX2_OUT;
	output CLKDV_OUT;
	output DCM_SP_LOCKED_OUT;

	input dcm_progclk;
	input dcm_progdata;
	input dcm_progen;
	input dcm_reset;
	output dcm_progdone;
	output dcm_locked;
	output [2:1] dcm_status;
	
	wire CLKFB_IN;
	wire CLKIN_IBUFG;
	wire CLK0_BUF;
	wire CLKFX1_BUF;
	wire CLKFX2_BUF;
	wire CLKDV_BUF;
	wire GND_BIT;
	wire dcm_progclk_buf;

	assign GND_BIT = 0;
	assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
	assign CLK0_OUT = CLKFB_IN;
	
	IBUFG  CLKIN_IBUFG_INST (.I(CLKIN_IN), 
		.O(CLKIN_IBUFG));
	BUFG  CLK0_BUFG_INST (.I(CLK0_BUF), 
		.O(CLKFB_IN));
	BUFG  CLKFX1_BUFG_INST (.I(CLKFX1_BUF), 
		.O(CLKFX1_OUT));
	BUFG  CLKFX2_BUFG_INST (.I(CLKFX2_BUF), 
		.O(CLKFX2_OUT));
	BUFG  CLKDV_BUFG_INST (.I(CLKDV_BUF), 
		.O(CLKDV_OUT));
	BUFG  DCMPROGCLK_BUFG_INST (.I(dcm_progclk), 
		.O(dcm_progclk_buf));

	// 100 MHZ osc gives fixed 50MHz CLKFX1, 12.5MHZ CLKDV
	DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(8),
		.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), 
		.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"), 
		.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), 
		.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), 
		.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") ) 
		DCM_SP_INST (.CLKFB(CLKFB_IN), 
		.CLKIN(CLKIN_IBUFG), 
		.DSSEN(GND_BIT), 
		.PSCLK(GND_BIT), 
		.PSEN(GND_BIT), 
		.PSINCDEC(GND_BIT), 
		.RST(GND_BIT), 
		.CLKDV(CLKDV_BUF), 
		.CLKFX(CLKFX1_BUF), 
		.CLKFX180(), 
		.CLK0(CLK0_BUF), 
		.CLK2X(), 
		.CLK2X180(), 
		.CLK90(), 
		.CLK180(), 
		.CLK270(), 
		.LOCKED(DCM_SP_LOCKED_OUT), 
		.PSDONE(), 
		.STATUS());

	DCM_CLKGEN #(
		.CLKFX_DIVIDE(100),			// 100Mhz osc so gives steps of 1MHz
		.CLKFX_MULTIPLY(SPEED_MHZ),
		.CLKFXDV_DIVIDE(2),			// Unused
		.CLKIN_PERIOD(10.0),
		.CLKFX_MD_MAX(0.000),
		.SPREAD_SPECTRUM("NONE"),
		.STARTUP_WAIT("FALSE")
		) 
		DCM_CLKGEN_INST (
		.CLKIN(CLKIN_IBUFG),
		.CLKFX(CLKFX2_BUF),
		.FREEZEDCM(1'b0),
		.PROGCLK(dcm_progclk_buf),
		.PROGDATA(dcm_progdata),
		.PROGEN(dcm_progen),
		.PROGDONE(dcm_progdone),
		.LOCKED(dcm_locked),
		.STATUS(dcm_status),
		.RST(dcm_reset)
		);

endmodule
