`include "defines.v"

module registers(
    input wire clk,
    input wire rst,

    input wire[4:0] readAddr1_i,
    input wire readEnable1_i,
    output reg[31:0] data1_o,

    input wire[4:0] readAddr2_i,
    input wire readEnable2_i,
    output reg[31:0] data2_o,

    input wire[4:0] writeAddr_i,
    input wire[31:0] writeData_i,
    input wire writeEnable_i
    );

    //Register File
    reg[31:0] regs[0:31];

    //Read 1
    always @(*) begin
        if (readAddr1_i == 5'h0) begin
            data1_o = `ZeroWord;
        end else if (readEnable1_i == `Enable && writeEnable_i == `Enable && readAddr1_i == writeAddr_i) begin
            data1_o = writeData_i;
        end else if (readEnable1_i == `Enable) begin
            data1_o = regs[readAddr1_i];
        end else begin
            data1_o = `ZeroWord;
        end
    end

    //Read 2
    always @(*) begin
        if (readAddr2_i == 5'h0) begin
            data2_o = `ZeroWord;
        end else if (readEnable2_i == `Enable && writeEnable_i == `Enable && readAddr2_i == writeAddr_i) begin
            data2_o = writeData_i;
        end else if (readEnable2_i == `Enable) begin
            data2_o = regs[readAddr2_i];
        end else begin
            data2_o = `ZeroWord;
        end
    end

    //Write
    always @(posedge clk) begin
        //regs[1] <= 32'b1;
        //regs[2] <= 32'b1;
        if (rst == `Enable) begin
            regs[0] <= `ZeroWord;
            regs[1] <= `ZeroWord;
            regs[2] <= `ZeroWord;
            regs[3] <= `ZeroWord;
            regs[4] <= `ZeroWord;
            regs[5] <= `ZeroWord;
            regs[6] <= `ZeroWord;
            regs[7] <= `ZeroWord;
            regs[8] <= `ZeroWord;
            regs[9] <= `ZeroWord;
            regs[10] <= `ZeroWord;
            regs[11] <= `ZeroWord;
            regs[12] <= `ZeroWord;
            regs[13] <= `ZeroWord;
            regs[14] <= `ZeroWord;
            regs[15] <= `ZeroWord;
            regs[16] <= `ZeroWord;
            regs[17] <= `ZeroWord;
            regs[18] <= `ZeroWord;
            regs[19] <= `ZeroWord;
            regs[20] <= `ZeroWord;
            regs[21] <= `ZeroWord;
            regs[22] <= `ZeroWord;
            regs[23] <= `ZeroWord;
            regs[24] <= `ZeroWord;
            regs[25] <= `ZeroWord;
            regs[26] <= `ZeroWord;
            regs[27] <= `ZeroWord;
            regs[28] <= `ZeroWord;
            regs[29] <= `ZeroWord;
            regs[30] <= `ZeroWord;
            regs[31] <= `ZeroWord;
        end else if (writeEnable_i == `Enable && writeAddr_i != 5'h0) begin
            regs[writeAddr_i] <= writeData_i;
        end
    end
endmodule
