// megafunction wizard: %ALTFP_SQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_sqrt 

// ============================================================
// File Name: acl_fp_sqrt.v
// Megafunction Name(s):
// 			altfp_sqrt
//
// Simulation Library Files(s):
// 			lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************


// (C) 1992-2014 Altera Corporation. All rights reserved.                         
// Your use of Altera Corporation's design tools, logic functions and other       
// software and tools, and its AMPP partner logic functions, and any output       
// files any of the foregoing (including device programming or simulation         
// files), and any associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License Subscription         
// Agreement, Altera MegaCore Function License Agreement, or other applicable     
// license agreement, including, without limitation, that your use is for the     
// sole purpose of programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the applicable         
// agreement for further details.                                                 
    




//altfp_sqrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=28 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock data result
//VERSION_BEGIN 11.0 cbx_altfp_sqrt 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



//alt_sqrt_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=28 WIDTH_SQRT=25 aclr clken clock rad root_result
//VERSION_BEGIN 11.0 cbx_altfp_sqrt 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ  VERSION_END

//synthesis_resources = lpm_add_sub 25 reg 1034 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  acl_fp_sqrt_alt_sqrt_block_6hb
	( 
	aclr,
	clken,
	clock,
	rad,
	root_result) ;
	input   aclr;
	input   clken;
	input   clock;
	input   [25:0]  rad;
	output   [24:0]  root_result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   aclr;
	tri1   clken;
	tri0   clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[23:0]	q_ff0c;
	reg	[23:0]	q_ff10c;
	reg	[23:0]	q_ff11c;
	reg	[23:0]	q_ff12c;
	reg	[23:0]	q_ff13c;
	reg	[23:0]	q_ff14c;
	reg	[23:0]	q_ff15c;
	reg	[23:0]	q_ff16c;
	reg	[23:0]	q_ff17c;
	reg	[23:0]	q_ff18c;
	reg	[23:0]	q_ff19c;
	reg	[23:0]	q_ff1c;
	reg	[23:0]	q_ff20c;
	reg	[23:0]	q_ff21c;
	reg	[23:0]	q_ff22c;
	reg	[23:0]	q_ff23c;
	reg	[23:0]	q_ff2c;
	reg	[23:0]	q_ff3c;
	reg	[23:0]	q_ff4c;
	reg	[23:0]	q_ff5c;
	reg	[23:0]	q_ff6c;
	reg	[23:0]	q_ff7c;
	reg	[23:0]	q_ff8c;
	reg	[23:0]	q_ff9c;
	reg	[25:0]	rad_ff0c;
	reg	[15:0]	rad_ff10c;
	reg	[14:0]	rad_ff11c;
	reg	[13:0]	rad_ff12c;
	reg	[12:0]	rad_ff13c;
	reg	[13:0]	rad_ff14c;
	reg	[14:0]	rad_ff15c;
	reg	[15:0]	rad_ff16c;
	reg	[16:0]	rad_ff17c;
	reg	[17:0]	rad_ff18c;
	reg	[18:0]	rad_ff19c;
	reg	[24:0]	rad_ff1c;
	reg	[19:0]	rad_ff20c;
	reg	[20:0]	rad_ff21c;
	reg	[21:0]	rad_ff22c;
	reg	[22:0]	rad_ff23c;
	reg	[23:0]	rad_ff2c;
	reg	[22:0]	rad_ff3c;
	reg	[21:0]	rad_ff4c;
	reg	[20:0]	rad_ff5c;
	reg	[19:0]	rad_ff6c;
	reg	[18:0]	rad_ff7c;
	reg	[17:0]	rad_ff8c;
	reg	[16:0]	rad_ff9c;
	wire  [8:0]   wire_add_sub10_result;
	wire  [9:0]   wire_add_sub11_result;
	wire  [10:0]   wire_add_sub12_result;
	wire  [11:0]   wire_add_sub13_result;
	wire  [12:0]   wire_add_sub14_result;
	wire  [13:0]   wire_add_sub15_result;
	wire  [13:0]   wire_add_sub16_result;
	wire  [12:0]   wire_add_sub17_result;
	wire  [13:0]   wire_add_sub18_result;
	wire  [14:0]   wire_add_sub19_result;
	wire  [15:0]   wire_add_sub20_result;
	wire  [16:0]   wire_add_sub21_result;
	wire  [17:0]   wire_add_sub22_result;
	wire  [18:0]   wire_add_sub23_result;
	wire  [19:0]   wire_add_sub24_result;
	wire  [20:0]   wire_add_sub25_result;
	wire  [21:0]   wire_add_sub26_result;
	wire  [22:0]   wire_add_sub27_result;
	wire  [23:0]   wire_add_sub28_result;
	wire  [2:0]   wire_add_sub4_result;
	wire  [3:0]   wire_add_sub5_result;
	wire  [4:0]   wire_add_sub6_result;
	wire  [5:0]   wire_add_sub7_result;
	wire  [6:0]   wire_add_sub8_result;
	wire  [7:0]   wire_add_sub9_result;
	wire  [26:0]  addnode_w0c;
	wire  [26:0]  addnode_w10c;
	wire  [26:0]  addnode_w11c;
	wire  [26:0]  addnode_w12c;
	wire  [26:0]  addnode_w13c;
	wire  [26:0]  addnode_w14c;
	wire  [26:0]  addnode_w15c;
	wire  [26:0]  addnode_w16c;
	wire  [26:0]  addnode_w17c;
	wire  [26:0]  addnode_w18c;
	wire  [26:0]  addnode_w19c;
	wire  [26:0]  addnode_w1c;
	wire  [26:0]  addnode_w20c;
	wire  [26:0]  addnode_w21c;
	wire  [26:0]  addnode_w22c;
	wire  [26:0]  addnode_w23c;
	wire  [26:0]  addnode_w24c;
	wire  [26:0]  addnode_w2c;
	wire  [26:0]  addnode_w3c;
	wire  [26:0]  addnode_w4c;
	wire  [26:0]  addnode_w5c;
	wire  [26:0]  addnode_w6c;
	wire  [26:0]  addnode_w7c;
	wire  [26:0]  addnode_w8c;
	wire  [26:0]  addnode_w9c;
	wire  [2:0]  qlevel_w0c;
	wire  [12:0]  qlevel_w10c;
	wire  [13:0]  qlevel_w11c;
	wire  [14:0]  qlevel_w12c;
	wire  [15:0]  qlevel_w13c;
	wire  [16:0]  qlevel_w14c;
	wire  [17:0]  qlevel_w15c;
	wire  [18:0]  qlevel_w16c;
	wire  [19:0]  qlevel_w17c;
	wire  [20:0]  qlevel_w18c;
	wire  [21:0]  qlevel_w19c;
	wire  [3:0]  qlevel_w1c;
	wire  [22:0]  qlevel_w20c;
	wire  [23:0]  qlevel_w21c;
	wire  [24:0]  qlevel_w22c;
	wire  [25:0]  qlevel_w23c;
	wire  [26:0]  qlevel_w24c;
	wire  [4:0]  qlevel_w2c;
	wire  [5:0]  qlevel_w3c;
	wire  [6:0]  qlevel_w4c;
	wire  [7:0]  qlevel_w5c;
	wire  [8:0]  qlevel_w6c;
	wire  [9:0]  qlevel_w7c;
	wire  [10:0]  qlevel_w8c;
	wire  [11:0]  qlevel_w9c;
	wire  [26:0]  slevel_w0c;
	wire  [26:0]  slevel_w10c;
	wire  [26:0]  slevel_w11c;
	wire  [26:0]  slevel_w12c;
	wire  [26:0]  slevel_w13c;
	wire  [26:0]  slevel_w14c;
	wire  [26:0]  slevel_w15c;
	wire  [26:0]  slevel_w16c;
	wire  [26:0]  slevel_w17c;
	wire  [26:0]  slevel_w18c;
	wire  [26:0]  slevel_w19c;
	wire  [26:0]  slevel_w1c;
	wire  [26:0]  slevel_w20c;
	wire  [26:0]  slevel_w21c;
	wire  [26:0]  slevel_w22c;
	wire  [26:0]  slevel_w23c;
	wire  [26:0]  slevel_w24c;
	wire  [26:0]  slevel_w2c;
	wire  [26:0]  slevel_w3c;
	wire  [26:0]  slevel_w4c;
	wire  [26:0]  slevel_w5c;
	wire  [26:0]  slevel_w6c;
	wire  [26:0]  slevel_w7c;
	wire  [26:0]  slevel_w8c;
	wire  [26:0]  slevel_w9c;

	// synopsys translate_off
	initial
		q_ff0c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff0c <= 24'b0;
		else if  (clken == 1'b1)   q_ff0c <= {q_ff0c[22:0], (~ addnode_w24c[26])};
	// synopsys translate_off
	initial
		q_ff10c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff10c <= 24'b0;
		else if  (clken == 1'b1)   q_ff10c <= {q_ff10c[22:0], (~ addnode_w14c[26])};
	// synopsys translate_off
	initial
		q_ff11c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff11c <= 24'b0;
		else if  (clken == 1'b1)   q_ff11c <= {q_ff11c[22:0], (~ addnode_w13c[26])};
	// synopsys translate_off
	initial
		q_ff12c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff12c <= 24'b0;
		else if  (clken == 1'b1)   q_ff12c <= {q_ff12c[22:0], (~ addnode_w12c[26])};
	// synopsys translate_off
	initial
		q_ff13c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff13c <= 24'b0;
		else if  (clken == 1'b1)   q_ff13c <= {q_ff13c[22:0], (~ addnode_w11c[26])};
	// synopsys translate_off
	initial
		q_ff14c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff14c <= 24'b0;
		else if  (clken == 1'b1)   q_ff14c <= {q_ff14c[22:0], (~ addnode_w10c[26])};
	// synopsys translate_off
	initial
		q_ff15c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff15c <= 24'b0;
		else if  (clken == 1'b1)   q_ff15c <= {q_ff15c[22:0], (~ addnode_w9c[26])};
	// synopsys translate_off
	initial
		q_ff16c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff16c <= 24'b0;
		else if  (clken == 1'b1)   q_ff16c <= {q_ff16c[22:0], (~ addnode_w8c[26])};
	// synopsys translate_off
	initial
		q_ff17c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff17c <= 24'b0;
		else if  (clken == 1'b1)   q_ff17c <= {q_ff17c[22:0], (~ addnode_w7c[26])};
	// synopsys translate_off
	initial
		q_ff18c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff18c <= 24'b0;
		else if  (clken == 1'b1)   q_ff18c <= {q_ff18c[22:0], (~ addnode_w6c[26])};
	// synopsys translate_off
	initial
		q_ff19c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff19c <= 24'b0;
		else if  (clken == 1'b1)   q_ff19c <= {q_ff19c[22:0], (~ addnode_w5c[26])};
	// synopsys translate_off
	initial
		q_ff1c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff1c <= 24'b0;
		else if  (clken == 1'b1)   q_ff1c <= {q_ff1c[22:0], (~ addnode_w23c[26])};
	// synopsys translate_off
	initial
		q_ff20c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff20c <= 24'b0;
		else if  (clken == 1'b1)   q_ff20c <= {q_ff20c[22:0], (~ addnode_w4c[26])};
	// synopsys translate_off
	initial
		q_ff21c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff21c <= 24'b0;
		else if  (clken == 1'b1)   q_ff21c <= {q_ff21c[22:0], (~ addnode_w3c[26])};
	// synopsys translate_off
	initial
		q_ff22c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff22c <= 24'b0;
		else if  (clken == 1'b1)   q_ff22c <= {q_ff22c[22:0], (~ addnode_w2c[26])};
	// synopsys translate_off
	initial
		q_ff23c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff23c <= 24'b0;
		else if  (clken == 1'b1)   q_ff23c <= {q_ff23c[22:0], (~ addnode_w1c[26])};
	// synopsys translate_off
	initial
		q_ff2c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff2c <= 24'b0;
		else if  (clken == 1'b1)   q_ff2c <= {q_ff2c[22:0], (~ addnode_w22c[26])};
	// synopsys translate_off
	initial
		q_ff3c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff3c <= 24'b0;
		else if  (clken == 1'b1)   q_ff3c <= {q_ff3c[22:0], (~ addnode_w21c[26])};
	// synopsys translate_off
	initial
		q_ff4c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff4c <= 24'b0;
		else if  (clken == 1'b1)   q_ff4c <= {q_ff4c[22:0], (~ addnode_w20c[26])};
	// synopsys translate_off
	initial
		q_ff5c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff5c <= 24'b0;
		else if  (clken == 1'b1)   q_ff5c <= {q_ff5c[22:0], (~ addnode_w19c[26])};
	// synopsys translate_off
	initial
		q_ff6c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff6c <= 24'b0;
		else if  (clken == 1'b1)   q_ff6c <= {q_ff6c[22:0], (~ addnode_w18c[26])};
	// synopsys translate_off
	initial
		q_ff7c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff7c <= 24'b0;
		else if  (clken == 1'b1)   q_ff7c <= {q_ff7c[22:0], (~ addnode_w17c[26])};
	// synopsys translate_off
	initial
		q_ff8c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff8c <= 24'b0;
		else if  (clken == 1'b1)   q_ff8c <= {q_ff8c[22:0], (~ addnode_w16c[26])};
	// synopsys translate_off
	initial
		q_ff9c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) q_ff9c <= 24'b0;
		else if  (clken == 1'b1)   q_ff9c <= {q_ff9c[22:0], (~ addnode_w15c[26])};
	// synopsys translate_off
	initial
		rad_ff0c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff0c <= 26'b0;
		else if  (clken == 1'b1)   rad_ff0c <= addnode_w0c[26:1];
	// synopsys translate_off
	initial
		rad_ff10c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff10c <= 16'b0;
		else if  (clken == 1'b1)   rad_ff10c <= addnode_w10c[26:11];
	// synopsys translate_off
	initial
		rad_ff11c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff11c <= 15'b0;
		else if  (clken == 1'b1)   rad_ff11c <= addnode_w11c[26:12];
	// synopsys translate_off
	initial
		rad_ff12c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff12c <= 14'b0;
		else if  (clken == 1'b1)   rad_ff12c <= addnode_w12c[26:13];
	// synopsys translate_off
	initial
		rad_ff13c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff13c <= 13'b0;
		else if  (clken == 1'b1)   rad_ff13c <= addnode_w13c[26:14];
	// synopsys translate_off
	initial
		rad_ff14c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff14c <= 14'b0;
		else if  (clken == 1'b1)   rad_ff14c <= addnode_w14c[26:13];
	// synopsys translate_off
	initial
		rad_ff15c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff15c <= 15'b0;
		else if  (clken == 1'b1)   rad_ff15c <= addnode_w15c[26:12];
	// synopsys translate_off
	initial
		rad_ff16c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff16c <= 16'b0;
		else if  (clken == 1'b1)   rad_ff16c <= addnode_w16c[26:11];
	// synopsys translate_off
	initial
		rad_ff17c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff17c <= 17'b0;
		else if  (clken == 1'b1)   rad_ff17c <= addnode_w17c[26:10];
	// synopsys translate_off
	initial
		rad_ff18c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff18c <= 18'b0;
		else if  (clken == 1'b1)   rad_ff18c <= addnode_w18c[26:9];
	// synopsys translate_off
	initial
		rad_ff19c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff19c <= 19'b0;
		else if  (clken == 1'b1)   rad_ff19c <= addnode_w19c[26:8];
	// synopsys translate_off
	initial
		rad_ff1c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff1c <= 25'b0;
		else if  (clken == 1'b1)   rad_ff1c <= addnode_w1c[26:2];
	// synopsys translate_off
	initial
		rad_ff20c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff20c <= 20'b0;
		else if  (clken == 1'b1)   rad_ff20c <= addnode_w20c[26:7];
	// synopsys translate_off
	initial
		rad_ff21c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff21c <= 21'b0;
		else if  (clken == 1'b1)   rad_ff21c <= addnode_w21c[26:6];
	// synopsys translate_off
	initial
		rad_ff22c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff22c <= 22'b0;
		else if  (clken == 1'b1)   rad_ff22c <= addnode_w22c[26:5];
	// synopsys translate_off
	initial
		rad_ff23c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff23c <= 23'b0;
		else if  (clken == 1'b1)   rad_ff23c <= addnode_w23c[26:4];
	// synopsys translate_off
	initial
		rad_ff2c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff2c <= 24'b0;
		else if  (clken == 1'b1)   rad_ff2c <= addnode_w2c[26:3];
	// synopsys translate_off
	initial
		rad_ff3c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff3c <= 23'b0;
		else if  (clken == 1'b1)   rad_ff3c <= addnode_w3c[26:4];
	// synopsys translate_off
	initial
		rad_ff4c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff4c <= 22'b0;
		else if  (clken == 1'b1)   rad_ff4c <= addnode_w4c[26:5];
	// synopsys translate_off
	initial
		rad_ff5c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff5c <= 21'b0;
		else if  (clken == 1'b1)   rad_ff5c <= addnode_w5c[26:6];
	// synopsys translate_off
	initial
		rad_ff6c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff6c <= 20'b0;
		else if  (clken == 1'b1)   rad_ff6c <= addnode_w6c[26:7];
	// synopsys translate_off
	initial
		rad_ff7c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff7c <= 19'b0;
		else if  (clken == 1'b1)   rad_ff7c <= addnode_w7c[26:8];
	// synopsys translate_off
	initial
		rad_ff8c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff8c <= 18'b0;
		else if  (clken == 1'b1)   rad_ff8c <= addnode_w8c[26:9];
	// synopsys translate_off
	initial
		rad_ff9c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) rad_ff9c <= 17'b0;
		else if  (clken == 1'b1)   rad_ff9c <= addnode_w9c[26:10];
	lpm_add_sub   add_sub10
	( 
	.cout(),
	.dataa({slevel_w6c[26:18]}),
	.datab({(({7{(~ rad_ff5c[20])}} & (~ qlevel_w6c[8:2])) | ({7{rad_ff5c[20]}} & qlevel_w6c[8:2])), qlevel_w6c[1:0]}),
	.overflow(),
	.result(wire_add_sub10_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub10.lpm_direction = "ADD",
		add_sub10.lpm_pipeline = 0,
		add_sub10.lpm_width = 9,
		add_sub10.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub11
	( 
	.cout(),
	.dataa({slevel_w7c[26:17]}),
	.datab({(({8{(~ rad_ff6c[19])}} & (~ qlevel_w7c[9:2])) | ({8{rad_ff6c[19]}} & qlevel_w7c[9:2])), qlevel_w7c[1:0]}),
	.overflow(),
	.result(wire_add_sub11_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub11.lpm_direction = "ADD",
		add_sub11.lpm_pipeline = 0,
		add_sub11.lpm_width = 10,
		add_sub11.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub12
	( 
	.cout(),
	.dataa({slevel_w8c[26:16]}),
	.datab({(({9{(~ rad_ff7c[18])}} & (~ qlevel_w8c[10:2])) | ({9{rad_ff7c[18]}} & qlevel_w8c[10:2])), qlevel_w8c[1:0]}),
	.overflow(),
	.result(wire_add_sub12_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub12.lpm_direction = "ADD",
		add_sub12.lpm_pipeline = 0,
		add_sub12.lpm_width = 11,
		add_sub12.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub13
	( 
	.cout(),
	.dataa({slevel_w9c[26:15]}),
	.datab({(({10{(~ rad_ff8c[17])}} & (~ qlevel_w9c[11:2])) | ({10{rad_ff8c[17]}} & qlevel_w9c[11:2])), qlevel_w9c[1:0]}),
	.overflow(),
	.result(wire_add_sub13_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub13.lpm_direction = "ADD",
		add_sub13.lpm_pipeline = 0,
		add_sub13.lpm_width = 12,
		add_sub13.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub14
	( 
	.cout(),
	.dataa({slevel_w10c[26:14]}),
	.datab({(({11{(~ rad_ff9c[16])}} & (~ qlevel_w10c[12:2])) | ({11{rad_ff9c[16]}} & qlevel_w10c[12:2])), qlevel_w10c[1:0]}),
	.overflow(),
	.result(wire_add_sub14_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub14.lpm_direction = "ADD",
		add_sub14.lpm_pipeline = 0,
		add_sub14.lpm_width = 13,
		add_sub14.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub15
	( 
	.cout(),
	.dataa({slevel_w11c[26:13]}),
	.datab({(({12{(~ rad_ff10c[15])}} & (~ qlevel_w11c[13:2])) | ({12{rad_ff10c[15]}} & qlevel_w11c[13:2])), qlevel_w11c[1:0]}),
	.overflow(),
	.result(wire_add_sub15_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub15.lpm_direction = "ADD",
		add_sub15.lpm_pipeline = 0,
		add_sub15.lpm_width = 14,
		add_sub15.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub16
	( 
	.cout(),
	.dataa({slevel_w12c[26:13]}),
	.datab({(({13{(~ rad_ff11c[14])}} & (~ qlevel_w12c[14:2])) | ({13{rad_ff11c[14]}} & qlevel_w12c[14:2])), qlevel_w12c[1]}),
	.overflow(),
	.result(wire_add_sub16_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub16.lpm_direction = "ADD",
		add_sub16.lpm_pipeline = 0,
		add_sub16.lpm_width = 14,
		add_sub16.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub17
	( 
	.cout(),
	.dataa({slevel_w13c[26:14]}),
	.datab({(({13{(~ rad_ff12c[13])}} & (~ qlevel_w13c[15:3])) | ({13{rad_ff12c[13]}} & qlevel_w13c[15:3]))}),
	.overflow(),
	.result(wire_add_sub17_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub17.lpm_direction = "ADD",
		add_sub17.lpm_pipeline = 0,
		add_sub17.lpm_width = 13,
		add_sub17.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub18
	( 
	.cout(),
	.dataa({slevel_w14c[26:13]}),
	.datab({(({14{(~ rad_ff13c[12])}} & (~ qlevel_w14c[16:3])) | ({14{rad_ff13c[12]}} & qlevel_w14c[16:3]))}),
	.overflow(),
	.result(wire_add_sub18_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub18.lpm_direction = "ADD",
		add_sub18.lpm_pipeline = 0,
		add_sub18.lpm_width = 14,
		add_sub18.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub19
	( 
	.cout(),
	.dataa({slevel_w15c[26:12]}),
	.datab({(({15{(~ rad_ff14c[13])}} & (~ qlevel_w15c[17:3])) | ({15{rad_ff14c[13]}} & qlevel_w15c[17:3]))}),
	.overflow(),
	.result(wire_add_sub19_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub19.lpm_direction = "ADD",
		add_sub19.lpm_pipeline = 0,
		add_sub19.lpm_width = 15,
		add_sub19.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub20
	( 
	.cout(),
	.dataa({slevel_w16c[26:11]}),
	.datab({(({16{(~ rad_ff15c[14])}} & (~ qlevel_w16c[18:3])) | ({16{rad_ff15c[14]}} & qlevel_w16c[18:3]))}),
	.overflow(),
	.result(wire_add_sub20_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub20.lpm_direction = "ADD",
		add_sub20.lpm_pipeline = 0,
		add_sub20.lpm_width = 16,
		add_sub20.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub21
	( 
	.cout(),
	.dataa({slevel_w17c[26:10]}),
	.datab({(({17{(~ rad_ff16c[15])}} & (~ qlevel_w17c[19:3])) | ({17{rad_ff16c[15]}} & qlevel_w17c[19:3]))}),
	.overflow(),
	.result(wire_add_sub21_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub21.lpm_direction = "ADD",
		add_sub21.lpm_pipeline = 0,
		add_sub21.lpm_width = 17,
		add_sub21.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub22
	( 
	.cout(),
	.dataa({slevel_w18c[26:9]}),
	.datab({(({18{(~ rad_ff17c[16])}} & (~ qlevel_w18c[20:3])) | ({18{rad_ff17c[16]}} & qlevel_w18c[20:3]))}),
	.overflow(),
	.result(wire_add_sub22_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub22.lpm_direction = "ADD",
		add_sub22.lpm_pipeline = 0,
		add_sub22.lpm_width = 18,
		add_sub22.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub23
	( 
	.cout(),
	.dataa({slevel_w19c[26:8]}),
	.datab({(({19{(~ rad_ff18c[17])}} & (~ qlevel_w19c[21:3])) | ({19{rad_ff18c[17]}} & qlevel_w19c[21:3]))}),
	.overflow(),
	.result(wire_add_sub23_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub23.lpm_direction = "ADD",
		add_sub23.lpm_pipeline = 0,
		add_sub23.lpm_width = 19,
		add_sub23.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub24
	( 
	.cout(),
	.dataa({slevel_w20c[26:7]}),
	.datab({(({20{(~ rad_ff19c[18])}} & (~ qlevel_w20c[22:3])) | ({20{rad_ff19c[18]}} & qlevel_w20c[22:3]))}),
	.overflow(),
	.result(wire_add_sub24_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub24.lpm_direction = "ADD",
		add_sub24.lpm_pipeline = 0,
		add_sub24.lpm_width = 20,
		add_sub24.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub25
	( 
	.cout(),
	.dataa({slevel_w21c[26:6]}),
	.datab({(({21{(~ rad_ff20c[19])}} & (~ qlevel_w21c[23:3])) | ({21{rad_ff20c[19]}} & qlevel_w21c[23:3]))}),
	.overflow(),
	.result(wire_add_sub25_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub25.lpm_direction = "ADD",
		add_sub25.lpm_pipeline = 0,
		add_sub25.lpm_width = 21,
		add_sub25.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub26
	( 
	.cout(),
	.dataa({slevel_w22c[26:5]}),
	.datab({(({22{(~ rad_ff21c[20])}} & (~ qlevel_w22c[24:3])) | ({22{rad_ff21c[20]}} & qlevel_w22c[24:3]))}),
	.overflow(),
	.result(wire_add_sub26_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub26.lpm_direction = "ADD",
		add_sub26.lpm_pipeline = 0,
		add_sub26.lpm_width = 22,
		add_sub26.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub27
	( 
	.cout(),
	.dataa({slevel_w23c[26:4]}),
	.datab({(({23{(~ rad_ff22c[21])}} & (~ qlevel_w23c[25:3])) | ({23{rad_ff22c[21]}} & qlevel_w23c[25:3]))}),
	.overflow(),
	.result(wire_add_sub27_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub27.lpm_direction = "ADD",
		add_sub27.lpm_pipeline = 0,
		add_sub27.lpm_width = 23,
		add_sub27.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub28
	( 
	.cout(),
	.dataa({slevel_w24c[26:3]}),
	.datab({qlevel_w24c[26:25], (({22{(~ rad_ff23c[22])}} & (~ qlevel_w24c[24:3])) | ({22{rad_ff23c[22]}} & qlevel_w24c[24:3]))}),
	.overflow(),
	.result(wire_add_sub28_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub28.lpm_direction = "ADD",
		add_sub28.lpm_pipeline = 0,
		add_sub28.lpm_width = 24,
		add_sub28.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub4
	( 
	.cout(),
	.dataa({slevel_w0c[26:24]}),
	.datab({qlevel_w0c[2:0]}),
	.overflow(),
	.result(wire_add_sub4_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub4.lpm_direction = "ADD",
		add_sub4.lpm_pipeline = 0,
		add_sub4.lpm_width = 3,
		add_sub4.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub5
	( 
	.cout(),
	.dataa({slevel_w1c[26:23]}),
	.datab({qlevel_w1c[3:0]}),
	.overflow(),
	.result(wire_add_sub5_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub5.lpm_direction = "ADD",
		add_sub5.lpm_pipeline = 0,
		add_sub5.lpm_width = 4,
		add_sub5.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub6
	( 
	.cout(),
	.dataa({slevel_w2c[26:22]}),
	.datab({(({3{(~ rad_ff1c[24])}} & (~ qlevel_w2c[4:2])) | ({3{rad_ff1c[24]}} & qlevel_w2c[4:2])), qlevel_w2c[1:0]}),
	.overflow(),
	.result(wire_add_sub6_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub6.lpm_direction = "ADD",
		add_sub6.lpm_pipeline = 0,
		add_sub6.lpm_width = 5,
		add_sub6.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub7
	( 
	.cout(),
	.dataa({slevel_w3c[26:21]}),
	.datab({(({4{(~ rad_ff2c[23])}} & (~ qlevel_w3c[5:2])) | ({4{rad_ff2c[23]}} & qlevel_w3c[5:2])), qlevel_w3c[1:0]}),
	.overflow(),
	.result(wire_add_sub7_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub7.lpm_direction = "ADD",
		add_sub7.lpm_pipeline = 0,
		add_sub7.lpm_width = 6,
		add_sub7.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub8
	( 
	.cout(),
	.dataa({slevel_w4c[26:20]}),
	.datab({(({5{(~ rad_ff3c[22])}} & (~ qlevel_w4c[6:2])) | ({5{rad_ff3c[22]}} & qlevel_w4c[6:2])), qlevel_w4c[1:0]}),
	.overflow(),
	.result(wire_add_sub8_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub8.lpm_direction = "ADD",
		add_sub8.lpm_pipeline = 0,
		add_sub8.lpm_width = 7,
		add_sub8.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub9
	( 
	.cout(),
	.dataa({slevel_w5c[26:19]}),
	.datab({(({6{(~ rad_ff4c[21])}} & (~ qlevel_w5c[7:2])) | ({6{rad_ff4c[21]}} & qlevel_w5c[7:2])), qlevel_w5c[1:0]}),
	.overflow(),
	.result(wire_add_sub9_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub9.lpm_direction = "ADD",
		add_sub9.lpm_pipeline = 0,
		add_sub9.lpm_width = 8,
		add_sub9.lpm_type = "lpm_add_sub";
	assign
		addnode_w0c = {wire_add_sub4_result[2:0], slevel_w0c[23:0]},
		addnode_w10c = {wire_add_sub14_result[12:0], slevel_w10c[13:0]},
		addnode_w11c = {wire_add_sub15_result[13:0], slevel_w11c[12:0]},
		addnode_w12c = {wire_add_sub16_result[13:0], qlevel_w12c[0], slevel_w12c[11:0]},
		addnode_w13c = {wire_add_sub17_result[12:0], 1'b1, qlevel_w13c[1:0], slevel_w13c[10:0]},
		addnode_w14c = {wire_add_sub18_result[13:0], 1'b1, qlevel_w14c[1:0], slevel_w14c[9:0]},
		addnode_w15c = {wire_add_sub19_result[14:0], 1'b1, qlevel_w15c[1:0], slevel_w15c[8:0]},
		addnode_w16c = {wire_add_sub20_result[15:0], 1'b1, qlevel_w16c[1:0], slevel_w16c[7:0]},
		addnode_w17c = {wire_add_sub21_result[16:0], 1'b1, qlevel_w17c[1:0], slevel_w17c[6:0]},
		addnode_w18c = {wire_add_sub22_result[17:0], 1'b1, qlevel_w18c[1:0], slevel_w18c[5:0]},
		addnode_w19c = {wire_add_sub23_result[18:0], 1'b1, qlevel_w19c[1:0], slevel_w19c[4:0]},
		addnode_w1c = {wire_add_sub5_result[3:0], slevel_w1c[22:0]},
		addnode_w20c = {wire_add_sub24_result[19:0], 1'b1, qlevel_w20c[1:0], slevel_w20c[3:0]},
		addnode_w21c = {wire_add_sub25_result[20:0], 1'b1, qlevel_w21c[1:0], slevel_w21c[2:0]},
		addnode_w22c = {wire_add_sub26_result[21:0], 1'b1, qlevel_w22c[1:0], slevel_w22c[1:0]},
		addnode_w23c = {wire_add_sub27_result[22:0], 1'b1, qlevel_w23c[1:0], slevel_w23c[0]},
		addnode_w24c = {wire_add_sub28_result[23:0], 1'b1, qlevel_w24c[1:0]},
		addnode_w2c = {wire_add_sub6_result[4:0], slevel_w2c[21:0]},
		addnode_w3c = {wire_add_sub7_result[5:0], slevel_w3c[20:0]},
		addnode_w4c = {wire_add_sub8_result[6:0], slevel_w4c[19:0]},
		addnode_w5c = {wire_add_sub9_result[7:0], slevel_w5c[18:0]},
		addnode_w6c = {wire_add_sub10_result[8:0], slevel_w6c[17:0]},
		addnode_w7c = {wire_add_sub11_result[9:0], slevel_w7c[16:0]},
		addnode_w8c = {wire_add_sub12_result[10:0], slevel_w8c[15:0]},
		addnode_w9c = {wire_add_sub13_result[11:0], slevel_w9c[14:0]},
		qlevel_w0c = {3{1'b1}},
		qlevel_w10c = {1'b0, 1'b1, q_ff23c[8], q_ff22c[7], q_ff21c[6], q_ff20c[5], q_ff19c[4], q_ff18c[3], q_ff17c[2], q_ff16c[1], q_ff15c[0], {2{1'b1}}},
		qlevel_w11c = {1'b0, 1'b1, q_ff23c[9], q_ff22c[8], q_ff21c[7], q_ff20c[6], q_ff19c[5], q_ff18c[4], q_ff17c[3], q_ff16c[2], q_ff15c[1], q_ff14c[0], {2{1'b1}}},
		qlevel_w12c = {1'b0, 1'b1, q_ff23c[10], q_ff22c[9], q_ff21c[8], q_ff20c[7], q_ff19c[6], q_ff18c[5], q_ff17c[4], q_ff16c[3], q_ff15c[2], q_ff14c[1], q_ff13c[0], {2{1'b1}}},
		qlevel_w13c = {1'b0, 1'b1, q_ff23c[11], q_ff22c[10], q_ff21c[9], q_ff20c[8], q_ff19c[7], q_ff18c[6], q_ff17c[5], q_ff16c[4], q_ff15c[3], q_ff14c[2], q_ff13c[1], q_ff12c[0], {2{1'b1}}},
		qlevel_w14c = {1'b0, 1'b1, q_ff23c[12], q_ff22c[11], q_ff21c[10], q_ff20c[9], q_ff19c[8], q_ff18c[7], q_ff17c[6], q_ff16c[5], q_ff15c[4], q_ff14c[3], q_ff13c[2], q_ff12c[1], q_ff11c[0], {2{1'b1}}},
		qlevel_w15c = {1'b0, 1'b1, q_ff23c[13], q_ff22c[12], q_ff21c[11], q_ff20c[10], q_ff19c[9], q_ff18c[8], q_ff17c[7], q_ff16c[6], q_ff15c[5], q_ff14c[4], q_ff13c[3], q_ff12c[2], q_ff11c[1], q_ff10c[0], {2{1'b1}}},
		qlevel_w16c = {1'b0, 1'b1, q_ff23c[14], q_ff22c[13], q_ff21c[12], q_ff20c[11], q_ff19c[10], q_ff18c[9], q_ff17c[8], q_ff16c[7], q_ff15c[6], q_ff14c[5], q_ff13c[4], q_ff12c[3], q_ff11c[2], q_ff10c[1], q_ff9c[0], {2{1'b1}}},
		qlevel_w17c = {1'b0, 1'b1, q_ff23c[15], q_ff22c[14], q_ff21c[13], q_ff20c[12], q_ff19c[11], q_ff18c[10], q_ff17c[9], q_ff16c[8], q_ff15c[7], q_ff14c[6], q_ff13c[5], q_ff12c[4], q_ff11c[3], q_ff10c[2], q_ff9c[1], q_ff8c[0], {2{1'b1}}},
		qlevel_w18c = {1'b0, 1'b1, q_ff23c[16], q_ff22c[15], q_ff21c[14], q_ff20c[13], q_ff19c[12], q_ff18c[11], q_ff17c[10], q_ff16c[9], q_ff15c[8], q_ff14c[7], q_ff13c[6], q_ff12c[5], q_ff11c[4], q_ff10c[3], q_ff9c[2], q_ff8c[1], q_ff7c[0], {2{1'b1}}},
		qlevel_w19c = {1'b0, 1'b1, q_ff23c[17], q_ff22c[16], q_ff21c[15], q_ff20c[14], q_ff19c[13], q_ff18c[12], q_ff17c[11], q_ff16c[10], q_ff15c[9], q_ff14c[8], q_ff13c[7], q_ff12c[6], q_ff11c[5], q_ff10c[4], q_ff9c[3], q_ff8c[2], q_ff7c[1], q_ff6c[0], {2{1'b1}}},
		qlevel_w1c = {1'b1, 1'b0, {2{1'b1}}},
		qlevel_w20c = {1'b0, 1'b1, q_ff23c[18], q_ff22c[17], q_ff21c[16], q_ff20c[15], q_ff19c[14], q_ff18c[13], q_ff17c[12], q_ff16c[11], q_ff15c[10], q_ff14c[9], q_ff13c[8], q_ff12c[7], q_ff11c[6], q_ff10c[5], q_ff9c[4], q_ff8c[3], q_ff7c[2], q_ff6c[1], q_ff5c[0], {2{1'b1}}},
		qlevel_w21c = {1'b0, 1'b1, q_ff23c[19], q_ff22c[18], q_ff21c[17], q_ff20c[16], q_ff19c[15], q_ff18c[14], q_ff17c[13], q_ff16c[12], q_ff15c[11], q_ff14c[10], q_ff13c[9], q_ff12c[8], q_ff11c[7], q_ff10c[6], q_ff9c[5], q_ff8c[4], q_ff7c[3], q_ff6c[2], q_ff5c[1], q_ff4c[0], {2{1'b1}}},
		qlevel_w22c = {1'b0, 1'b1, q_ff23c[20], q_ff22c[19], q_ff21c[18], q_ff20c[17], q_ff19c[16], q_ff18c[15], q_ff17c[14], q_ff16c[13], q_ff15c[12], q_ff14c[11], q_ff13c[10], q_ff12c[9], q_ff11c[8], q_ff10c[7], q_ff9c[6], q_ff8c[5], q_ff7c[4], q_ff6c[3], q_ff5c[2], q_ff4c[1], q_ff3c[0], {2{1'b1}}},
		qlevel_w23c = {1'b0, 1'b1, q_ff23c[21], q_ff22c[20], q_ff21c[19], q_ff20c[18], q_ff19c[17], q_ff18c[16], q_ff17c[15], q_ff16c[14], q_ff15c[13], q_ff14c[12], q_ff13c[11], q_ff12c[10], q_ff11c[9], q_ff10c[8], q_ff9c[7], q_ff8c[6], q_ff7c[5], q_ff6c[4], q_ff5c[3], q_ff4c[2], q_ff3c[1], q_ff2c[0], {2{1'b1}}},
		qlevel_w24c = {(~ rad_ff23c[22]), rad_ff23c[22], q_ff23c[22], q_ff22c[21], q_ff21c[20], q_ff20c[19], q_ff19c[18], q_ff18c[17], q_ff17c[16], q_ff16c[15], q_ff15c[14], q_ff14c[13], q_ff13c[12], q_ff12c[11], q_ff11c[10], q_ff10c[9], q_ff9c[8], q_ff8c[7], q_ff7c[6], q_ff6c[5], q_ff5c[4], q_ff4c[3], q_ff3c[2], q_ff2c[1], q_ff1c[0], {2{1'b1}}},
		qlevel_w2c = {1'b0, 1'b1, q_ff23c[0], {2{1'b1}}},
		qlevel_w3c = {1'b0, 1'b1, q_ff23c[1], q_ff22c[0], {2{1'b1}}},
		qlevel_w4c = {1'b0, 1'b1, q_ff23c[2], q_ff22c[1], q_ff21c[0], {2{1'b1}}},
		qlevel_w5c = {1'b0, 1'b1, q_ff23c[3], q_ff22c[2], q_ff21c[1], q_ff20c[0], {2{1'b1}}},
		qlevel_w6c = {1'b0, 1'b1, q_ff23c[4], q_ff22c[3], q_ff21c[2], q_ff20c[1], q_ff19c[0], {2{1'b1}}},
		qlevel_w7c = {1'b0, 1'b1, q_ff23c[5], q_ff22c[4], q_ff21c[3], q_ff20c[2], q_ff19c[1], q_ff18c[0], {2{1'b1}}},
		qlevel_w8c = {1'b0, 1'b1, q_ff23c[6], q_ff22c[5], q_ff21c[4], q_ff20c[3], q_ff19c[2], q_ff18c[1], q_ff17c[0], {2{1'b1}}},
		qlevel_w9c = {1'b0, 1'b1, q_ff23c[7], q_ff22c[6], q_ff21c[5], q_ff20c[4], q_ff19c[3], q_ff18c[2], q_ff17c[1], q_ff16c[0], {2{1'b1}}},
		root_result = {1'b1, q_ff23c[23], q_ff22c[22], q_ff21c[21], q_ff20c[20], q_ff19c[19], q_ff18c[18], q_ff17c[17], q_ff16c[16], q_ff15c[15], q_ff14c[14], q_ff13c[13], q_ff12c[12], q_ff11c[11], q_ff10c[10], q_ff9c[9], q_ff8c[8], q_ff7c[7], q_ff6c[6], q_ff5c[5], q_ff4c[4], q_ff3c[3], q_ff2c[2], q_ff1c[1], q_ff0c[0]},
		slevel_w0c = {1'b0, rad},
		slevel_w10c = {rad_ff9c[15:0], {11{1'b0}}},
		slevel_w11c = {rad_ff10c[14:0], {12{1'b0}}},
		slevel_w12c = {rad_ff11c[13:0], {13{1'b0}}},
		slevel_w13c = {rad_ff12c[12:0], 1'b1, {13{1'b0}}},
		slevel_w14c = {rad_ff13c[11:0], {3{1'b1}}, {12{1'b0}}},
		slevel_w15c = {rad_ff14c[12:0], {3{1'b1}}, {11{1'b0}}},
		slevel_w16c = {rad_ff15c[13:0], {3{1'b1}}, {10{1'b0}}},
		slevel_w17c = {rad_ff16c[14:0], {3{1'b1}}, {9{1'b0}}},
		slevel_w18c = {rad_ff17c[15:0], {3{1'b1}}, {8{1'b0}}},
		slevel_w19c = {rad_ff18c[16:0], {3{1'b1}}, {7{1'b0}}},
		slevel_w1c = {rad_ff0c[24:0], {2{1'b0}}},
		slevel_w20c = {rad_ff19c[17:0], {3{1'b1}}, {6{1'b0}}},
		slevel_w21c = {rad_ff20c[18:0], {3{1'b1}}, {5{1'b0}}},
		slevel_w22c = {rad_ff21c[19:0], {3{1'b1}}, {4{1'b0}}},
		slevel_w23c = {rad_ff22c[20:0], {3{1'b1}}, {3{1'b0}}},
		slevel_w24c = {rad_ff23c[21:0], {3{1'b1}}, {2{1'b0}}},
		slevel_w2c = {rad_ff1c[23:0], {3{1'b0}}},
		slevel_w3c = {rad_ff2c[22:0], {4{1'b0}}},
		slevel_w4c = {rad_ff3c[21:0], {5{1'b0}}},
		slevel_w5c = {rad_ff4c[20:0], {6{1'b0}}},
		slevel_w6c = {rad_ff5c[19:0], {7{1'b0}}},
		slevel_w7c = {rad_ff6c[18:0], {8{1'b0}}},
		slevel_w8c = {rad_ff7c[17:0], {9{1'b0}}},
		slevel_w9c = {rad_ff8c[16:0], {10{1'b0}}};
endmodule //acl_fp_sqrt_alt_sqrt_block_6hb

//synthesis_resources = lpm_add_sub 27 reg 1433 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  acl_fp_sqrt_altfp_sqrt_rbd
	( 
	clk_en,
	clock,
	data,
	result) ;
	input   clk_en;
	input   clock;
	input   [31:0]  data;
	output   [31:0]  result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1   clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  [24:0]   wire_alt_sqrt_block2_root_result;
	reg	exp_all_one_ff;
	reg	[7:0]	exp_ff1;
	reg	[7:0]	exp_ff20c;
	reg	[7:0]	exp_ff210c;
	reg	[7:0]	exp_ff211c;
	reg	[7:0]	exp_ff212c;
	reg	[7:0]	exp_ff213c;
	reg	[7:0]	exp_ff214c;
	reg	[7:0]	exp_ff215c;
	reg	[7:0]	exp_ff216c;
	reg	[7:0]	exp_ff217c;
	reg	[7:0]	exp_ff218c;
	reg	[7:0]	exp_ff219c;
	reg	[7:0]	exp_ff21c;
	reg	[7:0]	exp_ff220c;
	reg	[7:0]	exp_ff221c;
	reg	[7:0]	exp_ff222c;
	reg	[7:0]	exp_ff223c;
	reg	[7:0]	exp_ff224c;
	reg	[7:0]	exp_ff22c;
	reg	[7:0]	exp_ff23c;
	reg	[7:0]	exp_ff24c;
	reg	[7:0]	exp_ff25c;
	reg	[7:0]	exp_ff26c;
	reg	[7:0]	exp_ff27c;
	reg	[7:0]	exp_ff28c;
	reg	[7:0]	exp_ff29c;
	reg	[7:0]	exp_in_ff;
	reg	exp_not_zero_ff;
	reg	[7:0]	exp_result_ff;
	reg	[0:0]	infinity_ff0;
	reg	[0:0]	infinity_ff1;
	reg	[0:0]	infinity_ff2;
	reg	[0:0]	infinity_ff3;
	reg	[0:0]	infinity_ff4;
	reg	[0:0]	infinity_ff5;
	reg	[0:0]	infinity_ff6;
	reg	[0:0]	infinity_ff7;
	reg	[0:0]	infinity_ff8;
	reg	[0:0]	infinity_ff9;
	reg	[0:0]	infinity_ff10;
	reg	[0:0]	infinity_ff11;
	reg	[0:0]	infinity_ff12;
	reg	[0:0]	infinity_ff13;
	reg	[0:0]	infinity_ff14;
	reg	[0:0]	infinity_ff15;
	reg	[0:0]	infinity_ff16;
	reg	[0:0]	infinity_ff17;
	reg	[0:0]	infinity_ff18;
	reg	[0:0]	infinity_ff19;
	reg	[0:0]	infinity_ff20;
	reg	[0:0]	infinity_ff21;
	reg	[0:0]	infinity_ff22;
	reg	[0:0]	infinity_ff23;
	reg	[0:0]	infinity_ff24;
	reg	[22:0]	man_in_ff;
	reg	man_not_zero_ff;
	reg	[22:0]	man_result_ff;
	reg	[22:0]	man_rounding_ff;
	reg	[0:0]	nan_man_ff0;
	reg	[0:0]	nan_man_ff1;
	reg	[0:0]	nan_man_ff2;
	reg	[0:0]	nan_man_ff3;
	reg	[0:0]	nan_man_ff4;
	reg	[0:0]	nan_man_ff5;
	reg	[0:0]	nan_man_ff6;
	reg	[0:0]	nan_man_ff7;
	reg	[0:0]	nan_man_ff8;
	reg	[0:0]	nan_man_ff9;
	reg	[0:0]	nan_man_ff10;
	reg	[0:0]	nan_man_ff11;
	reg	[0:0]	nan_man_ff12;
	reg	[0:0]	nan_man_ff13;
	reg	[0:0]	nan_man_ff14;
	reg	[0:0]	nan_man_ff15;
	reg	[0:0]	nan_man_ff16;
	reg	[0:0]	nan_man_ff17;
	reg	[0:0]	nan_man_ff18;
	reg	[0:0]	nan_man_ff19;
	reg	[0:0]	nan_man_ff20;
	reg	[0:0]	nan_man_ff21;
	reg	[0:0]	nan_man_ff22;
	reg	[0:0]	nan_man_ff23;
	reg	[0:0]	nan_man_ff24;
	reg	[0:0]	sign_node_ff0;
	reg	[0:0]	sign_node_ff1;
	reg	[0:0]	sign_node_ff2;
	reg	[0:0]	sign_node_ff3;
	reg	[0:0]	sign_node_ff4;
	reg	[0:0]	sign_node_ff5;
	reg	[0:0]	sign_node_ff6;
	reg	[0:0]	sign_node_ff7;
	reg	[0:0]	sign_node_ff8;
	reg	[0:0]	sign_node_ff9;
	reg	[0:0]	sign_node_ff10;
	reg	[0:0]	sign_node_ff11;
	reg	[0:0]	sign_node_ff12;
	reg	[0:0]	sign_node_ff13;
	reg	[0:0]	sign_node_ff14;
	reg	[0:0]	sign_node_ff15;
	reg	[0:0]	sign_node_ff16;
	reg	[0:0]	sign_node_ff17;
	reg	[0:0]	sign_node_ff18;
	reg	[0:0]	sign_node_ff19;
	reg	[0:0]	sign_node_ff20;
	reg	[0:0]	sign_node_ff21;
	reg	[0:0]	sign_node_ff22;
	reg	[0:0]	sign_node_ff23;
	reg	[0:0]	sign_node_ff24;
	reg	[0:0]	sign_node_ff25;
	reg	[0:0]	sign_node_ff26;
	reg	[0:0]	sign_node_ff27;
	reg	[0:0]	zero_exp_ff0;
	reg	[0:0]	zero_exp_ff1;
	reg	[0:0]	zero_exp_ff2;
	reg	[0:0]	zero_exp_ff3;
	reg	[0:0]	zero_exp_ff4;
	reg	[0:0]	zero_exp_ff5;
	reg	[0:0]	zero_exp_ff6;
	reg	[0:0]	zero_exp_ff7;
	reg	[0:0]	zero_exp_ff8;
	reg	[0:0]	zero_exp_ff9;
	reg	[0:0]	zero_exp_ff10;
	reg	[0:0]	zero_exp_ff11;
	reg	[0:0]	zero_exp_ff12;
	reg	[0:0]	zero_exp_ff13;
	reg	[0:0]	zero_exp_ff14;
	reg	[0:0]	zero_exp_ff15;
	reg	[0:0]	zero_exp_ff16;
	reg	[0:0]	zero_exp_ff17;
	reg	[0:0]	zero_exp_ff18;
	reg	[0:0]	zero_exp_ff19;
	reg	[0:0]	zero_exp_ff20;
	reg	[0:0]	zero_exp_ff21;
	reg	[0:0]	zero_exp_ff22;
	reg	[0:0]	zero_exp_ff23;
	reg	[0:0]	zero_exp_ff24;
	wire  [8:0]   wire_add_sub1_result;
	wire  [22:0]   wire_add_sub3_result;
	wire aclr;
	wire  [7:0]  bias;
	wire  [7:0]  exp_all_one_w;
	wire  [7:0]  exp_div_w;
	wire  [7:0]  exp_ff2_w;
	wire  [7:0]  exp_not_zero_w;
	wire  infinitycondition_w;
	wire  [22:0]  man_not_zero_w;
	wire  [24:0]  man_root_result_w;
	wire  nancondition_w;
	wire  preadjust_w;
	wire  [25:0]  radicand_w;
	wire  roundbit_w;

	acl_fp_sqrt_alt_sqrt_block_6hb   alt_sqrt_block2
	( 
	.aclr(aclr),
	.clken(clk_en),
	.clock(clock),
	.rad(radicand_w),
	.root_result(wire_alt_sqrt_block2_root_result));
	// synopsys translate_off
	initial
		exp_all_one_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_all_one_ff <= 1'b0;
		else if  (clk_en == 1'b1)   exp_all_one_ff <= exp_all_one_w[7];
	// synopsys translate_off
	initial
		exp_ff1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff1 <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff1 <= exp_div_w;
	// synopsys translate_off
	initial
		exp_ff20c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff20c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff20c <= exp_ff1;
	// synopsys translate_off
	initial
		exp_ff210c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff210c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff210c <= exp_ff29c;
	// synopsys translate_off
	initial
		exp_ff211c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff211c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff211c <= exp_ff210c;
	// synopsys translate_off
	initial
		exp_ff212c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff212c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff212c <= exp_ff211c;
	// synopsys translate_off
	initial
		exp_ff213c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff213c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff213c <= exp_ff212c;
	// synopsys translate_off
	initial
		exp_ff214c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff214c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff214c <= exp_ff213c;
	// synopsys translate_off
	initial
		exp_ff215c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff215c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff215c <= exp_ff214c;
	// synopsys translate_off
	initial
		exp_ff216c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff216c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff216c <= exp_ff215c;
	// synopsys translate_off
	initial
		exp_ff217c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff217c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff217c <= exp_ff216c;
	// synopsys translate_off
	initial
		exp_ff218c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff218c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff218c <= exp_ff217c;
	// synopsys translate_off
	initial
		exp_ff219c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff219c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff219c <= exp_ff218c;
	// synopsys translate_off
	initial
		exp_ff21c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff21c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff21c <= exp_ff20c;
	// synopsys translate_off
	initial
		exp_ff220c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff220c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff220c <= exp_ff219c;
	// synopsys translate_off
	initial
		exp_ff221c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff221c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff221c <= exp_ff220c;
	// synopsys translate_off
	initial
		exp_ff222c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff222c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff222c <= exp_ff221c;
	// synopsys translate_off
	initial
		exp_ff223c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff223c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff223c <= exp_ff222c;
	// synopsys translate_off
	initial
		exp_ff224c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff224c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff224c <= exp_ff223c;
	// synopsys translate_off
	initial
		exp_ff22c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff22c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff22c <= exp_ff21c;
	// synopsys translate_off
	initial
		exp_ff23c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff23c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff23c <= exp_ff22c;
	// synopsys translate_off
	initial
		exp_ff24c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff24c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff24c <= exp_ff23c;
	// synopsys translate_off
	initial
		exp_ff25c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff25c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff25c <= exp_ff24c;
	// synopsys translate_off
	initial
		exp_ff26c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff26c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff26c <= exp_ff25c;
	// synopsys translate_off
	initial
		exp_ff27c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff27c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff27c <= exp_ff26c;
	// synopsys translate_off
	initial
		exp_ff28c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff28c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff28c <= exp_ff27c;
	// synopsys translate_off
	initial
		exp_ff29c = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_ff29c <= 8'b0;
		else if  (clk_en == 1'b1)   exp_ff29c <= exp_ff28c;
	// synopsys translate_off
	initial
		exp_in_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_in_ff <= 8'b0;
		else if  (clk_en == 1'b1)   exp_in_ff <= data[30:23];
	// synopsys translate_off
	initial
		exp_not_zero_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_not_zero_ff <= 1'b0;
		else if  (clk_en == 1'b1)   exp_not_zero_ff <= exp_not_zero_w[7];
	// synopsys translate_off
	initial
		exp_result_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) exp_result_ff <= 8'b0;
		else if  (clk_en == 1'b1)   exp_result_ff <= (((exp_ff2_w & {8{zero_exp_ff24[0:0]}}) | {8{nan_man_ff24[0:0]}}) | {8{infinity_ff24[0:0]}});
	// synopsys translate_off
	initial
		infinity_ff0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff0 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff0 <= (infinitycondition_w & (~ sign_node_ff1[0:0]));
	// synopsys translate_off
	initial
		infinity_ff1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff1 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff1 <= infinity_ff0[0:0];
	// synopsys translate_off
	initial
		infinity_ff2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff2 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff2 <= infinity_ff1[0:0];
	// synopsys translate_off
	initial
		infinity_ff3 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff3 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff3 <= infinity_ff2[0:0];
	// synopsys translate_off
	initial
		infinity_ff4 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff4 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff4 <= infinity_ff3[0:0];
	// synopsys translate_off
	initial
		infinity_ff5 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff5 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff5 <= infinity_ff4[0:0];
	// synopsys translate_off
	initial
		infinity_ff6 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff6 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff6 <= infinity_ff5[0:0];
	// synopsys translate_off
	initial
		infinity_ff7 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff7 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff7 <= infinity_ff6[0:0];
	// synopsys translate_off
	initial
		infinity_ff8 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff8 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff8 <= infinity_ff7[0:0];
	// synopsys translate_off
	initial
		infinity_ff9 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff9 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff9 <= infinity_ff8[0:0];
	// synopsys translate_off
	initial
		infinity_ff10 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff10 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff10 <= infinity_ff9[0:0];
	// synopsys translate_off
	initial
		infinity_ff11 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff11 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff11 <= infinity_ff10[0:0];
	// synopsys translate_off
	initial
		infinity_ff12 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff12 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff12 <= infinity_ff11[0:0];
	// synopsys translate_off
	initial
		infinity_ff13 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff13 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff13 <= infinity_ff12[0:0];
	// synopsys translate_off
	initial
		infinity_ff14 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff14 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff14 <= infinity_ff13[0:0];
	// synopsys translate_off
	initial
		infinity_ff15 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff15 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff15 <= infinity_ff14[0:0];
	// synopsys translate_off
	initial
		infinity_ff16 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff16 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff16 <= infinity_ff15[0:0];
	// synopsys translate_off
	initial
		infinity_ff17 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff17 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff17 <= infinity_ff16[0:0];
	// synopsys translate_off
	initial
		infinity_ff18 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff18 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff18 <= infinity_ff17[0:0];
	// synopsys translate_off
	initial
		infinity_ff19 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff19 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff19 <= infinity_ff18[0:0];
	// synopsys translate_off
	initial
		infinity_ff20 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff20 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff20 <= infinity_ff19[0:0];
	// synopsys translate_off
	initial
		infinity_ff21 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff21 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff21 <= infinity_ff20[0:0];
	// synopsys translate_off
	initial
		infinity_ff22 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff22 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff22 <= infinity_ff21[0:0];
	// synopsys translate_off
	initial
		infinity_ff23 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff23 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff23 <= infinity_ff22[0:0];
	// synopsys translate_off
	initial
		infinity_ff24 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) infinity_ff24 <= 1'b0;
		else if  (clk_en == 1'b1)   infinity_ff24 <= infinity_ff23[0:0];
	// synopsys translate_off
	initial
		man_in_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) man_in_ff <= 23'b0;
		else if  (clk_en == 1'b1)   man_in_ff <= data[22:0];
	// synopsys translate_off
	initial
		man_not_zero_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) man_not_zero_ff <= 1'b0;
		else if  (clk_en == 1'b1)   man_not_zero_ff <= man_not_zero_w[22];
	// synopsys translate_off
	initial
		man_result_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) man_result_ff <= 23'b0;
		else if  (clk_en == 1'b1)   man_result_ff <= ((man_rounding_ff & {23{zero_exp_ff24[0:0]}}) | {23{nan_man_ff24[0:0]}});
	// synopsys translate_off
	initial
		man_rounding_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) man_rounding_ff <= 23'b0;
		else if  (clk_en == 1'b1)   man_rounding_ff <= wire_add_sub3_result;
	// synopsys translate_off
	initial
		nan_man_ff0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff0 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff0 <= nancondition_w;
	// synopsys translate_off
	initial
		nan_man_ff1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff1 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff1 <= nan_man_ff0[0:0];
	// synopsys translate_off
	initial
		nan_man_ff2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff2 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff2 <= nan_man_ff1[0:0];
	// synopsys translate_off
	initial
		nan_man_ff3 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff3 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff3 <= nan_man_ff2[0:0];
	// synopsys translate_off
	initial
		nan_man_ff4 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff4 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff4 <= nan_man_ff3[0:0];
	// synopsys translate_off
	initial
		nan_man_ff5 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff5 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff5 <= nan_man_ff4[0:0];
	// synopsys translate_off
	initial
		nan_man_ff6 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff6 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff6 <= nan_man_ff5[0:0];
	// synopsys translate_off
	initial
		nan_man_ff7 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff7 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff7 <= nan_man_ff6[0:0];
	// synopsys translate_off
	initial
		nan_man_ff8 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff8 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff8 <= nan_man_ff7[0:0];
	// synopsys translate_off
	initial
		nan_man_ff9 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff9 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff9 <= nan_man_ff8[0:0];
	// synopsys translate_off
	initial
		nan_man_ff10 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff10 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff10 <= nan_man_ff9[0:0];
	// synopsys translate_off
	initial
		nan_man_ff11 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff11 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff11 <= nan_man_ff10[0:0];
	// synopsys translate_off
	initial
		nan_man_ff12 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff12 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff12 <= nan_man_ff11[0:0];
	// synopsys translate_off
	initial
		nan_man_ff13 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff13 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff13 <= nan_man_ff12[0:0];
	// synopsys translate_off
	initial
		nan_man_ff14 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff14 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff14 <= nan_man_ff13[0:0];
	// synopsys translate_off
	initial
		nan_man_ff15 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff15 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff15 <= nan_man_ff14[0:0];
	// synopsys translate_off
	initial
		nan_man_ff16 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff16 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff16 <= nan_man_ff15[0:0];
	// synopsys translate_off
	initial
		nan_man_ff17 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff17 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff17 <= nan_man_ff16[0:0];
	// synopsys translate_off
	initial
		nan_man_ff18 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff18 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff18 <= nan_man_ff17[0:0];
	// synopsys translate_off
	initial
		nan_man_ff19 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff19 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff19 <= nan_man_ff18[0:0];
	// synopsys translate_off
	initial
		nan_man_ff20 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff20 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff20 <= nan_man_ff19[0:0];
	// synopsys translate_off
	initial
		nan_man_ff21 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff21 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff21 <= nan_man_ff20[0:0];
	// synopsys translate_off
	initial
		nan_man_ff22 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff22 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff22 <= nan_man_ff21[0:0];
	// synopsys translate_off
	initial
		nan_man_ff23 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff23 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff23 <= nan_man_ff22[0:0];
	// synopsys translate_off
	initial
		nan_man_ff24 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) nan_man_ff24 <= 1'b0;
		else if  (clk_en == 1'b1)   nan_man_ff24 <= nan_man_ff23[0:0];
	// synopsys translate_off
	initial
		sign_node_ff0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff0 <= data[31];
	// synopsys translate_off
	initial
		sign_node_ff1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff1 <= sign_node_ff0[0:0];
	// synopsys translate_off
	initial
		sign_node_ff2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff2 <= sign_node_ff1[0:0];
	// synopsys translate_off
	initial
		sign_node_ff3 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff3 <= sign_node_ff2[0:0];
	// synopsys translate_off
	initial
		sign_node_ff4 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff4 <= sign_node_ff3[0:0];
	// synopsys translate_off
	initial
		sign_node_ff5 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff5 <= sign_node_ff4[0:0];
	// synopsys translate_off
	initial
		sign_node_ff6 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff6 <= sign_node_ff5[0:0];
	// synopsys translate_off
	initial
		sign_node_ff7 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff7 <= sign_node_ff6[0:0];
	// synopsys translate_off
	initial
		sign_node_ff8 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff8 <= sign_node_ff7[0:0];
	// synopsys translate_off
	initial
		sign_node_ff9 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff9 <= sign_node_ff8[0:0];
	// synopsys translate_off
	initial
		sign_node_ff10 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff10 <= sign_node_ff9[0:0];
	// synopsys translate_off
	initial
		sign_node_ff11 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff11 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff11 <= sign_node_ff10[0:0];
	// synopsys translate_off
	initial
		sign_node_ff12 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff12 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff12 <= sign_node_ff11[0:0];
	// synopsys translate_off
	initial
		sign_node_ff13 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff13 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff13 <= sign_node_ff12[0:0];
	// synopsys translate_off
	initial
		sign_node_ff14 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff14 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff14 <= sign_node_ff13[0:0];
	// synopsys translate_off
	initial
		sign_node_ff15 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff15 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff15 <= sign_node_ff14[0:0];
	// synopsys translate_off
	initial
		sign_node_ff16 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff16 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff16 <= sign_node_ff15[0:0];
	// synopsys translate_off
	initial
		sign_node_ff17 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff17 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff17 <= sign_node_ff16[0:0];
	// synopsys translate_off
	initial
		sign_node_ff18 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff18 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff18 <= sign_node_ff17[0:0];
	// synopsys translate_off
	initial
		sign_node_ff19 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff19 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff19 <= sign_node_ff18[0:0];
	// synopsys translate_off
	initial
		sign_node_ff20 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff20 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff20 <= sign_node_ff19[0:0];
	// synopsys translate_off
	initial
		sign_node_ff21 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff21 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff21 <= sign_node_ff20[0:0];
	// synopsys translate_off
	initial
		sign_node_ff22 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff22 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff22 <= sign_node_ff21[0:0];
	// synopsys translate_off
	initial
		sign_node_ff23 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff23 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff23 <= sign_node_ff22[0:0];
	// synopsys translate_off
	initial
		sign_node_ff24 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff24 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff24 <= sign_node_ff23[0:0];
	// synopsys translate_off
	initial
		sign_node_ff25 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff25 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff25 <= sign_node_ff24[0:0];
	// synopsys translate_off
	initial
		sign_node_ff26 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff26 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff26 <= sign_node_ff25[0:0];
	// synopsys translate_off
	initial
		sign_node_ff27 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) sign_node_ff27 <= 1'b0;
		else if  (clk_en == 1'b1)   sign_node_ff27 <= sign_node_ff26[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff0 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff0 <= exp_not_zero_ff;
	// synopsys translate_off
	initial
		zero_exp_ff1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff1 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff1 <= zero_exp_ff0[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff2 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff2 <= zero_exp_ff1[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff3 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff3 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff3 <= zero_exp_ff2[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff4 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff4 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff4 <= zero_exp_ff3[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff5 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff5 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff5 <= zero_exp_ff4[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff6 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff6 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff6 <= zero_exp_ff5[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff7 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff7 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff7 <= zero_exp_ff6[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff8 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff8 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff8 <= zero_exp_ff7[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff9 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff9 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff9 <= zero_exp_ff8[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff10 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff10 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff10 <= zero_exp_ff9[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff11 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff11 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff11 <= zero_exp_ff10[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff12 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff12 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff12 <= zero_exp_ff11[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff13 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff13 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff13 <= zero_exp_ff12[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff14 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff14 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff14 <= zero_exp_ff13[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff15 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff15 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff15 <= zero_exp_ff14[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff16 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff16 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff16 <= zero_exp_ff15[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff17 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff17 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff17 <= zero_exp_ff16[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff18 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff18 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff18 <= zero_exp_ff17[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff19 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff19 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff19 <= zero_exp_ff18[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff20 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff20 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff20 <= zero_exp_ff19[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff21 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff21 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff21 <= zero_exp_ff20[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff22 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff22 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff22 <= zero_exp_ff21[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff23 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff23 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff23 <= zero_exp_ff22[0:0];
	// synopsys translate_off
	initial
		zero_exp_ff24 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) zero_exp_ff24 <= 1'b0;
		else if  (clk_en == 1'b1)   zero_exp_ff24 <= zero_exp_ff23[0:0];
	lpm_add_sub   add_sub1
	( 
	.cout(),
	.dataa({1'b0, exp_in_ff}),
	.datab({1'b0, bias}),
	.overflow(),
	.result(wire_add_sub1_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub1.lpm_direction = "ADD",
		add_sub1.lpm_pipeline = 0,
		add_sub1.lpm_width = 9,
		add_sub1.lpm_type = "lpm_add_sub";
	lpm_add_sub   add_sub3
	( 
	.cout(),
	.dataa(man_root_result_w[23:1]),
	.datab({{22{1'b0}}, roundbit_w}),
	.overflow(),
	.result(wire_add_sub3_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aclr(1'b0),
	.add_sub(1'b1),
	.cin(),
	.clken(1'b1),
	.clock(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub3.lpm_direction = "ADD",
		add_sub3.lpm_pipeline = 0,
		add_sub3.lpm_width = 23,
		add_sub3.lpm_type = "lpm_add_sub";
	assign
		aclr = 1'b0,
		bias = {1'b0, {7{1'b1}}},
		exp_all_one_w = {(exp_in_ff[7] & exp_all_one_w[6]), (exp_in_ff[6] & exp_all_one_w[5]), (exp_in_ff[5] & exp_all_one_w[4]), (exp_in_ff[4] & exp_all_one_w[3]), (exp_in_ff[3] & exp_all_one_w[2]), (exp_in_ff[2] & exp_all_one_w[1]), (exp_in_ff[1] & exp_all_one_w[0]), exp_in_ff[0]},
		exp_div_w = {wire_add_sub1_result[8:1]},
		exp_ff2_w = exp_ff224c,
		exp_not_zero_w = {(exp_in_ff[7] | exp_not_zero_w[6]), (exp_in_ff[6] | exp_not_zero_w[5]), (exp_in_ff[5] | exp_not_zero_w[4]), (exp_in_ff[4] | exp_not_zero_w[3]), (exp_in_ff[3] | exp_not_zero_w[2]), (exp_in_ff[2] | exp_not_zero_w[1]), (exp_in_ff[1] | exp_not_zero_w[0]), exp_in_ff[0]},
		infinitycondition_w = ((~ man_not_zero_ff) & exp_all_one_ff),
		man_not_zero_w = {(man_in_ff[22] | man_not_zero_w[21]), (man_in_ff[21] | man_not_zero_w[20]), (man_in_ff[20] | man_not_zero_w[19]), (man_in_ff[19] | man_not_zero_w[18]), (man_in_ff[18] | man_not_zero_w[17]), (man_in_ff[17] | man_not_zero_w[16]), (man_in_ff[16] | man_not_zero_w[15]), (man_in_ff[15] | man_not_zero_w[14]), (man_in_ff[14] | man_not_zero_w[13]), (man_in_ff[13] | man_not_zero_w[12]), (man_in_ff[12] | man_not_zero_w[11]), (man_in_ff[11] | man_not_zero_w[10]), (man_in_ff[10] | man_not_zero_w[9]), (man_in_ff[9] | man_not_zero_w[8]), (man_in_ff[8] | man_not_zero_w[7]), (man_in_ff[7] | man_not_zero_w[6]), (man_in_ff[6] | man_not_zero_w[5]), (man_in_ff[5] | man_not_zero_w[4]), (man_in_ff[4] | man_not_zero_w[3]), (man_in_ff[3] | man_not_zero_w[2]), (man_in_ff[2] | man_not_zero_w[1]), (man_in_ff[1] | man_not_zero_w[0]), man_in_ff[0]},
		man_root_result_w = wire_alt_sqrt_block2_root_result,
		nancondition_w = ((sign_node_ff1[0:0] & exp_not_zero_ff) | (exp_all_one_ff & man_not_zero_ff)),
		preadjust_w = exp_in_ff[0],
		radicand_w = {(~ preadjust_w), (preadjust_w | (man_in_ff[22] & (~ preadjust_w))), ((man_in_ff[22:1] & {22{preadjust_w}}) | (man_in_ff[21:0] & {22{(~ preadjust_w)}})), (man_in_ff[0] & preadjust_w), 1'b0},
		result = {sign_node_ff27[0:0], exp_result_ff, man_result_ff},
		roundbit_w = wire_alt_sqrt_block2_root_result[0];
endmodule //acl_fp_sqrt_altfp_sqrt_rbd
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sqrt (
	enable,
	clock,
	dataa,
	result);

	input	  enable;
	input	  clock;
	input	[31:0]  dataa;
	output	[31:0]  result;

	wire [31:0] sub_wire0;
	wire [31:0] result = sub_wire0[31:0];

	acl_fp_sqrt_altfp_sqrt_rbd	acl_fp_sqrt_altfp_sqrt_rbd_component (
				.clk_en (enable),
				.clock (clock),
				.data (dataa),
				.result (sub_wire0));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "28"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
