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//-----------------------------------------------------------------------------
//
// Project    : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File       : pcie3_7x_0_pcie_bram_7vx_req.v
// Version    : 3.0
//----------------------------------------------------------------------------//
// Project      : Virtex-7 FPGA Gen3 Integrated Block for PCI Express         //
// Filename     : pcie3_7x_0_pcie_bram_7vx_req.v                                         //
// Description  : Instantiates the request buffer primitives; 8KB Dual Port   //
//                Request FIFO                                                //
//                                                                            //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_req.v                                                        //
//     pcie_bram_7vx_8k.v                                                     //
//----------------------------------------------------------------------------//

`timescale 1ps/1ps

module pcie3_7x_0_pcie_bram_7vx_req #(

  parameter IMPL_TARGET = "HARD",         // the implementation target, HARD or SOFT
  parameter NO_DECODE_LOGIC = "TRUE",     // No decode logic, TRUE or FALSE
  parameter INTERFACE_SPEED = "500 MHZ",  // the memory interface speed, 500 MHz or 250 MHz.
  parameter COMPLETION_SPACE = "16 KB"    // the completion FIFO spec, 8KB or 16KB

) (
  input               clk_i,     // user clock
  input               reset_i,   // bram reset

  input    [8:0]      waddr0_i,   // write address
  input    [8:0]      waddr1_i,   // write address
  input  [127:0]      wdata_i,   // write data
  input   [15:0]      wdip_i,    // write parity
  input               wen0_i,    // write enable
  input               wen1_i,    // write enable
  input               wen2_i,    // write enable
  input               wen3_i,    // write enable

  input    [8:0]      raddr0_i,   // write address
  input    [8:0]      raddr1_i,   // write address
  output [127:0]      rdata_o,   // read data
  output  [15:0]      rdop_o,    // read parity
  input               ren0_i,    // read enable
  input               ren1_i,    // read enable
  input               ren2_i,    // read enable
  input               ren3_i    // read enable

);


  pcie3_7x_0_pcie_bram_7vx_8k # (

    .IMPL_TARGET(IMPL_TARGET),
    .NO_DECODE_LOGIC(NO_DECODE_LOGIC),
    .INTERFACE_SPEED(INTERFACE_SPEED),
    .COMPLETION_SPACE(COMPLETION_SPACE)


  )
  U0
  (
    .clk_i              (clk_i),
    .reset_i            (reset_i),

    .waddr0_i           (waddr0_i[8:0]),
    .waddr1_i           (waddr1_i[8:0]),
    .wdata_i            (wdata_i[127:0]),
    .wdip_i             (wdip_i[15:0]),
    .wen_i              ({wen3_i, wen2_i, wen1_i, wen0_i}),

    .raddr0_i           (raddr0_i[8:0]),
    .raddr1_i           (raddr1_i[8:0]),
    .rdata_o            (rdata_o[127:0]),
    .rdop_o             (rdop_o[15:0]),
    .ren_i              ({ren3_i, ren2_i, ren1_i, ren0_i})

  );

endmodule // pcie_bram_7vx_req
