// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date        : Thu Oct 26 22:46:25 2017
// Host        : Juice-Laptop running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_alu_0_0/RAT_alu_0_0_stub.v
// Design      : RAT_alu_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "alu,Vivado 2016.4" *)
module RAT_alu_0_0(A, B, C_IN, Sel, SUM, C_FLAG, Z_FLAG)
/* synthesis syn_black_box black_box_pad_pin="A[7:0],B[7:0],C_IN,Sel[3:0],SUM[7:0],C_FLAG,Z_FLAG" */;
  input [7:0]A;
  input [7:0]B;
  input C_IN;
  input [3:0]Sel;
  output [7:0]SUM;
  output C_FLAG;
  output Z_FLAG;
endmodule
