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// IP VLNV: dtysky:user:CONTROL_UNIT:1.0
// IP Revision: 3

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module MIPS_CPU_CONTROL_UNIT_0_1 (
  op,
  func,
  z,
  wreg,
  regrt,
  jal,
  m2reg,
  shfit,
  aluimm,
  sext,
  wmem,
  aluc,
  pcsource
);

input wire [5 : 0] op;
input wire [5 : 0] func;
input wire z;
output wire wreg;
output wire regrt;
output wire jal;
output wire m2reg;
output wire shfit;
output wire aluimm;
output wire sext;
output wire wmem;
output wire [3 : 0] aluc;
output wire [1 : 0] pcsource;

  CONTROL_UNIT #(
    .cmd_add(6'B100000),
    .cmd_sub(6'B100010),
    .cmd_and(6'B100100),
    .cmd_or(6'B100101),
    .cmd_xor(6'B100110),
    .cmd_sll(6'B000000),
    .cmd_srl(6'B000010),
    .cmd_sra(6'B000011),
    .cmd_jr(6'B001000),
    .cmd_addi(6'B001000),
    .cmd_andi(6'B001100),
    .cmd_ori(6'B001101),
    .cmd_xori(6'B001110),
    .cmd_lw(6'B100011),
    .cmd_sw(6'B101011),
    .cmd_beq(6'B000100),
    .cmd_bne(6'B000101),
    .cmd_lui(6'B001111),
    .cmd_j(6'B000010),
    .cmd_jal(6'B000011)
  ) inst (
    .op(op),
    .func(func),
    .z(z),
    .wreg(wreg),
    .regrt(regrt),
    .jal(jal),
    .m2reg(m2reg),
    .shfit(shfit),
    .aluimm(aluimm),
    .sext(sext),
    .wmem(wmem),
    .aluc(aluc),
    .pcsource(pcsource)
  );
endmodule
