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// Agreement, Altera MegaCore Function License Agreement, or other applicable     
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module acl_fp_custom_mul_ll(
    // this interface matches what hdlgen expects
	input logic clock, 
    input logic resetn,
    input logic enable,
	input logic [31:0] dataa,
	input logic [31:0] datab,
	output logic [31:0] result
);
    acl_fp_custom_mul_ll_hc_core #(
        .HIGH_CAPACITY(0)
    )
    core(
        .clock(clock),
        .resetn(resetn),
        .enable(enable),
        .dataa(dataa),
        .datab(datab),
        .result(result)
    );
endmodule

