// soc_system_mm_interconnect_3.v

// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 13.1 162 at 2014.12.19.15:55:02

`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_3 (
		input  wire [11:0] hps_0_h2f_lw_axi_master_awid,                                        //                                       hps_0_h2f_lw_axi_master.awid
		input  wire [20:0] hps_0_h2f_lw_axi_master_awaddr,                                      //                                                              .awaddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awlen,                                       //                                                              .awlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awsize,                                      //                                                              .awsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awburst,                                     //                                                              .awburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_awlock,                                      //                                                              .awlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_awcache,                                     //                                                              .awcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_awprot,                                      //                                                              .awprot
		input  wire        hps_0_h2f_lw_axi_master_awvalid,                                     //                                                              .awvalid
		output wire        hps_0_h2f_lw_axi_master_awready,                                     //                                                              .awready
		input  wire [11:0] hps_0_h2f_lw_axi_master_wid,                                         //                                                              .wid
		input  wire [31:0] hps_0_h2f_lw_axi_master_wdata,                                       //                                                              .wdata
		input  wire [3:0]  hps_0_h2f_lw_axi_master_wstrb,                                       //                                                              .wstrb
		input  wire        hps_0_h2f_lw_axi_master_wlast,                                       //                                                              .wlast
		input  wire        hps_0_h2f_lw_axi_master_wvalid,                                      //                                                              .wvalid
		output wire        hps_0_h2f_lw_axi_master_wready,                                      //                                                              .wready
		output wire [11:0] hps_0_h2f_lw_axi_master_bid,                                         //                                                              .bid
		output wire [1:0]  hps_0_h2f_lw_axi_master_bresp,                                       //                                                              .bresp
		output wire        hps_0_h2f_lw_axi_master_bvalid,                                      //                                                              .bvalid
		input  wire        hps_0_h2f_lw_axi_master_bready,                                      //                                                              .bready
		input  wire [11:0] hps_0_h2f_lw_axi_master_arid,                                        //                                                              .arid
		input  wire [20:0] hps_0_h2f_lw_axi_master_araddr,                                      //                                                              .araddr
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arlen,                                       //                                                              .arlen
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arsize,                                      //                                                              .arsize
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arburst,                                     //                                                              .arburst
		input  wire [1:0]  hps_0_h2f_lw_axi_master_arlock,                                      //                                                              .arlock
		input  wire [3:0]  hps_0_h2f_lw_axi_master_arcache,                                     //                                                              .arcache
		input  wire [2:0]  hps_0_h2f_lw_axi_master_arprot,                                      //                                                              .arprot
		input  wire        hps_0_h2f_lw_axi_master_arvalid,                                     //                                                              .arvalid
		output wire        hps_0_h2f_lw_axi_master_arready,                                     //                                                              .arready
		output wire [11:0] hps_0_h2f_lw_axi_master_rid,                                         //                                                              .rid
		output wire [31:0] hps_0_h2f_lw_axi_master_rdata,                                       //                                                              .rdata
		output wire [1:0]  hps_0_h2f_lw_axi_master_rresp,                                       //                                                              .rresp
		output wire        hps_0_h2f_lw_axi_master_rlast,                                       //                                                              .rlast
		output wire        hps_0_h2f_lw_axi_master_rvalid,                                      //                                                              .rvalid
		input  wire        hps_0_h2f_lw_axi_master_rready,                                      //                                                              .rready
		input  wire        clk_0_clk_clk,                                                       //                                                     clk_0_clk.clk
		input  wire        system_pll_outclk0_clk,                                              //                                            system_pll_outclk0.clk
		input  wire        fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset,      //      fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset.reset
		input  wire        hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
		output wire [7:0]  fifo_bridge_cpuM_cpus0_s1_address,                                   //                                     fifo_bridge_cpuM_cpus0_s1.address
		output wire        fifo_bridge_cpuM_cpus0_s1_write,                                     //                                                              .write
		output wire        fifo_bridge_cpuM_cpus0_s1_read,                                      //                                                              .read
		input  wire [31:0] fifo_bridge_cpuM_cpus0_s1_readdata,                                  //                                                              .readdata
		output wire [31:0] fifo_bridge_cpuM_cpus0_s1_writedata,                                 //                                                              .writedata
		output wire [7:0]  fifo_bridge_cpuM_cpus1_s1_address,                                   //                                     fifo_bridge_cpuM_cpus1_s1.address
		output wire        fifo_bridge_cpuM_cpus1_s1_write,                                     //                                                              .write
		output wire        fifo_bridge_cpuM_cpus1_s1_read,                                      //                                                              .read
		input  wire [31:0] fifo_bridge_cpuM_cpus1_s1_readdata,                                  //                                                              .readdata
		output wire [31:0] fifo_bridge_cpuM_cpus1_s1_writedata                                  //                                                              .writedata
	);

	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // fifo_bridge_cpuM_cpus0_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;              // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus0_s1_translator:uav_burstcount
	wire   [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata;               // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus0_s1_translator:uav_writedata
	wire   [20:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address;                 // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus0_s1_translator:uav_address
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write;                   // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus0_s1_translator:uav_write
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock;                    // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus0_s1_translator:uav_lock
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read;                    // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus0_s1_translator:uav_read
	wire   [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus0_s1_translator:uav_debugaccess
	wire    [3:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;              // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus0_s1_translator:uav_byteenable
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;            // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data;             // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;            // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;       // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;        // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;       // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // fifo_bridge_cpuM_cpus1_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [2:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;              // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus1_s1_translator:uav_burstcount
	wire   [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata;               // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus1_s1_translator:uav_writedata
	wire   [20:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address;                 // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus1_s1_translator:uav_address
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write;                   // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus1_s1_translator:uav_write
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock;                    // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus1_s1_translator:uav_lock
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read;                    // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus1_s1_translator:uav_read
	wire   [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus1_s1_translator:uav_debugaccess
	wire    [3:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;              // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus1_s1_translator:uav_byteenable
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;            // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data;             // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;            // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire   [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;       // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire   [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;        // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;       // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket;                                             // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_valid;                                                   // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket;                                           // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
	wire  [111:0] hps_0_h2f_lw_axi_master_agent_write_cp_data;                                                    // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_write_cp_ready;                                                   // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket;                                              // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_valid;                                                    // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket;                                            // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [111:0] hps_0_h2f_lw_axi_master_agent_read_cp_data;                                                     // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
	wire          hps_0_h2f_lw_axi_master_agent_read_cp_ready;                                                    // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid;                   // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [111:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data;                    // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire          fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router:sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_src_endofpacket;                                                                      // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          id_router_src_valid;                                                                            // id_router:src_valid -> rsp_xbar_demux:sink_valid
	wire          id_router_src_startofpacket;                                                                    // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [111:0] id_router_src_data;                                                                             // id_router:src_data -> rsp_xbar_demux:sink_data
	wire    [1:0] id_router_src_channel;                                                                          // id_router:src_channel -> rsp_xbar_demux:sink_channel
	wire          id_router_src_ready;                                                                            // rsp_xbar_demux:sink_ready -> id_router:src_ready
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid;                   // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
	wire  [111:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data;                    // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
	wire          fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_001:sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire          id_router_001_src_endofpacket;                                                                  // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire          id_router_001_src_valid;                                                                        // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
	wire          id_router_001_src_startofpacket;                                                                // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [111:0] id_router_001_src_data;                                                                         // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
	wire    [1:0] id_router_001_src_channel;                                                                      // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
	wire          id_router_001_src_ready;                                                                        // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
	wire          addr_router_src_endofpacket;                                                                    // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
	wire          addr_router_src_valid;                                                                          // addr_router:src_valid -> limiter:cmd_sink_valid
	wire          addr_router_src_startofpacket;                                                                  // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
	wire  [111:0] addr_router_src_data;                                                                           // addr_router:src_data -> limiter:cmd_sink_data
	wire    [1:0] addr_router_src_channel;                                                                        // addr_router:src_channel -> limiter:cmd_sink_channel
	wire          addr_router_src_ready;                                                                          // limiter:cmd_sink_ready -> addr_router:src_ready
	wire          limiter_cmd_src_endofpacket;                                                                    // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          limiter_cmd_src_startofpacket;                                                                  // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [111:0] limiter_cmd_src_data;                                                                           // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
	wire    [1:0] limiter_cmd_src_channel;                                                                        // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
	wire          limiter_cmd_src_ready;                                                                          // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
	wire          rsp_xbar_mux_src_endofpacket;                                                                   // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
	wire          rsp_xbar_mux_src_valid;                                                                         // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
	wire          rsp_xbar_mux_src_startofpacket;                                                                 // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
	wire  [111:0] rsp_xbar_mux_src_data;                                                                          // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
	wire    [1:0] rsp_xbar_mux_src_channel;                                                                       // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
	wire          rsp_xbar_mux_src_ready;                                                                         // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
	wire          limiter_rsp_src_endofpacket;                                                                    // limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
	wire          limiter_rsp_src_valid;                                                                          // limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
	wire          limiter_rsp_src_startofpacket;                                                                  // limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
	wire  [111:0] limiter_rsp_src_data;                                                                           // limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
	wire    [1:0] limiter_rsp_src_channel;                                                                        // limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
	wire          limiter_rsp_src_ready;                                                                          // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> limiter:rsp_src_ready
	wire          addr_router_001_src_endofpacket;                                                                // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
	wire          addr_router_001_src_valid;                                                                      // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
	wire          addr_router_001_src_startofpacket;                                                              // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
	wire  [111:0] addr_router_001_src_data;                                                                       // addr_router_001:src_data -> limiter_001:cmd_sink_data
	wire    [1:0] addr_router_001_src_channel;                                                                    // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
	wire          addr_router_001_src_ready;                                                                      // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
	wire          limiter_001_cmd_src_endofpacket;                                                                // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          limiter_001_cmd_src_startofpacket;                                                              // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [111:0] limiter_001_cmd_src_data;                                                                       // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
	wire    [1:0] limiter_001_cmd_src_channel;                                                                    // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
	wire          limiter_001_cmd_src_ready;                                                                      // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
	wire          rsp_xbar_mux_001_src_endofpacket;                                                               // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
	wire          rsp_xbar_mux_001_src_valid;                                                                     // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
	wire          rsp_xbar_mux_001_src_startofpacket;                                                             // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
	wire  [111:0] rsp_xbar_mux_001_src_data;                                                                      // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
	wire    [1:0] rsp_xbar_mux_001_src_channel;                                                                   // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
	wire          rsp_xbar_mux_001_src_ready;                                                                     // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
	wire          limiter_001_rsp_src_endofpacket;                                                                // limiter_001:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
	wire          limiter_001_rsp_src_valid;                                                                      // limiter_001:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
	wire          limiter_001_rsp_src_startofpacket;                                                              // limiter_001:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
	wire  [111:0] limiter_001_rsp_src_data;                                                                       // limiter_001:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
	wire    [1:0] limiter_001_rsp_src_channel;                                                                    // limiter_001:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
	wire          limiter_001_rsp_src_ready;                                                                      // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> limiter_001:rsp_src_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                                   // cmd_xbar_mux:src_endofpacket -> burst_adapter:sink0_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                         // cmd_xbar_mux:src_valid -> burst_adapter:sink0_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                                 // cmd_xbar_mux:src_startofpacket -> burst_adapter:sink0_startofpacket
	wire  [111:0] cmd_xbar_mux_src_data;                                                                          // cmd_xbar_mux:src_data -> burst_adapter:sink0_data
	wire    [1:0] cmd_xbar_mux_src_channel;                                                                       // cmd_xbar_mux:src_channel -> burst_adapter:sink0_channel
	wire          cmd_xbar_mux_src_ready;                                                                         // burst_adapter:sink0_ready -> cmd_xbar_mux:src_ready
	wire          burst_adapter_source0_endofpacket;                                                              // burst_adapter:source0_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          burst_adapter_source0_valid;                                                                    // burst_adapter:source0_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          burst_adapter_source0_startofpacket;                                                            // burst_adapter:source0_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [111:0] burst_adapter_source0_data;                                                                     // burst_adapter:source0_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire          burst_adapter_source0_ready;                                                                    // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
	wire    [1:0] burst_adapter_source0_channel;                                                                  // burst_adapter:source0_channel -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_mux_001_src_endofpacket;                                                               // cmd_xbar_mux_001:src_endofpacket -> burst_adapter_001:sink0_endofpacket
	wire          cmd_xbar_mux_001_src_valid;                                                                     // cmd_xbar_mux_001:src_valid -> burst_adapter_001:sink0_valid
	wire          cmd_xbar_mux_001_src_startofpacket;                                                             // cmd_xbar_mux_001:src_startofpacket -> burst_adapter_001:sink0_startofpacket
	wire  [111:0] cmd_xbar_mux_001_src_data;                                                                      // cmd_xbar_mux_001:src_data -> burst_adapter_001:sink0_data
	wire    [1:0] cmd_xbar_mux_001_src_channel;                                                                   // cmd_xbar_mux_001:src_channel -> burst_adapter_001:sink0_channel
	wire          cmd_xbar_mux_001_src_ready;                                                                     // burst_adapter_001:sink0_ready -> cmd_xbar_mux_001:src_ready
	wire          burst_adapter_001_source0_endofpacket;                                                          // burst_adapter_001:source0_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          burst_adapter_001_source0_valid;                                                                // burst_adapter_001:source0_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire          burst_adapter_001_source0_startofpacket;                                                        // burst_adapter_001:source0_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [111:0] burst_adapter_001_source0_data;                                                                 // burst_adapter_001:source0_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire          burst_adapter_001_source0_ready;                                                                // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
	wire    [1:0] burst_adapter_001_source0_channel;                                                              // burst_adapter_001:source0_channel -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire          cmd_xbar_demux_src0_endofpacket;                                                                // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                                      // cmd_xbar_demux:src0_valid -> crosser:in_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                              // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
	wire  [111:0] cmd_xbar_demux_src0_data;                                                                       // cmd_xbar_demux:src0_data -> crosser:in_data
	wire    [1:0] cmd_xbar_demux_src0_channel;                                                                    // cmd_xbar_demux:src0_channel -> crosser:in_channel
	wire          cmd_xbar_demux_src0_ready;                                                                      // crosser:in_ready -> cmd_xbar_demux:src0_ready
	wire          crosser_out_endofpacket;                                                                        // crosser:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          crosser_out_valid;                                                                              // crosser:out_valid -> cmd_xbar_mux:sink0_valid
	wire          crosser_out_startofpacket;                                                                      // crosser:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [111:0] crosser_out_data;                                                                               // crosser:out_data -> cmd_xbar_mux:sink0_data
	wire    [1:0] crosser_out_channel;                                                                            // crosser:out_channel -> cmd_xbar_mux:sink0_channel
	wire          crosser_out_ready;                                                                              // cmd_xbar_mux:sink0_ready -> crosser:out_ready
	wire          cmd_xbar_demux_src1_endofpacket;                                                                // cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
	wire          cmd_xbar_demux_src1_valid;                                                                      // cmd_xbar_demux:src1_valid -> crosser_001:in_valid
	wire          cmd_xbar_demux_src1_startofpacket;                                                              // cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
	wire  [111:0] cmd_xbar_demux_src1_data;                                                                       // cmd_xbar_demux:src1_data -> crosser_001:in_data
	wire    [1:0] cmd_xbar_demux_src1_channel;                                                                    // cmd_xbar_demux:src1_channel -> crosser_001:in_channel
	wire          cmd_xbar_demux_src1_ready;                                                                      // crosser_001:in_ready -> cmd_xbar_demux:src1_ready
	wire          crosser_001_out_endofpacket;                                                                    // crosser_001:out_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
	wire          crosser_001_out_valid;                                                                          // crosser_001:out_valid -> cmd_xbar_mux_001:sink0_valid
	wire          crosser_001_out_startofpacket;                                                                  // crosser_001:out_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
	wire  [111:0] crosser_001_out_data;                                                                           // crosser_001:out_data -> cmd_xbar_mux_001:sink0_data
	wire    [1:0] crosser_001_out_channel;                                                                        // crosser_001:out_channel -> cmd_xbar_mux_001:sink0_channel
	wire          crosser_001_out_ready;                                                                          // cmd_xbar_mux_001:sink0_ready -> crosser_001:out_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                            // cmd_xbar_demux_001:src0_endofpacket -> crosser_002:in_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                                  // cmd_xbar_demux_001:src0_valid -> crosser_002:in_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                          // cmd_xbar_demux_001:src0_startofpacket -> crosser_002:in_startofpacket
	wire  [111:0] cmd_xbar_demux_001_src0_data;                                                                   // cmd_xbar_demux_001:src0_data -> crosser_002:in_data
	wire    [1:0] cmd_xbar_demux_001_src0_channel;                                                                // cmd_xbar_demux_001:src0_channel -> crosser_002:in_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                                  // crosser_002:in_ready -> cmd_xbar_demux_001:src0_ready
	wire          crosser_002_out_endofpacket;                                                                    // crosser_002:out_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire          crosser_002_out_valid;                                                                          // crosser_002:out_valid -> cmd_xbar_mux:sink1_valid
	wire          crosser_002_out_startofpacket;                                                                  // crosser_002:out_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire  [111:0] crosser_002_out_data;                                                                           // crosser_002:out_data -> cmd_xbar_mux:sink1_data
	wire    [1:0] crosser_002_out_channel;                                                                        // crosser_002:out_channel -> cmd_xbar_mux:sink1_channel
	wire          crosser_002_out_ready;                                                                          // cmd_xbar_mux:sink1_ready -> crosser_002:out_ready
	wire          cmd_xbar_demux_001_src1_endofpacket;                                                            // cmd_xbar_demux_001:src1_endofpacket -> crosser_003:in_endofpacket
	wire          cmd_xbar_demux_001_src1_valid;                                                                  // cmd_xbar_demux_001:src1_valid -> crosser_003:in_valid
	wire          cmd_xbar_demux_001_src1_startofpacket;                                                          // cmd_xbar_demux_001:src1_startofpacket -> crosser_003:in_startofpacket
	wire  [111:0] cmd_xbar_demux_001_src1_data;                                                                   // cmd_xbar_demux_001:src1_data -> crosser_003:in_data
	wire    [1:0] cmd_xbar_demux_001_src1_channel;                                                                // cmd_xbar_demux_001:src1_channel -> crosser_003:in_channel
	wire          cmd_xbar_demux_001_src1_ready;                                                                  // crosser_003:in_ready -> cmd_xbar_demux_001:src1_ready
	wire          crosser_003_out_endofpacket;                                                                    // crosser_003:out_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
	wire          crosser_003_out_valid;                                                                          // crosser_003:out_valid -> cmd_xbar_mux_001:sink1_valid
	wire          crosser_003_out_startofpacket;                                                                  // crosser_003:out_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
	wire  [111:0] crosser_003_out_data;                                                                           // crosser_003:out_data -> cmd_xbar_mux_001:sink1_data
	wire    [1:0] crosser_003_out_channel;                                                                        // crosser_003:out_channel -> cmd_xbar_mux_001:sink1_channel
	wire          crosser_003_out_ready;                                                                          // cmd_xbar_mux_001:sink1_ready -> crosser_003:out_ready
	wire          rsp_xbar_demux_src0_endofpacket;                                                                // rsp_xbar_demux:src0_endofpacket -> crosser_004:in_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                                      // rsp_xbar_demux:src0_valid -> crosser_004:in_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                              // rsp_xbar_demux:src0_startofpacket -> crosser_004:in_startofpacket
	wire  [111:0] rsp_xbar_demux_src0_data;                                                                       // rsp_xbar_demux:src0_data -> crosser_004:in_data
	wire    [1:0] rsp_xbar_demux_src0_channel;                                                                    // rsp_xbar_demux:src0_channel -> crosser_004:in_channel
	wire          rsp_xbar_demux_src0_ready;                                                                      // crosser_004:in_ready -> rsp_xbar_demux:src0_ready
	wire          crosser_004_out_endofpacket;                                                                    // crosser_004:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire          crosser_004_out_valid;                                                                          // crosser_004:out_valid -> rsp_xbar_mux:sink0_valid
	wire          crosser_004_out_startofpacket;                                                                  // crosser_004:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [111:0] crosser_004_out_data;                                                                           // crosser_004:out_data -> rsp_xbar_mux:sink0_data
	wire    [1:0] crosser_004_out_channel;                                                                        // crosser_004:out_channel -> rsp_xbar_mux:sink0_channel
	wire          crosser_004_out_ready;                                                                          // rsp_xbar_mux:sink0_ready -> crosser_004:out_ready
	wire          rsp_xbar_demux_src1_endofpacket;                                                                // rsp_xbar_demux:src1_endofpacket -> crosser_005:in_endofpacket
	wire          rsp_xbar_demux_src1_valid;                                                                      // rsp_xbar_demux:src1_valid -> crosser_005:in_valid
	wire          rsp_xbar_demux_src1_startofpacket;                                                              // rsp_xbar_demux:src1_startofpacket -> crosser_005:in_startofpacket
	wire  [111:0] rsp_xbar_demux_src1_data;                                                                       // rsp_xbar_demux:src1_data -> crosser_005:in_data
	wire    [1:0] rsp_xbar_demux_src1_channel;                                                                    // rsp_xbar_demux:src1_channel -> crosser_005:in_channel
	wire          rsp_xbar_demux_src1_ready;                                                                      // crosser_005:in_ready -> rsp_xbar_demux:src1_ready
	wire          crosser_005_out_endofpacket;                                                                    // crosser_005:out_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
	wire          crosser_005_out_valid;                                                                          // crosser_005:out_valid -> rsp_xbar_mux_001:sink0_valid
	wire          crosser_005_out_startofpacket;                                                                  // crosser_005:out_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
	wire  [111:0] crosser_005_out_data;                                                                           // crosser_005:out_data -> rsp_xbar_mux_001:sink0_data
	wire    [1:0] crosser_005_out_channel;                                                                        // crosser_005:out_channel -> rsp_xbar_mux_001:sink0_channel
	wire          crosser_005_out_ready;                                                                          // rsp_xbar_mux_001:sink0_ready -> crosser_005:out_ready
	wire          rsp_xbar_demux_001_src0_endofpacket;                                                            // rsp_xbar_demux_001:src0_endofpacket -> crosser_006:in_endofpacket
	wire          rsp_xbar_demux_001_src0_valid;                                                                  // rsp_xbar_demux_001:src0_valid -> crosser_006:in_valid
	wire          rsp_xbar_demux_001_src0_startofpacket;                                                          // rsp_xbar_demux_001:src0_startofpacket -> crosser_006:in_startofpacket
	wire  [111:0] rsp_xbar_demux_001_src0_data;                                                                   // rsp_xbar_demux_001:src0_data -> crosser_006:in_data
	wire    [1:0] rsp_xbar_demux_001_src0_channel;                                                                // rsp_xbar_demux_001:src0_channel -> crosser_006:in_channel
	wire          rsp_xbar_demux_001_src0_ready;                                                                  // crosser_006:in_ready -> rsp_xbar_demux_001:src0_ready
	wire          crosser_006_out_endofpacket;                                                                    // crosser_006:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire          crosser_006_out_valid;                                                                          // crosser_006:out_valid -> rsp_xbar_mux:sink1_valid
	wire          crosser_006_out_startofpacket;                                                                  // crosser_006:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [111:0] crosser_006_out_data;                                                                           // crosser_006:out_data -> rsp_xbar_mux:sink1_data
	wire    [1:0] crosser_006_out_channel;                                                                        // crosser_006:out_channel -> rsp_xbar_mux:sink1_channel
	wire          crosser_006_out_ready;                                                                          // rsp_xbar_mux:sink1_ready -> crosser_006:out_ready
	wire          rsp_xbar_demux_001_src1_endofpacket;                                                            // rsp_xbar_demux_001:src1_endofpacket -> crosser_007:in_endofpacket
	wire          rsp_xbar_demux_001_src1_valid;                                                                  // rsp_xbar_demux_001:src1_valid -> crosser_007:in_valid
	wire          rsp_xbar_demux_001_src1_startofpacket;                                                          // rsp_xbar_demux_001:src1_startofpacket -> crosser_007:in_startofpacket
	wire  [111:0] rsp_xbar_demux_001_src1_data;                                                                   // rsp_xbar_demux_001:src1_data -> crosser_007:in_data
	wire    [1:0] rsp_xbar_demux_001_src1_channel;                                                                // rsp_xbar_demux_001:src1_channel -> crosser_007:in_channel
	wire          rsp_xbar_demux_001_src1_ready;                                                                  // crosser_007:in_ready -> rsp_xbar_demux_001:src1_ready
	wire          crosser_007_out_endofpacket;                                                                    // crosser_007:out_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
	wire          crosser_007_out_valid;                                                                          // crosser_007:out_valid -> rsp_xbar_mux_001:sink1_valid
	wire          crosser_007_out_startofpacket;                                                                  // crosser_007:out_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
	wire  [111:0] crosser_007_out_data;                                                                           // crosser_007:out_data -> rsp_xbar_mux_001:sink1_data
	wire    [1:0] crosser_007_out_channel;                                                                        // crosser_007:out_channel -> rsp_xbar_mux_001:sink1_channel
	wire          crosser_007_out_ready;                                                                          // rsp_xbar_mux_001:sink1_ready -> crosser_007:out_ready
	wire    [1:0] limiter_cmd_valid_data;                                                                         // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
	wire    [1:0] limiter_001_cmd_valid_data;                                                                     // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (21),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_bridge_cpum_cpus0_s1_translator (
		.clk                      (system_pll_outclk0_clk),                                                               //                      clk.clk
		.reset                    (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                       //                    reset.reset
		.uav_address              (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (fifo_bridge_cpuM_cpus0_s1_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (fifo_bridge_cpuM_cpus0_s1_write),                                                      //                         .write
		.av_read                  (fifo_bridge_cpuM_cpus0_s1_read),                                                       //                         .read
		.av_readdata              (fifo_bridge_cpuM_cpus0_s1_readdata),                                                   //                         .readdata
		.av_writedata             (fifo_bridge_cpuM_cpus0_s1_writedata),                                                  //                         .writedata
		.av_begintransfer         (),                                                                                     //              (terminated)
		.av_beginbursttransfer    (),                                                                                     //              (terminated)
		.av_burstcount            (),                                                                                     //              (terminated)
		.av_byteenable            (),                                                                                     //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                 //              (terminated)
		.av_waitrequest           (1'b0),                                                                                 //              (terminated)
		.av_writebyteenable       (),                                                                                     //              (terminated)
		.av_lock                  (),                                                                                     //              (terminated)
		.av_chipselect            (),                                                                                     //              (terminated)
		.av_clken                 (),                                                                                     //              (terminated)
		.uav_clken                (1'b0),                                                                                 //              (terminated)
		.av_debugaccess           (),                                                                                     //              (terminated)
		.av_outputenable          (),                                                                                     //              (terminated)
		.uav_response             (),                                                                                     //              (terminated)
		.av_response              (2'b00),                                                                                //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                 //              (terminated)
		.uav_writeresponsevalid   (),                                                                                     //              (terminated)
		.av_writeresponserequest  (),                                                                                     //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                  //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (21),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) fifo_bridge_cpum_cpus1_s1_translator (
		.clk                      (system_pll_outclk0_clk),                                                               //                      clk.clk
		.reset                    (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                       //                    reset.reset
		.uav_address              (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read                 (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write                (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid        (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata             (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata            (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock                 (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address               (fifo_bridge_cpuM_cpus1_s1_address),                                                    //      avalon_anti_slave_0.address
		.av_write                 (fifo_bridge_cpuM_cpus1_s1_write),                                                      //                         .write
		.av_read                  (fifo_bridge_cpuM_cpus1_s1_read),                                                       //                         .read
		.av_readdata              (fifo_bridge_cpuM_cpus1_s1_readdata),                                                   //                         .readdata
		.av_writedata             (fifo_bridge_cpuM_cpus1_s1_writedata),                                                  //                         .writedata
		.av_begintransfer         (),                                                                                     //              (terminated)
		.av_beginbursttransfer    (),                                                                                     //              (terminated)
		.av_burstcount            (),                                                                                     //              (terminated)
		.av_byteenable            (),                                                                                     //              (terminated)
		.av_readdatavalid         (1'b0),                                                                                 //              (terminated)
		.av_waitrequest           (1'b0),                                                                                 //              (terminated)
		.av_writebyteenable       (),                                                                                     //              (terminated)
		.av_lock                  (),                                                                                     //              (terminated)
		.av_chipselect            (),                                                                                     //              (terminated)
		.av_clken                 (),                                                                                     //              (terminated)
		.uav_clken                (1'b0),                                                                                 //              (terminated)
		.av_debugaccess           (),                                                                                     //              (terminated)
		.av_outputenable          (),                                                                                     //              (terminated)
		.uav_response             (),                                                                                     //              (terminated)
		.av_response              (2'b00),                                                                                //              (terminated)
		.uav_writeresponserequest (1'b0),                                                                                 //              (terminated)
		.uav_writeresponsevalid   (),                                                                                     //              (terminated)
		.av_writeresponserequest  (),                                                                                     //              (terminated)
		.av_writeresponsevalid    (1'b0)                                                                                  //              (terminated)
	);

	altera_merlin_axi_master_ni #(
		.ID_WIDTH                  (12),
		.ADDR_WIDTH                (21),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (4),
		.AXI_LOCK_WIDTH            (2),
		.AXI_VERSION               ("AXI3"),
		.WRITE_ISSUING_CAPABILITY  (8),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (84),
		.PKT_CACHE_H               (106),
		.PKT_CACHE_L               (103),
		.PKT_ADDR_SIDEBAND_H       (82),
		.PKT_ADDR_SIDEBAND_L       (82),
		.PKT_PROTECTION_H          (102),
		.PKT_PROTECTION_L          (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_RESPONSE_STATUS_L     (107),
		.PKT_RESPONSE_STATUS_H     (108),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (62),
		.PKT_TRANS_LOCK            (61),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_THREAD_ID_H           (99),
		.PKT_THREAD_ID_L           (88),
		.PKT_QOS_L                 (85),
		.PKT_QOS_H                 (85),
		.PKT_ORI_BURST_SIZE_L      (109),
		.PKT_ORI_BURST_SIZE_H      (111),
		.PKT_DATA_SIDEBAND_H       (83),
		.PKT_DATA_SIDEBAND_L       (83),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.ID                        (0)
	) hps_0_h2f_lw_axi_master_agent (
		.aclk                   (clk_0_clk_clk),                                                        //              clk.clk
		.aresetn                (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //        clk_reset.reset_n
		.write_cp_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                         //         write_cp.valid
		.write_cp_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                          //                 .data
		.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                 //                 .startofpacket
		.write_cp_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                   //                 .endofpacket
		.write_cp_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                         //                 .ready
		.write_rp_valid         (limiter_rsp_src_valid),                                                //         write_rp.valid
		.write_rp_data          (limiter_rsp_src_data),                                                 //                 .data
		.write_rp_channel       (limiter_rsp_src_channel),                                              //                 .channel
		.write_rp_startofpacket (limiter_rsp_src_startofpacket),                                        //                 .startofpacket
		.write_rp_endofpacket   (limiter_rsp_src_endofpacket),                                          //                 .endofpacket
		.write_rp_ready         (limiter_rsp_src_ready),                                                //                 .ready
		.read_cp_valid          (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                          //          read_cp.valid
		.read_cp_data           (hps_0_h2f_lw_axi_master_agent_read_cp_data),                           //                 .data
		.read_cp_startofpacket  (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                  //                 .startofpacket
		.read_cp_endofpacket    (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                    //                 .endofpacket
		.read_cp_ready          (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                          //                 .ready
		.read_rp_valid          (limiter_001_rsp_src_valid),                                            //          read_rp.valid
		.read_rp_data           (limiter_001_rsp_src_data),                                             //                 .data
		.read_rp_channel        (limiter_001_rsp_src_channel),                                          //                 .channel
		.read_rp_startofpacket  (limiter_001_rsp_src_startofpacket),                                    //                 .startofpacket
		.read_rp_endofpacket    (limiter_001_rsp_src_endofpacket),                                      //                 .endofpacket
		.read_rp_ready          (limiter_001_rsp_src_ready),                                            //                 .ready
		.awid                   (hps_0_h2f_lw_axi_master_awid),                                         // altera_axi_slave.awid
		.awaddr                 (hps_0_h2f_lw_axi_master_awaddr),                                       //                 .awaddr
		.awlen                  (hps_0_h2f_lw_axi_master_awlen),                                        //                 .awlen
		.awsize                 (hps_0_h2f_lw_axi_master_awsize),                                       //                 .awsize
		.awburst                (hps_0_h2f_lw_axi_master_awburst),                                      //                 .awburst
		.awlock                 (hps_0_h2f_lw_axi_master_awlock),                                       //                 .awlock
		.awcache                (hps_0_h2f_lw_axi_master_awcache),                                      //                 .awcache
		.awprot                 (hps_0_h2f_lw_axi_master_awprot),                                       //                 .awprot
		.awvalid                (hps_0_h2f_lw_axi_master_awvalid),                                      //                 .awvalid
		.awready                (hps_0_h2f_lw_axi_master_awready),                                      //                 .awready
		.wid                    (hps_0_h2f_lw_axi_master_wid),                                          //                 .wid
		.wdata                  (hps_0_h2f_lw_axi_master_wdata),                                        //                 .wdata
		.wstrb                  (hps_0_h2f_lw_axi_master_wstrb),                                        //                 .wstrb
		.wlast                  (hps_0_h2f_lw_axi_master_wlast),                                        //                 .wlast
		.wvalid                 (hps_0_h2f_lw_axi_master_wvalid),                                       //                 .wvalid
		.wready                 (hps_0_h2f_lw_axi_master_wready),                                       //                 .wready
		.bid                    (hps_0_h2f_lw_axi_master_bid),                                          //                 .bid
		.bresp                  (hps_0_h2f_lw_axi_master_bresp),                                        //                 .bresp
		.bvalid                 (hps_0_h2f_lw_axi_master_bvalid),                                       //                 .bvalid
		.bready                 (hps_0_h2f_lw_axi_master_bready),                                       //                 .bready
		.arid                   (hps_0_h2f_lw_axi_master_arid),                                         //                 .arid
		.araddr                 (hps_0_h2f_lw_axi_master_araddr),                                       //                 .araddr
		.arlen                  (hps_0_h2f_lw_axi_master_arlen),                                        //                 .arlen
		.arsize                 (hps_0_h2f_lw_axi_master_arsize),                                       //                 .arsize
		.arburst                (hps_0_h2f_lw_axi_master_arburst),                                      //                 .arburst
		.arlock                 (hps_0_h2f_lw_axi_master_arlock),                                       //                 .arlock
		.arcache                (hps_0_h2f_lw_axi_master_arcache),                                      //                 .arcache
		.arprot                 (hps_0_h2f_lw_axi_master_arprot),                                       //                 .arprot
		.arvalid                (hps_0_h2f_lw_axi_master_arvalid),                                      //                 .arvalid
		.arready                (hps_0_h2f_lw_axi_master_arready),                                      //                 .arready
		.rid                    (hps_0_h2f_lw_axi_master_rid),                                          //                 .rid
		.rdata                  (hps_0_h2f_lw_axi_master_rdata),                                        //                 .rdata
		.rresp                  (hps_0_h2f_lw_axi_master_rresp),                                        //                 .rresp
		.rlast                  (hps_0_h2f_lw_axi_master_rlast),                                        //                 .rlast
		.rvalid                 (hps_0_h2f_lw_axi_master_rvalid),                                       //                 .rvalid
		.rready                 (hps_0_h2f_lw_axi_master_rready),                                       //                 .rready
		.awuser                 (1'b0),                                                                 //      (terminated)
		.aruser                 (1'b0),                                                                 //      (terminated)
		.awqos                  (4'b0000),                                                              //      (terminated)
		.arqos                  (4'b0000),                                                              //      (terminated)
		.awregion               (4'b0000),                                                              //      (terminated)
		.arregion               (4'b0000),                                                              //      (terminated)
		.wuser                  (8'b00000000),                                                          //      (terminated)
		.ruser                  (),                                                                     //      (terminated)
		.buser                  ()                                                                      //      (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (84),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.PKT_TRANS_LOCK            (61),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_PROTECTION_H          (102),
		.PKT_PROTECTION_L          (100),
		.PKT_RESPONSE_STATUS_H     (108),
		.PKT_RESPONSE_STATUS_L     (107),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_ORI_BURST_SIZE_L      (109),
		.PKT_ORI_BURST_SIZE_H      (111),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (112),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (system_pll_outclk0_clk),                                                                         //             clk.clk
		.reset                   (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                                 //       clk_reset.reset
		.m0_address              (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (burst_adapter_source0_ready),                                                                    //              cp.ready
		.cp_valid                (burst_adapter_source0_valid),                                                                    //                .valid
		.cp_data                 (burst_adapter_source0_data),                                                                     //                .data
		.cp_startofpacket        (burst_adapter_source0_startofpacket),                                                            //                .startofpacket
		.cp_endofpacket          (burst_adapter_source0_endofpacket),                                                              //                .endofpacket
		.cp_channel              (burst_adapter_source0_channel),                                                                  //                .channel
		.rf_sink_ready           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                          //     (terminated)
		.m0_writeresponserequest (),                                                                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (113),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                                                         //       clk.clk
		.reset             (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                                 // clk_reset.reset
		.in_data           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                          // (terminated)
		.csr_read          (1'b0),                                                                                           // (terminated)
		.csr_write         (1'b0),                                                                                           // (terminated)
		.csr_readdata      (),                                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                           // (terminated)
		.almost_full_data  (),                                                                                               // (terminated)
		.almost_empty_data (),                                                                                               // (terminated)
		.in_empty          (1'b0),                                                                                           // (terminated)
		.out_empty         (),                                                                                               // (terminated)
		.in_error          (1'b0),                                                                                           // (terminated)
		.out_error         (),                                                                                               // (terminated)
		.in_channel        (1'b0),                                                                                           // (terminated)
		.out_channel       ()                                                                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (system_pll_outclk0_clk),                                                                   //       clk.clk
		.reset             (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                           // clk_reset.reset
		.in_data           (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                                    // (terminated)
		.csr_read          (1'b0),                                                                                     // (terminated)
		.csr_write         (1'b0),                                                                                     // (terminated)
		.csr_readdata      (),                                                                                         // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
		.almost_full_data  (),                                                                                         // (terminated)
		.almost_empty_data (),                                                                                         // (terminated)
		.in_startofpacket  (1'b0),                                                                                     // (terminated)
		.in_endofpacket    (1'b0),                                                                                     // (terminated)
		.out_startofpacket (),                                                                                         // (terminated)
		.out_endofpacket   (),                                                                                         // (terminated)
		.in_empty          (1'b0),                                                                                     // (terminated)
		.out_empty         (),                                                                                         // (terminated)
		.in_error          (1'b0),                                                                                     // (terminated)
		.out_error         (),                                                                                         // (terminated)
		.in_channel        (1'b0),                                                                                     // (terminated)
		.out_channel       ()                                                                                          // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (84),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.PKT_TRANS_LOCK            (61),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_PROTECTION_H          (102),
		.PKT_PROTECTION_L          (100),
		.PKT_RESPONSE_STATUS_H     (108),
		.PKT_RESPONSE_STATUS_L     (107),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_ORI_BURST_SIZE_L      (109),
		.PKT_ORI_BURST_SIZE_H      (111),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (112),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (system_pll_outclk0_clk),                                                                         //             clk.clk
		.reset                   (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                                 //       clk_reset.reset
		.m0_address              (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (burst_adapter_001_source0_ready),                                                                //              cp.ready
		.cp_valid                (burst_adapter_001_source0_valid),                                                                //                .valid
		.cp_data                 (burst_adapter_001_source0_data),                                                                 //                .data
		.cp_startofpacket        (burst_adapter_001_source0_startofpacket),                                                        //                .startofpacket
		.cp_endofpacket          (burst_adapter_001_source0_endofpacket),                                                          //                .endofpacket
		.cp_channel              (burst_adapter_001_source0_channel),                                                              //                .channel
		.rf_sink_ready           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                                          //     (terminated)
		.m0_writeresponserequest (),                                                                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (113),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                                                         //       clk.clk
		.reset             (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                                 // clk_reset.reset
		.in_data           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                          // (terminated)
		.csr_read          (1'b0),                                                                                           // (terminated)
		.csr_write         (1'b0),                                                                                           // (terminated)
		.csr_readdata      (),                                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                           // (terminated)
		.almost_full_data  (),                                                                                               // (terminated)
		.almost_empty_data (),                                                                                               // (terminated)
		.in_empty          (1'b0),                                                                                           // (terminated)
		.out_empty         (),                                                                                               // (terminated)
		.in_error          (1'b0),                                                                                           // (terminated)
		.out_error         (),                                                                                               // (terminated)
		.in_channel        (1'b0),                                                                                           // (terminated)
		.out_channel       ()                                                                                                // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (system_pll_outclk0_clk),                                                                   //       clk.clk
		.reset             (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                           // clk_reset.reset
		.in_data           (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                                    // (terminated)
		.csr_read          (1'b0),                                                                                     // (terminated)
		.csr_write         (1'b0),                                                                                     // (terminated)
		.csr_readdata      (),                                                                                         // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
		.almost_full_data  (),                                                                                         // (terminated)
		.almost_empty_data (),                                                                                         // (terminated)
		.in_startofpacket  (1'b0),                                                                                     // (terminated)
		.in_endofpacket    (1'b0),                                                                                     // (terminated)
		.out_startofpacket (),                                                                                         // (terminated)
		.out_endofpacket   (),                                                                                         // (terminated)
		.in_empty          (1'b0),                                                                                     // (terminated)
		.out_empty         (),                                                                                         // (terminated)
		.in_error          (1'b0),                                                                                     // (terminated)
		.out_error         (),                                                                                         // (terminated)
		.in_channel        (1'b0),                                                                                     // (terminated)
		.out_channel       ()                                                                                          // (terminated)
	);

	soc_system_mm_interconnect_3_addr_router addr_router (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_write_cp_ready),                        //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_write_cp_valid),                        //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_write_cp_data),                         //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket),                //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket),                  //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                               //       src.ready
		.src_valid          (addr_router_src_valid),                                               //          .valid
		.src_data           (addr_router_src_data),                                                //          .data
		.src_channel        (addr_router_src_channel),                                             //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                          //          .endofpacket
	);

	soc_system_mm_interconnect_3_addr_router addr_router_001 (
		.sink_ready         (hps_0_h2f_lw_axi_master_agent_read_cp_ready),                         //      sink.ready
		.sink_valid         (hps_0_h2f_lw_axi_master_agent_read_cp_valid),                         //          .valid
		.sink_data          (hps_0_h2f_lw_axi_master_agent_read_cp_data),                          //          .data
		.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket),                   //          .endofpacket
		.clk                (clk_0_clk_clk),                                                       //       clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                           //       src.ready
		.src_valid          (addr_router_001_src_valid),                                           //          .valid
		.src_data           (addr_router_001_src_data),                                            //          .data
		.src_channel        (addr_router_001_src_channel),                                         //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                      //          .endofpacket
	);

	soc_system_mm_interconnect_3_id_router id_router (
		.sink_ready         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                                                               //       clk.clk
		.reset              (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                       // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                                  //       src.ready
		.src_valid          (id_router_src_valid),                                                                  //          .valid
		.src_data           (id_router_src_data),                                                                   //          .data
		.src_channel        (id_router_src_channel),                                                                //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                          //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                             //          .endofpacket
	);

	soc_system_mm_interconnect_3_id_router id_router_001 (
		.sink_ready         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                                                               //       clk.clk
		.reset              (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),                       // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                                                              //       src.ready
		.src_valid          (id_router_001_src_valid),                                                              //          .valid
		.src_data           (id_router_001_src_data),                                                               //          .data
		.src_channel        (id_router_001_src_channel),                                                            //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)                                                         //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.MAX_OUTSTANDING_RESPONSES (7),
		.PIPELINED                 (0),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.REORDER                   (0)
	) limiter (
		.clk                    (clk_0_clk_clk),                                                       //       clk.clk
		.reset                  (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_src_ready),                                               //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_src_valid),                                               //          .valid
		.cmd_sink_data          (addr_router_src_data),                                                //          .data
		.cmd_sink_channel       (addr_router_src_channel),                                             //          .channel
		.cmd_sink_startofpacket (addr_router_src_startofpacket),                                       //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_src_endofpacket),                                         //          .endofpacket
		.cmd_src_ready          (limiter_cmd_src_ready),                                               //   cmd_src.ready
		.cmd_src_data           (limiter_cmd_src_data),                                                //          .data
		.cmd_src_channel        (limiter_cmd_src_channel),                                             //          .channel
		.cmd_src_startofpacket  (limiter_cmd_src_startofpacket),                                       //          .startofpacket
		.cmd_src_endofpacket    (limiter_cmd_src_endofpacket),                                         //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_src_ready),                                              //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_src_valid),                                              //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_src_channel),                                            //          .channel
		.rsp_sink_data          (rsp_xbar_mux_src_data),                                               //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket),                                      //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_src_endofpacket),                                        //          .endofpacket
		.rsp_src_ready          (limiter_rsp_src_ready),                                               //   rsp_src.ready
		.rsp_src_valid          (limiter_rsp_src_valid),                                               //          .valid
		.rsp_src_data           (limiter_rsp_src_data),                                                //          .data
		.rsp_src_channel        (limiter_rsp_src_channel),                                             //          .channel
		.rsp_src_startofpacket  (limiter_rsp_src_startofpacket),                                       //          .startofpacket
		.rsp_src_endofpacket    (limiter_rsp_src_endofpacket),                                         //          .endofpacket
		.cmd_src_valid          (limiter_cmd_valid_data)                                               // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (87),
		.PKT_DEST_ID_L             (87),
		.PKT_SRC_ID_H              (86),
		.PKT_SRC_ID_L              (86),
		.PKT_TRANS_POSTED          (58),
		.PKT_TRANS_WRITE           (59),
		.MAX_OUTSTANDING_RESPONSES (7),
		.PIPELINED                 (0),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.VALID_WIDTH               (2),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.REORDER                   (0)
	) limiter_001 (
		.clk                    (clk_0_clk_clk),                                                       //       clk.clk
		.reset                  (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_001_src_ready),                                           //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_001_src_valid),                                           //          .valid
		.cmd_sink_data          (addr_router_001_src_data),                                            //          .data
		.cmd_sink_channel       (addr_router_001_src_channel),                                         //          .channel
		.cmd_sink_startofpacket (addr_router_001_src_startofpacket),                                   //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_001_src_endofpacket),                                     //          .endofpacket
		.cmd_src_ready          (limiter_001_cmd_src_ready),                                           //   cmd_src.ready
		.cmd_src_data           (limiter_001_cmd_src_data),                                            //          .data
		.cmd_src_channel        (limiter_001_cmd_src_channel),                                         //          .channel
		.cmd_src_startofpacket  (limiter_001_cmd_src_startofpacket),                                   //          .startofpacket
		.cmd_src_endofpacket    (limiter_001_cmd_src_endofpacket),                                     //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_001_src_ready),                                          //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_001_src_valid),                                          //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_001_src_channel),                                        //          .channel
		.rsp_sink_data          (rsp_xbar_mux_001_src_data),                                           //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket),                                  //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_001_src_endofpacket),                                    //          .endofpacket
		.rsp_src_ready          (limiter_001_rsp_src_ready),                                           //   rsp_src.ready
		.rsp_src_valid          (limiter_001_rsp_src_valid),                                           //          .valid
		.rsp_src_data           (limiter_001_rsp_src_data),                                            //          .data
		.rsp_src_channel        (limiter_001_rsp_src_channel),                                         //          .channel
		.rsp_src_startofpacket  (limiter_001_rsp_src_startofpacket),                                   //          .startofpacket
		.rsp_src_endofpacket    (limiter_001_rsp_src_endofpacket),                                     //          .endofpacket
		.cmd_src_valid          (limiter_001_cmd_valid_data)                                           // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (84),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (65),
		.OUT_BURSTWRAP_H           (76),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0)
	) burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                         //       cr0.clk
		.reset                 (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (cmd_xbar_mux_src_valid),                                         //     sink0.valid
		.sink0_data            (cmd_xbar_mux_src_data),                                          //          .data
		.sink0_channel         (cmd_xbar_mux_src_channel),                                       //          .channel
		.sink0_startofpacket   (cmd_xbar_mux_src_startofpacket),                                 //          .startofpacket
		.sink0_endofpacket     (cmd_xbar_mux_src_endofpacket),                                   //          .endofpacket
		.sink0_ready           (cmd_xbar_mux_src_ready),                                         //          .ready
		.source0_valid         (burst_adapter_source0_valid),                                    //   source0.valid
		.source0_data          (burst_adapter_source0_data),                                     //          .data
		.source0_channel       (burst_adapter_source0_channel),                                  //          .channel
		.source0_startofpacket (burst_adapter_source0_startofpacket),                            //          .startofpacket
		.source0_endofpacket   (burst_adapter_source0_endofpacket),                              //          .endofpacket
		.source0_ready         (burst_adapter_source0_ready)                                     //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (56),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (84),
		.PKT_BYTE_CNT_H            (69),
		.PKT_BYTE_CNT_L            (63),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (70),
		.PKT_TRANS_COMPRESSED_READ (57),
		.PKT_TRANS_WRITE           (59),
		.PKT_TRANS_READ            (60),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (112),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (65),
		.OUT_BURSTWRAP_H           (76),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0)
	) burst_adapter_001 (
		.clk                   (system_pll_outclk0_clk),                                         //       cr0.clk
		.reset                 (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (cmd_xbar_mux_001_src_valid),                                     //     sink0.valid
		.sink0_data            (cmd_xbar_mux_001_src_data),                                      //          .data
		.sink0_channel         (cmd_xbar_mux_001_src_channel),                                   //          .channel
		.sink0_startofpacket   (cmd_xbar_mux_001_src_startofpacket),                             //          .startofpacket
		.sink0_endofpacket     (cmd_xbar_mux_001_src_endofpacket),                               //          .endofpacket
		.sink0_ready           (cmd_xbar_mux_001_src_ready),                                     //          .ready
		.source0_valid         (burst_adapter_001_source0_valid),                                //   source0.valid
		.source0_data          (burst_adapter_001_source0_data),                                 //          .data
		.source0_channel       (burst_adapter_001_source0_channel),                              //          .channel
		.source0_startofpacket (burst_adapter_001_source0_startofpacket),                        //          .startofpacket
		.source0_endofpacket   (burst_adapter_001_source0_endofpacket),                          //          .endofpacket
		.source0_ready         (burst_adapter_001_source0_ready)                                 //          .ready
	);

	soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux (
		.clk                (clk_0_clk_clk),                                                       //        clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (limiter_cmd_src_ready),                                               //       sink.ready
		.sink_channel       (limiter_cmd_src_channel),                                             //           .channel
		.sink_data          (limiter_cmd_src_data),                                                //           .data
		.sink_startofpacket (limiter_cmd_src_startofpacket),                                       //           .startofpacket
		.sink_endofpacket   (limiter_cmd_src_endofpacket),                                         //           .endofpacket
		.sink_valid         (limiter_cmd_valid_data),                                              // sink_valid.data
		.src0_ready         (cmd_xbar_demux_src0_ready),                                           //       src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),                                           //           .valid
		.src0_data          (cmd_xbar_demux_src0_data),                                            //           .data
		.src0_channel       (cmd_xbar_demux_src0_channel),                                         //           .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket),                                   //           .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),                                     //           .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),                                           //       src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),                                           //           .valid
		.src1_data          (cmd_xbar_demux_src1_data),                                            //           .data
		.src1_channel       (cmd_xbar_demux_src1_channel),                                         //           .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket),                                   //           .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket)                                      //           .endofpacket
	);

	soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux_001 (
		.clk                (clk_0_clk_clk),                                                       //        clk.clk
		.reset              (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  clk_reset.reset
		.sink_ready         (limiter_001_cmd_src_ready),                                           //       sink.ready
		.sink_channel       (limiter_001_cmd_src_channel),                                         //           .channel
		.sink_data          (limiter_001_cmd_src_data),                                            //           .data
		.sink_startofpacket (limiter_001_cmd_src_startofpacket),                                   //           .startofpacket
		.sink_endofpacket   (limiter_001_cmd_src_endofpacket),                                     //           .endofpacket
		.sink_valid         (limiter_001_cmd_valid_data),                                          // sink_valid.data
		.src0_ready         (cmd_xbar_demux_001_src0_ready),                                       //       src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),                                       //           .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),                                        //           .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),                                     //           .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket),                               //           .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),                                 //           .endofpacket
		.src1_ready         (cmd_xbar_demux_001_src1_ready),                                       //       src1.ready
		.src1_valid         (cmd_xbar_demux_001_src1_valid),                                       //           .valid
		.src1_data          (cmd_xbar_demux_001_src1_data),                                        //           .data
		.src1_channel       (cmd_xbar_demux_001_src1_channel),                                     //           .channel
		.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket),                               //           .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)                                  //           .endofpacket
	);

	soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (system_pll_outclk0_clk),                                         //       clk.clk
		.reset               (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                                         //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                                         //          .valid
		.src_data            (cmd_xbar_mux_src_data),                                          //          .data
		.src_channel         (cmd_xbar_mux_src_channel),                                       //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),                                 //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),                                   //          .endofpacket
		.sink0_ready         (crosser_out_ready),                                              //     sink0.ready
		.sink0_valid         (crosser_out_valid),                                              //          .valid
		.sink0_channel       (crosser_out_channel),                                            //          .channel
		.sink0_data          (crosser_out_data),                                               //          .data
		.sink0_startofpacket (crosser_out_startofpacket),                                      //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket),                                        //          .endofpacket
		.sink1_ready         (crosser_002_out_ready),                                          //     sink1.ready
		.sink1_valid         (crosser_002_out_valid),                                          //          .valid
		.sink1_channel       (crosser_002_out_channel),                                        //          .channel
		.sink1_data          (crosser_002_out_data),                                           //          .data
		.sink1_startofpacket (crosser_002_out_startofpacket),                                  //          .startofpacket
		.sink1_endofpacket   (crosser_002_out_endofpacket)                                     //          .endofpacket
	);

	soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux_001 (
		.clk                 (system_pll_outclk0_clk),                                         //       clk.clk
		.reset               (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_001_src_ready),                                     //       src.ready
		.src_valid           (cmd_xbar_mux_001_src_valid),                                     //          .valid
		.src_data            (cmd_xbar_mux_001_src_data),                                      //          .data
		.src_channel         (cmd_xbar_mux_001_src_channel),                                   //          .channel
		.src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),                             //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),                               //          .endofpacket
		.sink0_ready         (crosser_001_out_ready),                                          //     sink0.ready
		.sink0_valid         (crosser_001_out_valid),                                          //          .valid
		.sink0_channel       (crosser_001_out_channel),                                        //          .channel
		.sink0_data          (crosser_001_out_data),                                           //          .data
		.sink0_startofpacket (crosser_001_out_startofpacket),                                  //          .startofpacket
		.sink0_endofpacket   (crosser_001_out_endofpacket),                                    //          .endofpacket
		.sink1_ready         (crosser_003_out_ready),                                          //     sink1.ready
		.sink1_valid         (crosser_003_out_valid),                                          //          .valid
		.sink1_channel       (crosser_003_out_channel),                                        //          .channel
		.sink1_data          (crosser_003_out_data),                                           //          .data
		.sink1_startofpacket (crosser_003_out_startofpacket),                                  //          .startofpacket
		.sink1_endofpacket   (crosser_003_out_endofpacket)                                     //          .endofpacket
	);

	soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux (
		.clk                (system_pll_outclk0_clk),                                         //       clk.clk
		.reset              (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_src_ready),                                            //      sink.ready
		.sink_channel       (id_router_src_channel),                                          //          .channel
		.sink_data          (id_router_src_data),                                             //          .data
		.sink_startofpacket (id_router_src_startofpacket),                                    //          .startofpacket
		.sink_endofpacket   (id_router_src_endofpacket),                                      //          .endofpacket
		.sink_valid         (id_router_src_valid),                                            //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),                                      //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),                                      //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),                                       //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),                                    //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),                              //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),                                //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),                                      //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),                                      //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),                                       //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),                                    //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket),                              //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket)                                 //          .endofpacket
	);

	soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux_001 (
		.clk                (system_pll_outclk0_clk),                                         //       clk.clk
		.reset              (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (id_router_001_src_ready),                                        //      sink.ready
		.sink_channel       (id_router_001_src_channel),                                      //          .channel
		.sink_data          (id_router_001_src_data),                                         //          .data
		.sink_startofpacket (id_router_001_src_startofpacket),                                //          .startofpacket
		.sink_endofpacket   (id_router_001_src_endofpacket),                                  //          .endofpacket
		.sink_valid         (id_router_001_src_valid),                                        //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),                                  //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),                                  //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),                                   //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),                                //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket),                          //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),                            //          .endofpacket
		.src1_ready         (rsp_xbar_demux_001_src1_ready),                                  //      src1.ready
		.src1_valid         (rsp_xbar_demux_001_src1_valid),                                  //          .valid
		.src1_data          (rsp_xbar_demux_001_src1_data),                                   //          .data
		.src1_channel       (rsp_xbar_demux_001_src1_channel),                                //          .channel
		.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket),                          //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket)                             //          .endofpacket
	);

	soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                                              //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                                              //          .valid
		.src_data            (rsp_xbar_mux_src_data),                                               //          .data
		.src_channel         (rsp_xbar_mux_src_channel),                                            //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),                                      //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),                                        //          .endofpacket
		.sink0_ready         (crosser_004_out_ready),                                               //     sink0.ready
		.sink0_valid         (crosser_004_out_valid),                                               //          .valid
		.sink0_channel       (crosser_004_out_channel),                                             //          .channel
		.sink0_data          (crosser_004_out_data),                                                //          .data
		.sink0_startofpacket (crosser_004_out_startofpacket),                                       //          .startofpacket
		.sink0_endofpacket   (crosser_004_out_endofpacket),                                         //          .endofpacket
		.sink1_ready         (crosser_006_out_ready),                                               //     sink1.ready
		.sink1_valid         (crosser_006_out_valid),                                               //          .valid
		.sink1_channel       (crosser_006_out_channel),                                             //          .channel
		.sink1_data          (crosser_006_out_data),                                                //          .data
		.sink1_startofpacket (crosser_006_out_startofpacket),                                       //          .startofpacket
		.sink1_endofpacket   (crosser_006_out_endofpacket)                                          //          .endofpacket
	);

	soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux_001 (
		.clk                 (clk_0_clk_clk),                                                       //       clk.clk
		.reset               (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_xbar_mux_001_src_ready),                                          //       src.ready
		.src_valid           (rsp_xbar_mux_001_src_valid),                                          //          .valid
		.src_data            (rsp_xbar_mux_001_src_data),                                           //          .data
		.src_channel         (rsp_xbar_mux_001_src_channel),                                        //          .channel
		.src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),                                  //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),                                    //          .endofpacket
		.sink0_ready         (crosser_005_out_ready),                                               //     sink0.ready
		.sink0_valid         (crosser_005_out_valid),                                               //          .valid
		.sink0_channel       (crosser_005_out_channel),                                             //          .channel
		.sink0_data          (crosser_005_out_data),                                                //          .data
		.sink0_startofpacket (crosser_005_out_startofpacket),                                       //          .startofpacket
		.sink0_endofpacket   (crosser_005_out_endofpacket),                                         //          .endofpacket
		.sink1_ready         (crosser_007_out_ready),                                               //     sink1.ready
		.sink1_valid         (crosser_007_out_valid),                                               //          .valid
		.sink1_channel       (crosser_007_out_channel),                                             //          .channel
		.sink1_data          (crosser_007_out_data),                                                //          .data
		.sink1_startofpacket (crosser_007_out_startofpacket),                                       //          .startofpacket
		.sink1_endofpacket   (crosser_007_out_endofpacket)                                          //          .endofpacket
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (clk_0_clk_clk),                                                       //        in_clk.clk
		.in_reset          (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (system_pll_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_src0_ready),                                           //            in.ready
		.in_valid          (cmd_xbar_demux_src0_valid),                                           //              .valid
		.in_startofpacket  (cmd_xbar_demux_src0_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src0_endofpacket),                                     //              .endofpacket
		.in_channel        (cmd_xbar_demux_src0_channel),                                         //              .channel
		.in_data           (cmd_xbar_demux_src0_data),                                            //              .data
		.out_ready         (crosser_out_ready),                                                   //           out.ready
		.out_valid         (crosser_out_valid),                                                   //              .valid
		.out_startofpacket (crosser_out_startofpacket),                                           //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                             //              .endofpacket
		.out_channel       (crosser_out_channel),                                                 //              .channel
		.out_data          (crosser_out_data),                                                    //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk_0_clk_clk),                                                       //        in_clk.clk
		.in_reset          (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (system_pll_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_src1_ready),                                           //            in.ready
		.in_valid          (cmd_xbar_demux_src1_valid),                                           //              .valid
		.in_startofpacket  (cmd_xbar_demux_src1_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src1_endofpacket),                                     //              .endofpacket
		.in_channel        (cmd_xbar_demux_src1_channel),                                         //              .channel
		.in_data           (cmd_xbar_demux_src1_data),                                            //              .data
		.out_ready         (crosser_001_out_ready),                                               //           out.ready
		.out_valid         (crosser_001_out_valid),                                               //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_001_out_channel),                                             //              .channel
		.out_data          (crosser_001_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_002 (
		.in_clk            (clk_0_clk_clk),                                                       //        in_clk.clk
		.in_reset          (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (system_pll_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_001_src0_ready),                                       //            in.ready
		.in_valid          (cmd_xbar_demux_001_src0_valid),                                       //              .valid
		.in_startofpacket  (cmd_xbar_demux_001_src0_startofpacket),                               //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src0_endofpacket),                                 //              .endofpacket
		.in_channel        (cmd_xbar_demux_001_src0_channel),                                     //              .channel
		.in_data           (cmd_xbar_demux_001_src0_data),                                        //              .data
		.out_ready         (crosser_002_out_ready),                                               //           out.ready
		.out_valid         (crosser_002_out_valid),                                               //              .valid
		.out_startofpacket (crosser_002_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_002_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_002_out_channel),                                             //              .channel
		.out_data          (crosser_002_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_003 (
		.in_clk            (clk_0_clk_clk),                                                       //        in_clk.clk
		.in_reset          (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (system_pll_outclk0_clk),                                              //       out_clk.clk
		.out_reset         (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_001_src1_ready),                                       //            in.ready
		.in_valid          (cmd_xbar_demux_001_src1_valid),                                       //              .valid
		.in_startofpacket  (cmd_xbar_demux_001_src1_startofpacket),                               //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src1_endofpacket),                                 //              .endofpacket
		.in_channel        (cmd_xbar_demux_001_src1_channel),                                     //              .channel
		.in_data           (cmd_xbar_demux_001_src1_data),                                        //              .data
		.out_ready         (crosser_003_out_ready),                                               //           out.ready
		.out_valid         (crosser_003_out_valid),                                               //              .valid
		.out_startofpacket (crosser_003_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_003_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_003_out_channel),                                             //              .channel
		.out_data          (crosser_003_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_004 (
		.in_clk            (system_pll_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      //  in_clk_reset.reset
		.out_clk           (clk_0_clk_clk),                                                       //       out_clk.clk
		.out_reset         (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_src0_ready),                                           //            in.ready
		.in_valid          (rsp_xbar_demux_src0_valid),                                           //              .valid
		.in_startofpacket  (rsp_xbar_demux_src0_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src0_endofpacket),                                     //              .endofpacket
		.in_channel        (rsp_xbar_demux_src0_channel),                                         //              .channel
		.in_data           (rsp_xbar_demux_src0_data),                                            //              .data
		.out_ready         (crosser_004_out_ready),                                               //           out.ready
		.out_valid         (crosser_004_out_valid),                                               //              .valid
		.out_startofpacket (crosser_004_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_004_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_004_out_channel),                                             //              .channel
		.out_data          (crosser_004_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_005 (
		.in_clk            (system_pll_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      //  in_clk_reset.reset
		.out_clk           (clk_0_clk_clk),                                                       //       out_clk.clk
		.out_reset         (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_src1_ready),                                           //            in.ready
		.in_valid          (rsp_xbar_demux_src1_valid),                                           //              .valid
		.in_startofpacket  (rsp_xbar_demux_src1_startofpacket),                                   //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src1_endofpacket),                                     //              .endofpacket
		.in_channel        (rsp_xbar_demux_src1_channel),                                         //              .channel
		.in_data           (rsp_xbar_demux_src1_data),                                            //              .data
		.out_ready         (crosser_005_out_ready),                                               //           out.ready
		.out_valid         (crosser_005_out_valid),                                               //              .valid
		.out_startofpacket (crosser_005_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_005_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_005_out_channel),                                             //              .channel
		.out_data          (crosser_005_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_006 (
		.in_clk            (system_pll_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      //  in_clk_reset.reset
		.out_clk           (clk_0_clk_clk),                                                       //       out_clk.clk
		.out_reset         (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_001_src0_ready),                                       //            in.ready
		.in_valid          (rsp_xbar_demux_001_src0_valid),                                       //              .valid
		.in_startofpacket  (rsp_xbar_demux_001_src0_startofpacket),                               //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_001_src0_endofpacket),                                 //              .endofpacket
		.in_channel        (rsp_xbar_demux_001_src0_channel),                                     //              .channel
		.in_data           (rsp_xbar_demux_001_src0_data),                                        //              .data
		.out_ready         (crosser_006_out_ready),                                               //           out.ready
		.out_valid         (crosser_006_out_valid),                                               //              .valid
		.out_startofpacket (crosser_006_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_006_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_006_out_channel),                                             //              .channel
		.out_data          (crosser_006_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (112),
		.BITS_PER_SYMBOL     (112),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_007 (
		.in_clk            (system_pll_outclk0_clk),                                              //        in_clk.clk
		.in_reset          (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset),      //  in_clk_reset.reset
		.out_clk           (clk_0_clk_clk),                                                       //       out_clk.clk
		.out_reset         (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_001_src1_ready),                                       //            in.ready
		.in_valid          (rsp_xbar_demux_001_src1_valid),                                       //              .valid
		.in_startofpacket  (rsp_xbar_demux_001_src1_startofpacket),                               //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_001_src1_endofpacket),                                 //              .endofpacket
		.in_channel        (rsp_xbar_demux_001_src1_channel),                                     //              .channel
		.in_data           (rsp_xbar_demux_001_src1_data),                                        //              .data
		.out_ready         (crosser_007_out_ready),                                               //           out.ready
		.out_valid         (crosser_007_out_valid),                                               //              .valid
		.out_startofpacket (crosser_007_out_startofpacket),                                       //              .startofpacket
		.out_endofpacket   (crosser_007_out_endofpacket),                                         //              .endofpacket
		.out_channel       (crosser_007_out_channel),                                             //              .channel
		.out_data          (crosser_007_out_data),                                                //              .data
		.in_empty          (1'b0),                                                                //   (terminated)
		.in_error          (1'b0),                                                                //   (terminated)
		.out_empty         (),                                                                    //   (terminated)
		.out_error         ()                                                                     //   (terminated)
	);

endmodule
