// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
//  by:  wig
//  on:  Thu Jun 22 05:51:07 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.3 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: ent_t.v,v $
// Revision 1.3  2006/06/22 07:20:00  wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp 
//
// Generator: mix_0.pl Revision: 1.45 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of ent_t
//

// No user `defines in this module


module ent_t
//
// Generated Module inst_t
//
	(
	);

// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
		wire		mix_logic0_0; 
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//
		assign	mix_logic0_0 = 1'b0;




	//
	// Generated Instances and Port Mappings
	//
		// Generated Instance Port Map for inst_a
		ent_a inst_a (
			.low_bit_a(mix_logic0_0)	// Ground bit port
		);
		// End of Generated Instance Port Map for inst_a

		// Generated Instance Port Map for inst_b
		ent_b inst_b (

		);
		// End of Generated Instance Port Map for inst_b



endmodule
//
// End of Generated Module rtl of ent_t
//

//
//!End of Module/s
// --------------------------------------------------------------
