/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */

(* src = "../../verilog/bytemuxquad.v:1" *)
module ByteMuxQuad(A_i, B_i, C_i, D_i, SAB_i, SC_i, SD_i, Y_o);
  (* src = "../../verilog/bytemuxquad.v:20" *)
  wire [7:0] AB;
  (* src = "../../verilog/bytemuxquad.v:21" *)
  wire [7:0] ABC;
  (* intersynth_conntype = "Byte" *)
  (* src = "../../verilog/bytemuxquad.v:3" *)
  input [7:0] A_i;
  (* intersynth_conntype = "Byte" *)
  (* src = "../../verilog/bytemuxquad.v:5" *)
  input [7:0] B_i;
  (* intersynth_conntype = "Byte" *)
  (* src = "../../verilog/bytemuxquad.v:7" *)
  input [7:0] C_i;
  (* intersynth_conntype = "Byte" *)
  (* src = "../../verilog/bytemuxquad.v:9" *)
  input [7:0] D_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/bytemuxquad.v:11" *)
  input SAB_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/bytemuxquad.v:13" *)
  input SC_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/bytemuxquad.v:15" *)
  input SD_i;
  (* intersynth_conntype = "Byte" *)
  (* src = "../../verilog/bytemuxquad.v:17" *)
  output [7:0] Y_o;
  (* src = "../../verilog/bytemuxquad.v:20" *)
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$ternary$../../verilog/bytemuxquad.v:20$1  (
    .A(A_i),
    .B(B_i),
    .S(SAB_i),
    .Y(AB)
  );
  (* src = "../../verilog/bytemuxquad.v:21" *)
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$ternary$../../verilog/bytemuxquad.v:21$2  (
    .A(AB),
    .B(C_i),
    .S(SC_i),
    .Y(ABC)
  );
  (* src = "../../verilog/bytemuxquad.v:22" *)
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$ternary$../../verilog/bytemuxquad.v:22$3  (
    .A(ABC),
    .B(D_i),
    .S(SD_i),
    .Y(Y_o)
  );
endmodule
