// soc_design_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 16.0 211

`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0 (
		input  wire        system_pll_outclk0_clk,                          //                        system_pll_outclk0.clk
		input  wire        Test_PipeLine_reset_reset_bridge_in_reset_reset, // Test_PipeLine_reset_reset_bridge_in_reset.reset
		input  wire [26:0] niosII_core_data_master_address,                 //                   niosII_core_data_master.address
		output wire        niosII_core_data_master_waitrequest,             //                                          .waitrequest
		input  wire [3:0]  niosII_core_data_master_burstcount,              //                                          .burstcount
		input  wire [3:0]  niosII_core_data_master_byteenable,              //                                          .byteenable
		input  wire        niosII_core_data_master_read,                    //                                          .read
		output wire [31:0] niosII_core_data_master_readdata,                //                                          .readdata
		output wire        niosII_core_data_master_readdatavalid,           //                                          .readdatavalid
		input  wire        niosII_core_data_master_write,                   //                                          .write
		input  wire [31:0] niosII_core_data_master_writedata,               //                                          .writedata
		input  wire        niosII_core_data_master_debugaccess,             //                                          .debugaccess
		input  wire [26:0] niosII_core_instruction_master_address,          //            niosII_core_instruction_master.address
		output wire        niosII_core_instruction_master_waitrequest,      //                                          .waitrequest
		input  wire [3:0]  niosII_core_instruction_master_burstcount,       //                                          .burstcount
		input  wire        niosII_core_instruction_master_read,             //                                          .read
		output wire [31:0] niosII_core_instruction_master_readdata,         //                                          .readdata
		output wire        niosII_core_instruction_master_readdatavalid,    //                                          .readdatavalid
		input  wire [31:0] Test_PipeLine_avm_m0_address,                    //                      Test_PipeLine_avm_m0.address
		output wire        Test_PipeLine_avm_m0_waitrequest,                //                                          .waitrequest
		input  wire [7:0]  Test_PipeLine_avm_m0_burstcount,                 //                                          .burstcount
		input  wire        Test_PipeLine_avm_m0_read,                       //                                          .read
		output wire [31:0] Test_PipeLine_avm_m0_readdata,                   //                                          .readdata
		output wire        Test_PipeLine_avm_m0_readdatavalid,              //                                          .readdatavalid
		input  wire        Test_PipeLine_avm_m0_write,                      //                                          .write
		input  wire [31:0] Test_PipeLine_avm_m0_writedata,                  //                                          .writedata
		output wire [8:0]  convolution_slave_avs_s0_address,                //                  convolution_slave_avs_s0.address
		output wire        convolution_slave_avs_s0_write,                  //                                          .write
		output wire        convolution_slave_avs_s0_read,                   //                                          .read
		input  wire [31:0] convolution_slave_avs_s0_readdata,               //                                          .readdata
		output wire [31:0] convolution_slave_avs_s0_writedata,              //                                          .writedata
		input  wire        convolution_slave_avs_s0_waitrequest,            //                                          .waitrequest
		output wire [0:0]  JTAG_avalon_jtag_slave_address,                  //                    JTAG_avalon_jtag_slave.address
		output wire        JTAG_avalon_jtag_slave_write,                    //                                          .write
		output wire        JTAG_avalon_jtag_slave_read,                     //                                          .read
		input  wire [31:0] JTAG_avalon_jtag_slave_readdata,                 //                                          .readdata
		output wire [31:0] JTAG_avalon_jtag_slave_writedata,                //                                          .writedata
		input  wire        JTAG_avalon_jtag_slave_waitrequest,              //                                          .waitrequest
		output wire        JTAG_avalon_jtag_slave_chipselect,               //                                          .chipselect
		output wire [8:0]  niosII_core_debug_mem_slave_address,             //               niosII_core_debug_mem_slave.address
		output wire        niosII_core_debug_mem_slave_write,               //                                          .write
		output wire        niosII_core_debug_mem_slave_read,                //                                          .read
		input  wire [31:0] niosII_core_debug_mem_slave_readdata,            //                                          .readdata
		output wire [31:0] niosII_core_debug_mem_slave_writedata,           //                                          .writedata
		output wire [3:0]  niosII_core_debug_mem_slave_byteenable,          //                                          .byteenable
		input  wire        niosII_core_debug_mem_slave_waitrequest,         //                                          .waitrequest
		output wire        niosII_core_debug_mem_slave_debugaccess,         //                                          .debugaccess
		output wire [24:0] SDRAM_s1_address,                                //                                  SDRAM_s1.address
		output wire        SDRAM_s1_write,                                  //                                          .write
		output wire        SDRAM_s1_read,                                   //                                          .read
		input  wire [15:0] SDRAM_s1_readdata,                               //                                          .readdata
		output wire [15:0] SDRAM_s1_writedata,                              //                                          .writedata
		output wire [1:0]  SDRAM_s1_byteenable,                             //                                          .byteenable
		input  wire        SDRAM_s1_readdatavalid,                          //                                          .readdatavalid
		input  wire        SDRAM_s1_waitrequest,                            //                                          .waitrequest
		output wire        SDRAM_s1_chipselect,                             //                                          .chipselect
		output wire [14:0] SRAM_s1_address,                                 //                                   SRAM_s1.address
		output wire        SRAM_s1_write,                                   //                                          .write
		input  wire [31:0] SRAM_s1_readdata,                                //                                          .readdata
		output wire [31:0] SRAM_s1_writedata,                               //                                          .writedata
		output wire [3:0]  SRAM_s1_byteenable,                              //                                          .byteenable
		output wire        SRAM_s1_chipselect,                              //                                          .chipselect
		output wire        SRAM_s1_clken,                                   //                                          .clken
		output wire [2:0]  Sys_Timer_s1_address,                            //                              Sys_Timer_s1.address
		output wire        Sys_Timer_s1_write,                              //                                          .write
		input  wire [15:0] Sys_Timer_s1_readdata,                           //                                          .readdata
		output wire [15:0] Sys_Timer_s1_writedata,                          //                                          .writedata
		output wire        Sys_Timer_s1_chipselect,                         //                                          .chipselect
		output wire [0:0]  SystemID_control_slave_address,                  //                    SystemID_control_slave.address
		input  wire [31:0] SystemID_control_slave_readdata,                 //                                          .readdata
		output wire [7:0]  Test_PipeLine_avs_s0_address,                    //                      Test_PipeLine_avs_s0.address
		output wire        Test_PipeLine_avs_s0_write,                      //                                          .write
		output wire        Test_PipeLine_avs_s0_read,                       //                                          .read
		input  wire [31:0] Test_PipeLine_avs_s0_readdata,                   //                                          .readdata
		output wire [31:0] Test_PipeLine_avs_s0_writedata,                  //                                          .writedata
		input  wire        Test_PipeLine_avs_s0_waitrequest,                //                                          .waitrequest
		output wire [0:0]  UART_COM_avalon_rs232_slave_address,             //               UART_COM_avalon_rs232_slave.address
		output wire        UART_COM_avalon_rs232_slave_write,               //                                          .write
		output wire        UART_COM_avalon_rs232_slave_read,                //                                          .read
		input  wire [31:0] UART_COM_avalon_rs232_slave_readdata,            //                                          .readdata
		output wire [31:0] UART_COM_avalon_rs232_slave_writedata,           //                                          .writedata
		output wire [3:0]  UART_COM_avalon_rs232_slave_byteenable,          //                                          .byteenable
		output wire        UART_COM_avalon_rs232_slave_chipselect           //                                          .chipselect
	);

	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest;             // Test_PipeLine_avm_m0_agent:av_waitrequest -> Test_PipeLine_avm_m0_translator:uav_waitrequest
	wire   [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata;                // Test_PipeLine_avm_m0_agent:av_readdata -> Test_PipeLine_avm_m0_translator:uav_readdata
	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess;             // Test_PipeLine_avm_m0_translator:uav_debugaccess -> Test_PipeLine_avm_m0_agent:av_debugaccess
	wire   [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_address;                 // Test_PipeLine_avm_m0_translator:uav_address -> Test_PipeLine_avm_m0_agent:av_address
	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_read;                    // Test_PipeLine_avm_m0_translator:uav_read -> Test_PipeLine_avm_m0_agent:av_read
	wire    [3:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable;              // Test_PipeLine_avm_m0_translator:uav_byteenable -> Test_PipeLine_avm_m0_agent:av_byteenable
	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid;           // Test_PipeLine_avm_m0_agent:av_readdatavalid -> Test_PipeLine_avm_m0_translator:uav_readdatavalid
	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_lock;                    // Test_PipeLine_avm_m0_translator:uav_lock -> Test_PipeLine_avm_m0_agent:av_lock
	wire          test_pipeline_avm_m0_translator_avalon_universal_master_0_write;                   // Test_PipeLine_avm_m0_translator:uav_write -> Test_PipeLine_avm_m0_agent:av_write
	wire   [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata;               // Test_PipeLine_avm_m0_translator:uav_writedata -> Test_PipeLine_avm_m0_agent:av_writedata
	wire    [9:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount;              // Test_PipeLine_avm_m0_translator:uav_burstcount -> Test_PipeLine_avm_m0_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                                 // rsp_mux:src_valid -> Test_PipeLine_avm_m0_agent:rp_valid
	wire  [119:0] rsp_mux_src_data;                                                                  // rsp_mux:src_data -> Test_PipeLine_avm_m0_agent:rp_data
	wire          rsp_mux_src_ready;                                                                 // Test_PipeLine_avm_m0_agent:rp_ready -> rsp_mux:src_ready
	wire    [8:0] rsp_mux_src_channel;                                                               // rsp_mux:src_channel -> Test_PipeLine_avm_m0_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                         // rsp_mux:src_startofpacket -> Test_PipeLine_avm_m0_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                           // rsp_mux:src_endofpacket -> Test_PipeLine_avm_m0_agent:rp_endofpacket
	wire          niosii_core_data_master_translator_avalon_universal_master_0_waitrequest;          // niosII_core_data_master_agent:av_waitrequest -> niosII_core_data_master_translator:uav_waitrequest
	wire   [31:0] niosii_core_data_master_translator_avalon_universal_master_0_readdata;             // niosII_core_data_master_agent:av_readdata -> niosII_core_data_master_translator:uav_readdata
	wire          niosii_core_data_master_translator_avalon_universal_master_0_debugaccess;          // niosII_core_data_master_translator:uav_debugaccess -> niosII_core_data_master_agent:av_debugaccess
	wire   [31:0] niosii_core_data_master_translator_avalon_universal_master_0_address;              // niosII_core_data_master_translator:uav_address -> niosII_core_data_master_agent:av_address
	wire          niosii_core_data_master_translator_avalon_universal_master_0_read;                 // niosII_core_data_master_translator:uav_read -> niosII_core_data_master_agent:av_read
	wire    [3:0] niosii_core_data_master_translator_avalon_universal_master_0_byteenable;           // niosII_core_data_master_translator:uav_byteenable -> niosII_core_data_master_agent:av_byteenable
	wire          niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid;        // niosII_core_data_master_agent:av_readdatavalid -> niosII_core_data_master_translator:uav_readdatavalid
	wire          niosii_core_data_master_translator_avalon_universal_master_0_lock;                 // niosII_core_data_master_translator:uav_lock -> niosII_core_data_master_agent:av_lock
	wire          niosii_core_data_master_translator_avalon_universal_master_0_write;                // niosII_core_data_master_translator:uav_write -> niosII_core_data_master_agent:av_write
	wire   [31:0] niosii_core_data_master_translator_avalon_universal_master_0_writedata;            // niosII_core_data_master_translator:uav_writedata -> niosII_core_data_master_agent:av_writedata
	wire    [5:0] niosii_core_data_master_translator_avalon_universal_master_0_burstcount;           // niosII_core_data_master_translator:uav_burstcount -> niosII_core_data_master_agent:av_burstcount
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest;   // niosII_core_instruction_master_agent:av_waitrequest -> niosII_core_instruction_master_translator:uav_waitrequest
	wire   [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_readdata;      // niosII_core_instruction_master_agent:av_readdata -> niosII_core_instruction_master_translator:uav_readdata
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess;   // niosII_core_instruction_master_translator:uav_debugaccess -> niosII_core_instruction_master_agent:av_debugaccess
	wire   [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_address;       // niosII_core_instruction_master_translator:uav_address -> niosII_core_instruction_master_agent:av_address
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_read;          // niosII_core_instruction_master_translator:uav_read -> niosII_core_instruction_master_agent:av_read
	wire    [3:0] niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable;    // niosII_core_instruction_master_translator:uav_byteenable -> niosII_core_instruction_master_agent:av_byteenable
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid; // niosII_core_instruction_master_agent:av_readdatavalid -> niosII_core_instruction_master_translator:uav_readdatavalid
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_lock;          // niosII_core_instruction_master_translator:uav_lock -> niosII_core_instruction_master_agent:av_lock
	wire          niosii_core_instruction_master_translator_avalon_universal_master_0_write;         // niosII_core_instruction_master_translator:uav_write -> niosII_core_instruction_master_agent:av_write
	wire   [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_writedata;     // niosII_core_instruction_master_translator:uav_writedata -> niosII_core_instruction_master_agent:av_writedata
	wire    [5:0] niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount;    // niosII_core_instruction_master_translator:uav_burstcount -> niosII_core_instruction_master_agent:av_burstcount
	wire   [15:0] sdram_s1_agent_m0_readdata;                                                        // SDRAM_s1_translator:uav_readdata -> SDRAM_s1_agent:m0_readdata
	wire          sdram_s1_agent_m0_waitrequest;                                                     // SDRAM_s1_translator:uav_waitrequest -> SDRAM_s1_agent:m0_waitrequest
	wire          sdram_s1_agent_m0_debugaccess;                                                     // SDRAM_s1_agent:m0_debugaccess -> SDRAM_s1_translator:uav_debugaccess
	wire   [31:0] sdram_s1_agent_m0_address;                                                         // SDRAM_s1_agent:m0_address -> SDRAM_s1_translator:uav_address
	wire    [1:0] sdram_s1_agent_m0_byteenable;                                                      // SDRAM_s1_agent:m0_byteenable -> SDRAM_s1_translator:uav_byteenable
	wire          sdram_s1_agent_m0_read;                                                            // SDRAM_s1_agent:m0_read -> SDRAM_s1_translator:uav_read
	wire          sdram_s1_agent_m0_readdatavalid;                                                   // SDRAM_s1_translator:uav_readdatavalid -> SDRAM_s1_agent:m0_readdatavalid
	wire          sdram_s1_agent_m0_lock;                                                            // SDRAM_s1_agent:m0_lock -> SDRAM_s1_translator:uav_lock
	wire   [15:0] sdram_s1_agent_m0_writedata;                                                       // SDRAM_s1_agent:m0_writedata -> SDRAM_s1_translator:uav_writedata
	wire          sdram_s1_agent_m0_write;                                                           // SDRAM_s1_agent:m0_write -> SDRAM_s1_translator:uav_write
	wire    [1:0] sdram_s1_agent_m0_burstcount;                                                      // SDRAM_s1_agent:m0_burstcount -> SDRAM_s1_translator:uav_burstcount
	wire          sdram_s1_agent_rf_source_valid;                                                    // SDRAM_s1_agent:rf_source_valid -> SDRAM_s1_agent_rsp_fifo:in_valid
	wire  [102:0] sdram_s1_agent_rf_source_data;                                                     // SDRAM_s1_agent:rf_source_data -> SDRAM_s1_agent_rsp_fifo:in_data
	wire          sdram_s1_agent_rf_source_ready;                                                    // SDRAM_s1_agent_rsp_fifo:in_ready -> SDRAM_s1_agent:rf_source_ready
	wire          sdram_s1_agent_rf_source_startofpacket;                                            // SDRAM_s1_agent:rf_source_startofpacket -> SDRAM_s1_agent_rsp_fifo:in_startofpacket
	wire          sdram_s1_agent_rf_source_endofpacket;                                              // SDRAM_s1_agent:rf_source_endofpacket -> SDRAM_s1_agent_rsp_fifo:in_endofpacket
	wire          sdram_s1_agent_rsp_fifo_out_valid;                                                 // SDRAM_s1_agent_rsp_fifo:out_valid -> SDRAM_s1_agent:rf_sink_valid
	wire  [102:0] sdram_s1_agent_rsp_fifo_out_data;                                                  // SDRAM_s1_agent_rsp_fifo:out_data -> SDRAM_s1_agent:rf_sink_data
	wire          sdram_s1_agent_rsp_fifo_out_ready;                                                 // SDRAM_s1_agent:rf_sink_ready -> SDRAM_s1_agent_rsp_fifo:out_ready
	wire          sdram_s1_agent_rsp_fifo_out_startofpacket;                                         // SDRAM_s1_agent_rsp_fifo:out_startofpacket -> SDRAM_s1_agent:rf_sink_startofpacket
	wire          sdram_s1_agent_rsp_fifo_out_endofpacket;                                           // SDRAM_s1_agent_rsp_fifo:out_endofpacket -> SDRAM_s1_agent:rf_sink_endofpacket
	wire          sdram_s1_agent_rdata_fifo_src_valid;                                               // SDRAM_s1_agent:rdata_fifo_src_valid -> SDRAM_s1_agent_rdata_fifo:in_valid
	wire   [17:0] sdram_s1_agent_rdata_fifo_src_data;                                                // SDRAM_s1_agent:rdata_fifo_src_data -> SDRAM_s1_agent_rdata_fifo:in_data
	wire          sdram_s1_agent_rdata_fifo_src_ready;                                               // SDRAM_s1_agent_rdata_fifo:in_ready -> SDRAM_s1_agent:rdata_fifo_src_ready
	wire   [31:0] niosii_core_debug_mem_slave_agent_m0_readdata;                                     // niosII_core_debug_mem_slave_translator:uav_readdata -> niosII_core_debug_mem_slave_agent:m0_readdata
	wire          niosii_core_debug_mem_slave_agent_m0_waitrequest;                                  // niosII_core_debug_mem_slave_translator:uav_waitrequest -> niosII_core_debug_mem_slave_agent:m0_waitrequest
	wire          niosii_core_debug_mem_slave_agent_m0_debugaccess;                                  // niosII_core_debug_mem_slave_agent:m0_debugaccess -> niosII_core_debug_mem_slave_translator:uav_debugaccess
	wire   [31:0] niosii_core_debug_mem_slave_agent_m0_address;                                      // niosII_core_debug_mem_slave_agent:m0_address -> niosII_core_debug_mem_slave_translator:uav_address
	wire    [3:0] niosii_core_debug_mem_slave_agent_m0_byteenable;                                   // niosII_core_debug_mem_slave_agent:m0_byteenable -> niosII_core_debug_mem_slave_translator:uav_byteenable
	wire          niosii_core_debug_mem_slave_agent_m0_read;                                         // niosII_core_debug_mem_slave_agent:m0_read -> niosII_core_debug_mem_slave_translator:uav_read
	wire          niosii_core_debug_mem_slave_agent_m0_readdatavalid;                                // niosII_core_debug_mem_slave_translator:uav_readdatavalid -> niosII_core_debug_mem_slave_agent:m0_readdatavalid
	wire          niosii_core_debug_mem_slave_agent_m0_lock;                                         // niosII_core_debug_mem_slave_agent:m0_lock -> niosII_core_debug_mem_slave_translator:uav_lock
	wire   [31:0] niosii_core_debug_mem_slave_agent_m0_writedata;                                    // niosII_core_debug_mem_slave_agent:m0_writedata -> niosII_core_debug_mem_slave_translator:uav_writedata
	wire          niosii_core_debug_mem_slave_agent_m0_write;                                        // niosII_core_debug_mem_slave_agent:m0_write -> niosII_core_debug_mem_slave_translator:uav_write
	wire    [2:0] niosii_core_debug_mem_slave_agent_m0_burstcount;                                   // niosII_core_debug_mem_slave_agent:m0_burstcount -> niosII_core_debug_mem_slave_translator:uav_burstcount
	wire          niosii_core_debug_mem_slave_agent_rf_source_valid;                                 // niosII_core_debug_mem_slave_agent:rf_source_valid -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_valid
	wire  [120:0] niosii_core_debug_mem_slave_agent_rf_source_data;                                  // niosII_core_debug_mem_slave_agent:rf_source_data -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_data
	wire          niosii_core_debug_mem_slave_agent_rf_source_ready;                                 // niosII_core_debug_mem_slave_agent_rsp_fifo:in_ready -> niosII_core_debug_mem_slave_agent:rf_source_ready
	wire          niosii_core_debug_mem_slave_agent_rf_source_startofpacket;                         // niosII_core_debug_mem_slave_agent:rf_source_startofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_startofpacket
	wire          niosii_core_debug_mem_slave_agent_rf_source_endofpacket;                           // niosII_core_debug_mem_slave_agent:rf_source_endofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_endofpacket
	wire          niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid;                              // niosII_core_debug_mem_slave_agent_rsp_fifo:out_valid -> niosII_core_debug_mem_slave_agent:rf_sink_valid
	wire  [120:0] niosii_core_debug_mem_slave_agent_rsp_fifo_out_data;                               // niosII_core_debug_mem_slave_agent_rsp_fifo:out_data -> niosII_core_debug_mem_slave_agent:rf_sink_data
	wire          niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready;                              // niosII_core_debug_mem_slave_agent:rf_sink_ready -> niosII_core_debug_mem_slave_agent_rsp_fifo:out_ready
	wire          niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket;                      // niosII_core_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_startofpacket
	wire          niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket;                        // niosII_core_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_endofpacket
	wire   [31:0] sram_s1_agent_m0_readdata;                                                         // SRAM_s1_translator:uav_readdata -> SRAM_s1_agent:m0_readdata
	wire          sram_s1_agent_m0_waitrequest;                                                      // SRAM_s1_translator:uav_waitrequest -> SRAM_s1_agent:m0_waitrequest
	wire          sram_s1_agent_m0_debugaccess;                                                      // SRAM_s1_agent:m0_debugaccess -> SRAM_s1_translator:uav_debugaccess
	wire   [31:0] sram_s1_agent_m0_address;                                                          // SRAM_s1_agent:m0_address -> SRAM_s1_translator:uav_address
	wire    [3:0] sram_s1_agent_m0_byteenable;                                                       // SRAM_s1_agent:m0_byteenable -> SRAM_s1_translator:uav_byteenable
	wire          sram_s1_agent_m0_read;                                                             // SRAM_s1_agent:m0_read -> SRAM_s1_translator:uav_read
	wire          sram_s1_agent_m0_readdatavalid;                                                    // SRAM_s1_translator:uav_readdatavalid -> SRAM_s1_agent:m0_readdatavalid
	wire          sram_s1_agent_m0_lock;                                                             // SRAM_s1_agent:m0_lock -> SRAM_s1_translator:uav_lock
	wire   [31:0] sram_s1_agent_m0_writedata;                                                        // SRAM_s1_agent:m0_writedata -> SRAM_s1_translator:uav_writedata
	wire          sram_s1_agent_m0_write;                                                            // SRAM_s1_agent:m0_write -> SRAM_s1_translator:uav_write
	wire    [2:0] sram_s1_agent_m0_burstcount;                                                       // SRAM_s1_agent:m0_burstcount -> SRAM_s1_translator:uav_burstcount
	wire          sram_s1_agent_rf_source_valid;                                                     // SRAM_s1_agent:rf_source_valid -> SRAM_s1_agent_rsp_fifo:in_valid
	wire  [120:0] sram_s1_agent_rf_source_data;                                                      // SRAM_s1_agent:rf_source_data -> SRAM_s1_agent_rsp_fifo:in_data
	wire          sram_s1_agent_rf_source_ready;                                                     // SRAM_s1_agent_rsp_fifo:in_ready -> SRAM_s1_agent:rf_source_ready
	wire          sram_s1_agent_rf_source_startofpacket;                                             // SRAM_s1_agent:rf_source_startofpacket -> SRAM_s1_agent_rsp_fifo:in_startofpacket
	wire          sram_s1_agent_rf_source_endofpacket;                                               // SRAM_s1_agent:rf_source_endofpacket -> SRAM_s1_agent_rsp_fifo:in_endofpacket
	wire          sram_s1_agent_rsp_fifo_out_valid;                                                  // SRAM_s1_agent_rsp_fifo:out_valid -> SRAM_s1_agent:rf_sink_valid
	wire  [120:0] sram_s1_agent_rsp_fifo_out_data;                                                   // SRAM_s1_agent_rsp_fifo:out_data -> SRAM_s1_agent:rf_sink_data
	wire          sram_s1_agent_rsp_fifo_out_ready;                                                  // SRAM_s1_agent:rf_sink_ready -> SRAM_s1_agent_rsp_fifo:out_ready
	wire          sram_s1_agent_rsp_fifo_out_startofpacket;                                          // SRAM_s1_agent_rsp_fifo:out_startofpacket -> SRAM_s1_agent:rf_sink_startofpacket
	wire          sram_s1_agent_rsp_fifo_out_endofpacket;                                            // SRAM_s1_agent_rsp_fifo:out_endofpacket -> SRAM_s1_agent:rf_sink_endofpacket
	wire   [31:0] jtag_avalon_jtag_slave_agent_m0_readdata;                                          // JTAG_avalon_jtag_slave_translator:uav_readdata -> JTAG_avalon_jtag_slave_agent:m0_readdata
	wire          jtag_avalon_jtag_slave_agent_m0_waitrequest;                                       // JTAG_avalon_jtag_slave_translator:uav_waitrequest -> JTAG_avalon_jtag_slave_agent:m0_waitrequest
	wire          jtag_avalon_jtag_slave_agent_m0_debugaccess;                                       // JTAG_avalon_jtag_slave_agent:m0_debugaccess -> JTAG_avalon_jtag_slave_translator:uav_debugaccess
	wire   [31:0] jtag_avalon_jtag_slave_agent_m0_address;                                           // JTAG_avalon_jtag_slave_agent:m0_address -> JTAG_avalon_jtag_slave_translator:uav_address
	wire    [3:0] jtag_avalon_jtag_slave_agent_m0_byteenable;                                        // JTAG_avalon_jtag_slave_agent:m0_byteenable -> JTAG_avalon_jtag_slave_translator:uav_byteenable
	wire          jtag_avalon_jtag_slave_agent_m0_read;                                              // JTAG_avalon_jtag_slave_agent:m0_read -> JTAG_avalon_jtag_slave_translator:uav_read
	wire          jtag_avalon_jtag_slave_agent_m0_readdatavalid;                                     // JTAG_avalon_jtag_slave_translator:uav_readdatavalid -> JTAG_avalon_jtag_slave_agent:m0_readdatavalid
	wire          jtag_avalon_jtag_slave_agent_m0_lock;                                              // JTAG_avalon_jtag_slave_agent:m0_lock -> JTAG_avalon_jtag_slave_translator:uav_lock
	wire   [31:0] jtag_avalon_jtag_slave_agent_m0_writedata;                                         // JTAG_avalon_jtag_slave_agent:m0_writedata -> JTAG_avalon_jtag_slave_translator:uav_writedata
	wire          jtag_avalon_jtag_slave_agent_m0_write;                                             // JTAG_avalon_jtag_slave_agent:m0_write -> JTAG_avalon_jtag_slave_translator:uav_write
	wire    [2:0] jtag_avalon_jtag_slave_agent_m0_burstcount;                                        // JTAG_avalon_jtag_slave_agent:m0_burstcount -> JTAG_avalon_jtag_slave_translator:uav_burstcount
	wire          jtag_avalon_jtag_slave_agent_rf_source_valid;                                      // JTAG_avalon_jtag_slave_agent:rf_source_valid -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [120:0] jtag_avalon_jtag_slave_agent_rf_source_data;                                       // JTAG_avalon_jtag_slave_agent:rf_source_data -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire          jtag_avalon_jtag_slave_agent_rf_source_ready;                                      // JTAG_avalon_jtag_slave_agent_rsp_fifo:in_ready -> JTAG_avalon_jtag_slave_agent:rf_source_ready
	wire          jtag_avalon_jtag_slave_agent_rf_source_startofpacket;                              // JTAG_avalon_jtag_slave_agent:rf_source_startofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire          jtag_avalon_jtag_slave_agent_rf_source_endofpacket;                                // JTAG_avalon_jtag_slave_agent:rf_source_endofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire          jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid;                                   // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_valid -> JTAG_avalon_jtag_slave_agent:rf_sink_valid
	wire  [120:0] jtag_avalon_jtag_slave_agent_rsp_fifo_out_data;                                    // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_data -> JTAG_avalon_jtag_slave_agent:rf_sink_data
	wire          jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready;                                   // JTAG_avalon_jtag_slave_agent:rf_sink_ready -> JTAG_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire          jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;                           // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire          jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                             // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire   [31:0] uart_com_avalon_rs232_slave_agent_m0_readdata;                                     // UART_COM_avalon_rs232_slave_translator:uav_readdata -> UART_COM_avalon_rs232_slave_agent:m0_readdata
	wire          uart_com_avalon_rs232_slave_agent_m0_waitrequest;                                  // UART_COM_avalon_rs232_slave_translator:uav_waitrequest -> UART_COM_avalon_rs232_slave_agent:m0_waitrequest
	wire          uart_com_avalon_rs232_slave_agent_m0_debugaccess;                                  // UART_COM_avalon_rs232_slave_agent:m0_debugaccess -> UART_COM_avalon_rs232_slave_translator:uav_debugaccess
	wire   [31:0] uart_com_avalon_rs232_slave_agent_m0_address;                                      // UART_COM_avalon_rs232_slave_agent:m0_address -> UART_COM_avalon_rs232_slave_translator:uav_address
	wire    [3:0] uart_com_avalon_rs232_slave_agent_m0_byteenable;                                   // UART_COM_avalon_rs232_slave_agent:m0_byteenable -> UART_COM_avalon_rs232_slave_translator:uav_byteenable
	wire          uart_com_avalon_rs232_slave_agent_m0_read;                                         // UART_COM_avalon_rs232_slave_agent:m0_read -> UART_COM_avalon_rs232_slave_translator:uav_read
	wire          uart_com_avalon_rs232_slave_agent_m0_readdatavalid;                                // UART_COM_avalon_rs232_slave_translator:uav_readdatavalid -> UART_COM_avalon_rs232_slave_agent:m0_readdatavalid
	wire          uart_com_avalon_rs232_slave_agent_m0_lock;                                         // UART_COM_avalon_rs232_slave_agent:m0_lock -> UART_COM_avalon_rs232_slave_translator:uav_lock
	wire   [31:0] uart_com_avalon_rs232_slave_agent_m0_writedata;                                    // UART_COM_avalon_rs232_slave_agent:m0_writedata -> UART_COM_avalon_rs232_slave_translator:uav_writedata
	wire          uart_com_avalon_rs232_slave_agent_m0_write;                                        // UART_COM_avalon_rs232_slave_agent:m0_write -> UART_COM_avalon_rs232_slave_translator:uav_write
	wire    [2:0] uart_com_avalon_rs232_slave_agent_m0_burstcount;                                   // UART_COM_avalon_rs232_slave_agent:m0_burstcount -> UART_COM_avalon_rs232_slave_translator:uav_burstcount
	wire          uart_com_avalon_rs232_slave_agent_rf_source_valid;                                 // UART_COM_avalon_rs232_slave_agent:rf_source_valid -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_valid
	wire  [120:0] uart_com_avalon_rs232_slave_agent_rf_source_data;                                  // UART_COM_avalon_rs232_slave_agent:rf_source_data -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_data
	wire          uart_com_avalon_rs232_slave_agent_rf_source_ready;                                 // UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_ready -> UART_COM_avalon_rs232_slave_agent:rf_source_ready
	wire          uart_com_avalon_rs232_slave_agent_rf_source_startofpacket;                         // UART_COM_avalon_rs232_slave_agent:rf_source_startofpacket -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_startofpacket
	wire          uart_com_avalon_rs232_slave_agent_rf_source_endofpacket;                           // UART_COM_avalon_rs232_slave_agent:rf_source_endofpacket -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_endofpacket
	wire          uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid;                              // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_valid -> UART_COM_avalon_rs232_slave_agent:rf_sink_valid
	wire  [120:0] uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data;                               // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_data -> UART_COM_avalon_rs232_slave_agent:rf_sink_data
	wire          uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready;                              // UART_COM_avalon_rs232_slave_agent:rf_sink_ready -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_ready
	wire          uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket;                      // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_startofpacket -> UART_COM_avalon_rs232_slave_agent:rf_sink_startofpacket
	wire          uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket;                        // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_endofpacket -> UART_COM_avalon_rs232_slave_agent:rf_sink_endofpacket
	wire   [31:0] convolution_slave_avs_s0_agent_m0_readdata;                                        // convolution_slave_avs_s0_translator:uav_readdata -> convolution_slave_avs_s0_agent:m0_readdata
	wire          convolution_slave_avs_s0_agent_m0_waitrequest;                                     // convolution_slave_avs_s0_translator:uav_waitrequest -> convolution_slave_avs_s0_agent:m0_waitrequest
	wire          convolution_slave_avs_s0_agent_m0_debugaccess;                                     // convolution_slave_avs_s0_agent:m0_debugaccess -> convolution_slave_avs_s0_translator:uav_debugaccess
	wire   [31:0] convolution_slave_avs_s0_agent_m0_address;                                         // convolution_slave_avs_s0_agent:m0_address -> convolution_slave_avs_s0_translator:uav_address
	wire    [3:0] convolution_slave_avs_s0_agent_m0_byteenable;                                      // convolution_slave_avs_s0_agent:m0_byteenable -> convolution_slave_avs_s0_translator:uav_byteenable
	wire          convolution_slave_avs_s0_agent_m0_read;                                            // convolution_slave_avs_s0_agent:m0_read -> convolution_slave_avs_s0_translator:uav_read
	wire          convolution_slave_avs_s0_agent_m0_readdatavalid;                                   // convolution_slave_avs_s0_translator:uav_readdatavalid -> convolution_slave_avs_s0_agent:m0_readdatavalid
	wire          convolution_slave_avs_s0_agent_m0_lock;                                            // convolution_slave_avs_s0_agent:m0_lock -> convolution_slave_avs_s0_translator:uav_lock
	wire   [31:0] convolution_slave_avs_s0_agent_m0_writedata;                                       // convolution_slave_avs_s0_agent:m0_writedata -> convolution_slave_avs_s0_translator:uav_writedata
	wire          convolution_slave_avs_s0_agent_m0_write;                                           // convolution_slave_avs_s0_agent:m0_write -> convolution_slave_avs_s0_translator:uav_write
	wire    [2:0] convolution_slave_avs_s0_agent_m0_burstcount;                                      // convolution_slave_avs_s0_agent:m0_burstcount -> convolution_slave_avs_s0_translator:uav_burstcount
	wire          convolution_slave_avs_s0_agent_rf_source_valid;                                    // convolution_slave_avs_s0_agent:rf_source_valid -> convolution_slave_avs_s0_agent_rsp_fifo:in_valid
	wire  [120:0] convolution_slave_avs_s0_agent_rf_source_data;                                     // convolution_slave_avs_s0_agent:rf_source_data -> convolution_slave_avs_s0_agent_rsp_fifo:in_data
	wire          convolution_slave_avs_s0_agent_rf_source_ready;                                    // convolution_slave_avs_s0_agent_rsp_fifo:in_ready -> convolution_slave_avs_s0_agent:rf_source_ready
	wire          convolution_slave_avs_s0_agent_rf_source_startofpacket;                            // convolution_slave_avs_s0_agent:rf_source_startofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_startofpacket
	wire          convolution_slave_avs_s0_agent_rf_source_endofpacket;                              // convolution_slave_avs_s0_agent:rf_source_endofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_endofpacket
	wire          convolution_slave_avs_s0_agent_rsp_fifo_out_valid;                                 // convolution_slave_avs_s0_agent_rsp_fifo:out_valid -> convolution_slave_avs_s0_agent:rf_sink_valid
	wire  [120:0] convolution_slave_avs_s0_agent_rsp_fifo_out_data;                                  // convolution_slave_avs_s0_agent_rsp_fifo:out_data -> convolution_slave_avs_s0_agent:rf_sink_data
	wire          convolution_slave_avs_s0_agent_rsp_fifo_out_ready;                                 // convolution_slave_avs_s0_agent:rf_sink_ready -> convolution_slave_avs_s0_agent_rsp_fifo:out_ready
	wire          convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket;                         // convolution_slave_avs_s0_agent_rsp_fifo:out_startofpacket -> convolution_slave_avs_s0_agent:rf_sink_startofpacket
	wire          convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket;                           // convolution_slave_avs_s0_agent_rsp_fifo:out_endofpacket -> convolution_slave_avs_s0_agent:rf_sink_endofpacket
	wire   [31:0] test_pipeline_avs_s0_agent_m0_readdata;                                            // Test_PipeLine_avs_s0_translator:uav_readdata -> Test_PipeLine_avs_s0_agent:m0_readdata
	wire          test_pipeline_avs_s0_agent_m0_waitrequest;                                         // Test_PipeLine_avs_s0_translator:uav_waitrequest -> Test_PipeLine_avs_s0_agent:m0_waitrequest
	wire          test_pipeline_avs_s0_agent_m0_debugaccess;                                         // Test_PipeLine_avs_s0_agent:m0_debugaccess -> Test_PipeLine_avs_s0_translator:uav_debugaccess
	wire   [31:0] test_pipeline_avs_s0_agent_m0_address;                                             // Test_PipeLine_avs_s0_agent:m0_address -> Test_PipeLine_avs_s0_translator:uav_address
	wire    [3:0] test_pipeline_avs_s0_agent_m0_byteenable;                                          // Test_PipeLine_avs_s0_agent:m0_byteenable -> Test_PipeLine_avs_s0_translator:uav_byteenable
	wire          test_pipeline_avs_s0_agent_m0_read;                                                // Test_PipeLine_avs_s0_agent:m0_read -> Test_PipeLine_avs_s0_translator:uav_read
	wire          test_pipeline_avs_s0_agent_m0_readdatavalid;                                       // Test_PipeLine_avs_s0_translator:uav_readdatavalid -> Test_PipeLine_avs_s0_agent:m0_readdatavalid
	wire          test_pipeline_avs_s0_agent_m0_lock;                                                // Test_PipeLine_avs_s0_agent:m0_lock -> Test_PipeLine_avs_s0_translator:uav_lock
	wire   [31:0] test_pipeline_avs_s0_agent_m0_writedata;                                           // Test_PipeLine_avs_s0_agent:m0_writedata -> Test_PipeLine_avs_s0_translator:uav_writedata
	wire          test_pipeline_avs_s0_agent_m0_write;                                               // Test_PipeLine_avs_s0_agent:m0_write -> Test_PipeLine_avs_s0_translator:uav_write
	wire    [2:0] test_pipeline_avs_s0_agent_m0_burstcount;                                          // Test_PipeLine_avs_s0_agent:m0_burstcount -> Test_PipeLine_avs_s0_translator:uav_burstcount
	wire          test_pipeline_avs_s0_agent_rf_source_valid;                                        // Test_PipeLine_avs_s0_agent:rf_source_valid -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_valid
	wire  [120:0] test_pipeline_avs_s0_agent_rf_source_data;                                         // Test_PipeLine_avs_s0_agent:rf_source_data -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_data
	wire          test_pipeline_avs_s0_agent_rf_source_ready;                                        // Test_PipeLine_avs_s0_agent_rsp_fifo:in_ready -> Test_PipeLine_avs_s0_agent:rf_source_ready
	wire          test_pipeline_avs_s0_agent_rf_source_startofpacket;                                // Test_PipeLine_avs_s0_agent:rf_source_startofpacket -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_startofpacket
	wire          test_pipeline_avs_s0_agent_rf_source_endofpacket;                                  // Test_PipeLine_avs_s0_agent:rf_source_endofpacket -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_endofpacket
	wire          test_pipeline_avs_s0_agent_rsp_fifo_out_valid;                                     // Test_PipeLine_avs_s0_agent_rsp_fifo:out_valid -> Test_PipeLine_avs_s0_agent:rf_sink_valid
	wire  [120:0] test_pipeline_avs_s0_agent_rsp_fifo_out_data;                                      // Test_PipeLine_avs_s0_agent_rsp_fifo:out_data -> Test_PipeLine_avs_s0_agent:rf_sink_data
	wire          test_pipeline_avs_s0_agent_rsp_fifo_out_ready;                                     // Test_PipeLine_avs_s0_agent:rf_sink_ready -> Test_PipeLine_avs_s0_agent_rsp_fifo:out_ready
	wire          test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket;                             // Test_PipeLine_avs_s0_agent_rsp_fifo:out_startofpacket -> Test_PipeLine_avs_s0_agent:rf_sink_startofpacket
	wire          test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket;                               // Test_PipeLine_avs_s0_agent_rsp_fifo:out_endofpacket -> Test_PipeLine_avs_s0_agent:rf_sink_endofpacket
	wire   [31:0] systemid_control_slave_agent_m0_readdata;                                          // SystemID_control_slave_translator:uav_readdata -> SystemID_control_slave_agent:m0_readdata
	wire          systemid_control_slave_agent_m0_waitrequest;                                       // SystemID_control_slave_translator:uav_waitrequest -> SystemID_control_slave_agent:m0_waitrequest
	wire          systemid_control_slave_agent_m0_debugaccess;                                       // SystemID_control_slave_agent:m0_debugaccess -> SystemID_control_slave_translator:uav_debugaccess
	wire   [31:0] systemid_control_slave_agent_m0_address;                                           // SystemID_control_slave_agent:m0_address -> SystemID_control_slave_translator:uav_address
	wire    [3:0] systemid_control_slave_agent_m0_byteenable;                                        // SystemID_control_slave_agent:m0_byteenable -> SystemID_control_slave_translator:uav_byteenable
	wire          systemid_control_slave_agent_m0_read;                                              // SystemID_control_slave_agent:m0_read -> SystemID_control_slave_translator:uav_read
	wire          systemid_control_slave_agent_m0_readdatavalid;                                     // SystemID_control_slave_translator:uav_readdatavalid -> SystemID_control_slave_agent:m0_readdatavalid
	wire          systemid_control_slave_agent_m0_lock;                                              // SystemID_control_slave_agent:m0_lock -> SystemID_control_slave_translator:uav_lock
	wire   [31:0] systemid_control_slave_agent_m0_writedata;                                         // SystemID_control_slave_agent:m0_writedata -> SystemID_control_slave_translator:uav_writedata
	wire          systemid_control_slave_agent_m0_write;                                             // SystemID_control_slave_agent:m0_write -> SystemID_control_slave_translator:uav_write
	wire    [2:0] systemid_control_slave_agent_m0_burstcount;                                        // SystemID_control_slave_agent:m0_burstcount -> SystemID_control_slave_translator:uav_burstcount
	wire          systemid_control_slave_agent_rf_source_valid;                                      // SystemID_control_slave_agent:rf_source_valid -> SystemID_control_slave_agent_rsp_fifo:in_valid
	wire  [120:0] systemid_control_slave_agent_rf_source_data;                                       // SystemID_control_slave_agent:rf_source_data -> SystemID_control_slave_agent_rsp_fifo:in_data
	wire          systemid_control_slave_agent_rf_source_ready;                                      // SystemID_control_slave_agent_rsp_fifo:in_ready -> SystemID_control_slave_agent:rf_source_ready
	wire          systemid_control_slave_agent_rf_source_startofpacket;                              // SystemID_control_slave_agent:rf_source_startofpacket -> SystemID_control_slave_agent_rsp_fifo:in_startofpacket
	wire          systemid_control_slave_agent_rf_source_endofpacket;                                // SystemID_control_slave_agent:rf_source_endofpacket -> SystemID_control_slave_agent_rsp_fifo:in_endofpacket
	wire          systemid_control_slave_agent_rsp_fifo_out_valid;                                   // SystemID_control_slave_agent_rsp_fifo:out_valid -> SystemID_control_slave_agent:rf_sink_valid
	wire  [120:0] systemid_control_slave_agent_rsp_fifo_out_data;                                    // SystemID_control_slave_agent_rsp_fifo:out_data -> SystemID_control_slave_agent:rf_sink_data
	wire          systemid_control_slave_agent_rsp_fifo_out_ready;                                   // SystemID_control_slave_agent:rf_sink_ready -> SystemID_control_slave_agent_rsp_fifo:out_ready
	wire          systemid_control_slave_agent_rsp_fifo_out_startofpacket;                           // SystemID_control_slave_agent_rsp_fifo:out_startofpacket -> SystemID_control_slave_agent:rf_sink_startofpacket
	wire          systemid_control_slave_agent_rsp_fifo_out_endofpacket;                             // SystemID_control_slave_agent_rsp_fifo:out_endofpacket -> SystemID_control_slave_agent:rf_sink_endofpacket
	wire   [31:0] sys_timer_s1_agent_m0_readdata;                                                    // Sys_Timer_s1_translator:uav_readdata -> Sys_Timer_s1_agent:m0_readdata
	wire          sys_timer_s1_agent_m0_waitrequest;                                                 // Sys_Timer_s1_translator:uav_waitrequest -> Sys_Timer_s1_agent:m0_waitrequest
	wire          sys_timer_s1_agent_m0_debugaccess;                                                 // Sys_Timer_s1_agent:m0_debugaccess -> Sys_Timer_s1_translator:uav_debugaccess
	wire   [31:0] sys_timer_s1_agent_m0_address;                                                     // Sys_Timer_s1_agent:m0_address -> Sys_Timer_s1_translator:uav_address
	wire    [3:0] sys_timer_s1_agent_m0_byteenable;                                                  // Sys_Timer_s1_agent:m0_byteenable -> Sys_Timer_s1_translator:uav_byteenable
	wire          sys_timer_s1_agent_m0_read;                                                        // Sys_Timer_s1_agent:m0_read -> Sys_Timer_s1_translator:uav_read
	wire          sys_timer_s1_agent_m0_readdatavalid;                                               // Sys_Timer_s1_translator:uav_readdatavalid -> Sys_Timer_s1_agent:m0_readdatavalid
	wire          sys_timer_s1_agent_m0_lock;                                                        // Sys_Timer_s1_agent:m0_lock -> Sys_Timer_s1_translator:uav_lock
	wire   [31:0] sys_timer_s1_agent_m0_writedata;                                                   // Sys_Timer_s1_agent:m0_writedata -> Sys_Timer_s1_translator:uav_writedata
	wire          sys_timer_s1_agent_m0_write;                                                       // Sys_Timer_s1_agent:m0_write -> Sys_Timer_s1_translator:uav_write
	wire    [2:0] sys_timer_s1_agent_m0_burstcount;                                                  // Sys_Timer_s1_agent:m0_burstcount -> Sys_Timer_s1_translator:uav_burstcount
	wire          sys_timer_s1_agent_rf_source_valid;                                                // Sys_Timer_s1_agent:rf_source_valid -> Sys_Timer_s1_agent_rsp_fifo:in_valid
	wire  [120:0] sys_timer_s1_agent_rf_source_data;                                                 // Sys_Timer_s1_agent:rf_source_data -> Sys_Timer_s1_agent_rsp_fifo:in_data
	wire          sys_timer_s1_agent_rf_source_ready;                                                // Sys_Timer_s1_agent_rsp_fifo:in_ready -> Sys_Timer_s1_agent:rf_source_ready
	wire          sys_timer_s1_agent_rf_source_startofpacket;                                        // Sys_Timer_s1_agent:rf_source_startofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_startofpacket
	wire          sys_timer_s1_agent_rf_source_endofpacket;                                          // Sys_Timer_s1_agent:rf_source_endofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_endofpacket
	wire          sys_timer_s1_agent_rsp_fifo_out_valid;                                             // Sys_Timer_s1_agent_rsp_fifo:out_valid -> Sys_Timer_s1_agent:rf_sink_valid
	wire  [120:0] sys_timer_s1_agent_rsp_fifo_out_data;                                              // Sys_Timer_s1_agent_rsp_fifo:out_data -> Sys_Timer_s1_agent:rf_sink_data
	wire          sys_timer_s1_agent_rsp_fifo_out_ready;                                             // Sys_Timer_s1_agent:rf_sink_ready -> Sys_Timer_s1_agent_rsp_fifo:out_ready
	wire          sys_timer_s1_agent_rsp_fifo_out_startofpacket;                                     // Sys_Timer_s1_agent_rsp_fifo:out_startofpacket -> Sys_Timer_s1_agent:rf_sink_startofpacket
	wire          sys_timer_s1_agent_rsp_fifo_out_endofpacket;                                       // Sys_Timer_s1_agent_rsp_fifo:out_endofpacket -> Sys_Timer_s1_agent:rf_sink_endofpacket
	wire          test_pipeline_avm_m0_agent_cp_valid;                                               // Test_PipeLine_avm_m0_agent:cp_valid -> router:sink_valid
	wire  [119:0] test_pipeline_avm_m0_agent_cp_data;                                                // Test_PipeLine_avm_m0_agent:cp_data -> router:sink_data
	wire          test_pipeline_avm_m0_agent_cp_ready;                                               // router:sink_ready -> Test_PipeLine_avm_m0_agent:cp_ready
	wire          test_pipeline_avm_m0_agent_cp_startofpacket;                                       // Test_PipeLine_avm_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          test_pipeline_avm_m0_agent_cp_endofpacket;                                         // Test_PipeLine_avm_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                  // router:src_valid -> cmd_demux:sink_valid
	wire  [119:0] router_src_data;                                                                   // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                  // cmd_demux:sink_ready -> router:src_ready
	wire    [8:0] router_src_channel;                                                                // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                          // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                            // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          niosii_core_data_master_agent_cp_valid;                                            // niosII_core_data_master_agent:cp_valid -> router_001:sink_valid
	wire  [119:0] niosii_core_data_master_agent_cp_data;                                             // niosII_core_data_master_agent:cp_data -> router_001:sink_data
	wire          niosii_core_data_master_agent_cp_ready;                                            // router_001:sink_ready -> niosII_core_data_master_agent:cp_ready
	wire          niosii_core_data_master_agent_cp_startofpacket;                                    // niosII_core_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          niosii_core_data_master_agent_cp_endofpacket;                                      // niosII_core_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          niosii_core_instruction_master_agent_cp_valid;                                     // niosII_core_instruction_master_agent:cp_valid -> router_002:sink_valid
	wire  [119:0] niosii_core_instruction_master_agent_cp_data;                                      // niosII_core_instruction_master_agent:cp_data -> router_002:sink_data
	wire          niosii_core_instruction_master_agent_cp_ready;                                     // router_002:sink_ready -> niosII_core_instruction_master_agent:cp_ready
	wire          niosii_core_instruction_master_agent_cp_startofpacket;                             // niosII_core_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
	wire          niosii_core_instruction_master_agent_cp_endofpacket;                               // niosII_core_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
	wire          sdram_s1_agent_rp_valid;                                                           // SDRAM_s1_agent:rp_valid -> router_003:sink_valid
	wire  [101:0] sdram_s1_agent_rp_data;                                                            // SDRAM_s1_agent:rp_data -> router_003:sink_data
	wire          sdram_s1_agent_rp_ready;                                                           // router_003:sink_ready -> SDRAM_s1_agent:rp_ready
	wire          sdram_s1_agent_rp_startofpacket;                                                   // SDRAM_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          sdram_s1_agent_rp_endofpacket;                                                     // SDRAM_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          niosii_core_debug_mem_slave_agent_rp_valid;                                        // niosII_core_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
	wire  [119:0] niosii_core_debug_mem_slave_agent_rp_data;                                         // niosII_core_debug_mem_slave_agent:rp_data -> router_004:sink_data
	wire          niosii_core_debug_mem_slave_agent_rp_ready;                                        // router_004:sink_ready -> niosII_core_debug_mem_slave_agent:rp_ready
	wire          niosii_core_debug_mem_slave_agent_rp_startofpacket;                                // niosII_core_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          niosii_core_debug_mem_slave_agent_rp_endofpacket;                                  // niosII_core_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                              // router_004:src_valid -> rsp_demux_001:sink_valid
	wire  [119:0] router_004_src_data;                                                               // router_004:src_data -> rsp_demux_001:sink_data
	wire          router_004_src_ready;                                                              // rsp_demux_001:sink_ready -> router_004:src_ready
	wire    [8:0] router_004_src_channel;                                                            // router_004:src_channel -> rsp_demux_001:sink_channel
	wire          router_004_src_startofpacket;                                                      // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_004_src_endofpacket;                                                        // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          sram_s1_agent_rp_valid;                                                            // SRAM_s1_agent:rp_valid -> router_005:sink_valid
	wire  [119:0] sram_s1_agent_rp_data;                                                             // SRAM_s1_agent:rp_data -> router_005:sink_data
	wire          sram_s1_agent_rp_ready;                                                            // router_005:sink_ready -> SRAM_s1_agent:rp_ready
	wire          sram_s1_agent_rp_startofpacket;                                                    // SRAM_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          sram_s1_agent_rp_endofpacket;                                                      // SRAM_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                              // router_005:src_valid -> rsp_demux_002:sink_valid
	wire  [119:0] router_005_src_data;                                                               // router_005:src_data -> rsp_demux_002:sink_data
	wire          router_005_src_ready;                                                              // rsp_demux_002:sink_ready -> router_005:src_ready
	wire    [8:0] router_005_src_channel;                                                            // router_005:src_channel -> rsp_demux_002:sink_channel
	wire          router_005_src_startofpacket;                                                      // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_005_src_endofpacket;                                                        // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          jtag_avalon_jtag_slave_agent_rp_valid;                                             // JTAG_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
	wire  [119:0] jtag_avalon_jtag_slave_agent_rp_data;                                              // JTAG_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
	wire          jtag_avalon_jtag_slave_agent_rp_ready;                                             // router_006:sink_ready -> JTAG_avalon_jtag_slave_agent:rp_ready
	wire          jtag_avalon_jtag_slave_agent_rp_startofpacket;                                     // JTAG_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          jtag_avalon_jtag_slave_agent_rp_endofpacket;                                       // JTAG_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                              // router_006:src_valid -> rsp_demux_003:sink_valid
	wire  [119:0] router_006_src_data;                                                               // router_006:src_data -> rsp_demux_003:sink_data
	wire          router_006_src_ready;                                                              // rsp_demux_003:sink_ready -> router_006:src_ready
	wire    [8:0] router_006_src_channel;                                                            // router_006:src_channel -> rsp_demux_003:sink_channel
	wire          router_006_src_startofpacket;                                                      // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_006_src_endofpacket;                                                        // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          uart_com_avalon_rs232_slave_agent_rp_valid;                                        // UART_COM_avalon_rs232_slave_agent:rp_valid -> router_007:sink_valid
	wire  [119:0] uart_com_avalon_rs232_slave_agent_rp_data;                                         // UART_COM_avalon_rs232_slave_agent:rp_data -> router_007:sink_data
	wire          uart_com_avalon_rs232_slave_agent_rp_ready;                                        // router_007:sink_ready -> UART_COM_avalon_rs232_slave_agent:rp_ready
	wire          uart_com_avalon_rs232_slave_agent_rp_startofpacket;                                // UART_COM_avalon_rs232_slave_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          uart_com_avalon_rs232_slave_agent_rp_endofpacket;                                  // UART_COM_avalon_rs232_slave_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                              // router_007:src_valid -> rsp_demux_004:sink_valid
	wire  [119:0] router_007_src_data;                                                               // router_007:src_data -> rsp_demux_004:sink_data
	wire          router_007_src_ready;                                                              // rsp_demux_004:sink_ready -> router_007:src_ready
	wire    [8:0] router_007_src_channel;                                                            // router_007:src_channel -> rsp_demux_004:sink_channel
	wire          router_007_src_startofpacket;                                                      // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_007_src_endofpacket;                                                        // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          convolution_slave_avs_s0_agent_rp_valid;                                           // convolution_slave_avs_s0_agent:rp_valid -> router_008:sink_valid
	wire  [119:0] convolution_slave_avs_s0_agent_rp_data;                                            // convolution_slave_avs_s0_agent:rp_data -> router_008:sink_data
	wire          convolution_slave_avs_s0_agent_rp_ready;                                           // router_008:sink_ready -> convolution_slave_avs_s0_agent:rp_ready
	wire          convolution_slave_avs_s0_agent_rp_startofpacket;                                   // convolution_slave_avs_s0_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          convolution_slave_avs_s0_agent_rp_endofpacket;                                     // convolution_slave_avs_s0_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                                              // router_008:src_valid -> rsp_demux_005:sink_valid
	wire  [119:0] router_008_src_data;                                                               // router_008:src_data -> rsp_demux_005:sink_data
	wire          router_008_src_ready;                                                              // rsp_demux_005:sink_ready -> router_008:src_ready
	wire    [8:0] router_008_src_channel;                                                            // router_008:src_channel -> rsp_demux_005:sink_channel
	wire          router_008_src_startofpacket;                                                      // router_008:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_008_src_endofpacket;                                                        // router_008:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          test_pipeline_avs_s0_agent_rp_valid;                                               // Test_PipeLine_avs_s0_agent:rp_valid -> router_009:sink_valid
	wire  [119:0] test_pipeline_avs_s0_agent_rp_data;                                                // Test_PipeLine_avs_s0_agent:rp_data -> router_009:sink_data
	wire          test_pipeline_avs_s0_agent_rp_ready;                                               // router_009:sink_ready -> Test_PipeLine_avs_s0_agent:rp_ready
	wire          test_pipeline_avs_s0_agent_rp_startofpacket;                                       // Test_PipeLine_avs_s0_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire          test_pipeline_avs_s0_agent_rp_endofpacket;                                         // Test_PipeLine_avs_s0_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire          router_009_src_valid;                                                              // router_009:src_valid -> rsp_demux_006:sink_valid
	wire  [119:0] router_009_src_data;                                                               // router_009:src_data -> rsp_demux_006:sink_data
	wire          router_009_src_ready;                                                              // rsp_demux_006:sink_ready -> router_009:src_ready
	wire    [8:0] router_009_src_channel;                                                            // router_009:src_channel -> rsp_demux_006:sink_channel
	wire          router_009_src_startofpacket;                                                      // router_009:src_startofpacket -> rsp_demux_006:sink_startofpacket
	wire          router_009_src_endofpacket;                                                        // router_009:src_endofpacket -> rsp_demux_006:sink_endofpacket
	wire          systemid_control_slave_agent_rp_valid;                                             // SystemID_control_slave_agent:rp_valid -> router_010:sink_valid
	wire  [119:0] systemid_control_slave_agent_rp_data;                                              // SystemID_control_slave_agent:rp_data -> router_010:sink_data
	wire          systemid_control_slave_agent_rp_ready;                                             // router_010:sink_ready -> SystemID_control_slave_agent:rp_ready
	wire          systemid_control_slave_agent_rp_startofpacket;                                     // SystemID_control_slave_agent:rp_startofpacket -> router_010:sink_startofpacket
	wire          systemid_control_slave_agent_rp_endofpacket;                                       // SystemID_control_slave_agent:rp_endofpacket -> router_010:sink_endofpacket
	wire          router_010_src_valid;                                                              // router_010:src_valid -> rsp_demux_007:sink_valid
	wire  [119:0] router_010_src_data;                                                               // router_010:src_data -> rsp_demux_007:sink_data
	wire          router_010_src_ready;                                                              // rsp_demux_007:sink_ready -> router_010:src_ready
	wire    [8:0] router_010_src_channel;                                                            // router_010:src_channel -> rsp_demux_007:sink_channel
	wire          router_010_src_startofpacket;                                                      // router_010:src_startofpacket -> rsp_demux_007:sink_startofpacket
	wire          router_010_src_endofpacket;                                                        // router_010:src_endofpacket -> rsp_demux_007:sink_endofpacket
	wire          sys_timer_s1_agent_rp_valid;                                                       // Sys_Timer_s1_agent:rp_valid -> router_011:sink_valid
	wire  [119:0] sys_timer_s1_agent_rp_data;                                                        // Sys_Timer_s1_agent:rp_data -> router_011:sink_data
	wire          sys_timer_s1_agent_rp_ready;                                                       // router_011:sink_ready -> Sys_Timer_s1_agent:rp_ready
	wire          sys_timer_s1_agent_rp_startofpacket;                                               // Sys_Timer_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
	wire          sys_timer_s1_agent_rp_endofpacket;                                                 // Sys_Timer_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
	wire          router_011_src_valid;                                                              // router_011:src_valid -> rsp_demux_008:sink_valid
	wire  [119:0] router_011_src_data;                                                               // router_011:src_data -> rsp_demux_008:sink_data
	wire          router_011_src_ready;                                                              // rsp_demux_008:sink_ready -> router_011:src_ready
	wire    [8:0] router_011_src_channel;                                                            // router_011:src_channel -> rsp_demux_008:sink_channel
	wire          router_011_src_startofpacket;                                                      // router_011:src_startofpacket -> rsp_demux_008:sink_startofpacket
	wire          router_011_src_endofpacket;                                                        // router_011:src_endofpacket -> rsp_demux_008:sink_endofpacket
	wire          router_001_src_valid;                                                              // router_001:src_valid -> niosII_core_data_master_limiter:cmd_sink_valid
	wire  [119:0] router_001_src_data;                                                               // router_001:src_data -> niosII_core_data_master_limiter:cmd_sink_data
	wire          router_001_src_ready;                                                              // niosII_core_data_master_limiter:cmd_sink_ready -> router_001:src_ready
	wire    [8:0] router_001_src_channel;                                                            // router_001:src_channel -> niosII_core_data_master_limiter:cmd_sink_channel
	wire          router_001_src_startofpacket;                                                      // router_001:src_startofpacket -> niosII_core_data_master_limiter:cmd_sink_startofpacket
	wire          router_001_src_endofpacket;                                                        // router_001:src_endofpacket -> niosII_core_data_master_limiter:cmd_sink_endofpacket
	wire  [119:0] niosii_core_data_master_limiter_cmd_src_data;                                      // niosII_core_data_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
	wire          niosii_core_data_master_limiter_cmd_src_ready;                                     // cmd_demux_001:sink_ready -> niosII_core_data_master_limiter:cmd_src_ready
	wire    [8:0] niosii_core_data_master_limiter_cmd_src_channel;                                   // niosII_core_data_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
	wire          niosii_core_data_master_limiter_cmd_src_startofpacket;                             // niosII_core_data_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          niosii_core_data_master_limiter_cmd_src_endofpacket;                               // niosII_core_data_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          rsp_mux_001_src_valid;                                                             // rsp_mux_001:src_valid -> niosII_core_data_master_limiter:rsp_sink_valid
	wire  [119:0] rsp_mux_001_src_data;                                                              // rsp_mux_001:src_data -> niosII_core_data_master_limiter:rsp_sink_data
	wire          rsp_mux_001_src_ready;                                                             // niosII_core_data_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
	wire    [8:0] rsp_mux_001_src_channel;                                                           // rsp_mux_001:src_channel -> niosII_core_data_master_limiter:rsp_sink_channel
	wire          rsp_mux_001_src_startofpacket;                                                     // rsp_mux_001:src_startofpacket -> niosII_core_data_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                       // rsp_mux_001:src_endofpacket -> niosII_core_data_master_limiter:rsp_sink_endofpacket
	wire          niosii_core_data_master_limiter_rsp_src_valid;                                     // niosII_core_data_master_limiter:rsp_src_valid -> niosII_core_data_master_agent:rp_valid
	wire  [119:0] niosii_core_data_master_limiter_rsp_src_data;                                      // niosII_core_data_master_limiter:rsp_src_data -> niosII_core_data_master_agent:rp_data
	wire          niosii_core_data_master_limiter_rsp_src_ready;                                     // niosII_core_data_master_agent:rp_ready -> niosII_core_data_master_limiter:rsp_src_ready
	wire    [8:0] niosii_core_data_master_limiter_rsp_src_channel;                                   // niosII_core_data_master_limiter:rsp_src_channel -> niosII_core_data_master_agent:rp_channel
	wire          niosii_core_data_master_limiter_rsp_src_startofpacket;                             // niosII_core_data_master_limiter:rsp_src_startofpacket -> niosII_core_data_master_agent:rp_startofpacket
	wire          niosii_core_data_master_limiter_rsp_src_endofpacket;                               // niosII_core_data_master_limiter:rsp_src_endofpacket -> niosII_core_data_master_agent:rp_endofpacket
	wire          router_002_src_valid;                                                              // router_002:src_valid -> niosII_core_instruction_master_limiter:cmd_sink_valid
	wire  [119:0] router_002_src_data;                                                               // router_002:src_data -> niosII_core_instruction_master_limiter:cmd_sink_data
	wire          router_002_src_ready;                                                              // niosII_core_instruction_master_limiter:cmd_sink_ready -> router_002:src_ready
	wire    [8:0] router_002_src_channel;                                                            // router_002:src_channel -> niosII_core_instruction_master_limiter:cmd_sink_channel
	wire          router_002_src_startofpacket;                                                      // router_002:src_startofpacket -> niosII_core_instruction_master_limiter:cmd_sink_startofpacket
	wire          router_002_src_endofpacket;                                                        // router_002:src_endofpacket -> niosII_core_instruction_master_limiter:cmd_sink_endofpacket
	wire  [119:0] niosii_core_instruction_master_limiter_cmd_src_data;                               // niosII_core_instruction_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
	wire          niosii_core_instruction_master_limiter_cmd_src_ready;                              // cmd_demux_002:sink_ready -> niosII_core_instruction_master_limiter:cmd_src_ready
	wire    [8:0] niosii_core_instruction_master_limiter_cmd_src_channel;                            // niosII_core_instruction_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
	wire          niosii_core_instruction_master_limiter_cmd_src_startofpacket;                      // niosII_core_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          niosii_core_instruction_master_limiter_cmd_src_endofpacket;                        // niosII_core_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          rsp_mux_002_src_valid;                                                             // rsp_mux_002:src_valid -> niosII_core_instruction_master_limiter:rsp_sink_valid
	wire  [119:0] rsp_mux_002_src_data;                                                              // rsp_mux_002:src_data -> niosII_core_instruction_master_limiter:rsp_sink_data
	wire          rsp_mux_002_src_ready;                                                             // niosII_core_instruction_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
	wire    [8:0] rsp_mux_002_src_channel;                                                           // rsp_mux_002:src_channel -> niosII_core_instruction_master_limiter:rsp_sink_channel
	wire          rsp_mux_002_src_startofpacket;                                                     // rsp_mux_002:src_startofpacket -> niosII_core_instruction_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                       // rsp_mux_002:src_endofpacket -> niosII_core_instruction_master_limiter:rsp_sink_endofpacket
	wire          niosii_core_instruction_master_limiter_rsp_src_valid;                              // niosII_core_instruction_master_limiter:rsp_src_valid -> niosII_core_instruction_master_agent:rp_valid
	wire  [119:0] niosii_core_instruction_master_limiter_rsp_src_data;                               // niosII_core_instruction_master_limiter:rsp_src_data -> niosII_core_instruction_master_agent:rp_data
	wire          niosii_core_instruction_master_limiter_rsp_src_ready;                              // niosII_core_instruction_master_agent:rp_ready -> niosII_core_instruction_master_limiter:rsp_src_ready
	wire    [8:0] niosii_core_instruction_master_limiter_rsp_src_channel;                            // niosII_core_instruction_master_limiter:rsp_src_channel -> niosII_core_instruction_master_agent:rp_channel
	wire          niosii_core_instruction_master_limiter_rsp_src_startofpacket;                      // niosII_core_instruction_master_limiter:rsp_src_startofpacket -> niosII_core_instruction_master_agent:rp_startofpacket
	wire          niosii_core_instruction_master_limiter_rsp_src_endofpacket;                        // niosII_core_instruction_master_limiter:rsp_src_endofpacket -> niosII_core_instruction_master_agent:rp_endofpacket
	wire          sdram_s1_burst_adapter_source0_valid;                                              // SDRAM_s1_burst_adapter:source0_valid -> SDRAM_s1_agent:cp_valid
	wire  [101:0] sdram_s1_burst_adapter_source0_data;                                               // SDRAM_s1_burst_adapter:source0_data -> SDRAM_s1_agent:cp_data
	wire          sdram_s1_burst_adapter_source0_ready;                                              // SDRAM_s1_agent:cp_ready -> SDRAM_s1_burst_adapter:source0_ready
	wire    [8:0] sdram_s1_burst_adapter_source0_channel;                                            // SDRAM_s1_burst_adapter:source0_channel -> SDRAM_s1_agent:cp_channel
	wire          sdram_s1_burst_adapter_source0_startofpacket;                                      // SDRAM_s1_burst_adapter:source0_startofpacket -> SDRAM_s1_agent:cp_startofpacket
	wire          sdram_s1_burst_adapter_source0_endofpacket;                                        // SDRAM_s1_burst_adapter:source0_endofpacket -> SDRAM_s1_agent:cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                             // cmd_mux_001:src_valid -> niosII_core_debug_mem_slave_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_001_src_data;                                                              // cmd_mux_001:src_data -> niosII_core_debug_mem_slave_burst_adapter:sink0_data
	wire          cmd_mux_001_src_ready;                                                             // niosII_core_debug_mem_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire    [8:0] cmd_mux_001_src_channel;                                                           // cmd_mux_001:src_channel -> niosII_core_debug_mem_slave_burst_adapter:sink0_channel
	wire          cmd_mux_001_src_startofpacket;                                                     // cmd_mux_001:src_startofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                       // cmd_mux_001:src_endofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_endofpacket
	wire          niosii_core_debug_mem_slave_burst_adapter_source0_valid;                           // niosII_core_debug_mem_slave_burst_adapter:source0_valid -> niosII_core_debug_mem_slave_agent:cp_valid
	wire  [119:0] niosii_core_debug_mem_slave_burst_adapter_source0_data;                            // niosII_core_debug_mem_slave_burst_adapter:source0_data -> niosII_core_debug_mem_slave_agent:cp_data
	wire          niosii_core_debug_mem_slave_burst_adapter_source0_ready;                           // niosII_core_debug_mem_slave_agent:cp_ready -> niosII_core_debug_mem_slave_burst_adapter:source0_ready
	wire    [8:0] niosii_core_debug_mem_slave_burst_adapter_source0_channel;                         // niosII_core_debug_mem_slave_burst_adapter:source0_channel -> niosII_core_debug_mem_slave_agent:cp_channel
	wire          niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket;                   // niosII_core_debug_mem_slave_burst_adapter:source0_startofpacket -> niosII_core_debug_mem_slave_agent:cp_startofpacket
	wire          niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket;                     // niosII_core_debug_mem_slave_burst_adapter:source0_endofpacket -> niosII_core_debug_mem_slave_agent:cp_endofpacket
	wire          cmd_mux_002_src_valid;                                                             // cmd_mux_002:src_valid -> SRAM_s1_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_002_src_data;                                                              // cmd_mux_002:src_data -> SRAM_s1_burst_adapter:sink0_data
	wire          cmd_mux_002_src_ready;                                                             // SRAM_s1_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
	wire    [8:0] cmd_mux_002_src_channel;                                                           // cmd_mux_002:src_channel -> SRAM_s1_burst_adapter:sink0_channel
	wire          cmd_mux_002_src_startofpacket;                                                     // cmd_mux_002:src_startofpacket -> SRAM_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                       // cmd_mux_002:src_endofpacket -> SRAM_s1_burst_adapter:sink0_endofpacket
	wire          sram_s1_burst_adapter_source0_valid;                                               // SRAM_s1_burst_adapter:source0_valid -> SRAM_s1_agent:cp_valid
	wire  [119:0] sram_s1_burst_adapter_source0_data;                                                // SRAM_s1_burst_adapter:source0_data -> SRAM_s1_agent:cp_data
	wire          sram_s1_burst_adapter_source0_ready;                                               // SRAM_s1_agent:cp_ready -> SRAM_s1_burst_adapter:source0_ready
	wire    [8:0] sram_s1_burst_adapter_source0_channel;                                             // SRAM_s1_burst_adapter:source0_channel -> SRAM_s1_agent:cp_channel
	wire          sram_s1_burst_adapter_source0_startofpacket;                                       // SRAM_s1_burst_adapter:source0_startofpacket -> SRAM_s1_agent:cp_startofpacket
	wire          sram_s1_burst_adapter_source0_endofpacket;                                         // SRAM_s1_burst_adapter:source0_endofpacket -> SRAM_s1_agent:cp_endofpacket
	wire          cmd_mux_003_src_valid;                                                             // cmd_mux_003:src_valid -> JTAG_avalon_jtag_slave_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_003_src_data;                                                              // cmd_mux_003:src_data -> JTAG_avalon_jtag_slave_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                                             // JTAG_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire    [8:0] cmd_mux_003_src_channel;                                                           // cmd_mux_003:src_channel -> JTAG_avalon_jtag_slave_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                                                     // cmd_mux_003:src_startofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                       // cmd_mux_003:src_endofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_endofpacket
	wire          jtag_avalon_jtag_slave_burst_adapter_source0_valid;                                // JTAG_avalon_jtag_slave_burst_adapter:source0_valid -> JTAG_avalon_jtag_slave_agent:cp_valid
	wire  [119:0] jtag_avalon_jtag_slave_burst_adapter_source0_data;                                 // JTAG_avalon_jtag_slave_burst_adapter:source0_data -> JTAG_avalon_jtag_slave_agent:cp_data
	wire          jtag_avalon_jtag_slave_burst_adapter_source0_ready;                                // JTAG_avalon_jtag_slave_agent:cp_ready -> JTAG_avalon_jtag_slave_burst_adapter:source0_ready
	wire    [8:0] jtag_avalon_jtag_slave_burst_adapter_source0_channel;                              // JTAG_avalon_jtag_slave_burst_adapter:source0_channel -> JTAG_avalon_jtag_slave_agent:cp_channel
	wire          jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket;                        // JTAG_avalon_jtag_slave_burst_adapter:source0_startofpacket -> JTAG_avalon_jtag_slave_agent:cp_startofpacket
	wire          jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket;                          // JTAG_avalon_jtag_slave_burst_adapter:source0_endofpacket -> JTAG_avalon_jtag_slave_agent:cp_endofpacket
	wire          cmd_mux_004_src_valid;                                                             // cmd_mux_004:src_valid -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_004_src_data;                                                              // cmd_mux_004:src_data -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_data
	wire          cmd_mux_004_src_ready;                                                             // UART_COM_avalon_rs232_slave_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
	wire    [8:0] cmd_mux_004_src_channel;                                                           // cmd_mux_004:src_channel -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_channel
	wire          cmd_mux_004_src_startofpacket;                                                     // cmd_mux_004:src_startofpacket -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                                       // cmd_mux_004:src_endofpacket -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_endofpacket
	wire          uart_com_avalon_rs232_slave_burst_adapter_source0_valid;                           // UART_COM_avalon_rs232_slave_burst_adapter:source0_valid -> UART_COM_avalon_rs232_slave_agent:cp_valid
	wire  [119:0] uart_com_avalon_rs232_slave_burst_adapter_source0_data;                            // UART_COM_avalon_rs232_slave_burst_adapter:source0_data -> UART_COM_avalon_rs232_slave_agent:cp_data
	wire          uart_com_avalon_rs232_slave_burst_adapter_source0_ready;                           // UART_COM_avalon_rs232_slave_agent:cp_ready -> UART_COM_avalon_rs232_slave_burst_adapter:source0_ready
	wire    [8:0] uart_com_avalon_rs232_slave_burst_adapter_source0_channel;                         // UART_COM_avalon_rs232_slave_burst_adapter:source0_channel -> UART_COM_avalon_rs232_slave_agent:cp_channel
	wire          uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket;                   // UART_COM_avalon_rs232_slave_burst_adapter:source0_startofpacket -> UART_COM_avalon_rs232_slave_agent:cp_startofpacket
	wire          uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket;                     // UART_COM_avalon_rs232_slave_burst_adapter:source0_endofpacket -> UART_COM_avalon_rs232_slave_agent:cp_endofpacket
	wire          cmd_mux_005_src_valid;                                                             // cmd_mux_005:src_valid -> convolution_slave_avs_s0_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_005_src_data;                                                              // cmd_mux_005:src_data -> convolution_slave_avs_s0_burst_adapter:sink0_data
	wire          cmd_mux_005_src_ready;                                                             // convolution_slave_avs_s0_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
	wire    [8:0] cmd_mux_005_src_channel;                                                           // cmd_mux_005:src_channel -> convolution_slave_avs_s0_burst_adapter:sink0_channel
	wire          cmd_mux_005_src_startofpacket;                                                     // cmd_mux_005:src_startofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                                       // cmd_mux_005:src_endofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_endofpacket
	wire          convolution_slave_avs_s0_burst_adapter_source0_valid;                              // convolution_slave_avs_s0_burst_adapter:source0_valid -> convolution_slave_avs_s0_agent:cp_valid
	wire  [119:0] convolution_slave_avs_s0_burst_adapter_source0_data;                               // convolution_slave_avs_s0_burst_adapter:source0_data -> convolution_slave_avs_s0_agent:cp_data
	wire          convolution_slave_avs_s0_burst_adapter_source0_ready;                              // convolution_slave_avs_s0_agent:cp_ready -> convolution_slave_avs_s0_burst_adapter:source0_ready
	wire    [8:0] convolution_slave_avs_s0_burst_adapter_source0_channel;                            // convolution_slave_avs_s0_burst_adapter:source0_channel -> convolution_slave_avs_s0_agent:cp_channel
	wire          convolution_slave_avs_s0_burst_adapter_source0_startofpacket;                      // convolution_slave_avs_s0_burst_adapter:source0_startofpacket -> convolution_slave_avs_s0_agent:cp_startofpacket
	wire          convolution_slave_avs_s0_burst_adapter_source0_endofpacket;                        // convolution_slave_avs_s0_burst_adapter:source0_endofpacket -> convolution_slave_avs_s0_agent:cp_endofpacket
	wire          cmd_mux_006_src_valid;                                                             // cmd_mux_006:src_valid -> Test_PipeLine_avs_s0_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_006_src_data;                                                              // cmd_mux_006:src_data -> Test_PipeLine_avs_s0_burst_adapter:sink0_data
	wire          cmd_mux_006_src_ready;                                                             // Test_PipeLine_avs_s0_burst_adapter:sink0_ready -> cmd_mux_006:src_ready
	wire    [8:0] cmd_mux_006_src_channel;                                                           // cmd_mux_006:src_channel -> Test_PipeLine_avs_s0_burst_adapter:sink0_channel
	wire          cmd_mux_006_src_startofpacket;                                                     // cmd_mux_006:src_startofpacket -> Test_PipeLine_avs_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_006_src_endofpacket;                                                       // cmd_mux_006:src_endofpacket -> Test_PipeLine_avs_s0_burst_adapter:sink0_endofpacket
	wire          test_pipeline_avs_s0_burst_adapter_source0_valid;                                  // Test_PipeLine_avs_s0_burst_adapter:source0_valid -> Test_PipeLine_avs_s0_agent:cp_valid
	wire  [119:0] test_pipeline_avs_s0_burst_adapter_source0_data;                                   // Test_PipeLine_avs_s0_burst_adapter:source0_data -> Test_PipeLine_avs_s0_agent:cp_data
	wire          test_pipeline_avs_s0_burst_adapter_source0_ready;                                  // Test_PipeLine_avs_s0_agent:cp_ready -> Test_PipeLine_avs_s0_burst_adapter:source0_ready
	wire    [8:0] test_pipeline_avs_s0_burst_adapter_source0_channel;                                // Test_PipeLine_avs_s0_burst_adapter:source0_channel -> Test_PipeLine_avs_s0_agent:cp_channel
	wire          test_pipeline_avs_s0_burst_adapter_source0_startofpacket;                          // Test_PipeLine_avs_s0_burst_adapter:source0_startofpacket -> Test_PipeLine_avs_s0_agent:cp_startofpacket
	wire          test_pipeline_avs_s0_burst_adapter_source0_endofpacket;                            // Test_PipeLine_avs_s0_burst_adapter:source0_endofpacket -> Test_PipeLine_avs_s0_agent:cp_endofpacket
	wire          cmd_mux_007_src_valid;                                                             // cmd_mux_007:src_valid -> SystemID_control_slave_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_007_src_data;                                                              // cmd_mux_007:src_data -> SystemID_control_slave_burst_adapter:sink0_data
	wire          cmd_mux_007_src_ready;                                                             // SystemID_control_slave_burst_adapter:sink0_ready -> cmd_mux_007:src_ready
	wire    [8:0] cmd_mux_007_src_channel;                                                           // cmd_mux_007:src_channel -> SystemID_control_slave_burst_adapter:sink0_channel
	wire          cmd_mux_007_src_startofpacket;                                                     // cmd_mux_007:src_startofpacket -> SystemID_control_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_007_src_endofpacket;                                                       // cmd_mux_007:src_endofpacket -> SystemID_control_slave_burst_adapter:sink0_endofpacket
	wire          systemid_control_slave_burst_adapter_source0_valid;                                // SystemID_control_slave_burst_adapter:source0_valid -> SystemID_control_slave_agent:cp_valid
	wire  [119:0] systemid_control_slave_burst_adapter_source0_data;                                 // SystemID_control_slave_burst_adapter:source0_data -> SystemID_control_slave_agent:cp_data
	wire          systemid_control_slave_burst_adapter_source0_ready;                                // SystemID_control_slave_agent:cp_ready -> SystemID_control_slave_burst_adapter:source0_ready
	wire    [8:0] systemid_control_slave_burst_adapter_source0_channel;                              // SystemID_control_slave_burst_adapter:source0_channel -> SystemID_control_slave_agent:cp_channel
	wire          systemid_control_slave_burst_adapter_source0_startofpacket;                        // SystemID_control_slave_burst_adapter:source0_startofpacket -> SystemID_control_slave_agent:cp_startofpacket
	wire          systemid_control_slave_burst_adapter_source0_endofpacket;                          // SystemID_control_slave_burst_adapter:source0_endofpacket -> SystemID_control_slave_agent:cp_endofpacket
	wire          cmd_mux_008_src_valid;                                                             // cmd_mux_008:src_valid -> Sys_Timer_s1_burst_adapter:sink0_valid
	wire  [119:0] cmd_mux_008_src_data;                                                              // cmd_mux_008:src_data -> Sys_Timer_s1_burst_adapter:sink0_data
	wire          cmd_mux_008_src_ready;                                                             // Sys_Timer_s1_burst_adapter:sink0_ready -> cmd_mux_008:src_ready
	wire    [8:0] cmd_mux_008_src_channel;                                                           // cmd_mux_008:src_channel -> Sys_Timer_s1_burst_adapter:sink0_channel
	wire          cmd_mux_008_src_startofpacket;                                                     // cmd_mux_008:src_startofpacket -> Sys_Timer_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_008_src_endofpacket;                                                       // cmd_mux_008:src_endofpacket -> Sys_Timer_s1_burst_adapter:sink0_endofpacket
	wire          sys_timer_s1_burst_adapter_source0_valid;                                          // Sys_Timer_s1_burst_adapter:source0_valid -> Sys_Timer_s1_agent:cp_valid
	wire  [119:0] sys_timer_s1_burst_adapter_source0_data;                                           // Sys_Timer_s1_burst_adapter:source0_data -> Sys_Timer_s1_agent:cp_data
	wire          sys_timer_s1_burst_adapter_source0_ready;                                          // Sys_Timer_s1_agent:cp_ready -> Sys_Timer_s1_burst_adapter:source0_ready
	wire    [8:0] sys_timer_s1_burst_adapter_source0_channel;                                        // Sys_Timer_s1_burst_adapter:source0_channel -> Sys_Timer_s1_agent:cp_channel
	wire          sys_timer_s1_burst_adapter_source0_startofpacket;                                  // Sys_Timer_s1_burst_adapter:source0_startofpacket -> Sys_Timer_s1_agent:cp_startofpacket
	wire          sys_timer_s1_burst_adapter_source0_endofpacket;                                    // Sys_Timer_s1_burst_adapter:source0_endofpacket -> Sys_Timer_s1_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                              // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [119:0] cmd_demux_src0_data;                                                               // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                              // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [8:0] cmd_demux_src0_channel;                                                            // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                      // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                        // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                          // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [119:0] cmd_demux_001_src0_data;                                                           // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                                          // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire    [8:0] cmd_demux_001_src0_channel;                                                        // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                                  // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                    // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_001_src1_valid;                                                          // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
	wire  [119:0] cmd_demux_001_src1_data;                                                           // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_001_src1_ready;                                                          // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
	wire    [8:0] cmd_demux_001_src1_channel;                                                        // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_001_src1_startofpacket;                                                  // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                                    // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_001_src2_valid;                                                          // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
	wire  [119:0] cmd_demux_001_src2_data;                                                           // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_001_src2_ready;                                                          // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
	wire    [8:0] cmd_demux_001_src2_channel;                                                        // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_001_src2_startofpacket;                                                  // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                                    // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_001_src3_valid;                                                          // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
	wire  [119:0] cmd_demux_001_src3_data;                                                           // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_001_src3_ready;                                                          // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
	wire    [8:0] cmd_demux_001_src3_channel;                                                        // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_001_src3_startofpacket;                                                  // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_001_src3_endofpacket;                                                    // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_001_src4_valid;                                                          // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
	wire  [119:0] cmd_demux_001_src4_data;                                                           // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_001_src4_ready;                                                          // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
	wire    [8:0] cmd_demux_001_src4_channel;                                                        // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_001_src4_startofpacket;                                                  // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_001_src4_endofpacket;                                                    // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_001_src5_valid;                                                          // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
	wire  [119:0] cmd_demux_001_src5_data;                                                           // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_001_src5_ready;                                                          // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
	wire    [8:0] cmd_demux_001_src5_channel;                                                        // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_001_src5_startofpacket;                                                  // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_001_src5_endofpacket;                                                    // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_001_src6_valid;                                                          // cmd_demux_001:src6_valid -> cmd_mux_006:sink0_valid
	wire  [119:0] cmd_demux_001_src6_data;                                                           // cmd_demux_001:src6_data -> cmd_mux_006:sink0_data
	wire          cmd_demux_001_src6_ready;                                                          // cmd_mux_006:sink0_ready -> cmd_demux_001:src6_ready
	wire    [8:0] cmd_demux_001_src6_channel;                                                        // cmd_demux_001:src6_channel -> cmd_mux_006:sink0_channel
	wire          cmd_demux_001_src6_startofpacket;                                                  // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	wire          cmd_demux_001_src6_endofpacket;                                                    // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	wire          cmd_demux_001_src7_valid;                                                          // cmd_demux_001:src7_valid -> cmd_mux_007:sink0_valid
	wire  [119:0] cmd_demux_001_src7_data;                                                           // cmd_demux_001:src7_data -> cmd_mux_007:sink0_data
	wire          cmd_demux_001_src7_ready;                                                          // cmd_mux_007:sink0_ready -> cmd_demux_001:src7_ready
	wire    [8:0] cmd_demux_001_src7_channel;                                                        // cmd_demux_001:src7_channel -> cmd_mux_007:sink0_channel
	wire          cmd_demux_001_src7_startofpacket;                                                  // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
	wire          cmd_demux_001_src7_endofpacket;                                                    // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
	wire          cmd_demux_001_src8_valid;                                                          // cmd_demux_001:src8_valid -> cmd_mux_008:sink0_valid
	wire  [119:0] cmd_demux_001_src8_data;                                                           // cmd_demux_001:src8_data -> cmd_mux_008:sink0_data
	wire          cmd_demux_001_src8_ready;                                                          // cmd_mux_008:sink0_ready -> cmd_demux_001:src8_ready
	wire    [8:0] cmd_demux_001_src8_channel;                                                        // cmd_demux_001:src8_channel -> cmd_mux_008:sink0_channel
	wire          cmd_demux_001_src8_startofpacket;                                                  // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
	wire          cmd_demux_001_src8_endofpacket;                                                    // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
	wire          cmd_demux_002_src0_valid;                                                          // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
	wire  [119:0] cmd_demux_002_src0_data;                                                           // cmd_demux_002:src0_data -> cmd_mux:sink2_data
	wire          cmd_demux_002_src0_ready;                                                          // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
	wire    [8:0] cmd_demux_002_src0_channel;                                                        // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
	wire          cmd_demux_002_src0_startofpacket;                                                  // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                                    // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
	wire          cmd_demux_002_src1_valid;                                                          // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
	wire  [119:0] cmd_demux_002_src1_data;                                                           // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_002_src1_ready;                                                          // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
	wire    [8:0] cmd_demux_002_src1_channel;                                                        // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_002_src1_startofpacket;                                                  // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                                    // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_002_src2_valid;                                                          // cmd_demux_002:src2_valid -> cmd_mux_002:sink1_valid
	wire  [119:0] cmd_demux_002_src2_data;                                                           // cmd_demux_002:src2_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_002_src2_ready;                                                          // cmd_mux_002:sink1_ready -> cmd_demux_002:src2_ready
	wire    [8:0] cmd_demux_002_src2_channel;                                                        // cmd_demux_002:src2_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_002_src2_startofpacket;                                                  // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_002_src2_endofpacket;                                                    // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                              // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [119:0] rsp_demux_src0_data;                                                               // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                              // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [8:0] rsp_demux_src0_channel;                                                            // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                      // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                        // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                              // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [119:0] rsp_demux_src1_data;                                                               // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                                              // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire    [8:0] rsp_demux_src1_channel;                                                            // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                                      // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                        // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_src2_valid;                                                              // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
	wire  [119:0] rsp_demux_src2_data;                                                               // rsp_demux:src2_data -> rsp_mux_002:sink0_data
	wire          rsp_demux_src2_ready;                                                              // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
	wire    [8:0] rsp_demux_src2_channel;                                                            // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
	wire          rsp_demux_src2_startofpacket;                                                      // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          rsp_demux_src2_endofpacket;                                                        // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                          // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
	wire  [119:0] rsp_demux_001_src0_data;                                                           // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_001_src0_ready;                                                          // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
	wire    [8:0] rsp_demux_001_src0_channel;                                                        // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                                  // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                    // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                                          // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
	wire  [119:0] rsp_demux_001_src1_data;                                                           // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_001_src1_ready;                                                          // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
	wire    [8:0] rsp_demux_001_src1_channel;                                                        // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_001_src1_startofpacket;                                                  // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                                    // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                          // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
	wire  [119:0] rsp_demux_002_src0_data;                                                           // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_002_src0_ready;                                                          // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
	wire    [8:0] rsp_demux_002_src0_channel;                                                        // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                                  // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                    // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_002_src1_valid;                                                          // rsp_demux_002:src1_valid -> rsp_mux_002:sink2_valid
	wire  [119:0] rsp_demux_002_src1_data;                                                           // rsp_demux_002:src1_data -> rsp_mux_002:sink2_data
	wire          rsp_demux_002_src1_ready;                                                          // rsp_mux_002:sink2_ready -> rsp_demux_002:src1_ready
	wire    [8:0] rsp_demux_002_src1_channel;                                                        // rsp_demux_002:src1_channel -> rsp_mux_002:sink2_channel
	wire          rsp_demux_002_src1_startofpacket;                                                  // rsp_demux_002:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                                    // rsp_demux_002:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                          // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
	wire  [119:0] rsp_demux_003_src0_data;                                                           // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
	wire          rsp_demux_003_src0_ready;                                                          // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
	wire    [8:0] rsp_demux_003_src0_channel;                                                        // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                                  // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                    // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                                          // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
	wire  [119:0] rsp_demux_004_src0_data;                                                           // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
	wire          rsp_demux_004_src0_ready;                                                          // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
	wire    [8:0] rsp_demux_004_src0_channel;                                                        // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                                  // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                                    // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                                          // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
	wire  [119:0] rsp_demux_005_src0_data;                                                           // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
	wire          rsp_demux_005_src0_ready;                                                          // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
	wire    [8:0] rsp_demux_005_src0_channel;                                                        // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                                                  // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                                    // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
	wire          rsp_demux_006_src0_valid;                                                          // rsp_demux_006:src0_valid -> rsp_mux_001:sink6_valid
	wire  [119:0] rsp_demux_006_src0_data;                                                           // rsp_demux_006:src0_data -> rsp_mux_001:sink6_data
	wire          rsp_demux_006_src0_ready;                                                          // rsp_mux_001:sink6_ready -> rsp_demux_006:src0_ready
	wire    [8:0] rsp_demux_006_src0_channel;                                                        // rsp_demux_006:src0_channel -> rsp_mux_001:sink6_channel
	wire          rsp_demux_006_src0_startofpacket;                                                  // rsp_demux_006:src0_startofpacket -> rsp_mux_001:sink6_startofpacket
	wire          rsp_demux_006_src0_endofpacket;                                                    // rsp_demux_006:src0_endofpacket -> rsp_mux_001:sink6_endofpacket
	wire          rsp_demux_007_src0_valid;                                                          // rsp_demux_007:src0_valid -> rsp_mux_001:sink7_valid
	wire  [119:0] rsp_demux_007_src0_data;                                                           // rsp_demux_007:src0_data -> rsp_mux_001:sink7_data
	wire          rsp_demux_007_src0_ready;                                                          // rsp_mux_001:sink7_ready -> rsp_demux_007:src0_ready
	wire    [8:0] rsp_demux_007_src0_channel;                                                        // rsp_demux_007:src0_channel -> rsp_mux_001:sink7_channel
	wire          rsp_demux_007_src0_startofpacket;                                                  // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink7_startofpacket
	wire          rsp_demux_007_src0_endofpacket;                                                    // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink7_endofpacket
	wire          rsp_demux_008_src0_valid;                                                          // rsp_demux_008:src0_valid -> rsp_mux_001:sink8_valid
	wire  [119:0] rsp_demux_008_src0_data;                                                           // rsp_demux_008:src0_data -> rsp_mux_001:sink8_data
	wire          rsp_demux_008_src0_ready;                                                          // rsp_mux_001:sink8_ready -> rsp_demux_008:src0_ready
	wire    [8:0] rsp_demux_008_src0_channel;                                                        // rsp_demux_008:src0_channel -> rsp_mux_001:sink8_channel
	wire          rsp_demux_008_src0_startofpacket;                                                  // rsp_demux_008:src0_startofpacket -> rsp_mux_001:sink8_startofpacket
	wire          rsp_demux_008_src0_endofpacket;                                                    // rsp_demux_008:src0_endofpacket -> rsp_mux_001:sink8_endofpacket
	wire          router_003_src_valid;                                                              // router_003:src_valid -> SDRAM_s1_rsp_width_adapter:in_valid
	wire  [101:0] router_003_src_data;                                                               // router_003:src_data -> SDRAM_s1_rsp_width_adapter:in_data
	wire          router_003_src_ready;                                                              // SDRAM_s1_rsp_width_adapter:in_ready -> router_003:src_ready
	wire    [8:0] router_003_src_channel;                                                            // router_003:src_channel -> SDRAM_s1_rsp_width_adapter:in_channel
	wire          router_003_src_startofpacket;                                                      // router_003:src_startofpacket -> SDRAM_s1_rsp_width_adapter:in_startofpacket
	wire          router_003_src_endofpacket;                                                        // router_003:src_endofpacket -> SDRAM_s1_rsp_width_adapter:in_endofpacket
	wire          sdram_s1_rsp_width_adapter_src_valid;                                              // SDRAM_s1_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [119:0] sdram_s1_rsp_width_adapter_src_data;                                               // SDRAM_s1_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          sdram_s1_rsp_width_adapter_src_ready;                                              // rsp_demux:sink_ready -> SDRAM_s1_rsp_width_adapter:out_ready
	wire    [8:0] sdram_s1_rsp_width_adapter_src_channel;                                            // SDRAM_s1_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          sdram_s1_rsp_width_adapter_src_startofpacket;                                      // SDRAM_s1_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          sdram_s1_rsp_width_adapter_src_endofpacket;                                        // SDRAM_s1_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                                                 // cmd_mux:src_valid -> SDRAM_s1_cmd_width_adapter:in_valid
	wire  [119:0] cmd_mux_src_data;                                                                  // cmd_mux:src_data -> SDRAM_s1_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                                 // SDRAM_s1_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [8:0] cmd_mux_src_channel;                                                               // cmd_mux:src_channel -> SDRAM_s1_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                         // cmd_mux:src_startofpacket -> SDRAM_s1_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                           // cmd_mux:src_endofpacket -> SDRAM_s1_cmd_width_adapter:in_endofpacket
	wire          sdram_s1_cmd_width_adapter_src_valid;                                              // SDRAM_s1_cmd_width_adapter:out_valid -> SDRAM_s1_burst_adapter:sink0_valid
	wire  [101:0] sdram_s1_cmd_width_adapter_src_data;                                               // SDRAM_s1_cmd_width_adapter:out_data -> SDRAM_s1_burst_adapter:sink0_data
	wire          sdram_s1_cmd_width_adapter_src_ready;                                              // SDRAM_s1_burst_adapter:sink0_ready -> SDRAM_s1_cmd_width_adapter:out_ready
	wire    [8:0] sdram_s1_cmd_width_adapter_src_channel;                                            // SDRAM_s1_cmd_width_adapter:out_channel -> SDRAM_s1_burst_adapter:sink0_channel
	wire          sdram_s1_cmd_width_adapter_src_startofpacket;                                      // SDRAM_s1_cmd_width_adapter:out_startofpacket -> SDRAM_s1_burst_adapter:sink0_startofpacket
	wire          sdram_s1_cmd_width_adapter_src_endofpacket;                                        // SDRAM_s1_cmd_width_adapter:out_endofpacket -> SDRAM_s1_burst_adapter:sink0_endofpacket
	wire    [8:0] niosii_core_data_master_limiter_cmd_valid_data;                                    // niosII_core_data_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
	wire    [8:0] niosii_core_instruction_master_limiter_cmd_valid_data;                             // niosII_core_instruction_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
	wire          sdram_s1_agent_rdata_fifo_out_valid;                                               // SDRAM_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [17:0] sdram_s1_agent_rdata_fifo_out_data;                                                // SDRAM_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          sdram_s1_agent_rdata_fifo_out_ready;                                               // avalon_st_adapter:in_0_ready -> SDRAM_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                                     // avalon_st_adapter:out_0_valid -> SDRAM_s1_agent:rdata_fifo_sink_valid
	wire   [17:0] avalon_st_adapter_out_0_data;                                                      // avalon_st_adapter:out_0_data -> SDRAM_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                     // SDRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                     // avalon_st_adapter:out_0_error -> SDRAM_s1_agent:rdata_fifo_sink_error
	wire          niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid;                            // niosII_core_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	wire   [33:0] niosii_core_debug_mem_slave_agent_rdata_fifo_src_data;                             // niosII_core_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	wire          niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready;                            // avalon_st_adapter_001:in_0_ready -> niosII_core_debug_mem_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_001_out_0_valid;                                                 // avalon_st_adapter_001:out_0_valid -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_001_out_0_data;                                                  // avalon_st_adapter_001:out_0_data -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                                 // niosII_core_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                                 // avalon_st_adapter_001:out_0_error -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_error
	wire          sram_s1_agent_rdata_fifo_src_valid;                                                // SRAM_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
	wire   [33:0] sram_s1_agent_rdata_fifo_src_data;                                                 // SRAM_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
	wire          sram_s1_agent_rdata_fifo_src_ready;                                                // avalon_st_adapter_002:in_0_ready -> SRAM_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_002_out_0_valid;                                                 // avalon_st_adapter_002:out_0_valid -> SRAM_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_002_out_0_data;                                                  // avalon_st_adapter_002:out_0_data -> SRAM_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_002_out_0_ready;                                                 // SRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire    [0:0] avalon_st_adapter_002_out_0_error;                                                 // avalon_st_adapter_002:out_0_error -> SRAM_s1_agent:rdata_fifo_sink_error
	wire          jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid;                                 // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
	wire   [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_src_data;                                  // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
	wire          jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready;                                 // avalon_st_adapter_003:in_0_ready -> JTAG_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_003_out_0_valid;                                                 // avalon_st_adapter_003:out_0_valid -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_003_out_0_data;                                                  // avalon_st_adapter_003:out_0_data -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_003_out_0_ready;                                                 // JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire    [0:0] avalon_st_adapter_003_out_0_error;                                                 // avalon_st_adapter_003:out_0_error -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_error
	wire          uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid;                            // UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
	wire   [33:0] uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data;                             // UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
	wire          uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready;                            // avalon_st_adapter_004:in_0_ready -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_004_out_0_valid;                                                 // avalon_st_adapter_004:out_0_valid -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_004_out_0_data;                                                  // avalon_st_adapter_004:out_0_data -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_004_out_0_ready;                                                 // UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
	wire    [0:0] avalon_st_adapter_004_out_0_error;                                                 // avalon_st_adapter_004:out_0_error -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_error
	wire          convolution_slave_avs_s0_agent_rdata_fifo_src_valid;                               // convolution_slave_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
	wire   [33:0] convolution_slave_avs_s0_agent_rdata_fifo_src_data;                                // convolution_slave_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
	wire          convolution_slave_avs_s0_agent_rdata_fifo_src_ready;                               // avalon_st_adapter_005:in_0_ready -> convolution_slave_avs_s0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_005_out_0_valid;                                                 // avalon_st_adapter_005:out_0_valid -> convolution_slave_avs_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_005_out_0_data;                                                  // avalon_st_adapter_005:out_0_data -> convolution_slave_avs_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_005_out_0_ready;                                                 // convolution_slave_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
	wire    [0:0] avalon_st_adapter_005_out_0_error;                                                 // avalon_st_adapter_005:out_0_error -> convolution_slave_avs_s0_agent:rdata_fifo_sink_error
	wire          test_pipeline_avs_s0_agent_rdata_fifo_src_valid;                                   // Test_PipeLine_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
	wire   [33:0] test_pipeline_avs_s0_agent_rdata_fifo_src_data;                                    // Test_PipeLine_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
	wire          test_pipeline_avs_s0_agent_rdata_fifo_src_ready;                                   // avalon_st_adapter_006:in_0_ready -> Test_PipeLine_avs_s0_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_006_out_0_valid;                                                 // avalon_st_adapter_006:out_0_valid -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_006_out_0_data;                                                  // avalon_st_adapter_006:out_0_data -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_006_out_0_ready;                                                 // Test_PipeLine_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
	wire    [0:0] avalon_st_adapter_006_out_0_error;                                                 // avalon_st_adapter_006:out_0_error -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_error
	wire          systemid_control_slave_agent_rdata_fifo_src_valid;                                 // SystemID_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
	wire   [33:0] systemid_control_slave_agent_rdata_fifo_src_data;                                  // SystemID_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
	wire          systemid_control_slave_agent_rdata_fifo_src_ready;                                 // avalon_st_adapter_007:in_0_ready -> SystemID_control_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_007_out_0_valid;                                                 // avalon_st_adapter_007:out_0_valid -> SystemID_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_007_out_0_data;                                                  // avalon_st_adapter_007:out_0_data -> SystemID_control_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_007_out_0_ready;                                                 // SystemID_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
	wire    [0:0] avalon_st_adapter_007_out_0_error;                                                 // avalon_st_adapter_007:out_0_error -> SystemID_control_slave_agent:rdata_fifo_sink_error
	wire          sys_timer_s1_agent_rdata_fifo_src_valid;                                           // Sys_Timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
	wire   [33:0] sys_timer_s1_agent_rdata_fifo_src_data;                                            // Sys_Timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
	wire          sys_timer_s1_agent_rdata_fifo_src_ready;                                           // avalon_st_adapter_008:in_0_ready -> Sys_Timer_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_008_out_0_valid;                                                 // avalon_st_adapter_008:out_0_valid -> Sys_Timer_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_008_out_0_data;                                                  // avalon_st_adapter_008:out_0_data -> Sys_Timer_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_008_out_0_ready;                                                 // Sys_Timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
	wire    [0:0] avalon_st_adapter_008_out_0_error;                                                 // avalon_st_adapter_008:out_0_error -> Sys_Timer_s1_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (8),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) test_pipeline_avm_m0_translator (
		.clk                    (system_pll_outclk0_clk),                                                  //                       clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),                         //                     reset.reset
		.uav_address            (test_pipeline_avm_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (test_pipeline_avm_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (test_pipeline_avm_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (test_pipeline_avm_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (Test_PipeLine_avm_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (Test_PipeLine_avm_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (Test_PipeLine_avm_m0_burstcount),                                         //                          .burstcount
		.av_read                (Test_PipeLine_avm_m0_read),                                               //                          .read
		.av_readdata            (Test_PipeLine_avm_m0_readdata),                                           //                          .readdata
		.av_readdatavalid       (Test_PipeLine_avm_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (Test_PipeLine_avm_m0_write),                                              //                          .write
		.av_writedata           (Test_PipeLine_avm_m0_writedata),                                          //                          .writedata
		.av_byteenable          (4'b1111),                                                                 //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                    //               (terminated)
		.av_begintransfer       (1'b0),                                                                    //               (terminated)
		.av_chipselect          (1'b0),                                                                    //               (terminated)
		.av_lock                (1'b0),                                                                    //               (terminated)
		.av_debugaccess         (1'b0),                                                                    //               (terminated)
		.uav_clken              (),                                                                        //               (terminated)
		.av_clken               (1'b1),                                                                    //               (terminated)
		.uav_response           (2'b00),                                                                   //               (terminated)
		.av_response            (),                                                                        //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                    //               (terminated)
		.av_writeresponsevalid  ()                                                                         //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (27),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (4),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (6),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) niosii_core_data_master_translator (
		.clk                    (system_pll_outclk0_clk),                                                     //                       clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),                            //                     reset.reset
		.uav_address            (niosii_core_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (niosii_core_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (niosii_core_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (niosii_core_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (niosii_core_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (niosii_core_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (niosii_core_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (niosii_core_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (niosII_core_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (niosII_core_data_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (niosII_core_data_master_burstcount),                                         //                          .burstcount
		.av_byteenable          (niosII_core_data_master_byteenable),                                         //                          .byteenable
		.av_read                (niosII_core_data_master_read),                                               //                          .read
		.av_readdata            (niosII_core_data_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (niosII_core_data_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (niosII_core_data_master_write),                                              //                          .write
		.av_writedata           (niosII_core_data_master_writedata),                                          //                          .writedata
		.av_debugaccess         (niosII_core_data_master_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                       //               (terminated)
		.av_begintransfer       (1'b0),                                                                       //               (terminated)
		.av_chipselect          (1'b0),                                                                       //               (terminated)
		.av_lock                (1'b0),                                                                       //               (terminated)
		.uav_clken              (),                                                                           //               (terminated)
		.av_clken               (1'b1),                                                                       //               (terminated)
		.uav_response           (2'b00),                                                                      //               (terminated)
		.av_response            (),                                                                           //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                       //               (terminated)
		.av_writeresponsevalid  ()                                                                            //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (27),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (4),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (6),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) niosii_core_instruction_master_translator (
		.clk                    (system_pll_outclk0_clk),                                                            //                       clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),                                   //                     reset.reset
		.uav_address            (niosii_core_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (niosii_core_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (niosii_core_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (niosii_core_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (niosII_core_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (niosII_core_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (niosII_core_instruction_master_burstcount),                                         //                          .burstcount
		.av_read                (niosII_core_instruction_master_read),                                               //                          .read
		.av_readdata            (niosII_core_instruction_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (niosII_core_instruction_master_readdatavalid),                                      //                          .readdatavalid
		.av_byteenable          (4'b1111),                                                                           //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                              //               (terminated)
		.av_begintransfer       (1'b0),                                                                              //               (terminated)
		.av_chipselect          (1'b0),                                                                              //               (terminated)
		.av_write               (1'b0),                                                                              //               (terminated)
		.av_writedata           (32'b00000000000000000000000000000000),                                              //               (terminated)
		.av_lock                (1'b0),                                                                              //               (terminated)
		.av_debugaccess         (1'b0),                                                                              //               (terminated)
		.uav_clken              (),                                                                                  //               (terminated)
		.av_clken               (1'b1),                                                                              //               (terminated)
		.uav_response           (2'b00),                                                                             //               (terminated)
		.av_response            (),                                                                                  //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                              //               (terminated)
		.av_writeresponsevalid  ()                                                                                   //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (16),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (2),
		.UAV_BYTEENABLE_W               (2),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (2),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (2),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sdram_s1_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sdram_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (sdram_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (sdram_s1_agent_m0_read),                          //                         .read
		.uav_write              (sdram_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (sdram_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (sdram_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (sdram_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (sdram_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (sdram_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (sdram_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (sdram_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (SDRAM_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (SDRAM_s1_write),                                  //                         .write
		.av_read                (SDRAM_s1_read),                                   //                         .read
		.av_readdata            (SDRAM_s1_readdata),                               //                         .readdata
		.av_writedata           (SDRAM_s1_writedata),                              //                         .writedata
		.av_byteenable          (SDRAM_s1_byteenable),                             //                         .byteenable
		.av_readdatavalid       (SDRAM_s1_readdatavalid),                          //                         .readdatavalid
		.av_waitrequest         (SDRAM_s1_waitrequest),                            //                         .waitrequest
		.av_chipselect          (SDRAM_s1_chipselect),                             //                         .chipselect
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) niosii_core_debug_mem_slave_translator (
		.clk                    (system_pll_outclk0_clk),                             //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),    //                    reset.reset
		.uav_address            (niosii_core_debug_mem_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (niosii_core_debug_mem_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (niosii_core_debug_mem_slave_agent_m0_read),          //                         .read
		.uav_write              (niosii_core_debug_mem_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (niosii_core_debug_mem_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (niosii_core_debug_mem_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (niosii_core_debug_mem_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (niosii_core_debug_mem_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (niosii_core_debug_mem_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (niosii_core_debug_mem_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (niosii_core_debug_mem_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (niosII_core_debug_mem_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (niosII_core_debug_mem_slave_write),                  //                         .write
		.av_read                (niosII_core_debug_mem_slave_read),                   //                         .read
		.av_readdata            (niosII_core_debug_mem_slave_readdata),               //                         .readdata
		.av_writedata           (niosII_core_debug_mem_slave_writedata),              //                         .writedata
		.av_byteenable          (niosII_core_debug_mem_slave_byteenable),             //                         .byteenable
		.av_waitrequest         (niosII_core_debug_mem_slave_waitrequest),            //                         .waitrequest
		.av_debugaccess         (niosII_core_debug_mem_slave_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                                   //              (terminated)
		.av_beginbursttransfer  (),                                                   //              (terminated)
		.av_burstcount          (),                                                   //              (terminated)
		.av_readdatavalid       (1'b0),                                               //              (terminated)
		.av_writebyteenable     (),                                                   //              (terminated)
		.av_lock                (),                                                   //              (terminated)
		.av_chipselect          (),                                                   //              (terminated)
		.av_clken               (),                                                   //              (terminated)
		.uav_clken              (1'b0),                                               //              (terminated)
		.av_outputenable        (),                                                   //              (terminated)
		.uav_response           (),                                                   //              (terminated)
		.av_response            (2'b00),                                              //              (terminated)
		.uav_writeresponsevalid (),                                                   //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (15),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sram_s1_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sram_s1_agent_m0_address),                        // avalon_universal_slave_0.address
		.uav_burstcount         (sram_s1_agent_m0_burstcount),                     //                         .burstcount
		.uav_read               (sram_s1_agent_m0_read),                           //                         .read
		.uav_write              (sram_s1_agent_m0_write),                          //                         .write
		.uav_waitrequest        (sram_s1_agent_m0_waitrequest),                    //                         .waitrequest
		.uav_readdatavalid      (sram_s1_agent_m0_readdatavalid),                  //                         .readdatavalid
		.uav_byteenable         (sram_s1_agent_m0_byteenable),                     //                         .byteenable
		.uav_readdata           (sram_s1_agent_m0_readdata),                       //                         .readdata
		.uav_writedata          (sram_s1_agent_m0_writedata),                      //                         .writedata
		.uav_lock               (sram_s1_agent_m0_lock),                           //                         .lock
		.uav_debugaccess        (sram_s1_agent_m0_debugaccess),                    //                         .debugaccess
		.av_address             (SRAM_s1_address),                                 //      avalon_anti_slave_0.address
		.av_write               (SRAM_s1_write),                                   //                         .write
		.av_readdata            (SRAM_s1_readdata),                                //                         .readdata
		.av_writedata           (SRAM_s1_writedata),                               //                         .writedata
		.av_byteenable          (SRAM_s1_byteenable),                              //                         .byteenable
		.av_chipselect          (SRAM_s1_chipselect),                              //                         .chipselect
		.av_clken               (SRAM_s1_clken),                                   //                         .clken
		.av_read                (),                                                //              (terminated)
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_waitrequest         (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) jtag_avalon_jtag_slave_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (jtag_avalon_jtag_slave_agent_m0_address),         // avalon_universal_slave_0.address
		.uav_burstcount         (jtag_avalon_jtag_slave_agent_m0_burstcount),      //                         .burstcount
		.uav_read               (jtag_avalon_jtag_slave_agent_m0_read),            //                         .read
		.uav_write              (jtag_avalon_jtag_slave_agent_m0_write),           //                         .write
		.uav_waitrequest        (jtag_avalon_jtag_slave_agent_m0_waitrequest),     //                         .waitrequest
		.uav_readdatavalid      (jtag_avalon_jtag_slave_agent_m0_readdatavalid),   //                         .readdatavalid
		.uav_byteenable         (jtag_avalon_jtag_slave_agent_m0_byteenable),      //                         .byteenable
		.uav_readdata           (jtag_avalon_jtag_slave_agent_m0_readdata),        //                         .readdata
		.uav_writedata          (jtag_avalon_jtag_slave_agent_m0_writedata),       //                         .writedata
		.uav_lock               (jtag_avalon_jtag_slave_agent_m0_lock),            //                         .lock
		.uav_debugaccess        (jtag_avalon_jtag_slave_agent_m0_debugaccess),     //                         .debugaccess
		.av_address             (JTAG_avalon_jtag_slave_address),                  //      avalon_anti_slave_0.address
		.av_write               (JTAG_avalon_jtag_slave_write),                    //                         .write
		.av_read                (JTAG_avalon_jtag_slave_read),                     //                         .read
		.av_readdata            (JTAG_avalon_jtag_slave_readdata),                 //                         .readdata
		.av_writedata           (JTAG_avalon_jtag_slave_writedata),                //                         .writedata
		.av_waitrequest         (JTAG_avalon_jtag_slave_waitrequest),              //                         .waitrequest
		.av_chipselect          (JTAG_avalon_jtag_slave_chipselect),               //                         .chipselect
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) uart_com_avalon_rs232_slave_translator (
		.clk                    (system_pll_outclk0_clk),                             //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),    //                    reset.reset
		.uav_address            (uart_com_avalon_rs232_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (uart_com_avalon_rs232_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (uart_com_avalon_rs232_slave_agent_m0_read),          //                         .read
		.uav_write              (uart_com_avalon_rs232_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (uart_com_avalon_rs232_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (uart_com_avalon_rs232_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (uart_com_avalon_rs232_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (uart_com_avalon_rs232_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (uart_com_avalon_rs232_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (uart_com_avalon_rs232_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (uart_com_avalon_rs232_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (UART_COM_avalon_rs232_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (UART_COM_avalon_rs232_slave_write),                  //                         .write
		.av_read                (UART_COM_avalon_rs232_slave_read),                   //                         .read
		.av_readdata            (UART_COM_avalon_rs232_slave_readdata),               //                         .readdata
		.av_writedata           (UART_COM_avalon_rs232_slave_writedata),              //                         .writedata
		.av_byteenable          (UART_COM_avalon_rs232_slave_byteenable),             //                         .byteenable
		.av_chipselect          (UART_COM_avalon_rs232_slave_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                   //              (terminated)
		.av_beginbursttransfer  (),                                                   //              (terminated)
		.av_burstcount          (),                                                   //              (terminated)
		.av_readdatavalid       (1'b0),                                               //              (terminated)
		.av_waitrequest         (1'b0),                                               //              (terminated)
		.av_writebyteenable     (),                                                   //              (terminated)
		.av_lock                (),                                                   //              (terminated)
		.av_clken               (),                                                   //              (terminated)
		.uav_clken              (1'b0),                                               //              (terminated)
		.av_debugaccess         (),                                                   //              (terminated)
		.av_outputenable        (),                                                   //              (terminated)
		.uav_response           (),                                                   //              (terminated)
		.av_response            (2'b00),                                              //              (terminated)
		.uav_writeresponsevalid (),                                                   //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) convolution_slave_avs_s0_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (convolution_slave_avs_s0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (convolution_slave_avs_s0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (convolution_slave_avs_s0_agent_m0_read),          //                         .read
		.uav_write              (convolution_slave_avs_s0_agent_m0_write),         //                         .write
		.uav_waitrequest        (convolution_slave_avs_s0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (convolution_slave_avs_s0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (convolution_slave_avs_s0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (convolution_slave_avs_s0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (convolution_slave_avs_s0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (convolution_slave_avs_s0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (convolution_slave_avs_s0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (convolution_slave_avs_s0_address),                //      avalon_anti_slave_0.address
		.av_write               (convolution_slave_avs_s0_write),                  //                         .write
		.av_read                (convolution_slave_avs_s0_read),                   //                         .read
		.av_readdata            (convolution_slave_avs_s0_readdata),               //                         .readdata
		.av_writedata           (convolution_slave_avs_s0_writedata),              //                         .writedata
		.av_waitrequest         (convolution_slave_avs_s0_waitrequest),            //                         .waitrequest
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) test_pipeline_avs_s0_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (test_pipeline_avs_s0_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (test_pipeline_avs_s0_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (test_pipeline_avs_s0_agent_m0_read),              //                         .read
		.uav_write              (test_pipeline_avs_s0_agent_m0_write),             //                         .write
		.uav_waitrequest        (test_pipeline_avs_s0_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (test_pipeline_avs_s0_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (test_pipeline_avs_s0_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (test_pipeline_avs_s0_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (test_pipeline_avs_s0_agent_m0_writedata),         //                         .writedata
		.uav_lock               (test_pipeline_avs_s0_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (test_pipeline_avs_s0_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (Test_PipeLine_avs_s0_address),                    //      avalon_anti_slave_0.address
		.av_write               (Test_PipeLine_avs_s0_write),                      //                         .write
		.av_read                (Test_PipeLine_avs_s0_read),                       //                         .read
		.av_readdata            (Test_PipeLine_avs_s0_readdata),                   //                         .readdata
		.av_writedata           (Test_PipeLine_avs_s0_writedata),                  //                         .writedata
		.av_waitrequest         (Test_PipeLine_avs_s0_waitrequest),                //                         .waitrequest
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) systemid_control_slave_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (systemid_control_slave_agent_m0_address),         // avalon_universal_slave_0.address
		.uav_burstcount         (systemid_control_slave_agent_m0_burstcount),      //                         .burstcount
		.uav_read               (systemid_control_slave_agent_m0_read),            //                         .read
		.uav_write              (systemid_control_slave_agent_m0_write),           //                         .write
		.uav_waitrequest        (systemid_control_slave_agent_m0_waitrequest),     //                         .waitrequest
		.uav_readdatavalid      (systemid_control_slave_agent_m0_readdatavalid),   //                         .readdatavalid
		.uav_byteenable         (systemid_control_slave_agent_m0_byteenable),      //                         .byteenable
		.uav_readdata           (systemid_control_slave_agent_m0_readdata),        //                         .readdata
		.uav_writedata          (systemid_control_slave_agent_m0_writedata),       //                         .writedata
		.uav_lock               (systemid_control_slave_agent_m0_lock),            //                         .lock
		.uav_debugaccess        (systemid_control_slave_agent_m0_debugaccess),     //                         .debugaccess
		.av_address             (SystemID_control_slave_address),                  //      avalon_anti_slave_0.address
		.av_readdata            (SystemID_control_slave_readdata),                 //                         .readdata
		.av_write               (),                                                //              (terminated)
		.av_read                (),                                                //              (terminated)
		.av_writedata           (),                                                //              (terminated)
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_waitrequest         (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sys_timer_s1_translator (
		.clk                    (system_pll_outclk0_clk),                          //                      clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sys_timer_s1_agent_m0_address),                   // avalon_universal_slave_0.address
		.uav_burstcount         (sys_timer_s1_agent_m0_burstcount),                //                         .burstcount
		.uav_read               (sys_timer_s1_agent_m0_read),                      //                         .read
		.uav_write              (sys_timer_s1_agent_m0_write),                     //                         .write
		.uav_waitrequest        (sys_timer_s1_agent_m0_waitrequest),               //                         .waitrequest
		.uav_readdatavalid      (sys_timer_s1_agent_m0_readdatavalid),             //                         .readdatavalid
		.uav_byteenable         (sys_timer_s1_agent_m0_byteenable),                //                         .byteenable
		.uav_readdata           (sys_timer_s1_agent_m0_readdata),                  //                         .readdata
		.uav_writedata          (sys_timer_s1_agent_m0_writedata),                 //                         .writedata
		.uav_lock               (sys_timer_s1_agent_m0_lock),                      //                         .lock
		.uav_debugaccess        (sys_timer_s1_agent_m0_debugaccess),               //                         .debugaccess
		.av_address             (Sys_Timer_s1_address),                            //      avalon_anti_slave_0.address
		.av_write               (Sys_Timer_s1_write),                              //                         .write
		.av_readdata            (Sys_Timer_s1_readdata),                           //                         .readdata
		.av_writedata           (Sys_Timer_s1_writedata),                          //                         .writedata
		.av_chipselect          (Sys_Timer_s1_chipselect),                         //                         .chipselect
		.av_read                (),                                                //              (terminated)
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_burstcount          (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_readdatavalid       (1'b0),                                            //              (terminated)
		.av_waitrequest         (1'b0),                                            //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_QOS_H                 (98),
		.PKT_QOS_L                 (98),
		.PKT_DATA_SIDEBAND_H       (96),
		.PKT_DATA_SIDEBAND_L       (96),
		.PKT_ADDR_SIDEBAND_H       (95),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_CACHE_H               (114),
		.PKT_CACHE_L               (111),
		.PKT_THREAD_ID_H           (107),
		.PKT_THREAD_ID_L           (107),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (63),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) test_pipeline_avm_m0_agent (
		.clk                   (system_pll_outclk0_clk),                                                  //       clk.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),                         // clk_reset.reset
		.av_address            (test_pipeline_avm_m0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (test_pipeline_avm_m0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (test_pipeline_avm_m0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (test_pipeline_avm_m0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (test_pipeline_avm_m0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (test_pipeline_avm_m0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (test_pipeline_avm_m0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (test_pipeline_avm_m0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (test_pipeline_avm_m0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                       //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                        //          .data
		.rp_channel            (rsp_mux_src_channel),                                                     //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                               //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                 //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                       //          .ready
		.av_response           (),                                                                        // (terminated)
		.av_writeresponsevalid ()                                                                         // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_QOS_H                 (98),
		.PKT_QOS_L                 (98),
		.PKT_DATA_SIDEBAND_H       (96),
		.PKT_DATA_SIDEBAND_L       (96),
		.PKT_ADDR_SIDEBAND_H       (95),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_CACHE_H               (114),
		.PKT_CACHE_L               (111),
		.PKT_THREAD_ID_H           (107),
		.PKT_THREAD_ID_L           (107),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.AV_BURSTCOUNT_W           (6),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (63),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) niosii_core_data_master_agent (
		.clk                   (system_pll_outclk0_clk),                                                     //       clk.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.av_address            (niosii_core_data_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (niosii_core_data_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (niosii_core_data_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (niosii_core_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (niosii_core_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (niosii_core_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (niosii_core_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (niosii_core_data_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (niosii_core_data_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (niosii_core_data_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (niosii_core_data_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (niosii_core_data_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (niosii_core_data_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (niosii_core_data_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (niosii_core_data_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (niosii_core_data_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (niosii_core_data_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (niosii_core_data_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (niosii_core_data_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                           // (terminated)
		.av_writeresponsevalid ()                                                                            // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_QOS_H                 (98),
		.PKT_QOS_L                 (98),
		.PKT_DATA_SIDEBAND_H       (96),
		.PKT_DATA_SIDEBAND_L       (96),
		.PKT_ADDR_SIDEBAND_H       (95),
		.PKT_ADDR_SIDEBAND_L       (95),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_CACHE_H               (114),
		.PKT_CACHE_L               (111),
		.PKT_THREAD_ID_H           (107),
		.PKT_THREAD_ID_L           (107),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.AV_BURSTCOUNT_W           (6),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (31),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) niosii_core_instruction_master_agent (
		.clk                   (system_pll_outclk0_clk),                                                            //       clk.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),                                   // clk_reset.reset
		.av_address            (niosii_core_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (niosii_core_instruction_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (niosii_core_instruction_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (niosii_core_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (niosii_core_instruction_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (niosii_core_instruction_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (niosii_core_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (niosii_core_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (niosii_core_instruction_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (niosii_core_instruction_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (niosii_core_instruction_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (niosii_core_instruction_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (niosii_core_instruction_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (niosii_core_instruction_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (niosii_core_instruction_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                                  // (terminated)
		.av_writeresponsevalid ()                                                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (101),
		.PKT_ORI_BURST_SIZE_L      (99),
		.PKT_RESPONSE_STATUS_H     (98),
		.PKT_RESPONSE_STATUS_L     (97),
		.PKT_BURST_SIZE_H          (74),
		.PKT_BURST_SIZE_L          (72),
		.PKT_TRANS_LOCK            (54),
		.PKT_BEGIN_BURST           (79),
		.PKT_PROTECTION_H          (92),
		.PKT_PROTECTION_L          (90),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (66),
		.PKT_BYTE_CNT_H            (65),
		.PKT_BYTE_CNT_L            (56),
		.PKT_ADDR_H                (49),
		.PKT_ADDR_L                (18),
		.PKT_TRANS_COMPRESSED_READ (50),
		.PKT_TRANS_POSTED          (51),
		.PKT_TRANS_WRITE           (52),
		.PKT_TRANS_READ            (53),
		.PKT_DATA_H                (15),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_SRC_ID_H              (84),
		.PKT_SRC_ID_L              (81),
		.PKT_DEST_ID_H             (88),
		.PKT_DEST_ID_L             (85),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (102),
		.AVS_BURSTCOUNT_W          (2),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sdram_s1_agent (
		.clk                     (system_pll_outclk0_clk),                          //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (sdram_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (sdram_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (sdram_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (sdram_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (sdram_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (sdram_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (sdram_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (sdram_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (sdram_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (sdram_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (sdram_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (sdram_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (sdram_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (sdram_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (sdram_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (sdram_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (sdram_s1_burst_adapter_source0_ready),            //              cp.ready
		.cp_valid                (sdram_s1_burst_adapter_source0_valid),            //                .valid
		.cp_data                 (sdram_s1_burst_adapter_source0_data),             //                .data
		.cp_startofpacket        (sdram_s1_burst_adapter_source0_startofpacket),    //                .startofpacket
		.cp_endofpacket          (sdram_s1_burst_adapter_source0_endofpacket),      //                .endofpacket
		.cp_channel              (sdram_s1_burst_adapter_source0_channel),          //                .channel
		.rf_sink_ready           (sdram_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (sdram_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (sdram_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (sdram_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (sdram_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (sdram_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (sdram_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (sdram_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (sdram_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                   // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                   //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                    //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                   //                .error
		.rdata_fifo_src_ready    (sdram_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sdram_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (sdram_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (103),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sdram_s1_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                          //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sdram_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (sdram_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (sdram_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (sdram_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (sdram_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (sdram_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (sdram_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (sdram_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (sdram_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (18),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sdram_s1_agent_rdata_fifo (
		.clk               (system_pll_outclk0_clk),                          //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sdram_s1_agent_rdata_fifo_src_data),              //        in.data
		.in_valid          (sdram_s1_agent_rdata_fifo_src_valid),             //          .valid
		.in_ready          (sdram_s1_agent_rdata_fifo_src_ready),             //          .ready
		.out_data          (sdram_s1_agent_rdata_fifo_out_data),              //       out.data
		.out_valid         (sdram_s1_agent_rdata_fifo_out_valid),             //          .valid
		.out_ready         (sdram_s1_agent_rdata_fifo_out_ready),             //          .ready
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_startofpacket  (1'b0),                                            // (terminated)
		.in_endofpacket    (1'b0),                                            // (terminated)
		.out_startofpacket (),                                                // (terminated)
		.out_endofpacket   (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) niosii_core_debug_mem_slave_agent (
		.clk                     (system_pll_outclk0_clk),                                          //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),                 //       clk_reset.reset
		.m0_address              (niosii_core_debug_mem_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (niosii_core_debug_mem_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (niosii_core_debug_mem_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (niosii_core_debug_mem_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (niosii_core_debug_mem_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (niosii_core_debug_mem_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (niosii_core_debug_mem_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (niosii_core_debug_mem_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (niosii_core_debug_mem_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (niosii_core_debug_mem_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (niosii_core_debug_mem_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (niosii_core_debug_mem_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (niosii_core_debug_mem_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (niosii_core_debug_mem_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (niosii_core_debug_mem_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (niosii_core_debug_mem_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (niosii_core_debug_mem_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (niosii_core_debug_mem_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (niosii_core_debug_mem_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (niosii_core_debug_mem_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (niosii_core_debug_mem_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (niosii_core_debug_mem_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (niosii_core_debug_mem_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (niosii_core_debug_mem_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (niosii_core_debug_mem_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                               // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                               //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                                //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                               //                .error
		.rdata_fifo_src_ready    (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) niosii_core_debug_mem_slave_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                       //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.in_data           (niosii_core_debug_mem_slave_agent_rf_source_data),             //        in.data
		.in_valid          (niosii_core_debug_mem_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (niosii_core_debug_mem_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (niosii_core_debug_mem_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (niosii_core_debug_mem_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated)
		.csr_read          (1'b0),                                                         // (terminated)
		.csr_write         (1'b0),                                                         // (terminated)
		.csr_readdata      (),                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
		.almost_full_data  (),                                                             // (terminated)
		.almost_empty_data (),                                                             // (terminated)
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.in_error          (1'b0),                                                         // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_channel        (1'b0),                                                         // (terminated)
		.out_channel       ()                                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sram_s1_agent (
		.clk                     (system_pll_outclk0_clk),                          //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (sram_s1_agent_m0_address),                        //              m0.address
		.m0_burstcount           (sram_s1_agent_m0_burstcount),                     //                .burstcount
		.m0_byteenable           (sram_s1_agent_m0_byteenable),                     //                .byteenable
		.m0_debugaccess          (sram_s1_agent_m0_debugaccess),                    //                .debugaccess
		.m0_lock                 (sram_s1_agent_m0_lock),                           //                .lock
		.m0_readdata             (sram_s1_agent_m0_readdata),                       //                .readdata
		.m0_readdatavalid        (sram_s1_agent_m0_readdatavalid),                  //                .readdatavalid
		.m0_read                 (sram_s1_agent_m0_read),                           //                .read
		.m0_waitrequest          (sram_s1_agent_m0_waitrequest),                    //                .waitrequest
		.m0_writedata            (sram_s1_agent_m0_writedata),                      //                .writedata
		.m0_write                (sram_s1_agent_m0_write),                          //                .write
		.rp_endofpacket          (sram_s1_agent_rp_endofpacket),                    //              rp.endofpacket
		.rp_ready                (sram_s1_agent_rp_ready),                          //                .ready
		.rp_valid                (sram_s1_agent_rp_valid),                          //                .valid
		.rp_data                 (sram_s1_agent_rp_data),                           //                .data
		.rp_startofpacket        (sram_s1_agent_rp_startofpacket),                  //                .startofpacket
		.cp_ready                (sram_s1_burst_adapter_source0_ready),             //              cp.ready
		.cp_valid                (sram_s1_burst_adapter_source0_valid),             //                .valid
		.cp_data                 (sram_s1_burst_adapter_source0_data),              //                .data
		.cp_startofpacket        (sram_s1_burst_adapter_source0_startofpacket),     //                .startofpacket
		.cp_endofpacket          (sram_s1_burst_adapter_source0_endofpacket),       //                .endofpacket
		.cp_channel              (sram_s1_burst_adapter_source0_channel),           //                .channel
		.rf_sink_ready           (sram_s1_agent_rsp_fifo_out_ready),                //         rf_sink.ready
		.rf_sink_valid           (sram_s1_agent_rsp_fifo_out_valid),                //                .valid
		.rf_sink_startofpacket   (sram_s1_agent_rsp_fifo_out_startofpacket),        //                .startofpacket
		.rf_sink_endofpacket     (sram_s1_agent_rsp_fifo_out_endofpacket),          //                .endofpacket
		.rf_sink_data            (sram_s1_agent_rsp_fifo_out_data),                 //                .data
		.rf_source_ready         (sram_s1_agent_rf_source_ready),                   //       rf_source.ready
		.rf_source_valid         (sram_s1_agent_rf_source_valid),                   //                .valid
		.rf_source_startofpacket (sram_s1_agent_rf_source_startofpacket),           //                .startofpacket
		.rf_source_endofpacket   (sram_s1_agent_rf_source_endofpacket),             //                .endofpacket
		.rf_source_data          (sram_s1_agent_rf_source_data),                    //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),               // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),               //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),               //                .error
		.rdata_fifo_src_ready    (sram_s1_agent_rdata_fifo_src_ready),              //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sram_s1_agent_rdata_fifo_src_valid),              //                .valid
		.rdata_fifo_src_data     (sram_s1_agent_rdata_fifo_src_data),               //                .data
		.m0_response             (2'b00),                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sram_s1_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                          //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sram_s1_agent_rf_source_data),                    //        in.data
		.in_valid          (sram_s1_agent_rf_source_valid),                   //          .valid
		.in_ready          (sram_s1_agent_rf_source_ready),                   //          .ready
		.in_startofpacket  (sram_s1_agent_rf_source_startofpacket),           //          .startofpacket
		.in_endofpacket    (sram_s1_agent_rf_source_endofpacket),             //          .endofpacket
		.out_data          (sram_s1_agent_rsp_fifo_out_data),                 //       out.data
		.out_valid         (sram_s1_agent_rsp_fifo_out_valid),                //          .valid
		.out_ready         (sram_s1_agent_rsp_fifo_out_ready),                //          .ready
		.out_startofpacket (sram_s1_agent_rsp_fifo_out_startofpacket),        //          .startofpacket
		.out_endofpacket   (sram_s1_agent_rsp_fifo_out_endofpacket),          //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) jtag_avalon_jtag_slave_agent (
		.clk                     (system_pll_outclk0_clk),                                     //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
		.m0_address              (jtag_avalon_jtag_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (jtag_avalon_jtag_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (jtag_avalon_jtag_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (jtag_avalon_jtag_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (jtag_avalon_jtag_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (jtag_avalon_jtag_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (jtag_avalon_jtag_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (jtag_avalon_jtag_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (jtag_avalon_jtag_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (jtag_avalon_jtag_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (jtag_avalon_jtag_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (jtag_avalon_jtag_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (jtag_avalon_jtag_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (jtag_avalon_jtag_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (jtag_avalon_jtag_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (jtag_avalon_jtag_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (jtag_avalon_jtag_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (jtag_avalon_jtag_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (jtag_avalon_jtag_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (jtag_avalon_jtag_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (jtag_avalon_jtag_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (jtag_avalon_jtag_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (jtag_avalon_jtag_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (jtag_avalon_jtag_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                          //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                           //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                          //                .error
		.rdata_fifo_src_ready    (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                  //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
		.in_data           (jtag_avalon_jtag_slave_agent_rf_source_data),             //        in.data
		.in_valid          (jtag_avalon_jtag_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (jtag_avalon_jtag_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (jtag_avalon_jtag_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (jtag_avalon_jtag_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated)
		.csr_read          (1'b0),                                                    // (terminated)
		.csr_write         (1'b0),                                                    // (terminated)
		.csr_readdata      (),                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated)
		.almost_full_data  (),                                                        // (terminated)
		.almost_empty_data (),                                                        // (terminated)
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_channel        (1'b0),                                                    // (terminated)
		.out_channel       ()                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) uart_com_avalon_rs232_slave_agent (
		.clk                     (system_pll_outclk0_clk),                                          //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),                 //       clk_reset.reset
		.m0_address              (uart_com_avalon_rs232_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (uart_com_avalon_rs232_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (uart_com_avalon_rs232_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (uart_com_avalon_rs232_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (uart_com_avalon_rs232_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (uart_com_avalon_rs232_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (uart_com_avalon_rs232_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (uart_com_avalon_rs232_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (uart_com_avalon_rs232_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (uart_com_avalon_rs232_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (uart_com_avalon_rs232_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (uart_com_avalon_rs232_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (uart_com_avalon_rs232_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (uart_com_avalon_rs232_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (uart_com_avalon_rs232_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (uart_com_avalon_rs232_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (uart_com_avalon_rs232_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (uart_com_avalon_rs232_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (uart_com_avalon_rs232_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (uart_com_avalon_rs232_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (uart_com_avalon_rs232_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (uart_com_avalon_rs232_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (uart_com_avalon_rs232_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (uart_com_avalon_rs232_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (uart_com_avalon_rs232_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_004_out_0_ready),                               // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_004_out_0_valid),                               //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_004_out_0_data),                                //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_004_out_0_error),                               //                .error
		.rdata_fifo_src_ready    (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                           //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                             //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uart_com_avalon_rs232_slave_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                       //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.in_data           (uart_com_avalon_rs232_slave_agent_rf_source_data),             //        in.data
		.in_valid          (uart_com_avalon_rs232_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (uart_com_avalon_rs232_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (uart_com_avalon_rs232_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (uart_com_avalon_rs232_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated)
		.csr_read          (1'b0),                                                         // (terminated)
		.csr_write         (1'b0),                                                         // (terminated)
		.csr_readdata      (),                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
		.almost_full_data  (),                                                             // (terminated)
		.almost_empty_data (),                                                             // (terminated)
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.in_error          (1'b0),                                                         // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_channel        (1'b0),                                                         // (terminated)
		.out_channel       ()                                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) convolution_slave_avs_s0_agent (
		.clk                     (system_pll_outclk0_clk),                                       //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),              //       clk_reset.reset
		.m0_address              (convolution_slave_avs_s0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (convolution_slave_avs_s0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (convolution_slave_avs_s0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (convolution_slave_avs_s0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (convolution_slave_avs_s0_agent_m0_lock),                       //                .lock
		.m0_readdata             (convolution_slave_avs_s0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (convolution_slave_avs_s0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (convolution_slave_avs_s0_agent_m0_read),                       //                .read
		.m0_waitrequest          (convolution_slave_avs_s0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (convolution_slave_avs_s0_agent_m0_writedata),                  //                .writedata
		.m0_write                (convolution_slave_avs_s0_agent_m0_write),                      //                .write
		.rp_endofpacket          (convolution_slave_avs_s0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (convolution_slave_avs_s0_agent_rp_ready),                      //                .ready
		.rp_valid                (convolution_slave_avs_s0_agent_rp_valid),                      //                .valid
		.rp_data                 (convolution_slave_avs_s0_agent_rp_data),                       //                .data
		.rp_startofpacket        (convolution_slave_avs_s0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (convolution_slave_avs_s0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (convolution_slave_avs_s0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (convolution_slave_avs_s0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (convolution_slave_avs_s0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (convolution_slave_avs_s0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (convolution_slave_avs_s0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (convolution_slave_avs_s0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (convolution_slave_avs_s0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (convolution_slave_avs_s0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (convolution_slave_avs_s0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (convolution_slave_avs_s0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (convolution_slave_avs_s0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (convolution_slave_avs_s0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_005_out_0_ready),                            // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_005_out_0_valid),                            //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_005_out_0_data),                             //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_005_out_0_error),                            //                .error
		.rdata_fifo_src_ready    (convolution_slave_avs_s0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (convolution_slave_avs_s0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (convolution_slave_avs_s0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                        //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) convolution_slave_avs_s0_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                    //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),           // clk_reset.reset
		.in_data           (convolution_slave_avs_s0_agent_rf_source_data),             //        in.data
		.in_valid          (convolution_slave_avs_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (convolution_slave_avs_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (convolution_slave_avs_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (convolution_slave_avs_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (convolution_slave_avs_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (convolution_slave_avs_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (convolution_slave_avs_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) test_pipeline_avs_s0_agent (
		.clk                     (system_pll_outclk0_clk),                                   //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),          //       clk_reset.reset
		.m0_address              (test_pipeline_avs_s0_agent_m0_address),                    //              m0.address
		.m0_burstcount           (test_pipeline_avs_s0_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (test_pipeline_avs_s0_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (test_pipeline_avs_s0_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (test_pipeline_avs_s0_agent_m0_lock),                       //                .lock
		.m0_readdata             (test_pipeline_avs_s0_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (test_pipeline_avs_s0_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (test_pipeline_avs_s0_agent_m0_read),                       //                .read
		.m0_waitrequest          (test_pipeline_avs_s0_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (test_pipeline_avs_s0_agent_m0_writedata),                  //                .writedata
		.m0_write                (test_pipeline_avs_s0_agent_m0_write),                      //                .write
		.rp_endofpacket          (test_pipeline_avs_s0_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (test_pipeline_avs_s0_agent_rp_ready),                      //                .ready
		.rp_valid                (test_pipeline_avs_s0_agent_rp_valid),                      //                .valid
		.rp_data                 (test_pipeline_avs_s0_agent_rp_data),                       //                .data
		.rp_startofpacket        (test_pipeline_avs_s0_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (test_pipeline_avs_s0_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (test_pipeline_avs_s0_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (test_pipeline_avs_s0_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (test_pipeline_avs_s0_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (test_pipeline_avs_s0_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (test_pipeline_avs_s0_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (test_pipeline_avs_s0_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (test_pipeline_avs_s0_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (test_pipeline_avs_s0_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (test_pipeline_avs_s0_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (test_pipeline_avs_s0_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (test_pipeline_avs_s0_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (test_pipeline_avs_s0_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (test_pipeline_avs_s0_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_006_out_0_ready),                        // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_006_out_0_valid),                        //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_006_out_0_data),                         //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_006_out_0_error),                        //                .error
		.rdata_fifo_src_ready    (test_pipeline_avs_s0_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (test_pipeline_avs_s0_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (test_pipeline_avs_s0_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                    //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                      //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) test_pipeline_avs_s0_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (test_pipeline_avs_s0_agent_rf_source_data),             //        in.data
		.in_valid          (test_pipeline_avs_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (test_pipeline_avs_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (test_pipeline_avs_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (test_pipeline_avs_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (test_pipeline_avs_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (test_pipeline_avs_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (test_pipeline_avs_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                 // (terminated)
		.csr_read          (1'b0),                                                  // (terminated)
		.csr_write         (1'b0),                                                  // (terminated)
		.csr_readdata      (),                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
		.almost_full_data  (),                                                      // (terminated)
		.almost_empty_data (),                                                      // (terminated)
		.in_empty          (1'b0),                                                  // (terminated)
		.out_empty         (),                                                      // (terminated)
		.in_error          (1'b0),                                                  // (terminated)
		.out_error         (),                                                      // (terminated)
		.in_channel        (1'b0),                                                  // (terminated)
		.out_channel       ()                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) systemid_control_slave_agent (
		.clk                     (system_pll_outclk0_clk),                                     //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
		.m0_address              (systemid_control_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (systemid_control_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (systemid_control_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (systemid_control_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (systemid_control_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (systemid_control_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (systemid_control_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (systemid_control_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (systemid_control_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (systemid_control_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (systemid_control_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (systemid_control_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (systemid_control_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (systemid_control_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (systemid_control_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (systemid_control_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (systemid_control_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (systemid_control_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (systemid_control_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (systemid_control_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (systemid_control_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (systemid_control_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (systemid_control_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (systemid_control_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (systemid_control_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (systemid_control_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (systemid_control_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (systemid_control_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (systemid_control_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (systemid_control_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (systemid_control_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (systemid_control_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_007_out_0_ready),                          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_007_out_0_valid),                          //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_007_out_0_data),                           //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_007_out_0_error),                          //                .error
		.rdata_fifo_src_ready    (systemid_control_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (systemid_control_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (systemid_control_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) systemid_control_slave_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                                  //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
		.in_data           (systemid_control_slave_agent_rf_source_data),             //        in.data
		.in_valid          (systemid_control_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (systemid_control_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (systemid_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (systemid_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (systemid_control_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (systemid_control_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (systemid_control_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (systemid_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (systemid_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated)
		.csr_read          (1'b0),                                                    // (terminated)
		.csr_write         (1'b0),                                                    // (terminated)
		.csr_readdata      (),                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated)
		.almost_full_data  (),                                                        // (terminated)
		.almost_empty_data (),                                                        // (terminated)
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_channel        (1'b0),                                                    // (terminated)
		.out_channel       ()                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (119),
		.PKT_ORI_BURST_SIZE_L      (117),
		.PKT_RESPONSE_STATUS_H     (116),
		.PKT_RESPONSE_STATUS_L     (115),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (97),
		.PKT_PROTECTION_H          (110),
		.PKT_PROTECTION_L          (108),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (9),
		.ST_DATA_W                 (120),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) sys_timer_s1_agent (
		.clk                     (system_pll_outclk0_clk),                           //             clk.clk
		.reset                   (Test_PipeLine_reset_reset_bridge_in_reset_reset),  //       clk_reset.reset
		.m0_address              (sys_timer_s1_agent_m0_address),                    //              m0.address
		.m0_burstcount           (sys_timer_s1_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (sys_timer_s1_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (sys_timer_s1_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (sys_timer_s1_agent_m0_lock),                       //                .lock
		.m0_readdata             (sys_timer_s1_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (sys_timer_s1_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (sys_timer_s1_agent_m0_read),                       //                .read
		.m0_waitrequest          (sys_timer_s1_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (sys_timer_s1_agent_m0_writedata),                  //                .writedata
		.m0_write                (sys_timer_s1_agent_m0_write),                      //                .write
		.rp_endofpacket          (sys_timer_s1_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (sys_timer_s1_agent_rp_ready),                      //                .ready
		.rp_valid                (sys_timer_s1_agent_rp_valid),                      //                .valid
		.rp_data                 (sys_timer_s1_agent_rp_data),                       //                .data
		.rp_startofpacket        (sys_timer_s1_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (sys_timer_s1_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (sys_timer_s1_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (sys_timer_s1_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (sys_timer_s1_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (sys_timer_s1_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (sys_timer_s1_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (sys_timer_s1_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (sys_timer_s1_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (sys_timer_s1_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (sys_timer_s1_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (sys_timer_s1_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (sys_timer_s1_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (sys_timer_s1_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (sys_timer_s1_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (sys_timer_s1_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (sys_timer_s1_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_008_out_0_ready),                // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_008_out_0_valid),                //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_008_out_0_data),                 //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_008_out_0_error),                //                .error
		.rdata_fifo_src_ready    (sys_timer_s1_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sys_timer_s1_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (sys_timer_s1_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                            //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (121),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sys_timer_s1_agent_rsp_fifo (
		.clk               (system_pll_outclk0_clk),                          //       clk.clk
		.reset             (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sys_timer_s1_agent_rf_source_data),               //        in.data
		.in_valid          (sys_timer_s1_agent_rf_source_valid),              //          .valid
		.in_ready          (sys_timer_s1_agent_rf_source_ready),              //          .ready
		.in_startofpacket  (sys_timer_s1_agent_rf_source_startofpacket),      //          .startofpacket
		.in_endofpacket    (sys_timer_s1_agent_rf_source_endofpacket),        //          .endofpacket
		.out_data          (sys_timer_s1_agent_rsp_fifo_out_data),            //       out.data
		.out_valid         (sys_timer_s1_agent_rsp_fifo_out_valid),           //          .valid
		.out_ready         (sys_timer_s1_agent_rsp_fifo_out_ready),           //          .ready
		.out_startofpacket (sys_timer_s1_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
		.out_endofpacket   (sys_timer_s1_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
		.csr_address       (2'b00),                                           // (terminated)
		.csr_read          (1'b0),                                            // (terminated)
		.csr_write         (1'b0),                                            // (terminated)
		.csr_readdata      (),                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated)
		.almost_full_data  (),                                                // (terminated)
		.almost_empty_data (),                                                // (terminated)
		.in_empty          (1'b0),                                            // (terminated)
		.out_empty         (),                                                // (terminated)
		.in_error          (1'b0),                                            // (terminated)
		.out_error         (),                                                // (terminated)
		.in_channel        (1'b0),                                            // (terminated)
		.out_channel       ()                                                 // (terminated)
	);

	soc_design_mm_interconnect_0_router router (
		.sink_ready         (test_pipeline_avm_m0_agent_cp_ready),             //      sink.ready
		.sink_valid         (test_pipeline_avm_m0_agent_cp_valid),             //          .valid
		.sink_data          (test_pipeline_avm_m0_agent_cp_data),              //          .data
		.sink_startofpacket (test_pipeline_avm_m0_agent_cp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (test_pipeline_avm_m0_agent_cp_endofpacket),       //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                //       src.ready
		.src_valid          (router_src_valid),                                //          .valid
		.src_data           (router_src_data),                                 //          .data
		.src_channel        (router_src_channel),                              //          .channel
		.src_startofpacket  (router_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                           //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (niosii_core_data_master_agent_cp_ready),          //      sink.ready
		.sink_valid         (niosii_core_data_master_agent_cp_valid),          //          .valid
		.sink_data          (niosii_core_data_master_agent_cp_data),           //          .data
		.sink_startofpacket (niosii_core_data_master_agent_cp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (niosii_core_data_master_agent_cp_endofpacket),    //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_001_src_ready),                            //       src.ready
		.src_valid          (router_001_src_valid),                            //          .valid
		.src_data           (router_001_src_data),                             //          .data
		.src_channel        (router_001_src_channel),                          //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (niosii_core_instruction_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (niosii_core_instruction_master_agent_cp_valid),         //          .valid
		.sink_data          (niosii_core_instruction_master_agent_cp_data),          //          .data
		.sink_startofpacket (niosii_core_instruction_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (niosii_core_instruction_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                                //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.src_ready          (router_002_src_ready),                                  //       src.ready
		.src_valid          (router_002_src_valid),                                  //          .valid
		.src_data           (router_002_src_data),                                   //          .data
		.src_channel        (router_002_src_channel),                                //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                          //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                             //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_003 router_003 (
		.sink_ready         (sdram_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (sdram_s1_agent_rp_valid),                         //          .valid
		.sink_data          (sdram_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (sdram_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (sdram_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_003_src_ready),                            //       src.ready
		.src_valid          (router_003_src_valid),                            //          .valid
		.src_data           (router_003_src_data),                             //          .data
		.src_channel        (router_003_src_channel),                          //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_004 router_004 (
		.sink_ready         (niosii_core_debug_mem_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (niosii_core_debug_mem_slave_agent_rp_valid),         //          .valid
		.sink_data          (niosii_core_debug_mem_slave_agent_rp_data),          //          .data
		.sink_startofpacket (niosii_core_debug_mem_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (niosii_core_debug_mem_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                             //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
		.src_ready          (router_004_src_ready),                               //       src.ready
		.src_valid          (router_004_src_valid),                               //          .valid
		.src_data           (router_004_src_data),                                //          .data
		.src_channel        (router_004_src_channel),                             //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                       //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                          //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_004 router_005 (
		.sink_ready         (sram_s1_agent_rp_ready),                          //      sink.ready
		.sink_valid         (sram_s1_agent_rp_valid),                          //          .valid
		.sink_data          (sram_s1_agent_rp_data),                           //          .data
		.sink_startofpacket (sram_s1_agent_rp_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (sram_s1_agent_rp_endofpacket),                    //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_005_src_ready),                            //       src.ready
		.src_valid          (router_005_src_valid),                            //          .valid
		.src_data           (router_005_src_data),                             //          .data
		.src_channel        (router_005_src_channel),                          //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_006 (
		.sink_ready         (jtag_avalon_jtag_slave_agent_rp_ready),           //      sink.ready
		.sink_valid         (jtag_avalon_jtag_slave_agent_rp_valid),           //          .valid
		.sink_data          (jtag_avalon_jtag_slave_agent_rp_data),            //          .data
		.sink_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket),   //          .startofpacket
		.sink_endofpacket   (jtag_avalon_jtag_slave_agent_rp_endofpacket),     //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                            //       src.ready
		.src_valid          (router_006_src_valid),                            //          .valid
		.src_data           (router_006_src_data),                             //          .data
		.src_channel        (router_006_src_channel),                          //          .channel
		.src_startofpacket  (router_006_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_007 (
		.sink_ready         (uart_com_avalon_rs232_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (uart_com_avalon_rs232_slave_agent_rp_valid),         //          .valid
		.sink_data          (uart_com_avalon_rs232_slave_agent_rp_data),          //          .data
		.sink_startofpacket (uart_com_avalon_rs232_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (uart_com_avalon_rs232_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                             //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
		.src_ready          (router_007_src_ready),                               //       src.ready
		.src_valid          (router_007_src_valid),                               //          .valid
		.src_data           (router_007_src_data),                                //          .data
		.src_channel        (router_007_src_channel),                             //          .channel
		.src_startofpacket  (router_007_src_startofpacket),                       //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                          //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_008 (
		.sink_ready         (convolution_slave_avs_s0_agent_rp_ready),         //      sink.ready
		.sink_valid         (convolution_slave_avs_s0_agent_rp_valid),         //          .valid
		.sink_data          (convolution_slave_avs_s0_agent_rp_data),          //          .data
		.sink_startofpacket (convolution_slave_avs_s0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (convolution_slave_avs_s0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_008_src_ready),                            //       src.ready
		.src_valid          (router_008_src_valid),                            //          .valid
		.src_data           (router_008_src_data),                             //          .data
		.src_channel        (router_008_src_channel),                          //          .channel
		.src_startofpacket  (router_008_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_009 (
		.sink_ready         (test_pipeline_avs_s0_agent_rp_ready),             //      sink.ready
		.sink_valid         (test_pipeline_avs_s0_agent_rp_valid),             //          .valid
		.sink_data          (test_pipeline_avs_s0_agent_rp_data),              //          .data
		.sink_startofpacket (test_pipeline_avs_s0_agent_rp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (test_pipeline_avs_s0_agent_rp_endofpacket),       //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_009_src_ready),                            //       src.ready
		.src_valid          (router_009_src_valid),                            //          .valid
		.src_data           (router_009_src_data),                             //          .data
		.src_channel        (router_009_src_channel),                          //          .channel
		.src_startofpacket  (router_009_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_009_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_010 (
		.sink_ready         (systemid_control_slave_agent_rp_ready),           //      sink.ready
		.sink_valid         (systemid_control_slave_agent_rp_valid),           //          .valid
		.sink_data          (systemid_control_slave_agent_rp_data),            //          .data
		.sink_startofpacket (systemid_control_slave_agent_rp_startofpacket),   //          .startofpacket
		.sink_endofpacket   (systemid_control_slave_agent_rp_endofpacket),     //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_010_src_ready),                            //       src.ready
		.src_valid          (router_010_src_valid),                            //          .valid
		.src_data           (router_010_src_data),                             //          .data
		.src_channel        (router_010_src_channel),                          //          .channel
		.src_startofpacket  (router_010_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_010_src_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_router_006 router_011 (
		.sink_ready         (sys_timer_s1_agent_rp_ready),                     //      sink.ready
		.sink_valid         (sys_timer_s1_agent_rp_valid),                     //          .valid
		.sink_data          (sys_timer_s1_agent_rp_data),                      //          .data
		.sink_startofpacket (sys_timer_s1_agent_rp_startofpacket),             //          .startofpacket
		.sink_endofpacket   (sys_timer_s1_agent_rp_endofpacket),               //          .endofpacket
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_011_src_ready),                            //       src.ready
		.src_valid          (router_011_src_valid),                            //          .valid
		.src_data           (router_011_src_data),                             //          .data
		.src_channel        (router_011_src_channel),                          //          .channel
		.src_startofpacket  (router_011_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_011_src_endofpacket)                       //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (9),
		.PIPELINED                 (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.VALID_WIDTH               (9),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) niosii_core_data_master_limiter (
		.clk                    (system_pll_outclk0_clk),                                //       clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.cmd_sink_ready         (router_001_src_ready),                                  //  cmd_sink.ready
		.cmd_sink_valid         (router_001_src_valid),                                  //          .valid
		.cmd_sink_data          (router_001_src_data),                                   //          .data
		.cmd_sink_channel       (router_001_src_channel),                                //          .channel
		.cmd_sink_startofpacket (router_001_src_startofpacket),                          //          .startofpacket
		.cmd_sink_endofpacket   (router_001_src_endofpacket),                            //          .endofpacket
		.cmd_src_ready          (niosii_core_data_master_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (niosii_core_data_master_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (niosii_core_data_master_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (niosii_core_data_master_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (niosii_core_data_master_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_001_src_ready),                                 //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_001_src_valid),                                 //          .valid
		.rsp_sink_channel       (rsp_mux_001_src_channel),                               //          .channel
		.rsp_sink_data          (rsp_mux_001_src_data),                                  //          .data
		.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket),                         //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_001_src_endofpacket),                           //          .endofpacket
		.rsp_src_ready          (niosii_core_data_master_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (niosii_core_data_master_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (niosii_core_data_master_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (niosii_core_data_master_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (niosii_core_data_master_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (niosii_core_data_master_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (niosii_core_data_master_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (106),
		.PKT_DEST_ID_L             (103),
		.PKT_SRC_ID_H              (102),
		.PKT_SRC_ID_L              (99),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.MAX_OUTSTANDING_RESPONSES (9),
		.PIPELINED                 (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.VALID_WIDTH               (9),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) niosii_core_instruction_master_limiter (
		.clk                    (system_pll_outclk0_clk),                                       //       clk.clk
		.reset                  (Test_PipeLine_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.cmd_sink_ready         (router_002_src_ready),                                         //  cmd_sink.ready
		.cmd_sink_valid         (router_002_src_valid),                                         //          .valid
		.cmd_sink_data          (router_002_src_data),                                          //          .data
		.cmd_sink_channel       (router_002_src_channel),                                       //          .channel
		.cmd_sink_startofpacket (router_002_src_startofpacket),                                 //          .startofpacket
		.cmd_sink_endofpacket   (router_002_src_endofpacket),                                   //          .endofpacket
		.cmd_src_ready          (niosii_core_instruction_master_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (niosii_core_instruction_master_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (niosii_core_instruction_master_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (niosii_core_instruction_master_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (niosii_core_instruction_master_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_002_src_ready),                                        //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_002_src_valid),                                        //          .valid
		.rsp_sink_channel       (rsp_mux_002_src_channel),                                      //          .channel
		.rsp_sink_data          (rsp_mux_002_src_data),                                         //          .data
		.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket),                                //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_002_src_endofpacket),                                  //          .endofpacket
		.rsp_src_ready          (niosii_core_instruction_master_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (niosii_core_instruction_master_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (niosii_core_instruction_master_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (niosii_core_instruction_master_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (niosii_core_instruction_master_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (niosii_core_instruction_master_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (niosii_core_instruction_master_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (49),
		.PKT_ADDR_L                (18),
		.PKT_BEGIN_BURST           (79),
		.PKT_BYTE_CNT_H            (65),
		.PKT_BYTE_CNT_L            (56),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_BURST_SIZE_H          (74),
		.PKT_BURST_SIZE_L          (72),
		.PKT_BURST_TYPE_H          (76),
		.PKT_BURST_TYPE_L          (75),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (66),
		.PKT_TRANS_COMPRESSED_READ (50),
		.PKT_TRANS_WRITE           (52),
		.PKT_TRANS_READ            (53),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (102),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (57),
		.OUT_BURSTWRAP_H           (71),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (31),
		.BURSTWRAP_CONST_VALUE     (31),
		.ADAPTER_VERSION           ("13.1")
	) sdram_s1_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                          //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (sdram_s1_cmd_width_adapter_src_valid),            //     sink0.valid
		.sink0_data            (sdram_s1_cmd_width_adapter_src_data),             //          .data
		.sink0_channel         (sdram_s1_cmd_width_adapter_src_channel),          //          .channel
		.sink0_startofpacket   (sdram_s1_cmd_width_adapter_src_startofpacket),    //          .startofpacket
		.sink0_endofpacket     (sdram_s1_cmd_width_adapter_src_endofpacket),      //          .endofpacket
		.sink0_ready           (sdram_s1_cmd_width_adapter_src_ready),            //          .ready
		.source0_valid         (sdram_s1_burst_adapter_source0_valid),            //   source0.valid
		.source0_data          (sdram_s1_burst_adapter_source0_data),             //          .data
		.source0_channel       (sdram_s1_burst_adapter_source0_channel),          //          .channel
		.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket),    //          .startofpacket
		.source0_endofpacket   (sdram_s1_burst_adapter_source0_endofpacket),      //          .endofpacket
		.source0_ready         (sdram_s1_burst_adapter_source0_ready)             //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (31),
		.BURSTWRAP_CONST_VALUE     (31),
		.ADAPTER_VERSION           ("13.1")
	) niosii_core_debug_mem_slave_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                          //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),                 // cr0_reset.reset
		.sink0_valid           (cmd_mux_001_src_valid),                                           //     sink0.valid
		.sink0_data            (cmd_mux_001_src_data),                                            //          .data
		.sink0_channel         (cmd_mux_001_src_channel),                                         //          .channel
		.sink0_startofpacket   (cmd_mux_001_src_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket     (cmd_mux_001_src_endofpacket),                                     //          .endofpacket
		.sink0_ready           (cmd_mux_001_src_ready),                                           //          .ready
		.source0_valid         (niosii_core_debug_mem_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (niosii_core_debug_mem_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (niosii_core_debug_mem_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (niosii_core_debug_mem_slave_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (31),
		.BURSTWRAP_CONST_VALUE     (31),
		.ADAPTER_VERSION           ("13.1")
	) sram_s1_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                          //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
		.sink0_valid           (cmd_mux_002_src_valid),                           //     sink0.valid
		.sink0_data            (cmd_mux_002_src_data),                            //          .data
		.sink0_channel         (cmd_mux_002_src_channel),                         //          .channel
		.sink0_startofpacket   (cmd_mux_002_src_startofpacket),                   //          .startofpacket
		.sink0_endofpacket     (cmd_mux_002_src_endofpacket),                     //          .endofpacket
		.sink0_ready           (cmd_mux_002_src_ready),                           //          .ready
		.source0_valid         (sram_s1_burst_adapter_source0_valid),             //   source0.valid
		.source0_data          (sram_s1_burst_adapter_source0_data),              //          .data
		.source0_channel       (sram_s1_burst_adapter_source0_channel),           //          .channel
		.source0_startofpacket (sram_s1_burst_adapter_source0_startofpacket),     //          .startofpacket
		.source0_endofpacket   (sram_s1_burst_adapter_source0_endofpacket),       //          .endofpacket
		.source0_ready         (sram_s1_burst_adapter_source0_ready)              //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) jtag_avalon_jtag_slave_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                     //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),            // cr0_reset.reset
		.sink0_valid           (cmd_mux_003_src_valid),                                      //     sink0.valid
		.sink0_data            (cmd_mux_003_src_data),                                       //          .data
		.sink0_channel         (cmd_mux_003_src_channel),                                    //          .channel
		.sink0_startofpacket   (cmd_mux_003_src_startofpacket),                              //          .startofpacket
		.sink0_endofpacket     (cmd_mux_003_src_endofpacket),                                //          .endofpacket
		.sink0_ready           (cmd_mux_003_src_ready),                                      //          .ready
		.source0_valid         (jtag_avalon_jtag_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (jtag_avalon_jtag_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (jtag_avalon_jtag_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (jtag_avalon_jtag_slave_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) uart_com_avalon_rs232_slave_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                          //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),                 // cr0_reset.reset
		.sink0_valid           (cmd_mux_004_src_valid),                                           //     sink0.valid
		.sink0_data            (cmd_mux_004_src_data),                                            //          .data
		.sink0_channel         (cmd_mux_004_src_channel),                                         //          .channel
		.sink0_startofpacket   (cmd_mux_004_src_startofpacket),                                   //          .startofpacket
		.sink0_endofpacket     (cmd_mux_004_src_endofpacket),                                     //          .endofpacket
		.sink0_ready           (cmd_mux_004_src_ready),                                           //          .ready
		.source0_valid         (uart_com_avalon_rs232_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (uart_com_avalon_rs232_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (uart_com_avalon_rs232_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (uart_com_avalon_rs232_slave_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) convolution_slave_avs_s0_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                       //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),              // cr0_reset.reset
		.sink0_valid           (cmd_mux_005_src_valid),                                        //     sink0.valid
		.sink0_data            (cmd_mux_005_src_data),                                         //          .data
		.sink0_channel         (cmd_mux_005_src_channel),                                      //          .channel
		.sink0_startofpacket   (cmd_mux_005_src_startofpacket),                                //          .startofpacket
		.sink0_endofpacket     (cmd_mux_005_src_endofpacket),                                  //          .endofpacket
		.sink0_ready           (cmd_mux_005_src_ready),                                        //          .ready
		.source0_valid         (convolution_slave_avs_s0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (convolution_slave_avs_s0_burst_adapter_source0_data),          //          .data
		.source0_channel       (convolution_slave_avs_s0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (convolution_slave_avs_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (convolution_slave_avs_s0_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) test_pipeline_avs_s0_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                   //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),          // cr0_reset.reset
		.sink0_valid           (cmd_mux_006_src_valid),                                    //     sink0.valid
		.sink0_data            (cmd_mux_006_src_data),                                     //          .data
		.sink0_channel         (cmd_mux_006_src_channel),                                  //          .channel
		.sink0_startofpacket   (cmd_mux_006_src_startofpacket),                            //          .startofpacket
		.sink0_endofpacket     (cmd_mux_006_src_endofpacket),                              //          .endofpacket
		.sink0_ready           (cmd_mux_006_src_ready),                                    //          .ready
		.source0_valid         (test_pipeline_avs_s0_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (test_pipeline_avs_s0_burst_adapter_source0_data),          //          .data
		.source0_channel       (test_pipeline_avs_s0_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (test_pipeline_avs_s0_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (test_pipeline_avs_s0_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (test_pipeline_avs_s0_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) systemid_control_slave_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                                     //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),            // cr0_reset.reset
		.sink0_valid           (cmd_mux_007_src_valid),                                      //     sink0.valid
		.sink0_data            (cmd_mux_007_src_data),                                       //          .data
		.sink0_channel         (cmd_mux_007_src_channel),                                    //          .channel
		.sink0_startofpacket   (cmd_mux_007_src_startofpacket),                              //          .startofpacket
		.sink0_endofpacket     (cmd_mux_007_src_endofpacket),                                //          .endofpacket
		.sink0_ready           (cmd_mux_007_src_ready),                                      //          .ready
		.source0_valid         (systemid_control_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (systemid_control_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (systemid_control_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (systemid_control_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (systemid_control_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (systemid_control_slave_burst_adapter_source0_ready)          //          .ready
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (97),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (92),
		.PKT_BURST_SIZE_L          (90),
		.PKT_BURST_TYPE_H          (94),
		.PKT_BURST_TYPE_L          (93),
		.PKT_BURSTWRAP_H           (89),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (120),
		.ST_CHANNEL_W              (9),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (89),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (63),
		.BURSTWRAP_CONST_VALUE     (63),
		.ADAPTER_VERSION           ("13.1")
	) sys_timer_s1_burst_adapter (
		.clk                   (system_pll_outclk0_clk),                           //       cr0.clk
		.reset                 (Test_PipeLine_reset_reset_bridge_in_reset_reset),  // cr0_reset.reset
		.sink0_valid           (cmd_mux_008_src_valid),                            //     sink0.valid
		.sink0_data            (cmd_mux_008_src_data),                             //          .data
		.sink0_channel         (cmd_mux_008_src_channel),                          //          .channel
		.sink0_startofpacket   (cmd_mux_008_src_startofpacket),                    //          .startofpacket
		.sink0_endofpacket     (cmd_mux_008_src_endofpacket),                      //          .endofpacket
		.sink0_ready           (cmd_mux_008_src_ready),                            //          .ready
		.source0_valid         (sys_timer_s1_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (sys_timer_s1_burst_adapter_source0_data),          //          .data
		.source0_channel       (sys_timer_s1_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (sys_timer_s1_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (sys_timer_s1_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (sys_timer_s1_burst_adapter_source0_ready)          //          .ready
	);

	soc_design_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                //      sink.ready
		.sink_channel       (router_src_channel),                              //          .channel
		.sink_data          (router_src_data),                                 //          .data
		.sink_startofpacket (router_src_startofpacket),                        //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                          //          .endofpacket
		.sink_valid         (router_src_valid),                                //          .valid
		.src0_ready         (cmd_demux_src0_ready),                            //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                            //          .valid
		.src0_data          (cmd_demux_src0_data),                             //          .data
		.src0_channel       (cmd_demux_src0_channel),                          //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
		.clk                (system_pll_outclk0_clk),                                //        clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset),       //  clk_reset.reset
		.sink_ready         (niosii_core_data_master_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (niosii_core_data_master_limiter_cmd_src_channel),       //           .channel
		.sink_data          (niosii_core_data_master_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (niosii_core_data_master_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (niosii_core_data_master_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (niosii_core_data_master_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_001_src0_ready),                              //       src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                              //           .valid
		.src0_data          (cmd_demux_001_src0_data),                               //           .data
		.src0_channel       (cmd_demux_001_src0_channel),                            //           .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                      //           .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),                        //           .endofpacket
		.src1_ready         (cmd_demux_001_src1_ready),                              //       src1.ready
		.src1_valid         (cmd_demux_001_src1_valid),                              //           .valid
		.src1_data          (cmd_demux_001_src1_data),                               //           .data
		.src1_channel       (cmd_demux_001_src1_channel),                            //           .channel
		.src1_startofpacket (cmd_demux_001_src1_startofpacket),                      //           .startofpacket
		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),                        //           .endofpacket
		.src2_ready         (cmd_demux_001_src2_ready),                              //       src2.ready
		.src2_valid         (cmd_demux_001_src2_valid),                              //           .valid
		.src2_data          (cmd_demux_001_src2_data),                               //           .data
		.src2_channel       (cmd_demux_001_src2_channel),                            //           .channel
		.src2_startofpacket (cmd_demux_001_src2_startofpacket),                      //           .startofpacket
		.src2_endofpacket   (cmd_demux_001_src2_endofpacket),                        //           .endofpacket
		.src3_ready         (cmd_demux_001_src3_ready),                              //       src3.ready
		.src3_valid         (cmd_demux_001_src3_valid),                              //           .valid
		.src3_data          (cmd_demux_001_src3_data),                               //           .data
		.src3_channel       (cmd_demux_001_src3_channel),                            //           .channel
		.src3_startofpacket (cmd_demux_001_src3_startofpacket),                      //           .startofpacket
		.src3_endofpacket   (cmd_demux_001_src3_endofpacket),                        //           .endofpacket
		.src4_ready         (cmd_demux_001_src4_ready),                              //       src4.ready
		.src4_valid         (cmd_demux_001_src4_valid),                              //           .valid
		.src4_data          (cmd_demux_001_src4_data),                               //           .data
		.src4_channel       (cmd_demux_001_src4_channel),                            //           .channel
		.src4_startofpacket (cmd_demux_001_src4_startofpacket),                      //           .startofpacket
		.src4_endofpacket   (cmd_demux_001_src4_endofpacket),                        //           .endofpacket
		.src5_ready         (cmd_demux_001_src5_ready),                              //       src5.ready
		.src5_valid         (cmd_demux_001_src5_valid),                              //           .valid
		.src5_data          (cmd_demux_001_src5_data),                               //           .data
		.src5_channel       (cmd_demux_001_src5_channel),                            //           .channel
		.src5_startofpacket (cmd_demux_001_src5_startofpacket),                      //           .startofpacket
		.src5_endofpacket   (cmd_demux_001_src5_endofpacket),                        //           .endofpacket
		.src6_ready         (cmd_demux_001_src6_ready),                              //       src6.ready
		.src6_valid         (cmd_demux_001_src6_valid),                              //           .valid
		.src6_data          (cmd_demux_001_src6_data),                               //           .data
		.src6_channel       (cmd_demux_001_src6_channel),                            //           .channel
		.src6_startofpacket (cmd_demux_001_src6_startofpacket),                      //           .startofpacket
		.src6_endofpacket   (cmd_demux_001_src6_endofpacket),                        //           .endofpacket
		.src7_ready         (cmd_demux_001_src7_ready),                              //       src7.ready
		.src7_valid         (cmd_demux_001_src7_valid),                              //           .valid
		.src7_data          (cmd_demux_001_src7_data),                               //           .data
		.src7_channel       (cmd_demux_001_src7_channel),                            //           .channel
		.src7_startofpacket (cmd_demux_001_src7_startofpacket),                      //           .startofpacket
		.src7_endofpacket   (cmd_demux_001_src7_endofpacket),                        //           .endofpacket
		.src8_ready         (cmd_demux_001_src8_ready),                              //       src8.ready
		.src8_valid         (cmd_demux_001_src8_valid),                              //           .valid
		.src8_data          (cmd_demux_001_src8_data),                               //           .data
		.src8_channel       (cmd_demux_001_src8_channel),                            //           .channel
		.src8_startofpacket (cmd_demux_001_src8_startofpacket),                      //           .startofpacket
		.src8_endofpacket   (cmd_demux_001_src8_endofpacket)                         //           .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
		.clk                (system_pll_outclk0_clk),                                       //        clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset),              //  clk_reset.reset
		.sink_ready         (niosii_core_instruction_master_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (niosii_core_instruction_master_limiter_cmd_src_channel),       //           .channel
		.sink_data          (niosii_core_instruction_master_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (niosii_core_instruction_master_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (niosii_core_instruction_master_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (niosii_core_instruction_master_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_002_src0_ready),                                     //       src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                                     //           .valid
		.src0_data          (cmd_demux_002_src0_data),                                      //           .data
		.src0_channel       (cmd_demux_002_src0_channel),                                   //           .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),                             //           .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),                               //           .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                                     //       src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                                     //           .valid
		.src1_data          (cmd_demux_002_src1_data),                                      //           .data
		.src1_channel       (cmd_demux_002_src1_channel),                                   //           .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),                             //           .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket),                               //           .endofpacket
		.src2_ready         (cmd_demux_002_src2_ready),                                     //       src2.ready
		.src2_valid         (cmd_demux_002_src2_valid),                                     //           .valid
		.src2_data          (cmd_demux_002_src2_data),                                      //           .data
		.src2_channel       (cmd_demux_002_src2_channel),                                   //           .channel
		.src2_startofpacket (cmd_demux_002_src2_startofpacket),                             //           .startofpacket
		.src2_endofpacket   (cmd_demux_002_src2_endofpacket)                                //           .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                               //       src.ready
		.src_valid           (cmd_mux_src_valid),                               //          .valid
		.src_data            (cmd_mux_src_data),                                //          .data
		.src_channel         (cmd_mux_src_channel),                             //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                            //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                            //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                          //          .channel
		.sink0_data          (cmd_demux_src0_data),                             //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                      //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                        //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                        //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                      //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                         //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),                //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket),                  //          .endofpacket
		.sink2_ready         (cmd_demux_002_src0_ready),                        //     sink2.ready
		.sink2_valid         (cmd_demux_002_src0_valid),                        //          .valid
		.sink2_channel       (cmd_demux_002_src0_channel),                      //          .channel
		.sink2_data          (cmd_demux_002_src0_data),                         //          .data
		.sink2_startofpacket (cmd_demux_002_src0_startofpacket),                //          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                           //          .valid
		.src_data            (cmd_mux_001_src_data),                            //          .data
		.src_channel         (cmd_mux_001_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src1_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src1_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src1_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src1_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src1_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src1_endofpacket),                  //          .endofpacket
		.sink1_ready         (cmd_demux_002_src1_ready),                        //     sink1.ready
		.sink1_valid         (cmd_demux_002_src1_valid),                        //          .valid
		.sink1_channel       (cmd_demux_002_src1_channel),                      //          .channel
		.sink1_data          (cmd_demux_002_src1_data),                         //          .data
		.sink1_startofpacket (cmd_demux_002_src1_startofpacket),                //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src1_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                           //          .valid
		.src_data            (cmd_mux_002_src_data),                            //          .data
		.src_channel         (cmd_mux_002_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src2_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src2_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src2_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src2_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src2_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src2_endofpacket),                  //          .endofpacket
		.sink1_ready         (cmd_demux_002_src2_ready),                        //     sink1.ready
		.sink1_valid         (cmd_demux_002_src2_valid),                        //          .valid
		.sink1_channel       (cmd_demux_002_src2_channel),                      //          .channel
		.sink1_data          (cmd_demux_002_src2_data),                         //          .data
		.sink1_startofpacket (cmd_demux_002_src2_startofpacket),                //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src2_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                           //          .valid
		.src_data            (cmd_mux_003_src_data),                            //          .data
		.src_channel         (cmd_mux_003_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src3_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src3_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src3_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src3_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src3_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src3_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_004 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_004_src_valid),                           //          .valid
		.src_data            (cmd_mux_004_src_data),                            //          .data
		.src_channel         (cmd_mux_004_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src4_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src4_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src4_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src4_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src4_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src4_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_005 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_005_src_valid),                           //          .valid
		.src_data            (cmd_mux_005_src_data),                            //          .data
		.src_channel         (cmd_mux_005_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src5_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src5_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src5_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src5_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src5_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src5_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_006 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_006_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_006_src_valid),                           //          .valid
		.src_data            (cmd_mux_006_src_data),                            //          .data
		.src_channel         (cmd_mux_006_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_006_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_006_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src6_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src6_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src6_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src6_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src6_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src6_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_007 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_007_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_007_src_valid),                           //          .valid
		.src_data            (cmd_mux_007_src_data),                            //          .data
		.src_channel         (cmd_mux_007_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_007_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_007_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src7_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src7_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src7_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src7_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src7_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src7_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_008 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_008_src_ready),                           //       src.ready
		.src_valid           (cmd_mux_008_src_valid),                           //          .valid
		.src_data            (cmd_mux_008_src_data),                            //          .data
		.src_channel         (cmd_mux_008_src_channel),                         //          .channel
		.src_startofpacket   (cmd_mux_008_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (cmd_mux_008_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (cmd_demux_001_src8_ready),                        //     sink0.ready
		.sink0_valid         (cmd_demux_001_src8_valid),                        //          .valid
		.sink0_channel       (cmd_demux_001_src8_channel),                      //          .channel
		.sink0_data          (cmd_demux_001_src8_data),                         //          .data
		.sink0_startofpacket (cmd_demux_001_src8_startofpacket),                //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src8_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (sdram_s1_rsp_width_adapter_src_ready),            //      sink.ready
		.sink_channel       (sdram_s1_rsp_width_adapter_src_channel),          //          .channel
		.sink_data          (sdram_s1_rsp_width_adapter_src_data),             //          .data
		.sink_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket),    //          .startofpacket
		.sink_endofpacket   (sdram_s1_rsp_width_adapter_src_endofpacket),      //          .endofpacket
		.sink_valid         (sdram_s1_rsp_width_adapter_src_valid),            //          .valid
		.src0_ready         (rsp_demux_src0_ready),                            //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                            //          .valid
		.src0_data          (rsp_demux_src0_data),                             //          .data
		.src0_channel       (rsp_demux_src0_channel),                          //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                    //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                      //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                            //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                            //          .valid
		.src1_data          (rsp_demux_src1_data),                             //          .data
		.src1_channel       (rsp_demux_src1_channel),                          //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                    //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket),                      //          .endofpacket
		.src2_ready         (rsp_demux_src2_ready),                            //      src2.ready
		.src2_valid         (rsp_demux_src2_valid),                            //          .valid
		.src2_data          (rsp_demux_src2_data),                             //          .data
		.src2_channel       (rsp_demux_src2_channel),                          //          .channel
		.src2_startofpacket (rsp_demux_src2_startofpacket),                    //          .startofpacket
		.src2_endofpacket   (rsp_demux_src2_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                            //      sink.ready
		.sink_channel       (router_004_src_channel),                          //          .channel
		.sink_data          (router_004_src_data),                             //          .data
		.sink_startofpacket (router_004_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_004_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_001_src0_data),                         //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                  //          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                        //      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                        //          .valid
		.src1_data          (rsp_demux_001_src1_data),                         //          .data
		.src1_channel       (rsp_demux_001_src1_channel),                      //          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),                //          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                            //      sink.ready
		.sink_channel       (router_005_src_channel),                          //          .channel
		.sink_data          (router_005_src_data),                             //          .data
		.sink_startofpacket (router_005_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_005_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_002_src0_data),                         //          .data
		.src0_channel       (rsp_demux_002_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),                  //          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                        //      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                        //          .valid
		.src1_data          (rsp_demux_002_src1_data),                         //          .data
		.src1_channel       (rsp_demux_002_src1_channel),                      //          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),                //          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_003 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                            //      sink.ready
		.sink_channel       (router_006_src_channel),                          //          .channel
		.sink_data          (router_006_src_data),                             //          .data
		.sink_startofpacket (router_006_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_006_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_003_src0_data),                         //          .data
		.src0_channel       (rsp_demux_003_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_004 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                            //      sink.ready
		.sink_channel       (router_007_src_channel),                          //          .channel
		.sink_data          (router_007_src_data),                             //          .data
		.sink_startofpacket (router_007_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_007_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_004_src0_data),                         //          .data
		.src0_channel       (rsp_demux_004_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_005 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_008_src_ready),                            //      sink.ready
		.sink_channel       (router_008_src_channel),                          //          .channel
		.sink_data          (router_008_src_data),                             //          .data
		.sink_startofpacket (router_008_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_008_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_005_src0_data),                         //          .data
		.src0_channel       (rsp_demux_005_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_006 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_009_src_ready),                            //      sink.ready
		.sink_channel       (router_009_src_channel),                          //          .channel
		.sink_data          (router_009_src_data),                             //          .data
		.sink_startofpacket (router_009_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_009_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_009_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_006_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_006_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_006_src0_data),                         //          .data
		.src0_channel       (rsp_demux_006_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_006_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_006_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_007 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_010_src_ready),                            //      sink.ready
		.sink_channel       (router_010_src_channel),                          //          .channel
		.sink_data          (router_010_src_data),                             //          .data
		.sink_startofpacket (router_010_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_010_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_010_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_007_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_007_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_007_src0_data),                         //          .data
		.src0_channel       (rsp_demux_007_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_007_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_007_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_cmd_demux rsp_demux_008 (
		.clk                (system_pll_outclk0_clk),                          //       clk.clk
		.reset              (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_011_src_ready),                            //      sink.ready
		.sink_channel       (router_011_src_channel),                          //          .channel
		.sink_data          (router_011_src_data),                             //          .data
		.sink_startofpacket (router_011_src_startofpacket),                    //          .startofpacket
		.sink_endofpacket   (router_011_src_endofpacket),                      //          .endofpacket
		.sink_valid         (router_011_src_valid),                            //          .valid
		.src0_ready         (rsp_demux_008_src0_ready),                        //      src0.ready
		.src0_valid         (rsp_demux_008_src0_valid),                        //          .valid
		.src0_data          (rsp_demux_008_src0_data),                         //          .data
		.src0_channel       (rsp_demux_008_src0_channel),                      //          .channel
		.src0_startofpacket (rsp_demux_008_src0_startofpacket),                //          .startofpacket
		.src0_endofpacket   (rsp_demux_008_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                               //       src.ready
		.src_valid           (rsp_mux_src_valid),                               //          .valid
		.src_data            (rsp_mux_src_data),                                //          .data
		.src_channel         (rsp_mux_src_channel),                             //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                            //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                            //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                          //          .channel
		.sink0_data          (rsp_demux_src0_data),                             //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket)                       //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                           //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                           //          .valid
		.src_data            (rsp_mux_001_src_data),                            //          .data
		.src_channel         (rsp_mux_001_src_channel),                         //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (rsp_demux_src1_ready),                            //     sink0.ready
		.sink0_valid         (rsp_demux_src1_valid),                            //          .valid
		.sink0_channel       (rsp_demux_src1_channel),                          //          .channel
		.sink0_data          (rsp_demux_src1_data),                             //          .data
		.sink0_startofpacket (rsp_demux_src1_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src1_endofpacket),                      //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                        //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                        //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                      //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                         //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                  //          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                        //     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                        //          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                      //          .channel
		.sink2_data          (rsp_demux_002_src0_data),                         //          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                  //          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                        //     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                        //          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                      //          .channel
		.sink3_data          (rsp_demux_003_src0_data),                         //          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                //          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket),                  //          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),                        //     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),                        //          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),                      //          .channel
		.sink4_data          (rsp_demux_004_src0_data),                         //          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),                //          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),                  //          .endofpacket
		.sink5_ready         (rsp_demux_005_src0_ready),                        //     sink5.ready
		.sink5_valid         (rsp_demux_005_src0_valid),                        //          .valid
		.sink5_channel       (rsp_demux_005_src0_channel),                      //          .channel
		.sink5_data          (rsp_demux_005_src0_data),                         //          .data
		.sink5_startofpacket (rsp_demux_005_src0_startofpacket),                //          .startofpacket
		.sink5_endofpacket   (rsp_demux_005_src0_endofpacket),                  //          .endofpacket
		.sink6_ready         (rsp_demux_006_src0_ready),                        //     sink6.ready
		.sink6_valid         (rsp_demux_006_src0_valid),                        //          .valid
		.sink6_channel       (rsp_demux_006_src0_channel),                      //          .channel
		.sink6_data          (rsp_demux_006_src0_data),                         //          .data
		.sink6_startofpacket (rsp_demux_006_src0_startofpacket),                //          .startofpacket
		.sink6_endofpacket   (rsp_demux_006_src0_endofpacket),                  //          .endofpacket
		.sink7_ready         (rsp_demux_007_src0_ready),                        //     sink7.ready
		.sink7_valid         (rsp_demux_007_src0_valid),                        //          .valid
		.sink7_channel       (rsp_demux_007_src0_channel),                      //          .channel
		.sink7_data          (rsp_demux_007_src0_data),                         //          .data
		.sink7_startofpacket (rsp_demux_007_src0_startofpacket),                //          .startofpacket
		.sink7_endofpacket   (rsp_demux_007_src0_endofpacket),                  //          .endofpacket
		.sink8_ready         (rsp_demux_008_src0_ready),                        //     sink8.ready
		.sink8_valid         (rsp_demux_008_src0_valid),                        //          .valid
		.sink8_channel       (rsp_demux_008_src0_channel),                      //          .channel
		.sink8_data          (rsp_demux_008_src0_data),                         //          .data
		.sink8_startofpacket (rsp_demux_008_src0_startofpacket),                //          .startofpacket
		.sink8_endofpacket   (rsp_demux_008_src0_endofpacket)                   //          .endofpacket
	);

	soc_design_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
		.clk                 (system_pll_outclk0_clk),                          //       clk.clk
		.reset               (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                           //       src.ready
		.src_valid           (rsp_mux_002_src_valid),                           //          .valid
		.src_data            (rsp_mux_002_src_data),                            //          .data
		.src_channel         (rsp_mux_002_src_channel),                         //          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                   //          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                     //          .endofpacket
		.sink0_ready         (rsp_demux_src2_ready),                            //     sink0.ready
		.sink0_valid         (rsp_demux_src2_valid),                            //          .valid
		.sink0_channel       (rsp_demux_src2_channel),                          //          .channel
		.sink0_data          (rsp_demux_src2_data),                             //          .data
		.sink0_startofpacket (rsp_demux_src2_startofpacket),                    //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src2_endofpacket),                      //          .endofpacket
		.sink1_ready         (rsp_demux_001_src1_ready),                        //     sink1.ready
		.sink1_valid         (rsp_demux_001_src1_valid),                        //          .valid
		.sink1_channel       (rsp_demux_001_src1_channel),                      //          .channel
		.sink1_data          (rsp_demux_001_src1_data),                         //          .data
		.sink1_startofpacket (rsp_demux_001_src1_startofpacket),                //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src1_endofpacket),                  //          .endofpacket
		.sink2_ready         (rsp_demux_002_src1_ready),                        //     sink2.ready
		.sink2_valid         (rsp_demux_002_src1_valid),                        //          .valid
		.sink2_channel       (rsp_demux_002_src1_channel),                      //          .channel
		.sink2_data          (rsp_demux_002_src1_data),                         //          .data
		.sink2_startofpacket (rsp_demux_002_src1_startofpacket),                //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src1_endofpacket)                   //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (49),
		.IN_PKT_ADDR_L                 (18),
		.IN_PKT_DATA_H                 (15),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (17),
		.IN_PKT_BYTEEN_L               (16),
		.IN_PKT_BYTE_CNT_H             (65),
		.IN_PKT_BYTE_CNT_L             (56),
		.IN_PKT_TRANS_COMPRESSED_READ  (50),
		.IN_PKT_TRANS_WRITE            (52),
		.IN_PKT_BURSTWRAP_H            (71),
		.IN_PKT_BURSTWRAP_L            (66),
		.IN_PKT_BURST_SIZE_H           (74),
		.IN_PKT_BURST_SIZE_L           (72),
		.IN_PKT_RESPONSE_STATUS_H      (98),
		.IN_PKT_RESPONSE_STATUS_L      (97),
		.IN_PKT_TRANS_EXCLUSIVE        (55),
		.IN_PKT_BURST_TYPE_H           (76),
		.IN_PKT_BURST_TYPE_L           (75),
		.IN_PKT_ORI_BURST_SIZE_L       (99),
		.IN_PKT_ORI_BURST_SIZE_H       (101),
		.IN_ST_DATA_W                  (102),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (92),
		.OUT_PKT_BURST_SIZE_L          (90),
		.OUT_PKT_RESPONSE_STATUS_H     (116),
		.OUT_PKT_RESPONSE_STATUS_L     (115),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (94),
		.OUT_PKT_BURST_TYPE_L          (93),
		.OUT_PKT_ORI_BURST_SIZE_L      (117),
		.OUT_PKT_ORI_BURST_SIZE_H      (119),
		.OUT_ST_DATA_W                 (120),
		.ST_CHANNEL_W                  (9),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) sdram_s1_rsp_width_adapter (
		.clk                  (system_pll_outclk0_clk),                          //       clk.clk
		.reset                (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (router_003_src_valid),                            //      sink.valid
		.in_channel           (router_003_src_channel),                          //          .channel
		.in_startofpacket     (router_003_src_startofpacket),                    //          .startofpacket
		.in_endofpacket       (router_003_src_endofpacket),                      //          .endofpacket
		.in_ready             (router_003_src_ready),                            //          .ready
		.in_data              (router_003_src_data),                             //          .data
		.out_endofpacket      (sdram_s1_rsp_width_adapter_src_endofpacket),      //       src.endofpacket
		.out_data             (sdram_s1_rsp_width_adapter_src_data),             //          .data
		.out_channel          (sdram_s1_rsp_width_adapter_src_channel),          //          .channel
		.out_valid            (sdram_s1_rsp_width_adapter_src_valid),            //          .valid
		.out_ready            (sdram_s1_rsp_width_adapter_src_ready),            //          .ready
		.out_startofpacket    (sdram_s1_rsp_width_adapter_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                           // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (89),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (92),
		.IN_PKT_BURST_SIZE_L           (90),
		.IN_PKT_RESPONSE_STATUS_H      (116),
		.IN_PKT_RESPONSE_STATUS_L      (115),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (94),
		.IN_PKT_BURST_TYPE_L           (93),
		.IN_PKT_ORI_BURST_SIZE_L       (117),
		.IN_PKT_ORI_BURST_SIZE_H       (119),
		.IN_ST_DATA_W                  (120),
		.OUT_PKT_ADDR_H                (49),
		.OUT_PKT_ADDR_L                (18),
		.OUT_PKT_DATA_H                (15),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (17),
		.OUT_PKT_BYTEEN_L              (16),
		.OUT_PKT_BYTE_CNT_H            (65),
		.OUT_PKT_BYTE_CNT_L            (56),
		.OUT_PKT_TRANS_COMPRESSED_READ (50),
		.OUT_PKT_BURST_SIZE_H          (74),
		.OUT_PKT_BURST_SIZE_L          (72),
		.OUT_PKT_RESPONSE_STATUS_H     (98),
		.OUT_PKT_RESPONSE_STATUS_L     (97),
		.OUT_PKT_TRANS_EXCLUSIVE       (55),
		.OUT_PKT_BURST_TYPE_H          (76),
		.OUT_PKT_BURST_TYPE_L          (75),
		.OUT_PKT_ORI_BURST_SIZE_L      (99),
		.OUT_PKT_ORI_BURST_SIZE_H      (101),
		.OUT_ST_DATA_W                 (102),
		.ST_CHANNEL_W                  (9),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) sdram_s1_cmd_width_adapter (
		.clk                  (system_pll_outclk0_clk),                          //       clk.clk
		.reset                (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                               //      sink.valid
		.in_channel           (cmd_mux_src_channel),                             //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                       //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                         //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                               //          .ready
		.in_data              (cmd_mux_src_data),                                //          .data
		.out_endofpacket      (sdram_s1_cmd_width_adapter_src_endofpacket),      //       src.endofpacket
		.out_data             (sdram_s1_cmd_width_adapter_src_data),             //          .data
		.out_channel          (sdram_s1_cmd_width_adapter_src_channel),          //          .channel
		.out_valid            (sdram_s1_cmd_width_adapter_src_valid),            //          .valid
		.out_ready            (sdram_s1_cmd_width_adapter_src_ready),            //          .ready
		.out_startofpacket    (sdram_s1_cmd_width_adapter_src_startofpacket),    //          .startofpacket
		.in_command_size_data (3'b000)                                           // (terminated)
	);

	soc_design_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (18),
		.inUsePackets    (0),
		.inDataWidth     (18),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (18),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (system_pll_outclk0_clk),                          // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (sdram_s1_agent_rdata_fifo_out_data),              //     in_0.data
		.in_0_valid     (sdram_s1_agent_rdata_fifo_out_valid),             //         .valid
		.in_0_ready     (sdram_s1_agent_rdata_fifo_out_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                   //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                   //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                    //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                                 // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
		.in_0_data      (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),                       //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),                      //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),                      //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)                       //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_002 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                          // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (sram_s1_agent_rdata_fifo_src_data),               //     in_0.data
		.in_0_valid     (sram_s1_agent_rdata_fifo_src_valid),              //         .valid
		.in_0_ready     (sram_s1_agent_rdata_fifo_src_ready),              //         .ready
		.out_0_data     (avalon_st_adapter_002_out_0_data),                //    out_0.data
		.out_0_valid    (avalon_st_adapter_002_out_0_valid),               //         .valid
		.out_0_ready    (avalon_st_adapter_002_out_0_ready),               //         .ready
		.out_0_error    (avalon_st_adapter_002_out_0_error)                //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_003 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                            // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset),   // in_rst_0.reset
		.in_0_data      (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_003_out_0_data),                  //    out_0.data
		.out_0_valid    (avalon_st_adapter_003_out_0_valid),                 //         .valid
		.out_0_ready    (avalon_st_adapter_003_out_0_ready),                 //         .ready
		.out_0_error    (avalon_st_adapter_003_out_0_error)                  //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_004 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                                 // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
		.in_0_data      (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_004_out_0_data),                       //    out_0.data
		.out_0_valid    (avalon_st_adapter_004_out_0_valid),                      //         .valid
		.out_0_ready    (avalon_st_adapter_004_out_0_ready),                      //         .ready
		.out_0_error    (avalon_st_adapter_004_out_0_error)                       //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_005 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                              // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset),     // in_rst_0.reset
		.in_0_data      (convolution_slave_avs_s0_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (convolution_slave_avs_s0_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (convolution_slave_avs_s0_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_005_out_0_data),                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_005_out_0_valid),                   //         .valid
		.out_0_ready    (avalon_st_adapter_005_out_0_ready),                   //         .ready
		.out_0_error    (avalon_st_adapter_005_out_0_error)                    //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_006 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                          // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (test_pipeline_avs_s0_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (test_pipeline_avs_s0_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (test_pipeline_avs_s0_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_006_out_0_data),                //    out_0.data
		.out_0_valid    (avalon_st_adapter_006_out_0_valid),               //         .valid
		.out_0_ready    (avalon_st_adapter_006_out_0_ready),               //         .ready
		.out_0_error    (avalon_st_adapter_006_out_0_error)                //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_007 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                            // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset),   // in_rst_0.reset
		.in_0_data      (systemid_control_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (systemid_control_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (systemid_control_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_007_out_0_data),                  //    out_0.data
		.out_0_valid    (avalon_st_adapter_007_out_0_valid),                 //         .valid
		.out_0_ready    (avalon_st_adapter_007_out_0_ready),                 //         .ready
		.out_0_error    (avalon_st_adapter_007_out_0_error)                  //         .error
	);

	soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_008 (
		.in_clk_0_clk   (system_pll_outclk0_clk),                          // in_clk_0.clk
		.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (sys_timer_s1_agent_rdata_fifo_src_data),          //     in_0.data
		.in_0_valid     (sys_timer_s1_agent_rdata_fifo_src_valid),         //         .valid
		.in_0_ready     (sys_timer_s1_agent_rdata_fifo_src_ready),         //         .ready
		.out_0_data     (avalon_st_adapter_008_out_0_data),                //    out_0.data
		.out_0_valid    (avalon_st_adapter_008_out_0_valid),               //         .valid
		.out_0_ready    (avalon_st_adapter_008_out_0_ready),               //         .ready
		.out_0_error    (avalon_st_adapter_008_out_0_error)                //         .error
	);

endmodule
