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// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module GALAGA_DROM (
  a,
  d,
  clk,
  we,
  spo
);

input wire [14 : 0] a;
input wire [7 : 0] d;
input wire clk;
input wire we;
output wire [7 : 0] spo;

  dist_mem_gen_v8_0 #(
    .C_FAMILY("zynq"),
    .C_ADDR_WIDTH(15),
    .C_DEFAULT_DATA("0"),
    .C_DEPTH(32768),
    .C_HAS_CLK(1),
    .C_HAS_D(1),
    .C_HAS_DPO(0),
    .C_HAS_DPRA(0),
    .C_HAS_I_CE(0),
    .C_HAS_QDPO(0),
    .C_HAS_QDPO_CE(0),
    .C_HAS_QDPO_CLK(0),
    .C_HAS_QDPO_RST(0),
    .C_HAS_QDPO_SRST(0),
    .C_HAS_QSPO(0),
    .C_HAS_QSPO_CE(0),
    .C_HAS_QSPO_RST(0),
    .C_HAS_QSPO_SRST(0),
    .C_HAS_SPO(1),
    .C_HAS_WE(1),
    .C_MEM_INIT_FILE("no_coe_file_loaded"),
    .C_ELABORATION_DIR("./"),
    .C_MEM_TYPE(1),
    .C_PIPELINE_STAGES(0),
    .C_QCE_JOINED(0),
    .C_QUALIFY_WE(0),
    .C_READ_MIF(0),
    .C_REG_A_D_INPUTS(0),
    .C_REG_DPRA_INPUT(0),
    .C_SYNC_ENABLE(1),
    .C_WIDTH(8),
    .C_PARSER_TYPE(1)
  ) inst (
    .a(a),
    .d(d),
    .dpra(15'B0),
    .clk(clk),
    .we(we),
    .i_ce(1'D1),
    .qspo_ce(1'D1),
    .qdpo_ce(1'D1),
    .qdpo_clk(1'D0),
    .qspo_rst(1'D0),
    .qdpo_rst(1'D0),
    .qspo_srst(1'D0),
    .qdpo_srst(1'D0),
    .spo(spo),
    .dpo(),
    .qspo(),
    .qdpo()
  );
endmodule
