// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date        : Thu Oct 26 22:46:57 2017
// Host        : Juice-Laptop running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_sim_netlist.v
// Design      : RAT_RegisterFile_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "RAT_RegisterFile_0_0,RegisterFile,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "RegisterFile,Vivado 2016.4" *) 
(* NotValidForBitStream *)
module RAT_RegisterFile_0_0
   (D_IN,
    DX_OUT,
    DY_OUT,
    ADRX,
    ADRY,
    WE,
    CLK);
  input [7:0]D_IN;
  output [7:0]DX_OUT;
  output [7:0]DY_OUT;
  input [4:0]ADRX;
  input [4:0]ADRY;
  input WE;
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;

  wire [4:0]ADRX;
  wire [4:0]ADRY;
  wire CLK;
  wire [7:0]DX_OUT;
  wire [7:0]DY_OUT;
  wire [7:0]D_IN;
  wire WE;

  RAT_RegisterFile_0_0_RegisterFile U0
       (.ADRX(ADRX),
        .ADRY(ADRY),
        .CLK(CLK),
        .DX_OUT(DX_OUT),
        .DY_OUT(DY_OUT),
        .D_IN(D_IN),
        .WE(WE));
endmodule

(* ORIG_REF_NAME = "RegisterFile" *) 
module RAT_RegisterFile_0_0_RegisterFile
   (DY_OUT,
    DX_OUT,
    CLK,
    D_IN,
    WE,
    ADRX,
    ADRY);
  output [7:0]DY_OUT;
  output [7:0]DX_OUT;
  input CLK;
  input [7:0]D_IN;
  input WE;
  input [4:0]ADRX;
  input [4:0]ADRY;

  wire [4:0]ADRX;
  wire [4:0]ADRY;
  wire CLK;
  wire [7:0]DX_OUT;
  wire [7:0]DY_OUT;
  wire [7:0]D_IN;
  wire WE;

  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_0_0
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[0]),
        .DPO(DY_OUT[0]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[0]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_1_1
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[1]),
        .DPO(DY_OUT[1]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[1]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_2_2
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[2]),
        .DPO(DY_OUT[2]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[2]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_3_3
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[3]),
        .DPO(DY_OUT[3]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[3]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_4_4
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[4]),
        .DPO(DY_OUT[4]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[4]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_5_5
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[5]),
        .DPO(DY_OUT[5]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[5]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_6_6
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[6]),
        .DPO(DY_OUT[6]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[6]),
        .WCLK(CLK),
        .WE(WE));
  RAM32X1D #(
    .INIT(32'h00000000)) 
    REG_reg_0_31_7_7
       (.A0(ADRX[0]),
        .A1(ADRX[1]),
        .A2(ADRX[2]),
        .A3(ADRX[3]),
        .A4(ADRX[4]),
        .D(D_IN[7]),
        .DPO(DY_OUT[7]),
        .DPRA0(ADRY[0]),
        .DPRA1(ADRY[1]),
        .DPRA2(ADRY[2]),
        .DPRA3(ADRY[3]),
        .DPRA4(ADRY[4]),
        .SPO(DX_OUT[7]),
        .WCLK(CLK),
        .WE(WE));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
