// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="vectoradd,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=65,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=10,HLS_SYN_LUT=149}" *)

module vectoradd (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_idle,
        ap_ready,
        in0,
        in0_ap_vld,
        in0_ap_ack,
        in1,
        in1_ap_vld,
        in1_ap_ack,
        out_r,
        out_r_ap_vld,
        out_r_ap_ack
);

parameter    ap_ST_fsm_state1 = 2'd1;
parameter    ap_ST_fsm_state2 = 2'd2;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
output   ap_idle;
output   ap_ready;
input  [31:0] in0;
input   in0_ap_vld;
output   in0_ap_ack;
input  [31:0] in1;
input   in1_ap_vld;
output   in1_ap_ack;
output  [31:0] out_r;
output   out_r_ap_vld;
input   out_r_ap_ack;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg in0_ap_ack;
reg in1_ap_ack;
reg out_r_ap_vld;

(* fsm_encoding = "none" *) reg   [1:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    in0_blk_n;
wire    ap_CS_fsm_state2;
wire   [0:0] exitcond_fu_64_p2;
reg    in1_blk_n;
reg    out_r_blk_n;
wire   [6:0] i_1_fu_70_p2;
reg    ap_block_state2;
reg    ap_sig_ioackin_out_r_ap_ack;
reg    ap_block_state2_io;
reg   [6:0] i_reg_53;
reg    ap_reg_ioackin_out_r_ap_ack;
reg   [1:0] ap_NS_fsm;
reg    ap_condition_100;
reg    ap_condition_57;

// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 ap_reg_ioackin_out_r_ap_ack = 1'b0;
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_reg_ioackin_out_r_ap_ack <= 1'b0;
    end else begin
        if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
            if ((1'b1 == ap_condition_57)) begin
                ap_reg_ioackin_out_r_ap_ack <= 1'b0;
            end else if ((1'b1 == ap_condition_100)) begin
                ap_reg_ioackin_out_r_ap_ack <= 1'b1;
            end
        end
    end
end

always @ (posedge ap_clk) begin
    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        i_reg_53 <= i_1_fu_70_p2;
    end else if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
        i_reg_53 <= 7'd0;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((ap_reg_ioackin_out_r_ap_ack == 1'b0)) begin
        ap_sig_ioackin_out_r_ap_ack = out_r_ap_ack;
    end else begin
        ap_sig_ioackin_out_r_ap_ack = 1'b1;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        in0_ap_ack = 1'b1;
    end else begin
        in0_ap_ack = 1'b0;
    end
end

always @ (*) begin
    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        in0_blk_n = in0_ap_vld;
    end else begin
        in0_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        in1_ap_ack = 1'b1;
    end else begin
        in1_ap_ack = 1'b0;
    end
end

always @ (*) begin
    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        in1_blk_n = in1_ap_vld;
    end else begin
        in1_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (ap_reg_ioackin_out_r_ap_ack == 1'b0) & (1'b1 == ap_CS_fsm_state2))) begin
        out_r_ap_vld = 1'b1;
    end else begin
        out_r_ap_vld = 1'b0;
    end
end

always @ (*) begin
    if (((exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
        out_r_blk_n = out_r_ap_ack;
    end else begin
        out_r_blk_n = 1'b1;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else if ((~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (exitcond_fu_64_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

always @ (*) begin
    ap_block_state2 = (((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));
end

always @ (*) begin
    ap_block_state2_io = ((exitcond_fu_64_p2 == 1'd0) & (ap_sig_ioackin_out_r_ap_ack == 1'b0));
end

always @ (*) begin
    ap_condition_100 = (~(((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0))) & (out_r_ap_ack == 1'b1));
end

always @ (*) begin
    ap_condition_57 = ~((1'b1 == ap_block_state2_io) | ((exitcond_fu_64_p2 == 1'd0) & (in1_ap_vld == 1'b0)) | ((exitcond_fu_64_p2 == 1'd0) & (in0_ap_vld == 1'b0)));
end

assign exitcond_fu_64_p2 = ((i_reg_53 == 7'd64) ? 1'b1 : 1'b0);

assign i_1_fu_70_p2 = (i_reg_53 + 7'd1);

assign out_r = (in0 + in1);

endmodule //vectoradd
