//--------------------------------------------------------------------------------
// Project    : SWITCH
// File       : gmii_if.v
// Version    : 0.2
// Author     : Shreejith S
//
// Description: GMII Interface Description - XILINX
//
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
//
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// PART OF THIS FILE AT ALL TIMES.
//
// Description:  This module creates a Gigabit Media Independent
//               Interface (GMII) by instantiating Input/Output buffers
//               and Input/Output flip-flops as required.
//
//               This interface is used to connect the Ethernet MAC to
//               an external Ethernet PHY via GMII connection.
//
//               The GMII receiver clocking logic is also defined here: the
//               receiver clock received from the PHY is unique and cannot be
//               shared across multiple instantiations of the core.  For the
//               receiver clock:
//
//               A BUFIO/BUFR combination is used for the input clock to allow
//               the use of IODELAYs on the DATA.
//------------------------------------------------------------------------------

`timescale 1 ps / 1 ps


module gmii_if (
    // Synchronous resets
    input            tx_reset,
    input            rx_reset,

    // Current operating speed is 10/100
    input            speed_is_10_100,

    // The following ports are the GMII physical interface: these will be at
    // pins on the FPGA
	 (* IOB = "TRUE" *)
    output reg [7:0] gmii_txd,
	 (* IOB = "TRUE" *)
    output reg       gmii_tx_en,
	 (* IOB = "TRUE" *)
    output reg       gmii_tx_er,
    output           gmii_tx_clk,
    input            gmii_crs,
    input            gmii_col,
    input      [7:0] gmii_rxd,
    input            gmii_rx_dv,
    input            gmii_rx_er,
    input            gmii_rx_clk,

    // The following ports are the internal GMII connections from IOB logic to
    // the TEMAC core
    input      [7:0] txd_from_mac,
    input            tx_en_from_mac,
    input            tx_er_from_mac,
    input            tx_clk,
    output           crs_to_mac,
    output           col_to_mac,
	 (* IOB = "TRUE" *)
    output reg [7:0] rxd_to_mac,
	 (* IOB = "TRUE" *)
    output reg       rx_dv_to_mac,
	 (* IOB = "TRUE" *)
    output reg       rx_er_to_mac,

    // Receiver clock for the MAC and Client Logic
    output           rx_clk

    );


  //----------------------------------------------------------------------------
  // internal signals
  //----------------------------------------------------------------------------

  (* ASYNC_REG = "TRUE" *)
  reg             gmii_col_reg;
  reg             gmii_col_reg_reg ;

  wire            gmii_rx_dv_delay;
  wire            gmii_rx_er_delay;
  wire   [7:0]    gmii_rxd_delay;
  wire            gmii_rx_clk_bufio;

  wire            rx_clk_int;


  //----------------------------------------------------------------------------
  // GMII Transmitter Clock Management :
  // drive gmii_tx_clk through IOB onto GMII interface
  //----------------------------------------------------------------------------


   // Instantiate a DDR output register.  This is a good way to drive
   // GMII_TX_CLK since the clock-to-PAD delay will be the same as that
   // for data driven from IOB Ouput flip-flops eg gmii_rxd[7:0].
   // This is set to produce an inverted clock w.r.t. gmii_tx_clk_int
   // so that the rising edge is centralised within the
   // gmii_rxd[7:0] valid window.
   ODDR gmii_tx_clk_ddr_iob (
      .Q                (gmii_tx_clk),
      .C                (tx_clk),
      .CE               (1'b1),
      .D1               (1'b0),
      .D2               (1'b1),
      .R                (1'b0),
      .S                (1'b0)
   );


   //---------------------------------------------------------------------------
   // GMII Transmitter Logic : drive TX signals through IOBs registers onto
   // GMII interface
   //---------------------------------------------------------------------------


   // Infer IOB Output flip-flops.
   always @(posedge tx_clk)
   begin
      gmii_tx_en           <= tx_en_from_mac;
      gmii_tx_er           <= tx_er_from_mac;
      gmii_txd             <= txd_from_mac;
   end


   // GMII_CRS is an asynchronous signal which is routed straight through to the
   // core
   assign crs_to_mac = gmii_crs;


   // GMII_COL is an asynchronous signal.  Here is registered, then 'stretched'
   // to ensure that the MAC will see it.
   always @(posedge tx_clk)
   begin
      if (tx_reset == 1'b1) begin
         gmii_col_reg         <= 1'b0;
         gmii_col_reg_reg     <= 1'b0;
      end
      else begin
         gmii_col_reg         <= gmii_col;
         gmii_col_reg_reg     <= gmii_col_reg;
      end
   end

   assign col_to_mac = gmii_col_reg_reg | gmii_col_reg | gmii_col;


   //---------------------------------------------------------------------------
   // GMII Receiver Clock Logic
   //---------------------------------------------------------------------------

   // Route gmii_rx_clk through a BUFIO/BUFR and onto regional clock routing
   BUFIO bufio_gmii_rx_clk (
      .I                (gmii_rx_clk),
      .O                (gmii_rx_clk_bufio)
   );


   // Route rx_clk through a BUFR onto regional clock routing
   BUFR bufr_gmii_rx_clk (
      .I                (gmii_rx_clk),
      .CE               (1'b1),
      .CLR              (1'b0),
      .O                (rx_clk_int)
   );

   // Assign the internal clock signal to the output port
   assign rx_clk = rx_clk_int;


   //---------------------------------------------------------------------------
   // GMII Receiver Logic : receive RX signals through IOBs from GMII interface
   //---------------------------------------------------------------------------

   // Use IDELAY to delay data to the capturing register.

   // Note: Delay value is set in UCF file
   // Please modify the IOBDELAY_VALUE according to your design.
   // For more information on IDELAYCTRL and IDELAY, please refer to
   // the User Guide.

   IODELAYE1 #(
      .IDELAY_TYPE      ("FIXED"),
      .DELAY_SRC        ("I"),
      .IDELAY_VALUE     (23)
   )
   delay_gmii_rx_dv (
      .IDATAIN          (gmii_rx_dv),
      .ODATAIN          (1'b0),
      .DATAOUT          (gmii_rx_dv_delay),
      .DATAIN           (1'b0),
      .C                (1'b0),
      .T                (1'b1),
      .CE               (1'b0),
      .CINVCTRL         (1'b0),
      .CLKIN            (1'b0),
      .CNTVALUEIN       (5'h0),
      .INC              (1'b0),
      .RST              (1'b0)
   );

   IODELAYE1 #(
      .IDELAY_TYPE      ("FIXED"),
      .DELAY_SRC        ("I"),
	  .IDELAY_VALUE     (23)
   )
   delay_gmii_rx_er (
      .IDATAIN          (gmii_rx_er),
      .ODATAIN          (1'b0),
      .DATAOUT          (gmii_rx_er_delay),
      .DATAIN           (1'b0),
      .C                (1'b0),
      .T                (1'b1),
      .CE               (1'b0),
      .CINVCTRL         (1'b0),
      .CLKIN            (1'b0),
      .CNTVALUEIN       (5'h0),
      .INC              (1'b0),
      .RST              (1'b0)
   );

   genvar i;
   generate for (i=0; i<8; i=i+1)
     begin : gmii_data_bus0

      IODELAYE1 #(
         .IDELAY_TYPE   ("FIXED"),
         .DELAY_SRC     ("I"),
		 .IDELAY_VALUE  (23)
      )
      delay_gmii_rxd (
         .IDATAIN       (gmii_rxd[i]),
         .ODATAIN       (1'b0),
         .DATAOUT       (gmii_rxd_delay[i]),
         .DATAIN        (1'b0),
         .C             (1'b0),
         .T             (1'b1),
         .CE            (1'b0),
         .CINVCTRL      (1'b0),
         .CLKIN         (1'b0),
         .CNTVALUEIN    (5'h0),
         .INC           (1'b0),
         .RST           (1'b0)
      );
     end
   endgenerate



   // Infer IOB Input flip-flops.
   always @(posedge gmii_rx_clk_bufio)
   begin
      rx_dv_to_mac <= gmii_rx_dv_delay;
      rx_er_to_mac <= gmii_rx_er_delay;
      rxd_to_mac   <= gmii_rxd_delay;
   end



endmodule
