// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module qam_dem_top_mounstrito (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        din_i_V,
        din_q_V,
        dout_mix_i_V,
        dout_mix_i_V_ap_vld,
        dout_mix_q_V,
        dout_mix_q_V_ap_vld,
        ph_in_i_V,
        ph_in_q_V,
        ph_out_i_V,
        ph_out_i_V_ap_vld,
        ph_out_q_V,
        ph_out_q_V_ap_vld,
        loop_integ_V,
        loop_integ_V_ap_vld,
        control_lf_p,
        control_lf_i,
        control_lf_out_gain,
        control_reg_clr,
        control_reg_init_V
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 15'b1;
parameter    ap_ST_st2_fsm_1 = 15'b10;
parameter    ap_ST_st3_fsm_2 = 15'b100;
parameter    ap_ST_st4_fsm_3 = 15'b1000;
parameter    ap_ST_st5_fsm_4 = 15'b10000;
parameter    ap_ST_st6_fsm_5 = 15'b100000;
parameter    ap_ST_st7_fsm_6 = 15'b1000000;
parameter    ap_ST_st8_fsm_7 = 15'b10000000;
parameter    ap_ST_st9_fsm_8 = 15'b100000000;
parameter    ap_ST_st10_fsm_9 = 15'b1000000000;
parameter    ap_ST_st11_fsm_10 = 15'b10000000000;
parameter    ap_ST_st12_fsm_11 = 15'b100000000000;
parameter    ap_ST_st13_fsm_12 = 15'b1000000000000;
parameter    ap_ST_st14_fsm_13 = 15'b10000000000000;
parameter    ap_ST_st15_fsm_14 = 15'b100000000000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv28_0 = 28'b0000000000000000000000000000;
parameter    ap_const_lv16_0 = 16'b0000000000000000;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_8 = 32'b1000;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv32_9 = 32'b1001;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv32_B = 32'b1011;
parameter    ap_const_lv32_C = 32'b1100;
parameter    ap_const_lv32_D = 32'b1101;
parameter    ap_const_lv32_E = 32'b1110;
parameter    ap_const_lv32_1A = 32'b11010;
parameter    ap_const_lv11_0 = 11'b00000000000;
parameter    ap_const_lv32_18 = 32'b11000;
parameter    ap_const_lv32_19 = 32'b11001;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv2_3 = 2'b11;
parameter    ap_const_lv5_0 = 5'b00000;
parameter    ap_const_lv32_14 = 32'b10100;
parameter    ap_const_lv32_12 = 32'b10010;
parameter    ap_const_lv32_13 = 32'b10011;
parameter    ap_const_lv14_1FFF = 14'b1111111111111;
parameter    ap_const_lv14_2000 = 14'b10000000000000;
parameter    ap_const_lv14_0 = 14'b00000000000000;
parameter    ap_const_lv8_0 = 8'b00000000;
parameter    ap_const_lv9_9 = 9'b1001;
parameter    ap_const_lv9_1F7 = 9'b111110111;
parameter    ap_const_lv32_1C = 32'b11100;
parameter    ap_const_lv32_1B = 32'b11011;
parameter    ap_const_lv28_7FFFFFF = 28'b111111111111111111111111111;
parameter    ap_const_lv28_8000000 = 28'b1000000000000000000000000000;
parameter    ap_const_lv32_F = 32'b1111;
parameter    ap_const_lv10_3FF = 10'b1111111111;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_true = 1'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [15:0] din_i_V;
input  [15:0] din_q_V;
output  [15:0] dout_mix_i_V;
output   dout_mix_i_V_ap_vld;
output  [15:0] dout_mix_q_V;
output   dout_mix_q_V_ap_vld;
input  [11:0] ph_in_i_V;
input  [11:0] ph_in_q_V;
output  [11:0] ph_out_i_V;
output   ph_out_i_V_ap_vld;
output  [11:0] ph_out_q_V;
output   ph_out_q_V_ap_vld;
output  [27:0] loop_integ_V;
output   loop_integ_V_ap_vld;
input  [7:0] control_lf_p;
input  [7:0] control_lf_i;
input  [7:0] control_lf_out_gain;
input  [0:0] control_reg_clr;
input  [27:0] control_reg_init_V;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg dout_mix_i_V_ap_vld;
reg dout_mix_q_V_ap_vld;
reg ph_out_i_V_ap_vld;
reg ph_out_q_V_ap_vld;
reg[27:0] loop_integ_V;
reg loop_integ_V_ap_vld;
reg    ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg   [14:0] ap_CS_fsm = 15'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_34;
reg   [27:0] i_reg_V = 28'b0000000000000000000000000000;
reg   [15:0] phase_angle_V = 16'b0000000000000000;
wire   [9:0] cos_lut_address0;
reg    cos_lut_ce0;
wire   [14:0] cos_lut_q0;
wire   [9:0] cos_lut_address1;
reg    cos_lut_ce1;
wire   [14:0] cos_lut_q1;
reg   [15:0] reg_312;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_82;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_bdd_89;
wire  signed [26:0] grp_fu_276_p2;
reg  signed [26:0] reg_316;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_bdd_99;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_bdd_106;
reg    ap_sig_cseq_ST_st9_fsm_8;
reg    ap_sig_bdd_114;
wire  signed [26:0] OP1_V_i_cast_fu_320_p1;
reg  signed [26:0] OP1_V_i_cast_reg_1471;
reg    ap_sig_bdd_122;
wire  signed [26:0] OP2_V_i_cast_fu_325_p1;
reg  signed [26:0] OP2_V_i_cast_reg_1476;
wire  signed [26:0] OP2_V_1_i_cast_fu_330_p1;
reg  signed [26:0] OP2_V_1_i_cast_reg_1481;
wire  signed [26:0] tmp_1_fu_335_p1;
reg  signed [26:0] tmp_1_reg_1486;
reg   [15:0] sd_out_i_V_reg_1491;
wire   [0:0] newsignbit_fu_372_p3;
reg   [0:0] newsignbit_reg_1497;
wire   [0:0] overflow_fu_408_p2;
reg   [0:0] overflow_reg_1503;
wire   [0:0] underflow_fu_432_p2;
reg   [0:0] underflow_reg_1509;
wire   [0:0] tmp_3_fu_467_p3;
reg   [0:0] tmp_3_reg_1516;
reg   [15:0] sd_out_q_V_reg_1521;
reg    ap_sig_cseq_ST_st6_fsm_5;
reg    ap_sig_bdd_148;
reg   [0:0] isneg_1_reg_1527;
reg   [0:0] newsignbit_1_reg_1533;
reg   [1:0] p_Result_1_i_reg_1541;
wire   [0:0] tmp_6_fu_620_p3;
reg   [0:0] tmp_6_reg_1547;
reg    ap_sig_cseq_ST_st7_fsm_6;
reg    ap_sig_bdd_163;
wire  signed [20:0] OP1_V_fu_628_p1;
wire  signed [20:0] OP2_V_fu_633_p1;
reg   [0:0] isneg_2_reg_1562;
reg    ap_sig_cseq_ST_st8_fsm_7;
reg    ap_sig_bdd_176;
reg   [13:0] p_Val2_9_reg_1568;
reg   [0:0] newsignbit_2_reg_1574;
reg   [1:0] p_Result_i8_reg_1580;
wire  signed [20:0] OP1_V_1_fu_692_p1;
wire  signed [20:0] OP2_V_1_fu_697_p1;
wire   [13:0] tmp_9_fu_775_p3;
reg   [13:0] tmp_9_reg_1596;
reg   [13:0] p_Val2_24_reg_1601;
reg    ap_sig_cseq_ST_st10_fsm_9;
reg    ap_sig_bdd_197;
wire   [0:0] overflow_3_fu_854_p2;
reg   [0:0] overflow_3_reg_1607;
wire   [0:0] underflow_3_fu_878_p2;
reg   [0:0] underflow_3_reg_1613;
wire   [27:0] p_Val2_26_fu_977_p3;
reg   [27:0] p_Val2_26_reg_1620;
reg    ap_sig_cseq_ST_st11_fsm_10;
reg    ap_sig_bdd_210;
wire   [27:0] p_Val2_4_fu_1041_p3;
reg   [27:0] p_Val2_4_reg_1625;
wire   [27:0] tmp_16_i_fu_1137_p3;
reg   [27:0] tmp_16_i_reg_1630;
reg    ap_sig_cseq_ST_st12_fsm_11;
reg    ap_sig_bdd_221;
wire   [0:0] isNeg_2_fu_1160_p3;
reg   [0:0] isNeg_2_reg_1636;
wire   [7:0] sh_assign_3_fu_1174_p3;
reg   [7:0] sh_assign_3_reg_1641;
reg   [1:0] msb_V_reg_1647;
reg    ap_sig_cseq_ST_st13_fsm_12;
reg    ap_sig_bdd_234;
reg   [0:0] tmp_26_reg_1654;
reg   [9:0] sin_adr_V_reg_1660;
reg    ap_sig_cseq_ST_st14_fsm_13;
reg    ap_sig_bdd_247;
wire   [63:0] tmp_23_i_fu_1300_p1;
wire   [63:0] tmp_24_i_fu_1305_p1;
wire   [27:0] p_Val2_41_fu_1145_p3;
reg   [27:0] loop_integ_V_preg = 28'b0000000000000000000000000000;
reg    ap_sig_cseq_ST_st15_fsm_14;
reg    ap_sig_bdd_275;
reg  signed [15:0] grp_fu_276_p0;
reg  signed [11:0] grp_fu_276_p1;
wire   [26:0] tmp_6_i_fu_340_p3;
wire  signed [26:0] p_Val2_1_fu_348_p2;
wire   [1:0] p_Result_i_fu_380_p4;
wire   [0:0] p_not_i1_i_fu_390_p2;
wire   [0:0] isneg_fu_364_p3;
wire   [0:0] brmerge_i1_i_fu_396_p2;
wire   [0:0] tmp_5_i_fu_402_p2;
wire   [0:0] p_not38_i1_i_fu_420_p2;
wire   [0:0] newsignbit_0_not_i1_i_fu_414_p2;
wire   [0:0] brmerge39_i1_i_fu_426_p2;
wire   [0:0] underflow_not_i_fu_442_p2;
wire   [0:0] brmerge_i_i1_i_fu_438_p2;
wire   [0:0] not_brmerge_i_i1_i_fu_452_p2;
wire   [0:0] brmerge8_i_fu_447_p2;
wire   [0:0] tmp_5_fu_458_p2;
wire   [0:0] tmp_s_fu_463_p2;
wire   [26:0] tmp_3_i_fu_475_p3;
wire  signed [26:0] p_Val2_3_fu_483_p2;
wire   [0:0] p_not_i_i_fu_525_p2;
wire   [0:0] brmerge_i_i_fu_530_p2;
wire   [0:0] tmp_7_i_fu_535_p2;
wire   [0:0] p_not38_i_i_fu_551_p2;
wire   [0:0] newsignbit_0_not_i_i_fu_546_p2;
wire   [0:0] brmerge39_i_i_fu_556_p2;
wire   [0:0] underflow_1_fu_562_p2;
wire   [0:0] overflow_1_fu_540_p2;
wire   [0:0] underflow_1_not_i_fu_573_p2;
wire   [1:0] tmp_i2_fu_585_p3;
wire   [0:0] brmerge_i_i_i_fu_567_p2;
wire   [0:0] not_brmerge_i_i_i_fu_604_p2;
wire   [0:0] brmerge9_i_fu_579_p2;
wire   [0:0] tmp_4_fu_610_p2;
wire   [0:0] tmp_8_fu_615_p2;
wire   [4:0] p_Result_s_fu_592_p5;
wire   [1:0] tmp_1_i3_fu_637_p3;
wire  signed [20:0] isneg_2_fu_656_p1;
wire  signed [20:0] p_Val2_9_fu_664_p1;
wire  signed [20:0] newsignbit_2_fu_674_p1;
wire  signed [20:0] p_Result_i8_fu_682_p1;
wire   [4:0] p_Result_2_fu_644_p5;
wire   [0:0] p_not_i_i9_fu_701_p2;
wire   [0:0] brmerge_i_i1_fu_706_p2;
wire   [0:0] tmp_8_i_fu_711_p2;
wire   [0:0] p_not38_i_i1_fu_727_p2;
wire   [0:0] newsignbit_0_not_i_i1_fu_722_p2;
wire   [0:0] brmerge39_i_i1_fu_732_p2;
wire   [0:0] underflow_2_fu_738_p2;
wire   [0:0] overflow_2_fu_716_p2;
wire   [0:0] underflow_not_i1_fu_749_p2;
wire   [0:0] brmerge_i_i_i1_fu_743_p2;
wire   [0:0] brmerge_i_fu_755_p2;
wire   [13:0] p_Val2_21_mux_i_fu_761_p3;
wire   [13:0] p_Val2_i1_fu_768_p3;
wire   [18:0] tmp_1_i1_fu_783_p3;
wire  signed [20:0] tmp_10_cast_i_fu_790_p1;
wire  signed [20:0] p_Val2_23_fu_794_p1;
wire  signed [20:0] p_Val2_23_fu_794_p2;
wire   [1:0] tmp_7_fu_826_p4;
wire   [0:0] newsignbit_3_fu_818_p3;
wire   [0:0] p_not_i_i_i_fu_836_p2;
wire   [0:0] isneg_3_fu_800_p3;
wire   [0:0] brmerge_i_i4_i_fu_842_p2;
wire   [0:0] tmp_3_i1_fu_848_p2;
wire   [0:0] p_not38_i_i_i_fu_866_p2;
wire   [0:0] newsignbit_0_not_i_i_i_fu_860_p2;
wire   [0:0] brmerge39_i_i_i_fu_872_p2;
wire   [0:0] underflow_4_not_i_fu_888_p2;
wire   [0:0] brmerge_i_i_i_i_fu_884_p2;
wire   [0:0] brmerge1_i_fu_893_p2;
wire   [13:0] ssdm_int_V_write_assign_fu_898_p3;
wire   [13:0] p_Val2_1_i_fu_905_p3;
wire   [13:0] tmp_10_fu_911_p3;
wire   [0:0] isNeg_fu_927_p3;
wire   [7:0] tmp_4_i_fu_935_p2;
wire   [7:0] sh_assign_fu_941_p3;
wire   [27:0] tmp_i1_fu_919_p3;
wire  signed [31:0] tmp_5_i1_fu_957_p1;
wire   [31:0] sh_assign_1_cast_i_fu_953_p1;
wire   [27:0] sh_assign_1_cast6_i_fu_949_p1;
wire   [31:0] tmp_6_i2_fu_961_p2;
wire   [27:0] tmp_16_fu_973_p1;
wire   [27:0] tmp_7_i1_fu_967_p2;
wire  signed [8:0] tmp_19_cast_i_fu_985_p1;
wire  signed [8:0] sh_assign_1_fu_989_p2;
wire   [0:0] isNeg_1_fu_995_p3;
wire  signed [8:0] tmp_8_i1_fu_1003_p2;
wire   [8:0] sh_assign_2_fu_1009_p3;
wire  signed [31:0] sh_assign_3_cast_i_fu_1021_p1;
wire  signed [27:0] sh_assign_3_cast5_i_fu_1017_p1;
wire   [31:0] tmp_10_i_fu_1025_p2;
wire   [27:0] tmp_18_fu_1037_p1;
wire   [27:0] tmp_11_i_fu_1031_p2;
wire   [27:0] p_Val2_5_fu_1053_p2;
wire  signed [28:0] tmp_12_i_fu_1058_p1;
wire  signed [28:0] tmp_13_i_fu_1062_p1;
wire  signed [28:0] p_Val2_27_fu_1065_p2;
wire   [0:0] newsignbit_4_fu_1083_p3;
wire   [0:0] isneg_4_fu_1071_p3;
wire   [0:0] tmp_15_i_fu_1091_p2;
wire   [0:0] isneg_not_i_fu_1109_p2;
wire   [0:0] brmerge_i_i_i2_fu_1103_p2;
wire   [27:0] p_Val2_29_fu_1079_p1;
wire   [0:0] underflow_4_fu_1097_p2;
wire   [0:0] brmerge_i1_fu_1115_p2;
wire   [27:0] p_Val2_28_mux_i_fu_1121_p3;
wire   [27:0] p_Val2_i2_fu_1129_p3;
wire   [7:0] tmp_17_i_fu_1168_p2;
wire  signed [31:0] tmp_18_i_fu_1188_p1;
wire   [31:0] sh_assign_5_cast_i_fu_1185_p1;
wire   [27:0] sh_assign_5_cast3_i_fu_1182_p1;
wire   [31:0] tmp_19_i_fu_1191_p2;
wire   [27:0] tmp_25_fu_1202_p1;
wire   [27:0] tmp_20_i_fu_1197_p2;
wire   [26:0] tmp_i2_15_fu_1217_p3;
wire   [27:0] p_Val2_33_fu_1206_p3;
wire  signed [28:0] tmp_35_cast_i_fu_1225_p1;
wire   [28:0] tmp_21_i_fu_1229_p1;
wire  signed [28:0] p_Val2_34_fu_1233_p2;
wire   [9:0] cos_adr_V_3_fu_1283_p2;
wire   [9:0] cos_adr_V_fu_1288_p3;
wire   [9:0] sin_adr_V_1_fu_1294_p3;
wire   [15:0] p_Val2_31_cast_i_fu_1314_p1;
wire   [15:0] p_Val2_32_cast_i_fu_1310_p1;
wire   [0:0] tmp_25_i_fu_1318_p2;
wire   [0:0] tmp_26_i_fu_1323_p2;
wire   [0:0] sel_tmp3_demorgan_i_fu_1345_p2;
wire   [0:0] tmp_27_i_fu_1328_p2;
wire   [0:0] sel_tmp3_i_fu_1351_p2;
wire   [0:0] sel_tmp6_i_fu_1363_p2;
wire   [0:0] sel_tmp7_i_fu_1369_p2;
wire   [0:0] sel_tmp4_i_fu_1357_p2;
wire   [10:0] tmp_11_fu_1381_p4;
wire   [15:0] sel_tmp_i_fu_1339_p2;
wire   [11:0] tmp_12_fu_1391_p1;
wire   [11:0] tmp_27_fu_1395_p4;
wire   [11:0] tmp_28_fu_1405_p3;
wire   [10:0] tmp_29_fu_1422_p4;
wire   [15:0] sin_out_V_fu_1333_p2;
wire   [11:0] tmp_30_fu_1432_p1;
wire   [11:0] tmp_31_fu_1436_p4;
wire   [0:0] or_cond_fu_1375_p2;
wire   [11:0] tmp_32_fu_1446_p3;
wire   [11:0] tmp_33_fu_1454_p3;
reg    grp_fu_276_ce;
reg   [14:0] ap_NS_fsm;


qam_dem_top_mounstrito_cos_lut #(
    .DataWidth( 15 ),
    .AddressRange( 1024 ),
    .AddressWidth( 10 ))
cos_lut_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( cos_lut_address0 ),
    .ce0( cos_lut_ce0 ),
    .q0( cos_lut_q0 ),
    .address1( cos_lut_address1 ),
    .ce1( cos_lut_ce1 ),
    .q1( cos_lut_q1 )
);

qam_dem_top_mul_16s_12s_27_2 #(
    .ID( 1 ),
    .NUM_STAGE( 2 ),
    .din0_WIDTH( 16 ),
    .din1_WIDTH( 12 ),
    .dout_WIDTH( 27 ))
qam_dem_top_mul_16s_12s_27_2_U1(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .din0( grp_fu_276_p0 ),
    .din1( grp_fu_276_p1 ),
    .ce( grp_fu_276_ce ),
    .dout( grp_fu_276_p2 )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
    if (ap_rst == 1'b1) begin
        ap_done_reg <= ap_const_logic_0;
    end else begin
        if ((ap_const_logic_1 == ap_continue)) begin
            ap_done_reg <= ap_const_logic_0;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
            ap_done_reg <= ap_const_logic_1;
        end
    end
end

/// loop_integ_V_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_loop_integ_V_preg
    if (ap_rst == 1'b1) begin
        loop_integ_V_preg <= ap_const_lv28_0;
    end else begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
            loop_integ_V_preg <= p_Val2_41_fu_1145_p3;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_122)) begin
        OP1_V_i_cast_reg_1471 <= OP1_V_i_cast_fu_320_p1;
        OP2_V_i_cast_reg_1476 <= OP2_V_i_cast_fu_325_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        OP2_V_1_i_cast_reg_1481 <= OP2_V_1_i_cast_fu_330_p1;
        tmp_1_reg_1486 <= tmp_1_fu_335_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
        i_reg_V <= p_Val2_41_fu_1145_p3;
        isNeg_2_reg_1636 <= control_lf_out_gain[ap_const_lv32_7];
        sh_assign_3_reg_1641 <= sh_assign_3_fu_1174_p3;
        tmp_16_i_reg_1630 <= tmp_16_i_fu_1137_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        isneg_1_reg_1527 <= p_Val2_3_fu_483_p2[ap_const_lv32_1A];
        newsignbit_1_reg_1533 <= p_Val2_3_fu_483_p2[ap_const_lv32_18];
        p_Result_1_i_reg_1541 <= {{p_Val2_3_fu_483_p2[ap_const_lv32_1A : ap_const_lv32_19]}};
        sd_out_q_V_reg_1521 <= {{p_Val2_3_fu_483_p2[ap_const_lv32_1A : ap_const_lv32_B]}};
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        isneg_2_reg_1562 <= isneg_2_fu_656_p1[ap_const_lv32_14];
        newsignbit_2_reg_1574 <= newsignbit_2_fu_674_p1[ap_const_lv32_12];
        p_Result_i8_reg_1580 <= {{p_Result_i8_fu_682_p1[ap_const_lv32_14 : ap_const_lv32_13]}};
        p_Val2_9_reg_1568 <= {{p_Val2_9_fu_664_p1[ap_const_lv32_12 : ap_const_lv32_5]}};
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) begin
        msb_V_reg_1647 <= {{p_Val2_34_fu_1233_p2[ap_const_lv32_1A : ap_const_lv32_19]}};
        phase_angle_V <= {{p_Val2_34_fu_1233_p2[ap_const_lv32_1A : ap_const_lv32_B]}};
        sin_adr_V_reg_1660 <= {{p_Val2_34_fu_1233_p2[ap_const_lv32_18 : ap_const_lv32_F]}};
        tmp_26_reg_1654 <= p_Val2_34_fu_1233_p2[ap_const_lv32_19];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        newsignbit_reg_1497 <= p_Val2_1_fu_348_p2[ap_const_lv32_18];
        overflow_reg_1503 <= overflow_fu_408_p2;
        sd_out_i_V_reg_1491 <= {{p_Val2_1_fu_348_p2[ap_const_lv32_1A : ap_const_lv32_B]}};
        underflow_reg_1509 <= underflow_fu_432_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
        overflow_3_reg_1607 <= overflow_3_fu_854_p2;
        p_Val2_24_reg_1601 <= {{p_Val2_23_fu_794_p2[ap_const_lv32_12 : ap_const_lv32_5]}};
        underflow_3_reg_1613 <= underflow_3_fu_878_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
        p_Val2_26_reg_1620 <= p_Val2_26_fu_977_p3;
        p_Val2_4_reg_1625 <= p_Val2_4_fu_1041_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) | (ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3))) begin
        reg_312 <= {{grp_fu_276_p2[ap_const_lv32_1A : ap_const_lv32_B]}};
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8))) begin
        reg_316 <= grp_fu_276_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        tmp_3_reg_1516 <= tmp_3_fu_467_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
        tmp_6_reg_1547 <= tmp_6_fu_620_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
        tmp_9_reg_1596 <= tmp_9_fu_775_p3;
    end
end

/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st15_fsm_14)
begin
    if (((ap_const_logic_1 == ap_done_reg) | (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st15_fsm_14)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st10_fsm_9 assign process. ///
always @ (ap_sig_bdd_197)
begin
    if (ap_sig_bdd_197) begin
        ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st11_fsm_10 assign process. ///
always @ (ap_sig_bdd_210)
begin
    if (ap_sig_bdd_210) begin
        ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st12_fsm_11 assign process. ///
always @ (ap_sig_bdd_221)
begin
    if (ap_sig_bdd_221) begin
        ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st13_fsm_12 assign process. ///
always @ (ap_sig_bdd_234)
begin
    if (ap_sig_bdd_234) begin
        ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st14_fsm_13 assign process. ///
always @ (ap_sig_bdd_247)
begin
    if (ap_sig_bdd_247) begin
        ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st15_fsm_14 assign process. ///
always @ (ap_sig_bdd_275)
begin
    if (ap_sig_bdd_275) begin
        ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_34)
begin
    if (ap_sig_bdd_34) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_82)
begin
    if (ap_sig_bdd_82) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_99)
begin
    if (ap_sig_bdd_99) begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_89)
begin
    if (ap_sig_bdd_89) begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_106)
begin
    if (ap_sig_bdd_106) begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_148)
begin
    if (ap_sig_bdd_148) begin
        ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st7_fsm_6 assign process. ///
always @ (ap_sig_bdd_163)
begin
    if (ap_sig_bdd_163) begin
        ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st8_fsm_7 assign process. ///
always @ (ap_sig_bdd_176)
begin
    if (ap_sig_bdd_176) begin
        ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st9_fsm_8 assign process. ///
always @ (ap_sig_bdd_114)
begin
    if (ap_sig_bdd_114) begin
        ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0;
    end
end

/// cos_lut_ce0 assign process. ///
always @ (ap_sig_cseq_ST_st14_fsm_13)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
        cos_lut_ce0 = ap_const_logic_1;
    end else begin
        cos_lut_ce0 = ap_const_logic_0;
    end
end

/// cos_lut_ce1 assign process. ///
always @ (ap_sig_cseq_ST_st14_fsm_13)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
        cos_lut_ce1 = ap_const_logic_1;
    end else begin
        cos_lut_ce1 = ap_const_logic_0;
    end
end

/// dout_mix_i_V_ap_vld assign process. ///
always @ (ap_sig_cseq_ST_st8_fsm_7)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        dout_mix_i_V_ap_vld = ap_const_logic_1;
    end else begin
        dout_mix_i_V_ap_vld = ap_const_logic_0;
    end
end

/// dout_mix_q_V_ap_vld assign process. ///
always @ (ap_sig_cseq_ST_st7_fsm_6)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
        dout_mix_q_V_ap_vld = ap_const_logic_1;
    end else begin
        dout_mix_q_V_ap_vld = ap_const_logic_0;
    end
end

/// grp_fu_276_ce assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st9_fsm_8 or ap_sig_bdd_122 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) | (ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) | (ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8) | ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_122) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7))) begin
        grp_fu_276_ce = ap_const_logic_1;
    end else begin
        grp_fu_276_ce = ap_const_logic_0;
    end
end

/// grp_fu_276_p0 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_st3_fsm_2 or OP1_V_i_cast_fu_320_p1 or OP1_V_i_cast_reg_1471 or tmp_1_fu_335_p1 or tmp_1_reg_1486 or ap_sig_cseq_ST_st7_fsm_6 or OP2_V_fu_633_p1 or ap_sig_cseq_ST_st8_fsm_7 or OP2_V_1_fu_697_p1)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        grp_fu_276_p0 = OP2_V_1_fu_697_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
        grp_fu_276_p0 = OP2_V_fu_633_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        grp_fu_276_p0 = tmp_1_reg_1486;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        grp_fu_276_p0 = OP1_V_i_cast_reg_1471;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        grp_fu_276_p0 = tmp_1_fu_335_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0)) begin
        grp_fu_276_p0 = OP1_V_i_cast_fu_320_p1;
    end else begin
        grp_fu_276_p0 = 'bx;
    end
end

/// grp_fu_276_p1 assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_st3_fsm_2 or OP2_V_i_cast_fu_325_p1 or OP2_V_i_cast_reg_1476 or OP2_V_1_i_cast_fu_330_p1 or OP2_V_1_i_cast_reg_1481 or ap_sig_cseq_ST_st7_fsm_6 or OP1_V_fu_628_p1 or ap_sig_cseq_ST_st8_fsm_7 or OP1_V_1_fu_692_p1)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
        grp_fu_276_p1 = OP1_V_1_fu_692_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
        grp_fu_276_p1 = OP1_V_fu_628_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        grp_fu_276_p1 = OP2_V_i_cast_reg_1476;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        grp_fu_276_p1 = OP2_V_1_i_cast_reg_1481;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        grp_fu_276_p1 = OP2_V_1_i_cast_fu_330_p1;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0)) begin
        grp_fu_276_p1 = OP2_V_i_cast_fu_325_p1;
    end else begin
        grp_fu_276_p1 = 'bx;
    end
end

/// loop_integ_V assign process. ///
always @ (ap_sig_cseq_ST_st12_fsm_11 or p_Val2_41_fu_1145_p3 or loop_integ_V_preg)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
        loop_integ_V = p_Val2_41_fu_1145_p3;
    end else begin
        loop_integ_V = loop_integ_V_preg;
    end
end

/// loop_integ_V_ap_vld assign process. ///
always @ (ap_sig_cseq_ST_st12_fsm_11)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
        loop_integ_V_ap_vld = ap_const_logic_1;
    end else begin
        loop_integ_V_ap_vld = ap_const_logic_0;
    end
end

/// ph_out_i_V_ap_vld assign process. ///
always @ (ap_sig_cseq_ST_st15_fsm_14)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
        ph_out_i_V_ap_vld = ap_const_logic_1;
    end else begin
        ph_out_i_V_ap_vld = ap_const_logic_0;
    end
end

/// ph_out_q_V_ap_vld assign process. ///
always @ (ap_sig_cseq_ST_st15_fsm_14)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
        ph_out_q_V_ap_vld = ap_const_logic_1;
    end else begin
        ph_out_q_V_ap_vld = ap_const_logic_0;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_122)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~ap_sig_bdd_122) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            ap_NS_fsm = ap_ST_st3_fsm_2;
        end
        ap_ST_st3_fsm_2 : 
        begin
            ap_NS_fsm = ap_ST_st4_fsm_3;
        end
        ap_ST_st4_fsm_3 : 
        begin
            ap_NS_fsm = ap_ST_st5_fsm_4;
        end
        ap_ST_st5_fsm_4 : 
        begin
            ap_NS_fsm = ap_ST_st6_fsm_5;
        end
        ap_ST_st6_fsm_5 : 
        begin
            ap_NS_fsm = ap_ST_st7_fsm_6;
        end
        ap_ST_st7_fsm_6 : 
        begin
            ap_NS_fsm = ap_ST_st8_fsm_7;
        end
        ap_ST_st8_fsm_7 : 
        begin
            ap_NS_fsm = ap_ST_st9_fsm_8;
        end
        ap_ST_st9_fsm_8 : 
        begin
            ap_NS_fsm = ap_ST_st10_fsm_9;
        end
        ap_ST_st10_fsm_9 : 
        begin
            ap_NS_fsm = ap_ST_st11_fsm_10;
        end
        ap_ST_st11_fsm_10 : 
        begin
            ap_NS_fsm = ap_ST_st12_fsm_11;
        end
        ap_ST_st12_fsm_11 : 
        begin
            ap_NS_fsm = ap_ST_st13_fsm_12;
        end
        ap_ST_st13_fsm_12 : 
        begin
            ap_NS_fsm = ap_ST_st14_fsm_13;
        end
        ap_ST_st14_fsm_13 : 
        begin
            ap_NS_fsm = ap_ST_st15_fsm_14;
        end
        ap_ST_st15_fsm_14 : 
        begin
            ap_NS_fsm = ap_ST_st1_fsm_0;
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign OP1_V_1_fu_692_p1 = $signed(p_Result_2_fu_644_p5);
assign OP1_V_fu_628_p1 = $signed(p_Result_s_fu_592_p5);
assign OP1_V_i_cast_fu_320_p1 = $signed(din_i_V);
assign OP2_V_1_fu_697_p1 = $signed(sd_out_i_V_reg_1491);
assign OP2_V_1_i_cast_fu_330_p1 = $signed(ph_in_q_V);
assign OP2_V_fu_633_p1 = $signed(sd_out_q_V_reg_1521);
assign OP2_V_i_cast_fu_325_p1 = $signed(ph_in_i_V);

/// ap_sig_bdd_106 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_106 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end

/// ap_sig_bdd_114 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_114 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end

/// ap_sig_bdd_122 assign process. ///
always @ (ap_start or ap_done_reg)
begin
    ap_sig_bdd_122 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end

/// ap_sig_bdd_148 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_148 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end

/// ap_sig_bdd_163 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_163 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end

/// ap_sig_bdd_176 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_176 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end

/// ap_sig_bdd_197 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_197 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end

/// ap_sig_bdd_210 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_210 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A]);
end

/// ap_sig_bdd_221 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_221 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B]);
end

/// ap_sig_bdd_234 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_234 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C]);
end

/// ap_sig_bdd_247 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_247 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D]);
end

/// ap_sig_bdd_275 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_275 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E]);
end

/// ap_sig_bdd_34 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_34 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_82 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_82 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_89 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_89 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_99 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_99 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign brmerge1_i_fu_893_p2 = (overflow_3_reg_1607 | underflow_4_not_i_fu_888_p2);
assign brmerge39_i1_i_fu_426_p2 = (p_not38_i1_i_fu_420_p2 | newsignbit_0_not_i1_i_fu_414_p2);
assign brmerge39_i_i1_fu_732_p2 = (p_not38_i_i1_fu_727_p2 | newsignbit_0_not_i_i1_fu_722_p2);
assign brmerge39_i_i_fu_556_p2 = (p_not38_i_i_fu_551_p2 | newsignbit_0_not_i_i_fu_546_p2);
assign brmerge39_i_i_i_fu_872_p2 = (p_not38_i_i_i_fu_866_p2 | newsignbit_0_not_i_i_i_fu_860_p2);
assign brmerge8_i_fu_447_p2 = (overflow_reg_1503 | underflow_not_i_fu_442_p2);
assign brmerge9_i_fu_579_p2 = (overflow_1_fu_540_p2 | underflow_1_not_i_fu_573_p2);
assign brmerge_i1_fu_1115_p2 = (newsignbit_4_fu_1083_p3 | isneg_not_i_fu_1109_p2);
assign brmerge_i1_i_fu_396_p2 = (newsignbit_fu_372_p3 | p_not_i1_i_fu_390_p2);
assign brmerge_i_fu_755_p2 = (overflow_2_fu_716_p2 | underflow_not_i1_fu_749_p2);
assign brmerge_i_i1_fu_706_p2 = (newsignbit_2_reg_1574 | p_not_i_i9_fu_701_p2);
assign brmerge_i_i1_i_fu_438_p2 = (underflow_reg_1509 | overflow_reg_1503);
assign brmerge_i_i4_i_fu_842_p2 = (newsignbit_3_fu_818_p3 | p_not_i_i_i_fu_836_p2);
assign brmerge_i_i_fu_530_p2 = (newsignbit_1_reg_1533 | p_not_i_i_fu_525_p2);
assign brmerge_i_i_i1_fu_743_p2 = (underflow_2_fu_738_p2 | overflow_2_fu_716_p2);
assign brmerge_i_i_i2_fu_1103_p2 = (isneg_4_fu_1071_p3 ^ newsignbit_4_fu_1083_p3);
assign brmerge_i_i_i_fu_567_p2 = (underflow_1_fu_562_p2 | overflow_1_fu_540_p2);
assign brmerge_i_i_i_i_fu_884_p2 = (underflow_3_reg_1613 | overflow_3_reg_1607);
assign cos_adr_V_3_fu_1283_p2 = (sin_adr_V_reg_1660 ^ ap_const_lv10_3FF);
assign cos_adr_V_fu_1288_p3 = ((tmp_26_reg_1654)? cos_adr_V_3_fu_1283_p2: sin_adr_V_reg_1660);
assign cos_lut_address0 = tmp_23_i_fu_1300_p1;
assign cos_lut_address1 = tmp_24_i_fu_1305_p1;
assign dout_mix_i_V = sd_out_i_V_reg_1491;
assign dout_mix_q_V = sd_out_q_V_reg_1521;
assign isNeg_1_fu_995_p3 = sh_assign_1_fu_989_p2[ap_const_lv32_8];
assign isNeg_2_fu_1160_p3 = control_lf_out_gain[ap_const_lv32_7];
assign isNeg_fu_927_p3 = control_lf_p[ap_const_lv32_7];
assign isneg_2_fu_656_p1 = grp_fu_276_p2;
assign isneg_3_fu_800_p3 = p_Val2_23_fu_794_p2[ap_const_lv32_14];
assign isneg_4_fu_1071_p3 = p_Val2_27_fu_1065_p2[ap_const_lv32_1C];
assign isneg_fu_364_p3 = p_Val2_1_fu_348_p2[ap_const_lv32_1A];
assign isneg_not_i_fu_1109_p2 = (isneg_4_fu_1071_p3 ^ ap_const_lv1_1);
assign newsignbit_0_not_i1_i_fu_414_p2 = (newsignbit_fu_372_p3 ^ ap_const_lv1_1);
assign newsignbit_0_not_i_i1_fu_722_p2 = (newsignbit_2_reg_1574 ^ ap_const_lv1_1);
assign newsignbit_0_not_i_i_fu_546_p2 = (newsignbit_1_reg_1533 ^ ap_const_lv1_1);
assign newsignbit_0_not_i_i_i_fu_860_p2 = (newsignbit_3_fu_818_p3 ^ ap_const_lv1_1);
assign newsignbit_2_fu_674_p1 = grp_fu_276_p2;
assign newsignbit_3_fu_818_p3 = p_Val2_23_fu_794_p2[ap_const_lv32_12];
assign newsignbit_4_fu_1083_p3 = p_Val2_27_fu_1065_p2[ap_const_lv32_1B];
assign newsignbit_fu_372_p3 = p_Val2_1_fu_348_p2[ap_const_lv32_18];
assign not_brmerge_i_i1_i_fu_452_p2 = (brmerge_i_i1_i_fu_438_p2 ^ ap_const_lv1_1);
assign not_brmerge_i_i_i_fu_604_p2 = (brmerge_i_i_i_fu_567_p2 ^ ap_const_lv1_1);
assign or_cond_fu_1375_p2 = (sel_tmp7_i_fu_1369_p2 | sel_tmp4_i_fu_1357_p2);
assign overflow_1_fu_540_p2 = (brmerge_i_i_fu_530_p2 & tmp_7_i_fu_535_p2);
assign overflow_2_fu_716_p2 = (brmerge_i_i1_fu_706_p2 & tmp_8_i_fu_711_p2);
assign overflow_3_fu_854_p2 = (brmerge_i_i4_i_fu_842_p2 & tmp_3_i1_fu_848_p2);
assign overflow_fu_408_p2 = (brmerge_i1_i_fu_396_p2 & tmp_5_i_fu_402_p2);
assign p_Result_2_fu_644_p5 = {{tmp_1_i3_fu_637_p3}, {ap_const_lv5_0[32'd2 : 32'd0]}};
assign p_Result_i8_fu_682_p1 = grp_fu_276_p2;
assign p_Result_i_fu_380_p4 = {{p_Val2_1_fu_348_p2[ap_const_lv32_1A : ap_const_lv32_19]}};
assign p_Result_s_fu_592_p5 = {{tmp_i2_fu_585_p3}, {ap_const_lv5_0[32'd2 : 32'd0]}};
assign p_Val2_1_fu_348_p2 = ($signed(tmp_6_i_fu_340_p3) - $signed(reg_316));
assign p_Val2_1_i_fu_905_p3 = ((underflow_3_reg_1613)? ap_const_lv14_2000: p_Val2_24_reg_1601);
assign p_Val2_21_mux_i_fu_761_p3 = ((brmerge_i_i_i1_fu_743_p2)? ap_const_lv14_1FFF: p_Val2_9_reg_1568);
assign p_Val2_23_fu_794_p1 = reg_316;
assign p_Val2_23_fu_794_p2 = ($signed(tmp_10_cast_i_fu_790_p1) - $signed(p_Val2_23_fu_794_p1));
assign p_Val2_26_fu_977_p3 = ((isNeg_fu_927_p3)? tmp_16_fu_973_p1: tmp_7_i1_fu_967_p2);
assign p_Val2_27_fu_1065_p2 = ($signed(tmp_12_i_fu_1058_p1) + $signed(tmp_13_i_fu_1062_p1));
assign p_Val2_28_mux_i_fu_1121_p3 = ((brmerge_i_i_i2_fu_1103_p2)? ap_const_lv28_7FFFFFF: p_Val2_29_fu_1079_p1);
assign p_Val2_29_fu_1079_p1 = p_Val2_27_fu_1065_p2[27:0];
assign p_Val2_31_cast_i_fu_1314_p1 = cos_lut_q1;
assign p_Val2_32_cast_i_fu_1310_p1 = cos_lut_q0;
assign p_Val2_33_fu_1206_p3 = ((isNeg_2_reg_1636)? tmp_25_fu_1202_p1: tmp_20_i_fu_1197_p2);
assign p_Val2_34_fu_1233_p2 = ($signed(tmp_35_cast_i_fu_1225_p1) - $signed(tmp_21_i_fu_1229_p1));
assign p_Val2_3_fu_483_p2 = ($signed(tmp_3_i_fu_475_p3) + $signed(reg_316));
assign p_Val2_41_fu_1145_p3 = ((control_reg_clr)? control_reg_init_V: p_Val2_5_fu_1053_p2);
assign p_Val2_4_fu_1041_p3 = ((isNeg_1_fu_995_p3)? tmp_18_fu_1037_p1: tmp_11_i_fu_1031_p2);
assign p_Val2_5_fu_1053_p2 = (i_reg_V + p_Val2_4_reg_1625);
assign p_Val2_9_fu_664_p1 = grp_fu_276_p2;
assign p_Val2_i1_fu_768_p3 = ((underflow_2_fu_738_p2)? ap_const_lv14_2000: p_Val2_9_reg_1568);
assign p_Val2_i2_fu_1129_p3 = ((underflow_4_fu_1097_p2)? ap_const_lv28_8000000: p_Val2_29_fu_1079_p1);
assign p_not38_i1_i_fu_420_p2 = (p_Result_i_fu_380_p4 != ap_const_lv2_3? 1'b1: 1'b0);
assign p_not38_i_i1_fu_727_p2 = (p_Result_i8_reg_1580 != ap_const_lv2_3? 1'b1: 1'b0);
assign p_not38_i_i_fu_551_p2 = (p_Result_1_i_reg_1541 != ap_const_lv2_3? 1'b1: 1'b0);
assign p_not38_i_i_i_fu_866_p2 = (tmp_7_fu_826_p4 != ap_const_lv2_3? 1'b1: 1'b0);
assign p_not_i1_i_fu_390_p2 = (p_Result_i_fu_380_p4 != ap_const_lv2_0? 1'b1: 1'b0);
assign p_not_i_i9_fu_701_p2 = (p_Result_i8_reg_1580 != ap_const_lv2_0? 1'b1: 1'b0);
assign p_not_i_i_fu_525_p2 = (p_Result_1_i_reg_1541 != ap_const_lv2_0? 1'b1: 1'b0);
assign p_not_i_i_i_fu_836_p2 = (tmp_7_fu_826_p4 != ap_const_lv2_0? 1'b1: 1'b0);
assign ph_out_i_V = ((sel_tmp7_i_fu_1369_p2)? tmp_12_fu_1391_p1: tmp_28_fu_1405_p3);
assign ph_out_q_V = ((or_cond_fu_1375_p2)? tmp_32_fu_1446_p3: tmp_33_fu_1454_p3);
assign sel_tmp3_demorgan_i_fu_1345_p2 = (tmp_25_i_fu_1318_p2 | tmp_26_i_fu_1323_p2);
assign sel_tmp3_i_fu_1351_p2 = (sel_tmp3_demorgan_i_fu_1345_p2 ^ ap_const_lv1_1);
assign sel_tmp4_i_fu_1357_p2 = (tmp_27_i_fu_1328_p2 & sel_tmp3_i_fu_1351_p2);
assign sel_tmp6_i_fu_1363_p2 = (tmp_25_i_fu_1318_p2 ^ ap_const_lv1_1);
assign sel_tmp7_i_fu_1369_p2 = (tmp_26_i_fu_1323_p2 & sel_tmp6_i_fu_1363_p2);
assign sel_tmp_i_fu_1339_p2 = (ap_const_lv16_0 - p_Val2_32_cast_i_fu_1310_p1);
assign sh_assign_1_cast6_i_fu_949_p1 = sh_assign_fu_941_p3;
assign sh_assign_1_cast_i_fu_953_p1 = sh_assign_fu_941_p3;
assign sh_assign_1_fu_989_p2 = ($signed(tmp_19_cast_i_fu_985_p1) + $signed(ap_const_lv9_9));
assign sh_assign_2_fu_1009_p3 = ((isNeg_1_fu_995_p3)? tmp_8_i1_fu_1003_p2: sh_assign_1_fu_989_p2);
assign sh_assign_3_cast5_i_fu_1017_p1 = $signed(sh_assign_2_fu_1009_p3);
assign sh_assign_3_cast_i_fu_1021_p1 = $signed(sh_assign_2_fu_1009_p3);
assign sh_assign_3_fu_1174_p3 = ((isNeg_2_fu_1160_p3)? tmp_17_i_fu_1168_p2: control_lf_out_gain);
assign sh_assign_5_cast3_i_fu_1182_p1 = sh_assign_3_reg_1641;
assign sh_assign_5_cast_i_fu_1185_p1 = sh_assign_3_reg_1641;
assign sh_assign_fu_941_p3 = ((isNeg_fu_927_p3)? tmp_4_i_fu_935_p2: control_lf_p);
assign sin_adr_V_1_fu_1294_p3 = ((tmp_26_reg_1654)? sin_adr_V_reg_1660: cos_adr_V_3_fu_1283_p2);
assign sin_out_V_fu_1333_p2 = (ap_const_lv16_0 - p_Val2_31_cast_i_fu_1314_p1);
assign ssdm_int_V_write_assign_fu_898_p3 = ((brmerge_i_i_i_i_fu_884_p2)? ap_const_lv14_1FFF: p_Val2_24_reg_1601);
assign tmp_10_cast_i_fu_790_p1 = $signed(tmp_1_i1_fu_783_p3);
assign tmp_10_fu_911_p3 = ((brmerge1_i_fu_893_p2)? ssdm_int_V_write_assign_fu_898_p3: p_Val2_1_i_fu_905_p3);
assign tmp_10_i_fu_1025_p2 = tmp_5_i1_fu_957_p1 << sh_assign_3_cast_i_fu_1021_p1;
assign tmp_11_fu_1381_p4 = {{cos_lut_q0[ap_const_lv32_E : ap_const_lv32_4]}};
assign tmp_11_i_fu_1031_p2 = $signed(tmp_i1_fu_919_p3) >>> sh_assign_3_cast5_i_fu_1017_p1;
assign tmp_12_fu_1391_p1 = tmp_11_fu_1381_p4;
assign tmp_12_i_fu_1058_p1 = $signed(p_Val2_5_fu_1053_p2);
assign tmp_13_i_fu_1062_p1 = $signed(p_Val2_26_reg_1620);
assign tmp_15_i_fu_1091_p2 = (newsignbit_4_fu_1083_p3 ^ ap_const_lv1_1);
assign tmp_16_fu_973_p1 = tmp_6_i2_fu_961_p2[27:0];
assign tmp_16_i_fu_1137_p3 = ((brmerge_i1_fu_1115_p2)? p_Val2_28_mux_i_fu_1121_p3: p_Val2_i2_fu_1129_p3);
assign tmp_17_i_fu_1168_p2 = (ap_const_lv8_0 - control_lf_out_gain);
assign tmp_18_fu_1037_p1 = tmp_10_i_fu_1025_p2[27:0];
assign tmp_18_i_fu_1188_p1 = $signed(tmp_16_i_reg_1630);
assign tmp_19_cast_i_fu_985_p1 = $signed(control_lf_i);
assign tmp_19_i_fu_1191_p2 = tmp_18_i_fu_1188_p1 << sh_assign_5_cast_i_fu_1185_p1;
assign tmp_1_fu_335_p1 = $signed(din_q_V);
assign tmp_1_i1_fu_783_p3 = {{tmp_9_reg_1596}, {ap_const_lv5_0}};
assign tmp_1_i3_fu_637_p3 = {{tmp_6_reg_1547}, {ap_const_lv1_1}};
assign tmp_20_i_fu_1197_p2 = $signed(tmp_16_i_reg_1630) >>> sh_assign_5_cast3_i_fu_1182_p1;
assign tmp_21_i_fu_1229_p1 = p_Val2_33_fu_1206_p3;
assign tmp_23_i_fu_1300_p1 = cos_adr_V_fu_1288_p3;
assign tmp_24_i_fu_1305_p1 = sin_adr_V_1_fu_1294_p3;
assign tmp_25_fu_1202_p1 = tmp_19_i_fu_1191_p2[27:0];
assign tmp_25_i_fu_1318_p2 = (msb_V_reg_1647 == ap_const_lv2_1? 1'b1: 1'b0);
assign tmp_26_i_fu_1323_p2 = (msb_V_reg_1647 == ap_const_lv2_0? 1'b1: 1'b0);
assign tmp_27_fu_1395_p4 = {{sel_tmp_i_fu_1339_p2[ap_const_lv32_F : ap_const_lv32_4]}};
assign tmp_27_i_fu_1328_p2 = (msb_V_reg_1647 == ap_const_lv2_3? 1'b1: 1'b0);
assign tmp_28_fu_1405_p3 = ((sel_tmp4_i_fu_1357_p2)? tmp_12_fu_1391_p1: tmp_27_fu_1395_p4);
assign tmp_29_fu_1422_p4 = {{cos_lut_q1[ap_const_lv32_E : ap_const_lv32_4]}};
assign tmp_30_fu_1432_p1 = tmp_29_fu_1422_p4;
assign tmp_31_fu_1436_p4 = {{sin_out_V_fu_1333_p2[ap_const_lv32_F : ap_const_lv32_4]}};
assign tmp_32_fu_1446_p3 = ((sel_tmp7_i_fu_1369_p2)? tmp_30_fu_1432_p1: tmp_31_fu_1436_p4);
assign tmp_33_fu_1454_p3 = ((tmp_25_i_fu_1318_p2)? tmp_30_fu_1432_p1: tmp_31_fu_1436_p4);
assign tmp_35_cast_i_fu_1225_p1 = $signed(tmp_i2_15_fu_1217_p3);
assign tmp_3_fu_467_p3 = ((brmerge8_i_fu_447_p2)? tmp_5_fu_458_p2: tmp_s_fu_463_p2);
assign tmp_3_i1_fu_848_p2 = (isneg_3_fu_800_p3 ^ ap_const_lv1_1);
assign tmp_3_i_fu_475_p3 = {{reg_312}, {ap_const_lv11_0}};
assign tmp_4_fu_610_p2 = (newsignbit_1_reg_1533 & not_brmerge_i_i_i_fu_604_p2);
assign tmp_4_i_fu_935_p2 = (ap_const_lv8_0 - control_lf_p);
assign tmp_5_fu_458_p2 = (newsignbit_reg_1497 & not_brmerge_i_i1_i_fu_452_p2);
assign tmp_5_i1_fu_957_p1 = $signed(tmp_i1_fu_919_p3);
assign tmp_5_i_fu_402_p2 = (isneg_fu_364_p3 ^ ap_const_lv1_1);
assign tmp_6_fu_620_p3 = ((brmerge9_i_fu_579_p2)? tmp_4_fu_610_p2: tmp_8_fu_615_p2);
assign tmp_6_i2_fu_961_p2 = tmp_5_i1_fu_957_p1 << sh_assign_1_cast_i_fu_953_p1;
assign tmp_6_i_fu_340_p3 = {{reg_312}, {ap_const_lv11_0}};
assign tmp_7_fu_826_p4 = {{p_Val2_23_fu_794_p2[ap_const_lv32_14 : ap_const_lv32_13]}};
assign tmp_7_i1_fu_967_p2 = $signed(tmp_i1_fu_919_p3) >>> sh_assign_1_cast6_i_fu_949_p1;
assign tmp_7_i_fu_535_p2 = (isneg_1_reg_1527 ^ ap_const_lv1_1);
assign tmp_8_fu_615_p2 = (underflow_1_fu_562_p2 | newsignbit_1_reg_1533);
assign tmp_8_i1_fu_1003_p2 = ($signed(ap_const_lv9_1F7) - $signed(tmp_19_cast_i_fu_985_p1));
assign tmp_8_i_fu_711_p2 = (isneg_2_reg_1562 ^ ap_const_lv1_1);
assign tmp_9_fu_775_p3 = ((brmerge_i_fu_755_p2)? p_Val2_21_mux_i_fu_761_p3: p_Val2_i1_fu_768_p3);
assign tmp_i1_fu_919_p3 = {{tmp_10_fu_911_p3}, {ap_const_lv14_0}};
assign tmp_i2_15_fu_1217_p3 = {{phase_angle_V}, {ap_const_lv11_0}};
assign tmp_i2_fu_585_p3 = {{tmp_3_reg_1516}, {ap_const_lv1_1}};
assign tmp_s_fu_463_p2 = (underflow_reg_1509 | newsignbit_reg_1497);
assign underflow_1_fu_562_p2 = (brmerge39_i_i_fu_556_p2 & isneg_1_reg_1527);
assign underflow_1_not_i_fu_573_p2 = (underflow_1_fu_562_p2 ^ ap_const_lv1_1);
assign underflow_2_fu_738_p2 = (brmerge39_i_i1_fu_732_p2 & isneg_2_reg_1562);
assign underflow_3_fu_878_p2 = (brmerge39_i_i_i_fu_872_p2 & isneg_3_fu_800_p3);
assign underflow_4_fu_1097_p2 = (isneg_4_fu_1071_p3 & tmp_15_i_fu_1091_p2);
assign underflow_4_not_i_fu_888_p2 = (underflow_3_reg_1613 ^ ap_const_lv1_1);
assign underflow_fu_432_p2 = (brmerge39_i1_i_fu_426_p2 & isneg_fu_364_p3);
assign underflow_not_i1_fu_749_p2 = (underflow_2_fu_738_p2 ^ ap_const_lv1_1);
assign underflow_not_i_fu_442_p2 = (underflow_reg_1509 ^ ap_const_lv1_1);


endmodule //qam_dem_top_mounstrito

