// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ec_e
//
// Generated
//  by:  wig
//  on:  Mon Apr 10 13:26:55 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ec_e.v,v 1.1 2006/04/10 15:42:10 wig Exp $
// $Date: 2006/04/10 15:42:10 $
// $Log: inst_ec_e.v,v $
// Revision 1.1  2006/04/10 15:42:10  wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp 
//
// Generator: mix_0.pl Revision: 1.44 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of inst_ec_e
//

	// No user `defines in this module


module inst_ec_e
//
// Generated module inst_ec
//
		(
		p_mix_v_select_2_2_gi,
		p_mix_v_select_5_5_gi,
		p_mix_c_addr_12_0_gi,
		p_mix_c_bus_in_31_0_gi
		);
	// Generated Module Inputs:
		input		p_mix_v_select_2_2_gi;
		input		p_mix_v_select_5_5_gi;
		input	[12:0]	p_mix_c_addr_12_0_gi;
		input	[31:0]	p_mix_c_bus_in_31_0_gi;
	// Generated Wires:
		wire		p_mix_v_select_2_2_gi;
		wire		p_mix_v_select_5_5_gi;
		wire	[12:0]	p_mix_c_addr_12_0_gi;
		wire	[31:0]	p_mix_c_bus_in_31_0_gi;
// End of generated module header




	// Internal signals

		//
		// Generated Signal List
		//
			wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
			wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
			wire [5:0] v_select; // __W_PORT_SIGNAL_MAP_REQ
		//
		// End of Generated Signal List
		//


	// %COMPILER_OPTS%

	// Generated Signal Assignments
			assign	c_addr = p_mix_c_addr_12_0_gi;  // __I_I_BUS_PORT
			assign	c_bus_in = p_mix_c_bus_in_31_0_gi;  // __I_I_BUS_PORT
			assign	v_select[5] = p_mix_v_select_5_5_gi;  // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
			assign	v_select[2] = p_mix_v_select_2_2_gi;  // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE




	//
	// Generated Instances
	// wiring ...

	// Generated Instances and Port Mappings
		// Generated Instance Port Map for inst_eca
		inst_eca_e inst_eca (
			.c_add(c_addr),
			.c_bus_in(c_bus_in),	// CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
			.v_select(v_select)	// RequestBusinterface:RequestBus#6(VPU)VPUinterface
		);
		// End of Generated Instance Port Map for inst_eca

		// Generated Instance Port Map for inst_ecb
		inst_ecb_e inst_ecb (
			.c_addr(c_addr),
			.c_bus_in(c_bus_in)	// CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
		);
		// End of Generated Instance Port Map for inst_ecb

		// Generated Instance Port Map for inst_ecc
		inst_ecc_e inst_ecc (
			.c_addr(c_addr),
			.c_bus_in(c_bus_in)	// CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
		);
		// End of Generated Instance Port Map for inst_ecc



endmodule
//
// End of Generated Module rtl of inst_ec_e
//

//
//!End of Module/s
// --------------------------------------------------------------
