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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 3.91
//  \   \         Application: MIG
//  /   /         Filename: phy_rdctrl_sync.v
// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \   \  /  \    Date Created: Aug 03 2009
//  \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
//   Synchronization of read control signal from MC/PHY rdlvl logic (clk) to
//   read capture logic (clk_rsync) clock domain. Also adds additional delay
//   to account for read latency
//Reference:
//Revision History:
//*****************************************************************************

/******************************************************************************
**$Id: phy_rdctrl_sync.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_rdctrl_sync.v,v $
******************************************************************************/

`timescale 1ps/1ps

module phy_rdctrl_sync #
  (
   parameter TCQ = 100
  )
  (
   input                      clk,
   input                      rst_rsync,       // Use only CLK_RSYNC[0] reset
   // Control for control sync logic
   input                      mc_data_sel,
   input [4:0]                rd_active_dly,
   // DFI signals from MC/PHY rdlvl logic
   input                      dfi_rddata_en,
   input                      phy_rddata_en,
   // Control for read logic, initialization logic
   output reg                 dfi_rddata_valid,
   output reg                 dfi_rddata_valid_phy,
   output reg                 rdpath_rdy       // asserted when read path
                                               // ready for use
   );

  // # of clock cycles after RST_RSYNC has deasserted before init/cal logic
  // is taken out of reset. This is only needed for simulation when the "no
  // init/no cal" option is selected. In this case, PHY_INIT will assert
  // DFI_INIT_COMPLETE signal almost instantaneously once it is taken out
  // of reset - however, there are certain pipe stages that must "flush
  // out" (related to circular buffer synchronization) for a few cycles after
  // RST_RSYNC is deasserted - in particular, the one related to generating
  // DFI_RDDATA_VALID must not drive an unknown value on the bus after
  // DFI_INIT_COMPLETE is asserted.
  // NOTE: # of cycles of delay required depends on the circular buffer
  //  depth for RD_ACTIVE - it should >= (0.5*depth + 1)
  localparam RDPATH_RDY_DLY = 10;

  wire                     rddata_en;
  wire                     rddata_en_rsync;
  wire                     rddata_en_srl_out;
  reg [RDPATH_RDY_DLY-1:0] rdpath_rdy_dly_r;

  //***************************************************************************
  // Delay RDDATA_EN by an amount determined during read-leveling
  // calibration to reflect the round trip delay from command issuance until
  // when read data is returned
  //***************************************************************************

  assign rddata_en = (mc_data_sel) ? dfi_rddata_en : phy_rddata_en;

  // May need to flop output of SRL for better timing
  SRLC32E u_rddata_en_srl
    (
     .Q   (rddata_en_srl_out),
     .Q31 (),
     .A   (rd_active_dly),
     .CE  (1'b1),
     .CLK (clk),
     .D   (rddata_en)
     );

  // Flop once more for better timing
  always @(posedge clk) begin
    // Only assert valid on DFI bus after initialization complete
    dfi_rddata_valid <= #TCQ rddata_en_srl_out & mc_data_sel;
    // Assert valid for PHY during initialization
    dfi_rddata_valid_phy <= #TCQ rddata_en_srl_out;
  end

  //***************************************************************************
  // Generate a signal that tells initialization logic that read path is
  // ready for use (i.e. for read leveling). Use RST_RSYNC, and delay it by
  // RDPATH_RDY_DLY clock cycles, then synchronize to CLK domain.
  // NOTE: This logic only required for simulation; for final h/w, there will
  //   always be a long delay between RST_RSYNC deassertion and
  //   DFI_INIT_COMPLETE assertion (for DRAM init, and leveling)
  //***************************************************************************

  // First delay by X number of clock cycles to guarantee that RDPATH_RDY
  // isn't asserted too soon after RST_RSYNC is deasserted (to allow various
  // synchronization pipe stages to "flush"). NOTE: Only RST_RSYNC[0] (or
  // any of the up to 4 RST_RSYNC's) is used - any of them is sufficient
  // close enough in timing to use
  always @(posedge clk or posedge rst_rsync) begin
    if (rst_rsync)
      rdpath_rdy_dly_r <= #TCQ {{RDPATH_RDY_DLY}{1'b0}};
    else
      rdpath_rdy_dly_r[RDPATH_RDY_DLY-1:1]
        <= #TCQ {rdpath_rdy_dly_r[RDPATH_RDY_DLY-2:0], 1'b1};
  end

  // Flop once more to prevent ISE tools from analyzing asynchronous path
  // through this flop to receiving logic
  always @(posedge clk)
    rdpath_rdy <= rdpath_rdy_dly_r[RDPATH_RDY_DLY-1];

endmodule
