/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */

(* src = "../../verilog/max6682.v:133" *)
module MAX6682(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
  (* src = "../../verilog/max6682.v:297" *)
  wire [31:0] \$0\SensorFSM_Timer[31:0] ;
  (* src = "../../verilog/max6682.v:327" *)
  wire [15:0] \$0\Word0[15:0] ;
  (* src = "../../verilog/max6682.v:231" *)
  wire \$2\SPI_FSM_Start[0:0] ;
  (* src = "../../verilog/max6682.v:231" *)
  wire \$2\SensorFSM_StoreNewValue[0:0] ;
  (* src = "../../verilog/max6682.v:231" *)
  wire \$2\SensorFSM_TimerPreset[0:0] ;
  (* src = "../../verilog/max6682.v:231" *)
  wire \$3\SensorFSM_TimerPreset[0:0] ;
  (* src = "../../verilog/max6682.v:231" *)
  wire \$4\SensorFSM_TimerPreset[0:0] ;
  wire \$auto$opt_reduce.cc:126:opt_mux$732 ;
  wire \$procmux$118_CMP ;
  wire \$procmux$123_CMP ;
  wire \$procmux$126_CMP ;
  wire [31:0] \$procmux$449_Y ;
  (* src = "../../verilog/max6682.v:311" *)
  wire [31:0] \$sub$../../verilog/max6682.v:311$18_Y ;
  (* src = "../../verilog/max6682.v:323" *)
  wire [15:0] AbsDiffResult;
  (* src = "../../verilog/max6682.v:184" *)
  wire [7:0] Byte0;
  (* src = "../../verilog/max6682.v:185" *)
  wire [7:0] Byte1;
  (* intersynth_port = "Clk_i" *)
  (* src = "../../verilog/max6682.v:137" *)
  input Clk_i;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "ReconfModuleIRQs_s" *)
  (* src = "../../verilog/max6682.v:141" *)
  output CpuIntr_o;
  (* src = "../../verilog/max6682.v:342" *)
  wire [16:0] DiffAB;
  (* src = "../../verilog/max6682.v:343" *)
  wire [15:0] DiffBA;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "ReconfModuleIn_s" *)
  (* src = "../../verilog/max6682.v:139" *)
  input Enable_i;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "Outputs_o" *)
  (* src = "../../verilog/max6682.v:143" *)
  output MAX6682CS_n_o;
  (* intersynth_conntype = "Word" *)
  (* intersynth_param = "PeriodCounterPresetH_i" *)
  (* src = "../../verilog/max6682.v:159" *)
  input [15:0] PeriodCounterPresetH_i;
  (* intersynth_conntype = "Word" *)
  (* intersynth_param = "PeriodCounterPresetL_i" *)
  (* src = "../../verilog/max6682.v:161" *)
  input [15:0] PeriodCounterPresetL_i;
  (* intersynth_port = "Reset_n_i" *)
  (* src = "../../verilog/max6682.v:135" *)
  input Reset_n_i;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_CPHA" *)
  (* src = "../../verilog/max6682.v:169" *)
  output SPI_CPHA_o;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_CPOL" *)
  (* src = "../../verilog/max6682.v:167" *)
  output SPI_CPOL_o;
  (* intersynth_conntype = "Byte" *)
  (* intersynth_port = "SPI_DataOut" *)
  (* src = "../../verilog/max6682.v:145" *)
  input [7:0] SPI_Data_i;
  (* intersynth_conntype = "Byte" *)
  (* intersynth_port = "SPI_DataIn" *)
  (* src = "../../verilog/max6682.v:151" *)
  output [7:0] SPI_Data_o;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_FIFOEmpty" *)
  (* src = "../../verilog/max6682.v:155" *)
  input SPI_FIFOEmpty_i;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_FIFOFull" *)
  (* src = "../../verilog/max6682.v:153" *)
  input SPI_FIFOFull_i;
  (* src = "../../verilog/max6682.v:183" *)
  wire SPI_FSM_Done;
  (* src = "../../verilog/max6682.v:182" *)
  wire SPI_FSM_Start;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_LSBFE" *)
  (* src = "../../verilog/max6682.v:171" *)
  output SPI_LSBFE_o;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_ReadNext" *)
  (* src = "../../verilog/max6682.v:149" *)
  output SPI_ReadNext_o;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_Transmission" *)
  (* src = "../../verilog/max6682.v:157" *)
  input SPI_Transmission_i;
  (* intersynth_conntype = "Bit" *)
  (* intersynth_port = "SPI_Write" *)
  (* src = "../../verilog/max6682.v:147" *)
  output SPI_Write_o;
  (* src = "../../verilog/max6682.v:215" *)
  wire SensorFSM_DiffTooLarge;
  (* src = "../../verilog/max6682.v:216" *)
  wire SensorFSM_StoreNewValue;
  (* src = "../../verilog/max6682.v:295" *)
  wire [31:0] SensorFSM_Timer;
  (* src = "../../verilog/max6682.v:214" *)
  wire SensorFSM_TimerEnable;
  (* src = "../../verilog/max6682.v:212" *)
  wire SensorFSM_TimerOvfl;
  (* src = "../../verilog/max6682.v:213" *)
  wire SensorFSM_TimerPreset;
  (* src = "../../verilog/max6682.v:321" *)
  wire [15:0] SensorValue;
  (* intersynth_conntype = "Word" *)
  (* intersynth_param = "SensorValue_o" *)
  (* src = "../../verilog/max6682.v:163" *)
  output [15:0] SensorValue_o;
  (* intersynth_conntype = "Word" *)
  (* intersynth_param = "Threshold_i" *)
  (* src = "../../verilog/max6682.v:165" *)
  input [15:0] Threshold_i;
  (* src = "../../verilog/max6682.v:322" *)
  wire [15:0] Word0;
  \$reduce_or  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000011),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$auto$opt_reduce.cc:130:opt_mux$733  (
    .A({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP  }),
    .Y(\$auto$opt_reduce.cc:126:opt_mux$732 )
  );
  (* src = "../../verilog/max6682.v:316" *)
  \$eq  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000100000),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000100000),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$eq$../../verilog/max6682.v:316$19  (
    .A(SensorFSM_Timer),
    .B(0),
    .Y(SensorFSM_TimerOvfl)
  );
  (* fsm_encoding = "auto" *)
  (* src = "../../verilog/max6682.v:210" *)
  \$fsm  #(
    .ARST_POLARITY(1'b0),
    .CLK_POLARITY(1'b1),
    .CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
    .CTRL_OUT_WIDTH(32'b00000000000000000000000000000011),
    .NAME("\\SensorFSM_State"),
    .STATE_BITS(32'b00000000000000000000000000000010),
    .STATE_NUM(32'b00000000000000000000000000000100),
    .STATE_NUM_LOG2(32'b00000000000000000000000000000011),
    .STATE_RST(32'b00000000000000000000000000000000),
    .STATE_TABLE(8'b11011000),
    .TRANS_NUM(32'b00000000000000000000000000001001),
    .TRANS_TABLE(117'b011zzzz0100000100zz10100100101zz1001010010zzz0000010001z11z011001001z01z010001001zz0z001001000zzz1010100000zzz0000100)
  ) \$fsm$\SensorFSM_State$738  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .CTRL_IN({ SensorFSM_TimerOvfl, SensorFSM_DiffTooLarge, SPI_FSM_Done, Enable_i }),
    .CTRL_OUT({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP  })
  );
  (* src = "../../verilog/max6682.v:348" *)
  \$gt  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010000),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000010000),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$gt$../../verilog/max6682.v:348$26  (
    .A(AbsDiffResult),
    .B(Threshold_i),
    .Y(SensorFSM_DiffTooLarge)
  );
  (* src = "../../verilog/max6682.v:297" *)
  \$adff  #(
    .ARST_POLARITY(1'b0),
    .ARST_VALUE(32'b00000000000000000000000000000000),
    .CLK_POLARITY(1'b1),
    .WIDTH(32'b00000000000000000000000000100000)
  ) \$procdff$727  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .D(\$0\SensorFSM_Timer[31:0] ),
    .Q(SensorFSM_Timer)
  );
  (* src = "../../verilog/max6682.v:327" *)
  \$adff  #(
    .ARST_POLARITY(1'b0),
    .ARST_VALUE(16'b0000000000000000),
    .CLK_POLARITY(1'b1),
    .WIDTH(32'b00000000000000000000000000010000)
  ) \$procdff$728  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .D(\$0\Word0[15:0] ),
    .Q(Word0)
  );
  \$not  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$117  (
    .A(\$auto$opt_reduce.cc:126:opt_mux$732 ),
    .Y(CpuIntr_o)
  );
  \$and  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$137  (
    .A(\$procmux$123_CMP ),
    .B(\$2\SPI_FSM_Start[0:0] ),
    .Y(SPI_FSM_Start)
  );
  \$and  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$147  (
    .A(\$procmux$118_CMP ),
    .B(\$2\SensorFSM_StoreNewValue[0:0] ),
    .Y(SensorFSM_StoreNewValue)
  );
  \$pmux  #(
    .S_WIDTH(32'b00000000000000000000000000000011),
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$177  (
    .A(1'b0),
    .B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0]  }),
    .S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP  }),
    .Y(SensorFSM_TimerEnable)
  );
  \$pmux  #(
    .S_WIDTH(32'b00000000000000000000000000000011),
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$192  (
    .A(1'b1),
    .B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0]  }),
    .S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP  }),
    .Y(SensorFSM_TimerPreset)
  );
  \$not  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$230  (
    .A(Enable_i),
    .Y(\$2\SensorFSM_TimerPreset[0:0] )
  );
  \$and  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$259  (
    .A(Enable_i),
    .B(SensorFSM_TimerOvfl),
    .Y(\$2\SPI_FSM_Start[0:0] )
  );
  \$and  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$336  (
    .A(SPI_FSM_Done),
    .B(SensorFSM_DiffTooLarge),
    .Y(\$2\SensorFSM_StoreNewValue[0:0] )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$368  (
    .A(1'b1),
    .B(\$4\SensorFSM_TimerPreset[0:0] ),
    .S(SPI_FSM_Done),
    .Y(\$3\SensorFSM_TimerPreset[0:0] )
  );
  \$not  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$400  (
    .A(SensorFSM_DiffTooLarge),
    .Y(\$4\SensorFSM_TimerPreset[0:0] )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000100000)
  ) \$procmux$449  (
    .A(SensorFSM_Timer),
    .B(\$sub$../../verilog/max6682.v:311$18_Y ),
    .S(SensorFSM_TimerEnable),
    .Y(\$procmux$449_Y )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000100000)
  ) \$procmux$452  (
    .A(\$procmux$449_Y ),
    .B({ PeriodCounterPresetH_i, PeriodCounterPresetL_i }),
    .S(SensorFSM_TimerPreset),
    .Y(\$0\SensorFSM_Timer[31:0] )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010000)
  ) \$procmux$455  (
    .A(Word0),
    .B({ 5'b00000, Byte1, Byte0[7:5] }),
    .S(SensorFSM_StoreNewValue),
    .Y(\$0\Word0[15:0] )
  );
  (* src = "../../verilog/max6682.v:311" *)
  \$sub  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000100000),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000100000)
  ) \$sub$../../verilog/max6682.v:311$18  (
    .A(SensorFSM_Timer),
    .B(1'b1),
    .Y(\$sub$../../verilog/max6682.v:311$18_Y )
  );
  (* src = "../../verilog/max6682.v:344" *)
  \$sub  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000010001),
    .Y_WIDTH(32'b00000000000000000000000000010001)
  ) \$sub$../../verilog/max6682.v:344$23  (
    .A({ 6'b000000, Byte1, Byte0[7:5] }),
    .B({ 1'b0, Word0 }),
    .Y(DiffAB)
  );
  (* src = "../../verilog/max6682.v:345" *)
  \$sub  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010000),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000010000),
    .Y_WIDTH(32'b00000000000000000000000000010000)
  ) \$sub$../../verilog/max6682.v:345$24  (
    .A(Word0),
    .B({ 5'b00000, Byte1, Byte0[7:5] }),
    .Y(DiffBA)
  );
  (* src = "../../verilog/max6682.v:346" *)
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010000)
  ) \$ternary$../../verilog/max6682.v:346$25  (
    .A(DiffAB[15:0]),
    .B(DiffBA),
    .S(DiffAB[16]),
    .Y(AbsDiffResult)
  );
  (* src = "../../verilog/max6682.v:187" *)
  MAX6682_SPI_FSM MAX6682_SPI_FSM_1 (
    .Byte0(Byte0),
    .Byte1(Byte1),
    .Clk_i(Clk_i),
    .MAX6682CS_n_o(MAX6682CS_n_o),
    .Reset_n_i(Reset_n_i),
    .SPI_Data_i(SPI_Data_i),
    .SPI_FSM_Done(SPI_FSM_Done),
    .SPI_FSM_Start(SPI_FSM_Start),
    .SPI_ReadNext_o(SPI_ReadNext_o),
    .SPI_Transmission_i(SPI_Transmission_i),
    .SPI_Write_o(SPI_Write_o)
  );
  assign SPI_CPHA_o = 1'b0;
  assign SPI_CPOL_o = 1'b0;
  assign SPI_Data_o = 8'b00000000;
  assign SPI_LSBFE_o = 1'b0;
  assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
  assign SensorValue_o = Word0;
endmodule

(* src = "../../verilog/max6682.v:1" *)
module MAX6682_SPI_FSM(Reset_n_i, Clk_i, SPI_FSM_Start, SPI_Transmission_i, MAX6682CS_n_o, SPI_Write_o, SPI_ReadNext_o, SPI_FSM_Done, SPI_Data_i, Byte0, Byte1);
  (* src = "../../verilog/max6682.v:111" *)
  wire [7:0] \$0\Byte0[7:0] ;
  (* src = "../../verilog/max6682.v:111" *)
  wire [7:0] \$0\Byte1[7:0] ;
  (* src = "../../verilog/max6682.v:50" *)
  wire \$2\MAX6682CS_n_o[0:0] ;
  (* src = "../../verilog/max6682.v:50" *)
  wire \$2\SPI_FSM_Wr1[0:0] ;
  wire \$auto$opt_reduce.cc:126:opt_mux$736 ;
  wire \$procmux$553_CMP ;
  wire \$procmux$554_CMP ;
  wire \$procmux$558_CMP ;
  wire \$procmux$559_CMP ;
  wire \$procmux$560_CMP ;
  wire \$procmux$563_CMP ;
  (* src = "../../verilog/max6682.v:11" *)
  output [7:0] Byte0;
  (* src = "../../verilog/max6682.v:12" *)
  output [7:0] Byte1;
  (* src = "../../verilog/max6682.v:3" *)
  input Clk_i;
  (* src = "../../verilog/max6682.v:6" *)
  output MAX6682CS_n_o;
  (* src = "../../verilog/max6682.v:2" *)
  input Reset_n_i;
  (* src = "../../verilog/max6682.v:10" *)
  input [7:0] SPI_Data_i;
  (* src = "../../verilog/max6682.v:9" *)
  output SPI_FSM_Done;
  (* src = "../../verilog/max6682.v:4" *)
  input SPI_FSM_Start;
  (* src = "../../verilog/max6682.v:24" *)
  wire SPI_FSM_Wr0;
  (* src = "../../verilog/max6682.v:23" *)
  wire SPI_FSM_Wr1;
  (* src = "../../verilog/max6682.v:8" *)
  output SPI_ReadNext_o;
  (* src = "../../verilog/max6682.v:5" *)
  input SPI_Transmission_i;
  (* src = "../../verilog/max6682.v:7" *)
  output SPI_Write_o;
  \$reduce_or  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000010),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$auto$opt_reduce.cc:130:opt_mux$735  (
    .A({ \$procmux$554_CMP , \$procmux$553_CMP  }),
    .Y(SPI_FSM_Done)
  );
  \$reduce_or  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000100),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$auto$opt_reduce.cc:130:opt_mux$737  (
    .A({ SPI_FSM_Wr0, \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP  }),
    .Y(\$auto$opt_reduce.cc:126:opt_mux$736 )
  );
  (* fsm_encoding = "auto" *)
  (* src = "../../verilog/max6682.v:21" *)
  \$fsm  #(
    .ARST_POLARITY(1'b0),
    .CLK_POLARITY(1'b1),
    .CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
    .CTRL_OUT_WIDTH(32'b00000000000000000000000000000111),
    .NAME("\\SPI_FSM_State"),
    .STATE_BITS(32'b00000000000000000000000000000011),
    .STATE_NUM(32'b00000000000000000000000000000111),
    .STATE_NUM_LOG2(32'b00000000000000000000000000000011),
    .STATE_RST(32'b00000000000000000000000000000000),
    .STATE_TABLE(21'b011101001110010100000),
    .TRANS_NUM(32'b00000000000000000000000000001001),
    .TRANS_TABLE(135'b1101z11000001001100z0010000100101zz0110000010100zz0100010000011zz0000000001010zz1100001000001zz1011000000000z11000100000000z00000100000)
  ) \$fsm$\SPI_FSM_State$743  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .CTRL_IN({ SPI_Transmission_i, SPI_FSM_Start }),
    .CTRL_OUT({ SPI_FSM_Wr0, \$procmux$563_CMP , \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP , \$procmux$554_CMP , \$procmux$553_CMP  })
  );
  (* src = "../../verilog/max6682.v:111" *)
  \$adff  #(
    .ARST_POLARITY(1'b0),
    .ARST_VALUE(8'b00000000),
    .CLK_POLARITY(1'b1),
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$procdff$729  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .D(\$0\Byte0[7:0] ),
    .Q(Byte0)
  );
  (* src = "../../verilog/max6682.v:111" *)
  \$adff  #(
    .ARST_POLARITY(1'b0),
    .ARST_VALUE(8'b00000000),
    .CLK_POLARITY(1'b1),
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$procdff$730  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .D(\$0\Byte1[7:0] ),
    .Q(Byte1)
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$procmux$458  (
    .A(Byte0),
    .B(SPI_Data_i),
    .S(SPI_FSM_Wr0),
    .Y(\$0\Byte0[7:0] )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000001000)
  ) \$procmux$465  (
    .A(Byte1),
    .B(SPI_Data_i),
    .S(SPI_FSM_Wr1),
    .Y(\$0\Byte1[7:0] )
  );
  \$and  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$583  (
    .A(\$procmux$558_CMP ),
    .B(\$2\SPI_FSM_Wr1[0:0] ),
    .Y(SPI_FSM_Wr1)
  );
  \$pmux  #(
    .S_WIDTH(32'b00000000000000000000000000000010),
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$593  (
    .A(1'b0),
    .B({ \$2\SPI_FSM_Wr1[0:0] , 1'b1 }),
    .S({ \$procmux$558_CMP , SPI_FSM_Wr0 }),
    .Y(SPI_ReadNext_o)
  );
  \$pmux  #(
    .S_WIDTH(32'b00000000000000000000000000000010),
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$606  (
    .A(1'b1),
    .B({ \$2\MAX6682CS_n_o[0:0] , 1'b0 }),
    .S({ \$procmux$563_CMP , \$auto$opt_reduce.cc:126:opt_mux$736  }),
    .Y(MAX6682CS_n_o)
  );
  \$pmux  #(
    .S_WIDTH(32'b00000000000000000000000000000010),
    .WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$637  (
    .A(1'b0),
    .B({ SPI_FSM_Start, 1'b1 }),
    .S({ \$procmux$563_CMP , \$procmux$560_CMP  }),
    .Y(SPI_Write_o)
  );
  \$not  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$666  (
    .A(SPI_FSM_Start),
    .Y(\$2\MAX6682CS_n_o[0:0] )
  );
  \$not  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$procmux$703  (
    .A(SPI_Transmission_i),
    .Y(\$2\SPI_FSM_Wr1[0:0] )
  );
endmodule
