// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement

`timescale 1ps/1ps

module ad_intp2_4 (

  clk,
  data,

  // outputs

  intp2_0,
  intp2_1,
  intp2_2,
  intp2_3);

  input           clk;
  input   [15:0]  data;
  
  // outputs

  output  [15:0]  intp2_0;
  output  [15:0]  intp2_1;
  output  [15:0]  intp2_2;
  output  [15:0]  intp2_3;

  // internal registers

  reg     [15:0]  data_s0 = 'd0;
  reg     [15:0]  data_s1 = 'd0;
  reg     [15:0]  data_s2 = 'd0;
  reg     [15:0]  data_s3 = 'd0;
  reg     [15:0]  data_s4 = 'd0;
  reg     [15:0]  data_s5 = 'd0;
  reg     [15:0]  data_s6 = 'd0;
  reg     [15:0]  data_s7 = 'd0;

  // internal signals

  wire    [15:0]  intp2_0_s;
  wire    [15:0]  intp2_1_s;

  // delay registers

  always @(posedge clk) begin
    data_s0 <= data_s2;
    data_s1 <= data_s3;
    data_s2 <= data_s4;
    data_s3 <= data_s5;
    data_s4 <= data_s6;
    data_s5 <= data_s7;
    data_s6 <= intp2_0_s;
    data_s7 <= intp2_1_s;
  end

  // interpolators (stage-2)

  ad_mac_1 i_mac_1_0 (
    .clk (clk),
    .data_s0 (data_s0),
    .data_s1 (data_s1),
    .data_s2 (data_s2),
    .data_s3 (data_s3),
    .data_s4 (data_s4),
    .data_s5 (data_s5),
    .mac_data_0 (intp2_0),
    .mac_data_1 (intp2_1));

  // interpolators (stage-2)

  ad_mac_1 i_mac_1_1 (
    .clk (clk),
    .data_s0 (data_s1),
    .data_s1 (data_s2),
    .data_s2 (data_s3),
    .data_s3 (data_s4),
    .data_s4 (data_s5),
    .data_s5 (data_s6),
    .mac_data_0 (intp2_2),
    .mac_data_1 (intp2_3));

  // interpolators (stage-1)

  ad_intp2_2 i_intp2_2 (
    .clk (clk),
    .data (data),
    .intp2_0 (intp2_0_s),
    .intp2_1 (intp2_1_s));

endmodule

// ***************************************************************************
// ***************************************************************************
