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// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 6

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodJSTK_pmod_bridge_0_0 (
  in0_I,
  in1_I,
  in2_I,
  in3_I,
  in0_O,
  in1_O,
  in2_O,
  in3_O,
  in0_T,
  in1_T,
  in2_T,
  in3_T,
  out0_I,
  out1_I,
  out2_I,
  out3_I,
  out4_I,
  out5_I,
  out6_I,
  out7_I,
  out0_O,
  out1_O,
  out2_O,
  out3_O,
  out4_O,
  out5_O,
  out6_O,
  out7_O,
  out0_T,
  out1_T,
  out2_T,
  out3_T,
  out4_T,
  out5_T,
  out6_T,
  out7_T
);

(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;

  pmod_concat #(
    .Top_Row_Interface("SPI"),
    .Bottom_Row_Interface("Disabled")
  ) inst (
    .in_top_bus_I(),
    .in_top_bus_O(4'B0),
    .in_top_bus_T(4'B0),
    .in_top_uart_gpio_bus_I(),
    .in_top_uart_gpio_bus_O(2'B1),
    .in_top_uart_gpio_bus_T(2'B1),
    .in_top_i2c_gpio_bus_I(),
    .in_top_i2c_gpio_bus_O(2'B1),
    .in_top_i2c_gpio_bus_T(2'B1),
    .in_bottom_bus_I(),
    .in_bottom_bus_O(4'B1),
    .in_bottom_bus_T(4'B1),
    .in_bottom_uart_gpio_bus_I(),
    .in_bottom_uart_gpio_bus_O(2'B1),
    .in_bottom_uart_gpio_bus_T(2'B1),
    .in_bottom_i2c_gpio_bus_I(),
    .in_bottom_i2c_gpio_bus_O(2'B1),
    .in_bottom_i2c_gpio_bus_T(2'B1),
    .in0_I(in0_I),
    .in1_I(in1_I),
    .in2_I(in2_I),
    .in3_I(in3_I),
    .in4_I(),
    .in5_I(),
    .in6_I(),
    .in7_I(),
    .in0_O(in0_O),
    .in1_O(in1_O),
    .in2_O(in2_O),
    .in3_O(in3_O),
    .in4_O(1'B1),
    .in5_O(1'B1),
    .in6_O(1'B1),
    .in7_O(1'B1),
    .in0_T(in0_T),
    .in1_T(in1_T),
    .in2_T(in2_T),
    .in3_T(in3_T),
    .in4_T(1'B1),
    .in5_T(1'B1),
    .in6_T(1'B1),
    .in7_T(1'B1),
    .out0_I(out0_I),
    .out1_I(out1_I),
    .out2_I(out2_I),
    .out3_I(out3_I),
    .out4_I(out4_I),
    .out5_I(out5_I),
    .out6_I(out6_I),
    .out7_I(out7_I),
    .out0_O(out0_O),
    .out1_O(out1_O),
    .out2_O(out2_O),
    .out3_O(out3_O),
    .out4_O(out4_O),
    .out5_O(out5_O),
    .out6_O(out6_O),
    .out7_O(out7_O),
    .out0_T(out0_T),
    .out1_T(out1_T),
    .out2_T(out2_T),
    .out3_T(out3_T),
    .out4_T(out4_T),
    .out5_T(out5_T),
    .out6_T(out6_T),
    .out7_T(out7_T)
  );
endmodule
