`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:43:50 08/14/2013
// Design Name:   siete_segmentos_principal
// Module Name:   C:/Users/Fabian/Desktop/Laboratorio 1/sietesegmentos/tests.v
// Project Name:  sietesegmentos
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: siete_segmentos_principal
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tests;

	// Inputs
	reg bitA;
	reg bitB;
	reg bitC;
	reg bitD;

	// Outputs
	wire seg_a;
	wire seg_b;
	wire seg_c;
	wire seg_d;
	wire seg_e;
	wire seg_f;
	wire seg_g;

	// Instantiate the Unit Under Test (UUT)
	siete_segmentos_principal uut (
		.bitA(bitA), 
		.bitB(bitB), 
		.bitC(bitC), 
		.bitD(bitD), 
		.seg_a(seg_a), 
		.seg_b(seg_b), 
		.seg_c(seg_c), 
		.seg_d(seg_d), 
		.seg_e(seg_e), 
		.seg_f(seg_f), 
		.seg_g(seg_g)
	);

	initial begin
		// Initialize Inputs
		bitA = 0;
		bitB = 0;
		bitC = 0;
		bitD = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

