// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}" *)

module sin_taylor_series (
        x,
        ap_clk,
        ap_rst,
        ap_return,
        ap_done,
        ap_start,
        ap_ready,
        ap_idle
);


input  [63:0] x;
input   ap_clk;
input   ap_rst;
output  [63:0] ap_return;
output   ap_done;
input   ap_start;
output   ap_ready;
output   ap_idle;

wire    Loop_sum_loop_proc_U0_ap_start;
wire    Loop_sum_loop_proc_U0_ap_done;
wire    Loop_sum_loop_proc_U0_ap_continue;
wire    Loop_sum_loop_proc_U0_ap_idle;
wire    Loop_sum_loop_proc_U0_ap_ready;
wire   [63:0] Loop_sum_loop_proc_U0_ap_return_0;
wire   [63:0] Loop_sum_loop_proc_U0_ap_return_1;
wire    ap_channel_done_sum_negative_0_loc_l;
wire    sum_negative_0_loc_l_full_n;
reg    ap_sync_reg_channel_write_sum_negative_0_loc_l;
wire    ap_sync_channel_write_sum_negative_0_loc_l;
wire    ap_channel_done_sum_positive_0_loc_l;
wire    sum_positive_0_loc_l_full_n;
reg    ap_sync_reg_channel_write_sum_positive_0_loc_l;
wire    ap_sync_channel_write_sum_positive_0_loc_l;
wire    Block_sin_taylor_ser_U0_ap_start;
wire    Block_sin_taylor_ser_U0_ap_done;
wire    Block_sin_taylor_ser_U0_ap_continue;
wire    Block_sin_taylor_ser_U0_ap_idle;
wire    Block_sin_taylor_ser_U0_ap_ready;
wire   [63:0] Block_sin_taylor_ser_U0_ap_return;
wire    ap_channel_done_tmp_loc_channel;
wire    tmp_loc_channel_full_n;
wire    p_source_files_sr_U0_ap_start;
wire    p_source_files_sr_U0_ap_done;
wire    p_source_files_sr_U0_ap_continue;
wire    p_source_files_sr_U0_ap_idle;
wire    p_source_files_sr_U0_ap_ready;
wire   [63:0] p_source_files_sr_U0_ap_return;
wire   [63:0] tmp_p_source_files_sr_fu_42_ap_return;
wire    ap_sync_continue;
wire   [63:0] sum_positive_0_loc_l_dout;
wire    sum_positive_0_loc_l_empty_n;
wire   [63:0] sum_negative_0_loc_l_dout;
wire    sum_negative_0_loc_l_empty_n;
wire   [63:0] tmp_loc_channel_dout;
wire    tmp_loc_channel_empty_n;
wire    ap_sync_done;
wire    ap_sync_ready;
wire    Loop_sum_loop_proc_U0_start_full_n;
wire    Loop_sum_loop_proc_U0_start_write;
wire    Block_sin_taylor_ser_U0_start_full_n;
wire    Block_sin_taylor_ser_U0_start_write;
wire    p_source_files_sr_U0_start_full_n;
wire    p_source_files_sr_U0_start_write;

// power-on initialization
initial begin
#0 ap_sync_reg_channel_write_sum_negative_0_loc_l = 1'b0;
#0 ap_sync_reg_channel_write_sum_positive_0_loc_l = 1'b0;
end

Loop_sum_loop_proc Loop_sum_loop_proc_U0(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(Loop_sum_loop_proc_U0_ap_start),
    .ap_done(Loop_sum_loop_proc_U0_ap_done),
    .ap_continue(Loop_sum_loop_proc_U0_ap_continue),
    .ap_idle(Loop_sum_loop_proc_U0_ap_idle),
    .ap_ready(Loop_sum_loop_proc_U0_ap_ready),
    .x(x),
    .ap_return_0(Loop_sum_loop_proc_U0_ap_return_0),
    .ap_return_1(Loop_sum_loop_proc_U0_ap_return_1)
);

Block_sin_taylor_ser Block_sin_taylor_ser_U0(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(Block_sin_taylor_ser_U0_ap_start),
    .ap_done(Block_sin_taylor_ser_U0_ap_done),
    .ap_continue(Block_sin_taylor_ser_U0_ap_continue),
    .ap_idle(Block_sin_taylor_ser_U0_ap_idle),
    .ap_ready(Block_sin_taylor_ser_U0_ap_ready),
    .p_read(sum_positive_0_loc_l_dout),
    .p_read1(sum_negative_0_loc_l_dout),
    .ap_return(Block_sin_taylor_ser_U0_ap_return)
);

p_source_files_sr p_source_files_sr_U0(
    .ap_clk(ap_clk),
    .ap_rst(ap_rst),
    .ap_start(p_source_files_sr_U0_ap_start),
    .ap_done(p_source_files_sr_U0_ap_done),
    .ap_continue(p_source_files_sr_U0_ap_continue),
    .ap_idle(p_source_files_sr_U0_ap_idle),
    .ap_ready(p_source_files_sr_U0_ap_ready),
    .p_read(tmp_loc_channel_dout),
    .ap_return(p_source_files_sr_U0_ap_return)
);

fifo_w64_d2_A sum_positive_0_loc_l_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .if_read_ce(1'b1),
    .if_write_ce(1'b1),
    .if_din(Loop_sum_loop_proc_U0_ap_return_0),
    .if_full_n(sum_positive_0_loc_l_full_n),
    .if_write(ap_channel_done_sum_positive_0_loc_l),
    .if_dout(sum_positive_0_loc_l_dout),
    .if_empty_n(sum_positive_0_loc_l_empty_n),
    .if_read(Block_sin_taylor_ser_U0_ap_ready)
);

fifo_w64_d2_A sum_negative_0_loc_l_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .if_read_ce(1'b1),
    .if_write_ce(1'b1),
    .if_din(Loop_sum_loop_proc_U0_ap_return_1),
    .if_full_n(sum_negative_0_loc_l_full_n),
    .if_write(ap_channel_done_sum_negative_0_loc_l),
    .if_dout(sum_negative_0_loc_l_dout),
    .if_empty_n(sum_negative_0_loc_l_empty_n),
    .if_read(Block_sin_taylor_ser_U0_ap_ready)
);

fifo_w64_d2_A tmp_loc_channel_U(
    .clk(ap_clk),
    .reset(ap_rst),
    .if_read_ce(1'b1),
    .if_write_ce(1'b1),
    .if_din(Block_sin_taylor_ser_U0_ap_return),
    .if_full_n(tmp_loc_channel_full_n),
    .if_write(Block_sin_taylor_ser_U0_ap_done),
    .if_dout(tmp_loc_channel_dout),
    .if_empty_n(tmp_loc_channel_empty_n),
    .if_read(p_source_files_sr_U0_ap_ready)
);

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_sync_reg_channel_write_sum_negative_0_loc_l <= 1'b0;
    end else begin
        if ((1'b1 == (Loop_sum_loop_proc_U0_ap_done & Loop_sum_loop_proc_U0_ap_continue))) begin
            ap_sync_reg_channel_write_sum_negative_0_loc_l <= 1'b0;
        end else begin
            ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst == 1'b1) begin
        ap_sync_reg_channel_write_sum_positive_0_loc_l <= 1'b0;
    end else begin
        if ((1'b1 == (Loop_sum_loop_proc_U0_ap_done & Loop_sum_loop_proc_U0_ap_continue))) begin
            ap_sync_reg_channel_write_sum_positive_0_loc_l <= 1'b0;
        end else begin
            ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
        end
    end
end

assign Block_sin_taylor_ser_U0_ap_continue = tmp_loc_channel_full_n;

assign Block_sin_taylor_ser_U0_ap_start = (sum_positive_0_loc_l_empty_n & sum_negative_0_loc_l_empty_n);

assign Block_sin_taylor_ser_U0_start_full_n = 1'b0;

assign Block_sin_taylor_ser_U0_start_write = 1'b0;

assign Loop_sum_loop_proc_U0_ap_continue = (ap_sync_channel_write_sum_negative_0_loc_l & ap_sync_channel_write_sum_positive_0_loc_l);

assign Loop_sum_loop_proc_U0_ap_start = ap_start;

assign Loop_sum_loop_proc_U0_start_full_n = 1'b0;

assign Loop_sum_loop_proc_U0_start_write = 1'b0;

assign ap_channel_done_sum_negative_0_loc_l = (Loop_sum_loop_proc_U0_ap_done & (ap_sync_reg_channel_write_sum_negative_0_loc_l ^ 1'b1));

assign ap_channel_done_sum_positive_0_loc_l = (Loop_sum_loop_proc_U0_ap_done & (ap_sync_reg_channel_write_sum_positive_0_loc_l ^ 1'b1));

assign ap_channel_done_tmp_loc_channel = Block_sin_taylor_ser_U0_ap_done;

assign ap_done = p_source_files_sr_U0_ap_done;

assign ap_idle = (Loop_sum_loop_proc_U0_ap_idle & Block_sin_taylor_ser_U0_ap_idle & p_source_files_sr_U0_ap_idle & (sum_positive_0_loc_l_empty_n ^ 1'b1) & (sum_negative_0_loc_l_empty_n ^ 1'b1) & (tmp_loc_channel_empty_n ^ 1'b1));

assign ap_ready = Loop_sum_loop_proc_U0_ap_ready;

assign ap_return = p_source_files_sr_U0_ap_return;

assign ap_sync_channel_write_sum_negative_0_loc_l = ((ap_channel_done_sum_negative_0_loc_l & sum_negative_0_loc_l_full_n) | ap_sync_reg_channel_write_sum_negative_0_loc_l);

assign ap_sync_channel_write_sum_positive_0_loc_l = ((ap_channel_done_sum_positive_0_loc_l & sum_positive_0_loc_l_full_n) | ap_sync_reg_channel_write_sum_positive_0_loc_l);

assign ap_sync_continue = 1'b1;

assign ap_sync_done = p_source_files_sr_U0_ap_done;

assign ap_sync_ready = Loop_sum_loop_proc_U0_ap_ready;

assign p_source_files_sr_U0_ap_continue = 1'b1;

assign p_source_files_sr_U0_ap_start = tmp_loc_channel_empty_n;

assign p_source_files_sr_U0_start_full_n = 1'b0;

assign p_source_files_sr_U0_start_write = 1'b0;

assign tmp_p_source_files_sr_fu_42_ap_return = 64'd0;

endmodule //sin_taylor_series
