`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 12/14/2015 05:20:43 PM
// Design Name: 
// Module Name: Problem4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Problem4(
    input A,
    input B,
    input C,
    input D,
    input E,
    output X
    );
    
    assign X = (~A & ~B & ~C & D & ~E) | (~A & ~B & ~C & D & E) | (~A & ~B & C & ~D & E) | (~A & ~B & C & D & E) | (~A & B & ~C & ~D & E) | (~A & B & ~C & D & E) | (~A & B & C & ~D & E) | (A & ~B & ~C & ~D & E) |(A & ~B & ~C & D & E) | (A & ~B & C & D & E) | (A & B & C & ~D & E) | (A & B & C & D & E);
//              00010                     00011                    00101                    00111                   01001                    01011                   01101                   10001                   10011                   10111                  11101                  11111                                                                                                               
    
endmodule
