// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module image_filter_Loop_1_proc (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        rows,
        cols,
        img_1_data_stream_0_V_din,
        img_1_data_stream_0_V_full_n,
        img_1_data_stream_0_V_write,
        img_1_data_stream_1_V_din,
        img_1_data_stream_1_V_full_n,
        img_1_data_stream_1_V_write,
        img_1_data_stream_2_V_din,
        img_1_data_stream_2_V_full_n,
        img_1_data_stream_2_V_write,
        img_0_data_stream_0_V_dout,
        img_0_data_stream_0_V_empty_n,
        img_0_data_stream_0_V_read,
        img_0_data_stream_1_V_dout,
        img_0_data_stream_1_V_empty_n,
        img_0_data_stream_1_V_read,
        img_0_data_stream_2_V_dout,
        img_0_data_stream_2_V_empty_n,
        img_0_data_stream_2_V_read,
        buffer_val_0_address0,
        buffer_val_0_ce0,
        buffer_val_0_we0,
        buffer_val_0_d0,
        buffer_val_0_q0,
        buffer_val_0_address1,
        buffer_val_0_ce1,
        buffer_val_0_we1,
        buffer_val_0_d1,
        buffer_val_0_q1,
        buffer_val_1_address0,
        buffer_val_1_ce0,
        buffer_val_1_we0,
        buffer_val_1_d0,
        buffer_val_1_q0,
        buffer_val_1_address1,
        buffer_val_1_ce1,
        buffer_val_1_we1,
        buffer_val_1_d1,
        buffer_val_1_q1,
        buffer_val_2_address0,
        buffer_val_2_ce0,
        buffer_val_2_we0,
        buffer_val_2_d0,
        buffer_val_2_q0,
        buffer_val_2_address1,
        buffer_val_2_ce1,
        buffer_val_2_we1,
        buffer_val_2_d1,
        buffer_val_2_q1
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 6'b1;
parameter    ap_ST_st2_fsm_1 = 6'b10;
parameter    ap_ST_pp0_stg0_fsm_2 = 6'b100;
parameter    ap_ST_pp0_stg1_fsm_3 = 6'b1000;
parameter    ap_ST_pp0_stg2_fsm_4 = 6'b10000;
parameter    ap_ST_st7_fsm_5 = 6'b100000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv1_0 = 1'b0;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv11_0 = 11'b00000000000;
parameter    ap_const_lv64_1 = 64'b1;
parameter    ap_const_lv64_2 = 64'b10;
parameter    ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter    ap_const_lv11_1 = 11'b1;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv10_0 = 10'b0000000000;
parameter    ap_true = 1'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [31:0] rows;
input  [31:0] cols;
output  [7:0] img_1_data_stream_0_V_din;
input   img_1_data_stream_0_V_full_n;
output   img_1_data_stream_0_V_write;
output  [7:0] img_1_data_stream_1_V_din;
input   img_1_data_stream_1_V_full_n;
output   img_1_data_stream_1_V_write;
output  [7:0] img_1_data_stream_2_V_din;
input   img_1_data_stream_2_V_full_n;
output   img_1_data_stream_2_V_write;
input  [7:0] img_0_data_stream_0_V_dout;
input   img_0_data_stream_0_V_empty_n;
output   img_0_data_stream_0_V_read;
input  [7:0] img_0_data_stream_1_V_dout;
input   img_0_data_stream_1_V_empty_n;
output   img_0_data_stream_1_V_read;
input  [7:0] img_0_data_stream_2_V_dout;
input   img_0_data_stream_2_V_empty_n;
output   img_0_data_stream_2_V_read;
output  [1:0] buffer_val_0_address0;
output   buffer_val_0_ce0;
output   buffer_val_0_we0;
output  [7:0] buffer_val_0_d0;
input  [7:0] buffer_val_0_q0;
output  [1:0] buffer_val_0_address1;
output   buffer_val_0_ce1;
output   buffer_val_0_we1;
output  [7:0] buffer_val_0_d1;
input  [7:0] buffer_val_0_q1;
output  [1:0] buffer_val_1_address0;
output   buffer_val_1_ce0;
output   buffer_val_1_we0;
output  [7:0] buffer_val_1_d0;
input  [7:0] buffer_val_1_q0;
output  [1:0] buffer_val_1_address1;
output   buffer_val_1_ce1;
output   buffer_val_1_we1;
output  [7:0] buffer_val_1_d1;
input  [7:0] buffer_val_1_q1;
output  [1:0] buffer_val_2_address0;
output   buffer_val_2_ce0;
output   buffer_val_2_we0;
output  [7:0] buffer_val_2_d0;
input  [7:0] buffer_val_2_q0;
output  [1:0] buffer_val_2_address1;
output   buffer_val_2_ce1;
output   buffer_val_2_we1;
output  [7:0] buffer_val_2_d1;
input  [7:0] buffer_val_2_q1;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_1_data_stream_0_V_write;
reg img_1_data_stream_1_V_write;
reg img_1_data_stream_2_V_write;
reg img_0_data_stream_0_V_read;
reg img_0_data_stream_1_V_read;
reg img_0_data_stream_2_V_read;
reg[1:0] buffer_val_0_address0;
reg buffer_val_0_ce0;
reg buffer_val_0_we0;
reg[7:0] buffer_val_0_d0;
reg buffer_val_0_ce1;
reg buffer_val_0_we1;
reg[1:0] buffer_val_1_address0;
reg buffer_val_1_ce0;
reg buffer_val_1_we0;
reg[7:0] buffer_val_1_d0;
reg buffer_val_1_ce1;
reg buffer_val_1_we1;
reg[1:0] buffer_val_2_address0;
reg buffer_val_2_ce0;
reg buffer_val_2_we0;
reg[7:0] buffer_val_2_d0;
reg[1:0] buffer_val_2_address1;
reg buffer_val_2_ce1;
reg buffer_val_2_we1;
reg    ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg   [5:0] ap_CS_fsm = 6'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_25;
reg   [10:0] col_reg_269;
wire   [11:0] tmp_fu_281_p1;
reg    ap_sig_bdd_104;
wire   [11:0] tmp_2_fu_285_p1;
wire   [1:0] buffer_val_0_addr_gep_fu_159_p3;
reg   [1:0] buffer_val_0_addr_reg_551;
wire   [1:0] buffer_val_0_addr_1_gep_fu_167_p3;
reg   [1:0] buffer_val_0_addr_1_reg_556;
wire   [1:0] buffer_val_1_addr_gep_fu_175_p3;
reg   [1:0] buffer_val_1_addr_reg_561;
wire   [1:0] buffer_val_1_addr_1_gep_fu_183_p3;
reg   [1:0] buffer_val_1_addr_1_reg_566;
wire   [1:0] buffer_val_2_addr_gep_fu_191_p3;
reg   [1:0] buffer_val_2_addr_reg_571;
wire   [1:0] buffer_val_2_addr_1_gep_fu_199_p3;
reg   [1:0] buffer_val_2_addr_1_reg_577;
wire   [1:0] buffer_val_0_addr_2_gep_fu_207_p3;
reg   [1:0] buffer_val_0_addr_2_reg_582;
wire   [1:0] buffer_val_1_addr_2_gep_fu_215_p3;
reg   [1:0] buffer_val_1_addr_2_reg_587;
wire   [1:0] buffer_val_2_addr_2_gep_fu_223_p3;
reg   [1:0] buffer_val_2_addr_2_reg_592;
wire   [0:0] exitcond2_fu_293_p2;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_134;
wire   [10:0] row_1_fu_298_p2;
reg   [10:0] row_1_reg_602;
wire   [0:0] exitcond1_fu_308_p2;
reg   [0:0] exitcond1_reg_607;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg    ap_sig_bdd_145;
reg    ap_reg_ppiten_pp0_it0 = 1'b0;
reg    ap_sig_bdd_159;
reg    ap_reg_ppiten_pp0_it1 = 1'b0;
wire   [10:0] col_1_fu_313_p2;
reg   [10:0] col_1_reg_611;
wire   [0:0] icmp_fu_329_p2;
reg   [0:0] icmp_reg_616;
reg   [7:0] scl_val_0_reg_624;
reg    ap_sig_cseq_ST_pp0_stg1_fsm_3;
reg    ap_sig_bdd_180;
reg    ap_sig_bdd_190;
reg   [7:0] scl_val_1_reg_630;
reg   [7:0] p_val_2_reg_636;
reg   [7:0] buffer_val_0_load_reg_643;
reg   [7:0] buffer_val_1_load_reg_649;
reg   [7:0] buffer_val_2_load_reg_655;
reg   [7:0] buffer_val_0_load_1_reg_660;
reg   [7:0] buffer_val_1_load_1_reg_665;
reg   [7:0] buffer_val_2_load_1_reg_670;
wire   [0:0] c_fu_335_p2;
reg   [0:0] c_reg_675;
wire   [0:0] ult_fu_341_p2;
reg   [0:0] ult_reg_681;
wire   [0:0] rev1_fu_353_p2;
reg   [0:0] rev1_reg_686;
wire   [0:0] c_1_fu_359_p2;
reg   [0:0] c_1_reg_691;
wire   [0:0] ult2_fu_365_p2;
reg   [0:0] ult2_reg_697;
wire   [0:0] rev3_fu_377_p2;
reg   [0:0] rev3_reg_702;
wire   [0:0] c_2_fu_383_p2;
reg   [0:0] c_2_reg_707;
wire   [0:0] ult4_fu_389_p2;
reg   [0:0] ult4_reg_713;
wire   [0:0] ult5_fu_395_p2;
reg   [0:0] ult5_reg_718;
wire   [7:0] p_val_0_1_fu_427_p3;
reg   [7:0] p_val_0_1_reg_723;
reg    ap_sig_cseq_ST_pp0_stg2_fsm_4;
reg    ap_sig_bdd_230;
wire   [7:0] p_val_1_1_fu_460_p3;
reg   [7:0] p_val_1_1_reg_728;
wire   [7:0] p_val_0_2_fu_499_p3;
reg   [7:0] p_val_0_2_reg_733;
wire   [0:0] sel_tmp2_fu_505_p2;
reg   [0:0] sel_tmp2_reg_738;
wire   [7:0] p_val_1_2_fu_510_p3;
reg   [7:0] p_val_1_2_reg_744;
wire   [7:0] tmp_6_fu_521_p3;
reg   [7:0] tmp_6_reg_749;
reg   [10:0] row_reg_258;
reg    ap_sig_cseq_ST_st7_fsm_5;
reg    ap_sig_bdd_257;
reg   [10:0] col_phi_fu_273_p4;
wire   [11:0] row_cast_fu_289_p1;
wire   [11:0] col_cast_fu_304_p1;
wire   [9:0] tmp_3_fu_319_p4;
wire   [0:0] ult1_fu_347_p2;
wire   [0:0] ult3_fu_371_p2;
wire   [0:0] rev_fu_401_p2;
wire   [0:0] c_0_not_fu_406_p2;
wire   [0:0] brmerge1_fu_417_p2;
wire   [0:0] brmerge_fu_411_p2;
wire   [7:0] buffer_val_0_load_scl_val_0_fu_421_p3;
wire   [0:0] rev2_fu_434_p2;
wire   [0:0] c_0_not_1_fu_439_p2;
wire   [0:0] brmerge1_1_fu_450_p2;
wire   [0:0] brmerge_1_fu_444_p2;
wire   [7:0] buffer_val_1_load_scl_val_1_fu_454_p3;
wire   [0:0] rev4_fu_467_p2;
wire   [0:0] c_0_not_2_fu_472_p2;
wire   [0:0] rev5_fu_483_p2;
wire   [0:0] brmerge1_2_fu_488_p2;
wire   [0:0] brmerge_2_fu_477_p2;
wire   [7:0] buffer_val_2_load_p_val_2_fu_493_p3;
wire   [7:0] sel_tmp9_fu_516_p3;
reg   [5:0] ap_NS_fsm;




/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
    if (ap_rst == 1'b1) begin
        ap_done_reg <= ap_const_logic_0;
    end else begin
        if ((ap_const_logic_1 == ap_continue)) begin
            ap_done_reg <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
            ap_done_reg <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
    end else begin
        if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
        end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4) & ~(exitcond1_reg_607 == ap_const_lv1_0)))) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        col_reg_269 <= col_1_reg_611;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
        col_reg_269 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_104)) begin
        row_reg_258 <= ap_const_lv11_0;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5)) begin
        row_reg_258 <= row_1_reg_602;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        buffer_val_0_load_1_reg_660 <= buffer_val_0_q1;
        buffer_val_0_load_reg_643 <= buffer_val_0_q0;
        buffer_val_1_load_1_reg_665 <= buffer_val_1_q1;
        buffer_val_1_load_reg_649 <= buffer_val_1_q0;
        buffer_val_2_load_1_reg_670 <= buffer_val_2_q1;
        buffer_val_2_load_reg_655 <= buffer_val_2_q0;
        c_1_reg_691 <= c_1_fu_359_p2;
        c_2_reg_707 <= c_2_fu_383_p2;
        c_reg_675 <= c_fu_335_p2;
        p_val_2_reg_636 <= img_0_data_stream_2_V_dout;
        rev1_reg_686 <= rev1_fu_353_p2;
        rev3_reg_702 <= rev3_fu_377_p2;
        scl_val_0_reg_624 <= img_0_data_stream_0_V_dout;
        scl_val_1_reg_630 <= img_0_data_stream_1_V_dout;
        ult2_reg_697 <= ult2_fu_365_p2;
        ult4_reg_713 <= ult4_fu_389_p2;
        ult5_reg_718 <= ult5_fu_395_p2;
        ult_reg_681 <= ult_fu_341_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        col_1_reg_611 <= col_1_fu_313_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        exitcond1_reg_607 <= exitcond1_fu_308_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
        icmp_reg_616 <= icmp_fu_329_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
        p_val_0_1_reg_723 <= p_val_0_1_fu_427_p3;
        p_val_0_2_reg_733 <= p_val_0_2_fu_499_p3;
        p_val_1_1_reg_728 <= p_val_1_1_fu_460_p3;
        p_val_1_2_reg_744 <= p_val_1_2_fu_510_p3;
        sel_tmp2_reg_738 <= sel_tmp2_fu_505_p2;
        tmp_6_reg_749 <= tmp_6_fu_521_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        row_1_reg_602 <= row_1_fu_298_p2;
    end
end

/// ap_done assign process. ///
always @ (ap_done_reg or exitcond2_fu_293_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
    if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0)))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (exitcond2_fu_293_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_145)
begin
    if (ap_sig_bdd_145) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg1_fsm_3 assign process. ///
always @ (ap_sig_bdd_180)
begin
    if (ap_sig_bdd_180) begin
        ap_sig_cseq_ST_pp0_stg1_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg1_fsm_3 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg2_fsm_4 assign process. ///
always @ (ap_sig_bdd_230)
begin
    if (ap_sig_bdd_230) begin
        ap_sig_cseq_ST_pp0_stg2_fsm_4 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg2_fsm_4 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_25)
begin
    if (ap_sig_bdd_25) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_134)
begin
    if (ap_sig_bdd_134) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st7_fsm_5 assign process. ///
always @ (ap_sig_bdd_257)
begin
    if (ap_sig_bdd_257) begin
        ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_0;
    end
end

/// buffer_val_0_address0 assign process. ///
always @ (buffer_val_0_addr_reg_551 or buffer_val_0_addr_1_reg_556 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
        buffer_val_0_address0 = buffer_val_0_addr_1_reg_556;
    end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)))) begin
        buffer_val_0_address0 = buffer_val_0_addr_reg_551;
    end else begin
        buffer_val_0_address0 = 'bx;
    end
end

/// buffer_val_0_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_0_ce0 = ap_const_logic_1;
    end else begin
        buffer_val_0_ce0 = ap_const_logic_0;
    end
end

/// buffer_val_0_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
        buffer_val_0_ce1 = ap_const_logic_1;
    end else begin
        buffer_val_0_ce1 = ap_const_logic_0;
    end
end

/// buffer_val_0_d0 assign process. ///
always @ (buffer_val_0_q1 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or buffer_val_0_load_reg_643 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
            buffer_val_0_d0 = buffer_val_0_load_reg_643;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
            buffer_val_0_d0 = buffer_val_0_q1;
        end else begin
            buffer_val_0_d0 = 'bx;
        end
    end else begin
        buffer_val_0_d0 = 'bx;
    end
end

/// buffer_val_0_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_0_we0 = ap_const_logic_1;
    end else begin
        buffer_val_0_we0 = ap_const_logic_0;
    end
end

/// buffer_val_0_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        buffer_val_0_we1 = ap_const_logic_1;
    end else begin
        buffer_val_0_we1 = ap_const_logic_0;
    end
end

/// buffer_val_1_address0 assign process. ///
always @ (buffer_val_1_addr_reg_561 or buffer_val_1_addr_1_reg_566 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
        buffer_val_1_address0 = buffer_val_1_addr_1_reg_566;
    end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)))) begin
        buffer_val_1_address0 = buffer_val_1_addr_reg_561;
    end else begin
        buffer_val_1_address0 = 'bx;
    end
end

/// buffer_val_1_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_1_ce0 = ap_const_logic_1;
    end else begin
        buffer_val_1_ce0 = ap_const_logic_0;
    end
end

/// buffer_val_1_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
        buffer_val_1_ce1 = ap_const_logic_1;
    end else begin
        buffer_val_1_ce1 = ap_const_logic_0;
    end
end

/// buffer_val_1_d0 assign process. ///
always @ (buffer_val_1_q1 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or buffer_val_1_load_reg_649 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
            buffer_val_1_d0 = buffer_val_1_load_reg_649;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
            buffer_val_1_d0 = buffer_val_1_q1;
        end else begin
            buffer_val_1_d0 = 'bx;
        end
    end else begin
        buffer_val_1_d0 = 'bx;
    end
end

/// buffer_val_1_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_1_we0 = ap_const_logic_1;
    end else begin
        buffer_val_1_we0 = ap_const_logic_0;
    end
end

/// buffer_val_1_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        buffer_val_1_we1 = ap_const_logic_1;
    end else begin
        buffer_val_1_we1 = ap_const_logic_0;
    end
end

/// buffer_val_2_address0 assign process. ///
always @ (buffer_val_2_addr_reg_571 or buffer_val_2_addr_1_reg_577 or buffer_val_2_addr_2_reg_592 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
            buffer_val_2_address0 = buffer_val_2_addr_2_reg_592;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
            buffer_val_2_address0 = buffer_val_2_addr_1_reg_577;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2)) begin
            buffer_val_2_address0 = buffer_val_2_addr_reg_571;
        end else begin
            buffer_val_2_address0 = 'bx;
        end
    end else begin
        buffer_val_2_address0 = 'bx;
    end
end

/// buffer_val_2_address1 assign process. ///
always @ (buffer_val_2_addr_reg_571 or buffer_val_2_addr_2_reg_592 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
            buffer_val_2_address1 = buffer_val_2_addr_reg_571;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2)) begin
            buffer_val_2_address1 = buffer_val_2_addr_2_reg_592;
        end else begin
            buffer_val_2_address1 = 'bx;
        end
    end else begin
        buffer_val_2_address1 = 'bx;
    end
end

/// buffer_val_2_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_2_ce0 = ap_const_logic_1;
    end else begin
        buffer_val_2_ce0 = ap_const_logic_0;
    end
end

/// buffer_val_2_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
        buffer_val_2_ce1 = ap_const_logic_1;
    end else begin
        buffer_val_2_ce1 = ap_const_logic_0;
    end
end

/// buffer_val_2_d0 assign process. ///
always @ (buffer_val_2_q0 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or p_val_2_reg_636 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
        if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
            buffer_val_2_d0 = p_val_2_reg_636;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
            buffer_val_2_d0 = buffer_val_2_q0;
        end else begin
            buffer_val_2_d0 = 'bx;
        end
    end else begin
        buffer_val_2_d0 = 'bx;
    end
end

/// buffer_val_2_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
    if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
        buffer_val_2_we0 = ap_const_logic_1;
    end else begin
        buffer_val_2_we0 = ap_const_logic_0;
    end
end

/// buffer_val_2_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        buffer_val_2_we1 = ap_const_logic_1;
    end else begin
        buffer_val_2_we1 = ap_const_logic_0;
    end
end

/// col_phi_fu_273_p4 assign process. ///
always @ (col_reg_269 or exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it1 or col_1_reg_611)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
        col_phi_fu_273_p4 = col_1_reg_611;
    end else begin
        col_phi_fu_273_p4 = col_reg_269;
    end
end

/// img_0_data_stream_0_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        img_0_data_stream_0_V_read = ap_const_logic_1;
    end else begin
        img_0_data_stream_0_V_read = ap_const_logic_0;
    end
end

/// img_0_data_stream_1_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        img_0_data_stream_1_V_read = ap_const_logic_1;
    end else begin
        img_0_data_stream_1_V_read = ap_const_logic_0;
    end
end

/// img_0_data_stream_2_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
        img_0_data_stream_2_V_read = ap_const_logic_1;
    end else begin
        img_0_data_stream_2_V_read = ap_const_logic_0;
    end
end

/// img_1_data_stream_0_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        img_1_data_stream_0_V_write = ap_const_logic_1;
    end else begin
        img_1_data_stream_0_V_write = ap_const_logic_0;
    end
end

/// img_1_data_stream_1_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        img_1_data_stream_1_V_write = ap_const_logic_1;
    end else begin
        img_1_data_stream_1_V_write = ap_const_logic_0;
    end
end

/// img_1_data_stream_2_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
        img_1_data_stream_2_V_write = ap_const_logic_1;
    end else begin
        img_1_data_stream_2_V_write = ap_const_logic_0;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_104 or exitcond2_fu_293_p2 or exitcond1_fu_308_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_190)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~ap_sig_bdd_104) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            if (~(exitcond2_fu_293_p2 == ap_const_lv1_0)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
            end
        end
        ap_ST_pp0_stg0_fsm_2 : 
        begin
            if ((~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0)))) begin
                ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
            end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
                ap_NS_fsm = ap_ST_st7_fsm_5;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
            end
        end
        ap_ST_pp0_stg1_fsm_3 : 
        begin
            if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) begin
                ap_NS_fsm = ap_ST_pp0_stg2_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
            end
        end
        ap_ST_pp0_stg2_fsm_4 : 
        begin
            ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
        end
        ap_ST_st7_fsm_5 : 
        begin
            ap_NS_fsm = ap_ST_st2_fsm_1;
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end


/// ap_sig_bdd_104 assign process. ///
always @ (ap_start or ap_done_reg)
begin
    ap_sig_bdd_104 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end

/// ap_sig_bdd_134 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_134 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_145 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_145 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end

/// ap_sig_bdd_159 assign process. ///
always @ (img_1_data_stream_0_V_full_n or img_1_data_stream_1_V_full_n or img_1_data_stream_2_V_full_n or exitcond1_reg_607)
begin
    ap_sig_bdd_159 = (((img_1_data_stream_0_V_full_n == ap_const_logic_0) & (exitcond1_reg_607 == ap_const_lv1_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_1_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_1_data_stream_2_V_full_n == ap_const_logic_0)));
end

/// ap_sig_bdd_180 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_180 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_190 assign process. ///
always @ (img_0_data_stream_0_V_empty_n or img_0_data_stream_1_V_empty_n or img_0_data_stream_2_V_empty_n or exitcond1_reg_607)
begin
    ap_sig_bdd_190 = (((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_0_V_empty_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_2_V_empty_n == ap_const_logic_0)));
end

/// ap_sig_bdd_230 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_230 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end

/// ap_sig_bdd_25 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_25 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_257 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_257 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
assign brmerge1_1_fu_450_p2 = (rev3_reg_702 | c_1_reg_691);
assign brmerge1_2_fu_488_p2 = (rev5_fu_483_p2 | c_2_reg_707);
assign brmerge1_fu_417_p2 = (rev1_reg_686 | c_reg_675);
assign brmerge_1_fu_444_p2 = (rev2_fu_434_p2 | c_0_not_1_fu_439_p2);
assign brmerge_2_fu_477_p2 = (rev4_fu_467_p2 | c_0_not_2_fu_472_p2);
assign brmerge_fu_411_p2 = (rev_fu_401_p2 | c_0_not_fu_406_p2);
assign buffer_val_0_addr_1_gep_fu_167_p3 = ap_const_lv64_2;
assign buffer_val_0_addr_2_gep_fu_207_p3 = ap_const_lv64_0;
assign buffer_val_0_addr_gep_fu_159_p3 = ap_const_lv64_1;
assign buffer_val_0_address1 = buffer_val_0_addr_2_reg_582;
assign buffer_val_0_d1 = img_0_data_stream_0_V_dout;
assign buffer_val_0_load_scl_val_0_fu_421_p3 = ((brmerge1_fu_417_p2)? buffer_val_0_load_reg_643: scl_val_0_reg_624);
assign buffer_val_1_addr_1_gep_fu_183_p3 = ap_const_lv64_2;
assign buffer_val_1_addr_2_gep_fu_215_p3 = ap_const_lv64_0;
assign buffer_val_1_addr_gep_fu_175_p3 = ap_const_lv64_1;
assign buffer_val_1_address1 = buffer_val_1_addr_2_reg_587;
assign buffer_val_1_d1 = img_0_data_stream_1_V_dout;
assign buffer_val_1_load_scl_val_1_fu_454_p3 = ((brmerge1_1_fu_450_p2)? buffer_val_1_load_reg_649: scl_val_1_reg_630);
assign buffer_val_2_addr_1_gep_fu_199_p3 = ap_const_lv64_2;
assign buffer_val_2_addr_2_gep_fu_223_p3 = ap_const_lv64_0;
assign buffer_val_2_addr_gep_fu_191_p3 = ap_const_lv64_1;
assign buffer_val_2_d1 = buffer_val_2_q1;
assign buffer_val_2_load_p_val_2_fu_493_p3 = ((brmerge1_2_fu_488_p2)? buffer_val_2_load_reg_655: p_val_2_reg_636);
assign c_0_not_1_fu_439_p2 = (c_1_reg_691 ^ ap_const_lv1_1);
assign c_0_not_2_fu_472_p2 = (c_2_reg_707 ^ ap_const_lv1_1);
assign c_0_not_fu_406_p2 = (c_reg_675 ^ ap_const_lv1_1);
assign c_1_fu_359_p2 = (buffer_val_1_q1 > img_0_data_stream_1_V_dout? 1'b1: 1'b0);
assign c_2_fu_383_p2 = (buffer_val_2_q1 > img_0_data_stream_2_V_dout? 1'b1: 1'b0);
assign c_fu_335_p2 = (buffer_val_0_q1 > img_0_data_stream_0_V_dout? 1'b1: 1'b0);
assign col_1_fu_313_p2 = (col_phi_fu_273_p4 + ap_const_lv11_1);
assign col_cast_fu_304_p1 = col_phi_fu_273_p4;
assign exitcond1_fu_308_p2 = (col_cast_fu_304_p1 == tmp_2_fu_285_p1? 1'b1: 1'b0);
assign exitcond2_fu_293_p2 = (row_cast_fu_289_p1 == tmp_fu_281_p1? 1'b1: 1'b0);
assign icmp_fu_329_p2 = (tmp_3_fu_319_p4 != ap_const_lv10_0? 1'b1: 1'b0);
assign img_1_data_stream_0_V_din = ((sel_tmp2_reg_738)? p_val_0_1_reg_723: p_val_0_2_reg_733);
assign img_1_data_stream_1_V_din = ((sel_tmp2_reg_738)? p_val_1_1_reg_728: p_val_1_2_reg_744);
assign img_1_data_stream_2_V_din = tmp_6_reg_749;
assign p_val_0_1_fu_427_p3 = ((brmerge_fu_411_p2)? buffer_val_0_load_scl_val_0_fu_421_p3: buffer_val_0_load_1_reg_660);
assign p_val_0_2_fu_499_p3 = ((icmp_reg_616)? p_val_0_1_fu_427_p3: scl_val_0_reg_624);
assign p_val_1_1_fu_460_p3 = ((brmerge_1_fu_444_p2)? buffer_val_1_load_scl_val_1_fu_454_p3: buffer_val_1_load_1_reg_665);
assign p_val_1_2_fu_510_p3 = ((icmp_reg_616)? p_val_1_1_fu_460_p3: scl_val_1_reg_630);
assign rev1_fu_353_p2 = (ult1_fu_347_p2 ^ ap_const_lv1_1);
assign rev2_fu_434_p2 = (ult2_reg_697 ^ ap_const_lv1_1);
assign rev3_fu_377_p2 = (ult3_fu_371_p2 ^ ap_const_lv1_1);
assign rev4_fu_467_p2 = (ult4_reg_713 ^ ap_const_lv1_1);
assign rev5_fu_483_p2 = (ult5_reg_718 ^ ap_const_lv1_1);
assign rev_fu_401_p2 = (ult_reg_681 ^ ap_const_lv1_1);
assign row_1_fu_298_p2 = (row_reg_258 + ap_const_lv11_1);
assign row_cast_fu_289_p1 = row_reg_258;
assign sel_tmp2_fu_505_p2 = (icmp_reg_616 & brmerge_2_fu_477_p2);
assign sel_tmp9_fu_516_p3 = ((icmp_reg_616)? buffer_val_2_load_1_reg_670: p_val_2_reg_636);
assign tmp_2_fu_285_p1 = cols[11:0];
assign tmp_3_fu_319_p4 = {{col_phi_fu_273_p4[ap_const_lv32_A : ap_const_lv32_1]}};
assign tmp_6_fu_521_p3 = ((sel_tmp2_fu_505_p2)? buffer_val_2_load_p_val_2_fu_493_p3: sel_tmp9_fu_516_p3);
assign tmp_fu_281_p1 = rows[11:0];
assign ult1_fu_347_p2 = (img_0_data_stream_0_V_dout < buffer_val_0_q0? 1'b1: 1'b0);
assign ult2_fu_365_p2 = (buffer_val_1_q1 < buffer_val_1_q0? 1'b1: 1'b0);
assign ult3_fu_371_p2 = (img_0_data_stream_1_V_dout < buffer_val_1_q0? 1'b1: 1'b0);
assign ult4_fu_389_p2 = (buffer_val_2_q1 < buffer_val_2_q0? 1'b1: 1'b0);
assign ult5_fu_395_p2 = (img_0_data_stream_2_V_dout < buffer_val_2_q0? 1'b1: 1'b0);
assign ult_fu_341_p2 = (buffer_val_0_q1 < buffer_val_0_q0? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
    buffer_val_0_addr_reg_551[1:0] <= 2'b01;
    buffer_val_0_addr_1_reg_556[1:0] <= 2'b10;
    buffer_val_1_addr_reg_561[1:0] <= 2'b01;
    buffer_val_1_addr_1_reg_566[1:0] <= 2'b10;
    buffer_val_2_addr_reg_571[1:0] <= 2'b01;
    buffer_val_2_addr_1_reg_577[1:0] <= 2'b10;
    buffer_val_0_addr_2_reg_582[1:0] <= 2'b00;
    buffer_val_1_addr_2_reg_587[1:0] <= 2'b00;
    buffer_val_2_addr_2_reg_592[1:0] <= 2'b00;
end



endmodule //image_filter_Loop_1_proc

