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// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0

`timescale 1ns/1ps

(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_4_0 (
  Din,
  Dout
);

input wire [31 : 0] Din;
output wire [23 : 0] Dout;

  xlslice #(
    .DIN_WIDTH(32),
    .DIN_FROM(29),
    .DIN_TO(6)
  ) inst (
    .Din(Din),
    .Dout(Dout)
  );
endmodule
