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// You must compile the wrapper file dp_ram.v when simulating
// the core, dp_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

`timescale 1ns/1ps

module dp_ram(
  s_aclk,
  s_aresetn,
  s_axis_tvalid,
  s_axis_tready,
  s_axis_tdata,
  m_axis_tvalid,
  m_axis_tready,
  m_axis_tdata,
  axis_data_count
);

input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [7 : 0] s_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
output [7 : 0] m_axis_tdata;
output [11 : 0] axis_data_count;

endmodule