//****************************************************************************************************  
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
//                   --              It to be define                --
//                   --                    ...                      --
//                   --                    ...                      --
//                   --                    ...                      --
//**************************************************************************************************** 
//File Information
//**************************************************************************************************** 
//File Name      : bus_addr_dec.v 
//Project Name   : azpr_soc
//Description    : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_addr_dec.v
//License        : CPL
//**************************************************************************************************** 
//Version Information
//**************************************************************************************************** 
//Create Date    : 01-07-2016 17:00(1th Fri,July,2016)
//First Author   : lichangbeiju
//Modify Date    : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author    : lichangbeiju
//Version Number : 002   
//Last Commit    : 03-09-2016 14:30(1th Sun,July,2016)
//**************************************************************************************************** 
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//**************************************************************************************************** 
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add io port.
//**************************************************************************************************** 
`include "../sys_include.h"

`include "bus.h"
module bus_addr_dec(
    input   wire    [`WordAddrBus]  s_addr      ,//30   address
    output  reg                     s0_cs_n     ,//01   slave 0 chip select rom
    output  reg                     s1_cs_n     ,//01   slave 1 chip select spm
    output  reg                     s2_cs_n     ,//01   slave 2 chip select timer
    output  reg                     s3_cs_n     ,//01   slave 3 chip select uart
    output  reg                     s4_cs_n     ,//01   slave 4 chip select gpio
    output  reg                     s5_cs_n     ,//01   slave 5 chip select nc
    output  reg                     s6_cs_n     ,//01   slave 6 chip select nc
    output  reg                     s7_cs_n      //01   slave 7 chip select nc

);

    //************************************************************************************************
    // 1.Parameter and constant define
    //************************************************************************************************
    
//    `define UDP
//    `define CLK_TEST_EN
    
    //************************************************************************************************
    // 2.Register and wire declaration
    //************************************************************************************************
    //------------------------------------------------------------------------------------------------
    // 2.1 the output reg
    //------------------------------------------------------------------------------------------------   

    //------------------------------------------------------------------------------------------------
    // 2.x the test logic
    //------------------------------------------------------------------------------------------------
    wire    [02:00]         s_index     ;//the bus slave index

    //************************************************************************************************
    // 3.Main code
    //************************************************************************************************

    assign s_index = s_addr[`BusSlaveIndexLoc];

    //------------------------------------------------------------------------------------------------
    // 3.1 the master grant logic
    //------------------------------------------------------------------------------------------------
    
    always @(*) begin : BUS_SLAVE_INDEX
        s0_cs_n = `DISABLE_N;
        s1_cs_n = `DISABLE_N;
        s2_cs_n = `DISABLE_N;
        s3_cs_n = `DISABLE_N;
        s4_cs_n = `DISABLE_N;
        s5_cs_n = `DISABLE_N;
        s6_cs_n = `DISABLE_N;
        s7_cs_n = `DISABLE_N;
        case(s_index)
            `BUS_SLAVE_0    :   begin
                s0_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_1    :   begin
                s1_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_2    :   begin
                s2_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_3    :   begin
                s3_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_4    :   begin
                s4_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_5    :   begin
                s5_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_6    :   begin
                s6_cs_n = `ENABLE_N;
            end
            `BUS_SLAVE_7    :   begin
                s7_cs_n = `ENABLE_N;
            end
        endcase
    end
    
     
    //------------------------------------------------------------------------------------------------
    // 3.2 the master owner control logic
    //------------------------------------------------------------------------------------------------
    

    
    //************************************************************************************************
    // 4.Sub module instantiation
    //************************************************************************************************
    //------------------------------------------------------------------------------------------------
    // 4.1 the clk generate module
    //------------------------------------------------------------------------------------------------    
    
endmodule    
//****************************************************************************************************
//End of Module
//****************************************************************************************************
