`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: David Ariando
// 
// Create Date:    22:22:00 01/31/2018 
// Project Name:   EECS301 Digital Design
// Design Name:    Lab #2 Project
// Module Name:    TF_CLS_PWM_Interval_Timer.v
// Target Devices: Altera Cyclone V
// Tool versions:  Quartus v17.1
// Description:    CLS Scan Rate Timer Timer Testbench
//                 
// Dependencies:   
//
//////////////////////////////////////////////////////////////////////////////////

module TF_CLS_Scan_Rate_Timer();
	
	wire SRT_TICK;
	reg  CLOCK_50;
	reg [1:0] RATE_SELECT;

	//
	// System Clock Emulation
	//
	// Toggle the CLOCK_50 signal every 10 ns to create to 50MHz clock signal
	//
	localparam CLK_RATE_HZ = 50000000; // Hz
	localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * 1000000000.0) / 2.0; // ns
	
	initial
	begin
		CLOCK_50 = 1'b0;
		forever #(CLK_HALF_PER) CLOCK_50 = ~CLOCK_50;
	end
	
	initial
	begin
		RATE_SELECT = 2'h0;
	end

	
	CLS_Scan_Rate_Timer
	#(
		.CLK_RATE_HZ (CLK_RATE_HZ)  // Hz
	)
	uut
	(
		// Input Signals
		.RATE_SELECT (RATE_SELECT),
		
		// Output Signals
		.SRT_TICK (SRT_TICK),
		
		// System Signals
		.CLK (CLOCK_50)
	);
endmodule