// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
//  by:  wig
//  on:  Mon Oct 24 10:52:44 2005
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.1 2005/10/25 13:15:35 wig Exp $
// $Date: 2005/10/25 13:15:35 $
// $Log: ent_ba.v,v $
// Revision 1.1  2005/10/25 13:15:35  wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp 
//
// Generator: mix_0.pl Revision: 1.38 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns / 1ps

//
//
// Start of Generated Module rtl of ent_ba
//

	// No `defines in this module


module ent_ba
//
// Generated module inst_ba
//
		(
		);
// End of generated module header


	// Internal signals

		//
		// Generated Signal List
		//
		//
		// End of Generated Signal List
		//


	// %COMPILER_OPTS%

	// Generated Signal Assignments




	//
	// Generated Instances
	// wiring ...

	// Generated Instances and Port Mappings


endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
