// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

module image_filter_Erode_32_32_1080_1920_s (
        ap_clk,
        ap_rst,
        ap_start,
        ap_done,
        ap_continue,
        ap_idle,
        ap_ready,
        p_src_rows_V_read,
        p_src_cols_V_read,
        p_src_data_stream_0_V_dout,
        p_src_data_stream_0_V_empty_n,
        p_src_data_stream_0_V_read,
        p_src_data_stream_1_V_dout,
        p_src_data_stream_1_V_empty_n,
        p_src_data_stream_1_V_read,
        p_src_data_stream_2_V_dout,
        p_src_data_stream_2_V_empty_n,
        p_src_data_stream_2_V_read,
        p_dst_data_stream_0_V_din,
        p_dst_data_stream_0_V_full_n,
        p_dst_data_stream_0_V_write,
        p_dst_data_stream_1_V_din,
        p_dst_data_stream_1_V_full_n,
        p_dst_data_stream_1_V_write,
        p_dst_data_stream_2_V_din,
        p_dst_data_stream_2_V_full_n,
        p_dst_data_stream_2_V_write
);

parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 8'b1;
parameter    ap_ST_st2_fsm_1 = 8'b10;
parameter    ap_ST_st3_fsm_2 = 8'b100;
parameter    ap_ST_st4_fsm_3 = 8'b1000;
parameter    ap_ST_st5_fsm_4 = 8'b10000;
parameter    ap_ST_st6_fsm_5 = 8'b100000;
parameter    ap_ST_pp0_stg0_fsm_6 = 8'b1000000;
parameter    ap_ST_st20_fsm_7 = 8'b10000000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv1_1 = 1'b1;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv32_2 = 32'b10;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv1_0 = 1'b0;
parameter    ap_const_lv32_4 = 32'b100;
parameter    ap_const_lv32_5 = 32'b101;
parameter    ap_const_lv32_6 = 32'b110;
parameter    ap_const_lv2_0 = 2'b00;
parameter    ap_const_lv11_0 = 11'b00000000000;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv5_1 = 5'b1;
parameter    ap_const_lv2_1 = 2'b1;
parameter    ap_const_lv8_0 = 8'b00000000;
parameter    ap_const_lv2_2 = 2'b10;
parameter    ap_const_lv11_5 = 11'b101;
parameter    ap_const_lv11_2 = 11'b10;
parameter    ap_const_lv11_7FD = 11'b11111111101;
parameter    ap_const_lv12_3 = 12'b11;
parameter    ap_const_lv11_7FF = 11'b11111111111;
parameter    ap_const_lv11_1 = 11'b1;
parameter    ap_const_lv11_4 = 11'b100;
parameter    ap_const_lv12_FFC = 12'b111111111100;
parameter    ap_const_lv32_B = 32'b1011;
parameter    ap_const_lv12_FFF = 12'b111111111111;
parameter    ap_const_lv12_FFB = 12'b111111111011;
parameter    ap_const_lv12_FFA = 12'b111111111010;
parameter    ap_const_lv32_A = 32'b1010;
parameter    ap_const_lv10_0 = 10'b0000000000;
parameter    ap_const_lv32_E = 32'b1110;
parameter    ap_true = 1'b1;

input   ap_clk;
input   ap_rst;
input   ap_start;
output   ap_done;
input   ap_continue;
output   ap_idle;
output   ap_ready;
input  [11:0] p_src_rows_V_read;
input  [11:0] p_src_cols_V_read;
input  [7:0] p_src_data_stream_0_V_dout;
input   p_src_data_stream_0_V_empty_n;
output   p_src_data_stream_0_V_read;
input  [7:0] p_src_data_stream_1_V_dout;
input   p_src_data_stream_1_V_empty_n;
output   p_src_data_stream_1_V_read;
input  [7:0] p_src_data_stream_2_V_dout;
input   p_src_data_stream_2_V_empty_n;
output   p_src_data_stream_2_V_read;
output  [7:0] p_dst_data_stream_0_V_din;
input   p_dst_data_stream_0_V_full_n;
output   p_dst_data_stream_0_V_write;
output  [7:0] p_dst_data_stream_1_V_din;
input   p_dst_data_stream_1_V_full_n;
output   p_dst_data_stream_1_V_write;
output  [7:0] p_dst_data_stream_2_V_din;
input   p_dst_data_stream_2_V_full_n;
output   p_dst_data_stream_2_V_write;

reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_src_data_stream_0_V_read;
reg p_src_data_stream_1_V_read;
reg p_src_data_stream_2_V_read;
reg p_dst_data_stream_0_V_write;
reg p_dst_data_stream_1_V_write;
reg p_dst_data_stream_2_V_write;
reg    ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm = 8'b1;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_bdd_27;
reg   [10:0] p_025_0_i_i_reg_656;
reg    ap_sig_bdd_67;
wire   [10:0] tmp_fu_884_p1;
reg   [10:0] tmp_reg_2745;
wire   [10:0] tmp_72_fu_888_p1;
reg   [10:0] tmp_72_reg_2751;
wire   [12:0] cols_assign_cast1_fu_892_p1;
reg   [12:0] cols_assign_cast1_reg_2757;
wire   [1:0] tmp_16_fu_896_p2;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_bdd_85;
wire   [1:0] tmp_19_fu_908_p2;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_bdd_94;
wire   [1:0] tmp_22_fu_920_p2;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_bdd_103;
wire   [10:0] heightloop_fu_932_p2;
reg   [10:0] heightloop_reg_3051;
wire   [0:0] tmp_23_fu_926_p2;
wire   [10:0] widthloop_fu_937_p2;
reg   [10:0] widthloop_reg_3056;
wire   [11:0] tmp_28_cast_fu_947_p1;
reg   [11:0] tmp_28_cast_reg_3061;
wire   [11:0] p_neg226_i_i_fu_951_p2;
reg   [11:0] p_neg226_i_i_reg_3068;
wire   [1:0] tmp_73_fu_956_p1;
reg   [1:0] tmp_73_reg_3076;
wire   [10:0] ref_fu_960_p2;
reg   [10:0] ref_reg_3084;
wire   [11:0] ref_cast_fu_965_p1;
reg   [11:0] ref_cast_reg_3089;
wire   [1:0] tmp_74_fu_969_p1;
reg   [1:0] tmp_74_reg_3094;
wire   [11:0] tmp_29_cast_cast3_fu_973_p1;
reg   [11:0] tmp_29_cast_cast3_reg_3099;
reg    ap_sig_cseq_ST_st5_fsm_4;
reg    ap_sig_bdd_133;
wire   [10:0] i_V_fu_982_p2;
reg   [10:0] i_V_reg_3108;
wire   [0:0] tmp_30_fu_988_p2;
reg   [0:0] tmp_30_reg_3113;
wire   [0:0] tmp_28_fu_977_p2;
wire   [11:0] ImagLoc_y_fu_994_p2;
reg   [11:0] ImagLoc_y_reg_3118;
wire   [0:0] or_cond_2_fu_1021_p2;
reg   [0:0] or_cond_2_reg_3126;
reg   [0:0] tmp_77_reg_3131;
wire   [1:0] tmp_32_fu_1035_p3;
reg   [1:0] tmp_32_reg_3135;
wire   [1:0] tmp_78_fu_1049_p1;
reg   [1:0] tmp_78_reg_3149;
wire   [1:0] tmp_79_fu_1053_p1;
reg   [1:0] tmp_79_reg_3155;
wire   [11:0] y_1_2_fu_1062_p2;
reg   [11:0] y_1_2_reg_3162;
reg    ap_sig_cseq_ST_st6_fsm_5;
reg    ap_sig_bdd_162;
wire   [11:0] y_1_2_1_fu_1067_p2;
reg   [11:0] y_1_2_1_reg_3169;
wire   [0:0] brmerge_fu_1072_p2;
reg   [0:0] brmerge_reg_3176;
wire   [0:0] tmp_33_fu_1081_p2;
reg   [0:0] tmp_33_reg_3180;
reg    ap_sig_cseq_ST_pp0_stg0_fsm_6;
reg    ap_sig_bdd_175;
reg    ap_reg_ppiten_pp0_it0 = 1'b0;
reg    ap_reg_ppiten_pp0_it1 = 1'b0;
reg    ap_reg_ppiten_pp0_it2 = 1'b0;
reg    ap_reg_ppiten_pp0_it3 = 1'b0;
reg    ap_reg_ppiten_pp0_it4 = 1'b0;
reg    ap_reg_ppiten_pp0_it5 = 1'b0;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it5;
reg   [0:0] or_cond2_reg_3206;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
reg   [0:0] or_cond2_1_reg_3228;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
reg   [0:0] or_cond2_2_reg_3248;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
reg    ap_sig_bdd_218;
reg    ap_reg_ppiten_pp0_it6 = 1'b0;
reg    ap_reg_ppiten_pp0_it7 = 1'b0;
reg    ap_reg_ppiten_pp0_it8 = 1'b0;
reg    ap_reg_ppiten_pp0_it9 = 1'b0;
reg    ap_reg_ppiten_pp0_it10 = 1'b0;
reg    ap_reg_ppiten_pp0_it11 = 1'b0;
reg   [0:0] or_cond219_i_i_reg_3189;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11;
reg    ap_sig_bdd_244;
reg    ap_reg_ppiten_pp0_it12 = 1'b0;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it6;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it7;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it8;
reg   [0:0] ap_reg_ppstg_tmp_33_reg_3180_pp0_it9;
wire   [10:0] j_V_fu_1086_p2;
wire   [0:0] or_cond219_i_i_fu_1108_p2;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
reg   [0:0] ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
wire   [11:0] ImagLoc_x_fu_1113_p2;
reg   [11:0] ImagLoc_x_reg_3193;
wire   [0:0] tmp_37_fu_1133_p2;
reg   [0:0] tmp_37_reg_3202;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_37_reg_3202_pp0_it6;
wire   [0:0] or_cond2_fu_1138_p2;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond2_reg_3206_pp0_it6;
reg   [0:0] tmp_84_reg_3210;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_84_reg_3210_pp0_it6;
wire   [0:0] tmp_38_fu_1152_p2;
reg   [0:0] tmp_38_reg_3214;
reg   [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_38_reg_3214_pp0_it5;
wire   [1:0] col_assign_fu_1157_p2;
reg   [1:0] col_assign_reg_3218;
reg   [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
reg   [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
reg   [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
reg   [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
reg   [1:0] ap_reg_ppstg_col_assign_reg_3218_pp0_it5;
wire   [0:0] tmp_63_1_fu_1168_p2;
reg   [0:0] tmp_63_1_reg_3224;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6;
wire   [0:0] or_cond2_1_fu_1173_p2;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6;
reg   [0:0] tmp_89_reg_3232;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_89_reg_3232_pp0_it6;
wire   [0:0] tmp_66_1_fu_1187_p2;
reg   [0:0] tmp_66_1_reg_3236;
reg   [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5;
wire   [1:0] tmp_93_fu_1197_p1;
reg   [1:0] tmp_93_reg_3240;
reg   [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it1;
reg   [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it2;
reg   [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it3;
reg   [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it4;
reg   [1:0] ap_reg_ppstg_tmp_93_reg_3240_pp0_it5;
wire   [0:0] tmp_63_2_fu_1207_p2;
reg   [0:0] tmp_63_2_reg_3244;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6;
wire   [0:0] or_cond2_2_fu_1212_p2;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
reg   [0:0] ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6;
reg   [0:0] tmp_98_reg_3252;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it5;
reg   [0:0] ap_reg_ppstg_tmp_98_reg_3252_pp0_it6;
wire   [0:0] tmp_66_2_fu_1226_p2;
reg   [0:0] tmp_66_2_reg_3256;
reg   [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1;
reg   [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2;
reg   [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3;
reg   [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4;
reg   [0:0] ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5;
wire   [1:0] tmp_102_fu_1236_p1;
reg   [1:0] tmp_102_reg_3260;
reg   [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it1;
reg   [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it2;
reg   [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it3;
reg   [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it4;
reg   [1:0] ap_reg_ppstg_tmp_102_reg_3260_pp0_it5;
wire   [1:0] tmp_96_fu_1244_p1;
reg   [1:0] tmp_96_reg_3264;
reg   [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it2;
reg   [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it3;
reg   [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it4;
reg   [1:0] ap_reg_ppstg_tmp_96_reg_3264_pp0_it5;
wire   [1:0] tmp_105_fu_1252_p1;
reg   [1:0] tmp_105_reg_3270;
reg   [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it2;
reg   [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it3;
reg   [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it4;
reg   [1:0] ap_reg_ppstg_tmp_105_reg_3270_pp0_it5;
wire   [1:0] tmp_87_fu_1256_p1;
reg   [1:0] tmp_87_reg_3276;
wire   [1:0] tmp_92_fu_1260_p1;
reg   [1:0] tmp_92_reg_3281;
wire   [1:0] tmp_101_fu_1264_p1;
reg   [1:0] tmp_101_reg_3286;
wire   [14:0] grp_image_filter_borderInterpolate_fu_692_ap_return;
reg   [14:0] x_reg_3291;
wire   [1:0] tmp_83_fu_1268_p1;
reg   [1:0] tmp_83_reg_3296;
reg   [1:0] ap_reg_ppstg_tmp_83_reg_3296_pp0_it5;
wire   [1:0] locy_0_2_t_fu_1272_p2;
reg   [1:0] locy_0_2_t_reg_3301;
reg   [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
reg   [1:0] ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6;
wire   [14:0] grp_image_filter_borderInterpolate_fu_700_ap_return;
reg   [14:0] x_1_reg_3305;
reg   [14:0] ap_reg_ppstg_x_1_reg_3305_pp0_it5;
wire   [1:0] locy_1_2_t_fu_1276_p2;
reg   [1:0] locy_1_2_t_reg_3313;
reg   [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
reg   [1:0] ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6;
wire   [14:0] grp_image_filter_borderInterpolate_fu_708_ap_return;
reg   [14:0] x_2_reg_3317;
reg   [14:0] ap_reg_ppstg_x_2_reg_3317_pp0_it5;
wire   [1:0] locy_2_2_t_fu_1280_p2;
reg   [1:0] locy_2_2_t_reg_3325;
reg   [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
reg   [1:0] ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6;
reg   [10:0] k_buf_0_val_0_addr_reg_3329;
reg   [10:0] k_buf_0_val_1_addr_reg_3335;
reg   [10:0] k_buf_0_val_2_addr_reg_3341;
wire   [7:0] k_buf_0_val_0_q0;
reg   [7:0] right_border_buf_0_val_2_0_reg_3377;
wire   [7:0] k_buf_0_val_1_q0;
reg   [7:0] right_border_buf_0_val_1_0_reg_3382;
wire   [7:0] k_buf_0_val_2_q0;
reg   [7:0] src_kernel_win_0_val_2_0_reg_3390;
wire   [1:0] tmp_85_fu_1311_p1;
reg   [1:0] tmp_85_reg_3397;
wire   [1:0] tmp_86_fu_1315_p1;
reg   [1:0] tmp_86_reg_3403;
wire   [1:0] col_assign_3_fu_1319_p2;
reg   [1:0] col_assign_3_reg_3409;
wire   [7:0] k_buf_1_val_0_q0;
reg   [7:0] right_border_buf_1_val_2_0_reg_3415;
wire   [7:0] k_buf_1_val_1_q0;
reg   [7:0] right_border_buf_1_val_1_0_reg_3420;
wire   [7:0] k_buf_1_val_2_q0;
reg   [7:0] src_kernel_win_1_val_2_0_reg_3428;
wire   [1:0] tmp_90_fu_1423_p1;
reg   [1:0] tmp_90_reg_3435;
wire   [1:0] tmp_91_fu_1427_p1;
reg   [1:0] tmp_91_reg_3441;
wire   [0:0] tmp_94_fu_1440_p3;
reg   [0:0] tmp_94_reg_3447;
wire   [1:0] col_assign_3_1_t1_fu_1450_p2;
reg   [1:0] col_assign_3_1_t1_reg_3453;
wire   [7:0] col_buf_1_val_0_0_16_fu_1475_p3;
reg   [7:0] col_buf_1_val_0_0_16_reg_3457;
wire   [0:0] sel_tmp43_fu_1489_p2;
reg   [0:0] sel_tmp43_reg_3463;
wire   [0:0] sel_tmp44_fu_1495_p2;
reg   [0:0] sel_tmp44_reg_3469;
wire   [7:0] k_buf_2_val_0_q0;
reg   [7:0] right_border_buf_2_val_2_0_reg_3474;
wire   [7:0] k_buf_2_val_1_q0;
reg   [7:0] right_border_buf_2_val_1_0_reg_3479;
wire   [7:0] k_buf_2_val_2_q0;
reg   [7:0] src_kernel_win_2_val_2_0_reg_3487;
wire   [1:0] tmp_99_fu_1609_p1;
reg   [1:0] tmp_99_reg_3494;
wire   [1:0] tmp_100_fu_1613_p1;
reg   [1:0] tmp_100_reg_3500;
wire   [0:0] tmp_103_fu_1626_p3;
reg   [0:0] tmp_103_reg_3506;
wire   [1:0] col_assign_3_2_t1_fu_1636_p2;
reg   [1:0] col_assign_3_2_t1_reg_3512;
wire   [7:0] col_buf_2_val_0_0_16_fu_1661_p3;
reg   [7:0] col_buf_2_val_0_0_16_reg_3516;
wire   [0:0] sel_tmp55_fu_1675_p2;
reg   [0:0] sel_tmp55_reg_3522;
wire   [0:0] sel_tmp56_fu_1681_p2;
reg   [0:0] sel_tmp56_reg_3528;
reg   [7:0] src_kernel_win_0_val_0_1_12_reg_3533;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10;
reg   [7:0] src_kernel_win_0_val_1_1_12_reg_3540;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8;
reg   [7:0] src_kernel_win_1_val_0_1_12_reg_3547;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10;
reg   [7:0] src_kernel_win_1_val_1_1_12_reg_3554;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8;
reg   [7:0] src_kernel_win_2_val_0_1_12_reg_3561;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10;
reg   [7:0] src_kernel_win_2_val_1_1_12_reg_3568;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587;
reg   [7:0] src_kernel_win_0_val_0_1_lo_reg_3593;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11;
reg   [7:0] src_kernel_win_0_val_1_1_lo_reg_3599;
reg   [7:0] ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9;
reg   [7:0] src_kernel_win_0_val_1_2_lo_reg_3605;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610;
wire   [0:0] tmp_115_0_1_fu_2364_p2;
reg   [0:0] tmp_115_0_1_reg_3615;
reg   [7:0] src_kernel_win_1_val_0_1_lo_reg_3620;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11;
reg   [7:0] src_kernel_win_1_val_1_1_lo_reg_3626;
reg   [7:0] ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9;
reg   [7:0] src_kernel_win_1_val_1_2_lo_reg_3632;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637;
wire   [0:0] tmp_115_1_1_fu_2394_p2;
reg   [0:0] tmp_115_1_1_reg_3642;
reg   [7:0] src_kernel_win_2_val_0_1_lo_reg_3647;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11;
reg   [7:0] src_kernel_win_2_val_1_1_lo_reg_3653;
reg   [7:0] ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9;
reg   [7:0] src_kernel_win_2_val_1_2_lo_reg_3659;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664;
wire   [0:0] tmp_115_2_1_fu_2424_p2;
reg   [0:0] tmp_115_2_1_reg_3669;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686;
reg   [7:0] src_kernel_win_0_val_0_2_lo_reg_3692;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697;
wire   [0:0] tmp_115_0_2_fu_2506_p2;
reg   [0:0] tmp_115_0_2_reg_3702;
reg   [7:0] src_kernel_win_1_val_0_2_lo_reg_3707;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712;
wire   [0:0] tmp_115_1_2_fu_2525_p2;
reg   [0:0] tmp_115_1_2_reg_3717;
reg   [7:0] src_kernel_win_2_val_0_2_lo_reg_3722;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727;
wire   [0:0] tmp_115_2_2_fu_2544_p2;
reg   [0:0] tmp_115_2_2_reg_3732;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
reg   [7:0] temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749;
wire   [10:0] k_buf_0_val_0_address0;
reg    k_buf_0_val_0_ce0;
wire   [10:0] k_buf_0_val_0_address1;
reg    k_buf_0_val_0_ce1;
reg    k_buf_0_val_0_we1;
wire   [7:0] k_buf_0_val_0_d1;
wire   [10:0] k_buf_0_val_1_address0;
reg    k_buf_0_val_1_ce0;
wire   [10:0] k_buf_0_val_1_address1;
reg    k_buf_0_val_1_ce1;
reg    k_buf_0_val_1_we1;
wire   [7:0] k_buf_0_val_1_d1;
wire   [10:0] k_buf_0_val_2_address0;
reg    k_buf_0_val_2_ce0;
wire   [10:0] k_buf_0_val_2_address1;
reg    k_buf_0_val_2_ce1;
reg    k_buf_0_val_2_we1;
wire   [7:0] k_buf_0_val_2_d1;
wire   [10:0] k_buf_1_val_0_address0;
reg    k_buf_1_val_0_ce0;
wire   [10:0] k_buf_1_val_0_address1;
reg    k_buf_1_val_0_ce1;
reg    k_buf_1_val_0_we1;
wire   [7:0] k_buf_1_val_0_d1;
wire   [10:0] k_buf_1_val_1_address0;
reg    k_buf_1_val_1_ce0;
reg   [10:0] k_buf_1_val_1_address1;
reg    k_buf_1_val_1_ce1;
reg    k_buf_1_val_1_we1;
wire   [7:0] k_buf_1_val_1_d1;
wire   [10:0] k_buf_1_val_2_address0;
reg    k_buf_1_val_2_ce0;
wire   [10:0] k_buf_1_val_2_address1;
reg    k_buf_1_val_2_ce1;
reg    k_buf_1_val_2_we1;
wire   [7:0] k_buf_1_val_2_d1;
wire   [10:0] k_buf_2_val_0_address0;
reg    k_buf_2_val_0_ce0;
wire   [10:0] k_buf_2_val_0_address1;
reg    k_buf_2_val_0_ce1;
reg    k_buf_2_val_0_we1;
wire   [7:0] k_buf_2_val_0_d1;
wire   [10:0] k_buf_2_val_1_address0;
reg    k_buf_2_val_1_ce0;
reg   [10:0] k_buf_2_val_1_address1;
reg    k_buf_2_val_1_ce1;
reg    k_buf_2_val_1_we1;
wire   [7:0] k_buf_2_val_1_d1;
wire   [10:0] k_buf_2_val_2_address0;
reg    k_buf_2_val_2_ce0;
wire   [10:0] k_buf_2_val_2_address1;
reg    k_buf_2_val_2_ce1;
reg    k_buf_2_val_2_we1;
wire   [7:0] k_buf_2_val_2_d1;
wire   [11:0] grp_image_filter_borderInterpolate_fu_668_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_668_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_668_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_668_ap_return;
reg    grp_image_filter_borderInterpolate_fu_668_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_676_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_676_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_676_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_676_ap_return;
reg    grp_image_filter_borderInterpolate_fu_676_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_684_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_684_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_684_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_684_ap_return;
reg    grp_image_filter_borderInterpolate_fu_684_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_692_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_692_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_692_borderType;
reg    grp_image_filter_borderInterpolate_fu_692_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_700_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_700_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_700_borderType;
reg    grp_image_filter_borderInterpolate_fu_700_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_708_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_708_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_708_borderType;
reg    grp_image_filter_borderInterpolate_fu_708_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_716_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_716_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_716_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_716_ap_return;
reg    grp_image_filter_borderInterpolate_fu_716_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_724_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_724_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_724_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_724_ap_return;
reg    grp_image_filter_borderInterpolate_fu_724_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_732_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_732_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_732_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_732_ap_return;
reg    grp_image_filter_borderInterpolate_fu_732_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_740_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_740_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_740_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_740_ap_return;
reg    grp_image_filter_borderInterpolate_fu_740_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_748_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_748_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_748_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_748_ap_return;
reg    grp_image_filter_borderInterpolate_fu_748_ap_ce;
wire   [11:0] grp_image_filter_borderInterpolate_fu_756_p;
wire   [11:0] grp_image_filter_borderInterpolate_fu_756_len;
wire   [4:0] grp_image_filter_borderInterpolate_fu_756_borderType;
wire   [14:0] grp_image_filter_borderInterpolate_fu_756_ap_return;
reg    grp_image_filter_borderInterpolate_fu_756_ap_ce;
reg   [1:0] tmp_15_reg_612;
wire   [0:0] tmp_s_fu_902_p2;
reg   [1:0] tmp_18_reg_623;
wire   [0:0] tmp_20_fu_914_p2;
reg   [1:0] tmp_21_reg_634;
reg   [10:0] p_012_0_i_i_reg_645;
reg    ap_sig_cseq_ST_st20_fsm_7;
reg    ap_sig_bdd_951;
wire   [63:0] tmp_35_fu_1287_p1;
wire  signed [63:0] tmp_56_1_fu_1294_p1;
wire  signed [63:0] tmp_56_2_fu_1300_p1;
wire   [63:0] tmp_99_1_fu_1516_p1;
wire   [10:0] k_buf_1_val_1_addr_1_gep_fu_554_p3;
wire   [63:0] tmp_99_2_fu_1702_p1;
wire   [10:0] k_buf_2_val_1_addr_1_gep_fu_594_p3;
reg   [7:0] right_border_buf_0_val_0_0_fu_178;
reg   [7:0] right_border_buf_0_val_0_1_fu_182;
reg   [7:0] right_border_buf_0_val_0_2_fu_186;
reg   [7:0] right_border_buf_1_val_0_0_fu_190;
reg   [7:0] right_border_buf_1_val_0_1_fu_194;
reg   [7:0] right_border_buf_1_val_0_2_fu_198;
reg   [7:0] right_border_buf_2_val_0_0_fu_202;
reg   [7:0] right_border_buf_2_val_0_1_fu_206;
reg   [7:0] right_border_buf_2_val_0_2_fu_210;
reg   [7:0] col_buf_0_val_0_0_fu_214;
reg   [7:0] col_buf_1_val_0_0_fu_218;
reg   [7:0] col_buf_2_val_0_0_fu_222;
reg   [7:0] src_kernel_win_0_val_0_1_fu_226;
wire   [7:0] src_kernel_win_0_val_0_1_9_fu_1838_p3;
wire   [7:0] col_buf_0_val_0_0_16_fu_1926_p3;
reg   [7:0] src_kernel_win_0_val_0_2_fu_230;
reg   [7:0] col_buf_2_val_0_0_11_fu_234;
reg   [7:0] src_kernel_win_0_val_2_1_fu_238;
reg   [7:0] src_kernel_win_0_val_1_1_fu_242;
wire   [7:0] src_kernel_win_0_val_1_1_9_fu_1870_p3;
wire   [7:0] right_border_buf_0_val_1_2_20_fu_1943_p3;
reg   [7:0] src_kernel_win_0_val_1_2_fu_246;
reg   [7:0] col_buf_2_val_0_0_12_fu_250;
reg   [7:0] src_kernel_win_0_val_2_2_fu_254;
reg   [7:0] col_buf_2_val_0_0_13_fu_258;
reg   [7:0] src_kernel_win_1_val_0_1_fu_262;
wire   [7:0] src_kernel_win_1_val_0_1_9_fu_2017_p3;
wire   [7:0] src_kernel_win_1_val_0_1_10_fu_2084_p3;
reg   [7:0] src_kernel_win_1_val_0_2_fu_266;
reg   [7:0] right_border_buf_2_val_1_2_12_fu_270;
wire   [7:0] right_border_buf_2_val_1_2_27_fu_1763_p3;
reg   [7:0] src_kernel_win_1_val_2_1_fu_274;
reg   [7:0] src_kernel_win_1_val_1_1_fu_278;
wire   [7:0] src_kernel_win_1_val_1_1_9_fu_2049_p3;
wire   [7:0] src_kernel_win_1_val_1_1_10_fu_2105_p3;
reg   [7:0] src_kernel_win_1_val_1_2_fu_282;
reg   [7:0] right_border_buf_2_val_1_2_19_fu_286;
wire   [7:0] right_border_buf_2_val_1_2_25_fu_1746_p3;
reg   [7:0] src_kernel_win_1_val_2_2_fu_290;
reg   [7:0] right_border_buf_2_val_1_2_20_fu_294;
wire   [7:0] right_border_buf_2_val_1_2_23_fu_1724_p3;
reg   [7:0] src_kernel_win_2_val_0_1_fu_298;
wire   [7:0] src_kernel_win_2_val_0_1_9_fu_2183_p3;
wire   [7:0] src_kernel_win_2_val_0_1_10_fu_2250_p3;
reg   [7:0] src_kernel_win_2_val_0_2_fu_302;
reg   [7:0] col_buf_1_val_0_0_11_fu_306;
reg   [7:0] src_kernel_win_2_val_2_1_fu_310;
reg   [7:0] src_kernel_win_2_val_1_1_fu_314;
wire   [7:0] src_kernel_win_2_val_1_1_9_fu_2215_p3;
wire   [7:0] src_kernel_win_2_val_1_1_10_fu_2271_p3;
reg   [7:0] src_kernel_win_2_val_1_2_fu_318;
reg   [7:0] col_buf_1_val_0_0_12_fu_322;
reg   [7:0] src_kernel_win_2_val_2_2_fu_326;
reg   [7:0] col_buf_1_val_0_0_13_fu_330;
reg   [7:0] right_border_buf_0_val_1_2_14_fu_334;
wire   [7:0] right_border_buf_0_val_1_2_19_fu_1391_p3;
reg   [7:0] right_border_buf_0_val_1_2_15_fu_338;
wire   [7:0] right_border_buf_0_val_1_2_5_fu_1382_p3;
reg   [7:0] right_border_buf_0_val_1_2_16_fu_342;
wire   [7:0] right_border_buf_0_val_1_2_3_fu_1365_p3;
reg   [7:0] col_buf_0_val_0_0_11_fu_346;
reg   [7:0] col_buf_0_val_0_0_12_fu_350;
reg   [7:0] col_buf_0_val_0_0_13_fu_354;
reg   [7:0] right_border_buf_1_val_1_2_12_fu_358;
wire   [7:0] right_border_buf_1_val_1_2_19_fu_1577_p3;
reg   [7:0] right_border_buf_1_val_1_2_15_fu_362;
wire   [7:0] right_border_buf_1_val_1_2_6_74_fu_1568_p3;
reg   [7:0] right_border_buf_1_val_1_2_16_fu_366;
wire   [7:0] right_border_buf_1_val_1_2_4_fu_1551_p3;
wire   [10:0] tmp_27_fu_942_p2;
wire   [10:0] tmp_75_fu_1000_p4;
wire   [0:0] icmp_fu_1010_p2;
wire   [0:0] tmp_58_2_fu_1016_p2;
wire   [10:0] p_i_i_fu_1042_p3;
wire   [0:0] tmp_31_fu_1057_p2;
wire   [9:0] tmp_80_fu_1092_p4;
wire   [0:0] icmp2_fu_1102_p2;
wire   [11:0] tmp_33_cast_fu_1077_p1;
wire  signed [12:0] ImagLoc_x_cast2_fu_1123_p1;
wire   [0:0] tmp_36_fu_1127_p2;
wire   [1:0] tmp_82_fu_1119_p1;
wire   [0:0] tmp_61_1_fu_1162_p2;
wire   [11:0] col_assign_1_fu_1192_p2;
wire   [0:0] tmp_61_2_fu_1201_p2;
wire   [11:0] col_assign_s_fu_1231_p2;
wire   [11:0] col_assign_4_1_fu_1240_p2;
wire   [11:0] col_assign_4_2_fu_1248_p2;
wire  signed [31:0] x_ext_fu_1284_p1;
wire   [0:0] sel_tmp24_fu_1347_p2;
wire   [0:0] sel_tmp26_fu_1360_p2;
wire   [7:0] right_border_buf_0_val_1_2_2_fu_1352_p3;
wire   [7:0] right_border_buf_0_val_1_2_4_fu_1374_p3;
wire   [1:0] tmp_95_fu_1447_p1;
wire   [0:0] sel_tmp39_fu_1455_p2;
wire   [0:0] sel_tmp40_fu_1469_p2;
wire   [7:0] col_buf_1_val_0_0_6_fu_1461_p3;
wire   [0:0] sel_tmp42_fu_1483_p2;
wire  signed [31:0] x_1_ext_fu_1415_p1;
wire   [0:0] sel_tmp36_fu_1533_p2;
wire   [0:0] sel_tmp38_fu_1546_p2;
wire   [7:0] right_border_buf_1_val_1_2_3_fu_1538_p3;
wire   [7:0] right_border_buf_1_val_1_2_5_fu_1560_p3;
wire   [1:0] tmp_104_fu_1633_p1;
wire   [0:0] sel_tmp51_fu_1641_p2;
wire   [0:0] sel_tmp52_fu_1655_p2;
wire   [7:0] col_buf_2_val_0_0_6_fu_1647_p3;
wire   [0:0] sel_tmp54_fu_1669_p2;
wire  signed [31:0] x_2_ext_fu_1601_p1;
wire   [0:0] sel_tmp57_fu_1719_p2;
wire   [0:0] sel_tmp58_fu_1733_p2;
wire   [7:0] right_border_buf_2_val_1_2_24_fu_1738_p3;
wire   [7:0] right_border_buf_2_val_1_2_26_fu_1755_p3;
wire   [0:0] sel_tmp8_fu_1821_p2;
wire   [1:0] locy_fu_1814_p2;
wire   [0:0] sel_tmp10_fu_1832_p2;
wire   [7:0] sel_tmp9_fu_1825_p3;
wire   [0:0] sel_tmp12_fu_1853_p2;
wire   [1:0] locy_0_1_t_fu_1846_p2;
wire   [0:0] sel_tmp14_fu_1864_p2;
wire   [7:0] sel_tmp13_fu_1857_p3;
wire   [0:0] sel_tmp_fu_1908_p2;
wire   [0:0] sel_tmp2_fu_1921_p2;
wire   [7:0] col_buf_0_val_0_0_6_fu_1913_p3;
wire   [7:0] right_border_buf_0_val_1_2_fu_1935_p3;
wire   [0:0] tmp_115_0_0_1_fu_1979_p2;
wire   [0:0] sel_tmp16_fu_2000_p2;
wire   [1:0] locy_1_0_t_fu_1993_p2;
wire   [0:0] sel_tmp18_fu_2011_p2;
wire   [7:0] sel_tmp17_fu_2004_p3;
wire   [0:0] sel_tmp20_fu_2032_p2;
wire   [1:0] locy_1_1_t_fu_2025_p2;
wire   [0:0] sel_tmp22_fu_2043_p2;
wire   [7:0] sel_tmp21_fu_2036_p3;
wire   [7:0] sel_tmp41_fu_2078_p3;
wire   [7:0] right_border_buf_1_val_1_2_fu_2091_p3;
wire   [7:0] right_border_buf_1_val_1_2_1_fu_2098_p3;
wire   [0:0] tmp_115_1_0_1_fu_2145_p2;
wire   [0:0] sel_tmp45_fu_2166_p2;
wire   [1:0] locy_2_0_t_fu_2159_p2;
wire   [0:0] sel_tmp47_fu_2177_p2;
wire   [7:0] sel_tmp46_fu_2170_p3;
wire   [0:0] sel_tmp48_fu_2198_p2;
wire   [1:0] locy_2_1_t_fu_2191_p2;
wire   [0:0] sel_tmp50_fu_2209_p2;
wire   [7:0] sel_tmp49_fu_2202_p3;
wire   [7:0] sel_tmp53_fu_2244_p3;
wire   [7:0] right_border_buf_2_val_1_2_fu_2257_p3;
wire   [7:0] right_border_buf_2_val_1_2_1_fu_2264_p3;
wire   [0:0] tmp_115_2_0_1_fu_2311_p2;
wire   [0:0] tmp_115_0_0_2_fu_2352_p2;
wire   [0:0] tmp_115_1_0_2_fu_2382_p2;
wire   [0:0] tmp_115_2_0_2_fu_2412_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3;
wire   [0:0] tmp_115_0_1_1_fu_2447_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3;
wire   [0:0] tmp_115_1_1_1_fu_2464_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3;
wire   [0:0] tmp_115_2_1_1_fu_2481_p2;
wire   [0:0] tmp_115_0_1_2_fu_2496_p2;
wire   [0:0] tmp_115_1_1_2_fu_2515_p2;
wire   [0:0] tmp_115_2_1_2_fu_2534_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3;
wire   [0:0] tmp_115_0_2_1_fu_2567_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3;
wire   [0:0] tmp_115_1_2_1_fu_2584_p2;
wire   [7:0] temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3;
wire   [0:0] tmp_115_2_2_1_fu_2601_p2;
wire   [0:0] tmp_115_0_2_2_fu_2613_p2;
wire   [0:0] tmp_115_1_2_2_fu_2624_p2;
wire   [0:0] tmp_115_2_2_2_fu_2635_p2;
reg   [7:0] ap_NS_fsm;
reg    ap_sig_bdd_967;
reg    ap_sig_bdd_979;


image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_0_val_0_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_0_val_0_address0 ),
    .ce0( k_buf_0_val_0_ce0 ),
    .q0( k_buf_0_val_0_q0 ),
    .address1( k_buf_0_val_0_address1 ),
    .ce1( k_buf_0_val_0_ce1 ),
    .we1( k_buf_0_val_0_we1 ),
    .d1( k_buf_0_val_0_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_0_val_1_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_0_val_1_address0 ),
    .ce0( k_buf_0_val_1_ce0 ),
    .q0( k_buf_0_val_1_q0 ),
    .address1( k_buf_0_val_1_address1 ),
    .ce1( k_buf_0_val_1_ce1 ),
    .we1( k_buf_0_val_1_we1 ),
    .d1( k_buf_0_val_1_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_0_val_2_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_0_val_2_address0 ),
    .ce0( k_buf_0_val_2_ce0 ),
    .q0( k_buf_0_val_2_q0 ),
    .address1( k_buf_0_val_2_address1 ),
    .ce1( k_buf_0_val_2_ce1 ),
    .we1( k_buf_0_val_2_we1 ),
    .d1( k_buf_0_val_2_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_1_val_0_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_1_val_0_address0 ),
    .ce0( k_buf_1_val_0_ce0 ),
    .q0( k_buf_1_val_0_q0 ),
    .address1( k_buf_1_val_0_address1 ),
    .ce1( k_buf_1_val_0_ce1 ),
    .we1( k_buf_1_val_0_we1 ),
    .d1( k_buf_1_val_0_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_1_val_1_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_1_val_1_address0 ),
    .ce0( k_buf_1_val_1_ce0 ),
    .q0( k_buf_1_val_1_q0 ),
    .address1( k_buf_1_val_1_address1 ),
    .ce1( k_buf_1_val_1_ce1 ),
    .we1( k_buf_1_val_1_we1 ),
    .d1( k_buf_1_val_1_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_1_val_2_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_1_val_2_address0 ),
    .ce0( k_buf_1_val_2_ce0 ),
    .q0( k_buf_1_val_2_q0 ),
    .address1( k_buf_1_val_2_address1 ),
    .ce1( k_buf_1_val_2_ce1 ),
    .we1( k_buf_1_val_2_we1 ),
    .d1( k_buf_1_val_2_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_2_val_0_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_2_val_0_address0 ),
    .ce0( k_buf_2_val_0_ce0 ),
    .q0( k_buf_2_val_0_q0 ),
    .address1( k_buf_2_val_0_address1 ),
    .ce1( k_buf_2_val_0_ce1 ),
    .we1( k_buf_2_val_0_we1 ),
    .d1( k_buf_2_val_0_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_2_val_1_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_2_val_1_address0 ),
    .ce0( k_buf_2_val_1_ce0 ),
    .q0( k_buf_2_val_1_q0 ),
    .address1( k_buf_2_val_1_address1 ),
    .ce1( k_buf_2_val_1_ce1 ),
    .we1( k_buf_2_val_1_we1 ),
    .d1( k_buf_2_val_1_d1 )
);

image_filter_Filter2D_k_buf_0_val_0 #(
    .DataWidth( 8 ),
    .AddressRange( 1920 ),
    .AddressWidth( 11 ))
k_buf_2_val_2_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .address0( k_buf_2_val_2_address0 ),
    .ce0( k_buf_2_val_2_ce0 ),
    .q0( k_buf_2_val_2_q0 ),
    .address1( k_buf_2_val_2_address1 ),
    .ce1( k_buf_2_val_2_ce1 ),
    .we1( k_buf_2_val_2_we1 ),
    .d1( k_buf_2_val_2_d1 )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_668(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_668_p ),
    .len( grp_image_filter_borderInterpolate_fu_668_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_668_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_668_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_668_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_676(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_676_p ),
    .len( grp_image_filter_borderInterpolate_fu_676_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_676_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_676_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_676_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_684(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_684_p ),
    .len( grp_image_filter_borderInterpolate_fu_684_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_684_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_684_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_684_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_692(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_692_p ),
    .len( grp_image_filter_borderInterpolate_fu_692_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_692_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_692_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_692_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_700(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_700_p ),
    .len( grp_image_filter_borderInterpolate_fu_700_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_700_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_700_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_700_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_708(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_708_p ),
    .len( grp_image_filter_borderInterpolate_fu_708_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_708_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_708_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_708_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_716(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_716_p ),
    .len( grp_image_filter_borderInterpolate_fu_716_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_716_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_716_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_716_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_724(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_724_p ),
    .len( grp_image_filter_borderInterpolate_fu_724_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_724_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_724_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_724_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_732(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_732_p ),
    .len( grp_image_filter_borderInterpolate_fu_732_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_732_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_732_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_732_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_740(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_740_p ),
    .len( grp_image_filter_borderInterpolate_fu_740_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_740_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_740_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_740_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_748(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_748_p ),
    .len( grp_image_filter_borderInterpolate_fu_748_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_748_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_748_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_748_ap_ce )
);

image_filter_borderInterpolate grp_image_filter_borderInterpolate_fu_756(
    .ap_clk( ap_clk ),
    .ap_rst( ap_rst ),
    .p( grp_image_filter_borderInterpolate_fu_756_p ),
    .len( grp_image_filter_borderInterpolate_fu_756_len ),
    .borderType( grp_image_filter_borderInterpolate_fu_756_borderType ),
    .ap_return( grp_image_filter_borderInterpolate_fu_756_ap_return ),
    .ap_ce( grp_image_filter_borderInterpolate_fu_756_ap_ce )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
    if (ap_rst == 1'b1) begin
        ap_done_reg <= ap_const_logic_0;
    end else begin
        if ((ap_const_logic_1 == ap_continue)) begin
            ap_done_reg <= ap_const_logic_0;
        end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
            ap_done_reg <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
            ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
        end
    end
end

/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
    end else begin
        if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
            ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
            ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
        end
    end
end

/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
        end
    end
end

/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
        end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
            ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
        end
    end
end

/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
        end
    end
end

/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
        end
    end
end

/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
        end
    end
end

/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
        end
    end
end

/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
        end
    end
end

/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
        end
    end
end

/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            if (~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
                ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
            end else if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) begin
                ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
            end
        end
    end
end

/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
    if (ap_rst == 1'b1) begin
        ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
    end else begin
        if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
            ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
        end
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_7)) begin
        p_012_0_i_i_reg_645 <= i_V_reg_3108;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
        p_012_0_i_i_reg_645 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
        p_025_0_i_i_reg_656 <= j_V_fu_1086_p2;
    end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        p_025_0_i_i_reg_656 <= ap_const_lv11_0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
        src_kernel_win_0_val_0_1_fu_226 <= right_border_buf_0_val_2_0_reg_3377;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0)))) begin
        src_kernel_win_0_val_0_1_fu_226 <= col_buf_0_val_0_0_16_fu_1926_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_0_val_0_1_fu_226 <= src_kernel_win_0_val_0_1_9_fu_1838_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
        src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_0_reg_3382;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0)))) begin
        src_kernel_win_0_val_1_1_fu_242 <= right_border_buf_0_val_1_2_20_fu_1943_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_0_val_1_1_fu_242 <= src_kernel_win_0_val_1_1_9_fu_1870_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & ~(col_assign_3_reg_3409 == ap_const_lv2_1) & ~(col_assign_3_reg_3409 == ap_const_lv2_0))) begin
        src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_2_fu_186;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_0))) begin
        src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_0_fu_178;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it6) & (col_assign_3_reg_3409 == ap_const_lv2_1))) begin
        src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_0_1_fu_182;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it6)))) begin
        src_kernel_win_0_val_2_1_fu_238 <= src_kernel_win_0_val_2_0_reg_3390;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_0))) begin
        src_kernel_win_0_val_2_1_fu_238 <= col_buf_0_val_0_0_fu_214;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 == ap_const_lv2_1))) begin
        src_kernel_win_0_val_2_1_fu_238 <= right_border_buf_0_val_1_0_reg_3382;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
        src_kernel_win_1_val_0_1_fu_262 <= right_border_buf_1_val_2_0_reg_3415;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447)))) begin
        src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_10_fu_2084_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_1_val_0_1_fu_262 <= src_kernel_win_1_val_0_1_9_fu_2017_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
        src_kernel_win_1_val_1_1_fu_278 <= right_border_buf_1_val_1_0_reg_3420;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447)))) begin
        src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_10_fu_2105_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_1_val_1_1_fu_278 <= src_kernel_win_1_val_1_1_9_fu_2049_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & ~(ap_const_lv1_0 == tmp_94_reg_3447))) begin
        src_kernel_win_1_val_2_1_fu_274 <= ap_const_lv8_0;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_1) & ~(col_assign_3_1_t1_reg_3453 == ap_const_lv2_0))) begin
        src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_2_fu_198;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_0))) begin
        src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_0_fu_190;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6) & (ap_const_lv1_0 == tmp_94_reg_3447) & (col_assign_3_1_t1_reg_3453 == ap_const_lv2_1))) begin
        src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_0_1_fu_194;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6)))) begin
        src_kernel_win_1_val_2_1_fu_274 <= src_kernel_win_1_val_2_0_reg_3428;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_0))) begin
        src_kernel_win_1_val_2_1_fu_274 <= col_buf_1_val_0_0_fu_218;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 == ap_const_lv2_1))) begin
        src_kernel_win_1_val_2_1_fu_274 <= right_border_buf_1_val_1_0_reg_3420;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
        src_kernel_win_2_val_0_1_fu_298 <= right_border_buf_2_val_2_0_reg_3474;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506)))) begin
        src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_10_fu_2250_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_2_val_0_1_fu_298 <= src_kernel_win_2_val_0_1_9_fu_2183_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
        src_kernel_win_2_val_1_1_fu_314 <= right_border_buf_2_val_1_0_reg_3479;
    end else if (((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506)))) begin
        src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_10_fu_2271_p3;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)))) begin
        src_kernel_win_2_val_1_1_fu_314 <= src_kernel_win_2_val_1_1_9_fu_2215_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & ~(ap_const_lv1_0 == tmp_103_reg_3506))) begin
        src_kernel_win_2_val_2_1_fu_310 <= ap_const_lv8_0;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_1) & ~(col_assign_3_2_t1_reg_3512 == ap_const_lv2_0))) begin
        src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_2_fu_210;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_0))) begin
        src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_0_fu_202;
    end else if ((~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6) & (ap_const_lv1_0 == tmp_103_reg_3506) & (col_assign_3_2_t1_reg_3512 == ap_const_lv2_1))) begin
        src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_0_1_fu_206;
    end else if ((((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1) & ~(ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it6)) | (~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6)))) begin
        src_kernel_win_2_val_2_1_fu_310 <= src_kernel_win_2_val_2_0_reg_3487;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_0))) begin
        src_kernel_win_2_val_2_1_fu_310 <= col_buf_2_val_0_0_fu_222;
    end else if (((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & (ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 == ap_const_lv2_1))) begin
        src_kernel_win_2_val_2_1_fu_310 <= right_border_buf_2_val_1_0_reg_3479;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
        tmp_15_reg_612 <= ap_const_lv2_0;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == tmp_s_fu_902_p2))) begin
        tmp_15_reg_612 <= tmp_16_fu_896_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_s_fu_902_p2))) begin
        tmp_18_reg_623 <= ap_const_lv2_0;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_20_fu_914_p2))) begin
        tmp_18_reg_623 <= tmp_19_fu_908_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_20_fu_914_p2))) begin
        tmp_21_reg_634 <= ap_const_lv2_0;
    end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
        tmp_21_reg_634 <= tmp_22_fu_920_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
        ImagLoc_x_reg_3193 <= ImagLoc_x_fu_1113_p2;
        or_cond219_i_i_reg_3189 <= or_cond219_i_i_fu_1108_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
        ImagLoc_y_reg_3118 <= ImagLoc_y_fu_994_p2;
        or_cond_2_reg_3126 <= or_cond_2_fu_1021_p2;
        tmp_30_reg_3113 <= tmp_30_fu_988_p2;
        tmp_32_reg_3135 <= tmp_32_fu_1035_p3;
        tmp_77_reg_3131 <= ImagLoc_y_fu_994_p2[ap_const_lv32_B];
        tmp_78_reg_3149 <= tmp_78_fu_1049_p1;
        tmp_79_reg_3155 <= tmp_79_fu_1053_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        ap_reg_ppstg_col_assign_reg_3218_pp0_it1 <= col_assign_reg_3218;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1 <= or_cond219_i_i_reg_3189;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1 <= or_cond2_1_reg_3228;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1 <= or_cond2_2_reg_3248;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it1 <= or_cond2_reg_3206;
        ap_reg_ppstg_tmp_102_reg_3260_pp0_it1 <= tmp_102_reg_3260;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 <= tmp_33_reg_3180;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it1 <= tmp_37_reg_3202;
        ap_reg_ppstg_tmp_38_reg_3214_pp0_it1 <= tmp_38_reg_3214;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1 <= tmp_63_1_reg_3224;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1 <= tmp_63_2_reg_3244;
        ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1 <= tmp_66_1_reg_3236;
        ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1 <= tmp_66_2_reg_3256;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it1 <= tmp_84_reg_3210;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it1 <= tmp_89_reg_3232;
        ap_reg_ppstg_tmp_93_reg_3240_pp0_it1 <= tmp_93_reg_3240;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it1 <= tmp_98_reg_3252;
        tmp_33_reg_3180 <= tmp_33_fu_1081_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12)))) begin
        ap_reg_ppstg_col_assign_reg_3218_pp0_it2 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it1;
        ap_reg_ppstg_col_assign_reg_3218_pp0_it3 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it2;
        ap_reg_ppstg_col_assign_reg_3218_pp0_it4 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it3;
        ap_reg_ppstg_col_assign_reg_3218_pp0_it5 <= ap_reg_ppstg_col_assign_reg_3218_pp0_it4;
        ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5 <= locy_0_2_t_reg_3301;
        ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it6 <= ap_reg_ppstg_locy_0_2_t_reg_3301_pp0_it5;
        ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5 <= locy_1_2_t_reg_3313;
        ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it6 <= ap_reg_ppstg_locy_1_2_t_reg_3313_pp0_it5;
        ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5 <= locy_2_2_t_reg_3325;
        ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it6 <= ap_reg_ppstg_locy_2_2_t_reg_3325_pp0_it5;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it1;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it2;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it3;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it4;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it5;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7;
        ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9 <= ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it1;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it2;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it3;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it4;
        ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it6 <= ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it1;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it2;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it3;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it4;
        ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it6 <= ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it1;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it3 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it2;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it4 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it3;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it4;
        ap_reg_ppstg_or_cond2_reg_3206_pp0_it6 <= ap_reg_ppstg_or_cond2_reg_3206_pp0_it5;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8 <= src_kernel_win_0_val_0_1_12_reg_3533;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it8;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it10;
        ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it9 <= src_kernel_win_0_val_0_1_lo_reg_3593;
        ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8 <= src_kernel_win_0_val_1_1_12_reg_3540;
        ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 <= src_kernel_win_0_val_1_1_lo_reg_3599;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8 <= src_kernel_win_1_val_0_1_12_reg_3547;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it8;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it10;
        ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it9 <= src_kernel_win_1_val_0_1_lo_reg_3620;
        ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8 <= src_kernel_win_1_val_1_1_12_reg_3554;
        ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 <= src_kernel_win_1_val_1_1_lo_reg_3626;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8 <= src_kernel_win_2_val_0_1_12_reg_3561;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it8;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it10;
        ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it9 <= src_kernel_win_2_val_0_1_lo_reg_3647;
        ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8 <= src_kernel_win_2_val_1_1_12_reg_3568;
        ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 <= src_kernel_win_2_val_1_1_lo_reg_3653;
        ap_reg_ppstg_tmp_102_reg_3260_pp0_it2 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it1;
        ap_reg_ppstg_tmp_102_reg_3260_pp0_it3 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it2;
        ap_reg_ppstg_tmp_102_reg_3260_pp0_it4 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it3;
        ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 <= ap_reg_ppstg_tmp_102_reg_3260_pp0_it4;
        ap_reg_ppstg_tmp_105_reg_3270_pp0_it2 <= tmp_105_reg_3270;
        ap_reg_ppstg_tmp_105_reg_3270_pp0_it3 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it2;
        ap_reg_ppstg_tmp_105_reg_3270_pp0_it4 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it3;
        ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 <= ap_reg_ppstg_tmp_105_reg_3270_pp0_it4;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it1;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it2;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it4 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it3;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it4;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it6 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it5;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it7 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it6;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it8 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it7;
        ap_reg_ppstg_tmp_33_reg_3180_pp0_it9 <= ap_reg_ppstg_tmp_33_reg_3180_pp0_it8;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it2 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it1;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it3 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it2;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it4 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it3;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it5 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it4;
        ap_reg_ppstg_tmp_37_reg_3202_pp0_it6 <= ap_reg_ppstg_tmp_37_reg_3202_pp0_it5;
        ap_reg_ppstg_tmp_38_reg_3214_pp0_it2 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it1;
        ap_reg_ppstg_tmp_38_reg_3214_pp0_it3 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it2;
        ap_reg_ppstg_tmp_38_reg_3214_pp0_it4 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it3;
        ap_reg_ppstg_tmp_38_reg_3214_pp0_it5 <= ap_reg_ppstg_tmp_38_reg_3214_pp0_it4;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it1;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it2;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it3;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it4;
        ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it6 <= ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it1;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it2;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it3;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it4;
        ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it6 <= ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5;
        ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it1;
        ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it2;
        ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it3;
        ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5 <= ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it4;
        ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it1;
        ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it2;
        ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it3;
        ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5 <= ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it4;
        ap_reg_ppstg_tmp_83_reg_3296_pp0_it5 <= tmp_83_reg_3296;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it2 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it1;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it3 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it2;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it4 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it3;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it5 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it4;
        ap_reg_ppstg_tmp_84_reg_3210_pp0_it6 <= ap_reg_ppstg_tmp_84_reg_3210_pp0_it5;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it2 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it1;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it3 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it2;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it4 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it3;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it5 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it4;
        ap_reg_ppstg_tmp_89_reg_3232_pp0_it6 <= ap_reg_ppstg_tmp_89_reg_3232_pp0_it5;
        ap_reg_ppstg_tmp_93_reg_3240_pp0_it2 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it1;
        ap_reg_ppstg_tmp_93_reg_3240_pp0_it3 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it2;
        ap_reg_ppstg_tmp_93_reg_3240_pp0_it4 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it3;
        ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 <= ap_reg_ppstg_tmp_93_reg_3240_pp0_it4;
        ap_reg_ppstg_tmp_96_reg_3264_pp0_it2 <= tmp_96_reg_3264;
        ap_reg_ppstg_tmp_96_reg_3264_pp0_it3 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it2;
        ap_reg_ppstg_tmp_96_reg_3264_pp0_it4 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it3;
        ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 <= ap_reg_ppstg_tmp_96_reg_3264_pp0_it4;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it2 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it1;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it3 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it2;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it4 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it3;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it5 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it4;
        ap_reg_ppstg_tmp_98_reg_3252_pp0_it6 <= ap_reg_ppstg_tmp_98_reg_3252_pp0_it5;
        ap_reg_ppstg_x_1_reg_3305_pp0_it5 <= x_1_reg_3305;
        ap_reg_ppstg_x_2_reg_3317_pp0_it5 <= x_2_reg_3317;
        src_kernel_win_0_val_0_1_12_reg_3533 <= src_kernel_win_0_val_0_1_fu_226;
        src_kernel_win_0_val_1_1_12_reg_3540 <= src_kernel_win_0_val_1_1_fu_242;
        src_kernel_win_1_val_0_1_12_reg_3547 <= src_kernel_win_1_val_0_1_fu_262;
        src_kernel_win_1_val_1_1_12_reg_3554 <= src_kernel_win_1_val_1_1_fu_278;
        src_kernel_win_2_val_0_1_12_reg_3561 <= src_kernel_win_2_val_0_1_fu_298;
        src_kernel_win_2_val_1_1_12_reg_3568 <= src_kernel_win_2_val_1_1_fu_314;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
        brmerge_reg_3176 <= brmerge_fu_1072_p2;
        y_1_2_1_reg_3169 <= y_1_2_1_fu_1067_p2;
        y_1_2_reg_3162 <= y_1_2_fu_1062_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_89_reg_3232_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_1_reg_3224_pp0_it5))) begin
        col_assign_3_1_t1_reg_3453 <= col_assign_3_1_t1_fu_1450_p2;
        col_buf_1_val_0_0_16_reg_3457 <= col_buf_1_val_0_0_16_fu_1475_p3;
        sel_tmp43_reg_3463 <= sel_tmp43_fu_1489_p2;
        sel_tmp44_reg_3469 <= sel_tmp44_fu_1495_p2;
        tmp_94_reg_3447 <= ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_98_reg_3252_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_63_2_reg_3244_pp0_it5))) begin
        col_assign_3_2_t1_reg_3512 <= col_assign_3_2_t1_fu_1636_p2;
        col_buf_2_val_0_0_16_reg_3516 <= col_buf_2_val_0_0_16_fu_1661_p3;
        sel_tmp55_reg_3522 <= sel_tmp55_fu_1675_p2;
        sel_tmp56_reg_3528 <= sel_tmp56_fu_1681_p2;
        tmp_103_reg_3506 <= ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_84_reg_3210_pp0_it5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_3202_pp0_it5))) begin
        col_assign_3_reg_3409 <= col_assign_3_fu_1319_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2) & (ap_const_lv1_0 == tmp_38_fu_1152_p2))) begin
        col_assign_reg_3218 <= col_assign_fu_1157_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_0_val_0_0_11_fu_346 <= k_buf_0_val_0_q0;
        right_border_buf_0_val_0_0_fu_178 <= k_buf_0_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1))) begin
        col_buf_0_val_0_0_12_fu_350 <= k_buf_0_val_0_q0;
        right_border_buf_0_val_0_1_fu_182 <= k_buf_0_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_0_val_0_0_13_fu_354 <= k_buf_0_val_0_q0;
        right_border_buf_0_val_0_2_fu_186 <= k_buf_0_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        col_buf_0_val_0_0_fu_214 <= k_buf_0_val_0_q0;
        col_buf_1_val_0_0_fu_218 <= k_buf_1_val_0_q0;
        col_buf_2_val_0_0_fu_222 <= k_buf_2_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_1_val_0_0_11_fu_306 <= k_buf_1_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1))) begin
        col_buf_1_val_0_0_12_fu_322 <= k_buf_1_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_1_val_0_0_13_fu_330 <= k_buf_1_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_2_val_0_0_11_fu_234 <= k_buf_2_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1))) begin
        col_buf_2_val_0_0_12_fu_250 <= k_buf_2_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0))) begin
        col_buf_2_val_0_0_13_fu_258 <= k_buf_2_val_0_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_67)) begin
        cols_assign_cast1_reg_2757[0] <= cols_assign_cast1_fu_892_p1[0];
cols_assign_cast1_reg_2757[1] <= cols_assign_cast1_fu_892_p1[1];
cols_assign_cast1_reg_2757[2] <= cols_assign_cast1_fu_892_p1[2];
cols_assign_cast1_reg_2757[3] <= cols_assign_cast1_fu_892_p1[3];
cols_assign_cast1_reg_2757[4] <= cols_assign_cast1_fu_892_p1[4];
cols_assign_cast1_reg_2757[5] <= cols_assign_cast1_fu_892_p1[5];
cols_assign_cast1_reg_2757[6] <= cols_assign_cast1_fu_892_p1[6];
cols_assign_cast1_reg_2757[7] <= cols_assign_cast1_fu_892_p1[7];
cols_assign_cast1_reg_2757[8] <= cols_assign_cast1_fu_892_p1[8];
cols_assign_cast1_reg_2757[9] <= cols_assign_cast1_fu_892_p1[9];
cols_assign_cast1_reg_2757[10] <= cols_assign_cast1_fu_892_p1[10];
cols_assign_cast1_reg_2757[11] <= cols_assign_cast1_fu_892_p1[11];
        tmp_72_reg_2751 <= tmp_72_fu_888_p1;
        tmp_reg_2745 <= tmp_fu_884_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(tmp_23_fu_926_p2 == ap_const_lv1_0))) begin
        heightloop_reg_3051 <= heightloop_fu_932_p2;
        p_neg226_i_i_reg_3068 <= p_neg226_i_i_fu_951_p2;
        ref_cast_reg_3089[0] <= ref_cast_fu_965_p1[0];
ref_cast_reg_3089[1] <= ref_cast_fu_965_p1[1];
ref_cast_reg_3089[2] <= ref_cast_fu_965_p1[2];
ref_cast_reg_3089[3] <= ref_cast_fu_965_p1[3];
ref_cast_reg_3089[4] <= ref_cast_fu_965_p1[4];
ref_cast_reg_3089[5] <= ref_cast_fu_965_p1[5];
ref_cast_reg_3089[6] <= ref_cast_fu_965_p1[6];
ref_cast_reg_3089[7] <= ref_cast_fu_965_p1[7];
ref_cast_reg_3089[8] <= ref_cast_fu_965_p1[8];
ref_cast_reg_3089[9] <= ref_cast_fu_965_p1[9];
ref_cast_reg_3089[10] <= ref_cast_fu_965_p1[10];
        ref_reg_3084 <= ref_fu_960_p2;
        tmp_28_cast_reg_3061[0] <= tmp_28_cast_fu_947_p1[0];
tmp_28_cast_reg_3061[1] <= tmp_28_cast_fu_947_p1[1];
tmp_28_cast_reg_3061[2] <= tmp_28_cast_fu_947_p1[2];
tmp_28_cast_reg_3061[3] <= tmp_28_cast_fu_947_p1[3];
tmp_28_cast_reg_3061[4] <= tmp_28_cast_fu_947_p1[4];
tmp_28_cast_reg_3061[5] <= tmp_28_cast_fu_947_p1[5];
tmp_28_cast_reg_3061[6] <= tmp_28_cast_fu_947_p1[6];
tmp_28_cast_reg_3061[7] <= tmp_28_cast_fu_947_p1[7];
tmp_28_cast_reg_3061[8] <= tmp_28_cast_fu_947_p1[8];
tmp_28_cast_reg_3061[9] <= tmp_28_cast_fu_947_p1[9];
tmp_28_cast_reg_3061[10] <= tmp_28_cast_fu_947_p1[10];
        tmp_73_reg_3076 <= tmp_73_fu_956_p1;
        tmp_74_reg_3094 <= tmp_74_fu_969_p1;
        widthloop_reg_3056 <= widthloop_fu_937_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
        i_V_reg_3108 <= i_V_fu_982_p2;
        tmp_29_cast_cast3_reg_3099[0] <= tmp_29_cast_cast3_fu_973_p1[0];
tmp_29_cast_cast3_reg_3099[1] <= tmp_29_cast_cast3_fu_973_p1[1];
tmp_29_cast_cast3_reg_3099[2] <= tmp_29_cast_cast3_fu_973_p1[2];
tmp_29_cast_cast3_reg_3099[3] <= tmp_29_cast_cast3_fu_973_p1[3];
tmp_29_cast_cast3_reg_3099[4] <= tmp_29_cast_cast3_fu_973_p1[4];
tmp_29_cast_cast3_reg_3099[5] <= tmp_29_cast_cast3_fu_973_p1[5];
tmp_29_cast_cast3_reg_3099[6] <= tmp_29_cast_cast3_fu_973_p1[6];
tmp_29_cast_cast3_reg_3099[7] <= tmp_29_cast_cast3_fu_973_p1[7];
tmp_29_cast_cast3_reg_3099[8] <= tmp_29_cast_cast3_fu_973_p1[8];
tmp_29_cast_cast3_reg_3099[9] <= tmp_29_cast_cast3_fu_973_p1[9];
tmp_29_cast_cast3_reg_3099[10] <= tmp_29_cast_cast3_fu_973_p1[10];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))) begin
        k_buf_0_val_0_addr_reg_3329 <= tmp_35_fu_1287_p1;
        k_buf_0_val_1_addr_reg_3335 <= tmp_35_fu_1287_p1;
        k_buf_0_val_2_addr_reg_3341 <= tmp_35_fu_1287_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3))) begin
        locy_0_2_t_reg_3301 <= locy_0_2_t_fu_1272_p2;
        locy_1_2_t_reg_3313 <= locy_1_2_t_fu_1276_p2;
        locy_2_2_t_reg_3325 <= locy_2_2_t_fu_1280_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2))) begin
        or_cond2_1_reg_3228 <= or_cond2_1_fu_1173_p2;
        or_cond2_2_reg_3248 <= or_cond2_2_fu_1212_p2;
        or_cond2_reg_3206 <= or_cond2_fu_1138_p2;
        tmp_37_reg_3202 <= tmp_37_fu_1133_p2;
        tmp_63_1_reg_3224 <= tmp_63_1_fu_1168_p2;
        tmp_63_2_reg_3244 <= tmp_63_2_fu_1207_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        right_border_buf_0_val_1_0_reg_3382 <= k_buf_0_val_1_q0;
        right_border_buf_0_val_2_0_reg_3377 <= k_buf_0_val_0_q0;
        right_border_buf_1_val_1_0_reg_3420 <= k_buf_1_val_1_q0;
        right_border_buf_1_val_2_0_reg_3415 <= k_buf_1_val_0_q0;
        right_border_buf_2_val_1_0_reg_3479 <= k_buf_2_val_1_q0;
        right_border_buf_2_val_2_0_reg_3474 <= k_buf_2_val_0_q0;
        src_kernel_win_0_val_2_0_reg_3390 <= k_buf_0_val_2_q0;
        src_kernel_win_1_val_2_0_reg_3428 <= k_buf_1_val_2_q0;
        src_kernel_win_2_val_2_0_reg_3487 <= k_buf_2_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0)))) begin
        right_border_buf_0_val_1_2_14_fu_334 <= right_border_buf_0_val_1_2_19_fu_1391_p3;
        right_border_buf_0_val_1_2_15_fu_338 <= right_border_buf_0_val_1_2_5_fu_1382_p3;
        right_border_buf_0_val_1_2_16_fu_342 <= right_border_buf_0_val_1_2_3_fu_1365_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
        right_border_buf_1_val_0_0_fu_190 <= k_buf_1_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_1))) begin
        right_border_buf_1_val_0_1_fu_194 <= k_buf_1_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_93_reg_3240_pp0_it5 == ap_const_lv2_0))) begin
        right_border_buf_1_val_0_2_fu_198 <= k_buf_1_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5) & (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0)))) begin
        right_border_buf_1_val_1_2_12_fu_358 <= right_border_buf_1_val_1_2_19_fu_1577_p3;
        right_border_buf_1_val_1_2_15_fu_362 <= right_border_buf_1_val_1_2_6_74_fu_1568_p3;
        right_border_buf_1_val_1_2_16_fu_366 <= right_border_buf_1_val_1_2_4_fu_1551_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
        right_border_buf_2_val_0_0_fu_202 <= k_buf_2_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_1))) begin
        right_border_buf_2_val_0_1_fu_206 <= k_buf_2_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_102_reg_3260_pp0_it5 == ap_const_lv2_0))) begin
        right_border_buf_2_val_0_2_fu_210 <= k_buf_2_val_2_q0;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1) & ~(ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5) & (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0)))) begin
        right_border_buf_2_val_1_2_12_fu_270 <= right_border_buf_2_val_1_2_27_fu_1763_p3;
        right_border_buf_2_val_1_2_19_fu_286 <= right_border_buf_2_val_1_2_25_fu_1746_p3;
        right_border_buf_2_val_1_2_20_fu_294 <= right_border_buf_2_val_1_2_23_fu_1724_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it7))) begin
        src_kernel_win_0_val_0_1_lo_reg_3593 <= src_kernel_win_0_val_0_1_fu_226;
        src_kernel_win_0_val_1_1_lo_reg_3599 <= src_kernel_win_0_val_1_1_fu_242;
        src_kernel_win_0_val_1_2_lo_reg_3605 <= src_kernel_win_0_val_1_2_fu_246;
        src_kernel_win_1_val_0_1_lo_reg_3620 <= src_kernel_win_1_val_0_1_fu_262;
        src_kernel_win_1_val_1_1_lo_reg_3626 <= src_kernel_win_1_val_1_1_fu_278;
        src_kernel_win_1_val_1_2_lo_reg_3632 <= src_kernel_win_1_val_1_2_fu_282;
        src_kernel_win_2_val_0_1_lo_reg_3647 <= src_kernel_win_2_val_0_1_fu_298;
        src_kernel_win_2_val_1_1_lo_reg_3653 <= src_kernel_win_2_val_1_1_fu_314;
        src_kernel_win_2_val_1_2_lo_reg_3659 <= src_kernel_win_2_val_1_2_fu_318;
        temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610 <= temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3;
        temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637 <= temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3;
        temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664 <= temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3;
        tmp_115_0_1_reg_3615 <= tmp_115_0_1_fu_2364_p2;
        tmp_115_1_1_reg_3642 <= tmp_115_1_1_fu_2394_p2;
        tmp_115_2_1_reg_3669 <= tmp_115_2_1_fu_2424_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it10) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it9))) begin
        src_kernel_win_0_val_0_2_fu_230 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it9;
        src_kernel_win_1_val_0_2_fu_266 <= ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it9;
        src_kernel_win_2_val_0_2_fu_302 <= ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it9;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it9))) begin
        src_kernel_win_0_val_0_2_lo_reg_3692 <= src_kernel_win_0_val_0_2_fu_230;
        src_kernel_win_1_val_0_2_lo_reg_3707 <= src_kernel_win_1_val_0_2_fu_266;
        src_kernel_win_2_val_0_2_lo_reg_3722 <= src_kernel_win_2_val_0_2_fu_302;
        temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697 <= temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3;
        temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712 <= temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3;
        temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727 <= temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3;
        tmp_115_0_2_reg_3702 <= tmp_115_0_2_fu_2506_p2;
        tmp_115_1_2_reg_3717 <= tmp_115_1_2_fu_2525_p2;
        tmp_115_2_2_reg_3732 <= tmp_115_2_2_fu_2544_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it8) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it7))) begin
        src_kernel_win_0_val_1_2_fu_246 <= src_kernel_win_0_val_1_1_12_reg_3540;
        src_kernel_win_1_val_1_2_fu_282 <= src_kernel_win_1_val_1_1_12_reg_3554;
        src_kernel_win_2_val_1_2_fu_318 <= src_kernel_win_2_val_1_1_12_reg_3568;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6))) begin
        src_kernel_win_0_val_2_2_fu_254 <= src_kernel_win_0_val_2_1_fu_238;
        src_kernel_win_1_val_2_2_fu_290 <= src_kernel_win_1_val_2_1_fu_274;
        src_kernel_win_2_val_2_2_fu_326 <= src_kernel_win_2_val_2_1_fu_310;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it6) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it6))) begin
        temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575 <= temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3;
        temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581 <= temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3;
        temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587 <= temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it8))) begin
        temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674 <= temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3;
        temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680 <= temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3;
        temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686 <= temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it10))) begin
        temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737 <= temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3;
        temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743 <= temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3;
        temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749 <= temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == tmp_77_reg_3131))) begin
        tmp_100_reg_3500 <= tmp_100_fu_1613_p1;
        tmp_85_reg_3397 <= tmp_85_fu_1311_p1;
        tmp_86_reg_3403 <= tmp_86_fu_1315_p1;
        tmp_90_reg_3435 <= tmp_90_fu_1423_p1;
        tmp_91_reg_3441 <= tmp_91_fu_1427_p1;
        tmp_99_reg_3494 <= tmp_99_fu_1609_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131))) begin
        tmp_101_reg_3286 <= tmp_101_fu_1264_p1;
        tmp_87_reg_3276 <= tmp_87_fu_1256_p1;
        tmp_92_reg_3281 <= tmp_92_fu_1260_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2) & (ap_const_lv1_0 == tmp_66_2_fu_1226_p2))) begin
        tmp_102_reg_3260 <= tmp_102_fu_1236_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & ~(ap_const_lv1_0 == or_cond2_2_reg_3248) & (ap_const_lv1_0 == tmp_66_2_reg_3256))) begin
        tmp_105_reg_3270 <= tmp_105_fu_1252_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
        tmp_38_reg_3214 <= tmp_38_fu_1152_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
        tmp_66_1_reg_3236 <= tmp_66_1_fu_1187_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
        tmp_66_2_reg_3256 <= tmp_66_2_fu_1226_p2;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3))) begin
        tmp_83_reg_3296 <= tmp_83_fu_1268_p1;
        x_1_reg_3305 <= grp_image_filter_borderInterpolate_fu_700_ap_return;
        x_2_reg_3317 <= grp_image_filter_borderInterpolate_fu_708_ap_return;
        x_reg_3291 <= grp_image_filter_borderInterpolate_fu_692_ap_return;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_fu_1138_p2))) begin
        tmp_84_reg_3210 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_1_fu_1173_p2))) begin
        tmp_89_reg_3232 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & ~(ap_const_lv1_0 == or_cond2_1_fu_1173_p2) & (ap_const_lv1_0 == tmp_66_1_fu_1187_p2))) begin
        tmp_93_reg_3240 <= tmp_93_fu_1197_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & ~(ap_const_lv1_0 == or_cond2_1_reg_3228) & (ap_const_lv1_0 == tmp_66_1_reg_3236))) begin
        tmp_96_reg_3264 <= tmp_96_fu_1244_p1;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == or_cond2_2_fu_1212_p2))) begin
        tmp_98_reg_3252 <= ImagLoc_x_fu_1113_p2[ap_const_lv32_B];
    end
end

/// ap_done assign process. ///
always @ (ap_done_reg or ap_sig_cseq_ST_st5_fsm_4 or tmp_28_fu_977_p2)
begin
    if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2)))) begin
        ap_done = ap_const_logic_1;
    end else begin
        ap_done = ap_const_logic_0;
    end
end

/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
    if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = ap_const_logic_1;
    end else begin
        ap_idle = ap_const_logic_0;
    end
end

/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st5_fsm_4 or tmp_28_fu_977_p2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == tmp_28_fu_977_p2))) begin
        ap_ready = ap_const_logic_1;
    end else begin
        ap_ready = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_pp0_stg0_fsm_6 assign process. ///
always @ (ap_sig_bdd_175)
begin
    if (ap_sig_bdd_175) begin
        ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_pp0_stg0_fsm_6 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_27)
begin
    if (ap_sig_bdd_27) begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st20_fsm_7 assign process. ///
always @ (ap_sig_bdd_951)
begin
    if (ap_sig_bdd_951) begin
        ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st20_fsm_7 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_85)
begin
    if (ap_sig_bdd_85) begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_94)
begin
    if (ap_sig_bdd_94) begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_103)
begin
    if (ap_sig_bdd_103) begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_133)
begin
    if (ap_sig_bdd_133) begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
    end
end

/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_162)
begin
    if (ap_sig_bdd_162) begin
        ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
    end else begin
        ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_668_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
        grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_668_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_676_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
        grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_676_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_684_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or tmp_33_fu_1081_p2 or tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_fu_1081_p2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == tmp_33_reg_3180) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1))))) begin
        grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_684_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_692_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
        grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_692_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_700_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
        grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_700_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_708_ap_ce assign process. ///
always @ (tmp_33_reg_3180 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it1 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (~(ap_const_lv1_0 == tmp_33_reg_3180) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3) | ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it1)))) begin
        grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_708_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_716_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_716_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_724_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_724_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_732_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_732_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_740_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_740_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_748_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_748_ap_ce = ap_const_logic_0;
    end
end

/// grp_image_filter_borderInterpolate_fu_756_ap_ce assign process. ///
always @ (tmp_77_reg_3131 or brmerge_reg_3176 or ap_sig_cseq_ST_pp0_stg0_fsm_6 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it2 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it3 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it4)
begin
    if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (((ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it2) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it3)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & (ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131)) | ((ap_const_lv1_0 == brmerge_reg_3176) & (ap_const_lv1_0 == tmp_77_reg_3131) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it4))))) begin
        grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_1;
    end else begin
        grp_image_filter_borderInterpolate_fu_756_ap_ce = ap_const_logic_0;
    end
end

/// k_buf_0_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_0_val_0_ce0 = ap_const_logic_1;
    end else begin
        k_buf_0_val_0_ce0 = ap_const_logic_0;
    end
end

/// k_buf_0_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_0_val_0_ce1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_0_ce1 = ap_const_logic_0;
    end
end

/// k_buf_0_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_0_val_0_we1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_0_we1 = ap_const_logic_0;
    end
end

/// k_buf_0_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_0_val_1_ce0 = ap_const_logic_1;
    end else begin
        k_buf_0_val_1_ce0 = ap_const_logic_0;
    end
end

/// k_buf_0_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
        k_buf_0_val_1_ce1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_1_ce1 = ap_const_logic_0;
    end
end

/// k_buf_0_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
        k_buf_0_val_1_we1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_1_we1 = ap_const_logic_0;
    end
end

/// k_buf_0_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_0_val_2_ce0 = ap_const_logic_1;
    end else begin
        k_buf_0_val_2_ce0 = ap_const_logic_0;
    end
end

/// k_buf_0_val_2_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
        k_buf_0_val_2_ce1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_2_ce1 = ap_const_logic_0;
    end
end

/// k_buf_0_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_38_reg_3214_pp0_it5)))) begin
        k_buf_0_val_2_we1 = ap_const_logic_1;
    end else begin
        k_buf_0_val_2_we1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_0_ce0 = ap_const_logic_1;
    end else begin
        k_buf_1_val_0_ce0 = ap_const_logic_0;
    end
end

/// k_buf_1_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_0_ce1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_0_ce1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_0_we1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_0_we1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5 or tmp_99_1_fu_1516_p1 or k_buf_1_val_1_addr_1_gep_fu_554_p3 or ap_sig_bdd_967)
begin
    if (ap_sig_bdd_967) begin
        if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) begin
            k_buf_1_val_1_address1 = k_buf_1_val_1_addr_1_gep_fu_554_p3;
        end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) begin
            k_buf_1_val_1_address1 = tmp_99_1_fu_1516_p1;
        end else begin
            k_buf_1_val_1_address1 = 'bx;
        end
    end else begin
        k_buf_1_val_1_address1 = 'bx;
    end
end

/// k_buf_1_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_1_ce0 = ap_const_logic_1;
    end else begin
        k_buf_1_val_1_ce0 = ap_const_logic_0;
    end
end

/// k_buf_1_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)))) begin
        k_buf_1_val_1_ce1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_1_ce1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_1_reg_3236_pp0_it5)))) begin
        k_buf_1_val_1_we1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_1_we1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_2_ce0 = ap_const_logic_1;
    end else begin
        k_buf_1_val_2_ce0 = ap_const_logic_0;
    end
end

/// k_buf_1_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_2_ce1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_2_ce1 = ap_const_logic_0;
    end
end

/// k_buf_1_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_1_val_2_we1 = ap_const_logic_1;
    end else begin
        k_buf_1_val_2_we1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_0_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_0_ce0 = ap_const_logic_1;
    end else begin
        k_buf_2_val_0_ce0 = ap_const_logic_0;
    end
end

/// k_buf_2_val_0_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_0_ce1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_0_ce1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_0_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_0_we1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_0_we1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_1_address1 assign process. ///
always @ (ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5 or tmp_99_2_fu_1702_p1 or k_buf_2_val_1_addr_1_gep_fu_594_p3 or ap_sig_bdd_979)
begin
    if (ap_sig_bdd_979) begin
        if (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) begin
            k_buf_2_val_1_address1 = k_buf_2_val_1_addr_1_gep_fu_594_p3;
        end else if ((ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) begin
            k_buf_2_val_1_address1 = tmp_99_2_fu_1702_p1;
        end else begin
            k_buf_2_val_1_address1 = 'bx;
        end
    end else begin
        k_buf_2_val_1_address1 = 'bx;
    end
end

/// k_buf_2_val_1_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_1_ce0 = ap_const_logic_1;
    end else begin
        k_buf_2_val_1_ce0 = ap_const_logic_0;
    end
end

/// k_buf_2_val_1_ce1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)))) begin
        k_buf_2_val_1_ce1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_1_ce1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_1_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)
begin
    if (((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_66_2_reg_3256_pp0_it5)))) begin
        k_buf_2_val_1_we1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_1_we1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_2_ce0 assign process. ///
always @ (ap_reg_ppiten_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_2_ce0 = ap_const_logic_1;
    end else begin
        k_buf_2_val_2_ce0 = ap_const_logic_0;
    end
end

/// k_buf_2_val_2_ce1 assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_2_ce1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_2_ce1 = ap_const_logic_0;
    end
end

/// k_buf_2_val_2_we1 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        k_buf_2_val_2_we1 = ap_const_logic_1;
    end else begin
        k_buf_2_val_2_we1 = ap_const_logic_0;
    end
end

/// p_dst_data_stream_0_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_dst_data_stream_0_V_write = ap_const_logic_1;
    end else begin
        p_dst_data_stream_0_V_write = ap_const_logic_0;
    end
end

/// p_dst_data_stream_1_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_dst_data_stream_1_V_write = ap_const_logic_1;
    end else begin
        p_dst_data_stream_1_V_write = ap_const_logic_0;
    end
end

/// p_dst_data_stream_2_V_write assign process. ///
always @ (ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_dst_data_stream_2_V_write = ap_const_logic_1;
    end else begin
        p_dst_data_stream_2_V_write = ap_const_logic_0;
    end
end

/// p_src_data_stream_0_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_src_data_stream_0_V_read = ap_const_logic_1;
    end else begin
        p_src_data_stream_0_V_read = ap_const_logic_0;
    end
end

/// p_src_data_stream_1_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_src_data_stream_1_V_read = ap_const_logic_1;
    end else begin
        p_src_data_stream_1_V_read = ap_const_logic_0;
    end
end

/// p_src_data_stream_2_V_read assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12)
begin
    if ((~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))))) begin
        p_src_data_stream_2_V_read = ap_const_logic_1;
    end else begin
        p_src_data_stream_2_V_read = ap_const_logic_0;
    end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_67 or tmp_23_fu_926_p2 or tmp_28_fu_977_p2 or ap_sig_bdd_218 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it11 or ap_sig_bdd_244 or ap_reg_ppiten_pp0_it12 or tmp_s_fu_902_p2 or tmp_20_fu_914_p2)
begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : 
        begin
            if (~ap_sig_bdd_67) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : 
        begin
            if (~(ap_const_lv1_0 == tmp_s_fu_902_p2)) begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end else begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end
        end
        ap_ST_st3_fsm_2 : 
        begin
            if (~(ap_const_lv1_0 == tmp_20_fu_914_p2)) begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st4_fsm_3 : 
        begin
            if (~(tmp_23_fu_926_p2 == ap_const_lv1_0)) begin
                ap_NS_fsm = ap_ST_st5_fsm_4;
            end else begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end
        end
        ap_ST_st5_fsm_4 : 
        begin
            if ((ap_const_lv1_0 == tmp_28_fu_977_p2)) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else begin
                ap_NS_fsm = ap_ST_st6_fsm_5;
            end
        end
        ap_ST_st6_fsm_5 : 
        begin
            ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
        end
        ap_ST_pp0_stg0_fsm_6 : 
        begin
            if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
            end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it12) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it11)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it7) & ~((ap_sig_bdd_218 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6)) | (ap_sig_bdd_244 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it12))) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it8)))) begin
                ap_NS_fsm = ap_ST_st20_fsm_7;
            end else begin
                ap_NS_fsm = ap_ST_pp0_stg0_fsm_6;
            end
        end
        ap_ST_st20_fsm_7 : 
        begin
            ap_NS_fsm = ap_ST_st5_fsm_4;
        end
        default : 
        begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ImagLoc_x_cast2_fu_1123_p1 = $signed(ImagLoc_x_fu_1113_p2);
assign ImagLoc_x_fu_1113_p2 = ($signed(tmp_33_cast_fu_1077_p1) + $signed(ap_const_lv12_FFF));
assign ImagLoc_y_fu_994_p2 = ($signed(tmp_29_cast_cast3_fu_973_p1) + $signed(ap_const_lv12_FFC));

/// ap_sig_bdd_103 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_103 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end

/// ap_sig_bdd_133 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_133 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end

/// ap_sig_bdd_162 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_162 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end

/// ap_sig_bdd_175 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_175 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end

/// ap_sig_bdd_218 assign process. ///
always @ (p_src_data_stream_0_V_empty_n or p_src_data_stream_1_V_empty_n or p_src_data_stream_2_V_empty_n or brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_reg_3206_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)
begin
    ap_sig_bdd_218 = (((p_src_data_stream_0_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_reg_3206_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_1_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5)) | (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & (p_src_data_stream_2_V_empty_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5)));
end

/// ap_sig_bdd_244 assign process. ///
always @ (p_dst_data_stream_0_V_full_n or p_dst_data_stream_1_V_full_n or p_dst_data_stream_2_V_full_n or ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)
begin
    ap_sig_bdd_244 = (((p_dst_data_stream_0_V_full_n == ap_const_logic_0) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_1_V_full_n == ap_const_logic_0)) | (~(ap_const_lv1_0 == ap_reg_ppstg_or_cond219_i_i_reg_3189_pp0_it11) & (p_dst_data_stream_2_V_full_n == ap_const_logic_0)));
end

/// ap_sig_bdd_27 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_27 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end

/// ap_sig_bdd_67 assign process. ///
always @ (ap_start or ap_done_reg)
begin
    ap_sig_bdd_67 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end

/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end

/// ap_sig_bdd_94 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_94 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end

/// ap_sig_bdd_951 assign process. ///
always @ (ap_CS_fsm)
begin
    ap_sig_bdd_951 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end

/// ap_sig_bdd_967 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
    ap_sig_bdd_967 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_1_reg_3228_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end

/// ap_sig_bdd_979 assign process. ///
always @ (brmerge_reg_3176 or ap_reg_ppstg_tmp_33_reg_3180_pp0_it5 or ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5 or ap_reg_ppiten_pp0_it6)
begin
    ap_sig_bdd_979 = (~(ap_const_lv1_0 == ap_reg_ppstg_tmp_33_reg_3180_pp0_it5) & ~(ap_const_lv1_0 == brmerge_reg_3176) & ~(ap_const_lv1_0 == ap_reg_ppstg_or_cond2_2_reg_3248_pp0_it5) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it6));
end
assign brmerge_fu_1072_p2 = (tmp_31_fu_1057_p2 | or_cond_2_reg_3126);
assign col_assign_1_fu_1192_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_assign_3_1_t1_fu_1450_p2 = (tmp_95_fu_1447_p1 + tmp_73_reg_3076);
assign col_assign_3_2_t1_fu_1636_p2 = (tmp_104_fu_1633_p1 + tmp_73_reg_3076);
assign col_assign_3_fu_1319_p2 = (ap_reg_ppstg_tmp_83_reg_3296_pp0_it5 + tmp_73_reg_3076);
assign col_assign_4_1_fu_1240_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_4_2_fu_1248_p2 = (ImagLoc_x_reg_3193 + p_neg226_i_i_reg_3068);
assign col_assign_fu_1157_p2 = (tmp_82_fu_1119_p1 + tmp_73_reg_3076);
assign col_assign_s_fu_1231_p2 = (ImagLoc_x_fu_1113_p2 + p_neg226_i_i_reg_3068);
assign col_buf_0_val_0_0_16_fu_1926_p3 = ((sel_tmp2_fu_1921_p2)? col_buf_0_val_0_0_11_fu_346: col_buf_0_val_0_0_6_fu_1913_p3);
assign col_buf_0_val_0_0_6_fu_1913_p3 = ((sel_tmp_fu_1908_p2)? col_buf_0_val_0_0_12_fu_350: col_buf_0_val_0_0_13_fu_354);
assign col_buf_1_val_0_0_16_fu_1475_p3 = ((sel_tmp40_fu_1469_p2)? col_buf_1_val_0_0_13_fu_330: col_buf_1_val_0_0_6_fu_1461_p3);
assign col_buf_1_val_0_0_6_fu_1461_p3 = ((sel_tmp39_fu_1455_p2)? col_buf_1_val_0_0_12_fu_322: col_buf_1_val_0_0_11_fu_306);
assign col_buf_2_val_0_0_16_fu_1661_p3 = ((sel_tmp52_fu_1655_p2)? col_buf_2_val_0_0_13_fu_258: col_buf_2_val_0_0_6_fu_1647_p3);
assign col_buf_2_val_0_0_6_fu_1647_p3 = ((sel_tmp51_fu_1641_p2)? col_buf_2_val_0_0_12_fu_250: col_buf_2_val_0_0_11_fu_234);
assign cols_assign_cast1_fu_892_p1 = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_668_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_668_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_668_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_676_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_676_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_676_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_684_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_684_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_684_p = y_1_2_1_reg_3169;
assign grp_image_filter_borderInterpolate_fu_692_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_692_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_692_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_700_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_700_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_700_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_708_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_708_len = p_src_cols_V_read;
assign grp_image_filter_borderInterpolate_fu_708_p = ImagLoc_x_reg_3193;
assign grp_image_filter_borderInterpolate_fu_716_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_716_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_716_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_724_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_724_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_724_p = y_1_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_732_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_732_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_732_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_740_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_740_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_740_p = y_1_2_reg_3162;
assign grp_image_filter_borderInterpolate_fu_748_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_748_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_748_p = ImagLoc_y_reg_3118;
assign grp_image_filter_borderInterpolate_fu_756_borderType = ap_const_lv5_1;
assign grp_image_filter_borderInterpolate_fu_756_len = p_src_rows_V_read;
assign grp_image_filter_borderInterpolate_fu_756_p = y_1_2_reg_3162;
assign heightloop_fu_932_p2 = (tmp_reg_2745 + ap_const_lv11_5);
assign i_V_fu_982_p2 = (p_012_0_i_i_reg_645 + ap_const_lv11_1);
assign icmp2_fu_1102_p2 = (tmp_80_fu_1092_p4 != ap_const_lv10_0? 1'b1: 1'b0);
assign icmp_fu_1010_p2 = ($signed(tmp_75_fu_1000_p4) > $signed(11'b00000000000)? 1'b1: 1'b0);
assign j_V_fu_1086_p2 = (p_025_0_i_i_reg_656 + ap_const_lv11_1);
assign k_buf_0_val_0_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_0_address1 = k_buf_0_val_0_addr_reg_3329;
assign k_buf_0_val_0_d1 = p_src_data_stream_0_V_dout;
assign k_buf_0_val_1_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_1_address1 = k_buf_0_val_1_addr_reg_3335;
assign k_buf_0_val_1_d1 = k_buf_0_val_0_q0;
assign k_buf_0_val_2_address0 = tmp_35_fu_1287_p1;
assign k_buf_0_val_2_address1 = k_buf_0_val_2_addr_reg_3341;
assign k_buf_0_val_2_d1 = k_buf_0_val_1_q0;
assign k_buf_1_val_0_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_0_address1 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_0_d1 = p_src_data_stream_1_V_dout;
assign k_buf_1_val_1_addr_1_gep_fu_554_p3 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_1_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_1_d1 = k_buf_1_val_0_q0;
assign k_buf_1_val_2_address0 = tmp_56_1_fu_1294_p1;
assign k_buf_1_val_2_address1 = tmp_99_1_fu_1516_p1;
assign k_buf_1_val_2_d1 = k_buf_1_val_1_q0;
assign k_buf_2_val_0_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_0_address1 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_0_d1 = p_src_data_stream_2_V_dout;
assign k_buf_2_val_1_addr_1_gep_fu_594_p3 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_1_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_1_d1 = k_buf_2_val_0_q0;
assign k_buf_2_val_2_address0 = tmp_56_2_fu_1300_p1;
assign k_buf_2_val_2_address1 = tmp_99_2_fu_1702_p1;
assign k_buf_2_val_2_d1 = k_buf_2_val_1_q0;
assign locy_0_1_t_fu_1846_p2 = (tmp_79_reg_3155 - tmp_86_reg_3403);
assign locy_0_2_t_fu_1272_p2 = (tmp_79_reg_3155 - tmp_87_reg_3276);
assign locy_1_0_t_fu_1993_p2 = (tmp_32_reg_3135 - tmp_90_reg_3435);
assign locy_1_1_t_fu_2025_p2 = (tmp_32_reg_3135 - tmp_91_reg_3441);
assign locy_1_2_t_fu_1276_p2 = (tmp_32_reg_3135 - tmp_92_reg_3281);
assign locy_2_0_t_fu_2159_p2 = (tmp_32_reg_3135 - tmp_99_reg_3494);
assign locy_2_1_t_fu_2191_p2 = (tmp_32_reg_3135 - tmp_100_reg_3500);
assign locy_2_2_t_fu_1280_p2 = (tmp_32_reg_3135 - tmp_101_reg_3286);
assign locy_fu_1814_p2 = (tmp_78_reg_3149 - tmp_85_reg_3397);
assign or_cond219_i_i_fu_1108_p2 = (tmp_30_reg_3113 & icmp2_fu_1102_p2);
assign or_cond2_1_fu_1173_p2 = (tmp_61_1_fu_1162_p2 & tmp_63_1_fu_1168_p2);
assign or_cond2_2_fu_1212_p2 = (tmp_61_2_fu_1201_p2 & tmp_63_2_fu_1207_p2);
assign or_cond2_fu_1138_p2 = (tmp_36_fu_1127_p2 & tmp_37_fu_1133_p2);
assign or_cond_2_fu_1021_p2 = (icmp_fu_1010_p2 & tmp_58_2_fu_1016_p2);
assign p_dst_data_stream_0_V_din = ((tmp_115_0_2_2_fu_2613_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11: temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737);
assign p_dst_data_stream_1_V_din = ((tmp_115_1_2_2_fu_2624_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11: temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743);
assign p_dst_data_stream_2_V_din = ((tmp_115_2_2_2_fu_2635_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11: temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749);
assign p_i_i_fu_1042_p3 = ((tmp_58_2_fu_1016_p2)? ap_const_lv11_2: ref_reg_3084);
assign p_neg226_i_i_fu_951_p2 = (ap_const_lv12_3 - p_src_cols_V_read);
assign ref_cast_fu_965_p1 = ref_fu_960_p2;
assign ref_fu_960_p2 = ($signed(tmp_reg_2745) + $signed(ap_const_lv11_7FF));
assign right_border_buf_0_val_1_2_19_fu_1391_p3 = ((sel_tmp26_fu_1360_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_14_fu_334);
assign right_border_buf_0_val_1_2_20_fu_1943_p3 = ((sel_tmp2_fu_1921_p2)? right_border_buf_0_val_1_2_14_fu_334: right_border_buf_0_val_1_2_fu_1935_p3);
assign right_border_buf_0_val_1_2_2_fu_1352_p3 = ((sel_tmp24_fu_1347_p2)? right_border_buf_0_val_1_2_16_fu_342: k_buf_0_val_1_q0);
assign right_border_buf_0_val_1_2_3_fu_1365_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_16_fu_342: right_border_buf_0_val_1_2_2_fu_1352_p3);
assign right_border_buf_0_val_1_2_4_fu_1374_p3 = ((sel_tmp24_fu_1347_p2)? k_buf_0_val_1_q0: right_border_buf_0_val_1_2_15_fu_338);
assign right_border_buf_0_val_1_2_5_fu_1382_p3 = ((sel_tmp26_fu_1360_p2)? right_border_buf_0_val_1_2_15_fu_338: right_border_buf_0_val_1_2_4_fu_1374_p3);
assign right_border_buf_0_val_1_2_fu_1935_p3 = ((sel_tmp_fu_1908_p2)? right_border_buf_0_val_1_2_15_fu_338: right_border_buf_0_val_1_2_16_fu_342);
assign right_border_buf_1_val_1_2_19_fu_1577_p3 = ((sel_tmp38_fu_1546_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_12_fu_358);
assign right_border_buf_1_val_1_2_1_fu_2098_p3 = ((tmp_94_reg_3447)? ap_const_lv8_0: right_border_buf_1_val_1_2_fu_2091_p3);
assign right_border_buf_1_val_1_2_3_fu_1538_p3 = ((sel_tmp36_fu_1533_p2)? right_border_buf_1_val_1_2_16_fu_366: k_buf_1_val_1_q0);
assign right_border_buf_1_val_1_2_4_fu_1551_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_16_fu_366: right_border_buf_1_val_1_2_3_fu_1538_p3);
assign right_border_buf_1_val_1_2_5_fu_1560_p3 = ((sel_tmp36_fu_1533_p2)? k_buf_1_val_1_q0: right_border_buf_1_val_1_2_15_fu_362);
assign right_border_buf_1_val_1_2_6_74_fu_1568_p3 = ((sel_tmp38_fu_1546_p2)? right_border_buf_1_val_1_2_15_fu_362: right_border_buf_1_val_1_2_5_fu_1560_p3);
assign right_border_buf_1_val_1_2_fu_2091_p3 = ((sel_tmp44_reg_3469)? right_border_buf_1_val_1_2_15_fu_362: right_border_buf_1_val_1_2_16_fu_366);
assign right_border_buf_2_val_1_2_1_fu_2264_p3 = ((tmp_103_reg_3506)? ap_const_lv8_0: right_border_buf_2_val_1_2_fu_2257_p3);
assign right_border_buf_2_val_1_2_23_fu_1724_p3 = ((sel_tmp57_fu_1719_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_20_fu_294);
assign right_border_buf_2_val_1_2_24_fu_1738_p3 = ((sel_tmp58_fu_1733_p2)? k_buf_2_val_1_q0: right_border_buf_2_val_1_2_19_fu_286);
assign right_border_buf_2_val_1_2_25_fu_1746_p3 = ((sel_tmp57_fu_1719_p2)? right_border_buf_2_val_1_2_19_fu_286: right_border_buf_2_val_1_2_24_fu_1738_p3);
assign right_border_buf_2_val_1_2_26_fu_1755_p3 = ((sel_tmp58_fu_1733_p2)? right_border_buf_2_val_1_2_12_fu_270: k_buf_2_val_1_q0);
assign right_border_buf_2_val_1_2_27_fu_1763_p3 = ((sel_tmp57_fu_1719_p2)? right_border_buf_2_val_1_2_12_fu_270: right_border_buf_2_val_1_2_26_fu_1755_p3);
assign right_border_buf_2_val_1_2_fu_2257_p3 = ((sel_tmp56_reg_3528)? right_border_buf_2_val_1_2_19_fu_286: right_border_buf_2_val_1_2_12_fu_270);
assign sel_tmp10_fu_1832_p2 = (locy_fu_1814_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp12_fu_1853_p2 = (tmp_79_reg_3155 == tmp_86_reg_3403? 1'b1: 1'b0);
assign sel_tmp13_fu_1857_p3 = ((sel_tmp12_fu_1853_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp14_fu_1864_p2 = (locy_0_1_t_fu_1846_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp16_fu_2000_p2 = (tmp_32_reg_3135 == tmp_90_reg_3435? 1'b1: 1'b0);
assign sel_tmp17_fu_2004_p3 = ((sel_tmp16_fu_2000_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp18_fu_2011_p2 = (locy_1_0_t_fu_1993_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp20_fu_2032_p2 = (tmp_32_reg_3135 == tmp_91_reg_3441? 1'b1: 1'b0);
assign sel_tmp21_fu_2036_p3 = ((sel_tmp20_fu_2032_p2)? col_buf_1_val_0_0_fu_218: src_kernel_win_1_val_2_0_reg_3428);
assign sel_tmp22_fu_2043_p2 = (locy_1_1_t_fu_2025_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp24_fu_1347_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp26_fu_1360_p2 = (ap_reg_ppstg_col_assign_reg_3218_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp2_fu_1921_p2 = (col_assign_3_reg_3409 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp36_fu_1533_p2 = (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp38_fu_1546_p2 = (ap_reg_ppstg_tmp_96_reg_3264_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp39_fu_1455_p2 = (col_assign_3_1_t1_fu_1450_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp40_fu_1469_p2 = (col_assign_3_1_t1_fu_1450_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp41_fu_2078_p3 = ((tmp_94_reg_3447)? ap_const_lv8_0: col_buf_1_val_0_0_16_reg_3457);
assign sel_tmp42_fu_1483_p2 = (tmp_94_fu_1440_p3 ^ ap_const_lv1_1);
assign sel_tmp43_fu_1489_p2 = (sel_tmp40_fu_1469_p2 & sel_tmp42_fu_1483_p2);
assign sel_tmp44_fu_1495_p2 = (sel_tmp39_fu_1455_p2 & sel_tmp42_fu_1483_p2);
assign sel_tmp45_fu_2166_p2 = (tmp_32_reg_3135 == tmp_99_reg_3494? 1'b1: 1'b0);
assign sel_tmp46_fu_2170_p3 = ((sel_tmp45_fu_2166_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp47_fu_2177_p2 = (locy_2_0_t_fu_2159_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp48_fu_2198_p2 = (tmp_32_reg_3135 == tmp_100_reg_3500? 1'b1: 1'b0);
assign sel_tmp49_fu_2202_p3 = ((sel_tmp48_fu_2198_p2)? col_buf_2_val_0_0_fu_222: src_kernel_win_2_val_2_0_reg_3487);
assign sel_tmp50_fu_2209_p2 = (locy_2_1_t_fu_2191_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp51_fu_1641_p2 = (col_assign_3_2_t1_fu_1636_p2 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp52_fu_1655_p2 = (col_assign_3_2_t1_fu_1636_p2 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp53_fu_2244_p3 = ((tmp_103_reg_3506)? ap_const_lv8_0: col_buf_2_val_0_0_16_reg_3516);
assign sel_tmp54_fu_1669_p2 = (tmp_103_fu_1626_p3 ^ ap_const_lv1_1);
assign sel_tmp55_fu_1675_p2 = (sel_tmp52_fu_1655_p2 & sel_tmp54_fu_1669_p2);
assign sel_tmp56_fu_1681_p2 = (sel_tmp51_fu_1641_p2 & sel_tmp54_fu_1669_p2);
assign sel_tmp57_fu_1719_p2 = (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_0? 1'b1: 1'b0);
assign sel_tmp58_fu_1733_p2 = (ap_reg_ppstg_tmp_105_reg_3270_pp0_it5 == ap_const_lv2_1? 1'b1: 1'b0);
assign sel_tmp8_fu_1821_p2 = (tmp_78_reg_3149 == tmp_85_reg_3397? 1'b1: 1'b0);
assign sel_tmp9_fu_1825_p3 = ((sel_tmp8_fu_1821_p2)? col_buf_0_val_0_0_fu_214: src_kernel_win_0_val_2_0_reg_3390);
assign sel_tmp_fu_1908_p2 = (col_assign_3_reg_3409 == ap_const_lv2_1? 1'b1: 1'b0);
assign src_kernel_win_0_val_0_1_9_fu_1838_p3 = ((sel_tmp10_fu_1832_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp9_fu_1825_p3);
assign src_kernel_win_0_val_1_1_9_fu_1870_p3 = ((sel_tmp14_fu_1864_p2)? right_border_buf_0_val_1_0_reg_3382: sel_tmp13_fu_1857_p3);
assign src_kernel_win_1_val_0_1_10_fu_2084_p3 = ((sel_tmp43_reg_3463)? col_buf_1_val_0_0_16_reg_3457: sel_tmp41_fu_2078_p3);
assign src_kernel_win_1_val_0_1_9_fu_2017_p3 = ((sel_tmp18_fu_2011_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp17_fu_2004_p3);
assign src_kernel_win_1_val_1_1_10_fu_2105_p3 = ((sel_tmp43_reg_3463)? right_border_buf_1_val_1_2_12_fu_358: right_border_buf_1_val_1_2_1_fu_2098_p3);
assign src_kernel_win_1_val_1_1_9_fu_2049_p3 = ((sel_tmp22_fu_2043_p2)? right_border_buf_1_val_1_0_reg_3420: sel_tmp21_fu_2036_p3);
assign src_kernel_win_2_val_0_1_10_fu_2250_p3 = ((sel_tmp55_reg_3522)? col_buf_2_val_0_0_16_reg_3516: sel_tmp53_fu_2244_p3);
assign src_kernel_win_2_val_0_1_9_fu_2183_p3 = ((sel_tmp47_fu_2177_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp46_fu_2170_p3);
assign src_kernel_win_2_val_1_1_10_fu_2271_p3 = ((sel_tmp55_reg_3522)? right_border_buf_2_val_1_2_20_fu_294: right_border_buf_2_val_1_2_1_fu_2264_p3);
assign src_kernel_win_2_val_1_1_9_fu_2215_p3 = ((sel_tmp50_fu_2209_p2)? right_border_buf_2_val_1_0_reg_3479: sel_tmp49_fu_2202_p3);
assign temp_0_i_i_i_057_i_i_1_0_0_1_fu_1985_p3 = ((tmp_115_0_0_1_fu_1979_p2)? src_kernel_win_0_val_2_1_fu_238: src_kernel_win_0_val_2_2_fu_254);
assign temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3 = ((tmp_115_0_0_2_fu_2352_p2)? src_kernel_win_0_val_2_1_fu_238: temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575);
assign temp_0_i_i_i_057_i_i_1_0_1_1_fu_2452_p3 = ((tmp_115_0_1_1_fu_2447_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8: temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3);
assign temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3 = ((tmp_115_0_1_2_fu_2496_p2)? ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9: temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674);
assign temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3 = ((tmp_115_0_1_reg_3615)? src_kernel_win_0_val_1_2_lo_reg_3605: temp_0_i_i_i_057_i_i_1_0_0_2_reg_3610);
assign temp_0_i_i_i_057_i_i_1_0_2_1_fu_2572_p3 = ((tmp_115_0_2_1_fu_2567_p2)? ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10: temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3);
assign temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3 = ((tmp_115_0_2_reg_3702)? src_kernel_win_0_val_0_2_lo_reg_3692: temp_0_i_i_i_057_i_i_1_0_1_2_reg_3697);
assign temp_0_i_i_i_057_i_i_1_1_0_1_fu_2151_p3 = ((tmp_115_1_0_1_fu_2145_p2)? src_kernel_win_1_val_2_1_fu_274: src_kernel_win_1_val_2_2_fu_290);
assign temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3 = ((tmp_115_1_0_2_fu_2382_p2)? src_kernel_win_1_val_2_1_fu_274: temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581);
assign temp_0_i_i_i_057_i_i_1_1_1_1_fu_2469_p3 = ((tmp_115_1_1_1_fu_2464_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8: temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3);
assign temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3 = ((tmp_115_1_1_2_fu_2515_p2)? ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9: temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680);
assign temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3 = ((tmp_115_1_1_reg_3642)? src_kernel_win_1_val_1_2_lo_reg_3632: temp_0_i_i_i_057_i_i_1_1_0_2_reg_3637);
assign temp_0_i_i_i_057_i_i_1_1_2_1_fu_2589_p3 = ((tmp_115_1_2_1_fu_2584_p2)? ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10: temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3);
assign temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3 = ((tmp_115_1_2_reg_3717)? src_kernel_win_1_val_0_2_lo_reg_3707: temp_0_i_i_i_057_i_i_1_1_1_2_reg_3712);
assign temp_0_i_i_i_057_i_i_1_2_0_1_fu_2317_p3 = ((tmp_115_2_0_1_fu_2311_p2)? src_kernel_win_2_val_2_1_fu_310: src_kernel_win_2_val_2_2_fu_326);
assign temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3 = ((tmp_115_2_0_2_fu_2412_p2)? src_kernel_win_2_val_2_1_fu_310: temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587);
assign temp_0_i_i_i_057_i_i_1_2_1_1_fu_2486_p3 = ((tmp_115_2_1_1_fu_2481_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8: temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3);
assign temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3 = ((tmp_115_2_1_2_fu_2534_p2)? ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9: temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686);
assign temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3 = ((tmp_115_2_1_reg_3669)? src_kernel_win_2_val_1_2_lo_reg_3659: temp_0_i_i_i_057_i_i_1_2_0_2_reg_3664);
assign temp_0_i_i_i_057_i_i_1_2_2_1_fu_2606_p3 = ((tmp_115_2_2_1_fu_2601_p2)? ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10: temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3);
assign temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3 = ((tmp_115_2_2_reg_3732)? src_kernel_win_2_val_0_2_lo_reg_3722: temp_0_i_i_i_057_i_i_1_2_1_2_reg_3727);
assign tmp_100_fu_1613_p1 = grp_image_filter_borderInterpolate_fu_756_ap_return[1:0];
assign tmp_101_fu_1264_p1 = grp_image_filter_borderInterpolate_fu_684_ap_return[1:0];
assign tmp_102_fu_1236_p1 = col_assign_s_fu_1231_p2[1:0];
assign tmp_103_fu_1626_p3 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[ap_const_lv32_E];
assign tmp_104_fu_1633_p1 = ap_reg_ppstg_x_2_reg_3317_pp0_it5[1:0];
assign tmp_105_fu_1252_p1 = col_assign_4_2_fu_1248_p2[1:0];
assign tmp_115_0_0_1_fu_1979_p2 = (src_kernel_win_0_val_2_1_fu_238 < src_kernel_win_0_val_2_2_fu_254? 1'b1: 1'b0);
assign tmp_115_0_0_2_fu_2352_p2 = (src_kernel_win_0_val_2_1_fu_238 < temp_0_i_i_i_057_i_i_1_0_0_1_reg_3575? 1'b1: 1'b0);
assign tmp_115_0_1_1_fu_2447_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_12_reg_3540_pp0_it8 < temp_0_i_i_i_057_i_i_1_0_1_fu_2442_p3? 1'b1: 1'b0);
assign tmp_115_0_1_2_fu_2496_p2 = (ap_reg_ppstg_src_kernel_win_0_val_1_1_lo_reg_3599_pp0_it9 < temp_0_i_i_i_057_i_i_1_0_1_1_reg_3674? 1'b1: 1'b0);
assign tmp_115_0_1_fu_2364_p2 = (src_kernel_win_0_val_1_2_fu_246 < temp_0_i_i_i_057_i_i_1_0_0_2_fu_2357_p3? 1'b1: 1'b0);
assign tmp_115_0_2_1_fu_2567_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_12_reg_3533_pp0_it10 < temp_0_i_i_i_057_i_i_1_0_2_fu_2562_p3? 1'b1: 1'b0);
assign tmp_115_0_2_2_fu_2613_p2 = (ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_3593_pp0_it11 < temp_0_i_i_i_057_i_i_1_0_2_1_reg_3737? 1'b1: 1'b0);
assign tmp_115_0_2_fu_2506_p2 = (src_kernel_win_0_val_0_2_fu_230 < temp_0_i_i_i_057_i_i_1_0_1_2_fu_2500_p3? 1'b1: 1'b0);
assign tmp_115_1_0_1_fu_2145_p2 = (src_kernel_win_1_val_2_1_fu_274 < src_kernel_win_1_val_2_2_fu_290? 1'b1: 1'b0);
assign tmp_115_1_0_2_fu_2382_p2 = (src_kernel_win_1_val_2_1_fu_274 < temp_0_i_i_i_057_i_i_1_1_0_1_reg_3581? 1'b1: 1'b0);
assign tmp_115_1_1_1_fu_2464_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_12_reg_3554_pp0_it8 < temp_0_i_i_i_057_i_i_1_1_1_fu_2459_p3? 1'b1: 1'b0);
assign tmp_115_1_1_2_fu_2515_p2 = (ap_reg_ppstg_src_kernel_win_1_val_1_1_lo_reg_3626_pp0_it9 < temp_0_i_i_i_057_i_i_1_1_1_1_reg_3680? 1'b1: 1'b0);
assign tmp_115_1_1_fu_2394_p2 = (src_kernel_win_1_val_1_2_fu_282 < temp_0_i_i_i_057_i_i_1_1_0_2_fu_2387_p3? 1'b1: 1'b0);
assign tmp_115_1_2_1_fu_2584_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_12_reg_3547_pp0_it10 < temp_0_i_i_i_057_i_i_1_1_2_fu_2579_p3? 1'b1: 1'b0);
assign tmp_115_1_2_2_fu_2624_p2 = (ap_reg_ppstg_src_kernel_win_1_val_0_1_lo_reg_3620_pp0_it11 < temp_0_i_i_i_057_i_i_1_1_2_1_reg_3743? 1'b1: 1'b0);
assign tmp_115_1_2_fu_2525_p2 = (src_kernel_win_1_val_0_2_fu_266 < temp_0_i_i_i_057_i_i_1_1_1_2_fu_2519_p3? 1'b1: 1'b0);
assign tmp_115_2_0_1_fu_2311_p2 = (src_kernel_win_2_val_2_1_fu_310 < src_kernel_win_2_val_2_2_fu_326? 1'b1: 1'b0);
assign tmp_115_2_0_2_fu_2412_p2 = (src_kernel_win_2_val_2_1_fu_310 < temp_0_i_i_i_057_i_i_1_2_0_1_reg_3587? 1'b1: 1'b0);
assign tmp_115_2_1_1_fu_2481_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_12_reg_3568_pp0_it8 < temp_0_i_i_i_057_i_i_1_2_1_fu_2476_p3? 1'b1: 1'b0);
assign tmp_115_2_1_2_fu_2534_p2 = (ap_reg_ppstg_src_kernel_win_2_val_1_1_lo_reg_3653_pp0_it9 < temp_0_i_i_i_057_i_i_1_2_1_1_reg_3686? 1'b1: 1'b0);
assign tmp_115_2_1_fu_2424_p2 = (src_kernel_win_2_val_1_2_fu_318 < temp_0_i_i_i_057_i_i_1_2_0_2_fu_2417_p3? 1'b1: 1'b0);
assign tmp_115_2_2_1_fu_2601_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_12_reg_3561_pp0_it10 < temp_0_i_i_i_057_i_i_1_2_2_fu_2596_p3? 1'b1: 1'b0);
assign tmp_115_2_2_2_fu_2635_p2 = (ap_reg_ppstg_src_kernel_win_2_val_0_1_lo_reg_3647_pp0_it11 < temp_0_i_i_i_057_i_i_1_2_2_1_reg_3749? 1'b1: 1'b0);
assign tmp_115_2_2_fu_2544_p2 = (src_kernel_win_2_val_0_2_fu_302 < temp_0_i_i_i_057_i_i_1_2_1_2_fu_2538_p3? 1'b1: 1'b0);
assign tmp_16_fu_896_p2 = (tmp_15_reg_612 + ap_const_lv2_1);
assign tmp_19_fu_908_p2 = (tmp_18_reg_623 + ap_const_lv2_1);
assign tmp_20_fu_914_p2 = (tmp_18_reg_623 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_22_fu_920_p2 = (tmp_21_reg_634 + ap_const_lv2_1);
assign tmp_23_fu_926_p2 = (tmp_21_reg_634 == ap_const_lv2_2? 1'b1: 1'b0);
assign tmp_27_fu_942_p2 = ($signed(tmp_72_reg_2751) + $signed(ap_const_lv11_7FD));
assign tmp_28_cast_fu_947_p1 = tmp_27_fu_942_p2;
assign tmp_28_fu_977_p2 = (p_012_0_i_i_reg_645 < heightloop_reg_3051? 1'b1: 1'b0);
assign tmp_29_cast_cast3_fu_973_p1 = p_012_0_i_i_reg_645;
assign tmp_30_fu_988_p2 = (p_012_0_i_i_reg_645 > ap_const_lv11_4? 1'b1: 1'b0);
assign tmp_31_fu_1057_p2 = ($signed(ImagLoc_y_reg_3118) < $signed(12'b111111111111)? 1'b1: 1'b0);
assign tmp_32_fu_1035_p3 = ((tmp_58_2_fu_1016_p2)? ap_const_lv2_2: tmp_74_reg_3094);
assign tmp_33_cast_fu_1077_p1 = p_025_0_i_i_reg_656;
assign tmp_33_fu_1081_p2 = (p_025_0_i_i_reg_656 < widthloop_reg_3056? 1'b1: 1'b0);
assign tmp_35_fu_1287_p1 = $unsigned(x_ext_fu_1284_p1);
assign tmp_36_fu_1127_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_37_fu_1133_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_38_fu_1152_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_56_1_fu_1294_p1 = $signed(x_1_reg_3305);
assign tmp_56_2_fu_1300_p1 = $signed(x_2_reg_3317);
assign tmp_58_2_fu_1016_p2 = ($signed(ImagLoc_y_fu_994_p2) < $signed(ref_cast_reg_3089)? 1'b1: 1'b0);
assign tmp_61_1_fu_1162_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_61_2_fu_1201_p2 = (p_025_0_i_i_reg_656 != ap_const_lv11_0? 1'b1: 1'b0);
assign tmp_63_1_fu_1168_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_63_2_fu_1207_p2 = ($signed(ImagLoc_x_cast2_fu_1123_p1) < $signed(cols_assign_cast1_reg_2757)? 1'b1: 1'b0);
assign tmp_66_1_fu_1187_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_66_2_fu_1226_p2 = ($signed(ImagLoc_x_fu_1113_p2) < $signed(tmp_28_cast_reg_3061)? 1'b1: 1'b0);
assign tmp_72_fu_888_p1 = p_src_cols_V_read[10:0];
assign tmp_73_fu_956_p1 = p_neg226_i_i_fu_951_p2[1:0];
assign tmp_74_fu_969_p1 = ref_fu_960_p2[1:0];
assign tmp_75_fu_1000_p4 = {{ImagLoc_y_fu_994_p2[ap_const_lv32_B : ap_const_lv32_1]}};
assign tmp_78_fu_1049_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_79_fu_1053_p1 = p_i_i_fu_1042_p3[1:0];
assign tmp_80_fu_1092_p4 = {{p_025_0_i_i_reg_656[ap_const_lv32_A : ap_const_lv32_1]}};
assign tmp_82_fu_1119_p1 = ImagLoc_x_fu_1113_p2[1:0];
assign tmp_83_fu_1268_p1 = grp_image_filter_borderInterpolate_fu_692_ap_return[1:0];
assign tmp_85_fu_1311_p1 = grp_image_filter_borderInterpolate_fu_716_ap_return[1:0];
assign tmp_86_fu_1315_p1 = grp_image_filter_borderInterpolate_fu_724_ap_return[1:0];
assign tmp_87_fu_1256_p1 = grp_image_filter_borderInterpolate_fu_668_ap_return[1:0];
assign tmp_90_fu_1423_p1 = grp_image_filter_borderInterpolate_fu_732_ap_return[1:0];
assign tmp_91_fu_1427_p1 = grp_image_filter_borderInterpolate_fu_740_ap_return[1:0];
assign tmp_92_fu_1260_p1 = grp_image_filter_borderInterpolate_fu_676_ap_return[1:0];
assign tmp_93_fu_1197_p1 = col_assign_1_fu_1192_p2[1:0];
assign tmp_94_fu_1440_p3 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[ap_const_lv32_E];
assign tmp_95_fu_1447_p1 = ap_reg_ppstg_x_1_reg_3305_pp0_it5[1:0];
assign tmp_96_fu_1244_p1 = col_assign_4_1_fu_1240_p2[1:0];
assign tmp_99_1_fu_1516_p1 = $unsigned(x_1_ext_fu_1415_p1);
assign tmp_99_2_fu_1702_p1 = $unsigned(x_2_ext_fu_1601_p1);
assign tmp_99_fu_1609_p1 = grp_image_filter_borderInterpolate_fu_748_ap_return[1:0];
assign tmp_fu_884_p1 = p_src_rows_V_read[10:0];
assign tmp_s_fu_902_p2 = (tmp_15_reg_612 == ap_const_lv2_2? 1'b1: 1'b0);
assign widthloop_fu_937_p2 = (tmp_72_reg_2751 + ap_const_lv11_2);
assign x_1_ext_fu_1415_p1 = $signed(ap_reg_ppstg_x_1_reg_3305_pp0_it5);
assign x_2_ext_fu_1601_p1 = $signed(ap_reg_ppstg_x_2_reg_3317_pp0_it5);
assign x_ext_fu_1284_p1 = $signed(x_reg_3291);
assign y_1_2_1_fu_1067_p2 = ($signed(tmp_29_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFA));
assign y_1_2_fu_1062_p2 = ($signed(tmp_29_cast_cast3_reg_3099) + $signed(ap_const_lv12_FFB));
always @ (posedge ap_clk)
begin
    cols_assign_cast1_reg_2757[12] <= 1'b0;
    tmp_28_cast_reg_3061[11] <= 1'b0;
    ref_cast_reg_3089[11] <= 1'b0;
    tmp_29_cast_cast3_reg_3099[11] <= 1'b0;
end



endmodule //image_filter_Erode_32_32_1080_1920_s

