`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11.06.2017 19:09:30
// Design Name: 
// Module Name: Display
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module display(
    input clk_display,
    input [31:0] num,
    input [7:0] puntos,
    output [7:0] segmentos,
    output reg [7:0] anodos
    );
    
    reg [2:0] counter;
    reg [3:0] X;
    
    always @(posedge clk_display) begin                   
                 counter <= counter+3'b1;         
    end
    
     always @(counter) begin                 
              case (counter)
                   4'd0: anodos= 8'b01111111;
                   4'd1: anodos= 8'b10111111;
                   4'd2: anodos= 8'b11011111;
                   4'd3: anodos= 8'b11101111;
                   4'd4: anodos= 8'b11110111;
                   4'd5: anodos= 8'b11111011;
                   4'd6: anodos= 8'b11111101;
                   4'd7: anodos= 8'b11111110;
                   default: anodos=8'b11111111;
           endcase
     end
     always @(*) begin
                     case(anodos)
                     8'b01111111: X=num[31:28];
                     8'b10111111: X=num[27:24]; 
                     8'b11011111: X=num[23:20];
                     8'b11101111: X=num[19:16];
                     8'b11110111: X=num[15:12];
                     8'b11111011: X=num[11:8];
                     8'b11111101: X=num[7:4];
                     8'b11111110: X=num[3:0];
                     default: X=4'b0 ;
                    endcase
               end
      Dec_4b_seg Dec(
      . NUM(X),
      . CATODOS({segmentos})
      );
endmodule