// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date        : Thu Oct 26 22:45:43 2017
// Host        : Juice-Laptop running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.v
// Design      : RAT_ControlUnit_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "RAT_ControlUnit_0_0,ControlUnit,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ControlUnit,Vivado 2016.4" *) 
(* NotValidForBitStream *)
module RAT_ControlUnit_0_0
   (CLK,
    C,
    Z,
    INT,
    RST,
    OPCODE_HI_5,
    OPCODE_LO_2,
    PC_LD,
    PC_INC,
    PC_RESET,
    PC_OE,
    PC_MUX_SEL,
    SP_LD,
    SP_MUX_SEL,
    SP_RESET,
    RF_WR,
    RF_WR_SEL,
    RF_OE,
    REG_IMMED_SEL,
    ALU_SEL,
    ALU_OPY_SEL,
    SCR_WR,
    SCR_OE,
    SCR_ADDR_SEL,
    C_FLAG_SEL,
    C_FLAG_LD,
    C_FLAG_SET,
    C_FLAG_CLR,
    SHAD_C_LD,
    Z_FLAG_SEL,
    Z_FLAG_LD,
    Z_FLAG_SET,
    Z_FLAG_CLR,
    SHAD_Z_LD,
    I_FLAG_SET,
    I_FLAG_CLR,
    IO_OE);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
  input C;
  input Z;
  input INT;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 RST RST" *) input RST;
  input [4:0]OPCODE_HI_5;
  input [1:0]OPCODE_LO_2;
  output PC_LD;
  output PC_INC;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 PC_RESET RST" *) output PC_RESET;
  output PC_OE;
  output [1:0]PC_MUX_SEL;
  output SP_LD;
  output [1:0]SP_MUX_SEL;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 SP_RESET RST" *) output SP_RESET;
  output RF_WR;
  output [1:0]RF_WR_SEL;
  output RF_OE;
  output REG_IMMED_SEL;
  output [3:0]ALU_SEL;
  output ALU_OPY_SEL;
  output SCR_WR;
  output SCR_OE;
  output [1:0]SCR_ADDR_SEL;
  output C_FLAG_SEL;
  output C_FLAG_LD;
  output C_FLAG_SET;
  output C_FLAG_CLR;
  output SHAD_C_LD;
  output Z_FLAG_SEL;
  output Z_FLAG_LD;
  output Z_FLAG_SET;
  output Z_FLAG_CLR;
  output SHAD_Z_LD;
  output I_FLAG_SET;
  output I_FLAG_CLR;
  output IO_OE;

  wire \<const0> ;
  wire ALU_OPY_SEL;
  wire [3:0]\^ALU_SEL ;
  wire CLK;
  wire INT;
  wire IO_OE;
  wire IO_OE_INST_0_i_1_n_0;
  wire [4:0]OPCODE_HI_5;
  wire [1:0]OPCODE_LO_2;
  wire PC_INC;
  wire PC_LD;
  wire PC_LD_INST_0_i_1_n_0;
  wire PC_OE;
  wire PC_RESET;
  wire RF_OE;
  wire RF_OE_INST_0_i_1_n_0;
  wire RF_WR;
  wire [1:1]\^RF_WR_SEL ;
  wire RST;

  assign ALU_SEL[3:2] = \^ALU_SEL [3:2];
  assign ALU_SEL[1] = \^ALU_SEL [2];
  assign ALU_SEL[0] = \^ALU_SEL [0];
  assign C_FLAG_CLR = \<const0> ;
  assign C_FLAG_LD = \^ALU_SEL [0];
  assign C_FLAG_SEL = \<const0> ;
  assign C_FLAG_SET = \<const0> ;
  assign I_FLAG_CLR = PC_OE;
  assign I_FLAG_SET = \<const0> ;
  assign PC_MUX_SEL[1] = PC_OE;
  assign PC_MUX_SEL[0] = \<const0> ;
  assign REG_IMMED_SEL = \<const0> ;
  assign RF_WR_SEL[1] = \^RF_WR_SEL [1];
  assign RF_WR_SEL[0] = \^RF_WR_SEL [1];
  assign SCR_ADDR_SEL[1] = PC_OE;
  assign SCR_ADDR_SEL[0] = PC_OE;
  assign SCR_OE = \<const0> ;
  assign SCR_WR = PC_OE;
  assign SHAD_C_LD = \<const0> ;
  assign SHAD_Z_LD = \<const0> ;
  assign SP_LD = PC_OE;
  assign SP_MUX_SEL[1] = PC_OE;
  assign SP_MUX_SEL[0] = \<const0> ;
  assign SP_RESET = PC_RESET;
  assign Z_FLAG_CLR = \<const0> ;
  assign Z_FLAG_LD = \^ALU_SEL [0];
  assign Z_FLAG_SEL = \<const0> ;
  assign Z_FLAG_SET = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h8)) 
    IO_OE_INST_0_i_1
       (.I0(OPCODE_HI_5[1]),
        .I1(OPCODE_HI_5[4]),
        .O(IO_OE_INST_0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    PC_LD_INST_0_i_1
       (.I0(OPCODE_HI_5[3]),
        .I1(OPCODE_HI_5[0]),
        .I2(OPCODE_HI_5[4]),
        .I3(OPCODE_HI_5[2]),
        .O(PC_LD_INST_0_i_1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    RF_OE_INST_0_i_1
       (.I0(OPCODE_LO_2[1]),
        .I1(OPCODE_LO_2[0]),
        .O(RF_OE_INST_0_i_1_n_0));
  RAT_ControlUnit_0_0_ControlUnit U0
       (.ALU_OPY_SEL(ALU_OPY_SEL),
        .ALU_SEL({\^ALU_SEL [3:2],\^ALU_SEL [0]}),
        .CLK(CLK),
        .INT(INT),
        .IO_OE(IO_OE),
        .OPCODE_HI_5(OPCODE_HI_5),
        .OPCODE_HI_5_2__s_port_(PC_LD_INST_0_i_1_n_0),
        .\OPCODE_HI_5_4__s_port_] (IO_OE_INST_0_i_1_n_0),
        .OPCODE_LO_2(OPCODE_LO_2),
        .\OPCODE_LO_2_0__s_port_] (RF_OE_INST_0_i_1_n_0),
        .PC_INC(PC_INC),
        .PC_LD(PC_LD),
        .PC_OE(PC_OE),
        .PC_RESET(PC_RESET),
        .RF_OE(RF_OE),
        .RF_WR(RF_WR),
        .RF_WR_SEL(\^RF_WR_SEL ),
        .RST(RST));
endmodule

(* ORIG_REF_NAME = "ControlUnit" *) 
module RAT_ControlUnit_0_0_ControlUnit
   (ALU_OPY_SEL,
    PC_RESET,
    PC_OE,
    IO_OE,
    RF_OE,
    RF_WR_SEL,
    RF_WR,
    ALU_SEL,
    PC_LD,
    PC_INC,
    \OPCODE_HI_5_4__s_port_] ,
    OPCODE_HI_5,
    \OPCODE_LO_2_0__s_port_] ,
    OPCODE_LO_2,
    INT,
    OPCODE_HI_5_2__s_port_,
    CLK,
    RST);
  output ALU_OPY_SEL;
  output PC_RESET;
  output PC_OE;
  output IO_OE;
  output RF_OE;
  output [0:0]RF_WR_SEL;
  output RF_WR;
  output [2:0]ALU_SEL;
  output PC_LD;
  output PC_INC;
  input \OPCODE_HI_5_4__s_port_] ;
  input [4:0]OPCODE_HI_5;
  input \OPCODE_LO_2_0__s_port_] ;
  input [1:0]OPCODE_LO_2;
  input INT;
  input OPCODE_HI_5_2__s_port_;
  input CLK;
  input RST;

  wire ALU_OPY_SEL;
  wire ALU_OPY_SEL_reg_i_1_n_0;
  wire ALU_OPY_SEL_reg_i_2_n_0;
  wire [2:0]ALU_SEL;
  wire CLK;
  wire INT;
  wire IO_OE;
  wire [1:0]NS;
  wire [4:0]OPCODE_HI_5;
  wire OPCODE_HI_5_2__s_net_1;
  wire OPCODE_HI_5_4__s_net_1;
  wire [1:0]OPCODE_LO_2;
  wire OPCODE_LO_2_0__s_net_1;
  wire PC_INC;
  wire PC_LD;
  wire PC_OE;
  wire PC_RESET;
  wire [1:0]PS;
  wire RF_OE;
  wire RF_WR;
  wire RF_WR_INST_0_i_1_n_0;
  wire RF_WR_INST_0_i_2_n_0;
  wire [0:0]RF_WR_SEL;
  wire \RF_WR_SEL[0]_INST_0_i_1_n_0 ;
  wire RST;

  assign OPCODE_HI_5_2__s_net_1 = OPCODE_HI_5_2__s_port_;
  assign OPCODE_HI_5_4__s_net_1 = \OPCODE_HI_5_4__s_port_] ;
  assign OPCODE_LO_2_0__s_net_1 = \OPCODE_LO_2_0__s_port_] ;
  (* XILINX_LEGACY_PRIM = "LD" *) 
  LDCE #(
    .INIT(1'b0)) 
    ALU_OPY_SEL_reg
       (.CLR(1'b0),
        .D(ALU_OPY_SEL_reg_i_1_n_0),
        .G(ALU_OPY_SEL_reg_i_2_n_0),
        .GE(1'b1),
        .Q(ALU_OPY_SEL));
  LUT5 #(
    .INIT(32'h40000040)) 
    ALU_OPY_SEL_reg_i_1
       (.I0(OPCODE_HI_5[2]),
        .I1(OPCODE_HI_5[1]),
        .I2(OPCODE_HI_5[4]),
        .I3(OPCODE_HI_5[0]),
        .I4(OPCODE_HI_5[3]),
        .O(ALU_OPY_SEL_reg_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h2)) 
    ALU_OPY_SEL_reg_i_2
       (.I0(PS[1]),
        .I1(PS[0]),
        .O(ALU_OPY_SEL_reg_i_2_n_0));
  LUT6 #(
    .INIT(64'hFF000820AA000820)) 
    \ALU_SEL[1]_INST_0 
       (.I0(RF_WR_INST_0_i_1_n_0),
        .I1(OPCODE_LO_2[0]),
        .I2(OPCODE_LO_2[1]),
        .I3(OPCODE_HI_5[1]),
        .I4(OPCODE_HI_5[4]),
        .I5(RF_WR_INST_0_i_2_n_0),
        .O(ALU_SEL[1]));
  LUT6 #(
    .INIT(64'hAAAA0C0000000000)) 
    \ALU_SEL[3]_INST_0 
       (.I0(RF_WR_INST_0_i_2_n_0),
        .I1(RF_WR_INST_0_i_1_n_0),
        .I2(OPCODE_LO_2[1]),
        .I3(OPCODE_LO_2[0]),
        .I4(OPCODE_HI_5[4]),
        .I5(OPCODE_HI_5[1]),
        .O(ALU_SEL[2]));
  LUT6 #(
    .INIT(64'h0000000000080000)) 
    IO_OE_INST_0
       (.I0(OPCODE_HI_5_4__s_net_1),
        .I1(OPCODE_HI_5[3]),
        .I2(OPCODE_HI_5[0]),
        .I3(OPCODE_HI_5[2]),
        .I4(PS[1]),
        .I5(PS[0]),
        .O(IO_OE));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h8)) 
    I_FLAG_CLR_INST_0
       (.I0(PS[0]),
        .I1(PS[1]),
        .O(PC_OE));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h2)) 
    PC_INC_INST_0
       (.I0(PS[0]),
        .I1(PS[1]),
        .O(PC_INC));
  LUT6 #(
    .INIT(64'hFFFF00000002FFFF)) 
    PC_LD_INST_0
       (.I0(OPCODE_HI_5_2__s_net_1),
        .I1(OPCODE_LO_2[0]),
        .I2(OPCODE_LO_2[1]),
        .I3(OPCODE_HI_5[1]),
        .I4(PS[1]),
        .I5(PS[0]),
        .O(PC_LD));
  LUT2 #(
    .INIT(4'hB)) 
    \PS[0]_i_1 
       (.I0(PS[1]),
        .I1(PS[0]),
        .O(NS[0]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h2C)) 
    \PS[1]_i_1 
       (.I0(INT),
        .I1(PS[0]),
        .I2(PS[1]),
        .O(NS[1]));
  FDCE \PS_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .CLR(RST),
        .D(NS[0]),
        .Q(PS[0]));
  FDCE \PS_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .CLR(RST),
        .D(NS[1]),
        .Q(PS[1]));
  LUT6 #(
    .INIT(64'h3030000000001000)) 
    RF_OE_INST_0
       (.I0(OPCODE_HI_5[3]),
        .I1(OPCODE_HI_5[0]),
        .I2(\RF_WR_SEL[0]_INST_0_i_1_n_0 ),
        .I3(OPCODE_LO_2_0__s_net_1),
        .I4(OPCODE_HI_5[4]),
        .I5(OPCODE_HI_5[1]),
        .O(RF_OE));
  LUT6 #(
    .INIT(64'hFFFF028088880280)) 
    RF_WR_INST_0
       (.I0(RF_WR_INST_0_i_1_n_0),
        .I1(OPCODE_HI_5[1]),
        .I2(OPCODE_LO_2[0]),
        .I3(OPCODE_LO_2[1]),
        .I4(OPCODE_HI_5[4]),
        .I5(RF_WR_INST_0_i_2_n_0),
        .O(RF_WR));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    RF_WR_INST_0_i_1
       (.I0(OPCODE_HI_5[3]),
        .I1(OPCODE_HI_5[0]),
        .I2(OPCODE_HI_5[2]),
        .I3(PS[1]),
        .I4(PS[0]),
        .O(RF_WR_INST_0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    RF_WR_INST_0_i_2
       (.I0(OPCODE_HI_5[3]),
        .I1(OPCODE_HI_5[0]),
        .I2(OPCODE_HI_5[2]),
        .I3(PS[1]),
        .I4(PS[0]),
        .O(RF_WR_INST_0_i_2_n_0));
  LUT5 #(
    .INIT(32'h40000000)) 
    \RF_WR_SEL[0]_INST_0 
       (.I0(OPCODE_HI_5[1]),
        .I1(OPCODE_HI_5[4]),
        .I2(\RF_WR_SEL[0]_INST_0_i_1_n_0 ),
        .I3(OPCODE_HI_5[0]),
        .I4(OPCODE_HI_5[3]),
        .O(RF_WR_SEL));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \RF_WR_SEL[0]_INST_0_i_1 
       (.I0(PS[0]),
        .I1(PS[1]),
        .I2(OPCODE_HI_5[2]),
        .O(\RF_WR_SEL[0]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h1)) 
    SP_RESET_INST_0
       (.I0(PS[0]),
        .I1(PS[1]),
        .O(PC_RESET));
  LUT5 #(
    .INIT(32'h80828080)) 
    Z_FLAG_LD_INST_0
       (.I0(RF_WR_INST_0_i_1_n_0),
        .I1(OPCODE_HI_5[1]),
        .I2(OPCODE_HI_5[4]),
        .I3(OPCODE_LO_2[0]),
        .I4(OPCODE_LO_2[1]),
        .O(ALU_SEL[0]));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
