// ghrd_10as066n2_avlmm_pr_freeze_bridge_1_altera_avlmm_pr_freeze_bridge_171_yvsimhi.v

// This file was auto-generated from altera_avlmm_pr_freeze_bridge_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 17.1 240

`timescale 1 ps / 1 ps
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1_altera_avlmm_pr_freeze_bridge_171_yvsimhi #(
		parameter ENABLE_FREEZE_FROM_PR_REGION = 0,
		parameter ENABLE_TRAFFIC_TRACKING      = 0
	) (
		input  wire        clock,                               //            clock.clk
		input  wire        freeze_conduit_freeze,               //   freeze_conduit.freeze
		output wire        freeze_conduit_illegal_request,      //                 .illegal_request
		input  wire        mst_bridge_to_pr_read,               // mst_bridge_to_pr.read
		output wire        mst_bridge_to_pr_waitrequest,        //                 .waitrequest
		input  wire        mst_bridge_to_pr_write,              //                 .write
		input  wire [31:0] mst_bridge_to_pr_address,            //                 .address
		input  wire [3:0]  mst_bridge_to_pr_byteenable,         //                 .byteenable
		input  wire [31:0] mst_bridge_to_pr_writedata,          //                 .writedata
		output wire [31:0] mst_bridge_to_pr_readdata,           //                 .readdata
		input  wire [2:0]  mst_bridge_to_pr_burstcount,         //                 .burstcount
		output wire        mst_bridge_to_pr_readdatavalid,      //                 .readdatavalid
		input  wire        mst_bridge_to_pr_beginbursttransfer, //                 .beginbursttransfer
		input  wire        mst_bridge_to_pr_debugaccess,        //                 .debugaccess
		output wire [1:0]  mst_bridge_to_pr_response,           //                 .response
		input  wire        mst_bridge_to_pr_lock,               //                 .lock
		output wire        mst_bridge_to_pr_writeresponsevalid, //                 .writeresponsevalid
		output wire        mst_bridge_to_sr_read,               // mst_bridge_to_sr.read
		input  wire        mst_bridge_to_sr_waitrequest,        //                 .waitrequest
		output wire        mst_bridge_to_sr_write,              //                 .write
		output wire [31:0] mst_bridge_to_sr_address,            //                 .address
		output wire [3:0]  mst_bridge_to_sr_byteenable,         //                 .byteenable
		output wire [31:0] mst_bridge_to_sr_writedata,          //                 .writedata
		input  wire [31:0] mst_bridge_to_sr_readdata,           //                 .readdata
		output wire [2:0]  mst_bridge_to_sr_burstcount,         //                 .burstcount
		input  wire        mst_bridge_to_sr_readdatavalid,      //                 .readdatavalid
		output wire        mst_bridge_to_sr_beginbursttransfer, //                 .beginbursttransfer
		output wire        mst_bridge_to_sr_debugaccess,        //                 .debugaccess
		input  wire [1:0]  mst_bridge_to_sr_response,           //                 .response
		output wire        mst_bridge_to_sr_lock,               //                 .lock
		input  wire        mst_bridge_to_sr_writeresponsevalid, //                 .writeresponsevalid
		input  wire        reset_n                              //          reset_n.reset_n
	);

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (ENABLE_FREEZE_FROM_PR_REGION != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_freeze_from_pr_region_check ( .error(1'b1) );
		end
		if (ENABLE_TRAFFIC_TRACKING != 0)
		begin
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
			instantiated_with_wrong_parameters_error_see_comment_above
					enable_traffic_tracking_check ( .error(1'b1) );
		end
	endgenerate

	altera_avlmm_mst_freeze_bridge #(
		.ENABLE_FREEZE_FROM_PR_REGION (0),
		.ENABLE_TRAFFIC_TRACKING      (0),
		.USE_BURSTCOUNT               (1),
		.USE_READ_WAIT_TIME           (0),
		.USE_WRITE_WAIT_TIME          (0),
		.MST_BRIDGE_ADDR_WIDTH        (32),
		.MST_BRIDGE_BYTEEN_WIDTH      (4),
		.MST_BRIDGE_BURSTCOUNT_WIDTH  (3),
		.MST_BRIDGE_RWT_WIDTH         (1),
		.MST_BRIDGE_WWT_WIDTH         (1),
		.MST_BRIDGE_WRDATA_WIDTH      (32),
		.MST_BRIDGE_RDDATA_WIDTH      (32),
		.MST_BRIDGE_READ_WAIT_TIME    (1),
		.MST_BRIDGE_WRITE_WAIT_TIME   (0)
	) avlmm_mst_freeze_bridge (
		.clk                                 (clock),                               //   input,   width = 1,       clock_sink.clk
		.reset_n                             (reset_n),                             //   input,   width = 1,            reset.reset_n
		.freeze                              (freeze_conduit_freeze),               //   input,   width = 1,   freeze_conduit.freeze
		.illegal_request                     (freeze_conduit_illegal_request),      //  output,   width = 1,                 .illegal_request
		.mst_bridge_to_pr_read               (mst_bridge_to_pr_read),               //   input,   width = 1, mst_bridge_to_pr.read
		.mst_bridge_to_pr_waitrequest        (mst_bridge_to_pr_waitrequest),        //  output,   width = 1,                 .waitrequest
		.mst_bridge_to_pr_write              (mst_bridge_to_pr_write),              //   input,   width = 1,                 .write
		.mst_bridge_to_pr_addr               (mst_bridge_to_pr_address),            //   input,  width = 32,                 .address
		.mst_bridge_to_pr_byteenable         (mst_bridge_to_pr_byteenable),         //   input,   width = 4,                 .byteenable
		.mst_bridge_to_pr_wrdata             (mst_bridge_to_pr_writedata),          //   input,  width = 32,                 .writedata
		.mst_bridge_to_pr_rddata             (mst_bridge_to_pr_readdata),           //  output,  width = 32,                 .readdata
		.mst_bridge_to_pr_burstcount         (mst_bridge_to_pr_burstcount),         //   input,   width = 3,                 .burstcount
		.mst_bridge_to_pr_rddata_valid       (mst_bridge_to_pr_readdatavalid),      //  output,   width = 1,                 .readdatavalid
		.mst_bridge_to_pr_beginbursttransfer (mst_bridge_to_pr_beginbursttransfer), //   input,   width = 1,                 .beginbursttransfer
		.mst_bridge_to_pr_debugaccess        (mst_bridge_to_pr_debugaccess),        //   input,   width = 1,                 .debugaccess
		.mst_bridge_to_pr_response           (mst_bridge_to_pr_response),           //  output,   width = 2,                 .response
		.mst_bridge_to_pr_lock               (mst_bridge_to_pr_lock),               //   input,   width = 1,                 .lock
		.mst_bridge_to_pr_writeresponsevalid (mst_bridge_to_pr_writeresponsevalid), //  output,   width = 1,                 .writeresponsevalid
		.mst_bridge_to_sr_read               (mst_bridge_to_sr_read),               //  output,   width = 1, mst_bridge_to_sr.read
		.mst_bridge_to_sr_waitrequest        (mst_bridge_to_sr_waitrequest),        //   input,   width = 1,                 .waitrequest
		.mst_bridge_to_sr_write              (mst_bridge_to_sr_write),              //  output,   width = 1,                 .write
		.mst_bridge_to_sr_addr               (mst_bridge_to_sr_address),            //  output,  width = 32,                 .address
		.mst_bridge_to_sr_byteenable         (mst_bridge_to_sr_byteenable),         //  output,   width = 4,                 .byteenable
		.mst_bridge_to_sr_wrdata             (mst_bridge_to_sr_writedata),          //  output,  width = 32,                 .writedata
		.mst_bridge_to_sr_rddata             (mst_bridge_to_sr_readdata),           //   input,  width = 32,                 .readdata
		.mst_bridge_to_sr_burstcount         (mst_bridge_to_sr_burstcount),         //  output,   width = 3,                 .burstcount
		.mst_bridge_to_sr_rddata_valid       (mst_bridge_to_sr_readdatavalid),      //   input,   width = 1,                 .readdatavalid
		.mst_bridge_to_sr_beginbursttransfer (mst_bridge_to_sr_beginbursttransfer), //  output,   width = 1,                 .beginbursttransfer
		.mst_bridge_to_sr_debugaccess        (mst_bridge_to_sr_debugaccess),        //  output,   width = 1,                 .debugaccess
		.mst_bridge_to_sr_response           (mst_bridge_to_sr_response),           //   input,   width = 2,                 .response
		.mst_bridge_to_sr_lock               (mst_bridge_to_sr_lock),               //  output,   width = 1,                 .lock
		.mst_bridge_to_sr_writeresponsevalid (mst_bridge_to_sr_writeresponsevalid), //   input,   width = 1,                 .writeresponsevalid
		.pr_freeze                           (1'b0)                                 // (terminated),                               
	);

endmodule
