// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_b_e
//
// Generated
//  by:  wig
//  on:  Wed Jun  7 16:54:20 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_b_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_b_e.v,v $
// Revision 1.4  2006/06/22 07:19:59  wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp 
//
// Generator: mix_0.pl Revision: 1.45 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns / 1ps



//
//
// Start of Generated Module rtl of inst_b_e
//

// No user `defines in this module


module inst_b_e
//
// Generated Module inst_b
//
	(
		port_b_1
	);

	// Generated Module Inputs:
		input		port_b_1;
	// Generated Wires:
		wire		port_b_1;
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//




	//
	// Generated Instances and Port Mappings
	//
		// Generated Instance Port Map for inst_ba
		ent_ba inst_ba (

		);
		// End of Generated Instance Port Map for inst_ba

		// Generated Instance Port Map for inst_bb
		ent_bb inst_bb (

		);
		// End of Generated Instance Port Map for inst_bb



endmodule
//
// End of Generated Module rtl of inst_b_e
//

//
//!End of Module/s
// --------------------------------------------------------------
