// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_top_rs
//
// Generated
//  by:  wig
//  on:  Tue Apr 25 19:40:28 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_top_rs.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_top_rs.v,v $
// Revision 1.1  2006/07/10 07:30:08  wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp 
//
// Generator: mix_0.pl Revision: 1.44 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of avfb_top_rs
//

	// No user `defines in this module


module avfb_top_rs
//
// Generated module i_avfb_top_rs
//
	(
	);

// End of generated module header


	// Internal signals

		//
		// Generated Signal List
		//
		//
		// End of Generated Signal List
		//


	// %COMPILER_OPTS%

	// Generated Signal Assignments




	//
	// Generated Instances
	// wiring ...

	// Generated Instances and Port Mappings
		// Generated Instance Port Map for i_rs_i2c_dcs
		rs_I2C_DCS i_rs_i2c_dcs (

		);
		// End of Generated Instance Port Map for i_rs_i2c_dcs



endmodule
//
// End of Generated Module rtl of avfb_top_rs
//

//
//!End of Module/s
// --------------------------------------------------------------
