// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
//  by:  wig
//  on:  Mon Oct 24 15:17:36 2005
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ad.v,v $
// Revision 1.2  2005/10/24 15:50:24  wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp 
//
// Generator: mix_0.pl Revision: 1.38 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns / 1ps

//
//
// Start of Generated Module rtl of ent_ad
//

	// No `defines in this module


module ent_ad
//
// Generated module inst_ad
//
		(
		port_ad_2	// Use internally test2, no port generated
		);
	// Generated Module Outputs:
		output		port_ad_2;
	// Generated Wires:
		reg		port_ad_2;
// End of generated module header


	// Internal signals

		//
		// Generated Signal List
		//
		//
		// End of Generated Signal List
		//


	// %COMPILER_OPTS%

	// Generated Signal Assignments




	//
	// Generated Instances
	// wiring ...

	// Generated Instances and Port Mappings


endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
