//
// Generated by Bluespec Compiler (build 16071eec)
//
//
// Ports:
// Name                         I/O  size props
// CSYSACK                        O     1 reg
// CACTIVE                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// CSYSREQ                        I     1 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkAxiLowPower(CLK,
		     RST_N,

		     CSYSREQ,

		     CSYSACK,

		     CACTIVE);
  input  CLK;
  input  RST_N;

  // action method cSYSREQ
  input  CSYSREQ;

  // value method cSYSACK
  output CSYSACK;

  // value method cACTIVE
  output CACTIVE;

  // signals for module outputs
  wire CACTIVE, CSYSACK;

  // register req_reg
  reg req_reg;
  wire req_reg$D_IN, req_reg$EN;

  // rule scheduling signals
  wire CAN_FIRE_cSYSREQ, WILL_FIRE_cSYSREQ;

  // action method cSYSREQ
  assign CAN_FIRE_cSYSREQ = 1'd1 ;
  assign WILL_FIRE_cSYSREQ = 1'd1 ;

  // value method cSYSACK
  assign CSYSACK = req_reg ;

  // value method cACTIVE
  assign CACTIVE = 1'd1 ;

  // register req_reg
  assign req_reg$D_IN = CSYSREQ ;
  assign req_reg$EN = 1'd1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        req_reg <= `BSV_ASSIGNMENT_DELAY 1'd1;
      end
    else
      begin
        if (req_reg$EN) req_reg <= `BSV_ASSIGNMENT_DELAY req_reg$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    req_reg = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkAxiLowPower

