`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    01:01:13 04/02/2016 
// Design Name: 
// Module Name:    ALU_1bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALU_1bit
(
// Input
		input								a_in,
		input								b_in,
		input								carry_in,
		input								b_invert,
		input								less,
		input     		[1:0]     	op,
		
// Output
		output	wire					result,
		output	wire					carry_out
    );

// Internal Variables
reg					b_invert_out;
reg					mux_out;
wire					fa_01_out;
wire					and_out;
wire					or_out;

//submodule
full_adder fa_01 (
	.x_in				( a_in				),
	.y_in				( b_invert_out 	),
	.c_in				( carry_in 			),
	.s_out			( fa_01_out 		),
	.c_out			( carry_out 		)
); // Full_Adder
 
// b_Inverter
always @ ( b_invert or b_in )
begin : Binvert
			if ( !b_invert )
				b_invert_out	=   	b_in;				// 	b
			else
				b_invert_out	=		~ b_in;			//		b'
end

// Logical_operation
assign		and_out	=	a_in & b_invert_out;
assign		or_out	=	a_in | b_invert_out;

assign		result   =  mux_out;

// op_Selection
always @ ( op or and_out or or_out or less or fa_01_out )
begin : Operation
		if ( op == 0 )			 // AND
			mux_out	= 	and_out;
			else if ( op == 1) // OR
				mux_out	= 	or_out;
			else if ( op == 2) // ADD/SUB
				mux_out	= 	fa_01_out;
			else 					// SLT
				mux_out	= 	less;		
end
endmodule

