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module acl_fp_atan(clock, resetn, enable, dataa, result);
  input clock, resetn, enable;
  input [31:0] dataa;
  output [31:0] result;
  
  fp_atan core(
      .sysclk(clock),
      .reset(~resetn),
      .enable(enable),
      .signin(dataa[31]),
      .exponentin(dataa[30:23]),
      .mantissain(dataa[22:0]),
      .signout(result[31]),
      .exponentout(result[30:23]),
      .mantissaout(result[22:0])
		);

endmodule

