//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Wed Nov 28 10:34:57 EST 2012
//
//
// Ports:
// Name                         I/O  size props
// wci_s_0_SResp                  O     2 const
// wci_s_0_SData                  O    32 const
// wci_s_0_SThreadBusy            O     1 const
// wci_s_0_SFlag                  O     2 const
// wci_s_1_SResp                  O     2 const
// wci_s_1_SData                  O    32 const
// wci_s_1_SThreadBusy            O     1 const
// wci_s_1_SFlag                  O     2 const
// wci_s_2_SResp                  O     2 reg
// wci_s_2_SData                  O    32 reg
// wci_s_2_SThreadBusy            O     1
// wci_s_2_SFlag                  O     2
// wci_s_3_SResp                  O     2 reg
// wci_s_3_SData                  O    32 reg
// wci_s_3_SThreadBusy            O     1
// wci_s_3_SFlag                  O     2
// wci_s_4_SResp                  O     2 reg
// wci_s_4_SData                  O    32 reg
// wci_s_4_SThreadBusy            O     1
// wci_s_4_SFlag                  O     2
// wci_s_5_SResp                  O     2 const
// wci_s_5_SData                  O    32 const
// wci_s_5_SThreadBusy            O     1 const
// wci_s_5_SFlag                  O     2 const
// wci_s_6_SResp                  O     2 const
// wci_s_6_SData                  O    32 const
// wci_s_6_SThreadBusy            O     1 const
// wci_s_6_SFlag                  O     2 const
// wci_s_7_SResp                  O     2 const
// wci_s_7_SData                  O    32 const
// wci_s_7_SThreadBusy            O     1 const
// wci_s_7_SFlag                  O     2 const
// wti_s_0_SThreadBusy            O     1 const
// wti_s_0_SReset_n               O     1 const
// wti_s_1_SThreadBusy            O     1 const
// wti_s_1_SReset_n               O     1 const
// wti_s_2_SThreadBusy            O     1 const
// wti_s_2_SReset_n               O     1 const
// wmiM0_MCmd                     O     3
// wmiM0_MReqLast                 O     1
// wmiM0_MReqInfo                 O     1
// wmiM0_MAddrSpace               O     1
// wmiM0_MAddr                    O    14
// wmiM0_MBurstLength             O    12
// wmiM0_MDataValid               O     1
// wmiM0_MDataLast                O     1
// wmiM0_MData                    O    32
// wmiM0_MDataByteEn              O     4
// wmiM0_MFlag                    O    32
// wmiM0_MReset_n                 O     1
// wmiM1_MCmd                     O     3
// wmiM1_MReqLast                 O     1
// wmiM1_MReqInfo                 O     1
// wmiM1_MAddrSpace               O     1
// wmiM1_MAddr                    O    14
// wmiM1_MBurstLength             O    12
// wmiM1_MDataValid               O     1
// wmiM1_MDataLast                O     1
// wmiM1_MData                    O    32
// wmiM1_MDataByteEn              O     4
// wmiM1_MFlag                    O    32
// wmiM1_MReset_n                 O     1
// wmemiM0_MCmd                   O     3 const
// wmemiM0_MReqLast               O     1 const
// wmemiM0_MAddr                  O    36 const
// wmemiM0_MBurstLength           O    12 const
// wmemiM0_MDataValid             O     1 const
// wmemiM0_MDataLast              O     1 const
// wmemiM0_MData                  O   128 const
// wmemiM0_MDataByteEn            O    16 const
// wmemiM0_MReset_n               O     1 const
// wsi_s_adc_SThreadBusy          O     1
// wsi_s_adc_SReset_n             O     1
// wsi_m_dac_MCmd                 O     3
// wsi_m_dac_MReqLast             O     1
// wsi_m_dac_MBurstPrecise        O     1
// wsi_m_dac_MBurstLength         O    12
// wsi_m_dac_MData                O    32 reg
// wsi_m_dac_MByteEn              O     4 reg
// wsi_m_dac_MReqInfo             O     8
// wsi_m_dac_MReset_n             O     1
// uuid                           O   512 const
// RST_N_rst_0                    I     1 unused
// RST_N_rst_1                    I     1 unused
// RST_N_rst_2                    I     1 reset
// RST_N_rst_3                    I     1 reset
// RST_N_rst_4                    I     1 reset
// RST_N_rst_5                    I     1 unused
// RST_N_rst_6                    I     1 unused
// RST_N_rst_7                    I     1 unused
// CLK                            I     1 clock
// RST_N                          I     1 unused
// wci_s_0_MCmd                   I     3 unused
// wci_s_0_MAddrSpace             I     1 unused
// wci_s_0_MByteEn                I     4 unused
// wci_s_0_MAddr                  I    32 unused
// wci_s_0_MData                  I    32 unused
// wci_s_0_MFlag                  I     2 unused
// wci_s_1_MCmd                   I     3 unused
// wci_s_1_MAddrSpace             I     1 unused
// wci_s_1_MByteEn                I     4 unused
// wci_s_1_MAddr                  I    32 unused
// wci_s_1_MData                  I    32 unused
// wci_s_1_MFlag                  I     2 unused
// wci_s_2_MCmd                   I     3
// wci_s_2_MAddrSpace             I     1
// wci_s_2_MByteEn                I     4
// wci_s_2_MAddr                  I    32
// wci_s_2_MData                  I    32
// wci_s_2_MFlag                  I     2 unused
// wci_s_3_MCmd                   I     3
// wci_s_3_MAddrSpace             I     1
// wci_s_3_MByteEn                I     4
// wci_s_3_MAddr                  I    32
// wci_s_3_MData                  I    32
// wci_s_3_MFlag                  I     2 unused
// wci_s_4_MCmd                   I     3
// wci_s_4_MAddrSpace             I     1
// wci_s_4_MByteEn                I     4
// wci_s_4_MAddr                  I    32
// wci_s_4_MData                  I    32
// wci_s_4_MFlag                  I     2 unused
// wci_s_5_MCmd                   I     3 unused
// wci_s_5_MAddrSpace             I     1 unused
// wci_s_5_MByteEn                I     4 unused
// wci_s_5_MAddr                  I    32 unused
// wci_s_5_MData                  I    32 unused
// wci_s_5_MFlag                  I     2 unused
// wci_s_6_MCmd                   I     3 unused
// wci_s_6_MAddrSpace             I     1 unused
// wci_s_6_MByteEn                I     4 unused
// wci_s_6_MAddr                  I    32 unused
// wci_s_6_MData                  I    32 unused
// wci_s_6_MFlag                  I     2 unused
// wci_s_7_MCmd                   I     3 unused
// wci_s_7_MAddrSpace             I     1 unused
// wci_s_7_MByteEn                I     4 unused
// wci_s_7_MAddr                  I    32 unused
// wci_s_7_MData                  I    32 unused
// wci_s_7_MFlag                  I     2 unused
// wti_s_0_MCmd                   I     3 unused
// wti_s_0_MData                  I    64 unused
// wti_s_1_MCmd                   I     3 unused
// wti_s_1_MData                  I    64 unused
// wti_s_2_MCmd                   I     3 unused
// wti_s_2_MData                  I    64 unused
// wmiM0_SResp                    I     2
// wmiM0_SData                    I    32
// wmiM0_SFlag                    I    32 reg
// wmiM1_SResp                    I     2
// wmiM1_SData                    I    32
// wmiM1_SFlag                    I    32 reg
// wmemiM0_SResp                  I     2 unused
// wmemiM0_SData                  I   128 unused
// wsi_s_adc_MCmd                 I     3
// wsi_s_adc_MBurstLength         I    12
// wsi_s_adc_MData                I    32
// wsi_s_adc_MByteEn              I     4
// wsi_s_adc_MReqInfo             I     8
// wmiM0_SThreadBusy              I     1 reg
// wmiM0_SDataThreadBusy          I     1 reg
// wmiM0_SRespLast                I     1 unused
// wmiM0_SReset_n                 I     1 reg
// wmiM1_SThreadBusy              I     1 reg
// wmiM1_SDataThreadBusy          I     1 reg
// wmiM1_SRespLast                I     1 unused
// wmiM1_SReset_n                 I     1 reg
// wmemiM0_SRespLast              I     1 unused
// wmemiM0_SCmdAccept             I     1 unused
// wmemiM0_SDataAccept            I     1 unused
// wsi_s_adc_MReqLast             I     1
// wsi_s_adc_MBurstPrecise        I     1
// wsi_s_adc_MReset_n             I     1 reg
// wsi_m_dac_SThreadBusy          I     1 reg
// wsi_m_dac_SReset_n             I     1 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkOCApp4B(RST_N_rst_0,
		 RST_N_rst_1,
		 RST_N_rst_2,
		 RST_N_rst_3,
		 RST_N_rst_4,
		 RST_N_rst_5,
		 RST_N_rst_6,
		 RST_N_rst_7,
		 CLK,
		 RST_N,

		 wci_s_0_MCmd,

		 wci_s_0_MAddrSpace,

		 wci_s_0_MByteEn,

		 wci_s_0_MAddr,

		 wci_s_0_MData,

		 wci_s_0_SResp,

		 wci_s_0_SData,

		 wci_s_0_SThreadBusy,

		 wci_s_0_SFlag,

		 wci_s_0_MFlag,

		 wci_s_1_MCmd,

		 wci_s_1_MAddrSpace,

		 wci_s_1_MByteEn,

		 wci_s_1_MAddr,

		 wci_s_1_MData,

		 wci_s_1_SResp,

		 wci_s_1_SData,

		 wci_s_1_SThreadBusy,

		 wci_s_1_SFlag,

		 wci_s_1_MFlag,

		 wci_s_2_MCmd,

		 wci_s_2_MAddrSpace,

		 wci_s_2_MByteEn,

		 wci_s_2_MAddr,

		 wci_s_2_MData,

		 wci_s_2_SResp,

		 wci_s_2_SData,

		 wci_s_2_SThreadBusy,

		 wci_s_2_SFlag,

		 wci_s_2_MFlag,

		 wci_s_3_MCmd,

		 wci_s_3_MAddrSpace,

		 wci_s_3_MByteEn,

		 wci_s_3_MAddr,

		 wci_s_3_MData,

		 wci_s_3_SResp,

		 wci_s_3_SData,

		 wci_s_3_SThreadBusy,

		 wci_s_3_SFlag,

		 wci_s_3_MFlag,

		 wci_s_4_MCmd,

		 wci_s_4_MAddrSpace,

		 wci_s_4_MByteEn,

		 wci_s_4_MAddr,

		 wci_s_4_MData,

		 wci_s_4_SResp,

		 wci_s_4_SData,

		 wci_s_4_SThreadBusy,

		 wci_s_4_SFlag,

		 wci_s_4_MFlag,

		 wci_s_5_MCmd,

		 wci_s_5_MAddrSpace,

		 wci_s_5_MByteEn,

		 wci_s_5_MAddr,

		 wci_s_5_MData,

		 wci_s_5_SResp,

		 wci_s_5_SData,

		 wci_s_5_SThreadBusy,

		 wci_s_5_SFlag,

		 wci_s_5_MFlag,

		 wci_s_6_MCmd,

		 wci_s_6_MAddrSpace,

		 wci_s_6_MByteEn,

		 wci_s_6_MAddr,

		 wci_s_6_MData,

		 wci_s_6_SResp,

		 wci_s_6_SData,

		 wci_s_6_SThreadBusy,

		 wci_s_6_SFlag,

		 wci_s_6_MFlag,

		 wci_s_7_MCmd,

		 wci_s_7_MAddrSpace,

		 wci_s_7_MByteEn,

		 wci_s_7_MAddr,

		 wci_s_7_MData,

		 wci_s_7_SResp,

		 wci_s_7_SData,

		 wci_s_7_SThreadBusy,

		 wci_s_7_SFlag,

		 wci_s_7_MFlag,

		 wti_s_0_MCmd,

		 wti_s_0_MData,

		 wti_s_0_SThreadBusy,

		 wti_s_0_SReset_n,

		 wti_s_1_MCmd,

		 wti_s_1_MData,

		 wti_s_1_SThreadBusy,

		 wti_s_1_SReset_n,

		 wti_s_2_MCmd,

		 wti_s_2_MData,

		 wti_s_2_SThreadBusy,

		 wti_s_2_SReset_n,

		 wmiM0_MCmd,

		 wmiM0_MReqLast,

		 wmiM0_MReqInfo,

		 wmiM0_MAddrSpace,

		 wmiM0_MAddr,

		 wmiM0_MBurstLength,

		 wmiM0_MDataValid,

		 wmiM0_MDataLast,

		 wmiM0_MData,

		 wmiM0_MDataByteEn,

		 wmiM0_SResp,

		 wmiM0_SData,

		 wmiM0_SThreadBusy,

		 wmiM0_SDataThreadBusy,

		 wmiM0_SRespLast,

		 wmiM0_SFlag,

		 wmiM0_MFlag,

		 wmiM0_MReset_n,

		 wmiM0_SReset_n,

		 wmiM1_MCmd,

		 wmiM1_MReqLast,

		 wmiM1_MReqInfo,

		 wmiM1_MAddrSpace,

		 wmiM1_MAddr,

		 wmiM1_MBurstLength,

		 wmiM1_MDataValid,

		 wmiM1_MDataLast,

		 wmiM1_MData,

		 wmiM1_MDataByteEn,

		 wmiM1_SResp,

		 wmiM1_SData,

		 wmiM1_SThreadBusy,

		 wmiM1_SDataThreadBusy,

		 wmiM1_SRespLast,

		 wmiM1_SFlag,

		 wmiM1_MFlag,

		 wmiM1_MReset_n,

		 wmiM1_SReset_n,

		 wmemiM0_MCmd,

		 wmemiM0_MReqLast,

		 wmemiM0_MAddr,

		 wmemiM0_MBurstLength,

		 wmemiM0_MDataValid,

		 wmemiM0_MDataLast,

		 wmemiM0_MData,

		 wmemiM0_MDataByteEn,

		 wmemiM0_SResp,

		 wmemiM0_SRespLast,

		 wmemiM0_SData,

		 wmemiM0_SCmdAccept,

		 wmemiM0_SDataAccept,

		 wmemiM0_MReset_n,

		 wsi_s_adc_MCmd,

		 wsi_s_adc_MReqLast,

		 wsi_s_adc_MBurstPrecise,

		 wsi_s_adc_MBurstLength,

		 wsi_s_adc_MData,

		 wsi_s_adc_MByteEn,

		 wsi_s_adc_MReqInfo,

		 wsi_s_adc_SThreadBusy,

		 wsi_s_adc_SReset_n,

		 wsi_s_adc_MReset_n,

		 wsi_m_dac_MCmd,

		 wsi_m_dac_MReqLast,

		 wsi_m_dac_MBurstPrecise,

		 wsi_m_dac_MBurstLength,

		 wsi_m_dac_MData,

		 wsi_m_dac_MByteEn,

		 wsi_m_dac_MReqInfo,

		 wsi_m_dac_SThreadBusy,

		 wsi_m_dac_MReset_n,

		 wsi_m_dac_SReset_n,

		 uuid);
  parameter [0 : 0] hasDebugLogic = 1'b0;
  input  RST_N_rst_0;
  input  RST_N_rst_1;
  input  RST_N_rst_2;
  input  RST_N_rst_3;
  input  RST_N_rst_4;
  input  RST_N_rst_5;
  input  RST_N_rst_6;
  input  RST_N_rst_7;
  input  CLK;
  input  RST_N;

  // action method wci_s_0_mCmd
  input  [2 : 0] wci_s_0_MCmd;

  // action method wci_s_0_mAddrSpace
  input  wci_s_0_MAddrSpace;

  // action method wci_s_0_mByteEn
  input  [3 : 0] wci_s_0_MByteEn;

  // action method wci_s_0_mAddr
  input  [31 : 0] wci_s_0_MAddr;

  // action method wci_s_0_mData
  input  [31 : 0] wci_s_0_MData;

  // value method wci_s_0_sResp
  output [1 : 0] wci_s_0_SResp;

  // value method wci_s_0_sData
  output [31 : 0] wci_s_0_SData;

  // value method wci_s_0_sThreadBusy
  output wci_s_0_SThreadBusy;

  // value method wci_s_0_sFlag
  output [1 : 0] wci_s_0_SFlag;

  // action method wci_s_0_mFlag
  input  [1 : 0] wci_s_0_MFlag;

  // action method wci_s_1_mCmd
  input  [2 : 0] wci_s_1_MCmd;

  // action method wci_s_1_mAddrSpace
  input  wci_s_1_MAddrSpace;

  // action method wci_s_1_mByteEn
  input  [3 : 0] wci_s_1_MByteEn;

  // action method wci_s_1_mAddr
  input  [31 : 0] wci_s_1_MAddr;

  // action method wci_s_1_mData
  input  [31 : 0] wci_s_1_MData;

  // value method wci_s_1_sResp
  output [1 : 0] wci_s_1_SResp;

  // value method wci_s_1_sData
  output [31 : 0] wci_s_1_SData;

  // value method wci_s_1_sThreadBusy
  output wci_s_1_SThreadBusy;

  // value method wci_s_1_sFlag
  output [1 : 0] wci_s_1_SFlag;

  // action method wci_s_1_mFlag
  input  [1 : 0] wci_s_1_MFlag;

  // action method wci_s_2_mCmd
  input  [2 : 0] wci_s_2_MCmd;

  // action method wci_s_2_mAddrSpace
  input  wci_s_2_MAddrSpace;

  // action method wci_s_2_mByteEn
  input  [3 : 0] wci_s_2_MByteEn;

  // action method wci_s_2_mAddr
  input  [31 : 0] wci_s_2_MAddr;

  // action method wci_s_2_mData
  input  [31 : 0] wci_s_2_MData;

  // value method wci_s_2_sResp
  output [1 : 0] wci_s_2_SResp;

  // value method wci_s_2_sData
  output [31 : 0] wci_s_2_SData;

  // value method wci_s_2_sThreadBusy
  output wci_s_2_SThreadBusy;

  // value method wci_s_2_sFlag
  output [1 : 0] wci_s_2_SFlag;

  // action method wci_s_2_mFlag
  input  [1 : 0] wci_s_2_MFlag;

  // action method wci_s_3_mCmd
  input  [2 : 0] wci_s_3_MCmd;

  // action method wci_s_3_mAddrSpace
  input  wci_s_3_MAddrSpace;

  // action method wci_s_3_mByteEn
  input  [3 : 0] wci_s_3_MByteEn;

  // action method wci_s_3_mAddr
  input  [31 : 0] wci_s_3_MAddr;

  // action method wci_s_3_mData
  input  [31 : 0] wci_s_3_MData;

  // value method wci_s_3_sResp
  output [1 : 0] wci_s_3_SResp;

  // value method wci_s_3_sData
  output [31 : 0] wci_s_3_SData;

  // value method wci_s_3_sThreadBusy
  output wci_s_3_SThreadBusy;

  // value method wci_s_3_sFlag
  output [1 : 0] wci_s_3_SFlag;

  // action method wci_s_3_mFlag
  input  [1 : 0] wci_s_3_MFlag;

  // action method wci_s_4_mCmd
  input  [2 : 0] wci_s_4_MCmd;

  // action method wci_s_4_mAddrSpace
  input  wci_s_4_MAddrSpace;

  // action method wci_s_4_mByteEn
  input  [3 : 0] wci_s_4_MByteEn;

  // action method wci_s_4_mAddr
  input  [31 : 0] wci_s_4_MAddr;

  // action method wci_s_4_mData
  input  [31 : 0] wci_s_4_MData;

  // value method wci_s_4_sResp
  output [1 : 0] wci_s_4_SResp;

  // value method wci_s_4_sData
  output [31 : 0] wci_s_4_SData;

  // value method wci_s_4_sThreadBusy
  output wci_s_4_SThreadBusy;

  // value method wci_s_4_sFlag
  output [1 : 0] wci_s_4_SFlag;

  // action method wci_s_4_mFlag
  input  [1 : 0] wci_s_4_MFlag;

  // action method wci_s_5_mCmd
  input  [2 : 0] wci_s_5_MCmd;

  // action method wci_s_5_mAddrSpace
  input  wci_s_5_MAddrSpace;

  // action method wci_s_5_mByteEn
  input  [3 : 0] wci_s_5_MByteEn;

  // action method wci_s_5_mAddr
  input  [31 : 0] wci_s_5_MAddr;

  // action method wci_s_5_mData
  input  [31 : 0] wci_s_5_MData;

  // value method wci_s_5_sResp
  output [1 : 0] wci_s_5_SResp;

  // value method wci_s_5_sData
  output [31 : 0] wci_s_5_SData;

  // value method wci_s_5_sThreadBusy
  output wci_s_5_SThreadBusy;

  // value method wci_s_5_sFlag
  output [1 : 0] wci_s_5_SFlag;

  // action method wci_s_5_mFlag
  input  [1 : 0] wci_s_5_MFlag;

  // action method wci_s_6_mCmd
  input  [2 : 0] wci_s_6_MCmd;

  // action method wci_s_6_mAddrSpace
  input  wci_s_6_MAddrSpace;

  // action method wci_s_6_mByteEn
  input  [3 : 0] wci_s_6_MByteEn;

  // action method wci_s_6_mAddr
  input  [31 : 0] wci_s_6_MAddr;

  // action method wci_s_6_mData
  input  [31 : 0] wci_s_6_MData;

  // value method wci_s_6_sResp
  output [1 : 0] wci_s_6_SResp;

  // value method wci_s_6_sData
  output [31 : 0] wci_s_6_SData;

  // value method wci_s_6_sThreadBusy
  output wci_s_6_SThreadBusy;

  // value method wci_s_6_sFlag
  output [1 : 0] wci_s_6_SFlag;

  // action method wci_s_6_mFlag
  input  [1 : 0] wci_s_6_MFlag;

  // action method wci_s_7_mCmd
  input  [2 : 0] wci_s_7_MCmd;

  // action method wci_s_7_mAddrSpace
  input  wci_s_7_MAddrSpace;

  // action method wci_s_7_mByteEn
  input  [3 : 0] wci_s_7_MByteEn;

  // action method wci_s_7_mAddr
  input  [31 : 0] wci_s_7_MAddr;

  // action method wci_s_7_mData
  input  [31 : 0] wci_s_7_MData;

  // value method wci_s_7_sResp
  output [1 : 0] wci_s_7_SResp;

  // value method wci_s_7_sData
  output [31 : 0] wci_s_7_SData;

  // value method wci_s_7_sThreadBusy
  output wci_s_7_SThreadBusy;

  // value method wci_s_7_sFlag
  output [1 : 0] wci_s_7_SFlag;

  // action method wci_s_7_mFlag
  input  [1 : 0] wci_s_7_MFlag;

  // action method wti_s_0_mCmd
  input  [2 : 0] wti_s_0_MCmd;

  // action method wti_s_0_mData
  input  [63 : 0] wti_s_0_MData;

  // value method wti_s_0_sThreadBusy
  output wti_s_0_SThreadBusy;

  // value method wti_s_0_sReset_n
  output wti_s_0_SReset_n;

  // action method wti_s_1_mCmd
  input  [2 : 0] wti_s_1_MCmd;

  // action method wti_s_1_mData
  input  [63 : 0] wti_s_1_MData;

  // value method wti_s_1_sThreadBusy
  output wti_s_1_SThreadBusy;

  // value method wti_s_1_sReset_n
  output wti_s_1_SReset_n;

  // action method wti_s_2_mCmd
  input  [2 : 0] wti_s_2_MCmd;

  // action method wti_s_2_mData
  input  [63 : 0] wti_s_2_MData;

  // value method wti_s_2_sThreadBusy
  output wti_s_2_SThreadBusy;

  // value method wti_s_2_sReset_n
  output wti_s_2_SReset_n;

  // value method wmiM0_mCmd
  output [2 : 0] wmiM0_MCmd;

  // value method wmiM0_mReqLast
  output wmiM0_MReqLast;

  // value method wmiM0_mReqInfo
  output wmiM0_MReqInfo;

  // value method wmiM0_mAddrSpace
  output wmiM0_MAddrSpace;

  // value method wmiM0_mAddr
  output [13 : 0] wmiM0_MAddr;

  // value method wmiM0_mBurstLength
  output [11 : 0] wmiM0_MBurstLength;

  // value method wmiM0_mDataValid
  output wmiM0_MDataValid;

  // value method wmiM0_mDataLast
  output wmiM0_MDataLast;

  // value method wmiM0_mData
  output [31 : 0] wmiM0_MData;

  // value method wmiM0_mDataInfo

  // value method wmiM0_mDataByteEn
  output [3 : 0] wmiM0_MDataByteEn;

  // action method wmiM0_sResp
  input  [1 : 0] wmiM0_SResp;

  // action method wmiM0_sData
  input  [31 : 0] wmiM0_SData;

  // action method wmiM0_sThreadBusy
  input  wmiM0_SThreadBusy;

  // action method wmiM0_sDataThreadBusy
  input  wmiM0_SDataThreadBusy;

  // action method wmiM0_sRespLast
  input  wmiM0_SRespLast;

  // action method wmiM0_sFlag
  input  [31 : 0] wmiM0_SFlag;

  // value method wmiM0_mFlag
  output [31 : 0] wmiM0_MFlag;

  // value method wmiM0_mReset_n
  output wmiM0_MReset_n;

  // action method wmiM0_sReset_n
  input  wmiM0_SReset_n;

  // value method wmiM1_mCmd
  output [2 : 0] wmiM1_MCmd;

  // value method wmiM1_mReqLast
  output wmiM1_MReqLast;

  // value method wmiM1_mReqInfo
  output wmiM1_MReqInfo;

  // value method wmiM1_mAddrSpace
  output wmiM1_MAddrSpace;

  // value method wmiM1_mAddr
  output [13 : 0] wmiM1_MAddr;

  // value method wmiM1_mBurstLength
  output [11 : 0] wmiM1_MBurstLength;

  // value method wmiM1_mDataValid
  output wmiM1_MDataValid;

  // value method wmiM1_mDataLast
  output wmiM1_MDataLast;

  // value method wmiM1_mData
  output [31 : 0] wmiM1_MData;

  // value method wmiM1_mDataInfo

  // value method wmiM1_mDataByteEn
  output [3 : 0] wmiM1_MDataByteEn;

  // action method wmiM1_sResp
  input  [1 : 0] wmiM1_SResp;

  // action method wmiM1_sData
  input  [31 : 0] wmiM1_SData;

  // action method wmiM1_sThreadBusy
  input  wmiM1_SThreadBusy;

  // action method wmiM1_sDataThreadBusy
  input  wmiM1_SDataThreadBusy;

  // action method wmiM1_sRespLast
  input  wmiM1_SRespLast;

  // action method wmiM1_sFlag
  input  [31 : 0] wmiM1_SFlag;

  // value method wmiM1_mFlag
  output [31 : 0] wmiM1_MFlag;

  // value method wmiM1_mReset_n
  output wmiM1_MReset_n;

  // action method wmiM1_sReset_n
  input  wmiM1_SReset_n;

  // value method wmemiM0_mCmd
  output [2 : 0] wmemiM0_MCmd;

  // value method wmemiM0_mReqLast
  output wmemiM0_MReqLast;

  // value method wmemiM0_mAddr
  output [35 : 0] wmemiM0_MAddr;

  // value method wmemiM0_mBurstLength
  output [11 : 0] wmemiM0_MBurstLength;

  // value method wmemiM0_mDataValid
  output wmemiM0_MDataValid;

  // value method wmemiM0_mDataLast
  output wmemiM0_MDataLast;

  // value method wmemiM0_mData
  output [127 : 0] wmemiM0_MData;

  // value method wmemiM0_mDataByteEn
  output [15 : 0] wmemiM0_MDataByteEn;

  // action method wmemiM0_sResp
  input  [1 : 0] wmemiM0_SResp;

  // action method wmemiM0_sRespLast
  input  wmemiM0_SRespLast;

  // action method wmemiM0_sData
  input  [127 : 0] wmemiM0_SData;

  // action method wmemiM0_sCmdAccept
  input  wmemiM0_SCmdAccept;

  // action method wmemiM0_sDataAccept
  input  wmemiM0_SDataAccept;

  // value method wmemiM0_mReset_n
  output wmemiM0_MReset_n;

  // action method wsi_s_adc_mCmd
  input  [2 : 0] wsi_s_adc_MCmd;

  // action method wsi_s_adc_mReqLast
  input  wsi_s_adc_MReqLast;

  // action method wsi_s_adc_mBurstPrecise
  input  wsi_s_adc_MBurstPrecise;

  // action method wsi_s_adc_mBurstLength
  input  [11 : 0] wsi_s_adc_MBurstLength;

  // action method wsi_s_adc_mData
  input  [31 : 0] wsi_s_adc_MData;

  // action method wsi_s_adc_mByteEn
  input  [3 : 0] wsi_s_adc_MByteEn;

  // action method wsi_s_adc_mReqInfo
  input  [7 : 0] wsi_s_adc_MReqInfo;

  // action method wsi_s_adc_mDataInfo

  // value method wsi_s_adc_sThreadBusy
  output wsi_s_adc_SThreadBusy;

  // value method wsi_s_adc_sReset_n
  output wsi_s_adc_SReset_n;

  // action method wsi_s_adc_mReset_n
  input  wsi_s_adc_MReset_n;

  // value method wsi_m_dac_mCmd
  output [2 : 0] wsi_m_dac_MCmd;

  // value method wsi_m_dac_mReqLast
  output wsi_m_dac_MReqLast;

  // value method wsi_m_dac_mBurstPrecise
  output wsi_m_dac_MBurstPrecise;

  // value method wsi_m_dac_mBurstLength
  output [11 : 0] wsi_m_dac_MBurstLength;

  // value method wsi_m_dac_mData
  output [31 : 0] wsi_m_dac_MData;

  // value method wsi_m_dac_mByteEn
  output [3 : 0] wsi_m_dac_MByteEn;

  // value method wsi_m_dac_mReqInfo
  output [7 : 0] wsi_m_dac_MReqInfo;

  // value method wsi_m_dac_mDataInfo

  // action method wsi_m_dac_sThreadBusy
  input  wsi_m_dac_SThreadBusy;

  // value method wsi_m_dac_mReset_n
  output wsi_m_dac_MReset_n;

  // action method wsi_m_dac_sReset_n
  input  wsi_m_dac_SReset_n;

  // value method uuid
  output [511 : 0] uuid;

  // signals for module outputs
  wire [511 : 0] uuid;
  wire [127 : 0] wmemiM0_MData;
  wire [35 : 0] wmemiM0_MAddr;
  wire [31 : 0] wci_s_0_SData,
		wci_s_1_SData,
		wci_s_2_SData,
		wci_s_3_SData,
		wci_s_4_SData,
		wci_s_5_SData,
		wci_s_6_SData,
		wci_s_7_SData,
		wmiM0_MData,
		wmiM0_MFlag,
		wmiM1_MData,
		wmiM1_MFlag,
		wsi_m_dac_MData;
  wire [15 : 0] wmemiM0_MDataByteEn;
  wire [13 : 0] wmiM0_MAddr, wmiM1_MAddr;
  wire [11 : 0] wmemiM0_MBurstLength,
		wmiM0_MBurstLength,
		wmiM1_MBurstLength,
		wsi_m_dac_MBurstLength;
  wire [7 : 0] wsi_m_dac_MReqInfo;
  wire [3 : 0] wmiM0_MDataByteEn, wmiM1_MDataByteEn, wsi_m_dac_MByteEn;
  wire [2 : 0] wmemiM0_MCmd, wmiM0_MCmd, wmiM1_MCmd, wsi_m_dac_MCmd;
  wire [1 : 0] wci_s_0_SFlag,
	       wci_s_0_SResp,
	       wci_s_1_SFlag,
	       wci_s_1_SResp,
	       wci_s_2_SFlag,
	       wci_s_2_SResp,
	       wci_s_3_SFlag,
	       wci_s_3_SResp,
	       wci_s_4_SFlag,
	       wci_s_4_SResp,
	       wci_s_5_SFlag,
	       wci_s_5_SResp,
	       wci_s_6_SFlag,
	       wci_s_6_SResp,
	       wci_s_7_SFlag,
	       wci_s_7_SResp;
  wire wci_s_0_SThreadBusy,
       wci_s_1_SThreadBusy,
       wci_s_2_SThreadBusy,
       wci_s_3_SThreadBusy,
       wci_s_4_SThreadBusy,
       wci_s_5_SThreadBusy,
       wci_s_6_SThreadBusy,
       wci_s_7_SThreadBusy,
       wmemiM0_MDataLast,
       wmemiM0_MDataValid,
       wmemiM0_MReqLast,
       wmemiM0_MReset_n,
       wmiM0_MAddrSpace,
       wmiM0_MDataLast,
       wmiM0_MDataValid,
       wmiM0_MReqInfo,
       wmiM0_MReqLast,
       wmiM0_MReset_n,
       wmiM1_MAddrSpace,
       wmiM1_MDataLast,
       wmiM1_MDataValid,
       wmiM1_MReqInfo,
       wmiM1_MReqLast,
       wmiM1_MReset_n,
       wsi_m_dac_MBurstPrecise,
       wsi_m_dac_MReqLast,
       wsi_m_dac_MReset_n,
       wsi_s_adc_SReset_n,
       wsi_s_adc_SThreadBusy,
       wti_s_0_SReset_n,
       wti_s_0_SThreadBusy,
       wti_s_1_SReset_n,
       wti_s_1_SThreadBusy,
       wti_s_2_SReset_n,
       wti_s_2_SThreadBusy;

  // inlined wires
  wire [31 : 0] tieOff0_wci_Es_mAddr_w$wget,
		tieOff0_wci_Es_mData_w$wget,
		tieOff1_wci_Es_mAddr_w$wget,
		tieOff1_wci_Es_mData_w$wget,
		tieOff5_wci_Es_mAddr_w$wget,
		tieOff5_wci_Es_mData_w$wget,
		tieOff6_wci_Es_mAddr_w$wget,
		tieOff6_wci_Es_mData_w$wget,
		tieOff7_wci_Es_mAddr_w$wget,
		tieOff7_wci_Es_mData_w$wget;
  wire [3 : 0] tieOff0_wci_Es_mByteEn_w$wget,
	       tieOff1_wci_Es_mByteEn_w$wget,
	       tieOff5_wci_Es_mByteEn_w$wget,
	       tieOff6_wci_Es_mByteEn_w$wget,
	       tieOff7_wci_Es_mByteEn_w$wget;
  wire [2 : 0] tieOff0_wci_Es_mCmd_w$wget,
	       tieOff1_wci_Es_mCmd_w$wget,
	       tieOff5_wci_Es_mCmd_w$wget,
	       tieOff6_wci_Es_mCmd_w$wget,
	       tieOff7_wci_Es_mCmd_w$wget;
  wire tieOff0_wci_Es_mAddrSpace_w$wget,
       tieOff0_wci_Es_mAddrSpace_w$whas,
       tieOff0_wci_Es_mAddr_w$whas,
       tieOff0_wci_Es_mByteEn_w$whas,
       tieOff0_wci_Es_mCmd_w$whas,
       tieOff0_wci_Es_mData_w$whas,
       tieOff1_wci_Es_mAddrSpace_w$wget,
       tieOff1_wci_Es_mAddrSpace_w$whas,
       tieOff1_wci_Es_mAddr_w$whas,
       tieOff1_wci_Es_mByteEn_w$whas,
       tieOff1_wci_Es_mCmd_w$whas,
       tieOff1_wci_Es_mData_w$whas,
       tieOff5_wci_Es_mAddrSpace_w$wget,
       tieOff5_wci_Es_mAddrSpace_w$whas,
       tieOff5_wci_Es_mAddr_w$whas,
       tieOff5_wci_Es_mByteEn_w$whas,
       tieOff5_wci_Es_mCmd_w$whas,
       tieOff5_wci_Es_mData_w$whas,
       tieOff6_wci_Es_mAddrSpace_w$wget,
       tieOff6_wci_Es_mAddrSpace_w$whas,
       tieOff6_wci_Es_mAddr_w$whas,
       tieOff6_wci_Es_mByteEn_w$whas,
       tieOff6_wci_Es_mCmd_w$whas,
       tieOff6_wci_Es_mData_w$whas,
       tieOff7_wci_Es_mAddrSpace_w$wget,
       tieOff7_wci_Es_mAddrSpace_w$whas,
       tieOff7_wci_Es_mAddr_w$whas,
       tieOff7_wci_Es_mByteEn_w$whas,
       tieOff7_wci_Es_mCmd_w$whas,
       tieOff7_wci_Es_mData_w$whas;

  // ports of submodule appW2
  wire [31 : 0] appW2$wciS0_MAddr,
		appW2$wciS0_MData,
		appW2$wciS0_SData,
		appW2$wmiM0_MData,
		appW2$wmiM0_MFlag,
		appW2$wmiM0_SData,
		appW2$wmiM0_SFlag,
		appW2$wsiM0_MData,
		appW2$wsiS0_MData;
  wire [13 : 0] appW2$wmiM0_MAddr;
  wire [11 : 0] appW2$wmiM0_MBurstLength,
		appW2$wsiM0_MBurstLength,
		appW2$wsiS0_MBurstLength;
  wire [7 : 0] appW2$wsiM0_MReqInfo, appW2$wsiS0_MReqInfo;
  wire [3 : 0] appW2$wciS0_MByteEn,
	       appW2$wmiM0_MDataByteEn,
	       appW2$wsiM0_MByteEn,
	       appW2$wsiS0_MByteEn;
  wire [2 : 0] appW2$wciS0_MCmd,
	       appW2$wmiM0_MCmd,
	       appW2$wsiM0_MCmd,
	       appW2$wsiS0_MCmd;
  wire [1 : 0] appW2$wciS0_MFlag,
	       appW2$wciS0_SFlag,
	       appW2$wciS0_SResp,
	       appW2$wmiM0_SResp;
  wire appW2$wciS0_MAddrSpace,
       appW2$wciS0_SThreadBusy,
       appW2$wmiM0_MAddrSpace,
       appW2$wmiM0_MDataLast,
       appW2$wmiM0_MDataValid,
       appW2$wmiM0_MReqInfo,
       appW2$wmiM0_MReqLast,
       appW2$wmiM0_MReset_n,
       appW2$wmiM0_SDataThreadBusy,
       appW2$wmiM0_SReset_n,
       appW2$wmiM0_SRespLast,
       appW2$wmiM0_SThreadBusy,
       appW2$wsiM0_MBurstPrecise,
       appW2$wsiM0_MReqLast,
       appW2$wsiM0_MReset_n,
       appW2$wsiM0_SReset_n,
       appW2$wsiM0_SThreadBusy,
       appW2$wsiS0_MBurstPrecise,
       appW2$wsiS0_MReqLast,
       appW2$wsiS0_MReset_n,
       appW2$wsiS0_SReset_n,
       appW2$wsiS0_SThreadBusy;

  // ports of submodule appW3
  wire [31 : 0] appW3$wciS0_MAddr,
		appW3$wciS0_MData,
		appW3$wciS0_SData,
		appW3$wsiM0_MData,
		appW3$wsiS0_MData;
  wire [11 : 0] appW3$wsiM0_MBurstLength, appW3$wsiS0_MBurstLength;
  wire [7 : 0] appW3$wsiM0_MReqInfo, appW3$wsiS0_MReqInfo;
  wire [3 : 0] appW3$wciS0_MByteEn, appW3$wsiM0_MByteEn, appW3$wsiS0_MByteEn;
  wire [2 : 0] appW3$wciS0_MCmd, appW3$wsiM0_MCmd, appW3$wsiS0_MCmd;
  wire [1 : 0] appW3$wciS0_MFlag, appW3$wciS0_SFlag, appW3$wciS0_SResp;
  wire appW3$wciS0_MAddrSpace,
       appW3$wciS0_SThreadBusy,
       appW3$wsiM0_MBurstPrecise,
       appW3$wsiM0_MReqLast,
       appW3$wsiM0_MReset_n,
       appW3$wsiM0_SReset_n,
       appW3$wsiM0_SThreadBusy,
       appW3$wsiS0_MBurstPrecise,
       appW3$wsiS0_MReqLast,
       appW3$wsiS0_MReset_n,
       appW3$wsiS0_SReset_n,
       appW3$wsiS0_SThreadBusy;

  // ports of submodule appW4
  wire [31 : 0] appW4$wciS0_MAddr,
		appW4$wciS0_MData,
		appW4$wciS0_SData,
		appW4$wmiM0_MData,
		appW4$wmiM0_MFlag,
		appW4$wmiM0_SData,
		appW4$wmiM0_SFlag,
		appW4$wsiM0_MData,
		appW4$wsiS0_MData;
  wire [13 : 0] appW4$wmiM0_MAddr;
  wire [11 : 0] appW4$wmiM0_MBurstLength,
		appW4$wsiM0_MBurstLength,
		appW4$wsiS0_MBurstLength;
  wire [7 : 0] appW4$wsiM0_MReqInfo, appW4$wsiS0_MReqInfo;
  wire [3 : 0] appW4$wciS0_MByteEn,
	       appW4$wmiM0_MDataByteEn,
	       appW4$wsiM0_MByteEn,
	       appW4$wsiS0_MByteEn;
  wire [2 : 0] appW4$wciS0_MCmd,
	       appW4$wmiM0_MCmd,
	       appW4$wsiM0_MCmd,
	       appW4$wsiS0_MCmd;
  wire [1 : 0] appW4$wciS0_MFlag,
	       appW4$wciS0_SFlag,
	       appW4$wciS0_SResp,
	       appW4$wmiM0_SResp;
  wire appW4$wciS0_MAddrSpace,
       appW4$wciS0_SThreadBusy,
       appW4$wmiM0_MAddrSpace,
       appW4$wmiM0_MDataLast,
       appW4$wmiM0_MDataValid,
       appW4$wmiM0_MReqInfo,
       appW4$wmiM0_MReqLast,
       appW4$wmiM0_MReset_n,
       appW4$wmiM0_SDataThreadBusy,
       appW4$wmiM0_SReset_n,
       appW4$wmiM0_SRespLast,
       appW4$wmiM0_SThreadBusy,
       appW4$wsiM0_MBurstPrecise,
       appW4$wsiM0_MReqLast,
       appW4$wsiM0_MReset_n,
       appW4$wsiM0_SReset_n,
       appW4$wsiM0_SThreadBusy,
       appW4$wsiS0_MBurstPrecise,
       appW4$wsiS0_MReqLast,
       appW4$wsiS0_MReset_n,
       appW4$wsiS0_SReset_n,
       appW4$wsiS0_SThreadBusy;

  // ports of submodule id
  wire [511 : 0] id$uuid;

  // value method wci_s_0_sResp
  assign wci_s_0_SResp = 2'd0 ;

  // value method wci_s_0_sData
  assign wci_s_0_SData = 32'hAAAAAAAA ;

  // value method wci_s_0_sThreadBusy
  assign wci_s_0_SThreadBusy = 1'd1 ;

  // value method wci_s_0_sFlag
  assign wci_s_0_SFlag = 2'b0 ;

  // value method wci_s_1_sResp
  assign wci_s_1_SResp = 2'd0 ;

  // value method wci_s_1_sData
  assign wci_s_1_SData = 32'hAAAAAAAA ;

  // value method wci_s_1_sThreadBusy
  assign wci_s_1_SThreadBusy = 1'd1 ;

  // value method wci_s_1_sFlag
  assign wci_s_1_SFlag = 2'b0 ;

  // value method wci_s_2_sResp
  assign wci_s_2_SResp = appW2$wciS0_SResp ;

  // value method wci_s_2_sData
  assign wci_s_2_SData = appW2$wciS0_SData ;

  // value method wci_s_2_sThreadBusy
  assign wci_s_2_SThreadBusy = appW2$wciS0_SThreadBusy ;

  // value method wci_s_2_sFlag
  assign wci_s_2_SFlag = appW2$wciS0_SFlag ;

  // value method wci_s_3_sResp
  assign wci_s_3_SResp = appW3$wciS0_SResp ;

  // value method wci_s_3_sData
  assign wci_s_3_SData = appW3$wciS0_SData ;

  // value method wci_s_3_sThreadBusy
  assign wci_s_3_SThreadBusy = appW3$wciS0_SThreadBusy ;

  // value method wci_s_3_sFlag
  assign wci_s_3_SFlag = appW3$wciS0_SFlag ;

  // value method wci_s_4_sResp
  assign wci_s_4_SResp = appW4$wciS0_SResp ;

  // value method wci_s_4_sData
  assign wci_s_4_SData = appW4$wciS0_SData ;

  // value method wci_s_4_sThreadBusy
  assign wci_s_4_SThreadBusy = appW4$wciS0_SThreadBusy ;

  // value method wci_s_4_sFlag
  assign wci_s_4_SFlag = appW4$wciS0_SFlag ;

  // value method wci_s_5_sResp
  assign wci_s_5_SResp = 2'd0 ;

  // value method wci_s_5_sData
  assign wci_s_5_SData = 32'hAAAAAAAA ;

  // value method wci_s_5_sThreadBusy
  assign wci_s_5_SThreadBusy = 1'd1 ;

  // value method wci_s_5_sFlag
  assign wci_s_5_SFlag = 2'b0 ;

  // value method wci_s_6_sResp
  assign wci_s_6_SResp = 2'd0 ;

  // value method wci_s_6_sData
  assign wci_s_6_SData = 32'hAAAAAAAA ;

  // value method wci_s_6_sThreadBusy
  assign wci_s_6_SThreadBusy = 1'd1 ;

  // value method wci_s_6_sFlag
  assign wci_s_6_SFlag = 2'b0 ;

  // value method wci_s_7_sResp
  assign wci_s_7_SResp = 2'd0 ;

  // value method wci_s_7_sData
  assign wci_s_7_SData = 32'hAAAAAAAA ;

  // value method wci_s_7_sThreadBusy
  assign wci_s_7_SThreadBusy = 1'd1 ;

  // value method wci_s_7_sFlag
  assign wci_s_7_SFlag = 2'b0 ;

  // value method wti_s_0_sThreadBusy
  assign wti_s_0_SThreadBusy = 1'h0 ;

  // value method wti_s_0_sReset_n
  assign wti_s_0_SReset_n = 1'h0 ;

  // value method wti_s_1_sThreadBusy
  assign wti_s_1_SThreadBusy = 1'h0 ;

  // value method wti_s_1_sReset_n
  assign wti_s_1_SReset_n = 1'h0 ;

  // value method wti_s_2_sThreadBusy
  assign wti_s_2_SThreadBusy = 1'h0 ;

  // value method wti_s_2_sReset_n
  assign wti_s_2_SReset_n = 1'h0 ;

  // value method wmiM0_mCmd
  assign wmiM0_MCmd = appW2$wmiM0_MCmd ;

  // value method wmiM0_mReqLast
  assign wmiM0_MReqLast = appW2$wmiM0_MReqLast ;

  // value method wmiM0_mReqInfo
  assign wmiM0_MReqInfo = appW2$wmiM0_MReqInfo ;

  // value method wmiM0_mAddrSpace
  assign wmiM0_MAddrSpace = appW2$wmiM0_MAddrSpace ;

  // value method wmiM0_mAddr
  assign wmiM0_MAddr = appW2$wmiM0_MAddr ;

  // value method wmiM0_mBurstLength
  assign wmiM0_MBurstLength = appW2$wmiM0_MBurstLength ;

  // value method wmiM0_mDataValid
  assign wmiM0_MDataValid = appW2$wmiM0_MDataValid ;

  // value method wmiM0_mDataLast
  assign wmiM0_MDataLast = appW2$wmiM0_MDataLast ;

  // value method wmiM0_mData
  assign wmiM0_MData = appW2$wmiM0_MData ;

  // value method wmiM0_mDataByteEn
  assign wmiM0_MDataByteEn = appW2$wmiM0_MDataByteEn ;

  // value method wmiM0_mFlag
  assign wmiM0_MFlag = appW2$wmiM0_MFlag ;

  // value method wmiM0_mReset_n
  assign wmiM0_MReset_n = appW2$wmiM0_MReset_n ;

  // value method wmiM1_mCmd
  assign wmiM1_MCmd = appW4$wmiM0_MCmd ;

  // value method wmiM1_mReqLast
  assign wmiM1_MReqLast = appW4$wmiM0_MReqLast ;

  // value method wmiM1_mReqInfo
  assign wmiM1_MReqInfo = appW4$wmiM0_MReqInfo ;

  // value method wmiM1_mAddrSpace
  assign wmiM1_MAddrSpace = appW4$wmiM0_MAddrSpace ;

  // value method wmiM1_mAddr
  assign wmiM1_MAddr = appW4$wmiM0_MAddr ;

  // value method wmiM1_mBurstLength
  assign wmiM1_MBurstLength = appW4$wmiM0_MBurstLength ;

  // value method wmiM1_mDataValid
  assign wmiM1_MDataValid = appW4$wmiM0_MDataValid ;

  // value method wmiM1_mDataLast
  assign wmiM1_MDataLast = appW4$wmiM0_MDataLast ;

  // value method wmiM1_mData
  assign wmiM1_MData = appW4$wmiM0_MData ;

  // value method wmiM1_mDataByteEn
  assign wmiM1_MDataByteEn = appW4$wmiM0_MDataByteEn ;

  // value method wmiM1_mFlag
  assign wmiM1_MFlag = appW4$wmiM0_MFlag ;

  // value method wmiM1_mReset_n
  assign wmiM1_MReset_n = appW4$wmiM0_MReset_n ;

  // value method wmemiM0_mCmd
  assign wmemiM0_MCmd = 3'h2 ;

  // value method wmemiM0_mReqLast
  assign wmemiM0_MReqLast = 1'h0 ;

  // value method wmemiM0_mAddr
  assign wmemiM0_MAddr = 36'hAAAAAAAAA ;

  // value method wmemiM0_mBurstLength
  assign wmemiM0_MBurstLength = 12'hAAA ;

  // value method wmemiM0_mDataValid
  assign wmemiM0_MDataValid = 1'h0 ;

  // value method wmemiM0_mDataLast
  assign wmemiM0_MDataLast = 1'h0 ;

  // value method wmemiM0_mData
  assign wmemiM0_MData = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;

  // value method wmemiM0_mDataByteEn
  assign wmemiM0_MDataByteEn = 16'hAAAA ;

  // value method wmemiM0_mReset_n
  assign wmemiM0_MReset_n = 1'h0 ;

  // value method wsi_s_adc_sThreadBusy
  assign wsi_s_adc_SThreadBusy = appW2$wsiS0_SThreadBusy ;

  // value method wsi_s_adc_sReset_n
  assign wsi_s_adc_SReset_n = appW2$wsiS0_SReset_n ;

  // value method wsi_m_dac_mCmd
  assign wsi_m_dac_MCmd = appW4$wsiM0_MCmd ;

  // value method wsi_m_dac_mReqLast
  assign wsi_m_dac_MReqLast = appW4$wsiM0_MReqLast ;

  // value method wsi_m_dac_mBurstPrecise
  assign wsi_m_dac_MBurstPrecise = appW4$wsiM0_MBurstPrecise ;

  // value method wsi_m_dac_mBurstLength
  assign wsi_m_dac_MBurstLength = appW4$wsiM0_MBurstLength ;

  // value method wsi_m_dac_mData
  assign wsi_m_dac_MData = appW4$wsiM0_MData ;

  // value method wsi_m_dac_mByteEn
  assign wsi_m_dac_MByteEn = appW4$wsiM0_MByteEn ;

  // value method wsi_m_dac_mReqInfo
  assign wsi_m_dac_MReqInfo = appW4$wsiM0_MReqInfo ;

  // value method wsi_m_dac_mReset_n
  assign wsi_m_dac_MReset_n = appW4$wsiM0_MReset_n ;

  // value method uuid
  assign uuid = id$uuid ;

  // submodule appW2
  mkSMAdapter4B #(.smaCtrlInit(32'h00000001),
		  .hasDebugLogic(hasDebugLogic)) appW2(.wciS0_Clk(CLK),
						       .wciS0_MReset_n(RST_N_rst_2),
						       .wciS0_MAddr(appW2$wciS0_MAddr),
						       .wciS0_MAddrSpace(appW2$wciS0_MAddrSpace),
						       .wciS0_MByteEn(appW2$wciS0_MByteEn),
						       .wciS0_MCmd(appW2$wciS0_MCmd),
						       .wciS0_MData(appW2$wciS0_MData),
						       .wciS0_MFlag(appW2$wciS0_MFlag),
						       .wmiM0_SData(appW2$wmiM0_SData),
						       .wmiM0_SFlag(appW2$wmiM0_SFlag),
						       .wmiM0_SResp(appW2$wmiM0_SResp),
						       .wsiS0_MBurstLength(appW2$wsiS0_MBurstLength),
						       .wsiS0_MByteEn(appW2$wsiS0_MByteEn),
						       .wsiS0_MCmd(appW2$wsiS0_MCmd),
						       .wsiS0_MData(appW2$wsiS0_MData),
						       .wsiS0_MReqInfo(appW2$wsiS0_MReqInfo),
						       .wmiM0_SThreadBusy(appW2$wmiM0_SThreadBusy),
						       .wmiM0_SDataThreadBusy(appW2$wmiM0_SDataThreadBusy),
						       .wmiM0_SRespLast(appW2$wmiM0_SRespLast),
						       .wmiM0_SReset_n(appW2$wmiM0_SReset_n),
						       .wsiM0_SThreadBusy(appW2$wsiM0_SThreadBusy),
						       .wsiM0_SReset_n(appW2$wsiM0_SReset_n),
						       .wsiS0_MReqLast(appW2$wsiS0_MReqLast),
						       .wsiS0_MBurstPrecise(appW2$wsiS0_MBurstPrecise),
						       .wsiS0_MReset_n(appW2$wsiS0_MReset_n),
						       .wciS0_SResp(appW2$wciS0_SResp),
						       .wciS0_SData(appW2$wciS0_SData),
						       .wciS0_SThreadBusy(appW2$wciS0_SThreadBusy),
						       .wciS0_SFlag(appW2$wciS0_SFlag),
						       .wmiM0_MCmd(appW2$wmiM0_MCmd),
						       .wmiM0_MReqLast(appW2$wmiM0_MReqLast),
						       .wmiM0_MReqInfo(appW2$wmiM0_MReqInfo),
						       .wmiM0_MAddrSpace(appW2$wmiM0_MAddrSpace),
						       .wmiM0_MAddr(appW2$wmiM0_MAddr),
						       .wmiM0_MBurstLength(appW2$wmiM0_MBurstLength),
						       .wmiM0_MDataValid(appW2$wmiM0_MDataValid),
						       .wmiM0_MDataLast(appW2$wmiM0_MDataLast),
						       .wmiM0_MData(appW2$wmiM0_MData),
						       .wmiM0_MDataByteEn(appW2$wmiM0_MDataByteEn),
						       .wmiM0_MFlag(appW2$wmiM0_MFlag),
						       .wmiM0_MReset_n(appW2$wmiM0_MReset_n),
						       .wsiM0_MCmd(appW2$wsiM0_MCmd),
						       .wsiM0_MReqLast(appW2$wsiM0_MReqLast),
						       .wsiM0_MBurstPrecise(appW2$wsiM0_MBurstPrecise),
						       .wsiM0_MBurstLength(appW2$wsiM0_MBurstLength),
						       .wsiM0_MData(appW2$wsiM0_MData),
						       .wsiM0_MByteEn(appW2$wsiM0_MByteEn),
						       .wsiM0_MReqInfo(appW2$wsiM0_MReqInfo),
						       .wsiM0_MReset_n(appW2$wsiM0_MReset_n),
						       .wsiS0_SThreadBusy(appW2$wsiS0_SThreadBusy),
						       .wsiS0_SReset_n(appW2$wsiS0_SReset_n));

  // submodule appW3
  mkDDCWorker #(.ddcCtrlInit(32'h0),
		.hasDebugLogic(hasDebugLogic)) appW3(.wciS0_Clk(CLK),
						     .wciS0_MReset_n(RST_N_rst_3),
						     .wciS0_MAddr(appW3$wciS0_MAddr),
						     .wciS0_MAddrSpace(appW3$wciS0_MAddrSpace),
						     .wciS0_MByteEn(appW3$wciS0_MByteEn),
						     .wciS0_MCmd(appW3$wciS0_MCmd),
						     .wciS0_MData(appW3$wciS0_MData),
						     .wciS0_MFlag(appW3$wciS0_MFlag),
						     .wsiS0_MBurstLength(appW3$wsiS0_MBurstLength),
						     .wsiS0_MByteEn(appW3$wsiS0_MByteEn),
						     .wsiS0_MCmd(appW3$wsiS0_MCmd),
						     .wsiS0_MData(appW3$wsiS0_MData),
						     .wsiS0_MReqInfo(appW3$wsiS0_MReqInfo),
						     .wsiS0_MReqLast(appW3$wsiS0_MReqLast),
						     .wsiS0_MBurstPrecise(appW3$wsiS0_MBurstPrecise),
						     .wsiS0_MReset_n(appW3$wsiS0_MReset_n),
						     .wsiM0_SThreadBusy(appW3$wsiM0_SThreadBusy),
						     .wsiM0_SReset_n(appW3$wsiM0_SReset_n),
						     .wciS0_SResp(appW3$wciS0_SResp),
						     .wciS0_SData(appW3$wciS0_SData),
						     .wciS0_SThreadBusy(appW3$wciS0_SThreadBusy),
						     .wciS0_SFlag(appW3$wciS0_SFlag),
						     .wsiS0_SThreadBusy(appW3$wsiS0_SThreadBusy),
						     .wsiS0_SReset_n(appW3$wsiS0_SReset_n),
						     .wsiM0_MCmd(appW3$wsiM0_MCmd),
						     .wsiM0_MReqLast(appW3$wsiM0_MReqLast),
						     .wsiM0_MBurstPrecise(appW3$wsiM0_MBurstPrecise),
						     .wsiM0_MBurstLength(appW3$wsiM0_MBurstLength),
						     .wsiM0_MData(appW3$wsiM0_MData),
						     .wsiM0_MByteEn(appW3$wsiM0_MByteEn),
						     .wsiM0_MReqInfo(appW3$wsiM0_MReqInfo),
						     .wsiM0_MReset_n(appW3$wsiM0_MReset_n));

  // submodule appW4
  mkSMAdapter4B #(.smaCtrlInit(32'h00000002),
		  .hasDebugLogic(hasDebugLogic)) appW4(.wciS0_Clk(CLK),
						       .wciS0_MReset_n(RST_N_rst_4),
						       .wciS0_MAddr(appW4$wciS0_MAddr),
						       .wciS0_MAddrSpace(appW4$wciS0_MAddrSpace),
						       .wciS0_MByteEn(appW4$wciS0_MByteEn),
						       .wciS0_MCmd(appW4$wciS0_MCmd),
						       .wciS0_MData(appW4$wciS0_MData),
						       .wciS0_MFlag(appW4$wciS0_MFlag),
						       .wmiM0_SData(appW4$wmiM0_SData),
						       .wmiM0_SFlag(appW4$wmiM0_SFlag),
						       .wmiM0_SResp(appW4$wmiM0_SResp),
						       .wsiS0_MBurstLength(appW4$wsiS0_MBurstLength),
						       .wsiS0_MByteEn(appW4$wsiS0_MByteEn),
						       .wsiS0_MCmd(appW4$wsiS0_MCmd),
						       .wsiS0_MData(appW4$wsiS0_MData),
						       .wsiS0_MReqInfo(appW4$wsiS0_MReqInfo),
						       .wmiM0_SThreadBusy(appW4$wmiM0_SThreadBusy),
						       .wmiM0_SDataThreadBusy(appW4$wmiM0_SDataThreadBusy),
						       .wmiM0_SRespLast(appW4$wmiM0_SRespLast),
						       .wmiM0_SReset_n(appW4$wmiM0_SReset_n),
						       .wsiM0_SThreadBusy(appW4$wsiM0_SThreadBusy),
						       .wsiM0_SReset_n(appW4$wsiM0_SReset_n),
						       .wsiS0_MReqLast(appW4$wsiS0_MReqLast),
						       .wsiS0_MBurstPrecise(appW4$wsiS0_MBurstPrecise),
						       .wsiS0_MReset_n(appW4$wsiS0_MReset_n),
						       .wciS0_SResp(appW4$wciS0_SResp),
						       .wciS0_SData(appW4$wciS0_SData),
						       .wciS0_SThreadBusy(appW4$wciS0_SThreadBusy),
						       .wciS0_SFlag(appW4$wciS0_SFlag),
						       .wmiM0_MCmd(appW4$wmiM0_MCmd),
						       .wmiM0_MReqLast(appW4$wmiM0_MReqLast),
						       .wmiM0_MReqInfo(appW4$wmiM0_MReqInfo),
						       .wmiM0_MAddrSpace(appW4$wmiM0_MAddrSpace),
						       .wmiM0_MAddr(appW4$wmiM0_MAddr),
						       .wmiM0_MBurstLength(appW4$wmiM0_MBurstLength),
						       .wmiM0_MDataValid(appW4$wmiM0_MDataValid),
						       .wmiM0_MDataLast(appW4$wmiM0_MDataLast),
						       .wmiM0_MData(appW4$wmiM0_MData),
						       .wmiM0_MDataByteEn(appW4$wmiM0_MDataByteEn),
						       .wmiM0_MFlag(appW4$wmiM0_MFlag),
						       .wmiM0_MReset_n(appW4$wmiM0_MReset_n),
						       .wsiM0_MCmd(appW4$wsiM0_MCmd),
						       .wsiM0_MReqLast(appW4$wsiM0_MReqLast),
						       .wsiM0_MBurstPrecise(appW4$wsiM0_MBurstPrecise),
						       .wsiM0_MBurstLength(appW4$wsiM0_MBurstLength),
						       .wsiM0_MData(appW4$wsiM0_MData),
						       .wsiM0_MByteEn(appW4$wsiM0_MByteEn),
						       .wsiM0_MReqInfo(appW4$wsiM0_MReqInfo),
						       .wsiM0_MReset_n(appW4$wsiM0_MReset_n),
						       .wsiS0_SThreadBusy(appW4$wsiS0_SThreadBusy),
						       .wsiS0_SReset_n(appW4$wsiS0_SReset_n));

  // submodule id
  mkUUID id(.uuid(id$uuid));

  // inlined wires
  assign tieOff0_wci_Es_mCmd_w$wget = wci_s_0_MCmd ;
  assign tieOff0_wci_Es_mCmd_w$whas = 1'd1 ;
  assign tieOff0_wci_Es_mAddrSpace_w$wget = wci_s_0_MAddrSpace ;
  assign tieOff0_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign tieOff0_wci_Es_mByteEn_w$wget = wci_s_0_MByteEn ;
  assign tieOff0_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign tieOff0_wci_Es_mAddr_w$wget = wci_s_0_MAddr ;
  assign tieOff0_wci_Es_mAddr_w$whas = 1'd1 ;
  assign tieOff0_wci_Es_mData_w$wget = wci_s_0_MData ;
  assign tieOff0_wci_Es_mData_w$whas = 1'd1 ;
  assign tieOff1_wci_Es_mCmd_w$wget = wci_s_1_MCmd ;
  assign tieOff1_wci_Es_mCmd_w$whas = 1'd1 ;
  assign tieOff1_wci_Es_mAddrSpace_w$wget = wci_s_1_MAddrSpace ;
  assign tieOff1_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign tieOff1_wci_Es_mByteEn_w$wget = wci_s_1_MByteEn ;
  assign tieOff1_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign tieOff1_wci_Es_mAddr_w$wget = wci_s_1_MAddr ;
  assign tieOff1_wci_Es_mAddr_w$whas = 1'd1 ;
  assign tieOff1_wci_Es_mData_w$wget = wci_s_1_MData ;
  assign tieOff1_wci_Es_mData_w$whas = 1'd1 ;
  assign tieOff5_wci_Es_mCmd_w$wget = wci_s_5_MCmd ;
  assign tieOff5_wci_Es_mCmd_w$whas = 1'd1 ;
  assign tieOff5_wci_Es_mAddrSpace_w$wget = wci_s_5_MAddrSpace ;
  assign tieOff5_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign tieOff5_wci_Es_mByteEn_w$wget = wci_s_5_MByteEn ;
  assign tieOff5_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign tieOff5_wci_Es_mAddr_w$wget = wci_s_5_MAddr ;
  assign tieOff5_wci_Es_mAddr_w$whas = 1'd1 ;
  assign tieOff5_wci_Es_mData_w$wget = wci_s_5_MData ;
  assign tieOff5_wci_Es_mData_w$whas = 1'd1 ;
  assign tieOff6_wci_Es_mCmd_w$wget = wci_s_6_MCmd ;
  assign tieOff6_wci_Es_mCmd_w$whas = 1'd1 ;
  assign tieOff6_wci_Es_mAddrSpace_w$wget = wci_s_6_MAddrSpace ;
  assign tieOff6_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign tieOff6_wci_Es_mByteEn_w$wget = wci_s_6_MByteEn ;
  assign tieOff6_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign tieOff6_wci_Es_mAddr_w$wget = wci_s_6_MAddr ;
  assign tieOff6_wci_Es_mAddr_w$whas = 1'd1 ;
  assign tieOff6_wci_Es_mData_w$wget = wci_s_6_MData ;
  assign tieOff6_wci_Es_mData_w$whas = 1'd1 ;
  assign tieOff7_wci_Es_mCmd_w$wget = wci_s_7_MCmd ;
  assign tieOff7_wci_Es_mCmd_w$whas = 1'd1 ;
  assign tieOff7_wci_Es_mAddrSpace_w$wget = wci_s_7_MAddrSpace ;
  assign tieOff7_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign tieOff7_wci_Es_mByteEn_w$wget = wci_s_7_MByteEn ;
  assign tieOff7_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign tieOff7_wci_Es_mAddr_w$wget = wci_s_7_MAddr ;
  assign tieOff7_wci_Es_mAddr_w$whas = 1'd1 ;
  assign tieOff7_wci_Es_mData_w$wget = wci_s_7_MData ;
  assign tieOff7_wci_Es_mData_w$whas = 1'd1 ;

  // submodule appW2
  assign appW2$wciS0_MAddr = wci_s_2_MAddr ;
  assign appW2$wciS0_MAddrSpace = wci_s_2_MAddrSpace ;
  assign appW2$wciS0_MByteEn = wci_s_2_MByteEn ;
  assign appW2$wciS0_MCmd = wci_s_2_MCmd ;
  assign appW2$wciS0_MData = wci_s_2_MData ;
  assign appW2$wciS0_MFlag = wci_s_2_MFlag ;
  assign appW2$wmiM0_SData = wmiM0_SData ;
  assign appW2$wmiM0_SFlag = wmiM0_SFlag ;
  assign appW2$wmiM0_SResp = wmiM0_SResp ;
  assign appW2$wsiS0_MBurstLength = wsi_s_adc_MBurstLength ;
  assign appW2$wsiS0_MByteEn = wsi_s_adc_MByteEn ;
  assign appW2$wsiS0_MCmd = wsi_s_adc_MCmd ;
  assign appW2$wsiS0_MData = wsi_s_adc_MData ;
  assign appW2$wsiS0_MReqInfo = wsi_s_adc_MReqInfo ;
  assign appW2$wmiM0_SThreadBusy = wmiM0_SThreadBusy ;
  assign appW2$wmiM0_SDataThreadBusy = wmiM0_SDataThreadBusy ;
  assign appW2$wmiM0_SRespLast = wmiM0_SRespLast ;
  assign appW2$wmiM0_SReset_n = wmiM0_SReset_n ;
  assign appW2$wsiM0_SThreadBusy = appW3$wsiS0_SThreadBusy ;
  assign appW2$wsiM0_SReset_n = appW3$wsiS0_SReset_n ;
  assign appW2$wsiS0_MReqLast = wsi_s_adc_MReqLast ;
  assign appW2$wsiS0_MBurstPrecise = wsi_s_adc_MBurstPrecise ;
  assign appW2$wsiS0_MReset_n = wsi_s_adc_MReset_n ;

  // submodule appW3
  assign appW3$wciS0_MAddr = wci_s_3_MAddr ;
  assign appW3$wciS0_MAddrSpace = wci_s_3_MAddrSpace ;
  assign appW3$wciS0_MByteEn = wci_s_3_MByteEn ;
  assign appW3$wciS0_MCmd = wci_s_3_MCmd ;
  assign appW3$wciS0_MData = wci_s_3_MData ;
  assign appW3$wciS0_MFlag = wci_s_3_MFlag ;
  assign appW3$wsiS0_MBurstLength = appW2$wsiM0_MBurstLength ;
  assign appW3$wsiS0_MByteEn = appW2$wsiM0_MByteEn ;
  assign appW3$wsiS0_MCmd = appW2$wsiM0_MCmd ;
  assign appW3$wsiS0_MData = appW2$wsiM0_MData ;
  assign appW3$wsiS0_MReqInfo = appW2$wsiM0_MReqInfo ;
  assign appW3$wsiS0_MReqLast = appW2$wsiM0_MReqLast ;
  assign appW3$wsiS0_MBurstPrecise = appW2$wsiM0_MBurstPrecise ;
  assign appW3$wsiS0_MReset_n = appW2$wsiM0_MReset_n ;
  assign appW3$wsiM0_SThreadBusy = appW4$wsiS0_SThreadBusy ;
  assign appW3$wsiM0_SReset_n = appW4$wsiS0_SReset_n ;

  // submodule appW4
  assign appW4$wciS0_MAddr = wci_s_4_MAddr ;
  assign appW4$wciS0_MAddrSpace = wci_s_4_MAddrSpace ;
  assign appW4$wciS0_MByteEn = wci_s_4_MByteEn ;
  assign appW4$wciS0_MCmd = wci_s_4_MCmd ;
  assign appW4$wciS0_MData = wci_s_4_MData ;
  assign appW4$wciS0_MFlag = wci_s_4_MFlag ;
  assign appW4$wmiM0_SData = wmiM1_SData ;
  assign appW4$wmiM0_SFlag = wmiM1_SFlag ;
  assign appW4$wmiM0_SResp = wmiM1_SResp ;
  assign appW4$wsiS0_MBurstLength = appW3$wsiM0_MBurstLength ;
  assign appW4$wsiS0_MByteEn = appW3$wsiM0_MByteEn ;
  assign appW4$wsiS0_MCmd = appW3$wsiM0_MCmd ;
  assign appW4$wsiS0_MData = appW3$wsiM0_MData ;
  assign appW4$wsiS0_MReqInfo = appW3$wsiM0_MReqInfo ;
  assign appW4$wmiM0_SThreadBusy = wmiM1_SThreadBusy ;
  assign appW4$wmiM0_SDataThreadBusy = wmiM1_SDataThreadBusy ;
  assign appW4$wmiM0_SRespLast = wmiM1_SRespLast ;
  assign appW4$wmiM0_SReset_n = wmiM1_SReset_n ;
  assign appW4$wsiM0_SThreadBusy = wsi_m_dac_SThreadBusy ;
  assign appW4$wsiM0_SReset_n = wsi_m_dac_SReset_n ;
  assign appW4$wsiS0_MReqLast = appW3$wsiM0_MReqLast ;
  assign appW4$wsiS0_MBurstPrecise = appW3$wsiM0_MBurstPrecise ;
  assign appW4$wsiS0_MReset_n = appW3$wsiM0_MReset_n ;
endmodule  // mkOCApp4B

