// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="axi_interfaces,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.162500,HLS_SYN_LAT=5,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2139,HLS_SYN_LUT=1196}" *)

module axi_interfaces (
        ap_clk,
        ap_rst_n,
        d_o_0_TREADY,
        d_o_1_TREADY,
        d_o_2_TREADY,
        d_o_3_TREADY,
        d_o_4_TREADY,
        d_o_5_TREADY,
        d_o_6_TREADY,
        d_o_7_TREADY,
        d_o_0_TDATA,
        d_o_0_TVALID,
        d_o_1_TDATA,
        d_o_1_TVALID,
        d_o_2_TDATA,
        d_o_2_TVALID,
        d_o_3_TDATA,
        d_o_3_TVALID,
        d_o_4_TDATA,
        d_o_4_TVALID,
        d_o_5_TDATA,
        d_o_5_TVALID,
        d_o_6_TDATA,
        d_o_6_TVALID,
        d_o_7_TDATA,
        d_o_7_TVALID,
        d_i_0_TDATA,
        d_i_0_TVALID,
        d_i_0_TREADY,
        d_i_1_TDATA,
        d_i_1_TVALID,
        d_i_1_TREADY,
        d_i_2_TDATA,
        d_i_2_TVALID,
        d_i_2_TREADY,
        d_i_3_TDATA,
        d_i_3_TVALID,
        d_i_3_TREADY,
        d_i_4_TDATA,
        d_i_4_TVALID,
        d_i_4_TREADY,
        d_i_5_TDATA,
        d_i_5_TVALID,
        d_i_5_TREADY,
        d_i_6_TDATA,
        d_i_6_TVALID,
        d_i_6_TREADY,
        d_i_7_TDATA,
        d_i_7_TVALID,
        d_i_7_TREADY,
        s_axi_AXILiteS_AWVALID,
        s_axi_AXILiteS_AWREADY,
        s_axi_AXILiteS_AWADDR,
        s_axi_AXILiteS_WVALID,
        s_axi_AXILiteS_WREADY,
        s_axi_AXILiteS_WDATA,
        s_axi_AXILiteS_WSTRB,
        s_axi_AXILiteS_ARVALID,
        s_axi_AXILiteS_ARREADY,
        s_axi_AXILiteS_ARADDR,
        s_axi_AXILiteS_RVALID,
        s_axi_AXILiteS_RREADY,
        s_axi_AXILiteS_RDATA,
        s_axi_AXILiteS_RRESP,
        s_axi_AXILiteS_BVALID,
        s_axi_AXILiteS_BREADY,
        s_axi_AXILiteS_BRESP,
        interrupt
);

parameter    ap_ST_fsm_state1 = 2'd1;
parameter    ap_ST_fsm_pp0_stage0 = 2'd2;
parameter    C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter    C_S_AXI_AXILITES_ADDR_WIDTH = 4;
parameter    C_S_AXI_DATA_WIDTH = 32;

parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);

input   ap_clk;
input   ap_rst_n;
input   d_o_0_TREADY;
input   d_o_1_TREADY;
input   d_o_2_TREADY;
input   d_o_3_TREADY;
input   d_o_4_TREADY;
input   d_o_5_TREADY;
input   d_o_6_TREADY;
input   d_o_7_TREADY;
output  [15:0] d_o_0_TDATA;
output   d_o_0_TVALID;
output  [15:0] d_o_1_TDATA;
output   d_o_1_TVALID;
output  [15:0] d_o_2_TDATA;
output   d_o_2_TVALID;
output  [15:0] d_o_3_TDATA;
output   d_o_3_TVALID;
output  [15:0] d_o_4_TDATA;
output   d_o_4_TVALID;
output  [15:0] d_o_5_TDATA;
output   d_o_5_TVALID;
output  [15:0] d_o_6_TDATA;
output   d_o_6_TVALID;
output  [15:0] d_o_7_TDATA;
output   d_o_7_TVALID;
input  [15:0] d_i_0_TDATA;
input   d_i_0_TVALID;
output   d_i_0_TREADY;
input  [15:0] d_i_1_TDATA;
input   d_i_1_TVALID;
output   d_i_1_TREADY;
input  [15:0] d_i_2_TDATA;
input   d_i_2_TVALID;
output   d_i_2_TREADY;
input  [15:0] d_i_3_TDATA;
input   d_i_3_TVALID;
output   d_i_3_TREADY;
input  [15:0] d_i_4_TDATA;
input   d_i_4_TVALID;
output   d_i_4_TREADY;
input  [15:0] d_i_5_TDATA;
input   d_i_5_TVALID;
output   d_i_5_TREADY;
input  [15:0] d_i_6_TDATA;
input   d_i_6_TVALID;
output   d_i_6_TREADY;
input  [15:0] d_i_7_TDATA;
input   d_i_7_TVALID;
output   d_i_7_TREADY;
input   s_axi_AXILiteS_AWVALID;
output   s_axi_AXILiteS_AWREADY;
input  [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_AWADDR;
input   s_axi_AXILiteS_WVALID;
output   s_axi_AXILiteS_WREADY;
input  [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_WDATA;
input  [C_S_AXI_AXILITES_WSTRB_WIDTH - 1:0] s_axi_AXILiteS_WSTRB;
input   s_axi_AXILiteS_ARVALID;
output   s_axi_AXILiteS_ARREADY;
input  [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_ARADDR;
output   s_axi_AXILiteS_RVALID;
input   s_axi_AXILiteS_RREADY;
output  [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_RDATA;
output  [1:0] s_axi_AXILiteS_RRESP;
output   s_axi_AXILiteS_BVALID;
input   s_axi_AXILiteS_BREADY;
output  [1:0] s_axi_AXILiteS_BRESP;
output   interrupt;

reg    ap_rst_n_inv;
wire    ap_start;
reg    ap_done;
reg    ap_idle;
(* fsm_encoding = "none" *) reg   [1:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    ap_ready;
wire   [0:0] exitcond_fu_246_p2;
wire    ap_CS_fsm_pp0_stage0;
wire    ap_enable_reg_pp0_iter0;
wire    ap_block_state2_pp0_stage0_iter0;
wire    d_i_0_0_vld_out;
wire    d_i_1_0_vld_out;
wire    d_i_2_0_vld_out;
wire    d_i_3_0_vld_out;
wire    d_i_4_0_vld_out;
wire    d_i_5_0_vld_out;
wire    d_i_6_0_vld_out;
wire    d_i_7_0_vld_out;
reg    ap_block_state4_pp0_stage0_iter1;
wire    d_o_0_1_ack_in;
wire    d_o_1_1_ack_in;
wire    d_o_2_1_ack_in;
wire    d_o_3_1_ack_in;
wire    d_o_4_1_ack_in;
wire    d_o_5_1_ack_in;
wire    d_o_6_1_ack_in;
wire    d_o_7_1_ack_in;
reg    ap_block_state4_io;
reg    ap_enable_reg_pp0_iter1;
reg    ap_block_state3_pp0_stage0_iter2;
reg    ap_block_state3_io;
reg    ap_enable_reg_pp0_iter2;
reg    ap_block_pp0_stage0_flag00011001;
reg   [15:0] d_o_0_1_data_out;
reg    d_o_0_1_vld_in;
wire    d_o_0_1_vld_out;
wire    d_o_0_1_ack_out;
reg   [15:0] d_o_0_1_payload_A;
reg   [15:0] d_o_0_1_payload_B;
reg    d_o_0_1_sel_rd;
reg    d_o_0_1_sel_wr;
wire    d_o_0_1_sel;
wire    d_o_0_1_load_A;
wire    d_o_0_1_load_B;
reg   [1:0] d_o_0_1_state;
wire    d_o_0_1_state_cmp_full;
reg   [15:0] d_o_1_1_data_out;
reg    d_o_1_1_vld_in;
wire    d_o_1_1_vld_out;
wire    d_o_1_1_ack_out;
reg   [15:0] d_o_1_1_payload_A;
reg   [15:0] d_o_1_1_payload_B;
reg    d_o_1_1_sel_rd;
reg    d_o_1_1_sel_wr;
wire    d_o_1_1_sel;
wire    d_o_1_1_load_A;
wire    d_o_1_1_load_B;
reg   [1:0] d_o_1_1_state;
wire    d_o_1_1_state_cmp_full;
reg   [15:0] d_o_2_1_data_out;
reg    d_o_2_1_vld_in;
wire    d_o_2_1_vld_out;
wire    d_o_2_1_ack_out;
reg   [15:0] d_o_2_1_payload_A;
reg   [15:0] d_o_2_1_payload_B;
reg    d_o_2_1_sel_rd;
reg    d_o_2_1_sel_wr;
wire    d_o_2_1_sel;
wire    d_o_2_1_load_A;
wire    d_o_2_1_load_B;
reg   [1:0] d_o_2_1_state;
wire    d_o_2_1_state_cmp_full;
reg   [15:0] d_o_3_1_data_out;
reg    d_o_3_1_vld_in;
wire    d_o_3_1_vld_out;
wire    d_o_3_1_ack_out;
reg   [15:0] d_o_3_1_payload_A;
reg   [15:0] d_o_3_1_payload_B;
reg    d_o_3_1_sel_rd;
reg    d_o_3_1_sel_wr;
wire    d_o_3_1_sel;
wire    d_o_3_1_load_A;
wire    d_o_3_1_load_B;
reg   [1:0] d_o_3_1_state;
wire    d_o_3_1_state_cmp_full;
reg   [15:0] d_o_4_1_data_out;
reg    d_o_4_1_vld_in;
wire    d_o_4_1_vld_out;
wire    d_o_4_1_ack_out;
reg   [15:0] d_o_4_1_payload_A;
reg   [15:0] d_o_4_1_payload_B;
reg    d_o_4_1_sel_rd;
reg    d_o_4_1_sel_wr;
wire    d_o_4_1_sel;
wire    d_o_4_1_load_A;
wire    d_o_4_1_load_B;
reg   [1:0] d_o_4_1_state;
wire    d_o_4_1_state_cmp_full;
reg   [15:0] d_o_5_1_data_out;
reg    d_o_5_1_vld_in;
wire    d_o_5_1_vld_out;
wire    d_o_5_1_ack_out;
reg   [15:0] d_o_5_1_payload_A;
reg   [15:0] d_o_5_1_payload_B;
reg    d_o_5_1_sel_rd;
reg    d_o_5_1_sel_wr;
wire    d_o_5_1_sel;
wire    d_o_5_1_load_A;
wire    d_o_5_1_load_B;
reg   [1:0] d_o_5_1_state;
wire    d_o_5_1_state_cmp_full;
reg   [15:0] d_o_6_1_data_out;
reg    d_o_6_1_vld_in;
wire    d_o_6_1_vld_out;
wire    d_o_6_1_ack_out;
reg   [15:0] d_o_6_1_payload_A;
reg   [15:0] d_o_6_1_payload_B;
reg    d_o_6_1_sel_rd;
reg    d_o_6_1_sel_wr;
wire    d_o_6_1_sel;
wire    d_o_6_1_load_A;
wire    d_o_6_1_load_B;
reg   [1:0] d_o_6_1_state;
wire    d_o_6_1_state_cmp_full;
reg   [15:0] d_o_7_1_data_out;
reg    d_o_7_1_vld_in;
wire    d_o_7_1_vld_out;
wire    d_o_7_1_ack_out;
reg   [15:0] d_o_7_1_payload_A;
reg   [15:0] d_o_7_1_payload_B;
reg    d_o_7_1_sel_rd;
reg    d_o_7_1_sel_wr;
wire    d_o_7_1_sel;
wire    d_o_7_1_load_A;
wire    d_o_7_1_load_B;
reg   [1:0] d_o_7_1_state;
wire    d_o_7_1_state_cmp_full;
reg   [15:0] d_i_0_0_data_out;
wire    d_i_0_0_vld_in;
wire    d_i_0_0_ack_in;
reg    d_i_0_0_ack_out;
reg   [15:0] d_i_0_0_payload_A;
reg   [15:0] d_i_0_0_payload_B;
reg    d_i_0_0_sel_rd;
reg    d_i_0_0_sel_wr;
wire    d_i_0_0_sel;
wire    d_i_0_0_load_A;
wire    d_i_0_0_load_B;
reg   [1:0] d_i_0_0_state;
wire    d_i_0_0_state_cmp_full;
reg   [15:0] d_i_1_0_data_out;
wire    d_i_1_0_vld_in;
wire    d_i_1_0_ack_in;
reg    d_i_1_0_ack_out;
reg   [15:0] d_i_1_0_payload_A;
reg   [15:0] d_i_1_0_payload_B;
reg    d_i_1_0_sel_rd;
reg    d_i_1_0_sel_wr;
wire    d_i_1_0_sel;
wire    d_i_1_0_load_A;
wire    d_i_1_0_load_B;
reg   [1:0] d_i_1_0_state;
wire    d_i_1_0_state_cmp_full;
reg   [15:0] d_i_2_0_data_out;
wire    d_i_2_0_vld_in;
wire    d_i_2_0_ack_in;
reg    d_i_2_0_ack_out;
reg   [15:0] d_i_2_0_payload_A;
reg   [15:0] d_i_2_0_payload_B;
reg    d_i_2_0_sel_rd;
reg    d_i_2_0_sel_wr;
wire    d_i_2_0_sel;
wire    d_i_2_0_load_A;
wire    d_i_2_0_load_B;
reg   [1:0] d_i_2_0_state;
wire    d_i_2_0_state_cmp_full;
reg   [15:0] d_i_3_0_data_out;
wire    d_i_3_0_vld_in;
wire    d_i_3_0_ack_in;
reg    d_i_3_0_ack_out;
reg   [15:0] d_i_3_0_payload_A;
reg   [15:0] d_i_3_0_payload_B;
reg    d_i_3_0_sel_rd;
reg    d_i_3_0_sel_wr;
wire    d_i_3_0_sel;
wire    d_i_3_0_load_A;
wire    d_i_3_0_load_B;
reg   [1:0] d_i_3_0_state;
wire    d_i_3_0_state_cmp_full;
reg   [15:0] d_i_4_0_data_out;
wire    d_i_4_0_vld_in;
wire    d_i_4_0_ack_in;
reg    d_i_4_0_ack_out;
reg   [15:0] d_i_4_0_payload_A;
reg   [15:0] d_i_4_0_payload_B;
reg    d_i_4_0_sel_rd;
reg    d_i_4_0_sel_wr;
wire    d_i_4_0_sel;
wire    d_i_4_0_load_A;
wire    d_i_4_0_load_B;
reg   [1:0] d_i_4_0_state;
wire    d_i_4_0_state_cmp_full;
reg   [15:0] d_i_5_0_data_out;
wire    d_i_5_0_vld_in;
wire    d_i_5_0_ack_in;
reg    d_i_5_0_ack_out;
reg   [15:0] d_i_5_0_payload_A;
reg   [15:0] d_i_5_0_payload_B;
reg    d_i_5_0_sel_rd;
reg    d_i_5_0_sel_wr;
wire    d_i_5_0_sel;
wire    d_i_5_0_load_A;
wire    d_i_5_0_load_B;
reg   [1:0] d_i_5_0_state;
wire    d_i_5_0_state_cmp_full;
reg   [15:0] d_i_6_0_data_out;
wire    d_i_6_0_vld_in;
wire    d_i_6_0_ack_in;
reg    d_i_6_0_ack_out;
reg   [15:0] d_i_6_0_payload_A;
reg   [15:0] d_i_6_0_payload_B;
reg    d_i_6_0_sel_rd;
reg    d_i_6_0_sel_wr;
wire    d_i_6_0_sel;
wire    d_i_6_0_load_A;
wire    d_i_6_0_load_B;
reg   [1:0] d_i_6_0_state;
wire    d_i_6_0_state_cmp_full;
reg   [15:0] d_i_7_0_data_out;
wire    d_i_7_0_vld_in;
wire    d_i_7_0_ack_in;
reg    d_i_7_0_ack_out;
reg   [15:0] d_i_7_0_payload_A;
reg   [15:0] d_i_7_0_payload_B;
reg    d_i_7_0_sel_rd;
reg    d_i_7_0_sel_wr;
wire    d_i_7_0_sel;
wire    d_i_7_0_load_A;
wire    d_i_7_0_load_B;
reg   [1:0] d_i_7_0_state;
wire    d_i_7_0_state_cmp_full;
reg   [31:0] acc_0;
reg   [31:0] acc_1;
reg   [31:0] acc_2;
reg   [31:0] acc_3;
reg   [31:0] acc_4;
reg   [31:0] acc_5;
reg   [31:0] acc_6;
reg   [31:0] acc_7;
reg    d_o_0_TDATA_blk_n;
wire    ap_block_pp0_stage0_flag00000000;
reg    d_o_1_TDATA_blk_n;
reg    d_o_2_TDATA_blk_n;
reg    d_o_3_TDATA_blk_n;
reg    d_o_4_TDATA_blk_n;
reg    d_o_5_TDATA_blk_n;
reg    d_o_6_TDATA_blk_n;
reg    d_o_7_TDATA_blk_n;
reg    d_i_0_TDATA_blk_n;
reg    d_i_1_TDATA_blk_n;
reg    d_i_2_TDATA_blk_n;
reg    d_i_3_TDATA_blk_n;
reg    d_i_4_TDATA_blk_n;
reg    d_i_5_TDATA_blk_n;
reg    d_i_6_TDATA_blk_n;
reg    d_i_7_TDATA_blk_n;
reg   [4:0] i1_reg_218;
wire   [4:0] tmp_17_fu_242_p1;
reg   [4:0] tmp_17_reg_502;
reg   [0:0] exitcond_reg_507;
reg   [0:0] ap_reg_pp0_iter1_exitcond_reg_507;
wire   [15:0] tmp_8_fu_278_p2;
wire   [15:0] tmp_2_1_fu_309_p2;
wire   [15:0] tmp_2_2_fu_340_p2;
wire   [15:0] tmp_2_3_fu_371_p2;
wire   [15:0] tmp_2_4_fu_402_p2;
wire   [15:0] tmp_2_5_fu_433_p2;
wire   [15:0] tmp_2_6_fu_464_p2;
wire   [15:0] tmp_2_7_fu_495_p2;
reg    ap_block_pp0_stage0_flag00011011;
reg   [4:0] i1_phi_fu_222_p6;
wire   [31:0] tmp_1_fu_266_p2;
wire   [31:0] tmp_1_1_fu_297_p2;
wire   [31:0] tmp_1_2_fu_328_p2;
wire   [31:0] tmp_1_3_fu_359_p2;
wire   [31:0] tmp_1_4_fu_390_p2;
wire   [31:0] tmp_1_5_fu_421_p2;
wire   [31:0] tmp_1_6_fu_452_p2;
wire   [31:0] tmp_1_7_fu_483_p2;
reg    ap_block_pp0_stage0_flag00001001;
wire   [5:0] i1_cast_fu_232_p1;
wire   [5:0] i_1_7_fu_236_p2;
wire  signed [31:0] tmp1_fu_258_p1;
wire   [15:0] tmp_2_fu_262_p1;
wire  signed [31:0] tmp_s_fu_289_p1;
wire   [15:0] tmp_10_fu_293_p1;
wire  signed [31:0] tmp_9_fu_320_p1;
wire   [15:0] tmp_11_fu_324_p1;
wire  signed [31:0] tmp_3_fu_351_p1;
wire   [15:0] tmp_12_fu_355_p1;
wire  signed [31:0] tmp_4_fu_382_p1;
wire   [15:0] tmp_13_fu_386_p1;
wire  signed [31:0] tmp_5_fu_413_p1;
wire   [15:0] tmp_14_fu_417_p1;
wire  signed [31:0] tmp_6_fu_444_p1;
wire   [15:0] tmp_15_fu_448_p1;
wire  signed [31:0] tmp_7_fu_475_p1;
wire   [15:0] tmp_16_fu_479_p1;
reg   [1:0] ap_NS_fsm;
reg    ap_idle_pp0_0to1;
reg    ap_reset_idle_pp0;
reg    ap_idle_pp0;
wire    ap_enable_pp0;
reg    ap_condition_1051;

// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 d_o_0_1_sel_rd = 1'b0;
#0 d_o_0_1_sel_wr = 1'b0;
#0 d_o_0_1_state = 2'd0;
#0 d_o_1_1_sel_rd = 1'b0;
#0 d_o_1_1_sel_wr = 1'b0;
#0 d_o_1_1_state = 2'd0;
#0 d_o_2_1_sel_rd = 1'b0;
#0 d_o_2_1_sel_wr = 1'b0;
#0 d_o_2_1_state = 2'd0;
#0 d_o_3_1_sel_rd = 1'b0;
#0 d_o_3_1_sel_wr = 1'b0;
#0 d_o_3_1_state = 2'd0;
#0 d_o_4_1_sel_rd = 1'b0;
#0 d_o_4_1_sel_wr = 1'b0;
#0 d_o_4_1_state = 2'd0;
#0 d_o_5_1_sel_rd = 1'b0;
#0 d_o_5_1_sel_wr = 1'b0;
#0 d_o_5_1_state = 2'd0;
#0 d_o_6_1_sel_rd = 1'b0;
#0 d_o_6_1_sel_wr = 1'b0;
#0 d_o_6_1_state = 2'd0;
#0 d_o_7_1_sel_rd = 1'b0;
#0 d_o_7_1_sel_wr = 1'b0;
#0 d_o_7_1_state = 2'd0;
#0 d_i_0_0_sel_rd = 1'b0;
#0 d_i_0_0_sel_wr = 1'b0;
#0 d_i_0_0_state = 2'd0;
#0 d_i_1_0_sel_rd = 1'b0;
#0 d_i_1_0_sel_wr = 1'b0;
#0 d_i_1_0_state = 2'd0;
#0 d_i_2_0_sel_rd = 1'b0;
#0 d_i_2_0_sel_wr = 1'b0;
#0 d_i_2_0_state = 2'd0;
#0 d_i_3_0_sel_rd = 1'b0;
#0 d_i_3_0_sel_wr = 1'b0;
#0 d_i_3_0_state = 2'd0;
#0 d_i_4_0_sel_rd = 1'b0;
#0 d_i_4_0_sel_wr = 1'b0;
#0 d_i_4_0_state = 2'd0;
#0 d_i_5_0_sel_rd = 1'b0;
#0 d_i_5_0_sel_wr = 1'b0;
#0 d_i_5_0_state = 2'd0;
#0 d_i_6_0_sel_rd = 1'b0;
#0 d_i_6_0_sel_wr = 1'b0;
#0 d_i_6_0_state = 2'd0;
#0 d_i_7_0_sel_rd = 1'b0;
#0 d_i_7_0_sel_wr = 1'b0;
#0 d_i_7_0_state = 2'd0;
#0 acc_0 = 32'd0;
#0 acc_1 = 32'd0;
#0 acc_2 = 32'd0;
#0 acc_3 = 32'd0;
#0 acc_4 = 32'd0;
#0 acc_5 = 32'd0;
#0 acc_6 = 32'd0;
#0 acc_7 = 32'd0;
end

axi_interfaces_AXILiteS_s_axi #(
    .C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
    .C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
axi_interfaces_AXILiteS_s_axi_U(
    .AWVALID(s_axi_AXILiteS_AWVALID),
    .AWREADY(s_axi_AXILiteS_AWREADY),
    .AWADDR(s_axi_AXILiteS_AWADDR),
    .WVALID(s_axi_AXILiteS_WVALID),
    .WREADY(s_axi_AXILiteS_WREADY),
    .WDATA(s_axi_AXILiteS_WDATA),
    .WSTRB(s_axi_AXILiteS_WSTRB),
    .ARVALID(s_axi_AXILiteS_ARVALID),
    .ARREADY(s_axi_AXILiteS_ARREADY),
    .ARADDR(s_axi_AXILiteS_ARADDR),
    .RVALID(s_axi_AXILiteS_RVALID),
    .RREADY(s_axi_AXILiteS_RREADY),
    .RDATA(s_axi_AXILiteS_RDATA),
    .RRESP(s_axi_AXILiteS_RRESP),
    .BVALID(s_axi_AXILiteS_BVALID),
    .BREADY(s_axi_AXILiteS_BREADY),
    .BRESP(s_axi_AXILiteS_BRESP),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .ap_start(ap_start),
    .interrupt(interrupt),
    .ap_ready(ap_ready),
    .ap_done(ap_done),
    .ap_idle(ap_idle)
);

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_enable_reg_pp0_iter1 <= 1'b0;
    end else begin
        if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0))) begin
            ap_enable_reg_pp0_iter1 <= ap_start;
        end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
            ap_enable_reg_pp0_iter1 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_enable_reg_pp0_iter2 <= 1'b0;
    end else begin
        if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
            ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
        end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
            ap_enable_reg_pp0_iter2 <= 1'b0;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_0_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_0_0_ack_out) & (1'b1 == d_i_0_0_vld_out))) begin
            d_i_0_0_sel_rd <= ~d_i_0_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_0_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_in))) begin
            d_i_0_0_sel_wr <= ~d_i_0_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_0_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_out) & (2'd3 == d_i_0_0_state)) | ((1'b0 == d_i_0_0_vld_in) & (2'd2 == d_i_0_0_state)))) begin
            d_i_0_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_0_0_vld_in) & (1'b0 == d_i_0_0_ack_out) & (2'd3 == d_i_0_0_state)) | ((1'b0 == d_i_0_0_ack_out) & (2'd1 == d_i_0_0_state)))) begin
            d_i_0_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_0_0_vld_in) & (2'd2 == d_i_0_0_state)) | ((1'b1 == d_i_0_0_ack_out) & (2'd1 == d_i_0_0_state)) | ((2'd3 == d_i_0_0_state) & ~((1'b1 == d_i_0_0_vld_in) & (1'b0 == d_i_0_0_ack_out)) & ~((1'b0 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_out))))) begin
            d_i_0_0_state <= 2'd3;
        end else begin
            d_i_0_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_1_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_1_0_ack_out) & (1'b1 == d_i_1_0_vld_out))) begin
            d_i_1_0_sel_rd <= ~d_i_1_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_1_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_in))) begin
            d_i_1_0_sel_wr <= ~d_i_1_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_1_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_out) & (2'd3 == d_i_1_0_state)) | ((1'b0 == d_i_1_0_vld_in) & (2'd2 == d_i_1_0_state)))) begin
            d_i_1_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_1_0_vld_in) & (1'b0 == d_i_1_0_ack_out) & (2'd3 == d_i_1_0_state)) | ((1'b0 == d_i_1_0_ack_out) & (2'd1 == d_i_1_0_state)))) begin
            d_i_1_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_1_0_vld_in) & (2'd2 == d_i_1_0_state)) | ((1'b1 == d_i_1_0_ack_out) & (2'd1 == d_i_1_0_state)) | ((2'd3 == d_i_1_0_state) & ~((1'b1 == d_i_1_0_vld_in) & (1'b0 == d_i_1_0_ack_out)) & ~((1'b0 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_out))))) begin
            d_i_1_0_state <= 2'd3;
        end else begin
            d_i_1_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_2_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_2_0_ack_out) & (1'b1 == d_i_2_0_vld_out))) begin
            d_i_2_0_sel_rd <= ~d_i_2_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_2_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_in))) begin
            d_i_2_0_sel_wr <= ~d_i_2_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_2_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_out) & (2'd3 == d_i_2_0_state)) | ((1'b0 == d_i_2_0_vld_in) & (2'd2 == d_i_2_0_state)))) begin
            d_i_2_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_2_0_vld_in) & (1'b0 == d_i_2_0_ack_out) & (2'd3 == d_i_2_0_state)) | ((1'b0 == d_i_2_0_ack_out) & (2'd1 == d_i_2_0_state)))) begin
            d_i_2_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_2_0_vld_in) & (2'd2 == d_i_2_0_state)) | ((1'b1 == d_i_2_0_ack_out) & (2'd1 == d_i_2_0_state)) | ((2'd3 == d_i_2_0_state) & ~((1'b1 == d_i_2_0_vld_in) & (1'b0 == d_i_2_0_ack_out)) & ~((1'b0 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_out))))) begin
            d_i_2_0_state <= 2'd3;
        end else begin
            d_i_2_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_3_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_3_0_ack_out) & (1'b1 == d_i_3_0_vld_out))) begin
            d_i_3_0_sel_rd <= ~d_i_3_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_3_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_in))) begin
            d_i_3_0_sel_wr <= ~d_i_3_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_3_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_out) & (2'd3 == d_i_3_0_state)) | ((1'b0 == d_i_3_0_vld_in) & (2'd2 == d_i_3_0_state)))) begin
            d_i_3_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_3_0_vld_in) & (1'b0 == d_i_3_0_ack_out) & (2'd3 == d_i_3_0_state)) | ((1'b0 == d_i_3_0_ack_out) & (2'd1 == d_i_3_0_state)))) begin
            d_i_3_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_3_0_vld_in) & (2'd2 == d_i_3_0_state)) | ((1'b1 == d_i_3_0_ack_out) & (2'd1 == d_i_3_0_state)) | ((2'd3 == d_i_3_0_state) & ~((1'b1 == d_i_3_0_vld_in) & (1'b0 == d_i_3_0_ack_out)) & ~((1'b0 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_out))))) begin
            d_i_3_0_state <= 2'd3;
        end else begin
            d_i_3_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_4_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_4_0_ack_out) & (1'b1 == d_i_4_0_vld_out))) begin
            d_i_4_0_sel_rd <= ~d_i_4_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_4_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_in))) begin
            d_i_4_0_sel_wr <= ~d_i_4_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_4_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_out) & (2'd3 == d_i_4_0_state)) | ((1'b0 == d_i_4_0_vld_in) & (2'd2 == d_i_4_0_state)))) begin
            d_i_4_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_4_0_vld_in) & (1'b0 == d_i_4_0_ack_out) & (2'd3 == d_i_4_0_state)) | ((1'b0 == d_i_4_0_ack_out) & (2'd1 == d_i_4_0_state)))) begin
            d_i_4_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_4_0_vld_in) & (2'd2 == d_i_4_0_state)) | ((1'b1 == d_i_4_0_ack_out) & (2'd1 == d_i_4_0_state)) | ((2'd3 == d_i_4_0_state) & ~((1'b1 == d_i_4_0_vld_in) & (1'b0 == d_i_4_0_ack_out)) & ~((1'b0 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_out))))) begin
            d_i_4_0_state <= 2'd3;
        end else begin
            d_i_4_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_5_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_5_0_ack_out) & (1'b1 == d_i_5_0_vld_out))) begin
            d_i_5_0_sel_rd <= ~d_i_5_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_5_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_in))) begin
            d_i_5_0_sel_wr <= ~d_i_5_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_5_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_out) & (2'd3 == d_i_5_0_state)) | ((1'b0 == d_i_5_0_vld_in) & (2'd2 == d_i_5_0_state)))) begin
            d_i_5_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_5_0_vld_in) & (1'b0 == d_i_5_0_ack_out) & (2'd3 == d_i_5_0_state)) | ((1'b0 == d_i_5_0_ack_out) & (2'd1 == d_i_5_0_state)))) begin
            d_i_5_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_5_0_vld_in) & (2'd2 == d_i_5_0_state)) | ((1'b1 == d_i_5_0_ack_out) & (2'd1 == d_i_5_0_state)) | ((2'd3 == d_i_5_0_state) & ~((1'b1 == d_i_5_0_vld_in) & (1'b0 == d_i_5_0_ack_out)) & ~((1'b0 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_out))))) begin
            d_i_5_0_state <= 2'd3;
        end else begin
            d_i_5_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_6_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_6_0_ack_out) & (1'b1 == d_i_6_0_vld_out))) begin
            d_i_6_0_sel_rd <= ~d_i_6_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_6_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_in))) begin
            d_i_6_0_sel_wr <= ~d_i_6_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_6_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_out) & (2'd3 == d_i_6_0_state)) | ((1'b0 == d_i_6_0_vld_in) & (2'd2 == d_i_6_0_state)))) begin
            d_i_6_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_6_0_vld_in) & (1'b0 == d_i_6_0_ack_out) & (2'd3 == d_i_6_0_state)) | ((1'b0 == d_i_6_0_ack_out) & (2'd1 == d_i_6_0_state)))) begin
            d_i_6_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_6_0_vld_in) & (2'd2 == d_i_6_0_state)) | ((1'b1 == d_i_6_0_ack_out) & (2'd1 == d_i_6_0_state)) | ((2'd3 == d_i_6_0_state) & ~((1'b1 == d_i_6_0_vld_in) & (1'b0 == d_i_6_0_ack_out)) & ~((1'b0 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_out))))) begin
            d_i_6_0_state <= 2'd3;
        end else begin
            d_i_6_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_7_0_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_i_7_0_ack_out) & (1'b1 == d_i_7_0_vld_out))) begin
            d_i_7_0_sel_rd <= ~d_i_7_0_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_7_0_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_in))) begin
            d_i_7_0_sel_wr <= ~d_i_7_0_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_i_7_0_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_out) & (2'd3 == d_i_7_0_state)) | ((1'b0 == d_i_7_0_vld_in) & (2'd2 == d_i_7_0_state)))) begin
            d_i_7_0_state <= 2'd2;
        end else if ((((1'b1 == d_i_7_0_vld_in) & (1'b0 == d_i_7_0_ack_out) & (2'd3 == d_i_7_0_state)) | ((1'b0 == d_i_7_0_ack_out) & (2'd1 == d_i_7_0_state)))) begin
            d_i_7_0_state <= 2'd1;
        end else if ((((1'b1 == d_i_7_0_vld_in) & (2'd2 == d_i_7_0_state)) | ((1'b1 == d_i_7_0_ack_out) & (2'd1 == d_i_7_0_state)) | ((2'd3 == d_i_7_0_state) & ~((1'b1 == d_i_7_0_vld_in) & (1'b0 == d_i_7_0_ack_out)) & ~((1'b0 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_out))))) begin
            d_i_7_0_state <= 2'd3;
        end else begin
            d_i_7_0_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_0_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_0_1_ack_out) & (1'b1 == d_o_0_1_vld_out))) begin
            d_o_0_1_sel_rd <= ~d_o_0_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_0_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_in))) begin
            d_o_0_1_sel_wr <= ~d_o_0_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_0_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd3)) | ((1'b0 == d_o_0_1_vld_in) & (d_o_0_1_state == 2'd2)))) begin
            d_o_0_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_0_1_vld_in) & (1'b0 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd3)) | ((1'b0 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd1)))) begin
            d_o_0_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_0_1_vld_in) & (d_o_0_1_state == 2'd2)) | ((1'b1 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd1)) | ((d_o_0_1_state == 2'd3) & ~((1'b1 == d_o_0_1_vld_in) & (1'b0 == d_o_0_1_ack_out)) & ~((1'b0 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_out))))) begin
            d_o_0_1_state <= 2'd3;
        end else begin
            d_o_0_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_1_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_1_1_ack_out) & (1'b1 == d_o_1_1_vld_out))) begin
            d_o_1_1_sel_rd <= ~d_o_1_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_1_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_in))) begin
            d_o_1_1_sel_wr <= ~d_o_1_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_1_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_out) & (2'd3 == d_o_1_1_state)) | ((1'b0 == d_o_1_1_vld_in) & (2'd2 == d_o_1_1_state)))) begin
            d_o_1_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_1_1_vld_in) & (1'b0 == d_o_1_1_ack_out) & (2'd3 == d_o_1_1_state)) | ((1'b0 == d_o_1_1_ack_out) & (2'd1 == d_o_1_1_state)))) begin
            d_o_1_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_1_1_vld_in) & (2'd2 == d_o_1_1_state)) | ((1'b1 == d_o_1_1_ack_out) & (2'd1 == d_o_1_1_state)) | ((2'd3 == d_o_1_1_state) & ~((1'b1 == d_o_1_1_vld_in) & (1'b0 == d_o_1_1_ack_out)) & ~((1'b0 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_out))))) begin
            d_o_1_1_state <= 2'd3;
        end else begin
            d_o_1_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_2_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_2_1_ack_out) & (1'b1 == d_o_2_1_vld_out))) begin
            d_o_2_1_sel_rd <= ~d_o_2_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_2_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_in))) begin
            d_o_2_1_sel_wr <= ~d_o_2_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_2_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_out) & (2'd3 == d_o_2_1_state)) | ((1'b0 == d_o_2_1_vld_in) & (2'd2 == d_o_2_1_state)))) begin
            d_o_2_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_2_1_vld_in) & (1'b0 == d_o_2_1_ack_out) & (2'd3 == d_o_2_1_state)) | ((1'b0 == d_o_2_1_ack_out) & (2'd1 == d_o_2_1_state)))) begin
            d_o_2_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_2_1_vld_in) & (2'd2 == d_o_2_1_state)) | ((1'b1 == d_o_2_1_ack_out) & (2'd1 == d_o_2_1_state)) | ((2'd3 == d_o_2_1_state) & ~((1'b1 == d_o_2_1_vld_in) & (1'b0 == d_o_2_1_ack_out)) & ~((1'b0 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_out))))) begin
            d_o_2_1_state <= 2'd3;
        end else begin
            d_o_2_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_3_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_3_1_ack_out) & (1'b1 == d_o_3_1_vld_out))) begin
            d_o_3_1_sel_rd <= ~d_o_3_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_3_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_in))) begin
            d_o_3_1_sel_wr <= ~d_o_3_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_3_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_out) & (2'd3 == d_o_3_1_state)) | ((1'b0 == d_o_3_1_vld_in) & (2'd2 == d_o_3_1_state)))) begin
            d_o_3_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_3_1_vld_in) & (1'b0 == d_o_3_1_ack_out) & (2'd3 == d_o_3_1_state)) | ((1'b0 == d_o_3_1_ack_out) & (2'd1 == d_o_3_1_state)))) begin
            d_o_3_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_3_1_vld_in) & (2'd2 == d_o_3_1_state)) | ((1'b1 == d_o_3_1_ack_out) & (2'd1 == d_o_3_1_state)) | ((2'd3 == d_o_3_1_state) & ~((1'b1 == d_o_3_1_vld_in) & (1'b0 == d_o_3_1_ack_out)) & ~((1'b0 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_out))))) begin
            d_o_3_1_state <= 2'd3;
        end else begin
            d_o_3_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_4_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_4_1_ack_out) & (1'b1 == d_o_4_1_vld_out))) begin
            d_o_4_1_sel_rd <= ~d_o_4_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_4_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_in))) begin
            d_o_4_1_sel_wr <= ~d_o_4_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_4_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_out) & (2'd3 == d_o_4_1_state)) | ((1'b0 == d_o_4_1_vld_in) & (2'd2 == d_o_4_1_state)))) begin
            d_o_4_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_4_1_vld_in) & (1'b0 == d_o_4_1_ack_out) & (2'd3 == d_o_4_1_state)) | ((1'b0 == d_o_4_1_ack_out) & (2'd1 == d_o_4_1_state)))) begin
            d_o_4_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_4_1_vld_in) & (2'd2 == d_o_4_1_state)) | ((1'b1 == d_o_4_1_ack_out) & (2'd1 == d_o_4_1_state)) | ((2'd3 == d_o_4_1_state) & ~((1'b1 == d_o_4_1_vld_in) & (1'b0 == d_o_4_1_ack_out)) & ~((1'b0 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_out))))) begin
            d_o_4_1_state <= 2'd3;
        end else begin
            d_o_4_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_5_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_5_1_ack_out) & (1'b1 == d_o_5_1_vld_out))) begin
            d_o_5_1_sel_rd <= ~d_o_5_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_5_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_in))) begin
            d_o_5_1_sel_wr <= ~d_o_5_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_5_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_out) & (2'd3 == d_o_5_1_state)) | ((1'b0 == d_o_5_1_vld_in) & (2'd2 == d_o_5_1_state)))) begin
            d_o_5_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_5_1_vld_in) & (1'b0 == d_o_5_1_ack_out) & (2'd3 == d_o_5_1_state)) | ((1'b0 == d_o_5_1_ack_out) & (2'd1 == d_o_5_1_state)))) begin
            d_o_5_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_5_1_vld_in) & (2'd2 == d_o_5_1_state)) | ((1'b1 == d_o_5_1_ack_out) & (2'd1 == d_o_5_1_state)) | ((2'd3 == d_o_5_1_state) & ~((1'b1 == d_o_5_1_vld_in) & (1'b0 == d_o_5_1_ack_out)) & ~((1'b0 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_out))))) begin
            d_o_5_1_state <= 2'd3;
        end else begin
            d_o_5_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_6_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_6_1_ack_out) & (1'b1 == d_o_6_1_vld_out))) begin
            d_o_6_1_sel_rd <= ~d_o_6_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_6_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_in))) begin
            d_o_6_1_sel_wr <= ~d_o_6_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_6_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_out) & (2'd3 == d_o_6_1_state)) | ((1'b0 == d_o_6_1_vld_in) & (2'd2 == d_o_6_1_state)))) begin
            d_o_6_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_6_1_vld_in) & (1'b0 == d_o_6_1_ack_out) & (2'd3 == d_o_6_1_state)) | ((1'b0 == d_o_6_1_ack_out) & (2'd1 == d_o_6_1_state)))) begin
            d_o_6_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_6_1_vld_in) & (2'd2 == d_o_6_1_state)) | ((1'b1 == d_o_6_1_ack_out) & (2'd1 == d_o_6_1_state)) | ((2'd3 == d_o_6_1_state) & ~((1'b1 == d_o_6_1_vld_in) & (1'b0 == d_o_6_1_ack_out)) & ~((1'b0 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_out))))) begin
            d_o_6_1_state <= 2'd3;
        end else begin
            d_o_6_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_7_1_sel_rd <= 1'b0;
    end else begin
        if (((1'b1 == d_o_7_1_ack_out) & (1'b1 == d_o_7_1_vld_out))) begin
            d_o_7_1_sel_rd <= ~d_o_7_1_sel_rd;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_7_1_sel_wr <= 1'b0;
    end else begin
        if (((1'b1 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_in))) begin
            d_o_7_1_sel_wr <= ~d_o_7_1_sel_wr;
        end
    end
end

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        d_o_7_1_state <= 2'd0;
    end else begin
        if ((((1'b0 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_out) & (2'd3 == d_o_7_1_state)) | ((1'b0 == d_o_7_1_vld_in) & (2'd2 == d_o_7_1_state)))) begin
            d_o_7_1_state <= 2'd2;
        end else if ((((1'b1 == d_o_7_1_vld_in) & (1'b0 == d_o_7_1_ack_out) & (2'd3 == d_o_7_1_state)) | ((1'b0 == d_o_7_1_ack_out) & (2'd1 == d_o_7_1_state)))) begin
            d_o_7_1_state <= 2'd1;
        end else if ((((1'b1 == d_o_7_1_vld_in) & (2'd2 == d_o_7_1_state)) | ((1'b1 == d_o_7_1_ack_out) & (2'd1 == d_o_7_1_state)) | ((2'd3 == d_o_7_1_state) & ~((1'b1 == d_o_7_1_vld_in) & (1'b0 == d_o_7_1_ack_out)) & ~((1'b0 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_out))))) begin
            d_o_7_1_state <= 2'd3;
        end else begin
            d_o_7_1_state <= 2'd2;
        end
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond_reg_507))) begin
        i1_reg_218 <= tmp_17_reg_502;
    end else if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd1 == exitcond_reg_507)))) begin
        i1_reg_218 <= 5'd0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        acc_0 <= tmp_1_fu_266_p2;
        acc_1 <= tmp_1_1_fu_297_p2;
        acc_2 <= tmp_1_2_fu_328_p2;
        acc_3 <= tmp_1_3_fu_359_p2;
        acc_4 <= tmp_1_4_fu_390_p2;
        acc_5 <= tmp_1_5_fu_421_p2;
        acc_6 <= tmp_1_6_fu_452_p2;
        acc_7 <= tmp_1_7_fu_483_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        ap_reg_pp0_iter1_exitcond_reg_507 <= exitcond_reg_507;
        exitcond_reg_507 <= exitcond_fu_246_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_0_0_load_A)) begin
        d_i_0_0_payload_A <= d_i_0_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_0_0_load_B)) begin
        d_i_0_0_payload_B <= d_i_0_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_1_0_load_A)) begin
        d_i_1_0_payload_A <= d_i_1_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_1_0_load_B)) begin
        d_i_1_0_payload_B <= d_i_1_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_2_0_load_A)) begin
        d_i_2_0_payload_A <= d_i_2_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_2_0_load_B)) begin
        d_i_2_0_payload_B <= d_i_2_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_3_0_load_A)) begin
        d_i_3_0_payload_A <= d_i_3_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_3_0_load_B)) begin
        d_i_3_0_payload_B <= d_i_3_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_4_0_load_A)) begin
        d_i_4_0_payload_A <= d_i_4_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_4_0_load_B)) begin
        d_i_4_0_payload_B <= d_i_4_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_5_0_load_A)) begin
        d_i_5_0_payload_A <= d_i_5_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_5_0_load_B)) begin
        d_i_5_0_payload_B <= d_i_5_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_6_0_load_A)) begin
        d_i_6_0_payload_A <= d_i_6_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_6_0_load_B)) begin
        d_i_6_0_payload_B <= d_i_6_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_7_0_load_A)) begin
        d_i_7_0_payload_A <= d_i_7_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_i_7_0_load_B)) begin
        d_i_7_0_payload_B <= d_i_7_TDATA;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_0_1_load_A)) begin
        d_o_0_1_payload_A <= tmp_8_fu_278_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_0_1_load_B)) begin
        d_o_0_1_payload_B <= tmp_8_fu_278_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_1_1_load_A)) begin
        d_o_1_1_payload_A <= tmp_2_1_fu_309_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_1_1_load_B)) begin
        d_o_1_1_payload_B <= tmp_2_1_fu_309_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_2_1_load_A)) begin
        d_o_2_1_payload_A <= tmp_2_2_fu_340_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_2_1_load_B)) begin
        d_o_2_1_payload_B <= tmp_2_2_fu_340_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_3_1_load_A)) begin
        d_o_3_1_payload_A <= tmp_2_3_fu_371_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_3_1_load_B)) begin
        d_o_3_1_payload_B <= tmp_2_3_fu_371_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_4_1_load_A)) begin
        d_o_4_1_payload_A <= tmp_2_4_fu_402_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_4_1_load_B)) begin
        d_o_4_1_payload_B <= tmp_2_4_fu_402_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_5_1_load_A)) begin
        d_o_5_1_payload_A <= tmp_2_5_fu_433_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_5_1_load_B)) begin
        d_o_5_1_payload_B <= tmp_2_5_fu_433_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_6_1_load_A)) begin
        d_o_6_1_payload_A <= tmp_2_6_fu_464_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_6_1_load_B)) begin
        d_o_6_1_payload_B <= tmp_2_6_fu_464_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_7_1_load_A)) begin
        d_o_7_1_payload_A <= tmp_2_7_fu_495_p2;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == d_o_7_1_load_B)) begin
        d_o_7_1_payload_B <= tmp_2_7_fu_495_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        tmp_17_reg_502 <= tmp_17_fu_242_p1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd1 == ap_reg_pp0_iter1_exitcond_reg_507))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2))) begin
        ap_idle_pp0 = 1'b1;
    end else begin
        ap_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
        ap_idle_pp0_0to1 = 1'b1;
    end else begin
        ap_idle_pp0_0to1 = 1'b0;
    end
end

always @ (*) begin
    if (((exitcond_fu_246_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to1))) begin
        ap_reset_idle_pp0 = 1'b1;
    end else begin
        ap_reset_idle_pp0 = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_0_0_ack_out = 1'b1;
    end else begin
        d_i_0_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_0_0_sel)) begin
        d_i_0_0_data_out = d_i_0_0_payload_B;
    end else begin
        d_i_0_0_data_out = d_i_0_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_0_TDATA_blk_n = d_i_0_0_state[1'd0];
    end else begin
        d_i_0_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_1_0_ack_out = 1'b1;
    end else begin
        d_i_1_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_1_0_sel)) begin
        d_i_1_0_data_out = d_i_1_0_payload_B;
    end else begin
        d_i_1_0_data_out = d_i_1_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_1_TDATA_blk_n = d_i_1_0_state[1'd0];
    end else begin
        d_i_1_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_2_0_ack_out = 1'b1;
    end else begin
        d_i_2_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_2_0_sel)) begin
        d_i_2_0_data_out = d_i_2_0_payload_B;
    end else begin
        d_i_2_0_data_out = d_i_2_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_2_TDATA_blk_n = d_i_2_0_state[1'd0];
    end else begin
        d_i_2_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_3_0_ack_out = 1'b1;
    end else begin
        d_i_3_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_3_0_sel)) begin
        d_i_3_0_data_out = d_i_3_0_payload_B;
    end else begin
        d_i_3_0_data_out = d_i_3_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_3_TDATA_blk_n = d_i_3_0_state[1'd0];
    end else begin
        d_i_3_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_4_0_ack_out = 1'b1;
    end else begin
        d_i_4_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_4_0_sel)) begin
        d_i_4_0_data_out = d_i_4_0_payload_B;
    end else begin
        d_i_4_0_data_out = d_i_4_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_4_TDATA_blk_n = d_i_4_0_state[1'd0];
    end else begin
        d_i_4_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_5_0_ack_out = 1'b1;
    end else begin
        d_i_5_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_5_0_sel)) begin
        d_i_5_0_data_out = d_i_5_0_payload_B;
    end else begin
        d_i_5_0_data_out = d_i_5_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_5_TDATA_blk_n = d_i_5_0_state[1'd0];
    end else begin
        d_i_5_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_6_0_ack_out = 1'b1;
    end else begin
        d_i_6_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_6_0_sel)) begin
        d_i_6_0_data_out = d_i_6_0_payload_B;
    end else begin
        d_i_6_0_data_out = d_i_6_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_6_TDATA_blk_n = d_i_6_0_state[1'd0];
    end else begin
        d_i_6_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_i_7_0_ack_out = 1'b1;
    end else begin
        d_i_7_0_ack_out = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == d_i_7_0_sel)) begin
        d_i_7_0_data_out = d_i_7_0_payload_B;
    end else begin
        d_i_7_0_data_out = d_i_7_0_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
        d_i_7_TDATA_blk_n = d_i_7_0_state[1'd0];
    end else begin
        d_i_7_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_0_1_sel)) begin
        d_o_0_1_data_out = d_o_0_1_payload_B;
    end else begin
        d_o_0_1_data_out = d_o_0_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_0_1_vld_in = 1'b1;
    end else begin
        d_o_0_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_0_TDATA_blk_n = d_o_0_1_state[1'd1];
    end else begin
        d_o_0_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_1_1_sel)) begin
        d_o_1_1_data_out = d_o_1_1_payload_B;
    end else begin
        d_o_1_1_data_out = d_o_1_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_1_1_vld_in = 1'b1;
    end else begin
        d_o_1_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_1_TDATA_blk_n = d_o_1_1_state[1'd1];
    end else begin
        d_o_1_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_2_1_sel)) begin
        d_o_2_1_data_out = d_o_2_1_payload_B;
    end else begin
        d_o_2_1_data_out = d_o_2_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_2_1_vld_in = 1'b1;
    end else begin
        d_o_2_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_2_TDATA_blk_n = d_o_2_1_state[1'd1];
    end else begin
        d_o_2_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_3_1_sel)) begin
        d_o_3_1_data_out = d_o_3_1_payload_B;
    end else begin
        d_o_3_1_data_out = d_o_3_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_3_1_vld_in = 1'b1;
    end else begin
        d_o_3_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_3_TDATA_blk_n = d_o_3_1_state[1'd1];
    end else begin
        d_o_3_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_4_1_sel)) begin
        d_o_4_1_data_out = d_o_4_1_payload_B;
    end else begin
        d_o_4_1_data_out = d_o_4_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_4_1_vld_in = 1'b1;
    end else begin
        d_o_4_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_4_TDATA_blk_n = d_o_4_1_state[1'd1];
    end else begin
        d_o_4_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_5_1_sel)) begin
        d_o_5_1_data_out = d_o_5_1_payload_B;
    end else begin
        d_o_5_1_data_out = d_o_5_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_5_1_vld_in = 1'b1;
    end else begin
        d_o_5_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_5_TDATA_blk_n = d_o_5_1_state[1'd1];
    end else begin
        d_o_5_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_6_1_sel)) begin
        d_o_6_1_data_out = d_o_6_1_payload_B;
    end else begin
        d_o_6_1_data_out = d_o_6_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_6_1_vld_in = 1'b1;
    end else begin
        d_o_6_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_6_TDATA_blk_n = d_o_6_1_state[1'd1];
    end else begin
        d_o_6_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((1'b1 == d_o_7_1_sel)) begin
        d_o_7_1_data_out = d_o_7_1_payload_B;
    end else begin
        d_o_7_1_data_out = d_o_7_1_payload_A;
    end
end

always @ (*) begin
    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
        d_o_7_1_vld_in = 1'b1;
    end else begin
        d_o_7_1_vld_in = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
        d_o_7_TDATA_blk_n = d_o_7_1_state[1'd1];
    end else begin
        d_o_7_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if ((ap_condition_1051 == 1'b1)) begin
        if ((1'd1 == exitcond_reg_507)) begin
            i1_phi_fu_222_p6 = 5'd0;
        end else if ((1'd0 == exitcond_reg_507)) begin
            i1_phi_fu_222_p6 = tmp_17_reg_502;
        end else begin
            i1_phi_fu_222_p6 = i1_reg_218;
        end
    end else begin
        i1_phi_fu_222_p6 = i1_reg_218;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_pp0_stage0 : begin
            if ((ap_reset_idle_pp0 == 1'b0)) begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end else if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_reset_idle_pp0))) begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end else begin
                ap_NS_fsm = ap_ST_fsm_pp0_stage0;
            end
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_pp0_stage0_flag00001001 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011001 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out) | (1'b1 == ap_block_state4_io)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in) | (1'b1 == ap_block_state3_io)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end

always @ (*) begin
    ap_block_pp0_stage0_flag00011011 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out) | (1'b1 == ap_block_state4_io)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in) | (1'b1 == ap_block_state3_io)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end

assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);

always @ (*) begin
    ap_block_state3_io = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end

always @ (*) begin
    ap_block_state3_pp0_stage0_iter2 = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end

always @ (*) begin
    ap_block_state4_io = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end

always @ (*) begin
    ap_block_state4_pp0_stage0_iter1 = ((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out));
end

always @ (*) begin
    ap_condition_1051 = ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0));
end

assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);

assign ap_enable_reg_pp0_iter0 = ap_start;

always @ (*) begin
    ap_rst_n_inv = ~ap_rst_n;
end

assign d_i_0_0_ack_in = d_i_0_0_state[1'd1];

assign d_i_0_0_load_A = (d_i_0_0_state_cmp_full & ~d_i_0_0_sel_wr);

assign d_i_0_0_load_B = (d_i_0_0_sel_wr & d_i_0_0_state_cmp_full);

assign d_i_0_0_sel = d_i_0_0_sel_rd;

assign d_i_0_0_state_cmp_full = ((d_i_0_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_0_0_vld_in = d_i_0_TVALID;

assign d_i_0_0_vld_out = d_i_0_0_state[1'd0];

assign d_i_0_TREADY = d_i_0_0_state[1'd1];

assign d_i_1_0_ack_in = d_i_1_0_state[1'd1];

assign d_i_1_0_load_A = (d_i_1_0_state_cmp_full & ~d_i_1_0_sel_wr);

assign d_i_1_0_load_B = (d_i_1_0_sel_wr & d_i_1_0_state_cmp_full);

assign d_i_1_0_sel = d_i_1_0_sel_rd;

assign d_i_1_0_state_cmp_full = ((d_i_1_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_1_0_vld_in = d_i_1_TVALID;

assign d_i_1_0_vld_out = d_i_1_0_state[1'd0];

assign d_i_1_TREADY = d_i_1_0_state[1'd1];

assign d_i_2_0_ack_in = d_i_2_0_state[1'd1];

assign d_i_2_0_load_A = (d_i_2_0_state_cmp_full & ~d_i_2_0_sel_wr);

assign d_i_2_0_load_B = (d_i_2_0_sel_wr & d_i_2_0_state_cmp_full);

assign d_i_2_0_sel = d_i_2_0_sel_rd;

assign d_i_2_0_state_cmp_full = ((d_i_2_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_2_0_vld_in = d_i_2_TVALID;

assign d_i_2_0_vld_out = d_i_2_0_state[1'd0];

assign d_i_2_TREADY = d_i_2_0_state[1'd1];

assign d_i_3_0_ack_in = d_i_3_0_state[1'd1];

assign d_i_3_0_load_A = (d_i_3_0_state_cmp_full & ~d_i_3_0_sel_wr);

assign d_i_3_0_load_B = (d_i_3_0_sel_wr & d_i_3_0_state_cmp_full);

assign d_i_3_0_sel = d_i_3_0_sel_rd;

assign d_i_3_0_state_cmp_full = ((d_i_3_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_3_0_vld_in = d_i_3_TVALID;

assign d_i_3_0_vld_out = d_i_3_0_state[1'd0];

assign d_i_3_TREADY = d_i_3_0_state[1'd1];

assign d_i_4_0_ack_in = d_i_4_0_state[1'd1];

assign d_i_4_0_load_A = (d_i_4_0_state_cmp_full & ~d_i_4_0_sel_wr);

assign d_i_4_0_load_B = (d_i_4_0_sel_wr & d_i_4_0_state_cmp_full);

assign d_i_4_0_sel = d_i_4_0_sel_rd;

assign d_i_4_0_state_cmp_full = ((d_i_4_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_4_0_vld_in = d_i_4_TVALID;

assign d_i_4_0_vld_out = d_i_4_0_state[1'd0];

assign d_i_4_TREADY = d_i_4_0_state[1'd1];

assign d_i_5_0_ack_in = d_i_5_0_state[1'd1];

assign d_i_5_0_load_A = (d_i_5_0_state_cmp_full & ~d_i_5_0_sel_wr);

assign d_i_5_0_load_B = (d_i_5_0_sel_wr & d_i_5_0_state_cmp_full);

assign d_i_5_0_sel = d_i_5_0_sel_rd;

assign d_i_5_0_state_cmp_full = ((d_i_5_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_5_0_vld_in = d_i_5_TVALID;

assign d_i_5_0_vld_out = d_i_5_0_state[1'd0];

assign d_i_5_TREADY = d_i_5_0_state[1'd1];

assign d_i_6_0_ack_in = d_i_6_0_state[1'd1];

assign d_i_6_0_load_A = (d_i_6_0_state_cmp_full & ~d_i_6_0_sel_wr);

assign d_i_6_0_load_B = (d_i_6_0_sel_wr & d_i_6_0_state_cmp_full);

assign d_i_6_0_sel = d_i_6_0_sel_rd;

assign d_i_6_0_state_cmp_full = ((d_i_6_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_6_0_vld_in = d_i_6_TVALID;

assign d_i_6_0_vld_out = d_i_6_0_state[1'd0];

assign d_i_6_TREADY = d_i_6_0_state[1'd1];

assign d_i_7_0_ack_in = d_i_7_0_state[1'd1];

assign d_i_7_0_load_A = (d_i_7_0_state_cmp_full & ~d_i_7_0_sel_wr);

assign d_i_7_0_load_B = (d_i_7_0_sel_wr & d_i_7_0_state_cmp_full);

assign d_i_7_0_sel = d_i_7_0_sel_rd;

assign d_i_7_0_state_cmp_full = ((d_i_7_0_state != 2'd1) ? 1'b1 : 1'b0);

assign d_i_7_0_vld_in = d_i_7_TVALID;

assign d_i_7_0_vld_out = d_i_7_0_state[1'd0];

assign d_i_7_TREADY = d_i_7_0_state[1'd1];

assign d_o_0_1_ack_in = d_o_0_1_state[1'd1];

assign d_o_0_1_ack_out = d_o_0_TREADY;

assign d_o_0_1_load_A = (d_o_0_1_state_cmp_full & ~d_o_0_1_sel_wr);

assign d_o_0_1_load_B = (d_o_0_1_sel_wr & d_o_0_1_state_cmp_full);

assign d_o_0_1_sel = d_o_0_1_sel_rd;

assign d_o_0_1_state_cmp_full = ((d_o_0_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_0_1_vld_out = d_o_0_1_state[1'd0];

assign d_o_0_TDATA = d_o_0_1_data_out;

assign d_o_0_TVALID = d_o_0_1_state[1'd0];

assign d_o_1_1_ack_in = d_o_1_1_state[1'd1];

assign d_o_1_1_ack_out = d_o_1_TREADY;

assign d_o_1_1_load_A = (d_o_1_1_state_cmp_full & ~d_o_1_1_sel_wr);

assign d_o_1_1_load_B = (d_o_1_1_sel_wr & d_o_1_1_state_cmp_full);

assign d_o_1_1_sel = d_o_1_1_sel_rd;

assign d_o_1_1_state_cmp_full = ((d_o_1_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_1_1_vld_out = d_o_1_1_state[1'd0];

assign d_o_1_TDATA = d_o_1_1_data_out;

assign d_o_1_TVALID = d_o_1_1_state[1'd0];

assign d_o_2_1_ack_in = d_o_2_1_state[1'd1];

assign d_o_2_1_ack_out = d_o_2_TREADY;

assign d_o_2_1_load_A = (d_o_2_1_state_cmp_full & ~d_o_2_1_sel_wr);

assign d_o_2_1_load_B = (d_o_2_1_sel_wr & d_o_2_1_state_cmp_full);

assign d_o_2_1_sel = d_o_2_1_sel_rd;

assign d_o_2_1_state_cmp_full = ((d_o_2_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_2_1_vld_out = d_o_2_1_state[1'd0];

assign d_o_2_TDATA = d_o_2_1_data_out;

assign d_o_2_TVALID = d_o_2_1_state[1'd0];

assign d_o_3_1_ack_in = d_o_3_1_state[1'd1];

assign d_o_3_1_ack_out = d_o_3_TREADY;

assign d_o_3_1_load_A = (d_o_3_1_state_cmp_full & ~d_o_3_1_sel_wr);

assign d_o_3_1_load_B = (d_o_3_1_sel_wr & d_o_3_1_state_cmp_full);

assign d_o_3_1_sel = d_o_3_1_sel_rd;

assign d_o_3_1_state_cmp_full = ((d_o_3_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_3_1_vld_out = d_o_3_1_state[1'd0];

assign d_o_3_TDATA = d_o_3_1_data_out;

assign d_o_3_TVALID = d_o_3_1_state[1'd0];

assign d_o_4_1_ack_in = d_o_4_1_state[1'd1];

assign d_o_4_1_ack_out = d_o_4_TREADY;

assign d_o_4_1_load_A = (d_o_4_1_state_cmp_full & ~d_o_4_1_sel_wr);

assign d_o_4_1_load_B = (d_o_4_1_sel_wr & d_o_4_1_state_cmp_full);

assign d_o_4_1_sel = d_o_4_1_sel_rd;

assign d_o_4_1_state_cmp_full = ((d_o_4_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_4_1_vld_out = d_o_4_1_state[1'd0];

assign d_o_4_TDATA = d_o_4_1_data_out;

assign d_o_4_TVALID = d_o_4_1_state[1'd0];

assign d_o_5_1_ack_in = d_o_5_1_state[1'd1];

assign d_o_5_1_ack_out = d_o_5_TREADY;

assign d_o_5_1_load_A = (d_o_5_1_state_cmp_full & ~d_o_5_1_sel_wr);

assign d_o_5_1_load_B = (d_o_5_1_sel_wr & d_o_5_1_state_cmp_full);

assign d_o_5_1_sel = d_o_5_1_sel_rd;

assign d_o_5_1_state_cmp_full = ((d_o_5_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_5_1_vld_out = d_o_5_1_state[1'd0];

assign d_o_5_TDATA = d_o_5_1_data_out;

assign d_o_5_TVALID = d_o_5_1_state[1'd0];

assign d_o_6_1_ack_in = d_o_6_1_state[1'd1];

assign d_o_6_1_ack_out = d_o_6_TREADY;

assign d_o_6_1_load_A = (d_o_6_1_state_cmp_full & ~d_o_6_1_sel_wr);

assign d_o_6_1_load_B = (d_o_6_1_sel_wr & d_o_6_1_state_cmp_full);

assign d_o_6_1_sel = d_o_6_1_sel_rd;

assign d_o_6_1_state_cmp_full = ((d_o_6_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_6_1_vld_out = d_o_6_1_state[1'd0];

assign d_o_6_TDATA = d_o_6_1_data_out;

assign d_o_6_TVALID = d_o_6_1_state[1'd0];

assign d_o_7_1_ack_in = d_o_7_1_state[1'd1];

assign d_o_7_1_ack_out = d_o_7_TREADY;

assign d_o_7_1_load_A = (d_o_7_1_state_cmp_full & ~d_o_7_1_sel_wr);

assign d_o_7_1_load_B = (d_o_7_1_sel_wr & d_o_7_1_state_cmp_full);

assign d_o_7_1_sel = d_o_7_1_sel_rd;

assign d_o_7_1_state_cmp_full = ((d_o_7_1_state != 2'd1) ? 1'b1 : 1'b0);

assign d_o_7_1_vld_out = d_o_7_1_state[1'd0];

assign d_o_7_TDATA = d_o_7_1_data_out;

assign d_o_7_TVALID = d_o_7_1_state[1'd0];

assign exitcond_fu_246_p2 = ((i_1_7_fu_236_p2 == 6'd32) ? 1'b1 : 1'b0);

assign i1_cast_fu_232_p1 = i1_phi_fu_222_p6;

assign i_1_7_fu_236_p2 = (6'd8 + i1_cast_fu_232_p1);

assign tmp1_fu_258_p1 = $signed(d_i_0_0_data_out);

assign tmp_10_fu_293_p1 = acc_1[15:0];

assign tmp_11_fu_324_p1 = acc_2[15:0];

assign tmp_12_fu_355_p1 = acc_3[15:0];

assign tmp_13_fu_386_p1 = acc_4[15:0];

assign tmp_14_fu_417_p1 = acc_5[15:0];

assign tmp_15_fu_448_p1 = acc_6[15:0];

assign tmp_16_fu_479_p1 = acc_7[15:0];

assign tmp_17_fu_242_p1 = i_1_7_fu_236_p2[4:0];

assign tmp_1_1_fu_297_p2 = ($signed(tmp_s_fu_289_p1) + $signed(acc_1));

assign tmp_1_2_fu_328_p2 = ($signed(tmp_9_fu_320_p1) + $signed(acc_2));

assign tmp_1_3_fu_359_p2 = ($signed(tmp_3_fu_351_p1) + $signed(acc_3));

assign tmp_1_4_fu_390_p2 = ($signed(tmp_4_fu_382_p1) + $signed(acc_4));

assign tmp_1_5_fu_421_p2 = ($signed(tmp_5_fu_413_p1) + $signed(acc_5));

assign tmp_1_6_fu_452_p2 = ($signed(tmp_6_fu_444_p1) + $signed(acc_6));

assign tmp_1_7_fu_483_p2 = ($signed(tmp_7_fu_475_p1) + $signed(acc_7));

assign tmp_1_fu_266_p2 = ($signed(tmp1_fu_258_p1) + $signed(acc_0));

assign tmp_2_1_fu_309_p2 = (tmp_10_fu_293_p1 + d_i_1_0_data_out);

assign tmp_2_2_fu_340_p2 = (tmp_11_fu_324_p1 + d_i_2_0_data_out);

assign tmp_2_3_fu_371_p2 = (tmp_12_fu_355_p1 + d_i_3_0_data_out);

assign tmp_2_4_fu_402_p2 = (tmp_13_fu_386_p1 + d_i_4_0_data_out);

assign tmp_2_5_fu_433_p2 = (tmp_14_fu_417_p1 + d_i_5_0_data_out);

assign tmp_2_6_fu_464_p2 = (tmp_15_fu_448_p1 + d_i_6_0_data_out);

assign tmp_2_7_fu_495_p2 = (tmp_16_fu_479_p1 + d_i_7_0_data_out);

assign tmp_2_fu_262_p1 = acc_0[15:0];

assign tmp_3_fu_351_p1 = $signed(d_i_3_0_data_out);

assign tmp_4_fu_382_p1 = $signed(d_i_4_0_data_out);

assign tmp_5_fu_413_p1 = $signed(d_i_5_0_data_out);

assign tmp_6_fu_444_p1 = $signed(d_i_6_0_data_out);

assign tmp_7_fu_475_p1 = $signed(d_i_7_0_data_out);

assign tmp_8_fu_278_p2 = (tmp_2_fu_262_p1 + d_i_0_0_data_out);

assign tmp_9_fu_320_p1 = $signed(d_i_2_0_data_out);

assign tmp_s_fu_289_p1 = $signed(d_i_1_0_data_out);

endmodule //axi_interfaces
