`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:44:46 09/24/2013
// Design Name:   Data_Parameters
// Module Name:   C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_data_parameters.v
// Project Name:  laboratorio3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Data_Parameters
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_data_parameters;

	// Inputs
	reg clock;
	reg reset;
	reg [3:0] mem_address;
	reg write_value_reg_en;
	reg [1:0] write_data_selector;

	// Outputs
	wire [3:0] write_value;

	// Instantiate the Unit Under Test (UUT)
	Data_Parameters uut (
		.clock(clock), 
		.reset(reset), 
		.mem_address(mem_address), 
		.write_value_reg_en(write_value_reg_en), 
		.write_data_selector(write_data_selector), 
		.write_value(write_value)
	);

	initial begin
		// Initialize Inputs
		clock = 0;
		reset = 0;
		mem_address = 0;
		write_value_reg_en = 0;
		write_data_selector = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

