// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult 

// ============================================================
// File Name: acl_int_mult64s.v
// Megafunction Name(s):
// 			lpm_mult
//
// Simulation Library Files(s):
// 			lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 174 10/17/2012 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult64s_s5 (
	enable,
	clock,
	dataa,
	datab,
	result);

  parameter INPUT1_WIDTH = 64;
  parameter INPUT2_WIDTH = 64;

	input	  enable;
	input	  clock;
	input	[INPUT1_WIDTH - 1 : 0]  dataa;
	input	[INPUT2_WIDTH - 1 : 0]  datab;
	(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output	reg [63:0]  result;
	(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg	[INPUT1_WIDTH - 1 : 0]  reg_dataa;
	(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg	[INPUT2_WIDTH - 1 : 0]  reg_datab;
	(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg	[INPUT1_WIDTH - 1 : 0]  reg_dataa2;
	(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg	[INPUT2_WIDTH - 1 : 0]  reg_datab2;
	
	localparam TMP1_WIDTH = (INPUT1_WIDTH > 32)? INPUT1_WIDTH : 33;
	localparam TMP2_WIDTH = (INPUT2_WIDTH > 32)? INPUT2_WIDTH : 33;

generate
if(INPUT1_WIDTH>=19 && INPUT1_WIDTH<=27 && INPUT2_WIDTH>=19 && INPUT2_WIDTH<=27)
begin
  // Use a special WYSIWYG for the 27x27 multiplier mode

  always@(posedge clock)
  begin
    if (enable)
    begin
      reg_dataa <= dataa;
      reg_datab <= datab;
    end
  end

  wire [53:0] mul_result;
  wire [26:0] inp_a;
  wire [26:0] inp_b;

  assign inp_a = reg_dataa;
  assign inp_b = reg_datab;

  sv_mult27 the_multiplier(clock,enable,inp_a,inp_b,mul_result);

  always@(*)
  begin
     result <= mul_result;
  end
end
else if(INPUT1_WIDTH == 64 && INPUT2_WIDTH >= 32 || INPUT2_WIDTH == 64 && INPUT1_WIDTH >= 32) begin : GEN_LONG_MUL //Karatsuba algorithm
  reg [63:0] temp0;
  reg [TMP1_WIDTH-1:0] R_a;
  reg [TMP2_WIDTH-1:0] R_b;
  reg [31:0] temp1, temp2;
  always@(posedge clock) begin
    if(enable) begin
      R_a <= dataa;
      R_b <= datab;
      temp0 <= R_a[31:0] * R_b[31:0];
      temp1 <= R_a[31:0] * R_b[TMP2_WIDTH-1:32];
      temp2 <= R_a[TMP1_WIDTH-1:32] * R_b[31:0];
      result[63:32] <= temp0[63:32] + temp1 + temp2;
      result[31:0] <= temp0[31:0];
    end
  end  
end
else
begin
  // Default LPM_MULT inference
  always@(posedge clock)
  begin
    if (enable)
    begin
      result <= reg_dataa2 * reg_datab2; 
      reg_dataa <= dataa;
      reg_datab <= datab;
      reg_dataa2 <= reg_dataa;
      reg_datab2 <= reg_datab;
    end
  end
end
endgenerate
endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "3"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "64"
// Retrieval info: PRIVATE: WidthB NUMERIC "64"
// Retrieval info: PRIVATE: WidthP NUMERIC "128"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "1"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "128"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL "dataa[63..0]"
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL "datab[63..0]"
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_mult64s_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
