// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date        : Thu Oct 26 22:45:01 2017
// Host        : Juice-Laptop running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_sim_netlist.v
// Design      : RAT_Mux4x1_10_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "RAT_Mux4x1_10_0_0,Mux4x1_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux4x1_10,Vivado 2016.4" *) 
(* NotValidForBitStream *)
module RAT_Mux4x1_10_0_0
   (A,
    B,
    C,
    D,
    SEL,
    X);
  input [9:0]A;
  input [9:0]B;
  input [9:0]C;
  input [9:0]D;
  input [1:0]SEL;
  output [9:0]X;

  wire [9:0]A;
  wire [9:0]B;
  wire [9:0]C;
  wire [9:0]D;
  wire [1:0]SEL;
  wire [9:0]X;

  RAT_Mux4x1_10_0_0_Mux4x1_10 U0
       (.A(A),
        .B(B),
        .C(C),
        .D(D),
        .SEL(SEL),
        .X(X));
endmodule

(* ORIG_REF_NAME = "Mux4x1_10" *) 
module RAT_Mux4x1_10_0_0_Mux4x1_10
   (X,
    D,
    B,
    C,
    SEL,
    A);
  output [9:0]X;
  input [9:0]D;
  input [9:0]B;
  input [9:0]C;
  input [1:0]SEL;
  input [9:0]A;

  wire [9:0]A;
  wire [9:0]B;
  wire [9:0]C;
  wire [9:0]D;
  wire [1:0]SEL;
  wire [9:0]X;

  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[0]_INST_0 
       (.I0(D[0]),
        .I1(B[0]),
        .I2(C[0]),
        .I3(SEL[1]),
        .I4(A[0]),
        .I5(SEL[0]),
        .O(X[0]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[1]_INST_0 
       (.I0(D[1]),
        .I1(B[1]),
        .I2(C[1]),
        .I3(SEL[1]),
        .I4(A[1]),
        .I5(SEL[0]),
        .O(X[1]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[2]_INST_0 
       (.I0(D[2]),
        .I1(B[2]),
        .I2(C[2]),
        .I3(SEL[1]),
        .I4(A[2]),
        .I5(SEL[0]),
        .O(X[2]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[3]_INST_0 
       (.I0(D[3]),
        .I1(B[3]),
        .I2(C[3]),
        .I3(SEL[1]),
        .I4(A[3]),
        .I5(SEL[0]),
        .O(X[3]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[4]_INST_0 
       (.I0(D[4]),
        .I1(B[4]),
        .I2(C[4]),
        .I3(SEL[1]),
        .I4(A[4]),
        .I5(SEL[0]),
        .O(X[4]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[5]_INST_0 
       (.I0(D[5]),
        .I1(B[5]),
        .I2(C[5]),
        .I3(SEL[1]),
        .I4(A[5]),
        .I5(SEL[0]),
        .O(X[5]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[6]_INST_0 
       (.I0(D[6]),
        .I1(B[6]),
        .I2(C[6]),
        .I3(SEL[1]),
        .I4(A[6]),
        .I5(SEL[0]),
        .O(X[6]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[7]_INST_0 
       (.I0(D[7]),
        .I1(B[7]),
        .I2(C[7]),
        .I3(SEL[1]),
        .I4(A[7]),
        .I5(SEL[0]),
        .O(X[7]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[8]_INST_0 
       (.I0(D[8]),
        .I1(B[8]),
        .I2(C[8]),
        .I3(SEL[1]),
        .I4(A[8]),
        .I5(SEL[0]),
        .O(X[8]));
  LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
    \X[9]_INST_0 
       (.I0(D[9]),
        .I1(B[9]),
        .I2(C[9]),
        .I3(SEL[1]),
        .I4(A[9]),
        .I5(SEL[0]),
        .O(X[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
