// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of aou
//
// Generated
//  by:  wig
//  on:  Mon Jun 26 16:38:04 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: aou.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: aou.v,v $
// Revision 1.3  2006/07/04 09:54:11  wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp 
//
// Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of aou
//

// No user `defines in this module


module aou
//
// Generated Module aou_i1
//
	(
		reset_i_n	// Async. Reset (CGU,PAD)
	);

	// Generated Module Inputs:
		input		reset_i_n;
	// Generated Wires:
		wire		reset_i_n;
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//




	//
	// Generated Instances and Port Mappings
	//


endmodule
//
// End of Generated Module rtl of aou
//

//
//!End of Module/s
// --------------------------------------------------------------
