// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of top
//
// Generated
//  by:  wig
//  on:  Tue Apr  1 13:31:51 2008
//  cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: top.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: top.v,v $
// Revision 1.1  2008/04/01 12:53:30  wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp 
//
// Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of top
//

// No user `defines in this module


module top
//
// Generated Module TOP
//
	(
	);

// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
		wire		clk; 
		wire		clk2_i; 
		wire		data; 
		wire		data2_i; 
		wire		ready0; 
		wire		ready1; 
		wire		ready2_0; 
		wire		ready2_1; 
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//




	//
	// Generated Instances and Port Mappings
	//
		// Generated Instance Port Map for M0
		m0 M0 (

			.clk2_o(clk2_i),
			.clk_o(clk),
			.data2_o(data2_i),
			.data_o(data),
			.ready0_i(ready0),
			.ready1_i(ready1),
			.ready2_0(ready2_0),
			.ready2_1(ready2_1)
		);
		// End of Generated Instance Port Map for M0

		// Generated Instance Port Map for N0
		n0 N0 (

			.clk2_i_i(clk2_i),
			.clk_i(clk),
			.data2_i_i(data2_i),
			.data_i(data),
			.ready0_o(ready0),
			.ready1_o(ready1),
			.ready2_0_o(ready2_0),
			.ready2_1_o(ready2_1)
		);
		// End of Generated Instance Port Map for N0



endmodule
//
// End of Generated Module rtl of top
//

//
//!End of Module/s
// --------------------------------------------------------------
