`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:00:08 11/01/2013
// Design Name:   divider
// Module Name:   C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/divider_test.v
// Project Name:  proyecto-final
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: divider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module divider_test;

	// Inputs
	reg in;
	reg [3:0] N;
	reg reset;

	// Outputs
	wire out;

	// Instantiate the Unit Under Test (UUT)
	divider uut (
		.in(in), 
		.out(out), 
		.N(N), 
		.reset(reset)
	);

	initial begin
		// Initialize Inputs
		in = 0;
		N = 0;
		reset = 1;

		// Wait 100 ns for global reset to finish
		#100;
		
		// Add stimulus here
		N = 2;
		
      #1000;
		reset = 0;
		
		

	end
      
endmodule

