`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:45:38 09/23/2013 
// Design Name: 
// Module Name:    Clock_Divider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_Divider(input clock, input reset, output reg clock_out);

	//Lleva la cuenta de los ciclos de reloj transcurridos
   reg [25:0] counter;
		
	initial 
		begin
			counter <= 26'b0;
			clock_out <= 1'b1;
		end
			
	always @(posedge clock or posedge reset)
	begin
		if(reset)
			begin
				counter <= 26'b0;
				clock_out <= 1'b1;
			end
		else
			if(counter == 26'd1134) //va convertir un clk de 50MHz a 1Hz
				begin
					counter <= 26'b0;
					clock_out <= ~clock_out;
				end
			else
				begin
					counter <= counter+1;
				end
	end	
endmodule
