// File: fpgalink_led.v
// Generated by MyHDL 0.8dev
// Date: Tue Apr 16 21:45:39 2013


`timescale 1ns/10ps

module fpgalink_led (
    IFCLK,
    RST,
    SLWR,
    SLRD,
    SLOE,
    FDIO,
    ADDR,
    FLAGA,
    FLAGB,
    FLAGC,
    FLAGD,
    PKTEND,
    leds
);
// 

input IFCLK;
input RST;
output SLWR;
wire SLWR;
output SLRD;
wire SLRD;
output SLOE;
reg SLOE;
output [7:0] FDIO;
wire [7:0] FDIO;
output [1:0] ADDR;
reg [1:0] ADDR;
input FLAGA;
input FLAGB;
input FLAGC;
input FLAGD;
output PKTEND;
reg PKTEND;
output [7:0] leds;
reg [7:0] leds;

reg f2hValid_in;
reg [7:0] dout;
reg h2fReady_in;
reg dsel;
reg fifosel;
wire [7:0] din;
reg [7:0] h2fData_out;
reg h2fValid_out;
reg [6:0] chanAddr_out;
reg [7:0] lreg;
reg [7:0] f2hData_in;
reg g_fli_is_write;
reg [3:0] g_fli_state;
reg g_fli_f2h_ready_o;
reg g_fli_is_aligned;
reg [31:0] g_fli_count;
reg [1:0] g_fli_fifop;





always @(posedge IFCLK, negedge RST) begin: FPGALINK_LED_G_FLI_HDL_SM
    if (RST == 0) begin
        g_fli_count <= 0;
        chanAddr_out <= 0;
        h2fData_out <= 0;
        dsel <= 0;
        g_fli_f2h_ready_o <= 0;
        PKTEND <= 0;
        g_fli_fifop <= 3;
        g_fli_is_write <= 0;
        fifosel <= 0;
        g_fli_state <= 4'b0000;
        dout <= 0;
        h2fValid_out <= 0;
        g_fli_is_aligned <= 0;
    end
    else begin
        case (g_fli_state)
            4'b0001: begin
                if (FLAGC) begin
                    g_fli_count <= (din << 24);
                    g_fli_state <= 4'b0010;
                end
                else begin
                    g_fli_count <= 0;
                end
            end
            4'b0010: begin
                if (FLAGC) begin
                    g_fli_count <= (g_fli_count | (din << 16));
                    g_fli_state <= 4'b0011;
                end
            end
            4'b0011: begin
                if (FLAGC) begin
                    g_fli_count <= (g_fli_count | (din << 8));
                    g_fli_state <= 4'b0100;
                end
            end
            4'b0100: begin
                if (FLAGC) begin
                    g_fli_count <= (g_fli_count | din);
                    if (g_fli_is_write) begin
                        g_fli_state <= 4'b0101;
                    end
                    else begin
                        if (h2fReady_in) begin
                            g_fli_fifop <= 2;
                            g_fli_state <= 4'b1001;
                        end
                        else begin
                            g_fli_fifop <= 3;
                            g_fli_state <= 4'b1010;
                        end
                    end
                end
            end
            4'b0101: begin
                fifosel <= 1;
                g_fli_fifop <= 3;
                if ((g_fli_count[9-1:0] == 0)) begin
                    g_fli_is_aligned <= 1'b1;
                end
                else begin
                    g_fli_is_aligned <= 1'b0;
                end
                g_fli_state <= 4'b0110;
            end
            4'b0110: begin
                if (FLAGB) begin
                    g_fli_f2h_ready_o <= 1'b1;
                end
                if ((FLAGB && f2hValid_in)) begin
                    g_fli_fifop <= 1;
                    dout <= f2hData_in;
                    dsel <= 1'b1;
                    g_fli_count <= (g_fli_count - 1);
                    if ((g_fli_count == 1)) begin
                        if (g_fli_is_aligned) begin
                            g_fli_state <= 4'b0111;
                        end
                        else begin
                            g_fli_state <= 4'b1000;
                        end
                    end
                end
                else begin
                    g_fli_fifop <= 3;
                end
            end
            4'b0111: begin
                fifosel <= 1;
                g_fli_fifop <= 3;
                g_fli_state <= 4'b0000;
            end
            4'b1000: begin
                fifosel <= 1;
                g_fli_fifop <= 3;
                PKTEND <= 1'b0;
                g_fli_state <= 4'b0000;
            end
            4'b1001: begin
                fifosel <= 0;
                if ((FLAGC && h2fReady_in)) begin
                    if ((!SLRD) !== 1) begin
                        $display("*** AssertionError ***");
                    end
                    h2fValid_out <= 1'b1;
                    h2fData_out <= din;
                    if ((g_fli_count <= 1)) begin
                        g_fli_state <= 4'b0000;
                        g_fli_count <= 0;
                    end
                    else begin
                        g_fli_count <= (g_fli_count - 1);
                    end
                end
            end
            4'b1010: begin
                if ((FLAGC && h2fReady_in)) begin
                    g_fli_state <= 4'b1001;
                    g_fli_fifop <= 2;
                end
            end
            default: begin
                g_fli_fifop <= 2;
                g_fli_count <= 0;
                h2fValid_out <= 1'b0;
                if (FLAGC) begin
                    chanAddr_out <= din[7-1:0];
                    g_fli_is_write <= din[7];
                    g_fli_state <= 4'b0001;
                end
            end
        endcase
    end
end



assign SLRD = g_fli_fifop[0];
assign SLWR = g_fli_fifop[1];



//module tristate(
//   inout  [7:0] dio,
//   input  [7:0] din,
//   output [7:0] dout,
//   input  [7:0] dsel):
   assign din = dio;
   assign dio = dsel ? dout : 8'bz;
//endmodule


always @(posedge IFCLK, negedge RST) begin: FPGALINK_LED_HDL_FL
    if (RST == 0) begin
        lreg <= 0;
    end
    else begin
        if ((h2fValid_out && (chanAddr_out == 1))) begin
            lreg <= h2fData_out;
        end
    end
end


always @(chanAddr_out, fifosel, lreg, SLRD) begin: FPGALINK_LED_HDL_ASSIGNS
    ADDR[0] = fifosel;
    ADDR[1] = 1'b1;
    SLOE = SLRD;
    f2hValid_in = 1'b1;
    h2fReady_in = 1'b1;
    leds = lreg;
    case (chanAddr_out)
        'h0: begin
            f2hData_in = 206;
        end
        'h1: begin
            f2hData_in = lreg;
        end
        default: begin
            f2hData_in = 85;
        end
    endcase
end

endmodule
