// amm_master_qsys_with_pcie_mm_interconnect_1.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 185

`timescale 1 ps / 1 ps
module amm_master_qsys_with_pcie_mm_interconnect_1 (
		input  wire        clk_50_clk_clk,                                              //                                            clk_50_clk.clk
		input  wire        pcie_ip_pcie_core_clk_clk,                                   //                                 pcie_ip_pcie_core_clk.clk
		input  wire        custom_module_reset_reset_bridge_in_reset_reset,             //             custom_module_reset_reset_bridge_in_reset.reset
		input  wire        pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset, // pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset.reset
		input  wire [31:0] pcie_ip_bar1_0_address,                                      //                                        pcie_ip_bar1_0.address
		output wire        pcie_ip_bar1_0_waitrequest,                                  //                                                      .waitrequest
		input  wire [6:0]  pcie_ip_bar1_0_burstcount,                                   //                                                      .burstcount
		input  wire [7:0]  pcie_ip_bar1_0_byteenable,                                   //                                                      .byteenable
		input  wire        pcie_ip_bar1_0_read,                                         //                                                      .read
		output wire [63:0] pcie_ip_bar1_0_readdata,                                     //                                                      .readdata
		output wire        pcie_ip_bar1_0_readdatavalid,                                //                                                      .readdatavalid
		input  wire        pcie_ip_bar1_0_write,                                        //                                                      .write
		input  wire [63:0] pcie_ip_bar1_0_writedata,                                    //                                                      .writedata
		output wire [4:0]  custom_module_avalon_slave_address,                          //                            custom_module_avalon_slave.address
		output wire        custom_module_avalon_slave_write,                            //                                                      .write
		output wire        custom_module_avalon_slave_read,                             //                                                      .read
		input  wire [31:0] custom_module_avalon_slave_readdata,                         //                                                      .readdata
		output wire [31:0] custom_module_avalon_slave_writedata,                        //                                                      .writedata
		output wire        custom_module_avalon_slave_chipselect                        //                                                      .chipselect
	);

	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_waitrequest;   // pcie_ip_bar1_0_agent:av_waitrequest -> pcie_ip_bar1_0_translator:uav_waitrequest
	wire   [63:0] pcie_ip_bar1_0_translator_avalon_universal_master_0_readdata;      // pcie_ip_bar1_0_agent:av_readdata -> pcie_ip_bar1_0_translator:uav_readdata
	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_debugaccess;   // pcie_ip_bar1_0_translator:uav_debugaccess -> pcie_ip_bar1_0_agent:av_debugaccess
	wire   [31:0] pcie_ip_bar1_0_translator_avalon_universal_master_0_address;       // pcie_ip_bar1_0_translator:uav_address -> pcie_ip_bar1_0_agent:av_address
	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_read;          // pcie_ip_bar1_0_translator:uav_read -> pcie_ip_bar1_0_agent:av_read
	wire    [7:0] pcie_ip_bar1_0_translator_avalon_universal_master_0_byteenable;    // pcie_ip_bar1_0_translator:uav_byteenable -> pcie_ip_bar1_0_agent:av_byteenable
	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_readdatavalid; // pcie_ip_bar1_0_agent:av_readdatavalid -> pcie_ip_bar1_0_translator:uav_readdatavalid
	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_lock;          // pcie_ip_bar1_0_translator:uav_lock -> pcie_ip_bar1_0_agent:av_lock
	wire          pcie_ip_bar1_0_translator_avalon_universal_master_0_write;         // pcie_ip_bar1_0_translator:uav_write -> pcie_ip_bar1_0_agent:av_write
	wire   [63:0] pcie_ip_bar1_0_translator_avalon_universal_master_0_writedata;     // pcie_ip_bar1_0_translator:uav_writedata -> pcie_ip_bar1_0_agent:av_writedata
	wire    [9:0] pcie_ip_bar1_0_translator_avalon_universal_master_0_burstcount;    // pcie_ip_bar1_0_translator:uav_burstcount -> pcie_ip_bar1_0_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                 // rsp_mux:src_valid -> pcie_ip_bar1_0_agent:rp_valid
	wire  [144:0] rsp_mux_src_data;                                                  // rsp_mux:src_data -> pcie_ip_bar1_0_agent:rp_data
	wire          rsp_mux_src_ready;                                                 // pcie_ip_bar1_0_agent:rp_ready -> rsp_mux:src_ready
	wire    [0:0] rsp_mux_src_channel;                                               // rsp_mux:src_channel -> pcie_ip_bar1_0_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                         // rsp_mux:src_startofpacket -> pcie_ip_bar1_0_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                           // rsp_mux:src_endofpacket -> pcie_ip_bar1_0_agent:rp_endofpacket
	wire   [31:0] custom_module_avalon_slave_agent_m0_readdata;                      // custom_module_avalon_slave_translator:uav_readdata -> custom_module_avalon_slave_agent:m0_readdata
	wire          custom_module_avalon_slave_agent_m0_waitrequest;                   // custom_module_avalon_slave_translator:uav_waitrequest -> custom_module_avalon_slave_agent:m0_waitrequest
	wire          custom_module_avalon_slave_agent_m0_debugaccess;                   // custom_module_avalon_slave_agent:m0_debugaccess -> custom_module_avalon_slave_translator:uav_debugaccess
	wire   [31:0] custom_module_avalon_slave_agent_m0_address;                       // custom_module_avalon_slave_agent:m0_address -> custom_module_avalon_slave_translator:uav_address
	wire    [3:0] custom_module_avalon_slave_agent_m0_byteenable;                    // custom_module_avalon_slave_agent:m0_byteenable -> custom_module_avalon_slave_translator:uav_byteenable
	wire          custom_module_avalon_slave_agent_m0_read;                          // custom_module_avalon_slave_agent:m0_read -> custom_module_avalon_slave_translator:uav_read
	wire          custom_module_avalon_slave_agent_m0_readdatavalid;                 // custom_module_avalon_slave_translator:uav_readdatavalid -> custom_module_avalon_slave_agent:m0_readdatavalid
	wire          custom_module_avalon_slave_agent_m0_lock;                          // custom_module_avalon_slave_agent:m0_lock -> custom_module_avalon_slave_translator:uav_lock
	wire   [31:0] custom_module_avalon_slave_agent_m0_writedata;                     // custom_module_avalon_slave_agent:m0_writedata -> custom_module_avalon_slave_translator:uav_writedata
	wire          custom_module_avalon_slave_agent_m0_write;                         // custom_module_avalon_slave_agent:m0_write -> custom_module_avalon_slave_translator:uav_write
	wire    [2:0] custom_module_avalon_slave_agent_m0_burstcount;                    // custom_module_avalon_slave_agent:m0_burstcount -> custom_module_avalon_slave_translator:uav_burstcount
	wire          custom_module_avalon_slave_agent_rf_source_valid;                  // custom_module_avalon_slave_agent:rf_source_valid -> custom_module_avalon_slave_agent_rsp_fifo:in_valid
	wire  [109:0] custom_module_avalon_slave_agent_rf_source_data;                   // custom_module_avalon_slave_agent:rf_source_data -> custom_module_avalon_slave_agent_rsp_fifo:in_data
	wire          custom_module_avalon_slave_agent_rf_source_ready;                  // custom_module_avalon_slave_agent_rsp_fifo:in_ready -> custom_module_avalon_slave_agent:rf_source_ready
	wire          custom_module_avalon_slave_agent_rf_source_startofpacket;          // custom_module_avalon_slave_agent:rf_source_startofpacket -> custom_module_avalon_slave_agent_rsp_fifo:in_startofpacket
	wire          custom_module_avalon_slave_agent_rf_source_endofpacket;            // custom_module_avalon_slave_agent:rf_source_endofpacket -> custom_module_avalon_slave_agent_rsp_fifo:in_endofpacket
	wire          custom_module_avalon_slave_agent_rsp_fifo_out_valid;               // custom_module_avalon_slave_agent_rsp_fifo:out_valid -> custom_module_avalon_slave_agent:rf_sink_valid
	wire  [109:0] custom_module_avalon_slave_agent_rsp_fifo_out_data;                // custom_module_avalon_slave_agent_rsp_fifo:out_data -> custom_module_avalon_slave_agent:rf_sink_data
	wire          custom_module_avalon_slave_agent_rsp_fifo_out_ready;               // custom_module_avalon_slave_agent:rf_sink_ready -> custom_module_avalon_slave_agent_rsp_fifo:out_ready
	wire          custom_module_avalon_slave_agent_rsp_fifo_out_startofpacket;       // custom_module_avalon_slave_agent_rsp_fifo:out_startofpacket -> custom_module_avalon_slave_agent:rf_sink_startofpacket
	wire          custom_module_avalon_slave_agent_rsp_fifo_out_endofpacket;         // custom_module_avalon_slave_agent_rsp_fifo:out_endofpacket -> custom_module_avalon_slave_agent:rf_sink_endofpacket
	wire          custom_module_avalon_slave_agent_rdata_fifo_src_valid;             // custom_module_avalon_slave_agent:rdata_fifo_src_valid -> custom_module_avalon_slave_agent_rdata_fifo:in_valid
	wire   [33:0] custom_module_avalon_slave_agent_rdata_fifo_src_data;              // custom_module_avalon_slave_agent:rdata_fifo_src_data -> custom_module_avalon_slave_agent_rdata_fifo:in_data
	wire          custom_module_avalon_slave_agent_rdata_fifo_src_ready;             // custom_module_avalon_slave_agent_rdata_fifo:in_ready -> custom_module_avalon_slave_agent:rdata_fifo_src_ready
	wire          pcie_ip_bar1_0_agent_cp_valid;                                     // pcie_ip_bar1_0_agent:cp_valid -> router:sink_valid
	wire  [144:0] pcie_ip_bar1_0_agent_cp_data;                                      // pcie_ip_bar1_0_agent:cp_data -> router:sink_data
	wire          pcie_ip_bar1_0_agent_cp_ready;                                     // router:sink_ready -> pcie_ip_bar1_0_agent:cp_ready
	wire          pcie_ip_bar1_0_agent_cp_startofpacket;                             // pcie_ip_bar1_0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          pcie_ip_bar1_0_agent_cp_endofpacket;                               // pcie_ip_bar1_0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                  // router:src_valid -> cmd_demux:sink_valid
	wire  [144:0] router_src_data;                                                   // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                  // cmd_demux:sink_ready -> router:src_ready
	wire    [0:0] router_src_channel;                                                // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                          // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                            // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          custom_module_avalon_slave_agent_rp_valid;                         // custom_module_avalon_slave_agent:rp_valid -> router_001:sink_valid
	wire  [108:0] custom_module_avalon_slave_agent_rp_data;                          // custom_module_avalon_slave_agent:rp_data -> router_001:sink_data
	wire          custom_module_avalon_slave_agent_rp_ready;                         // router_001:sink_ready -> custom_module_avalon_slave_agent:rp_ready
	wire          custom_module_avalon_slave_agent_rp_startofpacket;                 // custom_module_avalon_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          custom_module_avalon_slave_agent_rp_endofpacket;                   // custom_module_avalon_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          custom_module_avalon_slave_burst_adapter_source0_valid;            // custom_module_avalon_slave_burst_adapter:source0_valid -> custom_module_avalon_slave_agent:cp_valid
	wire  [108:0] custom_module_avalon_slave_burst_adapter_source0_data;             // custom_module_avalon_slave_burst_adapter:source0_data -> custom_module_avalon_slave_agent:cp_data
	wire          custom_module_avalon_slave_burst_adapter_source0_ready;            // custom_module_avalon_slave_agent:cp_ready -> custom_module_avalon_slave_burst_adapter:source0_ready
	wire    [0:0] custom_module_avalon_slave_burst_adapter_source0_channel;          // custom_module_avalon_slave_burst_adapter:source0_channel -> custom_module_avalon_slave_agent:cp_channel
	wire          custom_module_avalon_slave_burst_adapter_source0_startofpacket;    // custom_module_avalon_slave_burst_adapter:source0_startofpacket -> custom_module_avalon_slave_agent:cp_startofpacket
	wire          custom_module_avalon_slave_burst_adapter_source0_endofpacket;      // custom_module_avalon_slave_burst_adapter:source0_endofpacket -> custom_module_avalon_slave_agent:cp_endofpacket
	wire          router_001_src_valid;                                              // router_001:src_valid -> custom_module_avalon_slave_rsp_width_adapter:in_valid
	wire  [108:0] router_001_src_data;                                               // router_001:src_data -> custom_module_avalon_slave_rsp_width_adapter:in_data
	wire          router_001_src_ready;                                              // custom_module_avalon_slave_rsp_width_adapter:in_ready -> router_001:src_ready
	wire    [0:0] router_001_src_channel;                                            // router_001:src_channel -> custom_module_avalon_slave_rsp_width_adapter:in_channel
	wire          router_001_src_startofpacket;                                      // router_001:src_startofpacket -> custom_module_avalon_slave_rsp_width_adapter:in_startofpacket
	wire          router_001_src_endofpacket;                                        // router_001:src_endofpacket -> custom_module_avalon_slave_rsp_width_adapter:in_endofpacket
	wire          custom_module_avalon_slave_rsp_width_adapter_src_valid;            // custom_module_avalon_slave_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [144:0] custom_module_avalon_slave_rsp_width_adapter_src_data;             // custom_module_avalon_slave_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          custom_module_avalon_slave_rsp_width_adapter_src_ready;            // rsp_demux:sink_ready -> custom_module_avalon_slave_rsp_width_adapter:out_ready
	wire    [0:0] custom_module_avalon_slave_rsp_width_adapter_src_channel;          // custom_module_avalon_slave_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          custom_module_avalon_slave_rsp_width_adapter_src_startofpacket;    // custom_module_avalon_slave_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          custom_module_avalon_slave_rsp_width_adapter_src_endofpacket;      // custom_module_avalon_slave_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                                 // cmd_mux:src_valid -> custom_module_avalon_slave_cmd_width_adapter:in_valid
	wire  [144:0] cmd_mux_src_data;                                                  // cmd_mux:src_data -> custom_module_avalon_slave_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                 // custom_module_avalon_slave_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [0:0] cmd_mux_src_channel;                                               // cmd_mux:src_channel -> custom_module_avalon_slave_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                         // cmd_mux:src_startofpacket -> custom_module_avalon_slave_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                           // cmd_mux:src_endofpacket -> custom_module_avalon_slave_cmd_width_adapter:in_endofpacket
	wire          custom_module_avalon_slave_cmd_width_adapter_src_valid;            // custom_module_avalon_slave_cmd_width_adapter:out_valid -> custom_module_avalon_slave_burst_adapter:sink0_valid
	wire  [108:0] custom_module_avalon_slave_cmd_width_adapter_src_data;             // custom_module_avalon_slave_cmd_width_adapter:out_data -> custom_module_avalon_slave_burst_adapter:sink0_data
	wire          custom_module_avalon_slave_cmd_width_adapter_src_ready;            // custom_module_avalon_slave_burst_adapter:sink0_ready -> custom_module_avalon_slave_cmd_width_adapter:out_ready
	wire    [0:0] custom_module_avalon_slave_cmd_width_adapter_src_channel;          // custom_module_avalon_slave_cmd_width_adapter:out_channel -> custom_module_avalon_slave_burst_adapter:sink0_channel
	wire          custom_module_avalon_slave_cmd_width_adapter_src_startofpacket;    // custom_module_avalon_slave_cmd_width_adapter:out_startofpacket -> custom_module_avalon_slave_burst_adapter:sink0_startofpacket
	wire          custom_module_avalon_slave_cmd_width_adapter_src_endofpacket;      // custom_module_avalon_slave_cmd_width_adapter:out_endofpacket -> custom_module_avalon_slave_burst_adapter:sink0_endofpacket
	wire          cmd_demux_src0_valid;                                              // cmd_demux:src0_valid -> crosser:in_valid
	wire  [144:0] cmd_demux_src0_data;                                               // cmd_demux:src0_data -> crosser:in_data
	wire          cmd_demux_src0_ready;                                              // crosser:in_ready -> cmd_demux:src0_ready
	wire    [0:0] cmd_demux_src0_channel;                                            // cmd_demux:src0_channel -> crosser:in_channel
	wire          cmd_demux_src0_startofpacket;                                      // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                        // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          crosser_out_valid;                                                 // crosser:out_valid -> cmd_mux:sink0_valid
	wire  [144:0] crosser_out_data;                                                  // crosser:out_data -> cmd_mux:sink0_data
	wire          crosser_out_ready;                                                 // cmd_mux:sink0_ready -> crosser:out_ready
	wire    [0:0] crosser_out_channel;                                               // crosser:out_channel -> cmd_mux:sink0_channel
	wire          crosser_out_startofpacket;                                         // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          crosser_out_endofpacket;                                           // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                              // rsp_demux:src0_valid -> crosser_001:in_valid
	wire  [144:0] rsp_demux_src0_data;                                               // rsp_demux:src0_data -> crosser_001:in_data
	wire          rsp_demux_src0_ready;                                              // crosser_001:in_ready -> rsp_demux:src0_ready
	wire    [0:0] rsp_demux_src0_channel;                                            // rsp_demux:src0_channel -> crosser_001:in_channel
	wire          rsp_demux_src0_startofpacket;                                      // rsp_demux:src0_startofpacket -> crosser_001:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                        // rsp_demux:src0_endofpacket -> crosser_001:in_endofpacket
	wire          crosser_001_out_valid;                                             // crosser_001:out_valid -> rsp_mux:sink0_valid
	wire  [144:0] crosser_001_out_data;                                              // crosser_001:out_data -> rsp_mux:sink0_data
	wire          crosser_001_out_ready;                                             // rsp_mux:sink0_ready -> crosser_001:out_ready
	wire    [0:0] crosser_001_out_channel;                                           // crosser_001:out_channel -> rsp_mux:sink0_channel
	wire          crosser_001_out_startofpacket;                                     // crosser_001:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          crosser_001_out_endofpacket;                                       // crosser_001:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          custom_module_avalon_slave_agent_rdata_fifo_out_valid;             // custom_module_avalon_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [33:0] custom_module_avalon_slave_agent_rdata_fifo_out_data;              // custom_module_avalon_slave_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          custom_module_avalon_slave_agent_rdata_fifo_out_ready;             // avalon_st_adapter:in_0_ready -> custom_module_avalon_slave_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                     // avalon_st_adapter:out_0_valid -> custom_module_avalon_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_out_0_data;                                      // avalon_st_adapter:out_0_data -> custom_module_avalon_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                     // custom_module_avalon_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                     // avalon_st_adapter:out_0_error -> custom_module_avalon_slave_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) pcie_ip_bar1_0_translator (
		.clk                    (pcie_ip_pcie_core_clk_clk),                                         //                       clk.clk
		.reset                  (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset),       //                     reset.reset
		.uav_address            (pcie_ip_bar1_0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (pcie_ip_bar1_0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (pcie_ip_bar1_0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (pcie_ip_bar1_0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (pcie_ip_bar1_0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (pcie_ip_bar1_0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (pcie_ip_bar1_0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (pcie_ip_bar1_0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (pcie_ip_bar1_0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (pcie_ip_bar1_0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (pcie_ip_bar1_0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (pcie_ip_bar1_0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (pcie_ip_bar1_0_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (pcie_ip_bar1_0_burstcount),                                         //                          .burstcount
		.av_byteenable          (pcie_ip_bar1_0_byteenable),                                         //                          .byteenable
		.av_read                (pcie_ip_bar1_0_read),                                               //                          .read
		.av_readdata            (pcie_ip_bar1_0_readdata),                                           //                          .readdata
		.av_readdatavalid       (pcie_ip_bar1_0_readdatavalid),                                      //                          .readdatavalid
		.av_write               (pcie_ip_bar1_0_write),                                              //                          .write
		.av_writedata           (pcie_ip_bar1_0_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                              //               (terminated)
		.av_begintransfer       (1'b0),                                                              //               (terminated)
		.av_chipselect          (1'b0),                                                              //               (terminated)
		.av_lock                (1'b0),                                                              //               (terminated)
		.av_debugaccess         (1'b0),                                                              //               (terminated)
		.uav_clken              (),                                                                  //               (terminated)
		.av_clken               (1'b1),                                                              //               (terminated)
		.uav_response           (2'b00),                                                             //               (terminated)
		.av_response            (),                                                                  //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                              //               (terminated)
		.av_writeresponsevalid  ()                                                                   //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (5),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) custom_module_avalon_slave_translator (
		.clk                    (clk_50_clk_clk),                                    //                      clk.clk
		.reset                  (custom_module_reset_reset_bridge_in_reset_reset),   //                    reset.reset
		.uav_address            (custom_module_avalon_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (custom_module_avalon_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (custom_module_avalon_slave_agent_m0_read),          //                         .read
		.uav_write              (custom_module_avalon_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (custom_module_avalon_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (custom_module_avalon_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (custom_module_avalon_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (custom_module_avalon_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (custom_module_avalon_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (custom_module_avalon_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (custom_module_avalon_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (custom_module_avalon_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (custom_module_avalon_slave_write),                  //                         .write
		.av_read                (custom_module_avalon_slave_read),                   //                         .read
		.av_readdata            (custom_module_avalon_slave_readdata),               //                         .readdata
		.av_writedata           (custom_module_avalon_slave_writedata),              //                         .writedata
		.av_chipselect          (custom_module_avalon_slave_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                  //              (terminated)
		.av_beginbursttransfer  (),                                                  //              (terminated)
		.av_burstcount          (),                                                  //              (terminated)
		.av_byteenable          (),                                                  //              (terminated)
		.av_readdatavalid       (1'b0),                                              //              (terminated)
		.av_waitrequest         (1'b0),                                              //              (terminated)
		.av_writebyteenable     (),                                                  //              (terminated)
		.av_lock                (),                                                  //              (terminated)
		.av_clken               (),                                                  //              (terminated)
		.uav_clken              (1'b0),                                              //              (terminated)
		.av_debugaccess         (),                                                  //              (terminated)
		.av_outputenable        (),                                                  //              (terminated)
		.uav_response           (),                                                  //              (terminated)
		.av_response            (2'b00),                                             //              (terminated)
		.uav_writeresponsevalid (),                                                  //              (terminated)
		.av_writeresponsevalid  (1'b0)                                               //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (144),
		.PKT_ORI_BURST_SIZE_L      (142),
		.PKT_RESPONSE_STATUS_H     (141),
		.PKT_RESPONSE_STATUS_L     (140),
		.PKT_QOS_H                 (129),
		.PKT_QOS_L                 (129),
		.PKT_DATA_SIDEBAND_H       (127),
		.PKT_DATA_SIDEBAND_L       (127),
		.PKT_ADDR_SIDEBAND_H       (126),
		.PKT_ADDR_SIDEBAND_L       (126),
		.PKT_BURST_TYPE_H          (125),
		.PKT_BURST_TYPE_L          (124),
		.PKT_CACHE_H               (139),
		.PKT_CACHE_L               (136),
		.PKT_THREAD_ID_H           (132),
		.PKT_THREAD_ID_L           (132),
		.PKT_BURST_SIZE_H          (123),
		.PKT_BURST_SIZE_L          (121),
		.PKT_TRANS_EXCLUSIVE       (109),
		.PKT_TRANS_LOCK            (108),
		.PKT_BEGIN_BURST           (128),
		.PKT_PROTECTION_H          (135),
		.PKT_PROTECTION_L          (133),
		.PKT_BURSTWRAP_H           (120),
		.PKT_BURSTWRAP_L           (120),
		.PKT_BYTE_CNT_H            (119),
		.PKT_BYTE_CNT_L            (110),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (130),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (131),
		.PKT_DEST_ID_L             (131),
		.ST_DATA_W                 (145),
		.ST_CHANNEL_W              (1),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) pcie_ip_bar1_0_agent (
		.clk                   (pcie_ip_pcie_core_clk_clk),                                         //       clk.clk
		.reset                 (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.av_address            (pcie_ip_bar1_0_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (pcie_ip_bar1_0_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (pcie_ip_bar1_0_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (pcie_ip_bar1_0_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (pcie_ip_bar1_0_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (pcie_ip_bar1_0_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (pcie_ip_bar1_0_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (pcie_ip_bar1_0_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (pcie_ip_bar1_0_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (pcie_ip_bar1_0_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (pcie_ip_bar1_0_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (pcie_ip_bar1_0_agent_cp_valid),                                     //        cp.valid
		.cp_data               (pcie_ip_bar1_0_agent_cp_data),                                      //          .data
		.cp_startofpacket      (pcie_ip_bar1_0_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (pcie_ip_bar1_0_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (pcie_ip_bar1_0_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                 //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                  //          .data
		.rp_channel            (rsp_mux_src_channel),                                               //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                         //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                           //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                 //          .ready
		.av_response           (),                                                                  // (terminated)
		.av_writeresponsevalid ()                                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (108),
		.PKT_ORI_BURST_SIZE_L      (106),
		.PKT_RESPONSE_STATUS_H     (105),
		.PKT_RESPONSE_STATUS_L     (104),
		.PKT_BURST_SIZE_H          (87),
		.PKT_BURST_SIZE_L          (85),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (92),
		.PKT_PROTECTION_H          (99),
		.PKT_PROTECTION_L          (97),
		.PKT_BURSTWRAP_H           (84),
		.PKT_BURSTWRAP_L           (84),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (94),
		.PKT_SRC_ID_L              (94),
		.PKT_DEST_ID_H             (95),
		.PKT_DEST_ID_L             (95),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (1),
		.ST_DATA_W                 (109),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) custom_module_avalon_slave_agent (
		.clk                     (clk_50_clk_clk),                                                 //             clk.clk
		.reset                   (custom_module_reset_reset_bridge_in_reset_reset),                //       clk_reset.reset
		.m0_address              (custom_module_avalon_slave_agent_m0_address),                    //              m0.address
		.m0_burstcount           (custom_module_avalon_slave_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (custom_module_avalon_slave_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (custom_module_avalon_slave_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (custom_module_avalon_slave_agent_m0_lock),                       //                .lock
		.m0_readdata             (custom_module_avalon_slave_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (custom_module_avalon_slave_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (custom_module_avalon_slave_agent_m0_read),                       //                .read
		.m0_waitrequest          (custom_module_avalon_slave_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (custom_module_avalon_slave_agent_m0_writedata),                  //                .writedata
		.m0_write                (custom_module_avalon_slave_agent_m0_write),                      //                .write
		.rp_endofpacket          (custom_module_avalon_slave_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (custom_module_avalon_slave_agent_rp_ready),                      //                .ready
		.rp_valid                (custom_module_avalon_slave_agent_rp_valid),                      //                .valid
		.rp_data                 (custom_module_avalon_slave_agent_rp_data),                       //                .data
		.rp_startofpacket        (custom_module_avalon_slave_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (custom_module_avalon_slave_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (custom_module_avalon_slave_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (custom_module_avalon_slave_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (custom_module_avalon_slave_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (custom_module_avalon_slave_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (custom_module_avalon_slave_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (custom_module_avalon_slave_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (custom_module_avalon_slave_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (custom_module_avalon_slave_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (custom_module_avalon_slave_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (custom_module_avalon_slave_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (custom_module_avalon_slave_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (custom_module_avalon_slave_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (custom_module_avalon_slave_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (custom_module_avalon_slave_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (custom_module_avalon_slave_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                  // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                  //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                   //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                  //                .error
		.rdata_fifo_src_ready    (custom_module_avalon_slave_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (custom_module_avalon_slave_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (custom_module_avalon_slave_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (110),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) custom_module_avalon_slave_agent_rsp_fifo (
		.clk               (clk_50_clk_clk),                                              //       clk.clk
		.reset             (custom_module_reset_reset_bridge_in_reset_reset),             // clk_reset.reset
		.in_data           (custom_module_avalon_slave_agent_rf_source_data),             //        in.data
		.in_valid          (custom_module_avalon_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (custom_module_avalon_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (custom_module_avalon_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (custom_module_avalon_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (custom_module_avalon_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (custom_module_avalon_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (custom_module_avalon_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (custom_module_avalon_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (custom_module_avalon_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                       // (terminated)
		.csr_read          (1'b0),                                                        // (terminated)
		.csr_write         (1'b0),                                                        // (terminated)
		.csr_readdata      (),                                                            // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                        // (terminated)
		.almost_full_data  (),                                                            // (terminated)
		.almost_empty_data (),                                                            // (terminated)
		.in_empty          (1'b0),                                                        // (terminated)
		.out_empty         (),                                                            // (terminated)
		.in_error          (1'b0),                                                        // (terminated)
		.out_error         (),                                                            // (terminated)
		.in_channel        (1'b0),                                                        // (terminated)
		.out_channel       ()                                                             // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) custom_module_avalon_slave_agent_rdata_fifo (
		.clk               (clk_50_clk_clk),                                        //       clk.clk
		.reset             (custom_module_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (custom_module_avalon_slave_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (custom_module_avalon_slave_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (custom_module_avalon_slave_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (custom_module_avalon_slave_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (custom_module_avalon_slave_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (custom_module_avalon_slave_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                 // (terminated)
		.csr_read          (1'b0),                                                  // (terminated)
		.csr_write         (1'b0),                                                  // (terminated)
		.csr_readdata      (),                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
		.almost_full_data  (),                                                      // (terminated)
		.almost_empty_data (),                                                      // (terminated)
		.in_startofpacket  (1'b0),                                                  // (terminated)
		.in_endofpacket    (1'b0),                                                  // (terminated)
		.out_startofpacket (),                                                      // (terminated)
		.out_endofpacket   (),                                                      // (terminated)
		.in_empty          (1'b0),                                                  // (terminated)
		.out_empty         (),                                                      // (terminated)
		.in_error          (1'b0),                                                  // (terminated)
		.out_error         (),                                                      // (terminated)
		.in_channel        (1'b0),                                                  // (terminated)
		.out_channel       ()                                                       // (terminated)
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_router router (
		.sink_ready         (pcie_ip_bar1_0_agent_cp_ready),                               //      sink.ready
		.sink_valid         (pcie_ip_bar1_0_agent_cp_valid),                               //          .valid
		.sink_data          (pcie_ip_bar1_0_agent_cp_data),                                //          .data
		.sink_startofpacket (pcie_ip_bar1_0_agent_cp_startofpacket),                       //          .startofpacket
		.sink_endofpacket   (pcie_ip_bar1_0_agent_cp_endofpacket),                         //          .endofpacket
		.clk                (pcie_ip_pcie_core_clk_clk),                                   //       clk.clk
		.reset              (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                                            //       src.ready
		.src_valid          (router_src_valid),                                            //          .valid
		.src_data           (router_src_data),                                             //          .data
		.src_channel        (router_src_channel),                                          //          .channel
		.src_startofpacket  (router_src_startofpacket),                                    //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                       //          .endofpacket
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_router_001 router_001 (
		.sink_ready         (custom_module_avalon_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (custom_module_avalon_slave_agent_rp_valid),         //          .valid
		.sink_data          (custom_module_avalon_slave_agent_rp_data),          //          .data
		.sink_startofpacket (custom_module_avalon_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (custom_module_avalon_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_50_clk_clk),                                    //       clk.clk
		.reset              (custom_module_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.src_ready          (router_001_src_ready),                              //       src.ready
		.src_valid          (router_001_src_valid),                              //          .valid
		.src_data           (router_001_src_data),                               //          .data
		.src_channel        (router_001_src_channel),                            //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                      //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                         //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (92),
		.PKT_BYTE_CNT_H            (83),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (87),
		.PKT_BURST_SIZE_L          (85),
		.PKT_BURST_TYPE_H          (89),
		.PKT_BURST_TYPE_L          (88),
		.PKT_BURSTWRAP_H           (84),
		.PKT_BURSTWRAP_L           (84),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (109),
		.ST_CHANNEL_W              (1),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (84),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (1),
		.BURSTWRAP_CONST_VALUE     (1),
		.ADAPTER_VERSION           ("13.1")
	) custom_module_avalon_slave_burst_adapter (
		.clk                   (clk_50_clk_clk),                                                 //       cr0.clk
		.reset                 (custom_module_reset_reset_bridge_in_reset_reset),                // cr0_reset.reset
		.sink0_valid           (custom_module_avalon_slave_cmd_width_adapter_src_valid),         //     sink0.valid
		.sink0_data            (custom_module_avalon_slave_cmd_width_adapter_src_data),          //          .data
		.sink0_channel         (custom_module_avalon_slave_cmd_width_adapter_src_channel),       //          .channel
		.sink0_startofpacket   (custom_module_avalon_slave_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket     (custom_module_avalon_slave_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.sink0_ready           (custom_module_avalon_slave_cmd_width_adapter_src_ready),         //          .ready
		.source0_valid         (custom_module_avalon_slave_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (custom_module_avalon_slave_burst_adapter_source0_data),          //          .data
		.source0_channel       (custom_module_avalon_slave_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (custom_module_avalon_slave_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (custom_module_avalon_slave_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (custom_module_avalon_slave_burst_adapter_source0_ready)          //          .ready
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_cmd_demux cmd_demux (
		.clk                (pcie_ip_pcie_core_clk_clk),                                   //       clk.clk
		.reset              (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                                            //      sink.ready
		.sink_channel       (router_src_channel),                                          //          .channel
		.sink_data          (router_src_data),                                             //          .data
		.sink_startofpacket (router_src_startofpacket),                                    //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                      //          .endofpacket
		.sink_valid         (router_src_valid),                                            //          .valid
		.src0_ready         (cmd_demux_src0_ready),                                        //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                        //          .valid
		.src0_data          (cmd_demux_src0_data),                                         //          .data
		.src0_channel       (cmd_demux_src0_channel),                                      //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                   //          .endofpacket
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_cmd_mux cmd_mux (
		.clk                 (clk_50_clk_clk),                                  //       clk.clk
		.reset               (custom_module_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                               //       src.ready
		.src_valid           (cmd_mux_src_valid),                               //          .valid
		.src_data            (cmd_mux_src_data),                                //          .data
		.src_channel         (cmd_mux_src_channel),                             //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                       //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                         //          .endofpacket
		.sink0_ready         (crosser_out_ready),                               //     sink0.ready
		.sink0_valid         (crosser_out_valid),                               //          .valid
		.sink0_channel       (crosser_out_channel),                             //          .channel
		.sink0_data          (crosser_out_data),                                //          .data
		.sink0_startofpacket (crosser_out_startofpacket),                       //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket)                          //          .endofpacket
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_rsp_demux rsp_demux (
		.clk                (clk_50_clk_clk),                                                 //       clk.clk
		.reset              (custom_module_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.sink_ready         (custom_module_avalon_slave_rsp_width_adapter_src_ready),         //      sink.ready
		.sink_channel       (custom_module_avalon_slave_rsp_width_adapter_src_channel),       //          .channel
		.sink_data          (custom_module_avalon_slave_rsp_width_adapter_src_data),          //          .data
		.sink_startofpacket (custom_module_avalon_slave_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (custom_module_avalon_slave_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink_valid         (custom_module_avalon_slave_rsp_width_adapter_src_valid),         //          .valid
		.src0_ready         (rsp_demux_src0_ready),                                           //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                           //          .valid
		.src0_data          (rsp_demux_src0_data),                                            //          .data
		.src0_channel       (rsp_demux_src0_channel),                                         //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                   //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                      //          .endofpacket
	);

	amm_master_qsys_with_pcie_mm_interconnect_1_rsp_mux rsp_mux (
		.clk                 (pcie_ip_pcie_core_clk_clk),                                   //       clk.clk
		.reset               (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                           //       src.ready
		.src_valid           (rsp_mux_src_valid),                                           //          .valid
		.src_data            (rsp_mux_src_data),                                            //          .data
		.src_channel         (rsp_mux_src_channel),                                         //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                   //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                     //          .endofpacket
		.sink0_ready         (crosser_001_out_ready),                                       //     sink0.ready
		.sink0_valid         (crosser_001_out_valid),                                       //          .valid
		.sink0_channel       (crosser_001_out_channel),                                     //          .channel
		.sink0_data          (crosser_001_out_data),                                        //          .data
		.sink0_startofpacket (crosser_001_out_startofpacket),                               //          .startofpacket
		.sink0_endofpacket   (crosser_001_out_endofpacket)                                  //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (83),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (84),
		.IN_PKT_BURSTWRAP_L            (84),
		.IN_PKT_BURST_SIZE_H           (87),
		.IN_PKT_BURST_SIZE_L           (85),
		.IN_PKT_RESPONSE_STATUS_H      (105),
		.IN_PKT_RESPONSE_STATUS_L      (104),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (89),
		.IN_PKT_BURST_TYPE_L           (88),
		.IN_PKT_ORI_BURST_SIZE_L       (106),
		.IN_PKT_ORI_BURST_SIZE_H       (108),
		.IN_ST_DATA_W                  (109),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (119),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (123),
		.OUT_PKT_BURST_SIZE_L          (121),
		.OUT_PKT_RESPONSE_STATUS_H     (141),
		.OUT_PKT_RESPONSE_STATUS_L     (140),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (125),
		.OUT_PKT_BURST_TYPE_L          (124),
		.OUT_PKT_ORI_BURST_SIZE_L      (142),
		.OUT_PKT_ORI_BURST_SIZE_H      (144),
		.OUT_ST_DATA_W                 (145),
		.ST_CHANNEL_W                  (1),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) custom_module_avalon_slave_rsp_width_adapter (
		.clk                  (clk_50_clk_clk),                                                 //       clk.clk
		.reset                (custom_module_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_valid             (router_001_src_valid),                                           //      sink.valid
		.in_channel           (router_001_src_channel),                                         //          .channel
		.in_startofpacket     (router_001_src_startofpacket),                                   //          .startofpacket
		.in_endofpacket       (router_001_src_endofpacket),                                     //          .endofpacket
		.in_ready             (router_001_src_ready),                                           //          .ready
		.in_data              (router_001_src_data),                                            //          .data
		.out_endofpacket      (custom_module_avalon_slave_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (custom_module_avalon_slave_rsp_width_adapter_src_data),          //          .data
		.out_channel          (custom_module_avalon_slave_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (custom_module_avalon_slave_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (custom_module_avalon_slave_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (custom_module_avalon_slave_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                          // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (119),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (120),
		.IN_PKT_BURSTWRAP_L            (120),
		.IN_PKT_BURST_SIZE_H           (123),
		.IN_PKT_BURST_SIZE_L           (121),
		.IN_PKT_RESPONSE_STATUS_H      (141),
		.IN_PKT_RESPONSE_STATUS_L      (140),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (125),
		.IN_PKT_BURST_TYPE_L           (124),
		.IN_PKT_ORI_BURST_SIZE_L       (142),
		.IN_PKT_ORI_BURST_SIZE_H       (144),
		.IN_ST_DATA_W                  (145),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (83),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (87),
		.OUT_PKT_BURST_SIZE_L          (85),
		.OUT_PKT_RESPONSE_STATUS_H     (105),
		.OUT_PKT_RESPONSE_STATUS_L     (104),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (89),
		.OUT_PKT_BURST_TYPE_L          (88),
		.OUT_PKT_ORI_BURST_SIZE_L      (106),
		.OUT_PKT_ORI_BURST_SIZE_H      (108),
		.OUT_ST_DATA_W                 (109),
		.ST_CHANNEL_W                  (1),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) custom_module_avalon_slave_cmd_width_adapter (
		.clk                  (clk_50_clk_clk),                                                 //       clk.clk
		.reset                (custom_module_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                              //      sink.valid
		.in_channel           (cmd_mux_src_channel),                                            //          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                                      //          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                                        //          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                              //          .ready
		.in_data              (cmd_mux_src_data),                                               //          .data
		.out_endofpacket      (custom_module_avalon_slave_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (custom_module_avalon_slave_cmd_width_adapter_src_data),          //          .data
		.out_channel          (custom_module_avalon_slave_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (custom_module_avalon_slave_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (custom_module_avalon_slave_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (custom_module_avalon_slave_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                          // (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (145),
		.BITS_PER_SYMBOL     (145),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (1),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (pcie_ip_pcie_core_clk_clk),                                   //        in_clk.clk
		.in_reset          (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clk_50_clk_clk),                                              //       out_clk.clk
		.out_reset         (custom_module_reset_reset_bridge_in_reset_reset),             // out_clk_reset.reset
		.in_ready          (cmd_demux_src0_ready),                                        //            in.ready
		.in_valid          (cmd_demux_src0_valid),                                        //              .valid
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                //              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                  //              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                      //              .channel
		.in_data           (cmd_demux_src0_data),                                         //              .data
		.out_ready         (crosser_out_ready),                                           //           out.ready
		.out_valid         (crosser_out_valid),                                           //              .valid
		.out_startofpacket (crosser_out_startofpacket),                                   //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                     //              .endofpacket
		.out_channel       (crosser_out_channel),                                         //              .channel
		.out_data          (crosser_out_data),                                            //              .data
		.in_empty          (1'b0),                                                        //   (terminated)
		.in_error          (1'b0),                                                        //   (terminated)
		.out_empty         (),                                                            //   (terminated)
		.out_error         ()                                                             //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (145),
		.BITS_PER_SYMBOL     (145),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (1),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk_50_clk_clk),                                              //        in_clk.clk
		.in_reset          (custom_module_reset_reset_bridge_in_reset_reset),             //  in_clk_reset.reset
		.out_clk           (pcie_ip_pcie_core_clk_clk),                                   //       out_clk.clk
		.out_reset         (pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_demux_src0_ready),                                        //            in.ready
		.in_valid          (rsp_demux_src0_valid),                                        //              .valid
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                //              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                  //              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                      //              .channel
		.in_data           (rsp_demux_src0_data),                                         //              .data
		.out_ready         (crosser_001_out_ready),                                       //           out.ready
		.out_valid         (crosser_001_out_valid),                                       //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                               //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                                 //              .endofpacket
		.out_channel       (crosser_001_out_channel),                                     //              .channel
		.out_data          (crosser_001_out_data),                                        //              .data
		.in_empty          (1'b0),                                                        //   (terminated)
		.in_error          (1'b0),                                                        //   (terminated)
		.out_empty         (),                                                            //   (terminated)
		.out_error         ()                                                             //   (terminated)
	);

	amm_master_qsys_with_pcie_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (clk_50_clk_clk),                                        // in_clk_0.clk
		.in_rst_0_reset (custom_module_reset_reset_bridge_in_reset_reset),       // in_rst_0.reset
		.in_0_data      (custom_module_avalon_slave_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (custom_module_avalon_slave_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (custom_module_avalon_slave_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                          //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                         //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                         //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                          //         .error
	);

endmodule
