// -------------------------------------------------------------
//
// Generated Architecture Declaration for struct of ent_a
//
// Generated
//  by:  wig
//  on:  Fri Jul  7 06:37:54 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: ent_a.v,v $
// Revision 1.4  2006/07/10 07:30:09  wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp 
//
// Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module struct of ent_a
//

// No user `defines in this module


module ent_a
//
// Generated Module inst_a
//
	(
		p_mix_sc_sig_1_go,
		p_mix_sc_sig_2_go,
		p_mix_sc_sig_4_go
	);

	// Generated Module Outputs:
		output		p_mix_sc_sig_1_go;
		output	[31:0]	p_mix_sc_sig_2_go;
		output	[31:0]	p_mix_sc_sig_4_go;
	// Generated Wires:
		wire		p_mix_sc_sig_1_go;
		wire	[31:0]	p_mix_sc_sig_2_go;
		wire	[31:0]	p_mix_sc_sig_4_go;
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
		wire		sc_sig_1; // __W_PORT_SIGNAL_MAP_REQ
		wire	[31:0]	sc_sig_2; // __W_PORT_SIGNAL_MAP_REQ
		wire	[31:0]	sc_sig_4; // __W_PORT_SIGNAL_MAP_REQ
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//
		assign	p_mix_sc_sig_1_go	=	sc_sig_1;  // __I_O_BIT_PORT
		assign	p_mix_sc_sig_2_go	=	sc_sig_2;  // __I_O_BUS_PORT
		assign	p_mix_sc_sig_4_go	=	sc_sig_4;  // __I_O_BUS_PORT




	//
	// Generated Instances and Port Mappings
	//
		// Generated Instance Port Map for inst_aa
		ent_aa inst_aa (	// is i_padframe / hier inst_aa inst_aa inst_a
			.p_mix_sc_sig_2_go(sc_sig_2),	// reverse orderreverse order
					// multiline comments
			.p_mix_sc_sig_4_go(sc_sig_4)	// reverse order
					// multiline comments
					// line 3
					// line 4
					// line 5
					// line 6
					// line 7
					// line 8
					// line 9
					// line 10
					// ...[cut]...
		);
		// End of Generated Instance Port Map for inst_aa

		// Generated Instance Port Map for inst_ab
		ent_ab inst_ab (	// is i_vgca / hier inst_ab inst_ab inst_a
			.p_mix_sc_sig_1_go(sc_sig_1),	// bad conection bits detected
			.p_mix_sc_sig_2_go(sc_sig_2)	// reverse orderreverse order
					// multiline comments
		);
		// End of Generated Instance Port Map for inst_ab



endmodule
//
// End of Generated Module struct of ent_a
//

//
//!End of Module/s
// --------------------------------------------------------------
