`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   00:43:33 09/07/2013
// Design Name:   synchronizer
// Module Name:   C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab2/laboratorio2/test_synchronizer.v
// Project Name:  laboratorio2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: synchronizer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_synchronizer;

	// Inputs
	reg clk;
	reg rst;
	reg sensor;
	reg reprogram;
	reg walk_btn;

	// Outputs
	wire rst_out;
	wire sensor_out;
	wire walk_register;
	wire reprogram_out;

	// Instantiate the Unit Under Test (UUT)
	synchronizer uut (
		.clk(clk), 
		.rst(rst), 
		.sensor(sensor), 
		.reprogram(reprogram), 
		.walk_btn(walk_btn), 
		.rst_out(rst_out), 
		.sensor_out(sensor_out), 
		.walk_register(walk_register), 
		.reprogram_out(reprogram_out)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		sensor = 0;
		reprogram = 0;
		walk_btn = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

