// file: ClockDivider.v
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2____15.000______0.000______50.0______303.688____300.991
// CLK_OUT3____30.000______0.000______50.0______270.092____300.991
// CLK_OUT4____90.000______0.000______50.0______226.688____300.991
//
//----------------------------------------------------------------------------
// Input Clock   Freq (MHz)    Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)

module ClockDivider 
 (
 // Clock in ports
  input         clkIn,
  // Clock out ports
  output        clk108M,
  output        clk_cpu,
  output        clk2cpu,
  output        clk6cpu
 );

  ClockDivider_clk_wiz inst
  (
 // Clock in ports
  .clkIn(clkIn),
  // Clock out ports  
  .clk108M(clk108M),
  .clk_cpu(clk_cpu),
  .clk2cpu(clk2cpu),
  .clk6cpu(clk6cpu)              
  );

endmodule
