// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
// ANY MANUAL CHANGES WILL BE LOST
module wb_intercon
   (input         wb_clk_i,
    input         wb_rst_i,
    input  [31:0] wb_iwmb_adr_i,
    input  [31:0] wb_iwmb_dat_i,
    input   [3:0] wb_iwmb_sel_i,
    input         wb_iwmb_we_i,
    input         wb_iwmb_cyc_i,
    input         wb_iwmb_stb_i,
    input   [2:0] wb_iwmb_cti_i,
    input   [1:0] wb_iwmb_bte_i,
    output [31:0] wb_iwmb_dat_o,
    output        wb_iwmb_ack_o,
    output        wb_iwmb_err_o,
    output        wb_iwmb_rty_o,
    input  [31:0] wb_dwmb_adr_i,
    input  [31:0] wb_dwmb_dat_i,
    input   [3:0] wb_dwmb_sel_i,
    input         wb_dwmb_we_i,
    input         wb_dwmb_cyc_i,
    input         wb_dwmb_stb_i,
    input   [2:0] wb_dwmb_cti_i,
    input   [1:0] wb_dwmb_bte_i,
    output [31:0] wb_dwmb_dat_o,
    output        wb_dwmb_ack_o,
    output        wb_dwmb_err_o,
    output        wb_dwmb_rty_o,
    output [31:0] wb_uart_adr_o,
    output [31:0] wb_uart_dat_o,
    output  [3:0] wb_uart_sel_o,
    output        wb_uart_we_o,
    output        wb_uart_cyc_o,
    output        wb_uart_stb_o,
    output  [2:0] wb_uart_cti_o,
    output  [1:0] wb_uart_bte_o,
    input  [31:0] wb_uart_dat_i,
    input         wb_uart_ack_i,
    input         wb_uart_err_i,
    input         wb_uart_rty_i,
    output [31:0] wb_ram_adr_o,
    output [31:0] wb_ram_dat_o,
    output  [3:0] wb_ram_sel_o,
    output        wb_ram_we_o,
    output        wb_ram_cyc_o,
    output        wb_ram_stb_o,
    output  [2:0] wb_ram_cti_o,
    output  [1:0] wb_ram_bte_o,
    input  [31:0] wb_ram_dat_i,
    input         wb_ram_ack_i,
    input         wb_ram_err_i,
    input         wb_ram_rty_i,
    output [31:0] wb_rom_adr_o,
    output [31:0] wb_rom_dat_o,
    output  [3:0] wb_rom_sel_o,
    output        wb_rom_we_o,
    output        wb_rom_cyc_o,
    output        wb_rom_stb_o,
    output  [2:0] wb_rom_cti_o,
    output  [1:0] wb_rom_bte_o,
    input  [31:0] wb_rom_dat_i,
    input         wb_rom_ack_i,
    input         wb_rom_err_i,
    input         wb_rom_rty_i,
    output [31:0] wb_fw_interface_adr_o,
    output [31:0] wb_fw_interface_dat_o,
    output  [3:0] wb_fw_interface_sel_o,
    output        wb_fw_interface_we_o,
    output        wb_fw_interface_cyc_o,
    output        wb_fw_interface_stb_o,
    output  [2:0] wb_fw_interface_cti_o,
    output  [1:0] wb_fw_interface_bte_o,
    input  [31:0] wb_fw_interface_dat_i,
    input         wb_fw_interface_ack_i,
    input         wb_fw_interface_err_i,
    input         wb_fw_interface_rty_i);

wire [31:0] wb_m2s_iwmb_ram_adr;
wire [31:0] wb_m2s_iwmb_ram_dat;
wire  [3:0] wb_m2s_iwmb_ram_sel;
wire        wb_m2s_iwmb_ram_we;
wire        wb_m2s_iwmb_ram_cyc;
wire        wb_m2s_iwmb_ram_stb;
wire  [2:0] wb_m2s_iwmb_ram_cti;
wire  [1:0] wb_m2s_iwmb_ram_bte;
wire [31:0] wb_s2m_iwmb_ram_dat;
wire        wb_s2m_iwmb_ram_ack;
wire        wb_s2m_iwmb_ram_err;
wire        wb_s2m_iwmb_ram_rty;
wire [31:0] wb_m2s_iwmb_rom_adr;
wire [31:0] wb_m2s_iwmb_rom_dat;
wire  [3:0] wb_m2s_iwmb_rom_sel;
wire        wb_m2s_iwmb_rom_we;
wire        wb_m2s_iwmb_rom_cyc;
wire        wb_m2s_iwmb_rom_stb;
wire  [2:0] wb_m2s_iwmb_rom_cti;
wire  [1:0] wb_m2s_iwmb_rom_bte;
wire [31:0] wb_s2m_iwmb_rom_dat;
wire        wb_s2m_iwmb_rom_ack;
wire        wb_s2m_iwmb_rom_err;
wire        wb_s2m_iwmb_rom_rty;
wire [31:0] wb_m2s_iwmb_uart_adr;
wire [31:0] wb_m2s_iwmb_uart_dat;
wire  [3:0] wb_m2s_iwmb_uart_sel;
wire        wb_m2s_iwmb_uart_we;
wire        wb_m2s_iwmb_uart_cyc;
wire        wb_m2s_iwmb_uart_stb;
wire  [2:0] wb_m2s_iwmb_uart_cti;
wire  [1:0] wb_m2s_iwmb_uart_bte;
wire [31:0] wb_s2m_iwmb_uart_dat;
wire        wb_s2m_iwmb_uart_ack;
wire        wb_s2m_iwmb_uart_err;
wire        wb_s2m_iwmb_uart_rty;
wire [31:0] wb_m2s_iwmb_fw_interface_adr;
wire [31:0] wb_m2s_iwmb_fw_interface_dat;
wire  [3:0] wb_m2s_iwmb_fw_interface_sel;
wire        wb_m2s_iwmb_fw_interface_we;
wire        wb_m2s_iwmb_fw_interface_cyc;
wire        wb_m2s_iwmb_fw_interface_stb;
wire  [2:0] wb_m2s_iwmb_fw_interface_cti;
wire  [1:0] wb_m2s_iwmb_fw_interface_bte;
wire [31:0] wb_s2m_iwmb_fw_interface_dat;
wire        wb_s2m_iwmb_fw_interface_ack;
wire        wb_s2m_iwmb_fw_interface_err;
wire        wb_s2m_iwmb_fw_interface_rty;
wire [31:0] wb_m2s_dwmb_uart_adr;
wire [31:0] wb_m2s_dwmb_uart_dat;
wire  [3:0] wb_m2s_dwmb_uart_sel;
wire        wb_m2s_dwmb_uart_we;
wire        wb_m2s_dwmb_uart_cyc;
wire        wb_m2s_dwmb_uart_stb;
wire  [2:0] wb_m2s_dwmb_uart_cti;
wire  [1:0] wb_m2s_dwmb_uart_bte;
wire [31:0] wb_s2m_dwmb_uart_dat;
wire        wb_s2m_dwmb_uart_ack;
wire        wb_s2m_dwmb_uart_err;
wire        wb_s2m_dwmb_uart_rty;
wire [31:0] wb_m2s_dwmb_ram_adr;
wire [31:0] wb_m2s_dwmb_ram_dat;
wire  [3:0] wb_m2s_dwmb_ram_sel;
wire        wb_m2s_dwmb_ram_we;
wire        wb_m2s_dwmb_ram_cyc;
wire        wb_m2s_dwmb_ram_stb;
wire  [2:0] wb_m2s_dwmb_ram_cti;
wire  [1:0] wb_m2s_dwmb_ram_bte;
wire [31:0] wb_s2m_dwmb_ram_dat;
wire        wb_s2m_dwmb_ram_ack;
wire        wb_s2m_dwmb_ram_err;
wire        wb_s2m_dwmb_ram_rty;
wire [31:0] wb_m2s_dwmb_rom_adr;
wire [31:0] wb_m2s_dwmb_rom_dat;
wire  [3:0] wb_m2s_dwmb_rom_sel;
wire        wb_m2s_dwmb_rom_we;
wire        wb_m2s_dwmb_rom_cyc;
wire        wb_m2s_dwmb_rom_stb;
wire  [2:0] wb_m2s_dwmb_rom_cti;
wire  [1:0] wb_m2s_dwmb_rom_bte;
wire [31:0] wb_s2m_dwmb_rom_dat;
wire        wb_s2m_dwmb_rom_ack;
wire        wb_s2m_dwmb_rom_err;
wire        wb_s2m_dwmb_rom_rty;
wire [31:0] wb_m2s_dwmb_fw_interface_adr;
wire [31:0] wb_m2s_dwmb_fw_interface_dat;
wire  [3:0] wb_m2s_dwmb_fw_interface_sel;
wire        wb_m2s_dwmb_fw_interface_we;
wire        wb_m2s_dwmb_fw_interface_cyc;
wire        wb_m2s_dwmb_fw_interface_stb;
wire  [2:0] wb_m2s_dwmb_fw_interface_cti;
wire  [1:0] wb_m2s_dwmb_fw_interface_bte;
wire [31:0] wb_s2m_dwmb_fw_interface_dat;
wire        wb_s2m_dwmb_fw_interface_ack;
wire        wb_s2m_dwmb_fw_interface_err;
wire        wb_s2m_dwmb_fw_interface_rty;

wb_mux
  #(.num_slaves (4),
    .MATCH_ADDR ({32'h20000000, 32'h00000000, 32'h40000000, 32'he0000000}),
    .MATCH_MASK ({32'hffff8000, 32'hffff8000, 32'hffffffe0, 32'hffffff80}))
 wb_mux_iwmb
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i (wb_iwmb_adr_i),
    .wbm_dat_i (wb_iwmb_dat_i),
    .wbm_sel_i (wb_iwmb_sel_i),
    .wbm_we_i  (wb_iwmb_we_i),
    .wbm_cyc_i (wb_iwmb_cyc_i),
    .wbm_stb_i (wb_iwmb_stb_i),
    .wbm_cti_i (wb_iwmb_cti_i),
    .wbm_bte_i (wb_iwmb_bte_i),
    .wbm_dat_o (wb_iwmb_dat_o),
    .wbm_ack_o (wb_iwmb_ack_o),
    .wbm_err_o (wb_iwmb_err_o),
    .wbm_rty_o (wb_iwmb_rty_o),
    .wbs_adr_o ({wb_m2s_iwmb_ram_adr, wb_m2s_iwmb_rom_adr, wb_m2s_iwmb_uart_adr, wb_m2s_iwmb_fw_interface_adr}),
    .wbs_dat_o ({wb_m2s_iwmb_ram_dat, wb_m2s_iwmb_rom_dat, wb_m2s_iwmb_uart_dat, wb_m2s_iwmb_fw_interface_dat}),
    .wbs_sel_o ({wb_m2s_iwmb_ram_sel, wb_m2s_iwmb_rom_sel, wb_m2s_iwmb_uart_sel, wb_m2s_iwmb_fw_interface_sel}),
    .wbs_we_o  ({wb_m2s_iwmb_ram_we, wb_m2s_iwmb_rom_we, wb_m2s_iwmb_uart_we, wb_m2s_iwmb_fw_interface_we}),
    .wbs_cyc_o ({wb_m2s_iwmb_ram_cyc, wb_m2s_iwmb_rom_cyc, wb_m2s_iwmb_uart_cyc, wb_m2s_iwmb_fw_interface_cyc}),
    .wbs_stb_o ({wb_m2s_iwmb_ram_stb, wb_m2s_iwmb_rom_stb, wb_m2s_iwmb_uart_stb, wb_m2s_iwmb_fw_interface_stb}),
    .wbs_cti_o ({wb_m2s_iwmb_ram_cti, wb_m2s_iwmb_rom_cti, wb_m2s_iwmb_uart_cti, wb_m2s_iwmb_fw_interface_cti}),
    .wbs_bte_o ({wb_m2s_iwmb_ram_bte, wb_m2s_iwmb_rom_bte, wb_m2s_iwmb_uart_bte, wb_m2s_iwmb_fw_interface_bte}),
    .wbs_dat_i ({wb_s2m_iwmb_ram_dat, wb_s2m_iwmb_rom_dat, wb_s2m_iwmb_uart_dat, wb_s2m_iwmb_fw_interface_dat}),
    .wbs_ack_i ({wb_s2m_iwmb_ram_ack, wb_s2m_iwmb_rom_ack, wb_s2m_iwmb_uart_ack, wb_s2m_iwmb_fw_interface_ack}),
    .wbs_err_i ({wb_s2m_iwmb_ram_err, wb_s2m_iwmb_rom_err, wb_s2m_iwmb_uart_err, wb_s2m_iwmb_fw_interface_err}),
    .wbs_rty_i ({wb_s2m_iwmb_ram_rty, wb_s2m_iwmb_rom_rty, wb_s2m_iwmb_uart_rty, wb_s2m_iwmb_fw_interface_rty}));

wb_mux
  #(.num_slaves (4),
    .MATCH_ADDR ({32'h40000000, 32'h20000000, 32'h00000000, 32'he0000000}),
    .MATCH_MASK ({32'hffffffe0, 32'hffff8000, 32'hffff8000, 32'hffffff80}))
 wb_mux_dwmb
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i (wb_dwmb_adr_i),
    .wbm_dat_i (wb_dwmb_dat_i),
    .wbm_sel_i (wb_dwmb_sel_i),
    .wbm_we_i  (wb_dwmb_we_i),
    .wbm_cyc_i (wb_dwmb_cyc_i),
    .wbm_stb_i (wb_dwmb_stb_i),
    .wbm_cti_i (wb_dwmb_cti_i),
    .wbm_bte_i (wb_dwmb_bte_i),
    .wbm_dat_o (wb_dwmb_dat_o),
    .wbm_ack_o (wb_dwmb_ack_o),
    .wbm_err_o (wb_dwmb_err_o),
    .wbm_rty_o (wb_dwmb_rty_o),
    .wbs_adr_o ({wb_m2s_dwmb_uart_adr, wb_m2s_dwmb_ram_adr, wb_m2s_dwmb_rom_adr, wb_m2s_dwmb_fw_interface_adr}),
    .wbs_dat_o ({wb_m2s_dwmb_uart_dat, wb_m2s_dwmb_ram_dat, wb_m2s_dwmb_rom_dat, wb_m2s_dwmb_fw_interface_dat}),
    .wbs_sel_o ({wb_m2s_dwmb_uart_sel, wb_m2s_dwmb_ram_sel, wb_m2s_dwmb_rom_sel, wb_m2s_dwmb_fw_interface_sel}),
    .wbs_we_o  ({wb_m2s_dwmb_uart_we, wb_m2s_dwmb_ram_we, wb_m2s_dwmb_rom_we, wb_m2s_dwmb_fw_interface_we}),
    .wbs_cyc_o ({wb_m2s_dwmb_uart_cyc, wb_m2s_dwmb_ram_cyc, wb_m2s_dwmb_rom_cyc, wb_m2s_dwmb_fw_interface_cyc}),
    .wbs_stb_o ({wb_m2s_dwmb_uart_stb, wb_m2s_dwmb_ram_stb, wb_m2s_dwmb_rom_stb, wb_m2s_dwmb_fw_interface_stb}),
    .wbs_cti_o ({wb_m2s_dwmb_uart_cti, wb_m2s_dwmb_ram_cti, wb_m2s_dwmb_rom_cti, wb_m2s_dwmb_fw_interface_cti}),
    .wbs_bte_o ({wb_m2s_dwmb_uart_bte, wb_m2s_dwmb_ram_bte, wb_m2s_dwmb_rom_bte, wb_m2s_dwmb_fw_interface_bte}),
    .wbs_dat_i ({wb_s2m_dwmb_uart_dat, wb_s2m_dwmb_ram_dat, wb_s2m_dwmb_rom_dat, wb_s2m_dwmb_fw_interface_dat}),
    .wbs_ack_i ({wb_s2m_dwmb_uart_ack, wb_s2m_dwmb_ram_ack, wb_s2m_dwmb_rom_ack, wb_s2m_dwmb_fw_interface_ack}),
    .wbs_err_i ({wb_s2m_dwmb_uart_err, wb_s2m_dwmb_ram_err, wb_s2m_dwmb_rom_err, wb_s2m_dwmb_fw_interface_err}),
    .wbs_rty_i ({wb_s2m_dwmb_uart_rty, wb_s2m_dwmb_ram_rty, wb_s2m_dwmb_rom_rty, wb_s2m_dwmb_fw_interface_rty}));

wb_arbiter
  #(.num_masters (2))
 wb_arbiter_uart
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i ({wb_m2s_iwmb_uart_adr, wb_m2s_dwmb_uart_adr}),
    .wbm_dat_i ({wb_m2s_iwmb_uart_dat, wb_m2s_dwmb_uart_dat}),
    .wbm_sel_i ({wb_m2s_iwmb_uart_sel, wb_m2s_dwmb_uart_sel}),
    .wbm_we_i  ({wb_m2s_iwmb_uart_we, wb_m2s_dwmb_uart_we}),
    .wbm_cyc_i ({wb_m2s_iwmb_uart_cyc, wb_m2s_dwmb_uart_cyc}),
    .wbm_stb_i ({wb_m2s_iwmb_uart_stb, wb_m2s_dwmb_uart_stb}),
    .wbm_cti_i ({wb_m2s_iwmb_uart_cti, wb_m2s_dwmb_uart_cti}),
    .wbm_bte_i ({wb_m2s_iwmb_uart_bte, wb_m2s_dwmb_uart_bte}),
    .wbm_dat_o ({wb_s2m_iwmb_uart_dat, wb_s2m_dwmb_uart_dat}),
    .wbm_ack_o ({wb_s2m_iwmb_uart_ack, wb_s2m_dwmb_uart_ack}),
    .wbm_err_o ({wb_s2m_iwmb_uart_err, wb_s2m_dwmb_uart_err}),
    .wbm_rty_o ({wb_s2m_iwmb_uart_rty, wb_s2m_dwmb_uart_rty}),
    .wbs_adr_o (wb_uart_adr_o),
    .wbs_dat_o (wb_uart_dat_o),
    .wbs_sel_o (wb_uart_sel_o),
    .wbs_we_o  (wb_uart_we_o),
    .wbs_cyc_o (wb_uart_cyc_o),
    .wbs_stb_o (wb_uart_stb_o),
    .wbs_cti_o (wb_uart_cti_o),
    .wbs_bte_o (wb_uart_bte_o),
    .wbs_dat_i (wb_uart_dat_i),
    .wbs_ack_i (wb_uart_ack_i),
    .wbs_err_i (wb_uart_err_i),
    .wbs_rty_i (wb_uart_rty_i));

wb_arbiter
  #(.num_masters (2))
 wb_arbiter_ram
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i ({wb_m2s_iwmb_ram_adr, wb_m2s_dwmb_ram_adr}),
    .wbm_dat_i ({wb_m2s_iwmb_ram_dat, wb_m2s_dwmb_ram_dat}),
    .wbm_sel_i ({wb_m2s_iwmb_ram_sel, wb_m2s_dwmb_ram_sel}),
    .wbm_we_i  ({wb_m2s_iwmb_ram_we, wb_m2s_dwmb_ram_we}),
    .wbm_cyc_i ({wb_m2s_iwmb_ram_cyc, wb_m2s_dwmb_ram_cyc}),
    .wbm_stb_i ({wb_m2s_iwmb_ram_stb, wb_m2s_dwmb_ram_stb}),
    .wbm_cti_i ({wb_m2s_iwmb_ram_cti, wb_m2s_dwmb_ram_cti}),
    .wbm_bte_i ({wb_m2s_iwmb_ram_bte, wb_m2s_dwmb_ram_bte}),
    .wbm_dat_o ({wb_s2m_iwmb_ram_dat, wb_s2m_dwmb_ram_dat}),
    .wbm_ack_o ({wb_s2m_iwmb_ram_ack, wb_s2m_dwmb_ram_ack}),
    .wbm_err_o ({wb_s2m_iwmb_ram_err, wb_s2m_dwmb_ram_err}),
    .wbm_rty_o ({wb_s2m_iwmb_ram_rty, wb_s2m_dwmb_ram_rty}),
    .wbs_adr_o (wb_ram_adr_o),
    .wbs_dat_o (wb_ram_dat_o),
    .wbs_sel_o (wb_ram_sel_o),
    .wbs_we_o  (wb_ram_we_o),
    .wbs_cyc_o (wb_ram_cyc_o),
    .wbs_stb_o (wb_ram_stb_o),
    .wbs_cti_o (wb_ram_cti_o),
    .wbs_bte_o (wb_ram_bte_o),
    .wbs_dat_i (wb_ram_dat_i),
    .wbs_ack_i (wb_ram_ack_i),
    .wbs_err_i (wb_ram_err_i),
    .wbs_rty_i (wb_ram_rty_i));

wb_arbiter
  #(.num_masters (2))
 wb_arbiter_rom
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i ({wb_m2s_iwmb_rom_adr, wb_m2s_dwmb_rom_adr}),
    .wbm_dat_i ({wb_m2s_iwmb_rom_dat, wb_m2s_dwmb_rom_dat}),
    .wbm_sel_i ({wb_m2s_iwmb_rom_sel, wb_m2s_dwmb_rom_sel}),
    .wbm_we_i  ({wb_m2s_iwmb_rom_we, wb_m2s_dwmb_rom_we}),
    .wbm_cyc_i ({wb_m2s_iwmb_rom_cyc, wb_m2s_dwmb_rom_cyc}),
    .wbm_stb_i ({wb_m2s_iwmb_rom_stb, wb_m2s_dwmb_rom_stb}),
    .wbm_cti_i ({wb_m2s_iwmb_rom_cti, wb_m2s_dwmb_rom_cti}),
    .wbm_bte_i ({wb_m2s_iwmb_rom_bte, wb_m2s_dwmb_rom_bte}),
    .wbm_dat_o ({wb_s2m_iwmb_rom_dat, wb_s2m_dwmb_rom_dat}),
    .wbm_ack_o ({wb_s2m_iwmb_rom_ack, wb_s2m_dwmb_rom_ack}),
    .wbm_err_o ({wb_s2m_iwmb_rom_err, wb_s2m_dwmb_rom_err}),
    .wbm_rty_o ({wb_s2m_iwmb_rom_rty, wb_s2m_dwmb_rom_rty}),
    .wbs_adr_o (wb_rom_adr_o),
    .wbs_dat_o (wb_rom_dat_o),
    .wbs_sel_o (wb_rom_sel_o),
    .wbs_we_o  (wb_rom_we_o),
    .wbs_cyc_o (wb_rom_cyc_o),
    .wbs_stb_o (wb_rom_stb_o),
    .wbs_cti_o (wb_rom_cti_o),
    .wbs_bte_o (wb_rom_bte_o),
    .wbs_dat_i (wb_rom_dat_i),
    .wbs_ack_i (wb_rom_ack_i),
    .wbs_err_i (wb_rom_err_i),
    .wbs_rty_i (wb_rom_rty_i));

wb_arbiter
  #(.num_masters (2))
 wb_arbiter_fw_interface
   (.wb_clk_i  (wb_clk_i),
    .wb_rst_i  (wb_rst_i),
    .wbm_adr_i ({wb_m2s_iwmb_fw_interface_adr, wb_m2s_dwmb_fw_interface_adr}),
    .wbm_dat_i ({wb_m2s_iwmb_fw_interface_dat, wb_m2s_dwmb_fw_interface_dat}),
    .wbm_sel_i ({wb_m2s_iwmb_fw_interface_sel, wb_m2s_dwmb_fw_interface_sel}),
    .wbm_we_i  ({wb_m2s_iwmb_fw_interface_we, wb_m2s_dwmb_fw_interface_we}),
    .wbm_cyc_i ({wb_m2s_iwmb_fw_interface_cyc, wb_m2s_dwmb_fw_interface_cyc}),
    .wbm_stb_i ({wb_m2s_iwmb_fw_interface_stb, wb_m2s_dwmb_fw_interface_stb}),
    .wbm_cti_i ({wb_m2s_iwmb_fw_interface_cti, wb_m2s_dwmb_fw_interface_cti}),
    .wbm_bte_i ({wb_m2s_iwmb_fw_interface_bte, wb_m2s_dwmb_fw_interface_bte}),
    .wbm_dat_o ({wb_s2m_iwmb_fw_interface_dat, wb_s2m_dwmb_fw_interface_dat}),
    .wbm_ack_o ({wb_s2m_iwmb_fw_interface_ack, wb_s2m_dwmb_fw_interface_ack}),
    .wbm_err_o ({wb_s2m_iwmb_fw_interface_err, wb_s2m_dwmb_fw_interface_err}),
    .wbm_rty_o ({wb_s2m_iwmb_fw_interface_rty, wb_s2m_dwmb_fw_interface_rty}),
    .wbs_adr_o (wb_fw_interface_adr_o),
    .wbs_dat_o (wb_fw_interface_dat_o),
    .wbs_sel_o (wb_fw_interface_sel_o),
    .wbs_we_o  (wb_fw_interface_we_o),
    .wbs_cyc_o (wb_fw_interface_cyc_o),
    .wbs_stb_o (wb_fw_interface_stb_o),
    .wbs_cti_o (wb_fw_interface_cti_o),
    .wbs_bte_o (wb_fw_interface_bte_o),
    .wbs_dat_i (wb_fw_interface_dat_i),
    .wbs_ack_i (wb_fw_interface_ack_i),
    .wbs_err_i (wb_fw_interface_err_i),
    .wbs_rty_i (wb_fw_interface_rty_i));

endmodule
