/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */

(* src = "../../verilog/counter.v:1" *)
module Counter(Reset_n_i, Clk_i, ResetSig_i, Preset_i, Enable_i, Direction_i, PresetVal_i, D_o, Overflow_o, Zero_o);
  (* src = "../../verilog/counter.v:28" *)
  wire [16:0] \$0\Value[16:0] ;
  (* src = "../../verilog/counter.v:43" *)
  wire [16:0] \$add$../../verilog/counter.v:43$4_Y ;
  wire [16:0] \$procmux$22_Y ;
  wire [16:0] \$procmux$24_Y ;
  wire [16:0] \$procmux$27_Y ;
  (* src = "../../verilog/counter.v:45" *)
  wire [16:0] \$sub$../../verilog/counter.v:45$5_Y ;
  (* intersynth_port = "Clk_i" *)
  (* src = "../../verilog/counter.v:7" *)
  input Clk_i;
  (* intersynth_conntype = "Word" *)
  (* src = "../../verilog/counter.v:19" *)
  output [15:0] D_o;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:15" *)
  input Direction_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:13" *)
  input Enable_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:21" *)
  output Overflow_o;
  (* intersynth_conntype = "Word" *)
  (* src = "../../verilog/counter.v:17" *)
  input [15:0] PresetVal_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:11" *)
  input Preset_i;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:9" *)
  input ResetSig_i;
  (* intersynth_port = "Reset_n_i" *)
  (* src = "../../verilog/counter.v:5" *)
  input Reset_n_i;
  (* src = "../../verilog/counter.v:26" *)
  wire [16:0] Value;
  (* intersynth_conntype = "Bit" *)
  (* src = "../../verilog/counter.v:23" *)
  output Zero_o;
  (* src = "../../verilog/counter.v:43" *)
  \$add  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000010001)
  ) \$add$../../verilog/counter.v:43$4  (
    .A({ 1'b0, Value[15:0] }),
    .B(1'b1),
    .Y(\$add$../../verilog/counter.v:43$4_Y )
  );
  (* src = "../../verilog/counter.v:52" *)
  \$eq  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010000),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000010000),
    .Y_WIDTH(32'b00000000000000000000000000000001)
  ) \$eq$../../verilog/counter.v:52$6  (
    .A(Value[15:0]),
    .B(16'b0000000000000000),
    .Y(Zero_o)
  );
  (* src = "../../verilog/counter.v:28" *)
  \$adff  #(
    .ARST_POLARITY(1'b0),
    .ARST_VALUE(17'b00000000000000000),
    .CLK_POLARITY(1'b1),
    .WIDTH(32'b00000000000000000000000000010001)
  ) \$procdff$62  (
    .ARST(Reset_n_i),
    .CLK(Clk_i),
    .D(\$0\Value[16:0] ),
    .Q(Value)
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010001)
  ) \$procmux$22  (
    .A(\$add$../../verilog/counter.v:43$4_Y ),
    .B(\$sub$../../verilog/counter.v:45$5_Y ),
    .S(Direction_i),
    .Y(\$procmux$22_Y )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010001)
  ) \$procmux$24  (
    .A(Value),
    .B(\$procmux$22_Y ),
    .S(Enable_i),
    .Y(\$procmux$24_Y )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010001)
  ) \$procmux$27  (
    .A(\$procmux$24_Y ),
    .B({ 1'b0, PresetVal_i }),
    .S(Preset_i),
    .Y(\$procmux$27_Y )
  );
  \$mux  #(
    .WIDTH(32'b00000000000000000000000000010001)
  ) \$procmux$30  (
    .A(\$procmux$27_Y ),
    .B(17'b00000000000000000),
    .S(ResetSig_i),
    .Y(\$0\Value[16:0] )
  );
  (* src = "../../verilog/counter.v:45" *)
  \$sub  #(
    .A_SIGNED(32'b00000000000000000000000000000000),
    .A_WIDTH(32'b00000000000000000000000000010001),
    .B_SIGNED(32'b00000000000000000000000000000000),
    .B_WIDTH(32'b00000000000000000000000000000001),
    .Y_WIDTH(32'b00000000000000000000000000010001)
  ) \$sub$../../verilog/counter.v:45$5  (
    .A({ 1'b0, Value[15:0] }),
    .B(1'b1),
    .Y(\$sub$../../verilog/counter.v:45$5_Y )
  );
  assign D_o = Value[15:0];
  assign Overflow_o = Value[16];
endmodule
