`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:21:14 11/01/2013 
// Design Name: 
// Module Name:    clock_divider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider(input clock, input reset, input[5:0] counter, output reg clock_out);

	reg[5:0] temp_counter;
	
	initial 
		begin
			temp_counter <= 6'b0;
			clock_out <= 1'b0;
		end
			
	always @(posedge clock or posedge reset)
	begin
		if(reset)
			begin
				temp_counter <= 6'b0;
				clock_out <= 1'b0;
			end
		else
			if(temp_counter == counter) //va convertir un clk de 50MHz a 1Hz
				begin
					temp_counter <= 6'b0;
					clock_out <= ~clock_out;
				end
			else
				begin
					temp_counter <= temp_counter + 1;
				end
	end	
	
endmodule
