// File: clock.v
// Generated by MyHDL 0.8.1
// Date: Sun May 15 22:24:35 2016

`timescale 500ms/1ms

module clock (
    clk,
    fast_clk,
    rst,
    en,
    sec,
    pm,
    io_seg,
    io_sel
);

input clk;
input fast_clk;
input rst;
input en;
output [7:0] sec;
reg [7:0] sec;
output [17:0] pm;
reg [17:0] pm;
output [7:0] io_seg;
wire [7:0] io_seg;
output [3:0] io_sel; // Digit select on IO Shield
wire [3:0] io_sel;

reg [3:0] count [0:6-1];
reg [1:0] i, j;

// CLOCK_DECODER 74LS247
assign io_seg[0] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[1] = (((count[i+2][0] && (!count[i+2][1]) && count[i+2][2]) || ((!count[i+2][0]) && count[i+2][1] && count[i+2][2]) || (count[i+2][1] && count[i+2][3])) != 0);
assign io_seg[2] = ((((!count[i+2][0]) && count[i+2][1] && (!count[i+2][2])) || (count[i+2][2] && count[i+2][3])) != 0);
assign io_seg[3] = (((count[i+2][0] && (!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][0]) && (!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[4] = ((count[i+2][0] || ((!count[i+2][1]) && count[i+2][2])) != 0);
assign io_seg[5] = (((count[i+2][0] && (!count[i+2][2]) && (!count[i+2][3])) || (count[i+2][0] && count[i+2][1]) || (count[i+2][1] && (!count[i+2][2]))) != 0);
assign io_seg[6] = (((count[i+2][0] && count[i+2][1] && count[i+2][2]) || ((!count[i+2][1]) && (!count[i+2][2]) && (!count[i+2][3]))) != 0);
assign io_seg[7] = 1'b1 && ~(~i[0] && i[1]);

// Select 7-segment display to show digit
assign io_sel[0] = ~(~i[0] && ~i[1]);
assign io_sel[1] = ~(i[0] && ~i[1]);
assign io_sel[2] = ~(~i[0] && i[1]);
assign io_sel[3] = ~(i[0] && i[1]) || (count[5] == 0);

always @(i) begin
    j = i + 1'b1;
end

always @(posedge fast_clk, negedge fast_clk) begin
    if (rst) begin
        i <= 1'b0;
    end else begin
        i <= j;
    end
end

always @(posedge clk, posedge rst) begin: CLOCK_COUNTER
    if (rst) begin
        count[0] <= 0;
        count[1] <= 0;
        count[2] <= 0;
        count[3] <= 0;
        count[4] <= 0;
    end else if (en) begin
        count[0] <= ((count[0] + 1) % 10);
        count[1] <= ((count[1] + (count[0] == 9)) % 6);
        count[2] <= ((count[2] + ((count[0] == 9) && (count[1] == 5))) % 10);
        count[3] <= ((count[3] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9))) % 6);
        count[4] <= (((count[4] + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5))) % (10 - (7 * count[5]))) + ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0)));
    end
end

always @(posedge clk, posedge rst) begin: CLOCK_TFF
    if (rst) begin
        count[5] <= 0;
        pm <= 18'b0;
        sec <= 8'b0;
    end else if (en) begin
        count[5] <= ((count[5] != 0) ^ (((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 9)) || ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 2) && (count[5] != 0))));
        pm <= {18{(pm[0] ^ ((count[0] == 9) && (count[1] == 5) && (count[2] == 9) && (count[3] == 5) && (count[4] == 1) && (count[5] != 0)))}};
        sec <= (count[0]+10*count[1]+1) % 60;
    end
end

endmodule