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`timescale 1 ns / 1 ps

module delay_gen150us (/*AUTOARG*/
    // Outputs
    o_lfsr_256_done,
    // Inputs
    i_sys_rst, i_sys_clk
    );

    input               i_sys_clk;              // To U1 of lfsr_count64.v, ...
    input               i_sys_rst;              // To U1 of lfsr_count64.v, ...
    output              o_lfsr_256_done;        // From U5 of lfsr_count256.v
    wire              lfsr_64_done_i;         // From U1 of lfsr_count64.v
  
    lfsr_count64 U1(/*AUTOINST*/
                    // Outputs
                    .o_lfsr_64_done     (lfsr_64_done_i),
                    // Inputs
                    .i_sys_clk          (i_sys_clk),
                    .i_sys_rst          (i_sys_rst));
    lfsr_count255 U5(/*AUTOINST*/
                     // Outputs
                     .o_lfsr_256_done   (o_lfsr_256_done),
                     // Inputs
                     .i_sys_clk         (lfsr_64_done_i),
                     .i_sys_rst         (i_sys_rst));
        
endmodule // delay_gen150us
