// Avalon_Test_Streaming.v

// Generated using ACDS version 16.1 196

`timescale 1 ps / 1 ps
module Avalon_Test_Streaming (
	);

	wire   [0:0] st_source_bfm_src_valid;      // st_source_bfm:src_valid -> st_sink_bfm:sink_valid
	wire  [31:0] st_source_bfm_src_data;       // st_source_bfm:src_data -> st_sink_bfm:sink_data
	wire         st_source_bfm_src_ready;      // st_sink_bfm:sink_ready -> st_source_bfm:src_ready
	wire   [0:0] st_source_bfm_src_channel;    // st_source_bfm:src_channel -> st_sink_bfm:sink_channel
	wire         clock_source_bfm_clk_clk;     // clock_source_bfm:clk -> [reset_source_bfm:clk, st_sink_bfm:clk, st_source_bfm:clk]
	wire         reset_source_bfm_reset_reset; // reset_source_bfm:reset -> [st_sink_bfm:reset, st_source_bfm:reset]

	altera_avalon_clock_source #(
		.CLOCK_RATE (50),
		.CLOCK_UNIT (1000000)
	) clock_source_bfm (
		.clk (clock_source_bfm_clk_clk)  // clk.clk
	);

	altera_avalon_reset_source #(
		.ASSERT_HIGH_RESET    (1),
		.INITIAL_RESET_CYCLES (10)
	) reset_source_bfm (
		.reset (reset_source_bfm_reset_reset), // reset.reset
		.clk   (clock_source_bfm_clk_clk)      //   clk.clk
	);

	altera_avalon_st_sink_bfm #(
		.USE_PACKET       (0),
		.USE_CHANNEL      (1),
		.USE_ERROR        (0),
		.USE_READY        (1),
		.USE_VALID        (1),
		.USE_EMPTY        (0),
		.ST_SYMBOL_W      (8),
		.ST_NUMSYMBOLS    (4),
		.ST_CHANNEL_W     (1),
		.ST_ERROR_W       (1),
		.ST_EMPTY_W       (2),
		.ST_READY_LATENCY (0),
		.ST_BEATSPERCYCLE (1),
		.ST_MAX_CHANNELS  (1),
		.VHDL_ID          (0)
	) st_sink_bfm (
		.clk                (clock_source_bfm_clk_clk),     //       clk.clk
		.reset              (reset_source_bfm_reset_reset), // clk_reset.reset
		.sink_data          (st_source_bfm_src_data),       //      sink.data
		.sink_valid         (st_source_bfm_src_valid),      //          .valid
		.sink_ready         (st_source_bfm_src_ready),      //          .ready
		.sink_channel       (st_source_bfm_src_channel),    //          .channel
		.sink_startofpacket (1'b0),                         // (terminated)
		.sink_endofpacket   (1'b0),                         // (terminated)
		.sink_empty         (2'b00),                        // (terminated)
		.sink_error         (1'b0)                          // (terminated)
	);

	altera_avalon_st_source_bfm #(
		.USE_PACKET       (0),
		.USE_CHANNEL      (1),
		.USE_ERROR        (0),
		.USE_READY        (1),
		.USE_VALID        (1),
		.USE_EMPTY        (0),
		.ST_SYMBOL_W      (8),
		.ST_NUMSYMBOLS    (4),
		.ST_CHANNEL_W     (1),
		.ST_ERROR_W       (1),
		.ST_EMPTY_W       (2),
		.ST_READY_LATENCY (0),
		.ST_BEATSPERCYCLE (1),
		.ST_MAX_CHANNELS  (1),
		.VHDL_ID          (0)
	) st_source_bfm (
		.clk               (clock_source_bfm_clk_clk),     //       clk.clk
		.reset             (reset_source_bfm_reset_reset), // clk_reset.reset
		.src_data          (st_source_bfm_src_data),       //       src.data
		.src_valid         (st_source_bfm_src_valid),      //          .valid
		.src_ready         (st_source_bfm_src_ready),      //          .ready
		.src_channel       (st_source_bfm_src_channel),    //          .channel
		.src_startofpacket (),                             // (terminated)
		.src_endofpacket   (),                             // (terminated)
		.src_empty         (),                             // (terminated)
		.src_error         ()                              // (terminated)
	);

endmodule
