// -------------------------------------------------------------
// 
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Clarke_Transform.v
// Created: 2014-08-25 21:11:09
// 
// Generated by MATLAB 8.2 and HDL Coder 3.3
// 
// -------------------------------------------------------------


// -------------------------------------------------------------
// 
// Module: velocityControlHdl_Clarke_Transform
// Source Path: velocityControlHdl/Transform_ABC_to_dq/Clarke_Transform
// Hierarchy Level: 5
// 
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module velocityControlHdl_Clarke_Transform
          (
           phase_currents_0,
           phase_currents_1,
           alpha_current,
           beta_current
          );


  input   signed [17:0] phase_currents_0;  // sfix18_En15
  input   signed [17:0] phase_currents_1;  // sfix18_En15
  output  signed [17:0] alpha_current;  // sfix18_En13
  output  signed [17:0] beta_current;  // sfix18_En13


  wire signed [17:0] Alpha_Current_Data_Type_out1;  // sfix18_En13
  wire signed [35:0] Alpha_Gain_With_Headrom_out1;  // sfix36_En31
  wire signed [35:0] Beta_Gain_With_Headrom_out1;  // sfix36_En31
  wire signed [35:0] Add_out1;  // sfix36_En31
  wire signed [17:0] Beta_Current_Data_Type_out1;  // sfix18_En13

  // Converts balanced three-phase quantities into balanced two-phase quantities.
  // The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component.
  // The alpha and beta components are still dependent on time and speed.
  // 
  // Clarke Transform


  // <S41>/Alpha_Current_Data_Type
  // 
  // <S41>/A_phase_current
  // 
  // <S41>/B_phase_current
  assign Alpha_Current_Data_Type_out1 = {{2{phase_currents_0[17]}}, phase_currents_0[17:2]};



  assign alpha_current = Alpha_Current_Data_Type_out1;

  // <S41>/Alpha_Gain_With_Headrom
  assign Alpha_Gain_With_Headrom_out1 = 37837 * phase_currents_0;



  // <S41>/Beta_Gain_With_Headrom
  assign Beta_Gain_With_Headrom_out1 = 75674 * phase_currents_1;



  // <S41>/Add
  assign Add_out1 = Alpha_Gain_With_Headrom_out1 + Beta_Gain_With_Headrom_out1;



  // <S41>/Beta_Current_Data_Type
  assign Beta_Current_Data_Type_out1 = Add_out1[35:18];



  assign beta_current = Beta_Current_Data_Type_out1;

endmodule  // velocityControlHdl_Clarke_Transform

