// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="doHist,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.860000,HLS_SYN_LAT=524546,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=95,HLS_SYN_LUT=210}" *)

module doHist (
        ap_clk,
        ap_rst_n,
        inStream_TDATA,
        inStream_TVALID,
        inStream_TREADY,
        inStream_TKEEP,
        inStream_TSTRB,
        inStream_TUSER,
        inStream_TLAST,
        inStream_TID,
        inStream_TDEST,
        histo_Addr_A,
        histo_EN_A,
        histo_WEN_A,
        histo_Din_A,
        histo_Dout_A,
        histo_Clk_A,
        histo_Rst_A,
        s_axi_CTRL_BUS_AWVALID,
        s_axi_CTRL_BUS_AWREADY,
        s_axi_CTRL_BUS_AWADDR,
        s_axi_CTRL_BUS_WVALID,
        s_axi_CTRL_BUS_WREADY,
        s_axi_CTRL_BUS_WDATA,
        s_axi_CTRL_BUS_WSTRB,
        s_axi_CTRL_BUS_ARVALID,
        s_axi_CTRL_BUS_ARREADY,
        s_axi_CTRL_BUS_ARADDR,
        s_axi_CTRL_BUS_RVALID,
        s_axi_CTRL_BUS_RREADY,
        s_axi_CTRL_BUS_RDATA,
        s_axi_CTRL_BUS_RRESP,
        s_axi_CTRL_BUS_BVALID,
        s_axi_CTRL_BUS_BREADY,
        s_axi_CTRL_BUS_BRESP,
        interrupt
);

parameter    ap_ST_st1_fsm_0 = 4'b1;
parameter    ap_ST_st2_fsm_1 = 4'b10;
parameter    ap_ST_st3_fsm_2 = 4'b100;
parameter    ap_ST_st4_fsm_3 = 4'b1000;
parameter    ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter    ap_const_lv32_2 = 32'b10;
parameter    C_S_AXI_CTRL_BUS_DATA_WIDTH = 32;
parameter    ap_const_int64_8 = 8;
parameter    C_S_AXI_CTRL_BUS_ADDR_WIDTH = 4;
parameter    C_S_AXI_DATA_WIDTH = 32;
parameter    ap_const_lv32_1 = 32'b1;
parameter    ap_const_lv9_0 = 9'b000000000;
parameter    ap_const_lv32_3 = 32'b11;
parameter    ap_const_lv19_0 = 19'b0000000000000000000;
parameter    ap_const_lv4_0 = 4'b0000;
parameter    ap_const_lv4_F = 4'b1111;
parameter    ap_const_lv9_100 = 9'b100000000;
parameter    ap_const_lv9_1 = 9'b1;
parameter    ap_const_lv19_40000 = 19'b1000000000000000000;
parameter    ap_const_lv19_1 = 19'b1;

parameter C_S_AXI_CTRL_BUS_WSTRB_WIDTH = (C_S_AXI_CTRL_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);

input   ap_clk;
input   ap_rst_n;
input  [7:0] inStream_TDATA;
input   inStream_TVALID;
output   inStream_TREADY;
input  [0:0] inStream_TKEEP;
input  [0:0] inStream_TSTRB;
input  [1:0] inStream_TUSER;
input  [0:0] inStream_TLAST;
input  [4:0] inStream_TID;
input  [5:0] inStream_TDEST;
output  [31:0] histo_Addr_A;
output   histo_EN_A;
output  [3:0] histo_WEN_A;
output  [31:0] histo_Din_A;
input  [31:0] histo_Dout_A;
output   histo_Clk_A;
output   histo_Rst_A;
input   s_axi_CTRL_BUS_AWVALID;
output   s_axi_CTRL_BUS_AWREADY;
input  [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_AWADDR;
input   s_axi_CTRL_BUS_WVALID;
output   s_axi_CTRL_BUS_WREADY;
input  [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_WDATA;
input  [C_S_AXI_CTRL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CTRL_BUS_WSTRB;
input   s_axi_CTRL_BUS_ARVALID;
output   s_axi_CTRL_BUS_ARREADY;
input  [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_ARADDR;
output   s_axi_CTRL_BUS_RVALID;
input   s_axi_CTRL_BUS_RREADY;
output  [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_RDATA;
output  [1:0] s_axi_CTRL_BUS_RRESP;
output   s_axi_CTRL_BUS_BVALID;
input   s_axi_CTRL_BUS_BREADY;
output  [1:0] s_axi_CTRL_BUS_BRESP;
output   interrupt;

reg inStream_TREADY;
reg histo_EN_A;
reg[3:0] histo_WEN_A;
reg[31:0] histo_Din_A;
reg histo_Rst_A;

reg    ap_rst_n_inv;
wire    ap_start;
reg    ap_done;
reg    ap_idle;
(* fsm_encoding = "none" *) reg   [3:0] ap_CS_fsm;
reg    ap_sig_cseq_ST_st1_fsm_0;
reg    ap_sig_21;
reg    ap_ready;
reg    inStream_TDATA_blk_n;
reg    ap_sig_cseq_ST_st3_fsm_2;
reg    ap_sig_53;
wire   [0:0] exitcond_fu_148_p2;
wire   [8:0] idxHist_1_fu_137_p2;
reg    ap_sig_cseq_ST_st2_fsm_1;
reg    ap_sig_102;
wire   [18:0] idxPixel_1_fu_154_p2;
reg   [18:0] idxPixel_1_reg_187;
reg    ap_sig_108;
reg   [7:0] histo_addr_1_reg_192;
reg   [8:0] idxHist_reg_109;
wire   [0:0] exitcond2_fu_131_p2;
reg   [18:0] idxPixel_reg_120;
reg    ap_sig_cseq_ST_st4_fsm_3;
reg    ap_sig_130;
wire   [63:0] tmp_fu_143_p1;
wire   [63:0] tmp_3_fu_164_p1;
reg   [31:0] histo_Addr_A_orig;
wire   [31:0] tmp_4_fu_169_p2;
reg   [3:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 4'b1;
end

doHist_CTRL_BUS_s_axi #(
    .C_S_AXI_ADDR_WIDTH( C_S_AXI_CTRL_BUS_ADDR_WIDTH ),
    .C_S_AXI_DATA_WIDTH( C_S_AXI_CTRL_BUS_DATA_WIDTH ))
doHist_CTRL_BUS_s_axi_U(
    .AWVALID(s_axi_CTRL_BUS_AWVALID),
    .AWREADY(s_axi_CTRL_BUS_AWREADY),
    .AWADDR(s_axi_CTRL_BUS_AWADDR),
    .WVALID(s_axi_CTRL_BUS_WVALID),
    .WREADY(s_axi_CTRL_BUS_WREADY),
    .WDATA(s_axi_CTRL_BUS_WDATA),
    .WSTRB(s_axi_CTRL_BUS_WSTRB),
    .ARVALID(s_axi_CTRL_BUS_ARVALID),
    .ARREADY(s_axi_CTRL_BUS_ARREADY),
    .ARADDR(s_axi_CTRL_BUS_ARADDR),
    .RVALID(s_axi_CTRL_BUS_RVALID),
    .RREADY(s_axi_CTRL_BUS_RREADY),
    .RDATA(s_axi_CTRL_BUS_RDATA),
    .RRESP(s_axi_CTRL_BUS_RRESP),
    .BVALID(s_axi_CTRL_BUS_BVALID),
    .BREADY(s_axi_CTRL_BUS_BREADY),
    .BRESP(s_axi_CTRL_BUS_BRESP),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .ap_start(ap_start),
    .interrupt(interrupt),
    .ap_ready(ap_ready),
    .ap_done(ap_done),
    .ap_idle(ap_idle)
);

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2))) begin
        idxHist_reg_109 <= idxHist_1_fu_137_p2;
    end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin
        idxHist_reg_109 <= ap_const_lv9_0;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond2_fu_131_p2))) begin
        idxPixel_reg_120 <= ap_const_lv19_0;
    end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        idxPixel_reg_120 <= idxPixel_1_reg_187;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
        histo_addr_1_reg_192 <= tmp_3_fu_164_p1;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108)) begin
        idxPixel_1_reg_187 <= idxPixel_1_fu_154_p2;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_21) begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st1_fsm_0 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_102) begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st2_fsm_1 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_53) begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st3_fsm_2 = 1'b0;
    end
end

always @ (*) begin
    if (ap_sig_130) begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b1;
    end else begin
        ap_sig_cseq_ST_st4_fsm_3 = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        histo_Addr_A_orig = histo_addr_1_reg_192;
    end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        histo_Addr_A_orig = tmp_fu_143_p1;
    end else if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin
        histo_Addr_A_orig = tmp_3_fu_164_p1;
    end else begin
        histo_Addr_A_orig = 'bx;
    end
end

always @ (*) begin
    if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin
        histo_Din_A = tmp_4_fu_169_p2;
    end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin
        histo_Din_A = ap_const_lv32_0;
    end else begin
        histo_Din_A = 'bx;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | ((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_108) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
        histo_EN_A = 1'b1;
    end else begin
        histo_EN_A = 1'b0;
    end
end

always @ (*) begin
    if ((((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_131_p2)) | (1'b1 == ap_sig_cseq_ST_st4_fsm_3))) begin
        histo_WEN_A = ap_const_lv4_F;
    end else begin
        histo_WEN_A = ap_const_lv4_0;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0))) begin
        inStream_TDATA_blk_n = inStream_TVALID;
    end else begin
        inStream_TDATA_blk_n = 1'b1;
    end
end

always @ (*) begin
    if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
        inStream_TREADY = 1'b1;
    end else begin
        inStream_TREADY = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_st1_fsm_0 : begin
            if (~(ap_start == 1'b0)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end
        end
        ap_ST_st2_fsm_1 : begin
            if ((1'b0 == exitcond2_fu_131_p2)) begin
                ap_NS_fsm = ap_ST_st2_fsm_1;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st3_fsm_2 : begin
            if ((~ap_sig_108 & ~(exitcond_fu_148_p2 == 1'b0))) begin
                ap_NS_fsm = ap_ST_st1_fsm_0;
            end else if (((exitcond_fu_148_p2 == 1'b0) & ~ap_sig_108)) begin
                ap_NS_fsm = ap_ST_st4_fsm_3;
            end else begin
                ap_NS_fsm = ap_ST_st3_fsm_2;
            end
        end
        ap_ST_st4_fsm_3 : begin
            ap_NS_fsm = ap_ST_st3_fsm_2;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

always @ (*) begin
    ap_rst_n_inv = ~ap_rst_n;
end

always @ (*) begin
    ap_sig_102 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]);
end

always @ (*) begin
    ap_sig_108 = ((exitcond_fu_148_p2 == 1'b0) & (inStream_TVALID == 1'b0));
end

always @ (*) begin
    ap_sig_130 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]);
end

always @ (*) begin
    ap_sig_21 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end

always @ (*) begin
    ap_sig_53 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]);
end

assign exitcond2_fu_131_p2 = ((idxHist_reg_109 == ap_const_lv9_100) ? 1'b1 : 1'b0);

assign exitcond_fu_148_p2 = ((idxPixel_reg_120 == ap_const_lv19_40000) ? 1'b1 : 1'b0);

assign histo_Addr_A = histo_Addr_A_orig << ap_const_lv32_2;

assign histo_Clk_A = ap_clk;

always @ (*) begin
    histo_Rst_A = ~ap_rst_n;
end

assign idxHist_1_fu_137_p2 = (idxHist_reg_109 + ap_const_lv9_1);

assign idxPixel_1_fu_154_p2 = (idxPixel_reg_120 + ap_const_lv19_1);

assign tmp_3_fu_164_p1 = inStream_TDATA;

assign tmp_4_fu_169_p2 = (histo_Dout_A + ap_const_lv32_1);

assign tmp_fu_143_p1 = idxHist_reg_109;

endmodule //doHist
