// nios_system.v

// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:12

`timescale 1 ps / 1 ps
module nios_system (
		output wire [31:0] alu_a_export,           //           alu_a.export
		output wire [31:0] alu_b_export,           //           alu_b.export
		input  wire        alu_carry_out_export,   //   alu_carry_out.export
		output wire [2:0]  alu_control_export,     //     alu_control.export
		input  wire        alu_negative_export,    //    alu_negative.export
		input  wire [31:0] alu_out_export,         //         alu_out.export
		input  wire        alu_overflow_export,    //    alu_overflow.export
		input  wire        alu_zero_export,        //        alu_zero.export
		input  wire        clk_clk,                //             clk.clk
		output wire [3:0]  hex_0_export,           //           hex_0.export
		output wire [3:0]  hex_1_export,           //           hex_1.export
		output wire [3:0]  hex_2_export,           //           hex_2.export
		output wire [3:0]  hex_3_export,           //           hex_3.export
		output wire [3:0]  hex_4_export,           //           hex_4.export
		output wire [3:0]  hex_5_export,           //           hex_5.export
		input  wire [3:0]  keys_export,            //            keys.export
		output wire [9:0]  leds_export,            //            leds.export
		output wire [31:0] regfile_data_export,    //    regfile_data.export
		output wire [5:0]  regfile_r1sel_export,   //   regfile_r1sel.export
		output wire [5:0]  regfile_r2sel_export,   //   regfile_r2sel.export
		input  wire [31:0] regfile_reg1_export,    //    regfile_reg1.export
		input  wire [31:0] regfile_reg2_export,    //    regfile_reg2.export
		output wire        regfile_we_export,      //      regfile_we.export
		output wire [5:0]  regfile_wsel_export,    //    regfile_wsel.export
		input  wire        reset_reset_n,          //           reset.reset_n
		output wire [10:0] sram_addr_export,       //       sram_addr.export
		output wire        sram_cs_export,         //         sram_cs.export
		inout  wire [15:0] sram_data_in_export,    //    sram_data_in.export
		output wire        sram_oe_export,         //         sram_oe.export
		output wire        sram_read_write_export, // sram_read_write.export
		input  wire [9:0]  switches_export         //        switches.export
	);

	wire  [31:0] nios2_qsys_0_data_master_readdata;                           // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
	wire         nios2_qsys_0_data_master_waitrequest;                        // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
	wire         nios2_qsys_0_data_master_debugaccess;                        // nios2_qsys_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
	wire  [18:0] nios2_qsys_0_data_master_address;                            // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
	wire   [3:0] nios2_qsys_0_data_master_byteenable;                         // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
	wire         nios2_qsys_0_data_master_read;                               // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
	wire         nios2_qsys_0_data_master_write;                              // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
	wire  [31:0] nios2_qsys_0_data_master_writedata;                          // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
	wire  [31:0] nios2_qsys_0_instruction_master_readdata;                    // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
	wire         nios2_qsys_0_instruction_master_waitrequest;                 // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
	wire  [18:0] nios2_qsys_0_instruction_master_address;                     // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
	wire         nios2_qsys_0_instruction_master_read;                        // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect;  // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata;    // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address;     // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;        // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
	wire         mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;       // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata;   // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
	wire  [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata;     // nios2_qsys_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest;  // nios2_qsys_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess;  // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_debugaccess -> nios2_qsys_0:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address;      // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_address -> nios2_qsys_0:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read;         // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_read -> nios2_qsys_0:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable;   // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_byteenable -> nios2_qsys_0:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write;        // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_write -> nios2_qsys_0:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata;    // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_writedata -> nios2_qsys_0:debug_mem_slave_writedata
	wire         mm_interconnect_0_onchip_memory2_0_s1_chipselect;            // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
	wire  [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata;              // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
	wire  [14:0] mm_interconnect_0_onchip_memory2_0_s1_address;               // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
	wire   [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable;            // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
	wire         mm_interconnect_0_onchip_memory2_0_s1_write;                 // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
	wire  [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata;             // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
	wire         mm_interconnect_0_onchip_memory2_0_s1_clken;                 // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
	wire         mm_interconnect_0_leds_s1_chipselect;                        // mm_interconnect_0:LEDs_s1_chipselect -> LEDs:chipselect
	wire  [31:0] mm_interconnect_0_leds_s1_readdata;                          // LEDs:readdata -> mm_interconnect_0:LEDs_s1_readdata
	wire   [1:0] mm_interconnect_0_leds_s1_address;                           // mm_interconnect_0:LEDs_s1_address -> LEDs:address
	wire         mm_interconnect_0_leds_s1_write;                             // mm_interconnect_0:LEDs_s1_write -> LEDs:write_n
	wire  [31:0] mm_interconnect_0_leds_s1_writedata;                         // mm_interconnect_0:LEDs_s1_writedata -> LEDs:writedata
	wire  [31:0] mm_interconnect_0_switches_s1_readdata;                      // switches:readdata -> mm_interconnect_0:switches_s1_readdata
	wire   [1:0] mm_interconnect_0_switches_s1_address;                       // mm_interconnect_0:switches_s1_address -> switches:address
	wire         mm_interconnect_0_sram_data_s1_chipselect;                   // mm_interconnect_0:sram_data_s1_chipselect -> sram_data:chipselect
	wire  [31:0] mm_interconnect_0_sram_data_s1_readdata;                     // sram_data:readdata -> mm_interconnect_0:sram_data_s1_readdata
	wire   [1:0] mm_interconnect_0_sram_data_s1_address;                      // mm_interconnect_0:sram_data_s1_address -> sram_data:address
	wire         mm_interconnect_0_sram_data_s1_write;                        // mm_interconnect_0:sram_data_s1_write -> sram_data:write_n
	wire  [31:0] mm_interconnect_0_sram_data_s1_writedata;                    // mm_interconnect_0:sram_data_s1_writedata -> sram_data:writedata
	wire         mm_interconnect_0_sram_addr_s1_chipselect;                   // mm_interconnect_0:sram_addr_s1_chipselect -> sram_addr:chipselect
	wire  [31:0] mm_interconnect_0_sram_addr_s1_readdata;                     // sram_addr:readdata -> mm_interconnect_0:sram_addr_s1_readdata
	wire   [1:0] mm_interconnect_0_sram_addr_s1_address;                      // mm_interconnect_0:sram_addr_s1_address -> sram_addr:address
	wire         mm_interconnect_0_sram_addr_s1_write;                        // mm_interconnect_0:sram_addr_s1_write -> sram_addr:write_n
	wire  [31:0] mm_interconnect_0_sram_addr_s1_writedata;                    // mm_interconnect_0:sram_addr_s1_writedata -> sram_addr:writedata
	wire         mm_interconnect_0_sram_read_write_s1_chipselect;             // mm_interconnect_0:sram_read_write_s1_chipselect -> sram_read_write:chipselect
	wire  [31:0] mm_interconnect_0_sram_read_write_s1_readdata;               // sram_read_write:readdata -> mm_interconnect_0:sram_read_write_s1_readdata
	wire   [1:0] mm_interconnect_0_sram_read_write_s1_address;                // mm_interconnect_0:sram_read_write_s1_address -> sram_read_write:address
	wire         mm_interconnect_0_sram_read_write_s1_write;                  // mm_interconnect_0:sram_read_write_s1_write -> sram_read_write:write_n
	wire  [31:0] mm_interconnect_0_sram_read_write_s1_writedata;              // mm_interconnect_0:sram_read_write_s1_writedata -> sram_read_write:writedata
	wire         mm_interconnect_0_sram_cs_s1_chipselect;                     // mm_interconnect_0:sram_cs_s1_chipselect -> sram_cs:chipselect
	wire  [31:0] mm_interconnect_0_sram_cs_s1_readdata;                       // sram_cs:readdata -> mm_interconnect_0:sram_cs_s1_readdata
	wire   [1:0] mm_interconnect_0_sram_cs_s1_address;                        // mm_interconnect_0:sram_cs_s1_address -> sram_cs:address
	wire         mm_interconnect_0_sram_cs_s1_write;                          // mm_interconnect_0:sram_cs_s1_write -> sram_cs:write_n
	wire  [31:0] mm_interconnect_0_sram_cs_s1_writedata;                      // mm_interconnect_0:sram_cs_s1_writedata -> sram_cs:writedata
	wire         mm_interconnect_0_sram_oe_s1_chipselect;                     // mm_interconnect_0:sram_oe_s1_chipselect -> sram_oe:chipselect
	wire  [31:0] mm_interconnect_0_sram_oe_s1_readdata;                       // sram_oe:readdata -> mm_interconnect_0:sram_oe_s1_readdata
	wire   [1:0] mm_interconnect_0_sram_oe_s1_address;                        // mm_interconnect_0:sram_oe_s1_address -> sram_oe:address
	wire         mm_interconnect_0_sram_oe_s1_write;                          // mm_interconnect_0:sram_oe_s1_write -> sram_oe:write_n
	wire  [31:0] mm_interconnect_0_sram_oe_s1_writedata;                      // mm_interconnect_0:sram_oe_s1_writedata -> sram_oe:writedata
	wire         mm_interconnect_0_regfile_data_s1_chipselect;                // mm_interconnect_0:regfile_data_s1_chipselect -> regfile_data:chipselect
	wire  [31:0] mm_interconnect_0_regfile_data_s1_readdata;                  // regfile_data:readdata -> mm_interconnect_0:regfile_data_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_data_s1_address;                   // mm_interconnect_0:regfile_data_s1_address -> regfile_data:address
	wire         mm_interconnect_0_regfile_data_s1_write;                     // mm_interconnect_0:regfile_data_s1_write -> regfile_data:write_n
	wire  [31:0] mm_interconnect_0_regfile_data_s1_writedata;                 // mm_interconnect_0:regfile_data_s1_writedata -> regfile_data:writedata
	wire  [31:0] mm_interconnect_0_regfile_reg1_s1_readdata;                  // regfile_reg1:readdata -> mm_interconnect_0:regfile_reg1_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_reg1_s1_address;                   // mm_interconnect_0:regfile_reg1_s1_address -> regfile_reg1:address
	wire  [31:0] mm_interconnect_0_regfile_reg2_s1_readdata;                  // regfile_reg2:readdata -> mm_interconnect_0:regfile_reg2_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_reg2_s1_address;                   // mm_interconnect_0:regfile_reg2_s1_address -> regfile_reg2:address
	wire         mm_interconnect_0_regfile_r1sel_s1_chipselect;               // mm_interconnect_0:regfile_r1sel_s1_chipselect -> regfile_r1sel:chipselect
	wire  [31:0] mm_interconnect_0_regfile_r1sel_s1_readdata;                 // regfile_r1sel:readdata -> mm_interconnect_0:regfile_r1sel_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_r1sel_s1_address;                  // mm_interconnect_0:regfile_r1sel_s1_address -> regfile_r1sel:address
	wire         mm_interconnect_0_regfile_r1sel_s1_write;                    // mm_interconnect_0:regfile_r1sel_s1_write -> regfile_r1sel:write_n
	wire  [31:0] mm_interconnect_0_regfile_r1sel_s1_writedata;                // mm_interconnect_0:regfile_r1sel_s1_writedata -> regfile_r1sel:writedata
	wire         mm_interconnect_0_regfile_r2sel_s1_chipselect;               // mm_interconnect_0:regfile_r2sel_s1_chipselect -> regfile_r2sel:chipselect
	wire  [31:0] mm_interconnect_0_regfile_r2sel_s1_readdata;                 // regfile_r2sel:readdata -> mm_interconnect_0:regfile_r2sel_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_r2sel_s1_address;                  // mm_interconnect_0:regfile_r2sel_s1_address -> regfile_r2sel:address
	wire         mm_interconnect_0_regfile_r2sel_s1_write;                    // mm_interconnect_0:regfile_r2sel_s1_write -> regfile_r2sel:write_n
	wire  [31:0] mm_interconnect_0_regfile_r2sel_s1_writedata;                // mm_interconnect_0:regfile_r2sel_s1_writedata -> regfile_r2sel:writedata
	wire         mm_interconnect_0_regfile_wsel_s1_chipselect;                // mm_interconnect_0:regfile_wsel_s1_chipselect -> regfile_wsel:chipselect
	wire  [31:0] mm_interconnect_0_regfile_wsel_s1_readdata;                  // regfile_wsel:readdata -> mm_interconnect_0:regfile_wsel_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_wsel_s1_address;                   // mm_interconnect_0:regfile_wsel_s1_address -> regfile_wsel:address
	wire         mm_interconnect_0_regfile_wsel_s1_write;                     // mm_interconnect_0:regfile_wsel_s1_write -> regfile_wsel:write_n
	wire  [31:0] mm_interconnect_0_regfile_wsel_s1_writedata;                 // mm_interconnect_0:regfile_wsel_s1_writedata -> regfile_wsel:writedata
	wire         mm_interconnect_0_regfile_we_s1_chipselect;                  // mm_interconnect_0:regfile_we_s1_chipselect -> regfile_we:chipselect
	wire  [31:0] mm_interconnect_0_regfile_we_s1_readdata;                    // regfile_we:readdata -> mm_interconnect_0:regfile_we_s1_readdata
	wire   [1:0] mm_interconnect_0_regfile_we_s1_address;                     // mm_interconnect_0:regfile_we_s1_address -> regfile_we:address
	wire         mm_interconnect_0_regfile_we_s1_write;                       // mm_interconnect_0:regfile_we_s1_write -> regfile_we:write_n
	wire  [31:0] mm_interconnect_0_regfile_we_s1_writedata;                   // mm_interconnect_0:regfile_we_s1_writedata -> regfile_we:writedata
	wire         mm_interconnect_0_hex_0_s1_chipselect;                       // mm_interconnect_0:hex_0_s1_chipselect -> hex_0:chipselect
	wire  [31:0] mm_interconnect_0_hex_0_s1_readdata;                         // hex_0:readdata -> mm_interconnect_0:hex_0_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_0_s1_address;                          // mm_interconnect_0:hex_0_s1_address -> hex_0:address
	wire         mm_interconnect_0_hex_0_s1_write;                            // mm_interconnect_0:hex_0_s1_write -> hex_0:write_n
	wire  [31:0] mm_interconnect_0_hex_0_s1_writedata;                        // mm_interconnect_0:hex_0_s1_writedata -> hex_0:writedata
	wire         mm_interconnect_0_hex_1_s1_chipselect;                       // mm_interconnect_0:hex_1_s1_chipselect -> hex_1:chipselect
	wire  [31:0] mm_interconnect_0_hex_1_s1_readdata;                         // hex_1:readdata -> mm_interconnect_0:hex_1_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_1_s1_address;                          // mm_interconnect_0:hex_1_s1_address -> hex_1:address
	wire         mm_interconnect_0_hex_1_s1_write;                            // mm_interconnect_0:hex_1_s1_write -> hex_1:write_n
	wire  [31:0] mm_interconnect_0_hex_1_s1_writedata;                        // mm_interconnect_0:hex_1_s1_writedata -> hex_1:writedata
	wire         mm_interconnect_0_hex_2_s1_chipselect;                       // mm_interconnect_0:hex_2_s1_chipselect -> hex_2:chipselect
	wire  [31:0] mm_interconnect_0_hex_2_s1_readdata;                         // hex_2:readdata -> mm_interconnect_0:hex_2_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_2_s1_address;                          // mm_interconnect_0:hex_2_s1_address -> hex_2:address
	wire         mm_interconnect_0_hex_2_s1_write;                            // mm_interconnect_0:hex_2_s1_write -> hex_2:write_n
	wire  [31:0] mm_interconnect_0_hex_2_s1_writedata;                        // mm_interconnect_0:hex_2_s1_writedata -> hex_2:writedata
	wire         mm_interconnect_0_hex_3_s1_chipselect;                       // mm_interconnect_0:hex_3_s1_chipselect -> hex_3:chipselect
	wire  [31:0] mm_interconnect_0_hex_3_s1_readdata;                         // hex_3:readdata -> mm_interconnect_0:hex_3_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_3_s1_address;                          // mm_interconnect_0:hex_3_s1_address -> hex_3:address
	wire         mm_interconnect_0_hex_3_s1_write;                            // mm_interconnect_0:hex_3_s1_write -> hex_3:write_n
	wire  [31:0] mm_interconnect_0_hex_3_s1_writedata;                        // mm_interconnect_0:hex_3_s1_writedata -> hex_3:writedata
	wire         mm_interconnect_0_hex_4_s1_chipselect;                       // mm_interconnect_0:hex_4_s1_chipselect -> hex_4:chipselect
	wire  [31:0] mm_interconnect_0_hex_4_s1_readdata;                         // hex_4:readdata -> mm_interconnect_0:hex_4_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_4_s1_address;                          // mm_interconnect_0:hex_4_s1_address -> hex_4:address
	wire         mm_interconnect_0_hex_4_s1_write;                            // mm_interconnect_0:hex_4_s1_write -> hex_4:write_n
	wire  [31:0] mm_interconnect_0_hex_4_s1_writedata;                        // mm_interconnect_0:hex_4_s1_writedata -> hex_4:writedata
	wire         mm_interconnect_0_hex_5_s1_chipselect;                       // mm_interconnect_0:hex_5_s1_chipselect -> hex_5:chipselect
	wire  [31:0] mm_interconnect_0_hex_5_s1_readdata;                         // hex_5:readdata -> mm_interconnect_0:hex_5_s1_readdata
	wire   [1:0] mm_interconnect_0_hex_5_s1_address;                          // mm_interconnect_0:hex_5_s1_address -> hex_5:address
	wire         mm_interconnect_0_hex_5_s1_write;                            // mm_interconnect_0:hex_5_s1_write -> hex_5:write_n
	wire  [31:0] mm_interconnect_0_hex_5_s1_writedata;                        // mm_interconnect_0:hex_5_s1_writedata -> hex_5:writedata
	wire         mm_interconnect_0_alu_a_s1_chipselect;                       // mm_interconnect_0:alu_a_s1_chipselect -> alu_a:chipselect
	wire  [31:0] mm_interconnect_0_alu_a_s1_readdata;                         // alu_a:readdata -> mm_interconnect_0:alu_a_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_a_s1_address;                          // mm_interconnect_0:alu_a_s1_address -> alu_a:address
	wire         mm_interconnect_0_alu_a_s1_write;                            // mm_interconnect_0:alu_a_s1_write -> alu_a:write_n
	wire  [31:0] mm_interconnect_0_alu_a_s1_writedata;                        // mm_interconnect_0:alu_a_s1_writedata -> alu_a:writedata
	wire         mm_interconnect_0_alu_b_s1_chipselect;                       // mm_interconnect_0:alu_b_s1_chipselect -> alu_b:chipselect
	wire  [31:0] mm_interconnect_0_alu_b_s1_readdata;                         // alu_b:readdata -> mm_interconnect_0:alu_b_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_b_s1_address;                          // mm_interconnect_0:alu_b_s1_address -> alu_b:address
	wire         mm_interconnect_0_alu_b_s1_write;                            // mm_interconnect_0:alu_b_s1_write -> alu_b:write_n
	wire  [31:0] mm_interconnect_0_alu_b_s1_writedata;                        // mm_interconnect_0:alu_b_s1_writedata -> alu_b:writedata
	wire         mm_interconnect_0_alu_control_s1_chipselect;                 // mm_interconnect_0:alu_control_s1_chipselect -> alu_control:chipselect
	wire  [31:0] mm_interconnect_0_alu_control_s1_readdata;                   // alu_control:readdata -> mm_interconnect_0:alu_control_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_control_s1_address;                    // mm_interconnect_0:alu_control_s1_address -> alu_control:address
	wire         mm_interconnect_0_alu_control_s1_write;                      // mm_interconnect_0:alu_control_s1_write -> alu_control:write_n
	wire  [31:0] mm_interconnect_0_alu_control_s1_writedata;                  // mm_interconnect_0:alu_control_s1_writedata -> alu_control:writedata
	wire  [31:0] mm_interconnect_0_alu_out_s1_readdata;                       // alu_out:readdata -> mm_interconnect_0:alu_out_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_out_s1_address;                        // mm_interconnect_0:alu_out_s1_address -> alu_out:address
	wire  [31:0] mm_interconnect_0_alu_zero_s1_readdata;                      // alu_zero:readdata -> mm_interconnect_0:alu_zero_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_zero_s1_address;                       // mm_interconnect_0:alu_zero_s1_address -> alu_zero:address
	wire  [31:0] mm_interconnect_0_alu_overflow_s1_readdata;                  // alu_overflow:readdata -> mm_interconnect_0:alu_overflow_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_overflow_s1_address;                   // mm_interconnect_0:alu_overflow_s1_address -> alu_overflow:address
	wire  [31:0] mm_interconnect_0_alu_carry_out_s1_readdata;                 // alu_carry_out:readdata -> mm_interconnect_0:alu_carry_out_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_carry_out_s1_address;                  // mm_interconnect_0:alu_carry_out_s1_address -> alu_carry_out:address
	wire  [31:0] mm_interconnect_0_alu_negative_s1_readdata;                  // alu_negative:readdata -> mm_interconnect_0:alu_negative_s1_readdata
	wire   [1:0] mm_interconnect_0_alu_negative_s1_address;                   // mm_interconnect_0:alu_negative_s1_address -> alu_negative:address
	wire  [31:0] mm_interconnect_0_keys_s1_readdata;                          // keys:readdata -> mm_interconnect_0:keys_s1_readdata
	wire   [1:0] mm_interconnect_0_keys_s1_address;                           // mm_interconnect_0:keys_s1_address -> keys:address
	wire         irq_mapper_receiver0_irq;                                    // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
	wire  [31:0] nios2_qsys_0_irq_irq;                                        // irq_mapper:sender_irq -> nios2_qsys_0:irq
	wire         rst_controller_reset_out_reset;                              // rst_controller:reset_out -> [LEDs:reset_n, alu_a:reset_n, alu_b:reset_n, alu_carry_out:reset_n, alu_control:reset_n, alu_negative:reset_n, alu_out:reset_n, alu_overflow:reset_n, alu_zero:reset_n, hex_0:reset_n, hex_1:reset_n, hex_2:reset_n, hex_3:reset_n, hex_4:reset_n, hex_5:reset_n, irq_mapper:reset, jtag_uart_0:rst_n, keys:reset_n, mm_interconnect_0:nios2_qsys_0_reset_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory2_0:reset, regfile_data:reset_n, regfile_r1sel:reset_n, regfile_r2sel:reset_n, regfile_reg1:reset_n, regfile_reg2:reset_n, regfile_we:reset_n, regfile_wsel:reset_n, rst_translator:in_reset, sram_addr:reset_n, sram_cs:reset_n, sram_data:reset_n, sram_oe:reset_n, sram_read_write:reset_n, switches:reset_n]
	wire         rst_controller_reset_out_reset_req;                          // rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
	wire         nios2_qsys_0_debug_reset_request_reset;                      // nios2_qsys_0:debug_reset_request -> rst_controller:reset_in1

	nios_system_LEDs leds (
		.clk        (clk_clk),                              //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),      //               reset.reset_n
		.address    (mm_interconnect_0_leds_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_leds_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_leds_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_leds_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_leds_s1_readdata),   //                    .readdata
		.out_port   (leds_export)                           // external_connection.export
	);

	nios_system_alu_a alu_a (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_alu_a_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_alu_a_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_alu_a_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_alu_a_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_alu_a_s1_readdata),   //                    .readdata
		.out_port   (alu_a_export)                           // external_connection.export
	);

	nios_system_alu_a alu_b (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_alu_b_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_alu_b_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_alu_b_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_alu_b_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_alu_b_s1_readdata),   //                    .readdata
		.out_port   (alu_b_export)                           // external_connection.export
	);

	nios_system_alu_carry_out alu_carry_out (
		.clk      (clk_clk),                                     //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),             //               reset.reset_n
		.address  (mm_interconnect_0_alu_carry_out_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_alu_carry_out_s1_readdata), //                    .readdata
		.in_port  (alu_carry_out_export)                         // external_connection.export
	);

	nios_system_alu_control alu_control (
		.clk        (clk_clk),                                     //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),             //               reset.reset_n
		.address    (mm_interconnect_0_alu_control_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_alu_control_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_alu_control_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_alu_control_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_alu_control_s1_readdata),   //                    .readdata
		.out_port   (alu_control_export)                           // external_connection.export
	);

	nios_system_alu_carry_out alu_negative (
		.clk      (clk_clk),                                    //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address  (mm_interconnect_0_alu_negative_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_alu_negative_s1_readdata), //                    .readdata
		.in_port  (alu_negative_export)                         // external_connection.export
	);

	nios_system_alu_out alu_out (
		.clk      (clk_clk),                               //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address  (mm_interconnect_0_alu_out_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_alu_out_s1_readdata), //                    .readdata
		.in_port  (alu_out_export)                         // external_connection.export
	);

	nios_system_alu_carry_out alu_overflow (
		.clk      (clk_clk),                                    //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address  (mm_interconnect_0_alu_overflow_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_alu_overflow_s1_readdata), //                    .readdata
		.in_port  (alu_overflow_export)                         // external_connection.export
	);

	nios_system_alu_carry_out alu_zero (
		.clk      (clk_clk),                                //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),        //               reset.reset_n
		.address  (mm_interconnect_0_alu_zero_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_alu_zero_s1_readdata), //                    .readdata
		.in_port  (alu_zero_export)                         // external_connection.export
	);

	nios_system_hex_0 hex_0 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_0_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_0_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_0_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_0_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_0_s1_readdata),   //                    .readdata
		.out_port   (hex_0_export)                           // external_connection.export
	);

	nios_system_hex_0 hex_1 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_1_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_1_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_1_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_1_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_1_s1_readdata),   //                    .readdata
		.out_port   (hex_1_export)                           // external_connection.export
	);

	nios_system_hex_0 hex_2 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_2_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_2_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_2_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_2_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_2_s1_readdata),   //                    .readdata
		.out_port   (hex_2_export)                           // external_connection.export
	);

	nios_system_hex_0 hex_3 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_3_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_3_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_3_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_3_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_3_s1_readdata),   //                    .readdata
		.out_port   (hex_3_export)                           // external_connection.export
	);

	nios_system_hex_0 hex_4 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_4_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_4_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_4_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_4_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_4_s1_readdata),   //                    .readdata
		.out_port   (hex_4_export)                           // external_connection.export
	);

	nios_system_hex_0 hex_5 (
		.clk        (clk_clk),                               //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //               reset.reset_n
		.address    (mm_interconnect_0_hex_5_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_hex_5_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_hex_5_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_hex_5_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_hex_5_s1_readdata),   //                    .readdata
		.out_port   (hex_5_export)                           // external_connection.export
	);

	nios_system_jtag_uart_0 jtag_uart_0 (
		.clk            (clk_clk),                                                     //               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                             //             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect),  // avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address),     //                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read),       //                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata),    //                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write),      //                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata),   //                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), //                  .waitrequest
		.av_irq         (irq_mapper_receiver0_irq)                                     //               irq.irq
	);

	nios_system_keys keys (
		.clk      (clk_clk),                            //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),    //               reset.reset_n
		.address  (mm_interconnect_0_keys_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_keys_s1_readdata), //                    .readdata
		.in_port  (keys_export)                         // external_connection.export
	);

	nios_system_nios2_qsys_0 nios2_qsys_0 (
		.clk                                 (clk_clk),                                                    //                       clk.clk
		.reset_n                             (~rst_controller_reset_out_reset),                            //                     reset.reset_n
		.reset_req                           (rst_controller_reset_out_reset_req),                         //                          .reset_req
		.d_address                           (nios2_qsys_0_data_master_address),                           //               data_master.address
		.d_byteenable                        (nios2_qsys_0_data_master_byteenable),                        //                          .byteenable
		.d_read                              (nios2_qsys_0_data_master_read),                              //                          .read
		.d_readdata                          (nios2_qsys_0_data_master_readdata),                          //                          .readdata
		.d_waitrequest                       (nios2_qsys_0_data_master_waitrequest),                       //                          .waitrequest
		.d_write                             (nios2_qsys_0_data_master_write),                             //                          .write
		.d_writedata                         (nios2_qsys_0_data_master_writedata),                         //                          .writedata
		.debug_mem_slave_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess),                       //                          .debugaccess
		.i_address                           (nios2_qsys_0_instruction_master_address),                    //        instruction_master.address
		.i_read                              (nios2_qsys_0_instruction_master_read),                       //                          .read
		.i_readdata                          (nios2_qsys_0_instruction_master_readdata),                   //                          .readdata
		.i_waitrequest                       (nios2_qsys_0_instruction_master_waitrequest),                //                          .waitrequest
		.irq                                 (nios2_qsys_0_irq_irq),                                       //                       irq.irq
		.debug_reset_request                 (nios2_qsys_0_debug_reset_request_reset),                     //       debug_reset_request.reset
		.debug_mem_slave_address             (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address),     //           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable),  //                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), //                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read),        //                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata),    //                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), //                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write),       //                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata),   //                          .writedata
		.dummy_ci_port                       ()                                                            // custom_instruction_master.readra
	);

	nios_system_onchip_memory2_0 onchip_memory2_0 (
		.clk        (clk_clk),                                          //   clk1.clk
		.address    (mm_interconnect_0_onchip_memory2_0_s1_address),    //     s1.address
		.clken      (mm_interconnect_0_onchip_memory2_0_s1_clken),      //       .clken
		.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), //       .chipselect
		.write      (mm_interconnect_0_onchip_memory2_0_s1_write),      //       .write
		.readdata   (mm_interconnect_0_onchip_memory2_0_s1_readdata),   //       .readdata
		.writedata  (mm_interconnect_0_onchip_memory2_0_s1_writedata),  //       .writedata
		.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset),                   // reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)                //       .reset_req
	);

	nios_system_alu_a regfile_data (
		.clk        (clk_clk),                                      //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),              //               reset.reset_n
		.address    (mm_interconnect_0_regfile_data_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_regfile_data_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_regfile_data_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_regfile_data_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_regfile_data_s1_readdata),   //                    .readdata
		.out_port   (regfile_data_export)                           // external_connection.export
	);

	nios_system_regfile_r1sel regfile_r1sel (
		.clk        (clk_clk),                                       //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),               //               reset.reset_n
		.address    (mm_interconnect_0_regfile_r1sel_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_regfile_r1sel_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_regfile_r1sel_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_regfile_r1sel_s1_readdata),   //                    .readdata
		.out_port   (regfile_r1sel_export)                           // external_connection.export
	);

	nios_system_regfile_r1sel regfile_r2sel (
		.clk        (clk_clk),                                       //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),               //               reset.reset_n
		.address    (mm_interconnect_0_regfile_r2sel_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_regfile_r2sel_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_regfile_r2sel_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_regfile_r2sel_s1_readdata),   //                    .readdata
		.out_port   (regfile_r2sel_export)                           // external_connection.export
	);

	nios_system_alu_out regfile_reg1 (
		.clk      (clk_clk),                                    //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address  (mm_interconnect_0_regfile_reg1_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_regfile_reg1_s1_readdata), //                    .readdata
		.in_port  (regfile_reg1_export)                         // external_connection.export
	);

	nios_system_alu_out regfile_reg2 (
		.clk      (clk_clk),                                    //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address  (mm_interconnect_0_regfile_reg2_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_regfile_reg2_s1_readdata), //                    .readdata
		.in_port  (regfile_reg2_export)                         // external_connection.export
	);

	nios_system_regfile_we regfile_we (
		.clk        (clk_clk),                                    //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),            //               reset.reset_n
		.address    (mm_interconnect_0_regfile_we_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_regfile_we_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_regfile_we_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_regfile_we_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_regfile_we_s1_readdata),   //                    .readdata
		.out_port   (regfile_we_export)                           // external_connection.export
	);

	nios_system_regfile_r1sel regfile_wsel (
		.clk        (clk_clk),                                      //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),              //               reset.reset_n
		.address    (mm_interconnect_0_regfile_wsel_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_regfile_wsel_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_regfile_wsel_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_regfile_wsel_s1_readdata),   //                    .readdata
		.out_port   (regfile_wsel_export)                           // external_connection.export
	);

	nios_system_sram_addr sram_addr (
		.clk        (clk_clk),                                   //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),           //               reset.reset_n
		.address    (mm_interconnect_0_sram_addr_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_sram_addr_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_sram_addr_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_sram_addr_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_sram_addr_s1_readdata),   //                    .readdata
		.out_port   (sram_addr_export)                           // external_connection.export
	);

	nios_system_regfile_we sram_cs (
		.clk        (clk_clk),                                 //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_sram_cs_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_sram_cs_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_sram_cs_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_sram_cs_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_sram_cs_s1_readdata),   //                    .readdata
		.out_port   (sram_cs_export)                           // external_connection.export
	);

	nios_system_sram_data sram_data (
		.clk        (clk_clk),                                   //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),           //               reset.reset_n
		.address    (mm_interconnect_0_sram_data_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_sram_data_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_sram_data_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_sram_data_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_sram_data_s1_readdata),   //                    .readdata
		.bidir_port (sram_data_in_export)                        // external_connection.export
	);

	nios_system_regfile_we sram_oe (
		.clk        (clk_clk),                                 //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //               reset.reset_n
		.address    (mm_interconnect_0_sram_oe_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_sram_oe_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_sram_oe_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_sram_oe_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_sram_oe_s1_readdata),   //                    .readdata
		.out_port   (sram_oe_export)                           // external_connection.export
	);

	nios_system_regfile_we sram_read_write (
		.clk        (clk_clk),                                         //                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),                 //               reset.reset_n
		.address    (mm_interconnect_0_sram_read_write_s1_address),    //                  s1.address
		.write_n    (~mm_interconnect_0_sram_read_write_s1_write),     //                    .write_n
		.writedata  (mm_interconnect_0_sram_read_write_s1_writedata),  //                    .writedata
		.chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), //                    .chipselect
		.readdata   (mm_interconnect_0_sram_read_write_s1_readdata),   //                    .readdata
		.out_port   (sram_read_write_export)                           // external_connection.export
	);

	nios_system_switches switches (
		.clk      (clk_clk),                                //                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),        //               reset.reset_n
		.address  (mm_interconnect_0_switches_s1_address),  //                  s1.address
		.readdata (mm_interconnect_0_switches_s1_readdata), //                    .readdata
		.in_port  (switches_export)                         // external_connection.export
	);

	nios_system_mm_interconnect_0 mm_interconnect_0 (
		.clk_0_clk_clk                                  (clk_clk),                                                     //                                clk_0_clk.clk
		.nios2_qsys_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                              // nios2_qsys_0_reset_reset_bridge_in_reset.reset
		.nios2_qsys_0_data_master_address               (nios2_qsys_0_data_master_address),                            //                 nios2_qsys_0_data_master.address
		.nios2_qsys_0_data_master_waitrequest           (nios2_qsys_0_data_master_waitrequest),                        //                                         .waitrequest
		.nios2_qsys_0_data_master_byteenable            (nios2_qsys_0_data_master_byteenable),                         //                                         .byteenable
		.nios2_qsys_0_data_master_read                  (nios2_qsys_0_data_master_read),                               //                                         .read
		.nios2_qsys_0_data_master_readdata              (nios2_qsys_0_data_master_readdata),                           //                                         .readdata
		.nios2_qsys_0_data_master_write                 (nios2_qsys_0_data_master_write),                              //                                         .write
		.nios2_qsys_0_data_master_writedata             (nios2_qsys_0_data_master_writedata),                          //                                         .writedata
		.nios2_qsys_0_data_master_debugaccess           (nios2_qsys_0_data_master_debugaccess),                        //                                         .debugaccess
		.nios2_qsys_0_instruction_master_address        (nios2_qsys_0_instruction_master_address),                     //          nios2_qsys_0_instruction_master.address
		.nios2_qsys_0_instruction_master_waitrequest    (nios2_qsys_0_instruction_master_waitrequest),                 //                                         .waitrequest
		.nios2_qsys_0_instruction_master_read           (nios2_qsys_0_instruction_master_read),                        //                                         .read
		.nios2_qsys_0_instruction_master_readdata       (nios2_qsys_0_instruction_master_readdata),                    //                                         .readdata
		.alu_a_s1_address                               (mm_interconnect_0_alu_a_s1_address),                          //                                 alu_a_s1.address
		.alu_a_s1_write                                 (mm_interconnect_0_alu_a_s1_write),                            //                                         .write
		.alu_a_s1_readdata                              (mm_interconnect_0_alu_a_s1_readdata),                         //                                         .readdata
		.alu_a_s1_writedata                             (mm_interconnect_0_alu_a_s1_writedata),                        //                                         .writedata
		.alu_a_s1_chipselect                            (mm_interconnect_0_alu_a_s1_chipselect),                       //                                         .chipselect
		.alu_b_s1_address                               (mm_interconnect_0_alu_b_s1_address),                          //                                 alu_b_s1.address
		.alu_b_s1_write                                 (mm_interconnect_0_alu_b_s1_write),                            //                                         .write
		.alu_b_s1_readdata                              (mm_interconnect_0_alu_b_s1_readdata),                         //                                         .readdata
		.alu_b_s1_writedata                             (mm_interconnect_0_alu_b_s1_writedata),                        //                                         .writedata
		.alu_b_s1_chipselect                            (mm_interconnect_0_alu_b_s1_chipselect),                       //                                         .chipselect
		.alu_carry_out_s1_address                       (mm_interconnect_0_alu_carry_out_s1_address),                  //                         alu_carry_out_s1.address
		.alu_carry_out_s1_readdata                      (mm_interconnect_0_alu_carry_out_s1_readdata),                 //                                         .readdata
		.alu_control_s1_address                         (mm_interconnect_0_alu_control_s1_address),                    //                           alu_control_s1.address
		.alu_control_s1_write                           (mm_interconnect_0_alu_control_s1_write),                      //                                         .write
		.alu_control_s1_readdata                        (mm_interconnect_0_alu_control_s1_readdata),                   //                                         .readdata
		.alu_control_s1_writedata                       (mm_interconnect_0_alu_control_s1_writedata),                  //                                         .writedata
		.alu_control_s1_chipselect                      (mm_interconnect_0_alu_control_s1_chipselect),                 //                                         .chipselect
		.alu_negative_s1_address                        (mm_interconnect_0_alu_negative_s1_address),                   //                          alu_negative_s1.address
		.alu_negative_s1_readdata                       (mm_interconnect_0_alu_negative_s1_readdata),                  //                                         .readdata
		.alu_out_s1_address                             (mm_interconnect_0_alu_out_s1_address),                        //                               alu_out_s1.address
		.alu_out_s1_readdata                            (mm_interconnect_0_alu_out_s1_readdata),                       //                                         .readdata
		.alu_overflow_s1_address                        (mm_interconnect_0_alu_overflow_s1_address),                   //                          alu_overflow_s1.address
		.alu_overflow_s1_readdata                       (mm_interconnect_0_alu_overflow_s1_readdata),                  //                                         .readdata
		.alu_zero_s1_address                            (mm_interconnect_0_alu_zero_s1_address),                       //                              alu_zero_s1.address
		.alu_zero_s1_readdata                           (mm_interconnect_0_alu_zero_s1_readdata),                      //                                         .readdata
		.hex_0_s1_address                               (mm_interconnect_0_hex_0_s1_address),                          //                                 hex_0_s1.address
		.hex_0_s1_write                                 (mm_interconnect_0_hex_0_s1_write),                            //                                         .write
		.hex_0_s1_readdata                              (mm_interconnect_0_hex_0_s1_readdata),                         //                                         .readdata
		.hex_0_s1_writedata                             (mm_interconnect_0_hex_0_s1_writedata),                        //                                         .writedata
		.hex_0_s1_chipselect                            (mm_interconnect_0_hex_0_s1_chipselect),                       //                                         .chipselect
		.hex_1_s1_address                               (mm_interconnect_0_hex_1_s1_address),                          //                                 hex_1_s1.address
		.hex_1_s1_write                                 (mm_interconnect_0_hex_1_s1_write),                            //                                         .write
		.hex_1_s1_readdata                              (mm_interconnect_0_hex_1_s1_readdata),                         //                                         .readdata
		.hex_1_s1_writedata                             (mm_interconnect_0_hex_1_s1_writedata),                        //                                         .writedata
		.hex_1_s1_chipselect                            (mm_interconnect_0_hex_1_s1_chipselect),                       //                                         .chipselect
		.hex_2_s1_address                               (mm_interconnect_0_hex_2_s1_address),                          //                                 hex_2_s1.address
		.hex_2_s1_write                                 (mm_interconnect_0_hex_2_s1_write),                            //                                         .write
		.hex_2_s1_readdata                              (mm_interconnect_0_hex_2_s1_readdata),                         //                                         .readdata
		.hex_2_s1_writedata                             (mm_interconnect_0_hex_2_s1_writedata),                        //                                         .writedata
		.hex_2_s1_chipselect                            (mm_interconnect_0_hex_2_s1_chipselect),                       //                                         .chipselect
		.hex_3_s1_address                               (mm_interconnect_0_hex_3_s1_address),                          //                                 hex_3_s1.address
		.hex_3_s1_write                                 (mm_interconnect_0_hex_3_s1_write),                            //                                         .write
		.hex_3_s1_readdata                              (mm_interconnect_0_hex_3_s1_readdata),                         //                                         .readdata
		.hex_3_s1_writedata                             (mm_interconnect_0_hex_3_s1_writedata),                        //                                         .writedata
		.hex_3_s1_chipselect                            (mm_interconnect_0_hex_3_s1_chipselect),                       //                                         .chipselect
		.hex_4_s1_address                               (mm_interconnect_0_hex_4_s1_address),                          //                                 hex_4_s1.address
		.hex_4_s1_write                                 (mm_interconnect_0_hex_4_s1_write),                            //                                         .write
		.hex_4_s1_readdata                              (mm_interconnect_0_hex_4_s1_readdata),                         //                                         .readdata
		.hex_4_s1_writedata                             (mm_interconnect_0_hex_4_s1_writedata),                        //                                         .writedata
		.hex_4_s1_chipselect                            (mm_interconnect_0_hex_4_s1_chipselect),                       //                                         .chipselect
		.hex_5_s1_address                               (mm_interconnect_0_hex_5_s1_address),                          //                                 hex_5_s1.address
		.hex_5_s1_write                                 (mm_interconnect_0_hex_5_s1_write),                            //                                         .write
		.hex_5_s1_readdata                              (mm_interconnect_0_hex_5_s1_readdata),                         //                                         .readdata
		.hex_5_s1_writedata                             (mm_interconnect_0_hex_5_s1_writedata),                        //                                         .writedata
		.hex_5_s1_chipselect                            (mm_interconnect_0_hex_5_s1_chipselect),                       //                                         .chipselect
		.jtag_uart_0_avalon_jtag_slave_address          (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address),     //            jtag_uart_0_avalon_jtag_slave.address
		.jtag_uart_0_avalon_jtag_slave_write            (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write),       //                                         .write
		.jtag_uart_0_avalon_jtag_slave_read             (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read),        //                                         .read
		.jtag_uart_0_avalon_jtag_slave_readdata         (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata),    //                                         .readdata
		.jtag_uart_0_avalon_jtag_slave_writedata        (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata),   //                                         .writedata
		.jtag_uart_0_avalon_jtag_slave_waitrequest      (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), //                                         .waitrequest
		.jtag_uart_0_avalon_jtag_slave_chipselect       (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect),  //                                         .chipselect
		.keys_s1_address                                (mm_interconnect_0_keys_s1_address),                           //                                  keys_s1.address
		.keys_s1_readdata                               (mm_interconnect_0_keys_s1_readdata),                          //                                         .readdata
		.LEDs_s1_address                                (mm_interconnect_0_leds_s1_address),                           //                                  LEDs_s1.address
		.LEDs_s1_write                                  (mm_interconnect_0_leds_s1_write),                             //                                         .write
		.LEDs_s1_readdata                               (mm_interconnect_0_leds_s1_readdata),                          //                                         .readdata
		.LEDs_s1_writedata                              (mm_interconnect_0_leds_s1_writedata),                         //                                         .writedata
		.LEDs_s1_chipselect                             (mm_interconnect_0_leds_s1_chipselect),                        //                                         .chipselect
		.nios2_qsys_0_debug_mem_slave_address           (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address),      //             nios2_qsys_0_debug_mem_slave.address
		.nios2_qsys_0_debug_mem_slave_write             (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write),        //                                         .write
		.nios2_qsys_0_debug_mem_slave_read              (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read),         //                                         .read
		.nios2_qsys_0_debug_mem_slave_readdata          (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata),     //                                         .readdata
		.nios2_qsys_0_debug_mem_slave_writedata         (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata),    //                                         .writedata
		.nios2_qsys_0_debug_mem_slave_byteenable        (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable),   //                                         .byteenable
		.nios2_qsys_0_debug_mem_slave_waitrequest       (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest),  //                                         .waitrequest
		.nios2_qsys_0_debug_mem_slave_debugaccess       (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess),  //                                         .debugaccess
		.onchip_memory2_0_s1_address                    (mm_interconnect_0_onchip_memory2_0_s1_address),               //                      onchip_memory2_0_s1.address
		.onchip_memory2_0_s1_write                      (mm_interconnect_0_onchip_memory2_0_s1_write),                 //                                         .write
		.onchip_memory2_0_s1_readdata                   (mm_interconnect_0_onchip_memory2_0_s1_readdata),              //                                         .readdata
		.onchip_memory2_0_s1_writedata                  (mm_interconnect_0_onchip_memory2_0_s1_writedata),             //                                         .writedata
		.onchip_memory2_0_s1_byteenable                 (mm_interconnect_0_onchip_memory2_0_s1_byteenable),            //                                         .byteenable
		.onchip_memory2_0_s1_chipselect                 (mm_interconnect_0_onchip_memory2_0_s1_chipselect),            //                                         .chipselect
		.onchip_memory2_0_s1_clken                      (mm_interconnect_0_onchip_memory2_0_s1_clken),                 //                                         .clken
		.regfile_data_s1_address                        (mm_interconnect_0_regfile_data_s1_address),                   //                          regfile_data_s1.address
		.regfile_data_s1_write                          (mm_interconnect_0_regfile_data_s1_write),                     //                                         .write
		.regfile_data_s1_readdata                       (mm_interconnect_0_regfile_data_s1_readdata),                  //                                         .readdata
		.regfile_data_s1_writedata                      (mm_interconnect_0_regfile_data_s1_writedata),                 //                                         .writedata
		.regfile_data_s1_chipselect                     (mm_interconnect_0_regfile_data_s1_chipselect),                //                                         .chipselect
		.regfile_r1sel_s1_address                       (mm_interconnect_0_regfile_r1sel_s1_address),                  //                         regfile_r1sel_s1.address
		.regfile_r1sel_s1_write                         (mm_interconnect_0_regfile_r1sel_s1_write),                    //                                         .write
		.regfile_r1sel_s1_readdata                      (mm_interconnect_0_regfile_r1sel_s1_readdata),                 //                                         .readdata
		.regfile_r1sel_s1_writedata                     (mm_interconnect_0_regfile_r1sel_s1_writedata),                //                                         .writedata
		.regfile_r1sel_s1_chipselect                    (mm_interconnect_0_regfile_r1sel_s1_chipselect),               //                                         .chipselect
		.regfile_r2sel_s1_address                       (mm_interconnect_0_regfile_r2sel_s1_address),                  //                         regfile_r2sel_s1.address
		.regfile_r2sel_s1_write                         (mm_interconnect_0_regfile_r2sel_s1_write),                    //                                         .write
		.regfile_r2sel_s1_readdata                      (mm_interconnect_0_regfile_r2sel_s1_readdata),                 //                                         .readdata
		.regfile_r2sel_s1_writedata                     (mm_interconnect_0_regfile_r2sel_s1_writedata),                //                                         .writedata
		.regfile_r2sel_s1_chipselect                    (mm_interconnect_0_regfile_r2sel_s1_chipselect),               //                                         .chipselect
		.regfile_reg1_s1_address                        (mm_interconnect_0_regfile_reg1_s1_address),                   //                          regfile_reg1_s1.address
		.regfile_reg1_s1_readdata                       (mm_interconnect_0_regfile_reg1_s1_readdata),                  //                                         .readdata
		.regfile_reg2_s1_address                        (mm_interconnect_0_regfile_reg2_s1_address),                   //                          regfile_reg2_s1.address
		.regfile_reg2_s1_readdata                       (mm_interconnect_0_regfile_reg2_s1_readdata),                  //                                         .readdata
		.regfile_we_s1_address                          (mm_interconnect_0_regfile_we_s1_address),                     //                            regfile_we_s1.address
		.regfile_we_s1_write                            (mm_interconnect_0_regfile_we_s1_write),                       //                                         .write
		.regfile_we_s1_readdata                         (mm_interconnect_0_regfile_we_s1_readdata),                    //                                         .readdata
		.regfile_we_s1_writedata                        (mm_interconnect_0_regfile_we_s1_writedata),                   //                                         .writedata
		.regfile_we_s1_chipselect                       (mm_interconnect_0_regfile_we_s1_chipselect),                  //                                         .chipselect
		.regfile_wsel_s1_address                        (mm_interconnect_0_regfile_wsel_s1_address),                   //                          regfile_wsel_s1.address
		.regfile_wsel_s1_write                          (mm_interconnect_0_regfile_wsel_s1_write),                     //                                         .write
		.regfile_wsel_s1_readdata                       (mm_interconnect_0_regfile_wsel_s1_readdata),                  //                                         .readdata
		.regfile_wsel_s1_writedata                      (mm_interconnect_0_regfile_wsel_s1_writedata),                 //                                         .writedata
		.regfile_wsel_s1_chipselect                     (mm_interconnect_0_regfile_wsel_s1_chipselect),                //                                         .chipselect
		.sram_addr_s1_address                           (mm_interconnect_0_sram_addr_s1_address),                      //                             sram_addr_s1.address
		.sram_addr_s1_write                             (mm_interconnect_0_sram_addr_s1_write),                        //                                         .write
		.sram_addr_s1_readdata                          (mm_interconnect_0_sram_addr_s1_readdata),                     //                                         .readdata
		.sram_addr_s1_writedata                         (mm_interconnect_0_sram_addr_s1_writedata),                    //                                         .writedata
		.sram_addr_s1_chipselect                        (mm_interconnect_0_sram_addr_s1_chipselect),                   //                                         .chipselect
		.sram_cs_s1_address                             (mm_interconnect_0_sram_cs_s1_address),                        //                               sram_cs_s1.address
		.sram_cs_s1_write                               (mm_interconnect_0_sram_cs_s1_write),                          //                                         .write
		.sram_cs_s1_readdata                            (mm_interconnect_0_sram_cs_s1_readdata),                       //                                         .readdata
		.sram_cs_s1_writedata                           (mm_interconnect_0_sram_cs_s1_writedata),                      //                                         .writedata
		.sram_cs_s1_chipselect                          (mm_interconnect_0_sram_cs_s1_chipselect),                     //                                         .chipselect
		.sram_data_s1_address                           (mm_interconnect_0_sram_data_s1_address),                      //                             sram_data_s1.address
		.sram_data_s1_write                             (mm_interconnect_0_sram_data_s1_write),                        //                                         .write
		.sram_data_s1_readdata                          (mm_interconnect_0_sram_data_s1_readdata),                     //                                         .readdata
		.sram_data_s1_writedata                         (mm_interconnect_0_sram_data_s1_writedata),                    //                                         .writedata
		.sram_data_s1_chipselect                        (mm_interconnect_0_sram_data_s1_chipselect),                   //                                         .chipselect
		.sram_oe_s1_address                             (mm_interconnect_0_sram_oe_s1_address),                        //                               sram_oe_s1.address
		.sram_oe_s1_write                               (mm_interconnect_0_sram_oe_s1_write),                          //                                         .write
		.sram_oe_s1_readdata                            (mm_interconnect_0_sram_oe_s1_readdata),                       //                                         .readdata
		.sram_oe_s1_writedata                           (mm_interconnect_0_sram_oe_s1_writedata),                      //                                         .writedata
		.sram_oe_s1_chipselect                          (mm_interconnect_0_sram_oe_s1_chipselect),                     //                                         .chipselect
		.sram_read_write_s1_address                     (mm_interconnect_0_sram_read_write_s1_address),                //                       sram_read_write_s1.address
		.sram_read_write_s1_write                       (mm_interconnect_0_sram_read_write_s1_write),                  //                                         .write
		.sram_read_write_s1_readdata                    (mm_interconnect_0_sram_read_write_s1_readdata),               //                                         .readdata
		.sram_read_write_s1_writedata                   (mm_interconnect_0_sram_read_write_s1_writedata),              //                                         .writedata
		.sram_read_write_s1_chipselect                  (mm_interconnect_0_sram_read_write_s1_chipselect),             //                                         .chipselect
		.switches_s1_address                            (mm_interconnect_0_switches_s1_address),                       //                              switches_s1.address
		.switches_s1_readdata                           (mm_interconnect_0_switches_s1_readdata)                       //                                         .readdata
	);

	nios_system_irq_mapper irq_mapper (
		.clk           (clk_clk),                        //       clk.clk
		.reset         (rst_controller_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
		.sender_irq    (nios2_qsys_0_irq_irq)            //    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                         // reset_in0.reset
		.reset_in1      (nios2_qsys_0_debug_reset_request_reset), // reset_in1.reset
		.clk            (clk_clk),                                //       clk.clk
		.reset_out      (rst_controller_reset_out_reset),         // reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req),     //          .reset_req
		.reset_req_in0  (1'b0),                                   // (terminated)
		.reset_req_in1  (1'b0),                                   // (terminated)
		.reset_in2      (1'b0),                                   // (terminated)
		.reset_req_in2  (1'b0),                                   // (terminated)
		.reset_in3      (1'b0),                                   // (terminated)
		.reset_req_in3  (1'b0),                                   // (terminated)
		.reset_in4      (1'b0),                                   // (terminated)
		.reset_req_in4  (1'b0),                                   // (terminated)
		.reset_in5      (1'b0),                                   // (terminated)
		.reset_req_in5  (1'b0),                                   // (terminated)
		.reset_in6      (1'b0),                                   // (terminated)
		.reset_req_in6  (1'b0),                                   // (terminated)
		.reset_in7      (1'b0),                                   // (terminated)
		.reset_req_in7  (1'b0),                                   // (terminated)
		.reset_in8      (1'b0),                                   // (terminated)
		.reset_req_in8  (1'b0),                                   // (terminated)
		.reset_in9      (1'b0),                                   // (terminated)
		.reset_req_in9  (1'b0),                                   // (terminated)
		.reset_in10     (1'b0),                                   // (terminated)
		.reset_req_in10 (1'b0),                                   // (terminated)
		.reset_in11     (1'b0),                                   // (terminated)
		.reset_req_in11 (1'b0),                                   // (terminated)
		.reset_in12     (1'b0),                                   // (terminated)
		.reset_req_in12 (1'b0),                                   // (terminated)
		.reset_in13     (1'b0),                                   // (terminated)
		.reset_req_in13 (1'b0),                                   // (terminated)
		.reset_in14     (1'b0),                                   // (terminated)
		.reset_req_in14 (1'b0),                                   // (terminated)
		.reset_in15     (1'b0),                                   // (terminated)
		.reset_req_in15 (1'b0)                                    // (terminated)
	);

endmodule
