// DO NOT EDIT
// This file is automatically generated!
// $ smg.shen rtl/SMG/seq.smg
//
// https://github.com/sam-falvo/smg

module Sequencer(
	input 	take_irq,
	input 	csrok_i,
	input 	trap,
	input [7:0]	ccr,
	input 	xt4,
	input 	xt3,
	input 	xt2,
	input 	xt1,
	input 	xt0,
	input [31:0]	ir,
	input 	dack_i,
	input 	iack_i,
	input 	ft0,
	input 	rst,
	output 	mcause_irq_o,
	output 	mepc_pc,
	output 	alub_imm5,
	output 	alua_cdat,
	output 	cdat_alu,
	output 	cdat_imm5,
	output 	cwe_o,
	output 	cdat_rdat,
	output 	coe_o,
	output 	rdat_cdat,
	output 	mpie_1,
	output 	mie_mpie,
	output 	pc_mepc,
	output 	mcause_2,
	output 	mcause_3,
	output 	mcause_11,
	output 	mie_0,
	output 	mpie_mie,
	output 	pc_mtvec,
	output 	mepc_ia,
	output 	trap_o,
	output 	fence_o,
	output 	xt4_o,
	output 	alub_imm12sb,
	output 	ccr_alu,
	output 	dwe_o,
	output 	ddat_rdat,
	output 	rdat_ddat,
	output 	dsiz_fn3,
	output 	dstb_1,
	output 	dcyc_1,
	output 	dadr_alu,
	output 	ia_pc,
	output 	sx32_en,
	output 	pc_alu,
	output 	xt3_o,
	output 	and_en,
	output 	rsh_en,
	output 	xor_en,
	output 	ltu_en,
	output 	lts_en,
	output 	invB_en,
	output 	cflag_i,
	output 	lsh_en,
	output 	sum_en,
	output 	alub_imm20uj,
	output 	alub_imm20u,
	output 	alub_imm12s,
	output 	alub_imm12i,
	output 	alub_rdat,
	output 	alua_ia,
	output 	alua_0,
	output 	alua_rdat,
	output 	rwe_o,
	output 	rdat_pc,
	output 	rdat_alu,
	output 	ra_ird,
	output 	ra_ir2,
	output 	ra_ir1,
	output 	xt2_o,
	output 	xt1_o,
	output 	xt0_o,
	output 	ir_idat,
	output 	pc_pcPlus4,
	output 	istb_o,
	output 	iadr_pc,
	output 	pc_mbvec,
	output 	ft0_o
);
wire  isCsrRcI;
wire  isCsrRc;
wire  isCsrRsI;
wire  isCsrRs;
wire  isCsrRwI;
wire  isCsrRw;
wire  isMRet;
wire  isEBreak;
wire  isECall;
wire  isFence;
wire  isBr;
wire  isJal;
wire  isStore;
wire  isLoad;
wire  isLuiAuipc;
wire  useAlu2;
wire  useAlu;
wire  fn3_is_111;
wire  fn3_is_110;
wire  fn3_is_101;
wire  fn3_is_100;
wire  fn3_is_011;
wire  fn3_is_010;
wire  fn3_is_001;
wire  fn3_is_000;
wire  isJalr;
wire  isOpR;
wire  isOpI;
wire R1391 = (|rst) ; 
wire R1392 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) ; 
wire R1393 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) & ~(|iack_i) ; 
wire R1394 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) & (|iack_i) ; 
wire R1395 = ~(|rst) & ~(|take_irq) & (|trap) ; 
wire R1396 = ~(|rst) & (|ft0) & (|take_irq) ; 
wire R1397 = ~(|rst) & ~(|trap) & ~(|ft0) & ~(|xt0) & ~(|xt1) & ~(|xt2) & ~(|xt3) & ~(|xt4) ; 
wire R1398 = ( ir[14:12] == 3'b000 ) ; 
wire R1399 = ( ir[14:12] == 3'b001 ) ; 
wire R1400 = ( ir[14:12] == 3'b010 ) ; 
wire R1401 = ( ir[14:12] == 3'b011 ) ; 
wire R1402 = ( ir[14:12] == 3'b100 ) ; 
wire R1403 = ( ir[14:12] == 3'b101 ) ; 
wire R1404 = ( ir[14:12] == 3'b110 ) ; 
wire R1405 = ( ir[14:12] == 3'b111 ) ; 
wire R1406 = ( ir[6:4] == 3'b001 ) & ( ir[2:0] == 3'b011 ) ; 
wire R1407 = ( ir[6:4] == 3'b011 ) & ( ir[2:0] == 3'b011 ) ; 
wire R1408 = ~(|rst) & (|xt0) & (|isOpI) ; 
wire R1409 = ~(|rst) & (|xt1) & (|isOpI) ; 
wire R1410 = ~(|rst) & (|xt2) & (|isOpI) ; 
wire R1411 = (|useAlu) & (|fn3_is_000) ; 
wire R1412 = (|useAlu) & (|fn3_is_001) ; 
wire R1413 = (|useAlu) & (|fn3_is_010) ; 
wire R1414 = (|useAlu) & (|fn3_is_011) ; 
wire R1415 = (|useAlu) & (|fn3_is_100) ; 
wire R1416 = (|useAlu) & (|fn3_is_101) & ~(|ir[30]) ; 
wire R1417 = (|useAlu) & (|fn3_is_101) & (|ir[30]) ; 
wire R1418 = (|useAlu) & (|fn3_is_110) ; 
wire R1419 = (|useAlu) & (|fn3_is_111) ; 
wire R1420 = (|useAlu) & (|ir[3]) ; 
wire R1421 = ~(|rst) & (|xt0) & (|isOpR) ; 
wire R1422 = ~(|rst) & (|xt1) & (|isOpR) ; 
wire R1423 = ~(|rst) & (|xt2) & (|isOpR) ; 
wire R1424 = ~(|rst) & (|xt3) & (|isOpR) ; 
wire R1425 = (|useAlu2) & (|fn3_is_000) & ~(|ir[30]) ; 
wire R1426 = (|useAlu2) & (|fn3_is_000) & (|ir[30]) ; 
wire R1427 = (|useAlu2) & (|fn3_is_001) ; 
wire R1428 = (|useAlu2) & (|fn3_is_010) ; 
wire R1429 = (|useAlu2) & (|fn3_is_011) ; 
wire R1430 = (|useAlu2) & (|fn3_is_100) ; 
wire R1431 = (|useAlu2) & (|fn3_is_101) & ~(|ir[30]) ; 
wire R1432 = (|useAlu2) & (|fn3_is_101) & (|ir[30]) ; 
wire R1433 = (|useAlu2) & (|fn3_is_110) ; 
wire R1434 = (|useAlu2) & (|fn3_is_111) ; 
wire R1435 = (|useAlu2) & (|ir[3]) ; 
wire R1436 = ( ir[6:0] == 7'b1100111 ) ; 
wire R1437 = ( ir[6:0] == 7'b1101111 ) ; 
wire R1438 = ~(|rst) & (|xt0) & (|isJalr) ; 
wire R1439 = ~(|rst) & (|xt1) & (|isJalr) ; 
wire R1440 = ~(|rst) & (|xt2) & (|isJalr) ; 
wire R1441 = ~(|rst) & (|xt3) & (|isJalr) ; 
wire R1442 = ~(|rst) & (|xt0) & (|isJal) ; 
wire R1443 = ~(|rst) & (|xt1) & (|isJal) ; 
wire R1444 = ~(|rst) & (|xt2) & (|isJal) ; 
wire R1445 = ~(|ir[6]) & ( ir[4:0] == 5'b10111 ) ; 
wire R1446 = ~(|rst) & (|xt0) & (|isLuiAuipc) ; 
wire R1447 = ~(|rst) & (|xt0) & (|isLuiAuipc) & (|ir[5]) ; 
wire R1448 = ~(|rst) & (|xt0) & (|isLuiAuipc) & ~(|ir[5]) ; 
wire R1449 = ~(|rst) & (|xt1) & (|isLuiAuipc) ; 
wire R1450 = ( ir[6:0] == 7'b0000011 ) ; 
wire R1451 = ( ir[6:0] == 7'b0100011 ) ; 
wire R1452 = ~(|rst) & (|xt0) & (|isLoad) ; 
wire R1453 = ~(|rst) & (|xt1) & (|isLoad) ; 
wire R1454 = ~(|rst) & (|xt2) & (|isLoad) & ~(|dack_i) ; 
wire R1455 = ~(|rst) & (|xt2) & (|isLoad) & (|dack_i) ; 
wire R1456 = ~(|rst) & (|xt0) & (|isStore) ; 
wire R1457 = ~(|rst) & (|xt1) & (|isStore) ; 
wire R1458 = ~(|rst) & (|xt2) & (|isStore) & ~(|dack_i) ; 
wire R1459 = ~(|rst) & (|xt2) & (|isStore) & (|dack_i) ; 
wire R1460 = ( ir[6:0] == 7'b1100011 ) ; 
wire R1461 = ~(|rst) & (|xt0) & (|isBr) ; 
wire R1462 = ~(|rst) & (|xt1) & (|isBr) ; 
wire R1463 = ~(|rst) & (|xt2) & (|isBr) ; 
wire R1464 = ~(|rst) & (|xt3) & (|isBr) ; 
wire R1465 = ~(|rst) & (|xt4) & (|isBr) ; 
wire R1466 = (|isBr) & (|xt4) & (|fn3_is_000) & (|ccr[0]) ; 
wire R1467 = (|isBr) & (|xt4) & (|fn3_is_001) & (|ccr[1]) ; 
wire R1468 = (|isBr) & (|xt4) & (|fn3_is_100) & (|ccr[4]) ; 
wire R1469 = (|isBr) & (|xt4) & (|fn3_is_101) & (|ccr[5]) ; 
wire R1470 = (|isBr) & (|xt4) & (|fn3_is_110) & (|ccr[6]) ; 
wire R1471 = (|isBr) & (|xt4) & (|fn3_is_111) & (|ccr[7]) ; 
wire R1472 = ( ir[31:28] == 4'b0000 ) & ( ir[19:0] == 20'h0000F ) ; 
wire R1473 = ( ir[31:0] == 32'h0000100F ) ; 
wire R1474 = ~(|rst) & (|isFence) & (|xt0) ; 
wire R1475 = ~(|rst) & (|isFence) & (|xt1) ; 
wire R1476 = ~(|rst) & (|isFence) & (|xt2) ; 
wire R1477 = ~(|rst) & (|isFence) & (|xt3) ; 
wire R1478 = ( ir[31:0] == 32'b0000_0000_0000_00000_000_00000_1110011 ) ; 
wire R1479 = ( ir[31:0] == 32'b0000_0000_0001_00000_000_00000_1110011 ) ; 
wire R1480 = ~(|rst) & (|isECall) & (|xt0) ; 
wire R1481 = ~(|rst) & (|isEBreak) & (|xt0) ; 
wire R1482 = ( ir[31:0] == 32'b0011_0000_0010_00000_000_00000_1110011 ) ; 
wire R1483 = ~(|rst) & (|isMRet) & (|xt0) ; 
wire R1484 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_001) ; 
wire R1485 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_010) ; 
wire R1486 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_011) ; 
wire R1487 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_101) ; 
wire R1488 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_110) ; 
wire R1489 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_111) ; 
wire R1490 = ~(|rst) & (|isCsrRw) & (|xt0) & (|csrok_i) ; 
wire R1491 = ~(|rst) & (|isCsrRw) & (|xt1) ; 
wire R1492 = ~(|rst) & (|isCsrRwI) & (|xt0) & (|csrok_i) ; 
wire R1493 = ~(|rst) & (|isCsrRwI) & (|xt1) ; 
wire R1494 = ~(|rst) & (|isCsrRs) & (|xt0) & (|csrok_i) ; 
wire R1495 = ~(|rst) & (|isCsrRs) & (|xt1) ; 
wire R1496 = ~(|rst) & (|isCsrRs) & (|xt2) ; 
wire R1497 = ~(|rst) & (|isCsrRsI) & (|xt0) & (|csrok_i) ; 
wire R1498 = ~(|rst) & (|isCsrRsI) & (|xt1) ; 
wire R1499 = ~(|rst) & (|isCsrRsI) & (|xt2) ; 
wire R1500 = ~(|rst) & (|isCsrRc) & (|xt0) & (|csrok_i) ; 
wire R1501 = ~(|rst) & (|isCsrRc) & (|xt1) ; 
wire R1502 = ~(|rst) & (|isCsrRc) & (|xt2) ; 
wire R1503 = ~(|rst) & (|isCsrRcI) & (|xt0) & (|csrok_i) ; 
wire R1504 = ~(|rst) & (|isCsrRcI) & (|xt1) ; 
wire R1505 = ~(|rst) & (|isCsrRcI) & (|xt2) ; 
wire  out1506 = R1391 ? 1 : 0 ; 
wire  out1507 = R1391 ? 1 : 0 ; 
wire  out1508 = R1391 ? 1 : 0 ; 
wire  out1509 = R1391 ? 1 : 0 ; 
wire  out1510 = R1392 ? 1 : 0 ; 
wire  out1511 = R1392 ? 1 : 0 ; 
wire  out1512 = R1393 ? 1 : 0 ; 
wire  out1513 = R1394 ? 1 : 0 ; 
wire  out1514 = R1394 ? 1 : 0 ; 
wire  out1515 = R1394 ? 1 : 0 ; 
wire  out1516 = R1394 ? 1 : 0 ; 
wire  out1517 = R1395 ? 1 : 0 ; 
wire  out1518 = R1395 ? 1 : 0 ; 
wire  out1519 = R1395 ? 1 : 0 ; 
wire  out1520 = R1395 ? 1 : 0 ; 
wire  out1521 = R1395 ? 1 : 0 ; 
wire  out1522 = R1396 ? 1 : 0 ; 
wire  out1523 = R1396 ? 1 : 0 ; 
wire  out1524 = R1396 ? 1 : 0 ; 
wire  out1525 = R1396 ? 1 : 0 ; 
wire  out1526 = R1396 ? 1 : 0 ; 
wire  out1527 = R1396 ? 1 : 0 ; 
wire  out1528 = R1396 ? 1 : 0 ; 
wire  out1529 = R1397 ? 1 : 0 ; 
wire  out1530 = R1397 ? 1 : 0 ; 
wire  out1531 = R1398 ? 1 : 0 ; 
wire  out1532 = R1399 ? 1 : 0 ; 
wire  out1533 = R1400 ? 1 : 0 ; 
wire  out1534 = R1401 ? 1 : 0 ; 
wire  out1535 = R1402 ? 1 : 0 ; 
wire  out1536 = R1403 ? 1 : 0 ; 
wire  out1537 = R1404 ? 1 : 0 ; 
wire  out1538 = R1405 ? 1 : 0 ; 
wire  out1539 = R1406 ? 1 : 0 ; 
wire  out1540 = R1407 ? 1 : 0 ; 
wire  out1541 = R1408 ? 1 : 0 ; 
wire  out1542 = R1408 ? 1 : 0 ; 
wire  out1543 = R1409 ? 1 : 0 ; 
wire  out1544 = R1409 ? 1 : 0 ; 
wire  out1545 = R1409 ? 1 : 0 ; 
wire  out1546 = R1410 ? 1 : 0 ; 
wire  out1547 = R1410 ? 1 : 0 ; 
wire  out1548 = R1410 ? 1 : 0 ; 
wire  out1549 = R1410 ? 1 : 0 ; 
wire  out1550 = R1410 ? 1 : 0 ; 
wire  out1551 = R1411 ? 1 : 0 ; 
wire  out1552 = R1412 ? 1 : 0 ; 
wire  out1553 = R1413 ? 1 : 0 ; 
wire  out1554 = R1413 ? 1 : 0 ; 
wire  out1555 = R1413 ? 1 : 0 ; 
wire  out1556 = R1414 ? 1 : 0 ; 
wire  out1557 = R1414 ? 1 : 0 ; 
wire  out1558 = R1414 ? 1 : 0 ; 
wire  out1559 = R1415 ? 1 : 0 ; 
wire  out1560 = R1416 ? 1 : 0 ; 
wire  out1561 = R1417 ? 1 : 0 ; 
wire  out1562 = R1417 ? 1 : 0 ; 
wire  out1563 = R1418 ? 1 : 0 ; 
wire  out1564 = R1418 ? 1 : 0 ; 
wire  out1565 = R1419 ? 1 : 0 ; 
wire  out1566 = R1420 ? 1 : 0 ; 
wire  out1567 = R1421 ? 1 : 0 ; 
wire  out1568 = R1421 ? 1 : 0 ; 
wire  out1569 = R1422 ? 1 : 0 ; 
wire  out1570 = R1422 ? 1 : 0 ; 
wire  out1571 = R1422 ? 1 : 0 ; 
wire  out1572 = R1423 ? 1 : 0 ; 
wire  out1573 = R1423 ? 1 : 0 ; 
wire  out1574 = R1424 ? 1 : 0 ; 
wire  out1575 = R1424 ? 1 : 0 ; 
wire  out1576 = R1424 ? 1 : 0 ; 
wire  out1577 = R1424 ? 1 : 0 ; 
wire  out1578 = R1424 ? 1 : 0 ; 
wire  out1579 = R1425 ? 1 : 0 ; 
wire  out1580 = R1426 ? 1 : 0 ; 
wire  out1581 = R1426 ? 1 : 0 ; 
wire  out1582 = R1426 ? 1 : 0 ; 
wire  out1583 = R1427 ? 1 : 0 ; 
wire  out1584 = R1428 ? 1 : 0 ; 
wire  out1585 = R1428 ? 1 : 0 ; 
wire  out1586 = R1428 ? 1 : 0 ; 
wire  out1587 = R1429 ? 1 : 0 ; 
wire  out1588 = R1429 ? 1 : 0 ; 
wire  out1589 = R1429 ? 1 : 0 ; 
wire  out1590 = R1430 ? 1 : 0 ; 
wire  out1591 = R1431 ? 1 : 0 ; 
wire  out1592 = R1432 ? 1 : 0 ; 
wire  out1593 = R1432 ? 1 : 0 ; 
wire  out1594 = R1433 ? 1 : 0 ; 
wire  out1595 = R1433 ? 1 : 0 ; 
wire  out1596 = R1434 ? 1 : 0 ; 
wire  out1597 = R1435 ? 1 : 0 ; 
wire  out1598 = R1436 ? 1 : 0 ; 
wire  out1599 = R1437 ? 1 : 0 ; 
wire  out1600 = R1438 ? 1 : 0 ; 
wire  out1601 = R1438 ? 1 : 0 ; 
wire  out1602 = R1438 ? 1 : 0 ; 
wire  out1603 = R1438 ? 1 : 0 ; 
wire  out1604 = R1439 ? 1 : 0 ; 
wire  out1605 = R1439 ? 1 : 0 ; 
wire  out1606 = R1440 ? 1 : 0 ; 
wire  out1607 = R1440 ? 1 : 0 ; 
wire  out1608 = R1440 ? 1 : 0 ; 
wire  out1609 = R1441 ? 1 : 0 ; 
wire  out1610 = R1441 ? 1 : 0 ; 
wire  out1611 = R1441 ? 1 : 0 ; 
wire  out1612 = R1442 ? 1 : 0 ; 
wire  out1613 = R1442 ? 1 : 0 ; 
wire  out1614 = R1442 ? 1 : 0 ; 
wire  out1615 = R1442 ? 1 : 0 ; 
wire  out1616 = R1443 ? 1 : 0 ; 
wire  out1617 = R1443 ? 1 : 0 ; 
wire  out1618 = R1443 ? 1 : 0 ; 
wire  out1619 = R1444 ? 1 : 0 ; 
wire  out1620 = R1444 ? 1 : 0 ; 
wire  out1621 = R1444 ? 1 : 0 ; 
wire  out1622 = R1445 ? 1 : 0 ; 
wire  out1623 = R1446 ? 1 : 0 ; 
wire  out1624 = R1446 ? 1 : 0 ; 
wire  out1625 = R1447 ? 1 : 0 ; 
wire  out1626 = R1448 ? 1 : 0 ; 
wire  out1627 = R1449 ? 1 : 0 ; 
wire  out1628 = R1449 ? 1 : 0 ; 
wire  out1629 = R1449 ? 1 : 0 ; 
wire  out1630 = R1449 ? 1 : 0 ; 
wire  out1631 = R1449 ? 1 : 0 ; 
wire  out1632 = R1450 ? 1 : 0 ; 
wire  out1633 = R1451 ? 1 : 0 ; 
wire  out1634 = R1452 ? 1 : 0 ; 
wire  out1635 = R1452 ? 1 : 0 ; 
wire  out1636 = R1453 ? 1 : 0 ; 
wire  out1637 = R1453 ? 1 : 0 ; 
wire  out1638 = R1453 ? 1 : 0 ; 
wire  out1639 = R1454 ? 1 : 0 ; 
wire  out1640 = R1454 ? 1 : 0 ; 
wire  out1641 = R1454 ? 1 : 0 ; 
wire  out1642 = R1454 ? 1 : 0 ; 
wire  out1643 = R1454 ? 1 : 0 ; 
wire  out1644 = R1454 ? 1 : 0 ; 
wire  out1645 = R1455 ? 1 : 0 ; 
wire  out1646 = R1455 ? 1 : 0 ; 
wire  out1647 = R1455 ? 1 : 0 ; 
wire  out1648 = R1455 ? 1 : 0 ; 
wire  out1649 = R1455 ? 1 : 0 ; 
wire  out1650 = R1455 ? 1 : 0 ; 
wire  out1651 = R1455 ? 1 : 0 ; 
wire  out1652 = R1455 ? 1 : 0 ; 
wire  out1653 = R1455 ? 1 : 0 ; 
wire  out1654 = R1456 ? 1 : 0 ; 
wire  out1655 = R1456 ? 1 : 0 ; 
wire  out1656 = R1457 ? 1 : 0 ; 
wire  out1657 = R1457 ? 1 : 0 ; 
wire  out1658 = R1457 ? 1 : 0 ; 
wire  out1659 = R1457 ? 1 : 0 ; 
wire  out1660 = R1458 ? 1 : 0 ; 
wire  out1661 = R1458 ? 1 : 0 ; 
wire  out1662 = R1458 ? 1 : 0 ; 
wire  out1663 = R1458 ? 1 : 0 ; 
wire  out1664 = R1458 ? 1 : 0 ; 
wire  out1665 = R1458 ? 1 : 0 ; 
wire  out1666 = R1458 ? 1 : 0 ; 
wire  out1667 = R1458 ? 1 : 0 ; 
wire  out1668 = R1458 ? 1 : 0 ; 
wire  out1669 = R1459 ? 1 : 0 ; 
wire  out1670 = R1459 ? 1 : 0 ; 
wire  out1671 = R1459 ? 1 : 0 ; 
wire  out1672 = R1459 ? 1 : 0 ; 
wire  out1673 = R1459 ? 1 : 0 ; 
wire  out1674 = R1459 ? 1 : 0 ; 
wire  out1675 = R1459 ? 1 : 0 ; 
wire  out1676 = R1459 ? 1 : 0 ; 
wire  out1677 = R1460 ? 1 : 0 ; 
wire  out1678 = R1461 ? 1 : 0 ; 
wire  out1679 = R1461 ? 1 : 0 ; 
wire  out1680 = R1462 ? 1 : 0 ; 
wire  out1681 = R1462 ? 1 : 0 ; 
wire  out1682 = R1462 ? 1 : 0 ; 
wire  out1683 = R1463 ? 1 : 0 ; 
wire  out1684 = R1463 ? 1 : 0 ; 
wire  out1685 = R1464 ? 1 : 0 ; 
wire  out1686 = R1464 ? 1 : 0 ; 
wire  out1687 = R1464 ? 1 : 0 ; 
wire  out1688 = R1464 ? 1 : 0 ; 
wire  out1689 = R1464 ? 1 : 0 ; 
wire  out1690 = R1464 ? 1 : 0 ; 
wire  out1691 = R1464 ? 1 : 0 ; 
wire  out1692 = R1465 ? 1 : 0 ; 
wire  out1693 = R1465 ? 1 : 0 ; 
wire  out1694 = R1466 ? 1 : 0 ; 
wire  out1695 = R1467 ? 1 : 0 ; 
wire  out1696 = R1468 ? 1 : 0 ; 
wire  out1697 = R1469 ? 1 : 0 ; 
wire  out1698 = R1470 ? 1 : 0 ; 
wire  out1699 = R1471 ? 1 : 0 ; 
wire  out1700 = R1472 ? 1 : 0 ; 
wire  out1701 = R1473 ? 1 : 0 ; 
wire  out1702 = R1474 ? 1 : 0 ; 
wire  out1703 = R1474 ? 1 : 0 ; 
wire  out1704 = R1475 ? 1 : 0 ; 
wire  out1705 = R1475 ? 1 : 0 ; 
wire  out1706 = R1476 ? 1 : 0 ; 
wire  out1707 = R1476 ? 1 : 0 ; 
wire  out1708 = R1477 ? 1 : 0 ; 
wire  out1709 = R1477 ? 1 : 0 ; 
wire  out1710 = R1478 ? 1 : 0 ; 
wire  out1711 = R1479 ? 1 : 0 ; 
wire  out1712 = R1480 ? 1 : 0 ; 
wire  out1713 = R1480 ? 1 : 0 ; 
wire  out1714 = R1481 ? 1 : 0 ; 
wire  out1715 = R1481 ? 1 : 0 ; 
wire  out1716 = R1482 ? 1 : 0 ; 
wire  out1717 = R1483 ? 1 : 0 ; 
wire  out1718 = R1483 ? 1 : 0 ; 
wire  out1719 = R1483 ? 1 : 0 ; 
wire  out1720 = R1483 ? 1 : 0 ; 
wire  out1721 = R1484 ? 1 : 0 ; 
wire  out1722 = R1485 ? 1 : 0 ; 
wire  out1723 = R1486 ? 1 : 0 ; 
wire  out1724 = R1487 ? 1 : 0 ; 
wire  out1725 = R1488 ? 1 : 0 ; 
wire  out1726 = R1489 ? 1 : 0 ; 
wire  out1727 = R1490 ? 1 : 0 ; 
wire  out1728 = R1490 ? 1 : 0 ; 
wire  out1729 = R1491 ? 1 : 0 ; 
wire  out1730 = R1491 ? 1 : 0 ; 
wire  out1731 = R1491 ? 1 : 0 ; 
wire  out1732 = R1491 ? 1 : 0 ; 
wire  out1733 = R1491 ? 1 : 0 ; 
wire  out1734 = R1491 ? 1 : 0 ; 
wire  out1735 = R1491 ? 1 : 0 ; 
wire  out1736 = R1492 ? 1 : 0 ; 
wire  out1737 = R1493 ? 1 : 0 ; 
wire  out1738 = R1493 ? 1 : 0 ; 
wire  out1739 = R1493 ? 1 : 0 ; 
wire  out1740 = R1493 ? 1 : 0 ; 
wire  out1741 = R1493 ? 1 : 0 ; 
wire  out1742 = R1493 ? 1 : 0 ; 
wire  out1743 = R1493 ? 1 : 0 ; 
wire  out1744 = R1494 ? 1 : 0 ; 
wire  out1745 = R1494 ? 1 : 0 ; 
wire  out1746 = R1495 ? 1 : 0 ; 
wire  out1747 = R1495 ? 1 : 0 ; 
wire  out1748 = R1495 ? 1 : 0 ; 
wire  out1749 = R1495 ? 1 : 0 ; 
wire  out1750 = R1495 ? 1 : 0 ; 
wire  out1751 = R1495 ? 1 : 0 ; 
wire  out1752 = R1495 ? 1 : 0 ; 
wire  out1753 = R1496 ? 1 : 0 ; 
wire  out1754 = R1496 ? 1 : 0 ; 
wire  out1755 = R1496 ? 1 : 0 ; 
wire  out1756 = R1496 ? 1 : 0 ; 
wire  out1757 = R1496 ? 1 : 0 ; 
wire  out1758 = R1497 ? 1 : 0 ; 
wire  out1759 = R1498 ? 1 : 0 ; 
wire  out1760 = R1498 ? 1 : 0 ; 
wire  out1761 = R1498 ? 1 : 0 ; 
wire  out1762 = R1498 ? 1 : 0 ; 
wire  out1763 = R1498 ? 1 : 0 ; 
wire  out1764 = R1498 ? 1 : 0 ; 
wire  out1765 = R1498 ? 1 : 0 ; 
wire  out1766 = R1499 ? 1 : 0 ; 
wire  out1767 = R1499 ? 1 : 0 ; 
wire  out1768 = R1499 ? 1 : 0 ; 
wire  out1769 = R1499 ? 1 : 0 ; 
wire  out1770 = R1499 ? 1 : 0 ; 
wire  out1771 = R1500 ? 1 : 0 ; 
wire  out1772 = R1500 ? 1 : 0 ; 
wire  out1773 = R1501 ? 1 : 0 ; 
wire  out1774 = R1501 ? 1 : 0 ; 
wire  out1775 = R1501 ? 1 : 0 ; 
wire  out1776 = R1501 ? 1 : 0 ; 
wire  out1777 = R1501 ? 1 : 0 ; 
wire  out1778 = R1501 ? 1 : 0 ; 
wire  out1779 = R1501 ? 1 : 0 ; 
wire  out1780 = R1502 ? 1 : 0 ; 
wire  out1781 = R1502 ? 1 : 0 ; 
wire  out1782 = R1502 ? 1 : 0 ; 
wire  out1783 = R1502 ? 1 : 0 ; 
wire  out1784 = R1502 ? 1 : 0 ; 
wire  out1785 = R1503 ? 1 : 0 ; 
wire  out1786 = R1504 ? 1 : 0 ; 
wire  out1787 = R1504 ? 1 : 0 ; 
wire  out1788 = R1504 ? 1 : 0 ; 
wire  out1789 = R1504 ? 1 : 0 ; 
wire  out1790 = R1504 ? 1 : 0 ; 
wire  out1791 = R1504 ? 1 : 0 ; 
wire  out1792 = R1504 ? 1 : 0 ; 
wire  out1793 = R1505 ? 1 : 0 ; 
wire  out1794 = R1505 ? 1 : 0 ; 
wire  out1795 = R1505 ? 1 : 0 ; 
wire  out1796 = R1505 ? 1 : 0 ; 
wire  out1797 = R1505 ? 1 : 0 ; 
assign dsiz_fn3 = out1673|out1665|out1649|out1644;
assign isBr = out1677;
assign isFence = out1701|out1700;
assign isLoad = out1632;
assign invB_en = out1794|out1781|out1687|out1588|out1585|out1582|out1557|out1554;
assign ia_pc = out1514;
assign cflag_i = out1688|out1593|out1587|out1584|out1581|out1562|out1556|out1553;
assign and_en = out1793|out1780|out1766|out1753|out1596|out1594|out1565|out1563;
assign isJalr = out1598;
assign isCsrRs = out1722;
assign alua_ia = out1690|out1626|out1617;
assign isLuiAuipc = out1622;
assign fn3_is_000 = out1531;
assign isCsrRw = out1721;
assign coe_o = out1789|out1776|out1762|out1749|out1739|out1731;
assign mepc_ia = out1517;
assign fn3_is_001 = out1532;
assign fn3_is_010 = out1533;
assign fn3_is_100 = out1535;
assign fn3_is_011 = out1534;
assign fn3_is_101 = out1536;
assign fn3_is_110 = out1537;
assign fence_o = out1709|out1707|out1705|out1703;
assign fn3_is_111 = out1538;
assign iadr_pc = out1510;
assign useAlu = out1549;
assign ra_ird = out1787|out1774|out1760|out1747|out1737|out1729|out1650|out1627|out1613|out1601|out1574|out1546;
assign cwe_o = out1796|out1783|out1769|out1756|out1742|out1734;
assign dwe_o = out1675|out1668;
assign alua_cdat = out1791|out1778|out1764|out1751;
assign mepc_pc = out1522;
assign pc_mepc = out1718;
assign pc_alu = out1699|out1698|out1697|out1696|out1695|out1694|out1620|out1610;
assign dadr_alu = out1670|out1662|out1646|out1641;
assign ccr_alu = out1689;
assign cdat_alu = out1795|out1782|out1768|out1755;
assign pc_mbvec = out1507;
assign mcause_11 = out1713|out1526;
assign ir_idat = out1515;
assign lsh_en = out1583|out1552;
assign rdat_pc = out1614|out1602;
assign rdat_cdat = out1788|out1775|out1761|out1748|out1738|out1730;
assign cdat_rdat = out1733;
assign rdat_ddat = out1652;
assign ddat_rdat = out1674|out1666;
assign mpie_mie = out1524|out1519;
assign mie_mpie = out1719;
assign rsh_en = out1592|out1591|out1561|out1560;
assign istb_o = out1511;
assign rwe_o = out1790|out1777|out1763|out1750|out1740|out1732|out1651|out1629|out1615|out1603|out1576|out1548;
assign alua_rdat = out1682|out1657|out1637|out1607|out1570|out1544;
assign alub_imm12i = out1638|out1608|out1545;
assign sx32_en = out1597|out1566;
assign alub_rdat = out1779|out1752|out1684|out1573;
assign rdat_alu = out1628|out1575|out1547;
assign trap_o = out1714|out1712|out1529;
assign lts_en = out1586|out1555;
assign isStore = out1633;
assign sum_en = out1693|out1686|out1669|out1661|out1645|out1640|out1630|out1621|out1611|out1580|out1579|out1551;
assign ltu_en = out1589|out1558;
assign pc_mtvec = out1523|out1518;
assign alub_imm12sb = out1691;
assign xor_en = out1767|out1754|out1595|out1590|out1564|out1559;
assign alub_imm12s = out1658;
assign alub_imm20u = out1624;
assign mie_0 = out1525|out1520|out1508;
assign alub_imm20uj = out1618;
assign alua_0 = out1625;
assign dcyc_1 = out1671|out1663|out1647|out1642;
assign isECall = out1710;
assign isCsrRcI = out1726;
assign mpie_1 = out1720|out1509;
assign mcause_irq_o = out1527;
assign ft0_o = out1797|out1784|out1770|out1757|out1743|out1735|out1717|out1708|out1692|out1676|out1653|out1631|out1619|out1609|out1578|out1550|out1528|out1521|out1512|out1506;
assign useAlu2 = out1577;
assign dstb_1 = out1672|out1664|out1648|out1643;
assign ra_ir1 = out1772|out1745|out1728|out1679|out1655|out1635|out1605|out1568|out1542;
assign isEBreak = out1711;
assign ra_ir2 = out1681|out1667|out1659|out1571;
assign mcause_2 = out1530;
assign cdat_imm5 = out1741;
assign isOpI = out1539;
assign mcause_3 = out1715;
assign isCsrRsI = out1725;
assign pc_pcPlus4 = out1513;
assign xt0_o = out1516;
assign isCsrRwI = out1724;
assign xt1_o = out1785|out1771|out1758|out1744|out1736|out1727|out1702|out1678|out1654|out1634|out1623|out1612|out1600|out1567|out1541;
assign alub_imm5 = out1792|out1765;
assign xt2_o = out1786|out1773|out1759|out1746|out1704|out1680|out1660|out1656|out1639|out1636|out1616|out1604|out1569|out1543;
assign isOpR = out1540;
assign xt3_o = out1706|out1683|out1606|out1572;
assign xt4_o = out1685;
assign isMRet = out1716;
assign isCsrRc = out1723;
assign isJal = out1599;
endmodule
