// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.3
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="dut_inst,dut,{component_name=dut_inst,HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.789000,HLS_SYN_LAT=12,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=11,HLS_SYN_FF=593,HLS_SYN_LUT=750}" *)

module dut (
        ap_clk,
        ap_rst,
        in_fifo_V_dout,
        in_fifo_V_empty_n,
        in_fifo_V_read,
        out_fifo_V_din,
        out_fifo_V_full_n,
        out_fifo_V_write
);

input   ap_clk;
input   ap_rst;
input  [31:0] in_fifo_V_dout;
input   in_fifo_V_empty_n;
output   in_fifo_V_read;
output  [31:0] out_fifo_V_din;
input   out_fifo_V_full_n;
output   out_fifo_V_write;

reg in_fifo_V_read;
reg[31:0] out_fifo_V_din;
reg out_fifo_V_write;
reg   [31:0] tmp_2_reg_115;
reg   [3:0] ap_CS_fsm = 4'b0000;
reg   [31:0] tmp_6_reg_120;
reg   [31:0] tmp_7_reg_125;
wire   [63:0] full_fu_60_p2;
reg   [63:0] full_reg_130;
wire   [63:0] full_1_fu_79_p2;
reg   [63:0] full_1_reg_135;
reg   [31:0] data1_reg_150;
wire   [15:0] data2_2_fu_107_p1;
reg   [15:0] data2_2_reg_155;
wire   [31:0] tmp_1_fu_111_p1;
wire   [63:0] grp_fu_44_p0;
wire   [63:0] grp_fu_44_p1;
wire   [63:0] tmp_3_fu_48_p1;
wire   [63:0] tmp_4_fu_51_p2;
wire   [63:0] full_fu_60_p1;
wire   [63:0] tmp_9_fu_66_p1;
wire   [63:0] tmp_s_fu_69_p2;
wire   [63:0] full_1_fu_79_p1;
wire   [63:0] grp_fu_44_p2;
wire   [63:0] ret_fu_93_p1;
wire    grp_fu_44_ce;
reg   [3:0] ap_NS_fsm;
parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;
parameter    ap_ST_st1_fsm_0 = 4'b0000;
parameter    ap_ST_st2_fsm_1 = 4'b0001;
parameter    ap_ST_st3_fsm_2 = 4'b0010;
parameter    ap_ST_st4_fsm_3 = 4'b0011;
parameter    ap_ST_st5_fsm_4 = 4'b0100;
parameter    ap_ST_st6_fsm_5 = 4'b0101;
parameter    ap_ST_st7_fsm_6 = 4'b0110;
parameter    ap_ST_st8_fsm_7 = 4'b0111;
parameter    ap_ST_st9_fsm_8 = 4'b1000;
parameter    ap_ST_st10_fsm_9 = 4'b1001;
parameter    ap_ST_st11_fsm_10 = 4'b1010;
parameter    ap_ST_st12_fsm_11 = 4'b1011;
parameter    ap_ST_st13_fsm_12 = 4'b1100;
parameter    ap_const_lv64_20 = 64'b0000000000000000000000000000000000000000000000000000000000100000;
parameter    ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter    ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter    ap_true = 1'b1;


dut_grp_fu_44_ACMP_dmul_1 #(
    .ID( 1 ),
    .NUM_STAGE( 6 ),
    .din0_WIDTH( 64 ),
    .din1_WIDTH( 64 ),
    .dout_WIDTH( 64 ))
dut_grp_fu_44_ACMP_dmul_1_U(
    .clk( ap_clk ),
    .reset( ap_rst ),
    .din0( grp_fu_44_p0 ),
    .din1( grp_fu_44_p1 ),
    .ce( grp_fu_44_ce ),
    .dout( grp_fu_44_p2 )
);



/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
    if (ap_rst == 1'b1) begin
        ap_CS_fsm <= ap_ST_st1_fsm_0;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

/// assign process. ///
always @(posedge ap_clk)
begin
    if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
        data1_reg_150 <= {{ret_fu_93_p1[ap_const_lv32_3F : ap_const_lv32_20]}};
    end
    if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
        data2_2_reg_155 <= data2_2_fu_107_p1;
    end
    if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
        full_1_reg_135 <= full_1_fu_79_p2;
    end
    if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
        full_reg_130 <= full_fu_60_p2;
    end
    if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0))) begin
        tmp_2_reg_115 <= in_fifo_V_dout;
    end
    if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm))) begin
        tmp_6_reg_120 <= in_fifo_V_dout;
    end
    if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
        tmp_7_reg_125 <= in_fifo_V_dout;
    end
end

/// the next state (ap_NS_fsm) of the state machine. ///
always @ (in_fifo_V_empty_n or out_fifo_V_full_n or ap_CS_fsm)
begin
    if ((~(out_fifo_V_full_n == ap_const_logic_0) & (ap_ST_st13_fsm_12 == ap_CS_fsm))) begin
        ap_NS_fsm = ap_ST_st1_fsm_0;
    end else if (((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(out_fifo_V_full_n == ap_const_logic_0))) begin
        ap_NS_fsm = ap_ST_st13_fsm_12;
    end else if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st12_fsm_11;
    end else if ((ap_ST_st10_fsm_9 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st11_fsm_10;
    end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st10_fsm_9;
    end else if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st9_fsm_8;
    end else if ((ap_ST_st7_fsm_6 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st8_fsm_7;
    end else if ((ap_ST_st6_fsm_5 == ap_CS_fsm)) begin
        ap_NS_fsm = ap_ST_st7_fsm_6;
    end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
        ap_NS_fsm = ap_ST_st6_fsm_5;
    end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
        ap_NS_fsm = ap_ST_st5_fsm_4;
    end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm))) begin
        ap_NS_fsm = ap_ST_st4_fsm_3;
    end else if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0))) begin
        ap_NS_fsm = ap_ST_st3_fsm_2;
    end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
        ap_NS_fsm = ap_ST_st2_fsm_1;
    end else begin
        ap_NS_fsm = ap_CS_fsm;
    end
end

/// in_fifo_V_read assign process. ///
always @ (in_fifo_V_empty_n or ap_CS_fsm)
begin
    if ((((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st1_fsm_0 == ap_CS_fsm)))) begin
        in_fifo_V_read = ap_const_logic_1;
    end else begin
        in_fifo_V_read = ap_const_logic_0;
    end
end

/// out_fifo_V_din assign process. ///
always @ (ap_CS_fsm or data1_reg_150 or tmp_1_fu_111_p1)
begin
    if ((ap_ST_st13_fsm_12 == ap_CS_fsm)) begin
        out_fifo_V_din = tmp_1_fu_111_p1;
    end else if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
        out_fifo_V_din = data1_reg_150;
    end else begin
        out_fifo_V_din = tmp_1_fu_111_p1;
    end
end

/// out_fifo_V_write assign process. ///
always @ (out_fifo_V_full_n or ap_CS_fsm)
begin
    if ((((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(out_fifo_V_full_n == ap_const_logic_0)) | (~(out_fifo_V_full_n == ap_const_logic_0) & (ap_ST_st13_fsm_12 == ap_CS_fsm)))) begin
        out_fifo_V_write = ap_const_logic_1;
    end else begin
        out_fifo_V_write = ap_const_logic_0;
    end
end
assign data2_2_fu_107_p1 = ret_fu_93_p1[15:0];
assign full_1_fu_79_p1 = $signed(in_fifo_V_dout);
assign full_1_fu_79_p2 = (tmp_s_fu_69_p2 + full_1_fu_79_p1);
assign full_fu_60_p1 = $signed(tmp_6_reg_120);
assign full_fu_60_p2 = (tmp_4_fu_51_p2 + full_fu_60_p1);
assign grp_fu_44_ce = ap_const_logic_1;
assign grp_fu_44_p0 = full_reg_130;
assign grp_fu_44_p1 = full_1_reg_135;
assign ret_fu_93_p1 = grp_fu_44_p2;
assign tmp_1_fu_111_p1 = $unsigned(data2_2_reg_155);
assign tmp_3_fu_48_p1 = $unsigned(tmp_2_reg_115);
assign tmp_4_fu_51_p2 = tmp_3_fu_48_p1 << ap_const_lv64_20;
assign tmp_9_fu_66_p1 = $unsigned(tmp_7_reg_125);
assign tmp_s_fu_69_p2 = tmp_9_fu_66_p1 << ap_const_lv64_20;


endmodule //dut

