//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb  3 15:04:41 EST 2014
//
//
// Ports:
// Name                         I/O  size props
// wciS0_SResp                    O     2 reg
// wciS0_SData                    O    32 reg
// wciS0_SThreadBusy              O     1
// wciS0_SFlag                    O     2
// wciS0_Clk                      I     1 clock
// wciS0_MReset_n                 I     1 reset
// wciS0_MCmd                     I     3
// wciS0_MAddrSpace               I     1
// wciS0_MByteEn                  I     4
// wciS0_MAddr                    I    32
// wciS0_MData                    I    32
// wciS0_MFlag                    I     2 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkICAPWorker(wciS0_Clk,
		    wciS0_MReset_n,

		    wciS0_MCmd,

		    wciS0_MAddrSpace,

		    wciS0_MByteEn,

		    wciS0_MAddr,

		    wciS0_MData,

		    wciS0_SResp,

		    wciS0_SData,

		    wciS0_SThreadBusy,

		    wciS0_SFlag,

		    wciS0_MFlag);
  parameter icapPrim = "";
  parameter [0 : 0] hasDebugLogic = 1'b0;
  input  wciS0_Clk;
  input  wciS0_MReset_n;

  // action method wciS0_mCmd
  input  [2 : 0] wciS0_MCmd;

  // action method wciS0_mAddrSpace
  input  wciS0_MAddrSpace;

  // action method wciS0_mByteEn
  input  [3 : 0] wciS0_MByteEn;

  // action method wciS0_mAddr
  input  [31 : 0] wciS0_MAddr;

  // action method wciS0_mData
  input  [31 : 0] wciS0_MData;

  // value method wciS0_sResp
  output [1 : 0] wciS0_SResp;

  // value method wciS0_sData
  output [31 : 0] wciS0_SData;

  // value method wciS0_sThreadBusy
  output wciS0_SThreadBusy;

  // value method wciS0_sFlag
  output [1 : 0] wciS0_SFlag;

  // action method wciS0_mFlag
  input  [1 : 0] wciS0_MFlag;

  // signals for module outputs
  wire [31 : 0] wciS0_SData;
  wire [1 : 0] wciS0_SFlag, wciS0_SResp;
  wire wciS0_SThreadBusy;

  // inlined wires
  wire [71 : 0] wci_wslv_wciReq_wget;
  wire [33 : 0] wci_wslv_respF_x_wire_wget;
  wire [31 : 0] coutF_wDataIn_wget,
		coutF_wDataOut_wget,
		icap_icapIn_1_wget,
		icap_icapOut_1_wget,
		wci_wci_Es_mAddr_w_wget,
		wci_wci_Es_mData_w_wget;
  wire [10 : 0] coutF_rRdPtr_wdCounterCrossing_wget,
		coutF_rWrPtr_wdCounterCrossing_wget;
  wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
  wire [2 : 0] wci_wci_Es_mCmd_w_wget, wci_wslv_wEdge_wget;
  wire cinF_dClear_pw_whas,
       cinF_deq_happened_whas,
       cinF_deq_pw_whas,
       cinF_enq_pw_whas,
       cinF_sClear_pw_whas,
       coutF_pwDequeue_whas,
       coutF_pwEnqueue_whas,
       coutF_rRdPtr_pwDecrement_whas,
       coutF_rRdPtr_pwIncrement_whas,
       coutF_rWrPtr_pwDecrement_whas,
       coutF_rWrPtr_pwIncrement_whas,
       coutF_wDataIn_whas,
       coutF_wDataOut_whas,
       icap_cre_wget,
       icap_cre_whas,
       icap_cwe_wget,
       icap_cwe_whas,
       icap_icapBusy_1_wget,
       icap_icapBusy_1_whas,
       icap_icapCs_1_wget,
       icap_icapCs_1_whas,
       icap_icapIn_1_whas,
       icap_icapOut_1_whas,
       icap_icapRd_1_wget,
       icap_icapRd_1_whas,
       wci_wci_Es_mAddrSpace_w_wget,
       wci_wci_Es_mAddrSpace_w_whas,
       wci_wci_Es_mAddr_w_whas,
       wci_wci_Es_mByteEn_w_whas,
       wci_wci_Es_mCmd_w_whas,
       wci_wci_Es_mData_w_whas,
       wci_wslv_ctlAckReg_1_wget,
       wci_wslv_ctlAckReg_1_whas,
       wci_wslv_reqF_r_clr_whas,
       wci_wslv_reqF_r_deq_whas,
       wci_wslv_reqF_r_enq_whas,
       wci_wslv_respF_dequeueing_whas,
       wci_wslv_respF_enqueueing_whas,
       wci_wslv_respF_x_wire_whas,
       wci_wslv_sFlagReg_1_wget,
       wci_wslv_sFlagReg_1_whas,
       wci_wslv_sThreadBusy_pw_whas,
       wci_wslv_wEdge_whas,
       wci_wslv_wciReq_whas,
       wci_wslv_wci_cfrd_pw_whas,
       wci_wslv_wci_cfwr_pw_whas,
       wci_wslv_wci_ctrl_pw_whas;

  // register cinF_head_wrapped
  reg cinF_head_wrapped;
  wire cinF_head_wrapped_D_IN, cinF_head_wrapped_EN;

  // register cinF_tail_wrapped
  reg cinF_tail_wrapped;
  wire cinF_tail_wrapped_D_IN, cinF_tail_wrapped_EN;

  // register cinS
  reg [31 : 0] cinS;
  wire [31 : 0] cinS_D_IN;
  wire cinS_EN;

  // register coutF_rRdPtr_rdCounter
  reg [10 : 0] coutF_rRdPtr_rdCounter;
  wire [10 : 0] coutF_rRdPtr_rdCounter_D_IN;
  wire coutF_rRdPtr_rdCounter_EN;

  // register coutF_rRdPtr_rdCounterPre
  reg [10 : 0] coutF_rRdPtr_rdCounterPre;
  wire [10 : 0] coutF_rRdPtr_rdCounterPre_D_IN;
  wire coutF_rRdPtr_rdCounterPre_EN;

  // register coutF_rRdPtr_rsCounter
  reg [10 : 0] coutF_rRdPtr_rsCounter;
  wire [10 : 0] coutF_rRdPtr_rsCounter_D_IN;
  wire coutF_rRdPtr_rsCounter_EN;

  // register coutF_rWrPtr_rdCounter
  reg [10 : 0] coutF_rWrPtr_rdCounter;
  wire [10 : 0] coutF_rWrPtr_rdCounter_D_IN;
  wire coutF_rWrPtr_rdCounter_EN;

  // register coutF_rWrPtr_rdCounterPre
  reg [10 : 0] coutF_rWrPtr_rdCounterPre;
  wire [10 : 0] coutF_rWrPtr_rdCounterPre_D_IN;
  wire coutF_rWrPtr_rdCounterPre_EN;

  // register coutF_rWrPtr_rsCounter
  reg [10 : 0] coutF_rWrPtr_rsCounter;
  wire [10 : 0] coutF_rWrPtr_rsCounter_D_IN;
  wire coutF_rWrPtr_rsCounter_EN;

  // register dwRead
  reg [31 : 0] dwRead;
  wire [31 : 0] dwRead_D_IN;
  wire dwRead_EN;

  // register dwWritten
  reg [31 : 0] dwWritten;
  wire [31 : 0] dwWritten_D_IN;
  wire dwWritten_EN;

  // register icapCtrl
  reg [31 : 0] icapCtrl;
  wire [31 : 0] icapCtrl_D_IN;
  wire icapCtrl_EN;

  // register icap_icapBusy
  reg icap_icapBusy;
  wire icap_icapBusy_D_IN, icap_icapBusy_EN;

  // register icap_icapCs
  reg icap_icapCs;
  wire icap_icapCs_D_IN, icap_icapCs_EN;

  // register icap_icapIn
  reg [31 : 0] icap_icapIn;
  wire [31 : 0] icap_icapIn_D_IN;
  wire icap_icapIn_EN;

  // register icap_icapOut
  reg [31 : 0] icap_icapOut;
  wire [31 : 0] icap_icapOut_D_IN;
  wire icap_icapOut_EN;

  // register icap_icapRd
  reg icap_icapRd;
  wire icap_icapRd_D_IN, icap_icapRd_EN;

  // register icap_inCount
  reg [31 : 0] icap_inCount;
  wire [31 : 0] icap_inCount_D_IN;
  wire icap_inCount_EN;

  // register icap_outCount
  reg [31 : 0] icap_outCount;
  wire [31 : 0] icap_outCount_D_IN;
  wire icap_outCount_EN;

  // register wci_wslv_cEdge
  reg [2 : 0] wci_wslv_cEdge;
  wire [2 : 0] wci_wslv_cEdge_D_IN;
  wire wci_wslv_cEdge_EN;

  // register wci_wslv_cState
  reg [2 : 0] wci_wslv_cState;
  wire [2 : 0] wci_wslv_cState_D_IN;
  wire wci_wslv_cState_EN;

  // register wci_wslv_ctlAckReg
  reg wci_wslv_ctlAckReg;
  wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;

  // register wci_wslv_ctlOpActive
  reg wci_wslv_ctlOpActive;
  wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;

  // register wci_wslv_illegalEdge
  reg wci_wslv_illegalEdge;
  wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;

  // register wci_wslv_isReset_isInReset
  reg wci_wslv_isReset_isInReset;
  wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;

  // register wci_wslv_nState
  reg [2 : 0] wci_wslv_nState;
  reg [2 : 0] wci_wslv_nState_D_IN;
  wire wci_wslv_nState_EN;

  // register wci_wslv_reqF_countReg
  reg [1 : 0] wci_wslv_reqF_countReg;
  wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
  wire wci_wslv_reqF_countReg_EN;

  // register wci_wslv_respF_cntr_r
  reg [1 : 0] wci_wslv_respF_cntr_r;
  wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
  wire wci_wslv_respF_cntr_r_EN;

  // register wci_wslv_respF_q_0
  reg [33 : 0] wci_wslv_respF_q_0;
  reg [33 : 0] wci_wslv_respF_q_0_D_IN;
  wire wci_wslv_respF_q_0_EN;

  // register wci_wslv_respF_q_1
  reg [33 : 0] wci_wslv_respF_q_1;
  reg [33 : 0] wci_wslv_respF_q_1_D_IN;
  wire wci_wslv_respF_q_1_EN;

  // register wci_wslv_sFlagReg
  reg wci_wslv_sFlagReg;
  wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;

  // register wci_wslv_sThreadBusy_d
  reg wci_wslv_sThreadBusy_d;
  wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;

  // ports of submodule cd
  wire cd_CLK_OUT, cd_PREEDGE;

  // ports of submodule cinF_dCombinedReset
  wire cinF_dCombinedReset_RST_OUT;

  // ports of submodule cinF_dCrossedsReset
  wire cinF_dCrossedsReset_OUT_RST;

  // ports of submodule cinF_dInReset
  wire cinF_dInReset_VAL;

  // ports of submodule cinF_sCombinedReset
  wire cinF_sCombinedReset_RST_OUT;

  // ports of submodule cinF_sCrosseddReset
  wire cinF_sCrosseddReset_OUT_RST;

  // ports of submodule cinF_sInReset
  wire cinF_sInReset_VAL;

  // ports of submodule coutF_memory
  wire [31 : 0] coutF_memory_DIA, coutF_memory_DIB, coutF_memory_DOB;
  wire [9 : 0] coutF_memory_ADDRA, coutF_memory_ADDRB;
  wire coutF_memory_ENA, coutF_memory_ENB, coutF_memory_WEA, coutF_memory_WEB;

  // ports of submodule cre
  wire cre_dD_OUT, cre_sD_IN, cre_sEN, cre_sRDY;

  // ports of submodule cwe
  wire cwe_dD_OUT, cwe_sD_IN, cwe_sEN, cwe_sRDY;

  // ports of submodule icap_cinF
  wire [31 : 0] icap_cinF_D_IN, icap_cinF_D_OUT;
  wire icap_cinF_CLR,
       icap_cinF_DEQ,
       icap_cinF_EMPTY_N,
       icap_cinF_ENQ,
       icap_cinF_FULL_N;

  // ports of submodule icap_coutF
  wire [31 : 0] icap_coutF_D_IN, icap_coutF_D_OUT;
  wire icap_coutF_CLR,
       icap_coutF_DEQ,
       icap_coutF_EMPTY_N,
       icap_coutF_ENQ,
       icap_coutF_FULL_N;

  // ports of submodule icap_icap
  wire [31 : 0] icap_icap_I, icap_icap_O;
  wire icap_icap_BUSY, icap_icap_CSB, icap_icap_RDWRB;

  // ports of submodule inCnt
  wire [31 : 0] inCnt_dD_OUT, inCnt_sD_IN;
  wire inCnt_sEN, inCnt_sRDY;

  // ports of submodule outCnt
  wire [31 : 0] outCnt_dD_OUT, outCnt_sD_IN;
  wire outCnt_sEN, outCnt_sRDY;

  // ports of submodule slowReset
  wire slowReset_OUT_RST;

  // ports of submodule wci_wslv_reqF
  wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
  wire wci_wslv_reqF_CLR,
       wci_wslv_reqF_DEQ,
       wci_wslv_reqF_EMPTY_N,
       wci_wslv_reqF_ENQ;

  // rule scheduling signals
  wire CAN_FIRE_RL_wci_cfrd,
       WILL_FIRE_RL_cinF_deq_update_head,
       WILL_FIRE_RL_cinF_enq_update_tail,
       WILL_FIRE_RL_icap_read_configuration_data,
       WILL_FIRE_RL_icap_write_configration_data,
       WILL_FIRE_RL_wci_cfrd,
       WILL_FIRE_RL_wci_cfwr,
       WILL_FIRE_RL_wci_ctrl_EiI,
       WILL_FIRE_RL_wci_ctrl_IsO,
       WILL_FIRE_RL_wci_ctrl_OrE,
       WILL_FIRE_RL_wci_wslv_ctl_op_complete,
       WILL_FIRE_RL_wci_wslv_ctl_op_start,
       WILL_FIRE_RL_wci_wslv_respF_both,
       WILL_FIRE_RL_wci_wslv_respF_decCtr,
       WILL_FIRE_RL_wci_wslv_respF_incCtr;

  // inputs to muxes for submodule ports
  reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
  wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
		MUX_wci_wslv_respF_q_1_write_1__VAL_1,
		MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
		MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
  wire [10 : 0] MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1,
		MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1;
  wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2;
  wire MUX_wci_wslv_illegalEdge_write_1__SEL_1,
       MUX_wci_wslv_illegalEdge_write_1__VAL_1,
       MUX_wci_wslv_respF_q_0_write_1__SEL_1,
       MUX_wci_wslv_respF_q_0_write_1__SEL_2,
       MUX_wci_wslv_respF_q_1_write_1__SEL_1,
       MUX_wci_wslv_respF_q_1_write_1__SEL_2;

  // remaining internal signals
  reg [63 : 0] v__h26628, v__h3563, v__h3738, v__h3882;
  reg [31 : 0] v__h26380;
  wire [31 : 0] IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439,
		IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440,
		IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370,
		IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371,
		icapStatus__h26003,
		rdat__h26404,
		rdat__h26410,
		rdat__h26416,
		rdat__h26422,
		x3__h20684;
  wire [10 : 0] coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549,
		x__h16273,
		x__h18575,
		x__h21947,
		x_dReadBin__h20388,
		x_sReadBin__h20385,
		y__h17160,
		y__h19462;
  wire [9 : 0] x2__h21916;
  wire [2 : 0] x__h26497;
  wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
  wire NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599,
       NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590,
       _dfoo1,
       _dfoo3,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542,
       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545,
       coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494,
       coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471,
       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473,
       z__h17204,
       z__h17211,
       z__h17218,
       z__h17225,
       z__h17232,
       z__h17239,
       z__h17246,
       z__h17253,
       z__h17260,
       z__h19506,
       z__h19513,
       z__h19520,
       z__h19527,
       z__h19534,
       z__h19541,
       z__h19548,
       z__h19555,
       z__h19562;

  // value method wciS0_sResp
  assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;

  // value method wciS0_sData
  assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;

  // value method wciS0_sThreadBusy
  assign wciS0_SThreadBusy =
	     wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;

  // value method wciS0_sFlag
  assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;

  // submodule cd
  ClockDiv #(.width(32'd1),
	     .lower(32'd0),
	     .upper(32'd1),
	     .offset(32'd0)) cd(.CLK_IN(wciS0_Clk),
				.RST(wciS0_MReset_n),
				.PREEDGE(cd_PREEDGE),
				.CLK_OUT(cd_CLK_OUT));

  // submodule cinF_dCombinedReset
  ResetEither cinF_dCombinedReset(.A_RST(slowReset_OUT_RST),
				  .B_RST(cinF_dCrossedsReset_OUT_RST),
				  .RST_OUT(cinF_dCombinedReset_RST_OUT));

  // submodule cinF_dCrossedsReset
  SyncReset0 cinF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
				 .OUT_RST(cinF_dCrossedsReset_OUT_RST));

  // submodule cinF_dInReset
  ResetToBool cinF_dInReset(.RST(cinF_dCombinedReset_RST_OUT),
			    .VAL(cinF_dInReset_VAL));

  // submodule cinF_sCombinedReset
  ResetEither cinF_sCombinedReset(.A_RST(wciS0_MReset_n),
				  .B_RST(cinF_sCrosseddReset_OUT_RST),
				  .RST_OUT(cinF_sCombinedReset_RST_OUT));

  // submodule cinF_sCrosseddReset
  SyncReset0 cinF_sCrosseddReset(.IN_RST(slowReset_OUT_RST),
				 .OUT_RST(cinF_sCrosseddReset_OUT_RST));

  // submodule cinF_sInReset
  ResetToBool cinF_sInReset(.RST(cinF_sCombinedReset_RST_OUT),
			    .VAL(cinF_sInReset_VAL));

  // submodule coutF_memory
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) coutF_memory(.CLKA(cd_CLK_OUT),
					   .CLKB(wciS0_Clk),
					   .ADDRA(coutF_memory_ADDRA),
					   .ADDRB(coutF_memory_ADDRB),
					   .DIA(coutF_memory_DIA),
					   .DIB(coutF_memory_DIB),
					   .WEA(coutF_memory_WEA),
					   .WEB(coutF_memory_WEB),
					   .ENA(coutF_memory_ENA),
					   .ENB(coutF_memory_ENB),
					   .DOA(),
					   .DOB(coutF_memory_DOB));

  // submodule cre
  SyncRegister #(.width(32'd1), .init(1'd0)) cre(.sCLK(wciS0_Clk),
						 .dCLK(cd_CLK_OUT),
						 .sRST(wciS0_MReset_n),
						 .sD_IN(cre_sD_IN),
						 .sEN(cre_sEN),
						 .dD_OUT(cre_dD_OUT),
						 .sRDY(cre_sRDY));

  // submodule cwe
  SyncRegister #(.width(32'd1), .init(1'd0)) cwe(.sCLK(wciS0_Clk),
						 .dCLK(cd_CLK_OUT),
						 .sRST(wciS0_MReset_n),
						 .sD_IN(cwe_sD_IN),
						 .sEN(cwe_sEN),
						 .dD_OUT(cwe_dD_OUT),
						 .sRDY(cwe_sRDY));

  // submodule icap_cinF
  FIFO2 #(.width(32'd32), .guarded(32'd1)) icap_cinF(.RST(slowReset_OUT_RST),
						     .CLK(cd_CLK_OUT),
						     .D_IN(icap_cinF_D_IN),
						     .ENQ(icap_cinF_ENQ),
						     .DEQ(icap_cinF_DEQ),
						     .CLR(icap_cinF_CLR),
						     .D_OUT(icap_cinF_D_OUT),
						     .FULL_N(icap_cinF_FULL_N),
						     .EMPTY_N(icap_cinF_EMPTY_N));

  // submodule icap_coutF
  FIFO2 #(.width(32'd32), .guarded(32'd1)) icap_coutF(.RST(slowReset_OUT_RST),
						      .CLK(cd_CLK_OUT),
						      .D_IN(icap_coutF_D_IN),
						      .ENQ(icap_coutF_ENQ),
						      .DEQ(icap_coutF_DEQ),
						      .CLR(icap_coutF_CLR),
						      .D_OUT(icap_coutF_D_OUT),
						      .FULL_N(icap_coutF_FULL_N),
						      .EMPTY_N(icap_coutF_EMPTY_N));

  // submodule icap_icap
  ICAP_VIRTEX6 #(.ICAP_WIDTH("X32")) icap_icap(.CLK(cd_CLK_OUT),
					       .CSB(icap_icap_CSB),
					       .I(icap_icap_I),
					       .RDWRB(icap_icap_RDWRB),
					       .O(icap_icap_O),
					       .BUSY(icap_icap_BUSY));

  // submodule inCnt
  SyncRegister #(.width(32'd32), .init(32'd0)) inCnt(.sCLK(cd_CLK_OUT),
						     .dCLK(wciS0_Clk),
						     .sRST(slowReset_OUT_RST),
						     .sD_IN(inCnt_sD_IN),
						     .sEN(inCnt_sEN),
						     .dD_OUT(inCnt_dD_OUT),
						     .sRDY(inCnt_sRDY));

  // submodule outCnt
  SyncRegister #(.width(32'd32), .init(32'd0)) outCnt(.sCLK(cd_CLK_OUT),
						      .dCLK(wciS0_Clk),
						      .sRST(slowReset_OUT_RST),
						      .sD_IN(outCnt_sD_IN),
						      .sEN(outCnt_sEN),
						      .dD_OUT(outCnt_dD_OUT),
						      .sRDY(outCnt_sRDY));

  // submodule slowReset
  SyncResetA #(.RSTDELAY(32'd1)) slowReset(.CLK(cd_CLK_OUT),
					   .IN_RST(wciS0_MReset_n),
					   .OUT_RST(slowReset_OUT_RST));

  // submodule wci_wslv_reqF
  SizedFIFO #(.p1width(32'd72),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
					     .CLK(wciS0_Clk),
					     .D_IN(wci_wslv_reqF_D_IN),
					     .ENQ(wci_wslv_reqF_ENQ),
					     .DEQ(wci_wslv_reqF_DEQ),
					     .CLR(wci_wslv_reqF_CLR),
					     .D_OUT(wci_wslv_reqF_D_OUT),
					     .FULL_N(),
					     .EMPTY_N(wci_wslv_reqF_EMPTY_N));

  // rule RL_wci_cfwr
  assign WILL_FIRE_RL_wci_cfwr =
	     NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 &&
	     wci_wslv_wci_cfwr_pw_whas &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wci_wslv_ctl_op_start
  assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
	     wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wci_ctrl_IsO
  assign WILL_FIRE_RL_wci_ctrl_IsO =
	     wci_wslv_wci_ctrl_pw_whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd1 &&
	     wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;

  // rule RL_wci_ctrl_EiI
  assign WILL_FIRE_RL_wci_ctrl_EiI =
	     wci_wslv_wci_ctrl_pw_whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd0 &&
	     wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;

  // rule RL_wci_ctrl_OrE
  assign WILL_FIRE_RL_wci_ctrl_OrE =
	     wci_wslv_wci_ctrl_pw_whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd2 &&
	     wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;

  // rule RL_wci_wslv_ctl_op_complete
  assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
	     wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
	     wci_wslv_ctlAckReg ;

  // rule RL_icap_write_configration_data
  assign WILL_FIRE_RL_icap_write_configration_data =
	     icap_cinF_EMPTY_N && cwe_dD_OUT && !cre_dD_OUT ;

  // rule RL_icap_read_configuration_data
  assign WILL_FIRE_RL_icap_read_configuration_data =
	     (icap_icapBusy || icap_coutF_FULL_N) && cre_dD_OUT &&
	     !cwe_dD_OUT ;

  // rule RL_cinF_enq_update_tail
  assign WILL_FIRE_RL_cinF_enq_update_tail =
	     !cinF_sInReset_VAL && cinF_enq_pw_whas ;

  // rule RL_cinF_deq_update_head
  assign WILL_FIRE_RL_cinF_deq_update_head =
	     !cinF_dInReset_VAL && cinF_deq_pw_whas ;

  // rule RL_wci_cfrd
  assign CAN_FIRE_RL_wci_cfrd =
	     wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
	     (wci_wslv_reqF_D_OUT[63:32] != 32'h0000000C ||
	      NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599) &&
	     wci_wslv_wci_cfrd_pw_whas ;
  assign WILL_FIRE_RL_wci_cfrd =
	     CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wci_wslv_respF_incCtr
  assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
	     wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
	     !(wci_wslv_respF_cntr_r != 2'd0) ;

  // rule RL_wci_wslv_respF_decCtr
  assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
	     wci_wslv_respF_cntr_r != 2'd0 &&
	     !wci_wslv_respF_enqueueing_whas ;

  // rule RL_wci_wslv_respF_both
  assign WILL_FIRE_RL_wci_wslv_respF_both =
	     wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
	     wci_wslv_respF_enqueueing_whas ;

  // inputs to muxes for submodule ports
  assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
	      wci_wslv_cState != 3'd3 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
	      wci_wslv_cState != 3'd2 &&
	      wci_wslv_cState != 3'd1 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
  assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
	     WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
  assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_cntr_r == 2'd0 ;
  assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
	     WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
  assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_cntr_r == 2'd1 ;
  assign MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1 =
	     (~coutF_rRdPtr_rsCounter[IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440[3:0]]) ?
	       coutF_rRdPtr_rsCounter | x__h18575 :
	       coutF_rRdPtr_rsCounter & y__h19462 ;
  assign MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1 =
	     (~coutF_rWrPtr_rsCounter[IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371[3:0]]) ?
	       coutF_rWrPtr_rsCounter | x__h16273 :
	       coutF_rWrPtr_rsCounter & y__h17160 ;
  assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
	     wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
	     wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
	     wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
  assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
	     wci_wslv_respF_cntr_r + 2'd1 ;
  assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
	     (wci_wslv_respF_cntr_r == 2'd1) ?
	       MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
	       wci_wslv_respF_q_1 ;
  always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
	  MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
	  WILL_FIRE_RL_wci_cfrd or
	  MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_wci_wslv_ctl_op_complete:
	  MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
	      MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
      WILL_FIRE_RL_wci_cfrd:
	  MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
	      MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
      WILL_FIRE_RL_wci_cfwr:
	  MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
      default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
	     (wci_wslv_respF_cntr_r == 2'd2) ?
	       MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
	       34'h0AAAAAAAA ;
  assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
	     wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
  assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, v__h26380 } ;

  // inlined wires
  assign wci_wslv_wciReq_wget =
	     { wciS0_MCmd,
	       wciS0_MAddrSpace,
	       wciS0_MByteEn,
	       wciS0_MAddr,
	       wciS0_MData } ;
  assign wci_wslv_wciReq_whas = 1'd1 ;
  assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
  assign wci_wslv_respF_x_wire_whas =
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
	     WILL_FIRE_RL_wci_cfwr ;
  assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
  assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
  assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
  assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
  assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
  assign wci_wslv_ctlAckReg_1_whas =
	     WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
	     WILL_FIRE_RL_wci_ctrl_EiI ;
  assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
  assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
  assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
  assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
  assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
  assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
  assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
  assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
  assign wci_wci_Es_mData_w_wget = wciS0_MData ;
  assign wci_wci_Es_mData_w_whas = 1'd1 ;
  assign icap_icapCs_1_wget = 1'd1 ;
  assign icap_icapCs_1_whas =
	     WILL_FIRE_RL_icap_read_configuration_data ||
	     WILL_FIRE_RL_icap_write_configration_data ;
  assign icap_icapRd_1_wget = !WILL_FIRE_RL_icap_write_configration_data ;
  assign icap_icapRd_1_whas =
	     WILL_FIRE_RL_icap_write_configration_data ||
	     WILL_FIRE_RL_icap_read_configuration_data ;
  assign icap_icapIn_1_wget =
	     { icap_cinF_D_OUT[24],
	       icap_cinF_D_OUT[25],
	       icap_cinF_D_OUT[26],
	       icap_cinF_D_OUT[27],
	       icap_cinF_D_OUT[28],
	       icap_cinF_D_OUT[29],
	       icap_cinF_D_OUT[30],
	       icap_cinF_D_OUT[31],
	       icap_cinF_D_OUT[16],
	       icap_cinF_D_OUT[17],
	       icap_cinF_D_OUT[18],
	       icap_cinF_D_OUT[19],
	       icap_cinF_D_OUT[20],
	       icap_cinF_D_OUT[21],
	       icap_cinF_D_OUT[22],
	       icap_cinF_D_OUT[23],
	       icap_cinF_D_OUT[8],
	       icap_cinF_D_OUT[9],
	       icap_cinF_D_OUT[10],
	       icap_cinF_D_OUT[11],
	       icap_cinF_D_OUT[12],
	       icap_cinF_D_OUT[13],
	       icap_cinF_D_OUT[14],
	       icap_cinF_D_OUT[15],
	       icap_cinF_D_OUT[0],
	       icap_cinF_D_OUT[1],
	       icap_cinF_D_OUT[2],
	       icap_cinF_D_OUT[3],
	       icap_cinF_D_OUT[4],
	       icap_cinF_D_OUT[5],
	       icap_cinF_D_OUT[6],
	       icap_cinF_D_OUT[7] } ;
  assign icap_icapIn_1_whas = WILL_FIRE_RL_icap_write_configration_data ;
  assign icap_icapOut_1_wget = icap_icap_O ;
  assign icap_icapOut_1_whas = 1'd1 ;
  assign icap_icapBusy_1_wget = icap_icap_BUSY ;
  assign icap_icapBusy_1_whas = 1'd1 ;
  assign icap_cwe_wget = cwe_dD_OUT ;
  assign icap_cwe_whas = 1'd1 ;
  assign icap_cre_wget = cre_dD_OUT ;
  assign icap_cre_whas = 1'd1 ;
  assign coutF_wDataIn_wget = icap_coutF_D_OUT ;
  assign coutF_wDataIn_whas = coutF_pwEnqueue_whas ;
  assign coutF_wDataOut_wget = coutF_memory_DOB ;
  assign coutF_wDataOut_whas = 1'd1 ;
  assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
  assign wci_wslv_reqF_r_deq_whas =
	     WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_start ;
  assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
  assign wci_wslv_respF_enqueueing_whas =
	     WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
  assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
  assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
  assign wci_wslv_wci_cfwr_pw_whas =
	     wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
	     wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
  assign wci_wslv_wci_cfrd_pw_whas =
	     wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
	     wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
  assign wci_wslv_wci_ctrl_pw_whas =
	     wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
	     wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
  assign cinF_enq_pw_whas =
	     WILL_FIRE_RL_wci_cfwr &&
	     wci_wslv_reqF_D_OUT[63:32] == 32'h00000008 ;
  assign cinF_deq_pw_whas =
	     cinF_head_wrapped != cinF_tail_wrapped && !cinF_dInReset_VAL &&
	     icap_cinF_FULL_N ;
  assign cinF_sClear_pw_whas = 1'b0 ;
  assign cinF_dClear_pw_whas = 1'b0 ;
  assign cinF_deq_happened_whas = 1'b0 ;
  assign coutF_rWrPtr_pwIncrement_whas = coutF_pwEnqueue_whas ;
  assign coutF_rWrPtr_pwDecrement_whas = 1'b0 ;
  assign coutF_rRdPtr_pwIncrement_whas = coutF_pwDequeue_whas ;
  assign coutF_rRdPtr_pwDecrement_whas = 1'b0 ;
  assign coutF_pwDequeue_whas =
	     WILL_FIRE_RL_wci_cfrd &&
	     wci_wslv_reqF_D_OUT[63:32] == 32'h0000000C ;
  assign coutF_pwEnqueue_whas =
	     coutF_rWrPtr_rsCounter !=
	     { coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[10] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[9] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[8] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[7] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[6] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[5] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[4] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[3] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[2] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[1] ^
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549[0] } &&
	     icap_coutF_EMPTY_N ;
  assign coutF_rWrPtr_wdCounterCrossing_wget = coutF_rWrPtr_rsCounter ;
  assign coutF_rRdPtr_wdCounterCrossing_wget = coutF_rRdPtr_rsCounter ;

  // register cinF_head_wrapped
  assign cinF_head_wrapped_D_IN =
	     WILL_FIRE_RL_cinF_deq_update_head && !cinF_head_wrapped ;
  assign cinF_head_wrapped_EN =
	     WILL_FIRE_RL_cinF_deq_update_head || cinF_dInReset_VAL ;

  // register cinF_tail_wrapped
  assign cinF_tail_wrapped_D_IN =
	     WILL_FIRE_RL_cinF_enq_update_tail && !cinF_tail_wrapped ;
  assign cinF_tail_wrapped_EN =
	     WILL_FIRE_RL_cinF_enq_update_tail || cinF_sInReset_VAL ;

  // register cinS
  assign cinS_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
  assign cinS_EN = cinF_enq_pw_whas ;

  // register coutF_rRdPtr_rdCounter
  assign coutF_rRdPtr_rdCounter_D_IN = coutF_rRdPtr_rdCounterPre ;
  assign coutF_rRdPtr_rdCounter_EN = 1'd1 ;

  // register coutF_rRdPtr_rdCounterPre
  assign coutF_rRdPtr_rdCounterPre_D_IN = coutF_rRdPtr_rsCounter ;
  assign coutF_rRdPtr_rdCounterPre_EN = 1'd1 ;

  // register coutF_rRdPtr_rsCounter
  assign coutF_rRdPtr_rsCounter_D_IN =
	     MUX_coutF_rRdPtr_rsCounter_write_1__VAL_1 ;
  assign coutF_rRdPtr_rsCounter_EN = coutF_pwDequeue_whas ;

  // register coutF_rWrPtr_rdCounter
  assign coutF_rWrPtr_rdCounter_D_IN = coutF_rWrPtr_rdCounterPre ;
  assign coutF_rWrPtr_rdCounter_EN = 1'd1 ;

  // register coutF_rWrPtr_rdCounterPre
  assign coutF_rWrPtr_rdCounterPre_D_IN = coutF_rWrPtr_rsCounter ;
  assign coutF_rWrPtr_rdCounterPre_EN = 1'd1 ;

  // register coutF_rWrPtr_rsCounter
  assign coutF_rWrPtr_rsCounter_D_IN =
	     MUX_coutF_rWrPtr_rsCounter_write_1__VAL_1 ;
  assign coutF_rWrPtr_rsCounter_EN = coutF_pwEnqueue_whas ;

  // register dwRead
  assign dwRead_D_IN = 32'h0 ;
  assign dwRead_EN = 1'b0 ;

  // register dwWritten
  assign dwWritten_D_IN = 32'h0 ;
  assign dwWritten_EN = 1'b0 ;

  // register icapCtrl
  assign icapCtrl_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
  assign icapCtrl_EN =
	     WILL_FIRE_RL_wci_cfwr &&
	     wci_wslv_reqF_D_OUT[63:32] == 32'h00000004 ;

  // register icap_icapBusy
  assign icap_icapBusy_D_IN = icap_icap_BUSY ;
  assign icap_icapBusy_EN = 1'd1 ;

  // register icap_icapCs
  assign icap_icapCs_D_IN = icap_icapCs_1_whas ;
  assign icap_icapCs_EN = 1'd1 ;

  // register icap_icapIn
  assign icap_icapIn_D_IN =
	     WILL_FIRE_RL_icap_write_configration_data ?
	       icap_icapIn_1_wget :
	       32'hFFFFFFFF ;
  assign icap_icapIn_EN = 1'd1 ;

  // register icap_icapOut
  assign icap_icapOut_D_IN = icap_icap_O ;
  assign icap_icapOut_EN = 1'd1 ;

  // register icap_icapRd
  assign icap_icapRd_D_IN =
	     icap_icapRd_1_whas &&
	     !WILL_FIRE_RL_icap_write_configration_data ;
  assign icap_icapRd_EN = 1'd1 ;

  // register icap_inCount
  assign icap_inCount_D_IN = icap_inCount + 32'd1 ;
  assign icap_inCount_EN = WILL_FIRE_RL_icap_write_configration_data ;

  // register icap_outCount
  assign icap_outCount_D_IN = icap_outCount + 32'd1 ;
  assign icap_outCount_EN =
	     WILL_FIRE_RL_icap_read_configuration_data && !icap_icapBusy ;

  // register wci_wslv_cEdge
  assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
  assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;

  // register wci_wslv_cState
  assign wci_wslv_cState_D_IN = wci_wslv_nState ;
  assign wci_wslv_cState_EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;

  // register wci_wslv_ctlAckReg
  assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
  assign wci_wslv_ctlAckReg_EN = 1'd1 ;

  // register wci_wslv_ctlOpActive
  assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
  assign wci_wslv_ctlOpActive_EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_start ;

  // register wci_wslv_illegalEdge
  assign wci_wslv_illegalEdge_D_IN =
	     MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
	     MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
  assign wci_wslv_illegalEdge_EN =
	     MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;

  // register wci_wslv_isReset_isInReset
  assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
  assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;

  // register wci_wslv_nState
  always@(wci_wslv_reqF_D_OUT)
  begin
    case (wci_wslv_reqF_D_OUT[36:34])
      3'd0: wci_wslv_nState_D_IN = 3'd1;
      3'd1: wci_wslv_nState_D_IN = 3'd2;
      3'd2: wci_wslv_nState_D_IN = 3'd3;
      default: wci_wslv_nState_D_IN = 3'd0;
    endcase
  end
  assign wci_wslv_nState_EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     (wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
	      (wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
	      wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
	      (wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
	       wci_wslv_cState == 3'd1)) ;

  // register wci_wslv_reqF_countReg
  assign wci_wslv_reqF_countReg_D_IN =
	     (wci_wslv_wciReq_wget[71:69] != 3'd0) ?
	       wci_wslv_reqF_countReg + 2'd1 :
	       wci_wslv_reqF_countReg - 2'd1 ;
  assign wci_wslv_reqF_countReg_EN =
	     (wci_wslv_wciReq_wget[71:69] != 3'd0) !=
	     wci_wslv_reqF_r_deq_whas ;

  // register wci_wslv_respF_cntr_r
  assign wci_wslv_respF_cntr_r_D_IN =
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ?
	       wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
	       MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
  assign wci_wslv_respF_cntr_r_EN =
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ||
	     WILL_FIRE_RL_wci_wslv_respF_incCtr ;

  // register wci_wslv_respF_q_0
  always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
	  MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
	  MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
	  MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
	  WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_wci_wslv_respF_q_0_write_1__SEL_1:
	  wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
      MUX_wci_wslv_respF_q_0_write_1__SEL_2:
	  wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
      WILL_FIRE_RL_wci_wslv_respF_decCtr:
	  wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
      default: wci_wslv_respF_q_0_D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wci_wslv_respF_q_0_EN =
	     WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_cntr_r == 2'd0 ||
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ;

  // register wci_wslv_respF_q_1
  always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
	  MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
	  MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
	  MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
	  WILL_FIRE_RL_wci_wslv_respF_decCtr)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_wci_wslv_respF_q_1_write_1__SEL_1:
	  wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
      MUX_wci_wslv_respF_q_1_write_1__SEL_2:
	  wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
      WILL_FIRE_RL_wci_wslv_respF_decCtr:
	  wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
      default: wci_wslv_respF_q_1_D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wci_wslv_respF_q_1_EN =
	     WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_cntr_r == 2'd1 ||
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ;

  // register wci_wslv_sFlagReg
  assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
  assign wci_wslv_sFlagReg_EN = 1'd1 ;

  // register wci_wslv_sThreadBusy_d
  assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
  assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;

  // submodule coutF_memory
  assign coutF_memory_ADDRA =
	     { coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473,
	       coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 ^
	       coutF_rWrPtr_rsCounter[0] } ;
  assign coutF_memory_ADDRB =
	     coutF_pwDequeue_whas ? x__h21947[9:0] : x2__h21916 ;
  assign coutF_memory_DIA = x3__h20684 ;
  assign coutF_memory_DIB = 32'hAAAAAAAA /* unspecified value */  ;
  assign coutF_memory_WEA = coutF_pwEnqueue_whas ;
  assign coutF_memory_WEB = 1'd0 ;
  assign coutF_memory_ENA = 1'd1 ;
  assign coutF_memory_ENB = 1'd1 ;

  // submodule cre
  assign cre_sD_IN = icapCtrl[1] ;
  assign cre_sEN = cwe_sRDY && cre_sRDY && wci_wslv_cState == 3'd2 ;

  // submodule cwe
  assign cwe_sD_IN = icapCtrl[0] ;
  assign cwe_sEN = cwe_sRDY && cre_sRDY && wci_wslv_cState == 3'd2 ;

  // submodule icap_cinF
  assign icap_cinF_D_IN = cinS ;
  assign icap_cinF_ENQ = cinF_deq_pw_whas ;
  assign icap_cinF_DEQ = WILL_FIRE_RL_icap_write_configration_data ;
  assign icap_cinF_CLR = 1'b0 ;

  // submodule icap_coutF
  assign icap_coutF_D_IN =
	     { icap_icapOut[24],
	       icap_icapOut[25],
	       icap_icapOut[26],
	       icap_icapOut[27],
	       icap_icapOut[28],
	       icap_icapOut[29],
	       icap_icapOut[30],
	       icap_icapOut[31],
	       icap_icapOut[16],
	       icap_icapOut[17],
	       icap_icapOut[18],
	       icap_icapOut[19],
	       icap_icapOut[20],
	       icap_icapOut[21],
	       icap_icapOut[22],
	       icap_icapOut[23],
	       icap_icapOut[8],
	       icap_icapOut[9],
	       icap_icapOut[10],
	       icap_icapOut[11],
	       icap_icapOut[12],
	       icap_icapOut[13],
	       icap_icapOut[14],
	       icap_icapOut[15],
	       icap_icapOut[0],
	       icap_icapOut[1],
	       icap_icapOut[2],
	       icap_icapOut[3],
	       icap_icapOut[4],
	       icap_icapOut[5],
	       icap_icapOut[6],
	       icap_icapOut[7] } ;
  assign icap_coutF_ENQ =
	     WILL_FIRE_RL_icap_read_configuration_data && !icap_icapBusy ;
  assign icap_coutF_DEQ = coutF_pwEnqueue_whas ;
  assign icap_coutF_CLR = 1'b0 ;

  // submodule icap_icap
  assign icap_icap_CSB = !icap_icapCs ;
  assign icap_icap_I = icap_icapIn ;
  assign icap_icap_RDWRB = icap_icapRd ;

  // submodule inCnt
  assign inCnt_sD_IN = icap_inCount ;
  assign inCnt_sEN = inCnt_sRDY ;

  // submodule outCnt
  assign outCnt_sD_IN = icap_outCount ;
  assign outCnt_sEN = outCnt_sRDY ;

  // submodule wci_wslv_reqF
  assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
  assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
  assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
  assign wci_wslv_reqF_CLR = 1'b0 ;

  // remaining internal signals
  assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 =
	     (coutF_rRdPtr_rsCounter[0] || coutF_rRdPtr_rsCounter[1] ||
	      coutF_rRdPtr_rsCounter[2] ||
	      coutF_rRdPtr_rsCounter[3] ||
	      coutF_rRdPtr_rsCounter[4] ||
	      coutF_rRdPtr_rsCounter[5] ||
	      coutF_rRdPtr_rsCounter[6] ||
	      coutF_rRdPtr_rsCounter[7] ||
	      coutF_rRdPtr_rsCounter[8] ||
	      coutF_rRdPtr_rsCounter[9]) ?
	       (coutF_rRdPtr_rsCounter[0] ?
		  32'd1 :
		  (coutF_rRdPtr_rsCounter[1] ?
		     32'd2 :
		     (coutF_rRdPtr_rsCounter[2] ?
			32'd3 :
			(coutF_rRdPtr_rsCounter[3] ?
			   32'd4 :
			   (coutF_rRdPtr_rsCounter[4] ?
			      32'd5 :
			      (coutF_rRdPtr_rsCounter[5] ?
				 32'd6 :
				 (coutF_rRdPtr_rsCounter[6] ?
				    32'd7 :
				    (coutF_rRdPtr_rsCounter[7] ?
				       32'd8 :
				       (coutF_rRdPtr_rsCounter[8] ?
					  32'd9 :
					  (coutF_rRdPtr_rsCounter[9] ?
					     32'd10 :
					     (coutF_rRdPtr_rsCounter[10] ?
						32'd11 :
						32'd12))))))))))) :
	       32'd10 ;
  assign IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 =
	     coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 ?
	       IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_OR_coutF_ETC___d439 :
	       32'd0 ;
  assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 =
	     (coutF_rWrPtr_rsCounter[0] || coutF_rWrPtr_rsCounter[1] ||
	      coutF_rWrPtr_rsCounter[2] ||
	      coutF_rWrPtr_rsCounter[3] ||
	      coutF_rWrPtr_rsCounter[4] ||
	      coutF_rWrPtr_rsCounter[5] ||
	      coutF_rWrPtr_rsCounter[6] ||
	      coutF_rWrPtr_rsCounter[7] ||
	      coutF_rWrPtr_rsCounter[8] ||
	      coutF_rWrPtr_rsCounter[9]) ?
	       (coutF_rWrPtr_rsCounter[0] ?
		  32'd1 :
		  (coutF_rWrPtr_rsCounter[1] ?
		     32'd2 :
		     (coutF_rWrPtr_rsCounter[2] ?
			32'd3 :
			(coutF_rWrPtr_rsCounter[3] ?
			   32'd4 :
			   (coutF_rWrPtr_rsCounter[4] ?
			      32'd5 :
			      (coutF_rWrPtr_rsCounter[5] ?
				 32'd6 :
				 (coutF_rWrPtr_rsCounter[6] ?
				    32'd7 :
				    (coutF_rWrPtr_rsCounter[7] ?
				       32'd8 :
				       (coutF_rWrPtr_rsCounter[8] ?
					  32'd9 :
					  (coutF_rWrPtr_rsCounter[9] ?
					     32'd10 :
					     (coutF_rWrPtr_rsCounter[10] ?
						32'd11 :
						32'd12))))))))))) :
	       32'd10 ;
  assign IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 =
	     coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 ?
	       IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_OR_coutF_ETC___d370 :
	       32'd0 ;
  assign NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599 =
	     coutF_rRdPtr_rsCounter != coutF_rWrPtr_rdCounter ;
  assign NOT_wci_wslv_respF_cntr_r_8_EQ_2_1_2_AND_wci_w_ETC___d590 =
	     wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
	     (wci_wslv_reqF_D_OUT[63:32] != 32'h00000008 ||
	      cinF_head_wrapped == cinF_tail_wrapped && !cinF_sInReset_VAL &&
	      cd_PREEDGE) ;
  assign _dfoo1 =
	     wci_wslv_respF_cntr_r != 2'd2 ||
	     wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
  assign _dfoo3 =
	     wci_wslv_respF_cntr_r != 2'd1 ||
	     wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_CONCAT_cou_ETC___d549 =
	     x_dReadBin__h20388 + 11'd512 ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 =
	     coutF_rRdPtr_rdCounter[10] ^ coutF_rRdPtr_rdCounter[9] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525 ^
	     coutF_rRdPtr_rdCounter[8] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527 ^
	     coutF_rRdPtr_rdCounter[7] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530 ^
	     coutF_rRdPtr_rdCounter[6] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532 ^
	     coutF_rRdPtr_rdCounter[5] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535 ^
	     coutF_rRdPtr_rdCounter[4] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537 ^
	     coutF_rRdPtr_rdCounter[3] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540 ^
	     coutF_rRdPtr_rdCounter[2] ;
  assign coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 =
	     coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542 ^
	     coutF_rRdPtr_rdCounter[1] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_coutF_r_ETC___d418 =
	     z__h19562 ^ coutF_rRdPtr_rsCounter[10] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 =
	     coutF_rRdPtr_rsCounter[10] ^ coutF_rRdPtr_rsCounter[9] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481 ^
	     coutF_rRdPtr_rsCounter[8] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482 ^
	     coutF_rRdPtr_rsCounter[7] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484 ^
	     coutF_rRdPtr_rsCounter[6] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485 ^
	     coutF_rRdPtr_rsCounter[5] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487 ^
	     coutF_rRdPtr_rsCounter[4] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488 ^
	     coutF_rRdPtr_rsCounter[3] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490 ^
	     coutF_rRdPtr_rsCounter[2] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491 ^
	     coutF_rRdPtr_rsCounter[1] ;
  assign coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 =
	     coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493 ^
	     coutF_rRdPtr_rsCounter[0] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_coutF_r_ETC___d349 =
	     z__h17260 ^ coutF_rWrPtr_rsCounter[10] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 =
	     coutF_rWrPtr_rsCounter[10] ^ coutF_rWrPtr_rsCounter[9] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d461 ^
	     coutF_rWrPtr_rsCounter[8] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d462 ^
	     coutF_rWrPtr_rsCounter[7] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d464 ^
	     coutF_rWrPtr_rsCounter[6] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d465 ^
	     coutF_rWrPtr_rsCounter[5] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d467 ^
	     coutF_rWrPtr_rsCounter[4] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d468 ^
	     coutF_rWrPtr_rsCounter[3] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d470 ^
	     coutF_rWrPtr_rsCounter[2] ;
  assign coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d473 =
	     coutF_rWrPtr_rsCounter_22_BIT_10_48_XOR_coutF__ETC___d471 ^
	     coutF_rWrPtr_rsCounter[1] ;
  assign icapStatus__h26003 = { 29'd0, x__h26497 } ;
  assign rdat__h26404 = hasDebugLogic ? dwWritten : 32'd0 ;
  assign rdat__h26410 = hasDebugLogic ? dwRead : 32'd0 ;
  assign rdat__h26416 = hasDebugLogic ? inCnt_dD_OUT : 32'd0 ;
  assign rdat__h26422 = hasDebugLogic ? outCnt_dD_OUT : 32'd0 ;
  assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
	     wci_wslv_respF_cntr_r - 2'd1 ;
  assign x2__h21916 =
	     { coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ;
  assign x3__h20684 = coutF_pwEnqueue_whas ? icap_coutF_D_OUT : 32'd0 ;
  assign x__h16273 =
	     11'd1 <<
	     IF_coutF_rWrPtr_rsCounter_22_BIT_0_29_XOR_cout_ETC___d371 ;
  assign x__h18575 =
	     11'd1 <<
	     IF_coutF_rRdPtr_rsCounter_91_BIT_0_98_XOR_cout_ETC___d440 ;
  assign x__h21947 = x_sReadBin__h20385 + 11'd1 ;
  assign x__h26497 =
	     { NOT_coutF_rRdPtr_rsCounter_91_EQ_coutF_rWrPtr__ETC___d599,
	       icapCtrl[1:0] } ;
  assign x_dReadBin__h20388 =
	     { coutF_rRdPtr_rdCounter[10],
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d525,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d527,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d530,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d532,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d535,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d537,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d540,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d542,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545,
	       coutF_rRdPtr_rdCounter_22_BIT_10_23_XOR_coutF__ETC___d545 ^
	       coutF_rRdPtr_rdCounter[0] } ;
  assign x_sReadBin__h20385 =
	     { coutF_rRdPtr_rsCounter[10],
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d481,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d482,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d484,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d485,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d487,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d488,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d490,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d491,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d493,
	       coutF_rRdPtr_rsCounter_91_BIT_10_17_XOR_coutF__ETC___d494 } ;
  assign y__h17160 = ~x__h16273 ;
  assign y__h19462 = ~x__h18575 ;
  assign z__h17204 = coutF_rWrPtr_rsCounter[0] ^ coutF_rWrPtr_rsCounter[1] ;
  assign z__h17211 = z__h17204 ^ coutF_rWrPtr_rsCounter[2] ;
  assign z__h17218 = z__h17211 ^ coutF_rWrPtr_rsCounter[3] ;
  assign z__h17225 = z__h17218 ^ coutF_rWrPtr_rsCounter[4] ;
  assign z__h17232 = z__h17225 ^ coutF_rWrPtr_rsCounter[5] ;
  assign z__h17239 = z__h17232 ^ coutF_rWrPtr_rsCounter[6] ;
  assign z__h17246 = z__h17239 ^ coutF_rWrPtr_rsCounter[7] ;
  assign z__h17253 = z__h17246 ^ coutF_rWrPtr_rsCounter[8] ;
  assign z__h17260 = z__h17253 ^ coutF_rWrPtr_rsCounter[9] ;
  assign z__h19506 = coutF_rRdPtr_rsCounter[0] ^ coutF_rRdPtr_rsCounter[1] ;
  assign z__h19513 = z__h19506 ^ coutF_rRdPtr_rsCounter[2] ;
  assign z__h19520 = z__h19513 ^ coutF_rRdPtr_rsCounter[3] ;
  assign z__h19527 = z__h19520 ^ coutF_rRdPtr_rsCounter[4] ;
  assign z__h19534 = z__h19527 ^ coutF_rRdPtr_rsCounter[5] ;
  assign z__h19541 = z__h19534 ^ coutF_rRdPtr_rsCounter[6] ;
  assign z__h19548 = z__h19541 ^ coutF_rRdPtr_rsCounter[7] ;
  assign z__h19555 = z__h19548 ^ coutF_rRdPtr_rsCounter[8] ;
  assign z__h19562 = z__h19555 ^ coutF_rRdPtr_rsCounter[9] ;
  always@(wci_wslv_reqF_D_OUT or
	  icapStatus__h26003 or
	  icapCtrl or
	  coutF_memory_DOB or
	  rdat__h26404 or rdat__h26410 or rdat__h26416 or rdat__h26422)
  begin
    case (wci_wslv_reqF_D_OUT[63:32])
      32'h0: v__h26380 = icapStatus__h26003;
      32'h00000004: v__h26380 = icapCtrl;
      32'h0000000C: v__h26380 = coutF_memory_DOB;
      32'h00000040: v__h26380 = rdat__h26404;
      32'h00000044: v__h26380 = rdat__h26410;
      32'h00000048: v__h26380 = rdat__h26416;
      32'h0000004C: v__h26380 = rdat__h26422;
      default: v__h26380 = 32'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge wciS0_Clk)
  begin
    if (wciS0_MReset_n == `BSV_RESET_VALUE)
      begin
        cinF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
	dwRead <= `BSV_ASSIGNMENT_DELAY 32'd0;
	dwWritten <= `BSV_ASSIGNMENT_DELAY 32'd0;
	icapCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0;
	wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
	wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
	wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
	wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
	wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
	wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
      end
    else
      begin
        if (cinF_tail_wrapped_EN)
	  cinF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY cinF_tail_wrapped_D_IN;
	if (dwRead_EN) dwRead <= `BSV_ASSIGNMENT_DELAY dwRead_D_IN;
	if (dwWritten_EN) dwWritten <= `BSV_ASSIGNMENT_DELAY dwWritten_D_IN;
	if (icapCtrl_EN) icapCtrl <= `BSV_ASSIGNMENT_DELAY icapCtrl_D_IN;
	if (wci_wslv_cEdge_EN)
	  wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
	if (wci_wslv_cState_EN)
	  wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
	if (wci_wslv_ctlAckReg_EN)
	  wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
	if (wci_wslv_ctlOpActive_EN)
	  wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_ctlOpActive_D_IN;
	if (wci_wslv_illegalEdge_EN)
	  wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_illegalEdge_D_IN;
	if (wci_wslv_nState_EN)
	  wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
	if (wci_wslv_reqF_countReg_EN)
	  wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_reqF_countReg_D_IN;
	if (wci_wslv_respF_cntr_r_EN)
	  wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_respF_cntr_r_D_IN;
	if (wci_wslv_respF_q_0_EN)
	  wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
	if (wci_wslv_respF_q_1_EN)
	  wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
	if (wci_wslv_sFlagReg_EN)
	  wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
	if (wci_wslv_sThreadBusy_d_EN)
	  wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_sThreadBusy_d_D_IN;
      end
    if (cinS_EN) cinS <= `BSV_ASSIGNMENT_DELAY cinS_D_IN;
  end

  always@(posedge cd_CLK_OUT)
  begin
    if (slowReset_OUT_RST == `BSV_RESET_VALUE)
      begin
        cinF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
	icap_icapBusy <= `BSV_ASSIGNMENT_DELAY 1'd1;
	icap_icapCs <= `BSV_ASSIGNMENT_DELAY 1'd0;
	icap_icapIn <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
	icap_icapOut <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
	icap_icapRd <= `BSV_ASSIGNMENT_DELAY 1'd0;
	icap_inCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
	icap_outCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
      end
    else
      begin
        if (cinF_head_wrapped_EN)
	  cinF_head_wrapped <= `BSV_ASSIGNMENT_DELAY cinF_head_wrapped_D_IN;
	if (icap_icapBusy_EN)
	  icap_icapBusy <= `BSV_ASSIGNMENT_DELAY icap_icapBusy_D_IN;
	if (icap_icapCs_EN)
	  icap_icapCs <= `BSV_ASSIGNMENT_DELAY icap_icapCs_D_IN;
	if (icap_icapIn_EN)
	  icap_icapIn <= `BSV_ASSIGNMENT_DELAY icap_icapIn_D_IN;
	if (icap_icapOut_EN)
	  icap_icapOut <= `BSV_ASSIGNMENT_DELAY icap_icapOut_D_IN;
	if (icap_icapRd_EN)
	  icap_icapRd <= `BSV_ASSIGNMENT_DELAY icap_icapRd_D_IN;
	if (icap_inCount_EN)
	  icap_inCount <= `BSV_ASSIGNMENT_DELAY icap_inCount_D_IN;
	if (icap_outCount_EN)
	  icap_outCount <= `BSV_ASSIGNMENT_DELAY icap_outCount_D_IN;
      end
  end

  always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
  if (wciS0_MReset_n == `BSV_RESET_VALUE)
    begin
      coutF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
      coutF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
      coutF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
      wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
    end
  else
    begin
      if (coutF_rRdPtr_rsCounter_EN)
	coutF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
	    coutF_rRdPtr_rsCounter_D_IN;
      if (coutF_rWrPtr_rdCounter_EN)
	coutF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
	    coutF_rWrPtr_rdCounter_D_IN;
      if (coutF_rWrPtr_rdCounterPre_EN)
	coutF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
	    coutF_rWrPtr_rdCounterPre_D_IN;
      if (wci_wslv_isReset_isInReset_EN)
	wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
	    wci_wslv_isReset_isInReset_D_IN;
    end

  always@(posedge cd_CLK_OUT or `BSV_RESET_EDGE slowReset_OUT_RST)
  if (slowReset_OUT_RST == `BSV_RESET_VALUE)
    begin
      coutF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
      coutF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
      coutF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
    end
  else
    begin
      if (coutF_rRdPtr_rdCounter_EN)
	coutF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
	    coutF_rRdPtr_rdCounter_D_IN;
      if (coutF_rRdPtr_rdCounterPre_EN)
	coutF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
	    coutF_rRdPtr_rdCounterPre_D_IN;
      if (coutF_rWrPtr_rsCounter_EN)
	coutF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
	    coutF_rWrPtr_rsCounter_D_IN;
    end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cinF_head_wrapped = 1'h0;
    cinF_tail_wrapped = 1'h0;
    cinS = 32'hAAAAAAAA;
    coutF_rRdPtr_rdCounter = 11'h2AA;
    coutF_rRdPtr_rdCounterPre = 11'h2AA;
    coutF_rRdPtr_rsCounter = 11'h2AA;
    coutF_rWrPtr_rdCounter = 11'h2AA;
    coutF_rWrPtr_rdCounterPre = 11'h2AA;
    coutF_rWrPtr_rsCounter = 11'h2AA;
    dwRead = 32'hAAAAAAAA;
    dwWritten = 32'hAAAAAAAA;
    icapCtrl = 32'hAAAAAAAA;
    icap_icapBusy = 1'h0;
    icap_icapCs = 1'h0;
    icap_icapIn = 32'hAAAAAAAA;
    icap_icapOut = 32'hAAAAAAAA;
    icap_icapRd = 1'h0;
    icap_inCount = 32'hAAAAAAAA;
    icap_outCount = 32'hAAAAAAAA;
    wci_wslv_cEdge = 3'h2;
    wci_wslv_cState = 3'h2;
    wci_wslv_ctlAckReg = 1'h0;
    wci_wslv_ctlOpActive = 1'h0;
    wci_wslv_illegalEdge = 1'h0;
    wci_wslv_isReset_isInReset = 1'h0;
    wci_wslv_nState = 3'h2;
    wci_wslv_reqF_countReg = 2'h2;
    wci_wslv_respF_cntr_r = 2'h2;
    wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
    wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
    wci_wslv_sFlagReg = 1'h0;
    wci_wslv_sThreadBusy_d = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge wciS0_Clk)
  begin
    #0;
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
	begin
	  v__h3563 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
	$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
		 v__h3563,
		 wci_wslv_reqF_D_OUT[36:34],
		 wci_wslv_cState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_IsO)
	begin
	  v__h26628 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_IsO)
	$display("[%0d]: %m: Starting ICAPWorker", v__h26628);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 60: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 46: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 46: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
	begin
	  v__h3882 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
	$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
		 v__h3882,
		 wci_wslv_cEdge,
		 wci_wslv_cState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
	begin
	  v__h3738 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
	$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
		 v__h3738,
		 wci_wslv_cEdge,
		 wci_wslv_cState,
		 wci_wslv_nState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 26: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n  fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
	$display("Error: \"bsv/wrk/ICAPWorker.bsv\", line 77, column 36: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
  end
  // synopsys translate_on

  // synopsys translate_off
  always@(negedge cd_CLK_OUT)
  begin
    #0;
    if (slowReset_OUT_RST != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_icap_write_configration_data &&
	  WILL_FIRE_RL_icap_read_configuration_data)
	$display("Error: \"bsv/dev/ICAP.bsv\", line 127, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_icap_write_configration_data]\n  and [RL_icap_read_configuration_data] ) fired in the same clock cycle.\n");
  end
  // synopsys translate_on
endmodule  // mkICAPWorker

