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///////////////////////////////////////////////////////////////////////////////
//
//  RX_STREAM
//
//
//  Description: The RX_LL module receives data from the Aurora Channel,
//               converts it to a simple streaming format. This module expects
//               all data to be carried in a single, infinite frame, and it 
//               expects the data data in lanes to be all valid or all invalid
//
//               This module supports 4 2-byte lane designs.
//
//

`timescale 1 ns / 1 ps

module aur1_RX_STREAM
(
    // LocalLink PDU Interface
    RX_D,
    RX_SRC_RDY_N,


    // Global Logic Interface
    START_RX,


    // Aurora Lane Interface
    RX_PAD,
    RX_PE_DATA,
    RX_PE_DATA_V,
    RX_SCP,
    RX_ECP,


    // System Interface
    USER_CLK


);

`define DLY #1


//***********************************Port Declarations*******************************


    // LocalLink PDU Interface
    output  [0:63]     RX_D;
    output             RX_SRC_RDY_N;


    // Global Logic Interface
    input              START_RX;


    // Aurora Lane Interface
    input   [0:3]      RX_PAD;
    input   [0:63]     RX_PE_DATA;
    input   [0:3]      RX_PE_DATA_V;
    input   [0:3]      RX_SCP;
    input   [0:3]      RX_ECP;


    // System Interface
    input              USER_CLK;




//************************Register Declarations********************
    
    reg                infinite_frame_started_r;



//***********************Main Body of Code*************************
    
    
    //Don't start presenting data until the infinite frame starts
    always @(posedge USER_CLK)
        if(!START_RX)
            infinite_frame_started_r    <=  `DLY 1'b0;
        else if(RX_SCP > 4'd0)
            infinite_frame_started_r    <=  `DLY 1'b1;
        
        
    assign  RX_D     =   RX_PE_DATA;
    
    assign  RX_SRC_RDY_N   =   !(RX_PE_DATA_V[0] && infinite_frame_started_r);
    
    
    
endmodule
