// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
// 
// ===========================================================

`timescale 1 ns / 1 ps 

(* CORE_GENERATION_INFO="pointer_basic,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=211,HLS_SYN_LUT=228,HLS_VERSION=2018_2}" *)

module pointer_basic (
        ap_clk,
        ap_rst_n,
        s_axi_pointer_basic_io_AWVALID,
        s_axi_pointer_basic_io_AWREADY,
        s_axi_pointer_basic_io_AWADDR,
        s_axi_pointer_basic_io_WVALID,
        s_axi_pointer_basic_io_WREADY,
        s_axi_pointer_basic_io_WDATA,
        s_axi_pointer_basic_io_WSTRB,
        s_axi_pointer_basic_io_ARVALID,
        s_axi_pointer_basic_io_ARREADY,
        s_axi_pointer_basic_io_ARADDR,
        s_axi_pointer_basic_io_RVALID,
        s_axi_pointer_basic_io_RREADY,
        s_axi_pointer_basic_io_RDATA,
        s_axi_pointer_basic_io_RRESP,
        s_axi_pointer_basic_io_BVALID,
        s_axi_pointer_basic_io_BREADY,
        s_axi_pointer_basic_io_BRESP,
        interrupt
);

parameter    ap_ST_fsm_state1 = 3'd1;
parameter    ap_ST_fsm_state2 = 3'd2;
parameter    ap_ST_fsm_state3 = 3'd4;
parameter    C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH = 32;
parameter    C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH = 5;
parameter    C_S_AXI_DATA_WIDTH = 32;

parameter C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);

input   ap_clk;
input   ap_rst_n;
input   s_axi_pointer_basic_io_AWVALID;
output   s_axi_pointer_basic_io_AWREADY;
input  [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_AWADDR;
input   s_axi_pointer_basic_io_WVALID;
output   s_axi_pointer_basic_io_WREADY;
input  [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_WDATA;
input  [C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH - 1:0] s_axi_pointer_basic_io_WSTRB;
input   s_axi_pointer_basic_io_ARVALID;
output   s_axi_pointer_basic_io_ARREADY;
input  [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_ARADDR;
output   s_axi_pointer_basic_io_RVALID;
input   s_axi_pointer_basic_io_RREADY;
output  [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_RDATA;
output  [1:0] s_axi_pointer_basic_io_RRESP;
output   s_axi_pointer_basic_io_BVALID;
input   s_axi_pointer_basic_io_BREADY;
output  [1:0] s_axi_pointer_basic_io_BRESP;
output   interrupt;

 reg    ap_rst_n_inv;
wire    ap_start;
reg    ap_done;
reg    ap_idle;
(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
wire    ap_CS_fsm_state1;
reg    ap_ready;
wire   [31:0] d_i;
reg    d_o_ap_vld;
reg   [31:0] acc;
reg   [31:0] d_read_reg_52;
wire   [31:0] acc_assign_fu_41_p2;
reg   [31:0] acc_assign_reg_57;
wire    ap_CS_fsm_state2;
wire    ap_CS_fsm_state3;
reg   [2:0] ap_NS_fsm;

// power-on initialization
initial begin
#0 ap_CS_fsm = 3'd1;
#0 acc = 32'd0;
end

pointer_basic_pointer_basic_io_s_axi #(
    .C_S_AXI_ADDR_WIDTH( C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH ),
    .C_S_AXI_DATA_WIDTH( C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH ))
pointer_basic_pointer_basic_io_s_axi_U(
    .AWVALID(s_axi_pointer_basic_io_AWVALID),
    .AWREADY(s_axi_pointer_basic_io_AWREADY),
    .AWADDR(s_axi_pointer_basic_io_AWADDR),
    .WVALID(s_axi_pointer_basic_io_WVALID),
    .WREADY(s_axi_pointer_basic_io_WREADY),
    .WDATA(s_axi_pointer_basic_io_WDATA),
    .WSTRB(s_axi_pointer_basic_io_WSTRB),
    .ARVALID(s_axi_pointer_basic_io_ARVALID),
    .ARREADY(s_axi_pointer_basic_io_ARREADY),
    .ARADDR(s_axi_pointer_basic_io_ARADDR),
    .RVALID(s_axi_pointer_basic_io_RVALID),
    .RREADY(s_axi_pointer_basic_io_RREADY),
    .RDATA(s_axi_pointer_basic_io_RDATA),
    .RRESP(s_axi_pointer_basic_io_RRESP),
    .BVALID(s_axi_pointer_basic_io_BVALID),
    .BREADY(s_axi_pointer_basic_io_BREADY),
    .BRESP(s_axi_pointer_basic_io_BRESP),
    .ACLK(ap_clk),
    .ARESET(ap_rst_n_inv),
    .ACLK_EN(1'b1),
    .ap_start(ap_start),
    .interrupt(interrupt),
    .ap_ready(ap_ready),
    .ap_done(ap_done),
    .ap_idle(ap_idle),
    .d_o(acc_assign_reg_57),
    .d_o_ap_vld(d_o_ap_vld),
    .d_i(d_i)
);

always @ (posedge ap_clk) begin
    if (ap_rst_n_inv == 1'b1) begin
        ap_CS_fsm <= ap_ST_fsm_state1;
    end else begin
        ap_CS_fsm <= ap_NS_fsm;
    end
end

always @ (posedge ap_clk) begin
    if ((1'b1 == ap_CS_fsm_state2)) begin
        acc <= acc_assign_fu_41_p2;
        acc_assign_reg_57 <= acc_assign_fu_41_p2;
    end
end

always @ (posedge ap_clk) begin
    if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
        d_read_reg_52 <= d_i;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        ap_done = 1'b1;
    end else begin
        ap_done = 1'b0;
    end
end

always @ (*) begin
    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
        ap_idle = 1'b1;
    end else begin
        ap_idle = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        ap_ready = 1'b1;
    end else begin
        ap_ready = 1'b0;
    end
end

always @ (*) begin
    if ((1'b1 == ap_CS_fsm_state3)) begin
        d_o_ap_vld = 1'b1;
    end else begin
        d_o_ap_vld = 1'b0;
    end
end

always @ (*) begin
    case (ap_CS_fsm)
        ap_ST_fsm_state1 : begin
            if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
                ap_NS_fsm = ap_ST_fsm_state2;
            end else begin
                ap_NS_fsm = ap_ST_fsm_state1;
            end
        end
        ap_ST_fsm_state2 : begin
            ap_NS_fsm = ap_ST_fsm_state3;
        end
        ap_ST_fsm_state3 : begin
            ap_NS_fsm = ap_ST_fsm_state1;
        end
        default : begin
            ap_NS_fsm = 'bx;
        end
    endcase
end

assign acc_assign_fu_41_p2 = (acc + d_read_reg_52);

assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];

assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];

assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];

always @ (*) begin
    ap_rst_n_inv = ~ap_rst_n;
end

endmodule //pointer_basic
