// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE 

// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// 			ALTTEMP_SENSE
//
// Simulation Library Files(s):
// 			
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix V" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 12.0SP2 cbx_alttemp_sense 2012:08:02:15:11:11:SJ cbx_cycloneii 2012:08:02:15:11:11:SJ cbx_lpm_add_sub 2012:08:02:15:11:11:SJ cbx_lpm_compare 2012:08:02:15:11:11:SJ cbx_lpm_counter 2012:08:02:15:11:11:SJ cbx_lpm_decode 2012:08:02:15:11:11:SJ cbx_mgl 2012:08:02:15:40:54:SJ cbx_stratix 2012:08:02:15:11:11:SJ cbx_stratixii 2012:08:02:15:11:11:SJ cbx_stratixiii 2012:08:02:15:11:11:SJ cbx_stratixv 2012:08:02:15:11:11:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = stratixv_tsdblock 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module  temp_sense_alttemp_sense_v8t
	( 
	ce,
	clk,
	clr,
	tsdcaldone,
	tsdcalo) /* synthesis synthesis_clearbox=2 */;
	input   ce;
	input   clk;
	input   clr;
	output   tsdcaldone;
	output   [7:0]  tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1   ce;
	tri0   clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	wire  wire_sd1_tsdcaldone;
	wire  [7:0]   wire_sd1_tsdcalo;

	stratixv_tsdblock   sd1
	( 
	.ce(ce),
	.clk(clk),
	.clr(clr),
	.tsdcaldone(wire_sd1_tsdcaldone),
	.tsdcalo(wire_sd1_tsdcalo));
	defparam
		sd1.clock_divider_enable = "true",
		sd1.clock_divider_value = 80,
		sd1.sim_tsdcalo = 0,
		sd1.lpm_type = "stratixv_tsdblock";
	assign
		tsdcaldone = wire_sd1_tsdcaldone,
		tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_v8t
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
	ce,
	clk,
	clr,
	tsdcaldone,
	tsdcalo)/* synthesis synthesis_clearbox = 2 */;

	input	  ce;
	input	  clk;
	input	  clr;
	output	  tsdcaldone;
	output	[7:0]  tsdcalo;

	wire [7:0] sub_wire0;
	wire  sub_wire1;
	wire [7:0] tsdcalo = sub_wire0[7:0];
	wire  tsdcaldone = sub_wire1;

	temp_sense_alttemp_sense_v8t	temp_sense_alttemp_sense_v8t_component (
				.ce (ce),
				.clk (clk),
				.clr (clr),
				.tsdcalo (sub_wire0),
				.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
	 clearbox_macroname = ALTTEMP_SENSE
	 clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp FALSE TRUE
