
`timescale 1 ns / 1 ps

	module draw_fifo_v1_0_S00_AXI #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line

		// Width of S_AXI data bus
		parameter integer C_S_AXI_DATA_WIDTH	= 32,
		// Width of S_AXI address bus
		parameter integer C_S_AXI_ADDR_WIDTH	= 3
	)
	(
		// Users to add ports here
		output reg [15:0] x1,
		output reg [15:0] y1,
		output reg [15:0] x2,
		output reg [15:0] y2,
		output reg [15:0] x3,
		output reg [15:0] c1,
		output reg [15:0] c2,
		output reg [15:0] c3,
		output wire ap_rstn,
		output wire ap_start,
		input wire ap_done,
		input wire ap_ready,
		input wire ap_idle,
		// User ports ends
		// Do not modify the ports beyond this line

		// Global Clock Signal
		input wire  S_AXI_ACLK,
		// Global Reset Signal. This Signal is Active LOW
		input wire  S_AXI_ARESETN,
		// Write address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 + 2: 0] S_AXI_AWADDR,
		// Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether
    		// the transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_AWPROT,
		// Write address valid. This signal indicates that the master signaling
    		// valid write address and control information.
		input wire  S_AXI_AWVALID,
		// Write address ready. This signal indicates that the slave is ready
    		// to accept an address and associated control signals.
		output wire  S_AXI_AWREADY,
		// Write data (issued by master, acceped by Slave) 
		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
		// Write strobes. This signal indicates which byte lanes hold
    		// valid data. There is one write strobe bit for each eight
    		// bits of the write data bus.    
		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
		// Write valid. This signal indicates that valid write
    		// data and strobes are available.
		input wire  S_AXI_WVALID,
		// Write ready. This signal indicates that the slave
    		// can accept the write data.
		output wire  S_AXI_WREADY,
		// Write response. This signal indicates the status
    		// of the write transaction.
		output wire [1 : 0] S_AXI_BRESP,
		// Write response valid. This signal indicates that the channel
    		// is signaling a valid write response.
		output wire  S_AXI_BVALID,
		// Response ready. This signal indicates that the master
    		// can accept a write response.
		input wire  S_AXI_BREADY,
		// Read address (issued by master, acceped by Slave)
		input wire [C_S_AXI_ADDR_WIDTH-1 + 2: 0] S_AXI_ARADDR,
		// Protection type. This signal indicates the privilege
    		// and security level of the transaction, and whether the
    		// transaction is a data access or an instruction access.
		input wire [2 : 0] S_AXI_ARPROT,
		// Read address valid. This signal indicates that the channel
    		// is signaling valid read address and control information.
		input wire  S_AXI_ARVALID,
		// Read address ready. This signal indicates that the slave is
    		// ready to accept an address and associated control signals.
		output wire  S_AXI_ARREADY,
		// Read data (issued by slave)
		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
		// Read response. This signal indicates the status of the
    		// read transfer.
		output wire [1 : 0] S_AXI_RRESP,
		// Read valid. This signal indicates that the channel is
    		// signaling the required read data.
		output wire  S_AXI_RVALID,
		// Read ready. This signal indicates that the master can
    		// accept the read data and response information.
		input wire  S_AXI_RREADY
	);

	// AXI4LITE signals
	reg [C_S_AXI_ADDR_WIDTH-1 + 2 : 0] 	axi_awaddr;
	reg  	axi_awready;
	reg  	axi_wready;
	reg [1 : 0] 	axi_bresp;
	reg  	axi_bvalid;
	reg [C_S_AXI_ADDR_WIDTH-1 + 2: 0] 	axi_araddr;
	reg  	axi_arready;
	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
	reg [1 : 0] 	axi_rresp;
	reg  	axi_rvalid;

	// Example-specific design signals
	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
	// ADDR_LSB is used for addressing 32/64 bit registers/memories
	// ADDR_LSB = 2 for 32 bits (n downto 2)
	// ADDR_LSB = 3 for 64 bits (n downto 3)
	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
	localparam integer OPT_MEM_ADDR_BITS = 0;
	//----------------------------------------------
	//-- Signals for user logic register space example
	//------------------------------------------------
	//-- Number of Slave Registers 2
	reg 	slv_rstn = 'b0;
	wire	 slv_reg_rden;
	wire	 slv_reg_wren;
	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
	wire 	fifo_empty;
	wire	fifo_full;
	wire	ren;
	reg	fifo_ren2 = 'b0;
	reg [2:0] state = 3'h0;
	wire [31:0] fifo_dout;
	reg [31:0] x1y1PreLoad = 32'h0;
	reg [31:0] x2y2PreLoad = 32'h0;
	reg [31:0] x3c1PreLoad = 32'h0;
	reg [31:0] c2c3PreLoad = 32'h0;
	reg fifo_next;
	reg fifo_start = 'b0;
	reg fifo_busy = 'b0;
	reg fifo_prefetch = 'b0;
    	
	assign ap_start = fifo_start && (~ap_ready || (state == 3'd4));

	always @(posedge S_AXI_ACLK) begin
		if (ap_start)
			fifo_busy <= 'b1;
		else if (ap_ready)
			fifo_busy <= 'b0;
	end

	// control FIFO
	assign ren = (state < 3'd4);
	always @(posedge S_AXI_ACLK) begin
		fifo_ren2 <= ren & ~fifo_empty;
		fifo_next <= ap_idle && fifo_empty && (state == 4'd0) && ~fifo_start;
	end

	// load register until state == 3'h4
	// preStart means shift register is 'full'
	always @(posedge S_AXI_ACLK) begin
		if (~slv_rstn) begin
			x1 <= x1;
			y1 <= y1;
			x2 <= x2;
			y2 <= y2;
			x3 <= x3;
			c1 <= c1;
			c2 <= c2;
			c3 <= c3;
			x1y1PreLoad <= x1y1PreLoad;
			x2y2PreLoad <= x2y2PreLoad;
			x3c1PreLoad <= x3c1PreLoad;
			c2c3PreLoad <= c2c3PreLoad;
			state <= 3'h0;
			fifo_start <= 'b0;
			fifo_prefetch <= 'b0;
		end
                else if (state == 3'h4) begin
			if (~fifo_start || ap_ready) begin
				// draw parameter loaded and the engine is ready
				x1 <= x1y1PreLoad[15:0];
				y1 <= x1y1PreLoad[31:16];
				x2 <= x2y2PreLoad[15:0];
				y2 <= x2y2PreLoad[31:16];
				x3 <= x3c1PreLoad[15:0];
				c1 <= x3c1PreLoad[31:16];
				c2 <= c2c3PreLoad[15:0];
				c3 <= c2c3PreLoad[31:16];
				x2y2PreLoad <= x2y2PreLoad;
				x3c1PreLoad <= x3c1PreLoad;
				c2c3PreLoad <= c2c3PreLoad;
				fifo_prefetch <= fifo_prefetch;
				// start the engine
				fifo_start <= 'b1;
				if (fifo_prefetch) begin
					// next data prefetched
					x1y1PreLoad <= fifo_dout;
					state <= 3'h1;
				end
				else begin
					// next not ready
					x1y1PreLoad <= x1y1PreLoad;
					state <= 3'h0;
				end
			end
			else begin
				// wait for the engine done
				x1 <= x1;
				y1 <= y1;
				x2 <= x2;
				y2 <= y2;
				x3 <= x3;
				c1 <= c1;
				c2 <= c2;
				c3 <= c3;
				x1y1PreLoad <= x1y1PreLoad;
				x2y2PreLoad <= x2y2PreLoad;
				x3c1PreLoad <= x3c1PreLoad;
				c2c3PreLoad <= c2c3PreLoad;
				fifo_prefetch <= fifo_prefetch;
				fifo_start <= fifo_start;
				state <= state;
			end
		end
		else begin
			x1 <= x1;
			y1 <= y1;
			x2 <= x2;
			y2 <= y2;
			x3 <= x3;
			c1 <= c1;
			c2 <= c2;
			c3 <= c3;
			fifo_start <= ap_ready ? 'b0 : fifo_start;
			if (fifo_ren2) begin
				// fifo can be read; load a word
				// shift registers
				case (state)
					3'd0:
						begin
							x1y1PreLoad <= fifo_dout;
							x2y2PreLoad <= x2y2PreLoad;
							x3c1PreLoad <= x3c1PreLoad;
							c2c3PreLoad <= c2c3PreLoad;
							fifo_prefetch <= 'b0;
						end
					3'd1:
						begin
							x1y1PreLoad <= x1y1PreLoad;
							x2y2PreLoad <= fifo_dout;
							x3c1PreLoad <= x3c1PreLoad;
							c2c3PreLoad <= c2c3PreLoad;
							fifo_prefetch <= 'b0;
						end
					3'd2:
						begin
							x1y1PreLoad <= x1y1PreLoad;
							x2y2PreLoad <= x2y2PreLoad;
							x3c1PreLoad <= fifo_dout;
							c2c3PreLoad <= c2c3PreLoad;
							fifo_prefetch <= 'b0;
						end
					3'd3:
						begin
							x1y1PreLoad <= x1y1PreLoad;
							x2y2PreLoad <= x2y2PreLoad;
							x3c1PreLoad <= x3c1PreLoad;
							c2c3PreLoad <= fifo_dout;
							fifo_prefetch <= ~fifo_empty;
						end
					default:
						begin
							x1y1PreLoad <= x1y1PreLoad;
							x2y2PreLoad <= x2y2PreLoad;
							x3c1PreLoad <= x3c1PreLoad;
							c2c3PreLoad <= c2c3PreLoad;
							fifo_prefetch <= fifo_prefetch;
						end
				endcase
				// update the regsiter count
				state <= state + 3'h1;
			end
			else begin
				// wait for next data
				x1y1PreLoad <= x1y1PreLoad;
				x2y2PreLoad <= x2y2PreLoad;
				x3c1PreLoad <= x3c1PreLoad;
				c2c3PreLoad <= c2c3PreLoad;
				fifo_start <= ap_ready ? 'b0 : fifo_start;
				fifo_prefetch <= fifo_prefetch;
				state <= state;
			end
		end
	end

	// I/O Connections assignments
	assign ap_rstn		= slv_rstn;
	assign S_AXI_AWREADY	= axi_awready;
	assign S_AXI_WREADY	= axi_wready;
	assign S_AXI_BRESP	= axi_bresp;
	assign S_AXI_BVALID	= axi_bvalid;
	assign S_AXI_ARREADY	= axi_arready;
	assign S_AXI_RDATA	= axi_rdata;
	assign S_AXI_RRESP	= axi_rresp;
	assign S_AXI_RVALID	= axi_rvalid;

	
	// Implement axi_awready generation
	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
	// de-asserted when reset is low.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin
	          // slave is ready to accept write address when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_awready <= 1'b1;
	        end
	      else           
	        begin
	          axi_awready <= 1'b0;
	        end
	    end 
	end       

	// Implement axi_awaddr latching
	// This process is used to latch the address when both 
	// S_AXI_AWVALID and S_AXI_WVALID are valid. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_awaddr <= 0;
	    end 
	  else
	    begin    
	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
	        begin
	          // Write Address latching 
	          axi_awaddr <= S_AXI_AWADDR;
	        end
	    end 
	end       

	// Implement axi_wready generation
	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
	// de-asserted when reset is low. 

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_wready <= 1'b0;
	    end 
	  else
	    begin    
	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
	        begin
	          // slave is ready to accept write data when 
	          // there is a valid write address and write data
	          // on the write address and data bus. This design 
	          // expects no outstanding transactions. 
	          axi_wready <= 1'b1;
	        end
	      else
	        begin
	          axi_wready <= 1'b0;
	        end
	    end 
	end       

	// Implement memory mapped register select and write logic generation
	// The write data is accepted and written to memory mapped registers when
	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
	// select byte enables of slave registers while writing.
	// These registers are cleared when reset (active low) is applied.
	// Slave register write enable is asserted when valid address and data are available
	// and the slave is ready to accept the write address and write data.
	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
	wire fifo_wen = slv_reg_wren && (axi_awaddr[2] == 1'h0);

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      slv_rstn <= 'b0;
	    end
	  else
	    if (slv_reg_wren
             && (axi_awaddr[2] == 1'h1)
	     && (S_AXI_WSTRB[3] == 'b1)
             ) begin
		slv_rstn <= S_AXI_WDATA[31];
	    end
	end    

	// Implement write response logic generation
	// The write response and response valid signals are asserted by the slave 
	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
	// This marks the acceptance of address and indicates the status of 
	// write transaction.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_bvalid  <= 0;
	      axi_bresp   <= 2'b0;
	    end 
	  else
	    begin    
	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
	        begin
	          // indicates a valid write response is available
	          axi_bvalid <= 1'b1;
	          axi_bresp  <= 2'b0; // 'OKAY' response 
	        end                   // work error responses in future
	      else
	        begin
	          if (S_AXI_BREADY && axi_bvalid) 
	            //check if bready is asserted while bvalid is high) 
	            //(there is a possibility that bready is always asserted high)   
	            begin
	              axi_bvalid <= 1'b0; 
	            end  
	        end
	    end
	end   

	// Implement axi_arready generation
	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
	// S_AXI_ARVALID is asserted. axi_awready is 
	// de-asserted when reset (active low) is asserted. 
	// The read address is also latched when S_AXI_ARVALID is 
	// asserted. axi_araddr is reset to zero on reset assertion.

	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_arready <= 1'b0;
	      axi_araddr  <= 32'b0;
	    end 
	  else
	    begin    
	      if (~axi_arready && S_AXI_ARVALID)
	        begin
	          // indicates that the slave has acceped the valid read address
	          axi_arready <= 1'b1;
	          // Read address latching
	          axi_araddr  <= S_AXI_ARADDR;
	        end
	      else
	        begin
	          axi_arready <= 1'b0;
	        end
	    end 
	end       

	// Implement axi_arvalid generation
	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
	// data are available on the axi_rdata bus at this instance. The 
	// assertion of axi_rvalid marks the validity of read data on the 
	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
	// cleared to zero on reset (active low).  
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rvalid <= 0;
	      axi_rresp  <= 0;
	    end 
	  else
	    begin    
	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
	        begin
	          // Valid read data is available at the read data bus
	          axi_rvalid <= 1'b1;
	          axi_rresp  <= 2'b0; // 'OKAY' response
	        end   
	      else if (axi_rvalid && S_AXI_RREADY)
	        begin
	          // Read data is accepted by the master
	          axi_rvalid <= 1'b0;
	        end                
	    end
	end    

	// Implement memory mapped register select and read logic generation
	// Slave register read enable is asserted when valid address is available
	// and the slave is ready to accept the read address.
	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
	always @(*)
	begin
	      // Address decoding for reading registers
	      case ( axi_araddr[4:2] )
	        3'h0   : reg_data_out <= {30'h0, fifo_full, fifo_next};
	        3'h1   : reg_data_out <= {slv_rstn, ap_start, fifo_busy, 25'h0, ap_idle, state};
		3'h2   : reg_data_out <= {y1, x1};
		3'h3   : reg_data_out <= x1y1PreLoad;
		3'h4   : reg_data_out <= {y2, x2};
		3'h5   : reg_data_out <= x2y2PreLoad;
		3'h6   : reg_data_out <= {c1, x3};
		3'h7   : reg_data_out <= x3c1PreLoad;
	        default : reg_data_out <= 0;
	      endcase
	end

	// Output register or memory read data
	always @( posedge S_AXI_ACLK )
	begin
	  if ( S_AXI_ARESETN == 1'b0 )
	    begin
	      axi_rdata  <= 0;
	    end 
	  else
	    begin    
	      // When there is a valid read address (S_AXI_ARVALID) with 
	      // acceptance of read address by the slave (axi_arready), 
	      // output the read dada 
	      if (slv_reg_rden)
	        begin
	          axi_rdata <= reg_data_out;     // register read data
	        end   
	    end
	end    

	// Add user logic here
	draw_fifo draw_fifo (
		.srst	(~slv_rstn),
		.clk	(S_AXI_ACLK),
		.din	(S_AXI_WDATA),
		.wr_en	(fifo_wen),
		.rd_en	(ren),
		.dout	(fifo_dout),
		.full	(fifo_full),
		.empty	(fifo_empty)
	);	
	// User logic ends

	endmodule
