// wasca_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 15.1 193

`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0 (
		input  wire        altpll_0_c0_clk,                                            //                                          altpll_0_c0.clk
		input  wire        clk_0_clk_clk,                                              //                                            clk_0_clk.clk
		input  wire        abus_slave_0_reset_reset_bridge_in_reset_reset,             //             abus_slave_0_reset_reset_bridge_in_reset.reset
		input  wire        altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
		input  wire [27:0] abus_slave_0_avalon_master_address,                         //                           abus_slave_0_avalon_master.address
		output wire        abus_slave_0_avalon_master_waitrequest,                     //                                                     .waitrequest
		input  wire [0:0]  abus_slave_0_avalon_master_burstcount,                      //                                                     .burstcount
		input  wire [1:0]  abus_slave_0_avalon_master_byteenable,                      //                                                     .byteenable
		input  wire        abus_slave_0_avalon_master_read,                            //                                                     .read
		output wire [15:0] abus_slave_0_avalon_master_readdata,                        //                                                     .readdata
		output wire        abus_slave_0_avalon_master_readdatavalid,                   //                                                     .readdatavalid
		input  wire        abus_slave_0_avalon_master_write,                           //                                                     .write
		input  wire [15:0] abus_slave_0_avalon_master_writedata,                       //                                                     .writedata
		input  wire [27:0] nios2_gen2_0_data_master_address,                           //                             nios2_gen2_0_data_master.address
		output wire        nios2_gen2_0_data_master_waitrequest,                       //                                                     .waitrequest
		input  wire [3:0]  nios2_gen2_0_data_master_byteenable,                        //                                                     .byteenable
		input  wire        nios2_gen2_0_data_master_read,                              //                                                     .read
		output wire [31:0] nios2_gen2_0_data_master_readdata,                          //                                                     .readdata
		input  wire        nios2_gen2_0_data_master_write,                             //                                                     .write
		input  wire [31:0] nios2_gen2_0_data_master_writedata,                         //                                                     .writedata
		input  wire        nios2_gen2_0_data_master_debugaccess,                       //                                                     .debugaccess
		input  wire [27:0] nios2_gen2_0_instruction_master_address,                    //                      nios2_gen2_0_instruction_master.address
		output wire        nios2_gen2_0_instruction_master_waitrequest,                //                                                     .waitrequest
		input  wire        nios2_gen2_0_instruction_master_read,                       //                                                     .read
		output wire [31:0] nios2_gen2_0_instruction_master_readdata,                   //                                                     .readdata
		output wire [7:0]  abus_demux_0_avalon_nios_address,                           //                             abus_demux_0_avalon_nios.address
		output wire        abus_demux_0_avalon_nios_write,                             //                                                     .write
		output wire        abus_demux_0_avalon_nios_read,                              //                                                     .read
		input  wire [31:0] abus_demux_0_avalon_nios_readdata,                          //                                                     .readdata
		output wire [31:0] abus_demux_0_avalon_nios_writedata,                         //                                                     .writedata
		output wire [0:0]  abus_demux_0_avalon_nios_burstcount,                        //                                                     .burstcount
		input  wire        abus_demux_0_avalon_nios_readdatavalid,                     //                                                     .readdatavalid
		input  wire        abus_demux_0_avalon_nios_waitrequest,                       //                                                     .waitrequest
		output wire [7:0]  abus_slave_0_avalon_nios_address,                           //                             abus_slave_0_avalon_nios.address
		output wire        abus_slave_0_avalon_nios_write,                             //                                                     .write
		output wire        abus_slave_0_avalon_nios_read,                              //                                                     .read
		input  wire [31:0] abus_slave_0_avalon_nios_readdata,                          //                                                     .readdata
		output wire [31:0] abus_slave_0_avalon_nios_writedata,                         //                                                     .writedata
		output wire [0:0]  abus_slave_0_avalon_nios_burstcount,                        //                                                     .burstcount
		input  wire        abus_slave_0_avalon_nios_readdatavalid,                     //                                                     .readdatavalid
		input  wire        abus_slave_0_avalon_nios_waitrequest,                       //                                                     .waitrequest
		output wire [1:0]  altpll_0_pll_slave_address,                                 //                                   altpll_0_pll_slave.address
		output wire        altpll_0_pll_slave_write,                                   //                                                     .write
		output wire        altpll_0_pll_slave_read,                                    //                                                     .read
		input  wire [31:0] altpll_0_pll_slave_readdata,                                //                                                     .readdata
		output wire [31:0] altpll_0_pll_slave_writedata,                               //                                                     .writedata
		output wire [24:0] external_sdram_controller_s1_address,                       //                         external_sdram_controller_s1.address
		output wire        external_sdram_controller_s1_write,                         //                                                     .write
		output wire        external_sdram_controller_s1_read,                          //                                                     .read
		input  wire [15:0] external_sdram_controller_s1_readdata,                      //                                                     .readdata
		output wire [15:0] external_sdram_controller_s1_writedata,                     //                                                     .writedata
		output wire [1:0]  external_sdram_controller_s1_byteenable,                    //                                                     .byteenable
		input  wire        external_sdram_controller_s1_readdatavalid,                 //                                                     .readdatavalid
		input  wire        external_sdram_controller_s1_waitrequest,                   //                                                     .waitrequest
		output wire        external_sdram_controller_s1_chipselect,                    //                                                     .chipselect
		output wire [1:0]  extra_leds_s1_address,                                      //                                        extra_leds_s1.address
		output wire        extra_leds_s1_write,                                        //                                                     .write
		input  wire [31:0] extra_leds_s1_readdata,                                     //                                                     .readdata
		output wire [31:0] extra_leds_s1_writedata,                                    //                                                     .writedata
		output wire        extra_leds_s1_chipselect,                                   //                                                     .chipselect
		output wire [1:0]  hex0_s1_address,                                            //                                              hex0_s1.address
		output wire        hex0_s1_write,                                              //                                                     .write
		input  wire [31:0] hex0_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex0_s1_writedata,                                          //                                                     .writedata
		output wire        hex0_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hex1_s1_address,                                            //                                              hex1_s1.address
		output wire        hex1_s1_write,                                              //                                                     .write
		input  wire [31:0] hex1_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex1_s1_writedata,                                          //                                                     .writedata
		output wire        hex1_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hex2_s1_address,                                            //                                              hex2_s1.address
		output wire        hex2_s1_write,                                              //                                                     .write
		input  wire [31:0] hex2_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex2_s1_writedata,                                          //                                                     .writedata
		output wire        hex2_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hex3_s1_address,                                            //                                              hex3_s1.address
		output wire        hex3_s1_write,                                              //                                                     .write
		input  wire [31:0] hex3_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex3_s1_writedata,                                          //                                                     .writedata
		output wire        hex3_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hex4_s1_address,                                            //                                              hex4_s1.address
		output wire        hex4_s1_write,                                              //                                                     .write
		input  wire [31:0] hex4_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex4_s1_writedata,                                          //                                                     .writedata
		output wire        hex4_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hex5_s1_address,                                            //                                              hex5_s1.address
		output wire        hex5_s1_write,                                              //                                                     .write
		input  wire [31:0] hex5_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] hex5_s1_writedata,                                          //                                                     .writedata
		output wire        hex5_s1_chipselect,                                         //                                                     .chipselect
		output wire [1:0]  hexdot_s1_address,                                          //                                            hexdot_s1.address
		output wire        hexdot_s1_write,                                            //                                                     .write
		input  wire [31:0] hexdot_s1_readdata,                                         //                                                     .readdata
		output wire [31:0] hexdot_s1_writedata,                                        //                                                     .writedata
		output wire        hexdot_s1_chipselect,                                       //                                                     .chipselect
		output wire [1:0]  leds_s1_address,                                            //                                              leds_s1.address
		output wire        leds_s1_write,                                              //                                                     .write
		input  wire [31:0] leds_s1_readdata,                                           //                                                     .readdata
		output wire [31:0] leds_s1_writedata,                                          //                                                     .writedata
		output wire        leds_s1_chipselect,                                         //                                                     .chipselect
		output wire [8:0]  nios2_gen2_0_debug_mem_slave_address,                       //                         nios2_gen2_0_debug_mem_slave.address
		output wire        nios2_gen2_0_debug_mem_slave_write,                         //                                                     .write
		output wire        nios2_gen2_0_debug_mem_slave_read,                          //                                                     .read
		input  wire [31:0] nios2_gen2_0_debug_mem_slave_readdata,                      //                                                     .readdata
		output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata,                     //                                                     .writedata
		output wire [3:0]  nios2_gen2_0_debug_mem_slave_byteenable,                    //                                                     .byteenable
		input  wire        nios2_gen2_0_debug_mem_slave_waitrequest,                   //                                                     .waitrequest
		output wire        nios2_gen2_0_debug_mem_slave_debugaccess,                   //                                                     .debugaccess
		output wire [0:0]  onchip_flash_0_csr_address,                                 //                                   onchip_flash_0_csr.address
		output wire        onchip_flash_0_csr_write,                                   //                                                     .write
		output wire        onchip_flash_0_csr_read,                                    //                                                     .read
		input  wire [31:0] onchip_flash_0_csr_readdata,                                //                                                     .readdata
		output wire [31:0] onchip_flash_0_csr_writedata,                               //                                                     .writedata
		output wire [18:0] onchip_flash_0_data_address,                                //                                  onchip_flash_0_data.address
		output wire        onchip_flash_0_data_write,                                  //                                                     .write
		output wire        onchip_flash_0_data_read,                                   //                                                     .read
		input  wire [31:0] onchip_flash_0_data_readdata,                               //                                                     .readdata
		output wire [31:0] onchip_flash_0_data_writedata,                              //                                                     .writedata
		output wire [3:0]  onchip_flash_0_data_burstcount,                             //                                                     .burstcount
		input  wire        onchip_flash_0_data_readdatavalid,                          //                                                     .readdatavalid
		input  wire        onchip_flash_0_data_waitrequest,                            //                                                     .waitrequest
		output wire [12:0] onchip_memory2_0_s1_address,                                //                                  onchip_memory2_0_s1.address
		output wire        onchip_memory2_0_s1_write,                                  //                                                     .write
		input  wire [31:0] onchip_memory2_0_s1_readdata,                               //                                                     .readdata
		output wire [31:0] onchip_memory2_0_s1_writedata,                              //                                                     .writedata
		output wire [3:0]  onchip_memory2_0_s1_byteenable,                             //                                                     .byteenable
		output wire        onchip_memory2_0_s1_chipselect,                             //                                                     .chipselect
		output wire        onchip_memory2_0_s1_clken,                                  //                                                     .clken
		output wire [9:0]  onchip_memory2_1_s1_address,                                //                                  onchip_memory2_1_s1.address
		output wire        onchip_memory2_1_s1_write,                                  //                                                     .write
		input  wire [31:0] onchip_memory2_1_s1_readdata,                               //                                                     .readdata
		output wire [31:0] onchip_memory2_1_s1_writedata,                              //                                                     .writedata
		output wire [3:0]  onchip_memory2_1_s1_byteenable,                             //                                                     .byteenable
		output wire        onchip_memory2_1_s1_chipselect,                             //                                                     .chipselect
		output wire        onchip_memory2_1_s1_clken,                                  //                                                     .clken
		output wire [2:0]  performance_counter_0_control_slave_address,                //                  performance_counter_0_control_slave.address
		output wire        performance_counter_0_control_slave_write,                  //                                                     .write
		input  wire [31:0] performance_counter_0_control_slave_readdata,               //                                                     .readdata
		output wire [31:0] performance_counter_0_control_slave_writedata,              //                                                     .writedata
		output wire        performance_counter_0_control_slave_begintransfer,          //                                                     .begintransfer
		output wire [2:0]  spi_stm32_spi_control_port_address,                         //                           spi_stm32_spi_control_port.address
		output wire        spi_stm32_spi_control_port_write,                           //                                                     .write
		output wire        spi_stm32_spi_control_port_read,                            //                                                     .read
		input  wire [15:0] spi_stm32_spi_control_port_readdata,                        //                                                     .readdata
		output wire [15:0] spi_stm32_spi_control_port_writedata,                       //                                                     .writedata
		output wire        spi_stm32_spi_control_port_chipselect,                      //                                                     .chipselect
		output wire [1:0]  spi_sync_s1_address,                                        //                                          spi_sync_s1.address
		input  wire [31:0] spi_sync_s1_readdata,                                       //                                                     .readdata
		output wire [1:0]  switches_s1_address,                                        //                                          switches_s1.address
		input  wire [31:0] switches_s1_readdata,                                       //                                                     .readdata
		output wire [2:0]  uart_0_s1_address,                                          //                                            uart_0_s1.address
		output wire        uart_0_s1_write,                                            //                                                     .write
		output wire        uart_0_s1_read,                                             //                                                     .read
		input  wire [15:0] uart_0_s1_readdata,                                         //                                                     .readdata
		output wire [15:0] uart_0_s1_writedata,                                        //                                                     .writedata
		output wire        uart_0_s1_begintransfer,                                    //                                                     .begintransfer
		output wire        uart_0_s1_chipselect                                        //                                                     .chipselect
	);

	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest;                  // abus_slave_0_avalon_master_agent:av_waitrequest -> abus_slave_0_avalon_master_translator:uav_waitrequest
	wire   [15:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata;                     // abus_slave_0_avalon_master_agent:av_readdata -> abus_slave_0_avalon_master_translator:uav_readdata
	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess;                  // abus_slave_0_avalon_master_translator:uav_debugaccess -> abus_slave_0_avalon_master_agent:av_debugaccess
	wire   [27:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_address;                      // abus_slave_0_avalon_master_translator:uav_address -> abus_slave_0_avalon_master_agent:av_address
	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_read;                         // abus_slave_0_avalon_master_translator:uav_read -> abus_slave_0_avalon_master_agent:av_read
	wire    [1:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable;                   // abus_slave_0_avalon_master_translator:uav_byteenable -> abus_slave_0_avalon_master_agent:av_byteenable
	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid;                // abus_slave_0_avalon_master_agent:av_readdatavalid -> abus_slave_0_avalon_master_translator:uav_readdatavalid
	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock;                         // abus_slave_0_avalon_master_translator:uav_lock -> abus_slave_0_avalon_master_agent:av_lock
	wire          abus_slave_0_avalon_master_translator_avalon_universal_master_0_write;                        // abus_slave_0_avalon_master_translator:uav_write -> abus_slave_0_avalon_master_agent:av_write
	wire   [15:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata;                    // abus_slave_0_avalon_master_translator:uav_writedata -> abus_slave_0_avalon_master_agent:av_writedata
	wire    [1:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount;                   // abus_slave_0_avalon_master_translator:uav_burstcount -> abus_slave_0_avalon_master_agent:av_burstcount
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest;                    // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
	wire   [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata;                       // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess;                    // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
	wire   [27:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address;                        // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_read;                           // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
	wire    [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable;                     // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid;                  // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock;                           // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
	wire          nios2_gen2_0_data_master_translator_avalon_universal_master_0_write;                          // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
	wire   [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata;                      // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
	wire    [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount;                     // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                                                        // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
	wire  [110:0] rsp_mux_001_src_data;                                                                         // rsp_mux_001:src_data -> nios2_gen2_0_data_master_agent:rp_data
	wire          rsp_mux_001_src_ready;                                                                        // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux_001:src_ready
	wire   [22:0] rsp_mux_001_src_channel;                                                                      // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                                                // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                                  // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest;             // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
	wire   [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata;                // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess;             // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
	wire   [27:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address;                 // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read;                    // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
	wire    [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable;              // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid;           // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock;                    // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
	wire          nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write;                   // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
	wire   [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata;               // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
	wire    [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount;              // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
	wire          rsp_mux_002_src_valid;                                                                        // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
	wire  [110:0] rsp_mux_002_src_data;                                                                         // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
	wire          rsp_mux_002_src_ready;                                                                        // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
	wire   [22:0] rsp_mux_002_src_channel;                                                                      // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
	wire          rsp_mux_002_src_startofpacket;                                                                // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                                  // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
	wire   [15:0] external_sdram_controller_s1_agent_m0_readdata;                                               // external_sdram_controller_s1_translator:uav_readdata -> external_sdram_controller_s1_agent:m0_readdata
	wire          external_sdram_controller_s1_agent_m0_waitrequest;                                            // external_sdram_controller_s1_translator:uav_waitrequest -> external_sdram_controller_s1_agent:m0_waitrequest
	wire          external_sdram_controller_s1_agent_m0_debugaccess;                                            // external_sdram_controller_s1_agent:m0_debugaccess -> external_sdram_controller_s1_translator:uav_debugaccess
	wire   [27:0] external_sdram_controller_s1_agent_m0_address;                                                // external_sdram_controller_s1_agent:m0_address -> external_sdram_controller_s1_translator:uav_address
	wire    [1:0] external_sdram_controller_s1_agent_m0_byteenable;                                             // external_sdram_controller_s1_agent:m0_byteenable -> external_sdram_controller_s1_translator:uav_byteenable
	wire          external_sdram_controller_s1_agent_m0_read;                                                   // external_sdram_controller_s1_agent:m0_read -> external_sdram_controller_s1_translator:uav_read
	wire          external_sdram_controller_s1_agent_m0_readdatavalid;                                          // external_sdram_controller_s1_translator:uav_readdatavalid -> external_sdram_controller_s1_agent:m0_readdatavalid
	wire          external_sdram_controller_s1_agent_m0_lock;                                                   // external_sdram_controller_s1_agent:m0_lock -> external_sdram_controller_s1_translator:uav_lock
	wire   [15:0] external_sdram_controller_s1_agent_m0_writedata;                                              // external_sdram_controller_s1_agent:m0_writedata -> external_sdram_controller_s1_translator:uav_writedata
	wire          external_sdram_controller_s1_agent_m0_write;                                                  // external_sdram_controller_s1_agent:m0_write -> external_sdram_controller_s1_translator:uav_write
	wire    [1:0] external_sdram_controller_s1_agent_m0_burstcount;                                             // external_sdram_controller_s1_agent:m0_burstcount -> external_sdram_controller_s1_translator:uav_burstcount
	wire          external_sdram_controller_s1_agent_rf_source_valid;                                           // external_sdram_controller_s1_agent:rf_source_valid -> external_sdram_controller_s1_agent_rsp_fifo:in_valid
	wire   [93:0] external_sdram_controller_s1_agent_rf_source_data;                                            // external_sdram_controller_s1_agent:rf_source_data -> external_sdram_controller_s1_agent_rsp_fifo:in_data
	wire          external_sdram_controller_s1_agent_rf_source_ready;                                           // external_sdram_controller_s1_agent_rsp_fifo:in_ready -> external_sdram_controller_s1_agent:rf_source_ready
	wire          external_sdram_controller_s1_agent_rf_source_startofpacket;                                   // external_sdram_controller_s1_agent:rf_source_startofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_startofpacket
	wire          external_sdram_controller_s1_agent_rf_source_endofpacket;                                     // external_sdram_controller_s1_agent:rf_source_endofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_endofpacket
	wire          external_sdram_controller_s1_agent_rsp_fifo_out_valid;                                        // external_sdram_controller_s1_agent_rsp_fifo:out_valid -> external_sdram_controller_s1_agent:rf_sink_valid
	wire   [93:0] external_sdram_controller_s1_agent_rsp_fifo_out_data;                                         // external_sdram_controller_s1_agent_rsp_fifo:out_data -> external_sdram_controller_s1_agent:rf_sink_data
	wire          external_sdram_controller_s1_agent_rsp_fifo_out_ready;                                        // external_sdram_controller_s1_agent:rf_sink_ready -> external_sdram_controller_s1_agent_rsp_fifo:out_ready
	wire          external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket;                                // external_sdram_controller_s1_agent_rsp_fifo:out_startofpacket -> external_sdram_controller_s1_agent:rf_sink_startofpacket
	wire          external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket;                                  // external_sdram_controller_s1_agent_rsp_fifo:out_endofpacket -> external_sdram_controller_s1_agent:rf_sink_endofpacket
	wire          external_sdram_controller_s1_agent_rdata_fifo_src_valid;                                      // external_sdram_controller_s1_agent:rdata_fifo_src_valid -> external_sdram_controller_s1_agent_rdata_fifo:in_valid
	wire   [17:0] external_sdram_controller_s1_agent_rdata_fifo_src_data;                                       // external_sdram_controller_s1_agent:rdata_fifo_src_data -> external_sdram_controller_s1_agent_rdata_fifo:in_data
	wire          external_sdram_controller_s1_agent_rdata_fifo_src_ready;                                      // external_sdram_controller_s1_agent_rdata_fifo:in_ready -> external_sdram_controller_s1_agent:rdata_fifo_src_ready
	wire   [31:0] onchip_memory2_1_s1_agent_m0_readdata;                                                        // onchip_memory2_1_s1_translator:uav_readdata -> onchip_memory2_1_s1_agent:m0_readdata
	wire          onchip_memory2_1_s1_agent_m0_waitrequest;                                                     // onchip_memory2_1_s1_translator:uav_waitrequest -> onchip_memory2_1_s1_agent:m0_waitrequest
	wire          onchip_memory2_1_s1_agent_m0_debugaccess;                                                     // onchip_memory2_1_s1_agent:m0_debugaccess -> onchip_memory2_1_s1_translator:uav_debugaccess
	wire   [27:0] onchip_memory2_1_s1_agent_m0_address;                                                         // onchip_memory2_1_s1_agent:m0_address -> onchip_memory2_1_s1_translator:uav_address
	wire    [3:0] onchip_memory2_1_s1_agent_m0_byteenable;                                                      // onchip_memory2_1_s1_agent:m0_byteenable -> onchip_memory2_1_s1_translator:uav_byteenable
	wire          onchip_memory2_1_s1_agent_m0_read;                                                            // onchip_memory2_1_s1_agent:m0_read -> onchip_memory2_1_s1_translator:uav_read
	wire          onchip_memory2_1_s1_agent_m0_readdatavalid;                                                   // onchip_memory2_1_s1_translator:uav_readdatavalid -> onchip_memory2_1_s1_agent:m0_readdatavalid
	wire          onchip_memory2_1_s1_agent_m0_lock;                                                            // onchip_memory2_1_s1_agent:m0_lock -> onchip_memory2_1_s1_translator:uav_lock
	wire   [31:0] onchip_memory2_1_s1_agent_m0_writedata;                                                       // onchip_memory2_1_s1_agent:m0_writedata -> onchip_memory2_1_s1_translator:uav_writedata
	wire          onchip_memory2_1_s1_agent_m0_write;                                                           // onchip_memory2_1_s1_agent:m0_write -> onchip_memory2_1_s1_translator:uav_write
	wire    [2:0] onchip_memory2_1_s1_agent_m0_burstcount;                                                      // onchip_memory2_1_s1_agent:m0_burstcount -> onchip_memory2_1_s1_translator:uav_burstcount
	wire          onchip_memory2_1_s1_agent_rf_source_valid;                                                    // onchip_memory2_1_s1_agent:rf_source_valid -> onchip_memory2_1_s1_agent_rsp_fifo:in_valid
	wire  [111:0] onchip_memory2_1_s1_agent_rf_source_data;                                                     // onchip_memory2_1_s1_agent:rf_source_data -> onchip_memory2_1_s1_agent_rsp_fifo:in_data
	wire          onchip_memory2_1_s1_agent_rf_source_ready;                                                    // onchip_memory2_1_s1_agent_rsp_fifo:in_ready -> onchip_memory2_1_s1_agent:rf_source_ready
	wire          onchip_memory2_1_s1_agent_rf_source_startofpacket;                                            // onchip_memory2_1_s1_agent:rf_source_startofpacket -> onchip_memory2_1_s1_agent_rsp_fifo:in_startofpacket
	wire          onchip_memory2_1_s1_agent_rf_source_endofpacket;                                              // onchip_memory2_1_s1_agent:rf_source_endofpacket -> onchip_memory2_1_s1_agent_rsp_fifo:in_endofpacket
	wire          onchip_memory2_1_s1_agent_rsp_fifo_out_valid;                                                 // onchip_memory2_1_s1_agent_rsp_fifo:out_valid -> onchip_memory2_1_s1_agent:rf_sink_valid
	wire  [111:0] onchip_memory2_1_s1_agent_rsp_fifo_out_data;                                                  // onchip_memory2_1_s1_agent_rsp_fifo:out_data -> onchip_memory2_1_s1_agent:rf_sink_data
	wire          onchip_memory2_1_s1_agent_rsp_fifo_out_ready;                                                 // onchip_memory2_1_s1_agent:rf_sink_ready -> onchip_memory2_1_s1_agent_rsp_fifo:out_ready
	wire          onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket;                                         // onchip_memory2_1_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s1_agent:rf_sink_startofpacket
	wire          onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket;                                           // onchip_memory2_1_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_001_src_valid;                                                                        // cmd_mux_001:src_valid -> onchip_memory2_1_s1_agent:cp_valid
	wire  [110:0] cmd_mux_001_src_data;                                                                         // cmd_mux_001:src_data -> onchip_memory2_1_s1_agent:cp_data
	wire          cmd_mux_001_src_ready;                                                                        // onchip_memory2_1_s1_agent:cp_ready -> cmd_mux_001:src_ready
	wire   [22:0] cmd_mux_001_src_channel;                                                                      // cmd_mux_001:src_channel -> onchip_memory2_1_s1_agent:cp_channel
	wire          cmd_mux_001_src_startofpacket;                                                                // cmd_mux_001:src_startofpacket -> onchip_memory2_1_s1_agent:cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                                  // cmd_mux_001:src_endofpacket -> onchip_memory2_1_s1_agent:cp_endofpacket
	wire   [31:0] abus_slave_0_avalon_nios_agent_m0_readdata;                                                   // abus_slave_0_avalon_nios_translator:uav_readdata -> abus_slave_0_avalon_nios_agent:m0_readdata
	wire          abus_slave_0_avalon_nios_agent_m0_waitrequest;                                                // abus_slave_0_avalon_nios_translator:uav_waitrequest -> abus_slave_0_avalon_nios_agent:m0_waitrequest
	wire          abus_slave_0_avalon_nios_agent_m0_debugaccess;                                                // abus_slave_0_avalon_nios_agent:m0_debugaccess -> abus_slave_0_avalon_nios_translator:uav_debugaccess
	wire   [27:0] abus_slave_0_avalon_nios_agent_m0_address;                                                    // abus_slave_0_avalon_nios_agent:m0_address -> abus_slave_0_avalon_nios_translator:uav_address
	wire    [3:0] abus_slave_0_avalon_nios_agent_m0_byteenable;                                                 // abus_slave_0_avalon_nios_agent:m0_byteenable -> abus_slave_0_avalon_nios_translator:uav_byteenable
	wire          abus_slave_0_avalon_nios_agent_m0_read;                                                       // abus_slave_0_avalon_nios_agent:m0_read -> abus_slave_0_avalon_nios_translator:uav_read
	wire          abus_slave_0_avalon_nios_agent_m0_readdatavalid;                                              // abus_slave_0_avalon_nios_translator:uav_readdatavalid -> abus_slave_0_avalon_nios_agent:m0_readdatavalid
	wire          abus_slave_0_avalon_nios_agent_m0_lock;                                                       // abus_slave_0_avalon_nios_agent:m0_lock -> abus_slave_0_avalon_nios_translator:uav_lock
	wire   [31:0] abus_slave_0_avalon_nios_agent_m0_writedata;                                                  // abus_slave_0_avalon_nios_agent:m0_writedata -> abus_slave_0_avalon_nios_translator:uav_writedata
	wire          abus_slave_0_avalon_nios_agent_m0_write;                                                      // abus_slave_0_avalon_nios_agent:m0_write -> abus_slave_0_avalon_nios_translator:uav_write
	wire    [2:0] abus_slave_0_avalon_nios_agent_m0_burstcount;                                                 // abus_slave_0_avalon_nios_agent:m0_burstcount -> abus_slave_0_avalon_nios_translator:uav_burstcount
	wire          abus_slave_0_avalon_nios_agent_rf_source_valid;                                               // abus_slave_0_avalon_nios_agent:rf_source_valid -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_valid
	wire  [111:0] abus_slave_0_avalon_nios_agent_rf_source_data;                                                // abus_slave_0_avalon_nios_agent:rf_source_data -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_data
	wire          abus_slave_0_avalon_nios_agent_rf_source_ready;                                               // abus_slave_0_avalon_nios_agent_rsp_fifo:in_ready -> abus_slave_0_avalon_nios_agent:rf_source_ready
	wire          abus_slave_0_avalon_nios_agent_rf_source_startofpacket;                                       // abus_slave_0_avalon_nios_agent:rf_source_startofpacket -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_startofpacket
	wire          abus_slave_0_avalon_nios_agent_rf_source_endofpacket;                                         // abus_slave_0_avalon_nios_agent:rf_source_endofpacket -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_endofpacket
	wire          abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid;                                            // abus_slave_0_avalon_nios_agent_rsp_fifo:out_valid -> abus_slave_0_avalon_nios_agent:rf_sink_valid
	wire  [111:0] abus_slave_0_avalon_nios_agent_rsp_fifo_out_data;                                             // abus_slave_0_avalon_nios_agent_rsp_fifo:out_data -> abus_slave_0_avalon_nios_agent:rf_sink_data
	wire          abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready;                                            // abus_slave_0_avalon_nios_agent:rf_sink_ready -> abus_slave_0_avalon_nios_agent_rsp_fifo:out_ready
	wire          abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket;                                    // abus_slave_0_avalon_nios_agent_rsp_fifo:out_startofpacket -> abus_slave_0_avalon_nios_agent:rf_sink_startofpacket
	wire          abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket;                                      // abus_slave_0_avalon_nios_agent_rsp_fifo:out_endofpacket -> abus_slave_0_avalon_nios_agent:rf_sink_endofpacket
	wire          cmd_mux_002_src_valid;                                                                        // cmd_mux_002:src_valid -> abus_slave_0_avalon_nios_agent:cp_valid
	wire  [110:0] cmd_mux_002_src_data;                                                                         // cmd_mux_002:src_data -> abus_slave_0_avalon_nios_agent:cp_data
	wire          cmd_mux_002_src_ready;                                                                        // abus_slave_0_avalon_nios_agent:cp_ready -> cmd_mux_002:src_ready
	wire   [22:0] cmd_mux_002_src_channel;                                                                      // cmd_mux_002:src_channel -> abus_slave_0_avalon_nios_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                                                // cmd_mux_002:src_startofpacket -> abus_slave_0_avalon_nios_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                                  // cmd_mux_002:src_endofpacket -> abus_slave_0_avalon_nios_agent:cp_endofpacket
	wire   [31:0] abus_demux_0_avalon_nios_agent_m0_readdata;                                                   // abus_demux_0_avalon_nios_translator:uav_readdata -> abus_demux_0_avalon_nios_agent:m0_readdata
	wire          abus_demux_0_avalon_nios_agent_m0_waitrequest;                                                // abus_demux_0_avalon_nios_translator:uav_waitrequest -> abus_demux_0_avalon_nios_agent:m0_waitrequest
	wire          abus_demux_0_avalon_nios_agent_m0_debugaccess;                                                // abus_demux_0_avalon_nios_agent:m0_debugaccess -> abus_demux_0_avalon_nios_translator:uav_debugaccess
	wire   [27:0] abus_demux_0_avalon_nios_agent_m0_address;                                                    // abus_demux_0_avalon_nios_agent:m0_address -> abus_demux_0_avalon_nios_translator:uav_address
	wire    [3:0] abus_demux_0_avalon_nios_agent_m0_byteenable;                                                 // abus_demux_0_avalon_nios_agent:m0_byteenable -> abus_demux_0_avalon_nios_translator:uav_byteenable
	wire          abus_demux_0_avalon_nios_agent_m0_read;                                                       // abus_demux_0_avalon_nios_agent:m0_read -> abus_demux_0_avalon_nios_translator:uav_read
	wire          abus_demux_0_avalon_nios_agent_m0_readdatavalid;                                              // abus_demux_0_avalon_nios_translator:uav_readdatavalid -> abus_demux_0_avalon_nios_agent:m0_readdatavalid
	wire          abus_demux_0_avalon_nios_agent_m0_lock;                                                       // abus_demux_0_avalon_nios_agent:m0_lock -> abus_demux_0_avalon_nios_translator:uav_lock
	wire   [31:0] abus_demux_0_avalon_nios_agent_m0_writedata;                                                  // abus_demux_0_avalon_nios_agent:m0_writedata -> abus_demux_0_avalon_nios_translator:uav_writedata
	wire          abus_demux_0_avalon_nios_agent_m0_write;                                                      // abus_demux_0_avalon_nios_agent:m0_write -> abus_demux_0_avalon_nios_translator:uav_write
	wire    [2:0] abus_demux_0_avalon_nios_agent_m0_burstcount;                                                 // abus_demux_0_avalon_nios_agent:m0_burstcount -> abus_demux_0_avalon_nios_translator:uav_burstcount
	wire          abus_demux_0_avalon_nios_agent_rf_source_valid;                                               // abus_demux_0_avalon_nios_agent:rf_source_valid -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_valid
	wire  [111:0] abus_demux_0_avalon_nios_agent_rf_source_data;                                                // abus_demux_0_avalon_nios_agent:rf_source_data -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_data
	wire          abus_demux_0_avalon_nios_agent_rf_source_ready;                                               // abus_demux_0_avalon_nios_agent_rsp_fifo:in_ready -> abus_demux_0_avalon_nios_agent:rf_source_ready
	wire          abus_demux_0_avalon_nios_agent_rf_source_startofpacket;                                       // abus_demux_0_avalon_nios_agent:rf_source_startofpacket -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_startofpacket
	wire          abus_demux_0_avalon_nios_agent_rf_source_endofpacket;                                         // abus_demux_0_avalon_nios_agent:rf_source_endofpacket -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_endofpacket
	wire          abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid;                                            // abus_demux_0_avalon_nios_agent_rsp_fifo:out_valid -> abus_demux_0_avalon_nios_agent:rf_sink_valid
	wire  [111:0] abus_demux_0_avalon_nios_agent_rsp_fifo_out_data;                                             // abus_demux_0_avalon_nios_agent_rsp_fifo:out_data -> abus_demux_0_avalon_nios_agent:rf_sink_data
	wire          abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready;                                            // abus_demux_0_avalon_nios_agent:rf_sink_ready -> abus_demux_0_avalon_nios_agent_rsp_fifo:out_ready
	wire          abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket;                                    // abus_demux_0_avalon_nios_agent_rsp_fifo:out_startofpacket -> abus_demux_0_avalon_nios_agent:rf_sink_startofpacket
	wire          abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket;                                      // abus_demux_0_avalon_nios_agent_rsp_fifo:out_endofpacket -> abus_demux_0_avalon_nios_agent:rf_sink_endofpacket
	wire          cmd_mux_003_src_valid;                                                                        // cmd_mux_003:src_valid -> abus_demux_0_avalon_nios_agent:cp_valid
	wire  [110:0] cmd_mux_003_src_data;                                                                         // cmd_mux_003:src_data -> abus_demux_0_avalon_nios_agent:cp_data
	wire          cmd_mux_003_src_ready;                                                                        // abus_demux_0_avalon_nios_agent:cp_ready -> cmd_mux_003:src_ready
	wire   [22:0] cmd_mux_003_src_channel;                                                                      // cmd_mux_003:src_channel -> abus_demux_0_avalon_nios_agent:cp_channel
	wire          cmd_mux_003_src_startofpacket;                                                                // cmd_mux_003:src_startofpacket -> abus_demux_0_avalon_nios_agent:cp_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                                  // cmd_mux_003:src_endofpacket -> abus_demux_0_avalon_nios_agent:cp_endofpacket
	wire   [31:0] performance_counter_0_control_slave_agent_m0_readdata;                                        // performance_counter_0_control_slave_translator:uav_readdata -> performance_counter_0_control_slave_agent:m0_readdata
	wire          performance_counter_0_control_slave_agent_m0_waitrequest;                                     // performance_counter_0_control_slave_translator:uav_waitrequest -> performance_counter_0_control_slave_agent:m0_waitrequest
	wire          performance_counter_0_control_slave_agent_m0_debugaccess;                                     // performance_counter_0_control_slave_agent:m0_debugaccess -> performance_counter_0_control_slave_translator:uav_debugaccess
	wire   [27:0] performance_counter_0_control_slave_agent_m0_address;                                         // performance_counter_0_control_slave_agent:m0_address -> performance_counter_0_control_slave_translator:uav_address
	wire    [3:0] performance_counter_0_control_slave_agent_m0_byteenable;                                      // performance_counter_0_control_slave_agent:m0_byteenable -> performance_counter_0_control_slave_translator:uav_byteenable
	wire          performance_counter_0_control_slave_agent_m0_read;                                            // performance_counter_0_control_slave_agent:m0_read -> performance_counter_0_control_slave_translator:uav_read
	wire          performance_counter_0_control_slave_agent_m0_readdatavalid;                                   // performance_counter_0_control_slave_translator:uav_readdatavalid -> performance_counter_0_control_slave_agent:m0_readdatavalid
	wire          performance_counter_0_control_slave_agent_m0_lock;                                            // performance_counter_0_control_slave_agent:m0_lock -> performance_counter_0_control_slave_translator:uav_lock
	wire   [31:0] performance_counter_0_control_slave_agent_m0_writedata;                                       // performance_counter_0_control_slave_agent:m0_writedata -> performance_counter_0_control_slave_translator:uav_writedata
	wire          performance_counter_0_control_slave_agent_m0_write;                                           // performance_counter_0_control_slave_agent:m0_write -> performance_counter_0_control_slave_translator:uav_write
	wire    [2:0] performance_counter_0_control_slave_agent_m0_burstcount;                                      // performance_counter_0_control_slave_agent:m0_burstcount -> performance_counter_0_control_slave_translator:uav_burstcount
	wire          performance_counter_0_control_slave_agent_rf_source_valid;                                    // performance_counter_0_control_slave_agent:rf_source_valid -> performance_counter_0_control_slave_agent_rsp_fifo:in_valid
	wire  [111:0] performance_counter_0_control_slave_agent_rf_source_data;                                     // performance_counter_0_control_slave_agent:rf_source_data -> performance_counter_0_control_slave_agent_rsp_fifo:in_data
	wire          performance_counter_0_control_slave_agent_rf_source_ready;                                    // performance_counter_0_control_slave_agent_rsp_fifo:in_ready -> performance_counter_0_control_slave_agent:rf_source_ready
	wire          performance_counter_0_control_slave_agent_rf_source_startofpacket;                            // performance_counter_0_control_slave_agent:rf_source_startofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_startofpacket
	wire          performance_counter_0_control_slave_agent_rf_source_endofpacket;                              // performance_counter_0_control_slave_agent:rf_source_endofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_endofpacket
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_valid;                                 // performance_counter_0_control_slave_agent_rsp_fifo:out_valid -> performance_counter_0_control_slave_agent:rf_sink_valid
	wire  [111:0] performance_counter_0_control_slave_agent_rsp_fifo_out_data;                                  // performance_counter_0_control_slave_agent_rsp_fifo:out_data -> performance_counter_0_control_slave_agent:rf_sink_data
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_ready;                                 // performance_counter_0_control_slave_agent:rf_sink_ready -> performance_counter_0_control_slave_agent_rsp_fifo:out_ready
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket;                         // performance_counter_0_control_slave_agent_rsp_fifo:out_startofpacket -> performance_counter_0_control_slave_agent:rf_sink_startofpacket
	wire          performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket;                           // performance_counter_0_control_slave_agent_rsp_fifo:out_endofpacket -> performance_counter_0_control_slave_agent:rf_sink_endofpacket
	wire          cmd_mux_004_src_valid;                                                                        // cmd_mux_004:src_valid -> performance_counter_0_control_slave_agent:cp_valid
	wire  [110:0] cmd_mux_004_src_data;                                                                         // cmd_mux_004:src_data -> performance_counter_0_control_slave_agent:cp_data
	wire          cmd_mux_004_src_ready;                                                                        // performance_counter_0_control_slave_agent:cp_ready -> cmd_mux_004:src_ready
	wire   [22:0] cmd_mux_004_src_channel;                                                                      // cmd_mux_004:src_channel -> performance_counter_0_control_slave_agent:cp_channel
	wire          cmd_mux_004_src_startofpacket;                                                                // cmd_mux_004:src_startofpacket -> performance_counter_0_control_slave_agent:cp_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                                                  // cmd_mux_004:src_endofpacket -> performance_counter_0_control_slave_agent:cp_endofpacket
	wire   [31:0] onchip_flash_0_csr_agent_m0_readdata;                                                         // onchip_flash_0_csr_translator:uav_readdata -> onchip_flash_0_csr_agent:m0_readdata
	wire          onchip_flash_0_csr_agent_m0_waitrequest;                                                      // onchip_flash_0_csr_translator:uav_waitrequest -> onchip_flash_0_csr_agent:m0_waitrequest
	wire          onchip_flash_0_csr_agent_m0_debugaccess;                                                      // onchip_flash_0_csr_agent:m0_debugaccess -> onchip_flash_0_csr_translator:uav_debugaccess
	wire   [27:0] onchip_flash_0_csr_agent_m0_address;                                                          // onchip_flash_0_csr_agent:m0_address -> onchip_flash_0_csr_translator:uav_address
	wire    [3:0] onchip_flash_0_csr_agent_m0_byteenable;                                                       // onchip_flash_0_csr_agent:m0_byteenable -> onchip_flash_0_csr_translator:uav_byteenable
	wire          onchip_flash_0_csr_agent_m0_read;                                                             // onchip_flash_0_csr_agent:m0_read -> onchip_flash_0_csr_translator:uav_read
	wire          onchip_flash_0_csr_agent_m0_readdatavalid;                                                    // onchip_flash_0_csr_translator:uav_readdatavalid -> onchip_flash_0_csr_agent:m0_readdatavalid
	wire          onchip_flash_0_csr_agent_m0_lock;                                                             // onchip_flash_0_csr_agent:m0_lock -> onchip_flash_0_csr_translator:uav_lock
	wire   [31:0] onchip_flash_0_csr_agent_m0_writedata;                                                        // onchip_flash_0_csr_agent:m0_writedata -> onchip_flash_0_csr_translator:uav_writedata
	wire          onchip_flash_0_csr_agent_m0_write;                                                            // onchip_flash_0_csr_agent:m0_write -> onchip_flash_0_csr_translator:uav_write
	wire    [2:0] onchip_flash_0_csr_agent_m0_burstcount;                                                       // onchip_flash_0_csr_agent:m0_burstcount -> onchip_flash_0_csr_translator:uav_burstcount
	wire          onchip_flash_0_csr_agent_rf_source_valid;                                                     // onchip_flash_0_csr_agent:rf_source_valid -> onchip_flash_0_csr_agent_rsp_fifo:in_valid
	wire  [111:0] onchip_flash_0_csr_agent_rf_source_data;                                                      // onchip_flash_0_csr_agent:rf_source_data -> onchip_flash_0_csr_agent_rsp_fifo:in_data
	wire          onchip_flash_0_csr_agent_rf_source_ready;                                                     // onchip_flash_0_csr_agent_rsp_fifo:in_ready -> onchip_flash_0_csr_agent:rf_source_ready
	wire          onchip_flash_0_csr_agent_rf_source_startofpacket;                                             // onchip_flash_0_csr_agent:rf_source_startofpacket -> onchip_flash_0_csr_agent_rsp_fifo:in_startofpacket
	wire          onchip_flash_0_csr_agent_rf_source_endofpacket;                                               // onchip_flash_0_csr_agent:rf_source_endofpacket -> onchip_flash_0_csr_agent_rsp_fifo:in_endofpacket
	wire          onchip_flash_0_csr_agent_rsp_fifo_out_valid;                                                  // onchip_flash_0_csr_agent_rsp_fifo:out_valid -> onchip_flash_0_csr_agent:rf_sink_valid
	wire  [111:0] onchip_flash_0_csr_agent_rsp_fifo_out_data;                                                   // onchip_flash_0_csr_agent_rsp_fifo:out_data -> onchip_flash_0_csr_agent:rf_sink_data
	wire          onchip_flash_0_csr_agent_rsp_fifo_out_ready;                                                  // onchip_flash_0_csr_agent:rf_sink_ready -> onchip_flash_0_csr_agent_rsp_fifo:out_ready
	wire          onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket;                                          // onchip_flash_0_csr_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_csr_agent:rf_sink_startofpacket
	wire          onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket;                                            // onchip_flash_0_csr_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_csr_agent:rf_sink_endofpacket
	wire          cmd_mux_005_src_valid;                                                                        // cmd_mux_005:src_valid -> onchip_flash_0_csr_agent:cp_valid
	wire  [110:0] cmd_mux_005_src_data;                                                                         // cmd_mux_005:src_data -> onchip_flash_0_csr_agent:cp_data
	wire          cmd_mux_005_src_ready;                                                                        // onchip_flash_0_csr_agent:cp_ready -> cmd_mux_005:src_ready
	wire   [22:0] cmd_mux_005_src_channel;                                                                      // cmd_mux_005:src_channel -> onchip_flash_0_csr_agent:cp_channel
	wire          cmd_mux_005_src_startofpacket;                                                                // cmd_mux_005:src_startofpacket -> onchip_flash_0_csr_agent:cp_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                                                  // cmd_mux_005:src_endofpacket -> onchip_flash_0_csr_agent:cp_endofpacket
	wire   [31:0] onchip_flash_0_data_agent_m0_readdata;                                                        // onchip_flash_0_data_translator:uav_readdata -> onchip_flash_0_data_agent:m0_readdata
	wire          onchip_flash_0_data_agent_m0_waitrequest;                                                     // onchip_flash_0_data_translator:uav_waitrequest -> onchip_flash_0_data_agent:m0_waitrequest
	wire          onchip_flash_0_data_agent_m0_debugaccess;                                                     // onchip_flash_0_data_agent:m0_debugaccess -> onchip_flash_0_data_translator:uav_debugaccess
	wire   [27:0] onchip_flash_0_data_agent_m0_address;                                                         // onchip_flash_0_data_agent:m0_address -> onchip_flash_0_data_translator:uav_address
	wire    [3:0] onchip_flash_0_data_agent_m0_byteenable;                                                      // onchip_flash_0_data_agent:m0_byteenable -> onchip_flash_0_data_translator:uav_byteenable
	wire          onchip_flash_0_data_agent_m0_read;                                                            // onchip_flash_0_data_agent:m0_read -> onchip_flash_0_data_translator:uav_read
	wire          onchip_flash_0_data_agent_m0_readdatavalid;                                                   // onchip_flash_0_data_translator:uav_readdatavalid -> onchip_flash_0_data_agent:m0_readdatavalid
	wire          onchip_flash_0_data_agent_m0_lock;                                                            // onchip_flash_0_data_agent:m0_lock -> onchip_flash_0_data_translator:uav_lock
	wire   [31:0] onchip_flash_0_data_agent_m0_writedata;                                                       // onchip_flash_0_data_agent:m0_writedata -> onchip_flash_0_data_translator:uav_writedata
	wire          onchip_flash_0_data_agent_m0_write;                                                           // onchip_flash_0_data_agent:m0_write -> onchip_flash_0_data_translator:uav_write
	wire    [5:0] onchip_flash_0_data_agent_m0_burstcount;                                                      // onchip_flash_0_data_agent:m0_burstcount -> onchip_flash_0_data_translator:uav_burstcount
	wire          onchip_flash_0_data_agent_rf_source_valid;                                                    // onchip_flash_0_data_agent:rf_source_valid -> onchip_flash_0_data_agent_rsp_fifo:in_valid
	wire  [111:0] onchip_flash_0_data_agent_rf_source_data;                                                     // onchip_flash_0_data_agent:rf_source_data -> onchip_flash_0_data_agent_rsp_fifo:in_data
	wire          onchip_flash_0_data_agent_rf_source_ready;                                                    // onchip_flash_0_data_agent_rsp_fifo:in_ready -> onchip_flash_0_data_agent:rf_source_ready
	wire          onchip_flash_0_data_agent_rf_source_startofpacket;                                            // onchip_flash_0_data_agent:rf_source_startofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_startofpacket
	wire          onchip_flash_0_data_agent_rf_source_endofpacket;                                              // onchip_flash_0_data_agent:rf_source_endofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_endofpacket
	wire          onchip_flash_0_data_agent_rsp_fifo_out_valid;                                                 // onchip_flash_0_data_agent_rsp_fifo:out_valid -> onchip_flash_0_data_agent:rf_sink_valid
	wire  [111:0] onchip_flash_0_data_agent_rsp_fifo_out_data;                                                  // onchip_flash_0_data_agent_rsp_fifo:out_data -> onchip_flash_0_data_agent:rf_sink_data
	wire          onchip_flash_0_data_agent_rsp_fifo_out_ready;                                                 // onchip_flash_0_data_agent:rf_sink_ready -> onchip_flash_0_data_agent_rsp_fifo:out_ready
	wire          onchip_flash_0_data_agent_rsp_fifo_out_startofpacket;                                         // onchip_flash_0_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_data_agent:rf_sink_startofpacket
	wire          onchip_flash_0_data_agent_rsp_fifo_out_endofpacket;                                           // onchip_flash_0_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_data_agent:rf_sink_endofpacket
	wire          cmd_mux_006_src_valid;                                                                        // cmd_mux_006:src_valid -> onchip_flash_0_data_agent:cp_valid
	wire  [110:0] cmd_mux_006_src_data;                                                                         // cmd_mux_006:src_data -> onchip_flash_0_data_agent:cp_data
	wire          cmd_mux_006_src_ready;                                                                        // onchip_flash_0_data_agent:cp_ready -> cmd_mux_006:src_ready
	wire   [22:0] cmd_mux_006_src_channel;                                                                      // cmd_mux_006:src_channel -> onchip_flash_0_data_agent:cp_channel
	wire          cmd_mux_006_src_startofpacket;                                                                // cmd_mux_006:src_startofpacket -> onchip_flash_0_data_agent:cp_startofpacket
	wire          cmd_mux_006_src_endofpacket;                                                                  // cmd_mux_006:src_endofpacket -> onchip_flash_0_data_agent:cp_endofpacket
	wire   [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata;                                               // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest;                                            // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess;                                            // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
	wire   [27:0] nios2_gen2_0_debug_mem_slave_agent_m0_address;                                                // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
	wire    [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable;                                             // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_read;                                                   // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid;                                          // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_lock;                                                   // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
	wire   [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata;                                              // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
	wire          nios2_gen2_0_debug_mem_slave_agent_m0_write;                                                  // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
	wire    [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount;                                             // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
	wire          nios2_gen2_0_debug_mem_slave_agent_rf_source_valid;                                           // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
	wire  [111:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data;                                            // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
	wire          nios2_gen2_0_debug_mem_slave_agent_rf_source_ready;                                           // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
	wire          nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket;                                   // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
	wire          nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket;                                     // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
	wire          nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid;                                        // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
	wire  [111:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data;                                         // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
	wire          nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready;                                        // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
	wire          nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket;                                // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
	wire          nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket;                                  // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
	wire          cmd_mux_007_src_valid;                                                                        // cmd_mux_007:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
	wire  [110:0] cmd_mux_007_src_data;                                                                         // cmd_mux_007:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
	wire          cmd_mux_007_src_ready;                                                                        // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_007:src_ready
	wire   [22:0] cmd_mux_007_src_channel;                                                                      // cmd_mux_007:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
	wire          cmd_mux_007_src_startofpacket;                                                                // cmd_mux_007:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
	wire          cmd_mux_007_src_endofpacket;                                                                  // cmd_mux_007:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
	wire   [31:0] altpll_0_pll_slave_agent_m0_readdata;                                                         // altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_agent:m0_readdata
	wire          altpll_0_pll_slave_agent_m0_waitrequest;                                                      // altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_agent:m0_waitrequest
	wire          altpll_0_pll_slave_agent_m0_debugaccess;                                                      // altpll_0_pll_slave_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
	wire   [27:0] altpll_0_pll_slave_agent_m0_address;                                                          // altpll_0_pll_slave_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
	wire    [3:0] altpll_0_pll_slave_agent_m0_byteenable;                                                       // altpll_0_pll_slave_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
	wire          altpll_0_pll_slave_agent_m0_read;                                                             // altpll_0_pll_slave_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
	wire          altpll_0_pll_slave_agent_m0_readdatavalid;                                                    // altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_agent:m0_readdatavalid
	wire          altpll_0_pll_slave_agent_m0_lock;                                                             // altpll_0_pll_slave_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
	wire   [31:0] altpll_0_pll_slave_agent_m0_writedata;                                                        // altpll_0_pll_slave_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
	wire          altpll_0_pll_slave_agent_m0_write;                                                            // altpll_0_pll_slave_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
	wire    [2:0] altpll_0_pll_slave_agent_m0_burstcount;                                                       // altpll_0_pll_slave_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
	wire          altpll_0_pll_slave_agent_rf_source_valid;                                                     // altpll_0_pll_slave_agent:rf_source_valid -> altpll_0_pll_slave_agent_rsp_fifo:in_valid
	wire  [111:0] altpll_0_pll_slave_agent_rf_source_data;                                                      // altpll_0_pll_slave_agent:rf_source_data -> altpll_0_pll_slave_agent_rsp_fifo:in_data
	wire          altpll_0_pll_slave_agent_rf_source_ready;                                                     // altpll_0_pll_slave_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_agent:rf_source_ready
	wire          altpll_0_pll_slave_agent_rf_source_startofpacket;                                             // altpll_0_pll_slave_agent:rf_source_startofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_startofpacket
	wire          altpll_0_pll_slave_agent_rf_source_endofpacket;                                               // altpll_0_pll_slave_agent:rf_source_endofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_endofpacket
	wire          altpll_0_pll_slave_agent_rsp_fifo_out_valid;                                                  // altpll_0_pll_slave_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_agent:rf_sink_valid
	wire  [111:0] altpll_0_pll_slave_agent_rsp_fifo_out_data;                                                   // altpll_0_pll_slave_agent_rsp_fifo:out_data -> altpll_0_pll_slave_agent:rf_sink_data
	wire          altpll_0_pll_slave_agent_rsp_fifo_out_ready;                                                  // altpll_0_pll_slave_agent:rf_sink_ready -> altpll_0_pll_slave_agent_rsp_fifo:out_ready
	wire          altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket;                                          // altpll_0_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_agent:rf_sink_startofpacket
	wire          altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket;                                            // altpll_0_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_agent:rf_sink_endofpacket
	wire          altpll_0_pll_slave_agent_rdata_fifo_src_valid;                                                // altpll_0_pll_slave_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_agent_rdata_fifo:in_valid
	wire   [33:0] altpll_0_pll_slave_agent_rdata_fifo_src_data;                                                 // altpll_0_pll_slave_agent:rdata_fifo_src_data -> altpll_0_pll_slave_agent_rdata_fifo:in_data
	wire          altpll_0_pll_slave_agent_rdata_fifo_src_ready;                                                // altpll_0_pll_slave_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_008_src_valid;                                                                        // cmd_mux_008:src_valid -> altpll_0_pll_slave_agent:cp_valid
	wire  [110:0] cmd_mux_008_src_data;                                                                         // cmd_mux_008:src_data -> altpll_0_pll_slave_agent:cp_data
	wire          cmd_mux_008_src_ready;                                                                        // altpll_0_pll_slave_agent:cp_ready -> cmd_mux_008:src_ready
	wire   [22:0] cmd_mux_008_src_channel;                                                                      // cmd_mux_008:src_channel -> altpll_0_pll_slave_agent:cp_channel
	wire          cmd_mux_008_src_startofpacket;                                                                // cmd_mux_008:src_startofpacket -> altpll_0_pll_slave_agent:cp_startofpacket
	wire          cmd_mux_008_src_endofpacket;                                                                  // cmd_mux_008:src_endofpacket -> altpll_0_pll_slave_agent:cp_endofpacket
	wire   [31:0] onchip_memory2_0_s1_agent_m0_readdata;                                                        // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
	wire          onchip_memory2_0_s1_agent_m0_waitrequest;                                                     // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
	wire          onchip_memory2_0_s1_agent_m0_debugaccess;                                                     // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
	wire   [27:0] onchip_memory2_0_s1_agent_m0_address;                                                         // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
	wire    [3:0] onchip_memory2_0_s1_agent_m0_byteenable;                                                      // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
	wire          onchip_memory2_0_s1_agent_m0_read;                                                            // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
	wire          onchip_memory2_0_s1_agent_m0_readdatavalid;                                                   // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
	wire          onchip_memory2_0_s1_agent_m0_lock;                                                            // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
	wire   [31:0] onchip_memory2_0_s1_agent_m0_writedata;                                                       // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
	wire          onchip_memory2_0_s1_agent_m0_write;                                                           // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
	wire    [2:0] onchip_memory2_0_s1_agent_m0_burstcount;                                                      // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
	wire          onchip_memory2_0_s1_agent_rf_source_valid;                                                    // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
	wire  [111:0] onchip_memory2_0_s1_agent_rf_source_data;                                                     // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
	wire          onchip_memory2_0_s1_agent_rf_source_ready;                                                    // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
	wire          onchip_memory2_0_s1_agent_rf_source_startofpacket;                                            // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
	wire          onchip_memory2_0_s1_agent_rf_source_endofpacket;                                              // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_valid;                                                 // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
	wire  [111:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data;                                                  // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_ready;                                                 // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket;                                         // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
	wire          onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket;                                           // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_009_src_valid;                                                                        // cmd_mux_009:src_valid -> onchip_memory2_0_s1_agent:cp_valid
	wire  [110:0] cmd_mux_009_src_data;                                                                         // cmd_mux_009:src_data -> onchip_memory2_0_s1_agent:cp_data
	wire          cmd_mux_009_src_ready;                                                                        // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_009:src_ready
	wire   [22:0] cmd_mux_009_src_channel;                                                                      // cmd_mux_009:src_channel -> onchip_memory2_0_s1_agent:cp_channel
	wire          cmd_mux_009_src_startofpacket;                                                                // cmd_mux_009:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
	wire          cmd_mux_009_src_endofpacket;                                                                  // cmd_mux_009:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
	wire   [31:0] switches_s1_agent_m0_readdata;                                                                // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
	wire          switches_s1_agent_m0_waitrequest;                                                             // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
	wire          switches_s1_agent_m0_debugaccess;                                                             // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
	wire   [27:0] switches_s1_agent_m0_address;                                                                 // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
	wire    [3:0] switches_s1_agent_m0_byteenable;                                                              // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
	wire          switches_s1_agent_m0_read;                                                                    // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
	wire          switches_s1_agent_m0_readdatavalid;                                                           // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
	wire          switches_s1_agent_m0_lock;                                                                    // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
	wire   [31:0] switches_s1_agent_m0_writedata;                                                               // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
	wire          switches_s1_agent_m0_write;                                                                   // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
	wire    [2:0] switches_s1_agent_m0_burstcount;                                                              // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
	wire          switches_s1_agent_rf_source_valid;                                                            // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
	wire  [111:0] switches_s1_agent_rf_source_data;                                                             // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
	wire          switches_s1_agent_rf_source_ready;                                                            // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
	wire          switches_s1_agent_rf_source_startofpacket;                                                    // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
	wire          switches_s1_agent_rf_source_endofpacket;                                                      // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
	wire          switches_s1_agent_rsp_fifo_out_valid;                                                         // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
	wire  [111:0] switches_s1_agent_rsp_fifo_out_data;                                                          // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
	wire          switches_s1_agent_rsp_fifo_out_ready;                                                         // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
	wire          switches_s1_agent_rsp_fifo_out_startofpacket;                                                 // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
	wire          switches_s1_agent_rsp_fifo_out_endofpacket;                                                   // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_010_src_valid;                                                                        // cmd_mux_010:src_valid -> switches_s1_agent:cp_valid
	wire  [110:0] cmd_mux_010_src_data;                                                                         // cmd_mux_010:src_data -> switches_s1_agent:cp_data
	wire          cmd_mux_010_src_ready;                                                                        // switches_s1_agent:cp_ready -> cmd_mux_010:src_ready
	wire   [22:0] cmd_mux_010_src_channel;                                                                      // cmd_mux_010:src_channel -> switches_s1_agent:cp_channel
	wire          cmd_mux_010_src_startofpacket;                                                                // cmd_mux_010:src_startofpacket -> switches_s1_agent:cp_startofpacket
	wire          cmd_mux_010_src_endofpacket;                                                                  // cmd_mux_010:src_endofpacket -> switches_s1_agent:cp_endofpacket
	wire   [31:0] leds_s1_agent_m0_readdata;                                                                    // leds_s1_translator:uav_readdata -> leds_s1_agent:m0_readdata
	wire          leds_s1_agent_m0_waitrequest;                                                                 // leds_s1_translator:uav_waitrequest -> leds_s1_agent:m0_waitrequest
	wire          leds_s1_agent_m0_debugaccess;                                                                 // leds_s1_agent:m0_debugaccess -> leds_s1_translator:uav_debugaccess
	wire   [27:0] leds_s1_agent_m0_address;                                                                     // leds_s1_agent:m0_address -> leds_s1_translator:uav_address
	wire    [3:0] leds_s1_agent_m0_byteenable;                                                                  // leds_s1_agent:m0_byteenable -> leds_s1_translator:uav_byteenable
	wire          leds_s1_agent_m0_read;                                                                        // leds_s1_agent:m0_read -> leds_s1_translator:uav_read
	wire          leds_s1_agent_m0_readdatavalid;                                                               // leds_s1_translator:uav_readdatavalid -> leds_s1_agent:m0_readdatavalid
	wire          leds_s1_agent_m0_lock;                                                                        // leds_s1_agent:m0_lock -> leds_s1_translator:uav_lock
	wire   [31:0] leds_s1_agent_m0_writedata;                                                                   // leds_s1_agent:m0_writedata -> leds_s1_translator:uav_writedata
	wire          leds_s1_agent_m0_write;                                                                       // leds_s1_agent:m0_write -> leds_s1_translator:uav_write
	wire    [2:0] leds_s1_agent_m0_burstcount;                                                                  // leds_s1_agent:m0_burstcount -> leds_s1_translator:uav_burstcount
	wire          leds_s1_agent_rf_source_valid;                                                                // leds_s1_agent:rf_source_valid -> leds_s1_agent_rsp_fifo:in_valid
	wire  [111:0] leds_s1_agent_rf_source_data;                                                                 // leds_s1_agent:rf_source_data -> leds_s1_agent_rsp_fifo:in_data
	wire          leds_s1_agent_rf_source_ready;                                                                // leds_s1_agent_rsp_fifo:in_ready -> leds_s1_agent:rf_source_ready
	wire          leds_s1_agent_rf_source_startofpacket;                                                        // leds_s1_agent:rf_source_startofpacket -> leds_s1_agent_rsp_fifo:in_startofpacket
	wire          leds_s1_agent_rf_source_endofpacket;                                                          // leds_s1_agent:rf_source_endofpacket -> leds_s1_agent_rsp_fifo:in_endofpacket
	wire          leds_s1_agent_rsp_fifo_out_valid;                                                             // leds_s1_agent_rsp_fifo:out_valid -> leds_s1_agent:rf_sink_valid
	wire  [111:0] leds_s1_agent_rsp_fifo_out_data;                                                              // leds_s1_agent_rsp_fifo:out_data -> leds_s1_agent:rf_sink_data
	wire          leds_s1_agent_rsp_fifo_out_ready;                                                             // leds_s1_agent:rf_sink_ready -> leds_s1_agent_rsp_fifo:out_ready
	wire          leds_s1_agent_rsp_fifo_out_startofpacket;                                                     // leds_s1_agent_rsp_fifo:out_startofpacket -> leds_s1_agent:rf_sink_startofpacket
	wire          leds_s1_agent_rsp_fifo_out_endofpacket;                                                       // leds_s1_agent_rsp_fifo:out_endofpacket -> leds_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_011_src_valid;                                                                        // cmd_mux_011:src_valid -> leds_s1_agent:cp_valid
	wire  [110:0] cmd_mux_011_src_data;                                                                         // cmd_mux_011:src_data -> leds_s1_agent:cp_data
	wire          cmd_mux_011_src_ready;                                                                        // leds_s1_agent:cp_ready -> cmd_mux_011:src_ready
	wire   [22:0] cmd_mux_011_src_channel;                                                                      // cmd_mux_011:src_channel -> leds_s1_agent:cp_channel
	wire          cmd_mux_011_src_startofpacket;                                                                // cmd_mux_011:src_startofpacket -> leds_s1_agent:cp_startofpacket
	wire          cmd_mux_011_src_endofpacket;                                                                  // cmd_mux_011:src_endofpacket -> leds_s1_agent:cp_endofpacket
	wire   [31:0] uart_0_s1_agent_m0_readdata;                                                                  // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
	wire          uart_0_s1_agent_m0_waitrequest;                                                               // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
	wire          uart_0_s1_agent_m0_debugaccess;                                                               // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
	wire   [27:0] uart_0_s1_agent_m0_address;                                                                   // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
	wire    [3:0] uart_0_s1_agent_m0_byteenable;                                                                // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
	wire          uart_0_s1_agent_m0_read;                                                                      // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
	wire          uart_0_s1_agent_m0_readdatavalid;                                                             // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
	wire          uart_0_s1_agent_m0_lock;                                                                      // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
	wire   [31:0] uart_0_s1_agent_m0_writedata;                                                                 // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
	wire          uart_0_s1_agent_m0_write;                                                                     // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
	wire    [2:0] uart_0_s1_agent_m0_burstcount;                                                                // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
	wire          uart_0_s1_agent_rf_source_valid;                                                              // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
	wire  [111:0] uart_0_s1_agent_rf_source_data;                                                               // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
	wire          uart_0_s1_agent_rf_source_ready;                                                              // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
	wire          uart_0_s1_agent_rf_source_startofpacket;                                                      // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
	wire          uart_0_s1_agent_rf_source_endofpacket;                                                        // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
	wire          uart_0_s1_agent_rsp_fifo_out_valid;                                                           // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
	wire  [111:0] uart_0_s1_agent_rsp_fifo_out_data;                                                            // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
	wire          uart_0_s1_agent_rsp_fifo_out_ready;                                                           // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
	wire          uart_0_s1_agent_rsp_fifo_out_startofpacket;                                                   // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
	wire          uart_0_s1_agent_rsp_fifo_out_endofpacket;                                                     // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_012_src_valid;                                                                        // cmd_mux_012:src_valid -> uart_0_s1_agent:cp_valid
	wire  [110:0] cmd_mux_012_src_data;                                                                         // cmd_mux_012:src_data -> uart_0_s1_agent:cp_data
	wire          cmd_mux_012_src_ready;                                                                        // uart_0_s1_agent:cp_ready -> cmd_mux_012:src_ready
	wire   [22:0] cmd_mux_012_src_channel;                                                                      // cmd_mux_012:src_channel -> uart_0_s1_agent:cp_channel
	wire          cmd_mux_012_src_startofpacket;                                                                // cmd_mux_012:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
	wire          cmd_mux_012_src_endofpacket;                                                                  // cmd_mux_012:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
	wire   [31:0] hex0_s1_agent_m0_readdata;                                                                    // hex0_s1_translator:uav_readdata -> hex0_s1_agent:m0_readdata
	wire          hex0_s1_agent_m0_waitrequest;                                                                 // hex0_s1_translator:uav_waitrequest -> hex0_s1_agent:m0_waitrequest
	wire          hex0_s1_agent_m0_debugaccess;                                                                 // hex0_s1_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess
	wire   [27:0] hex0_s1_agent_m0_address;                                                                     // hex0_s1_agent:m0_address -> hex0_s1_translator:uav_address
	wire    [3:0] hex0_s1_agent_m0_byteenable;                                                                  // hex0_s1_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable
	wire          hex0_s1_agent_m0_read;                                                                        // hex0_s1_agent:m0_read -> hex0_s1_translator:uav_read
	wire          hex0_s1_agent_m0_readdatavalid;                                                               // hex0_s1_translator:uav_readdatavalid -> hex0_s1_agent:m0_readdatavalid
	wire          hex0_s1_agent_m0_lock;                                                                        // hex0_s1_agent:m0_lock -> hex0_s1_translator:uav_lock
	wire   [31:0] hex0_s1_agent_m0_writedata;                                                                   // hex0_s1_agent:m0_writedata -> hex0_s1_translator:uav_writedata
	wire          hex0_s1_agent_m0_write;                                                                       // hex0_s1_agent:m0_write -> hex0_s1_translator:uav_write
	wire    [2:0] hex0_s1_agent_m0_burstcount;                                                                  // hex0_s1_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount
	wire          hex0_s1_agent_rf_source_valid;                                                                // hex0_s1_agent:rf_source_valid -> hex0_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex0_s1_agent_rf_source_data;                                                                 // hex0_s1_agent:rf_source_data -> hex0_s1_agent_rsp_fifo:in_data
	wire          hex0_s1_agent_rf_source_ready;                                                                // hex0_s1_agent_rsp_fifo:in_ready -> hex0_s1_agent:rf_source_ready
	wire          hex0_s1_agent_rf_source_startofpacket;                                                        // hex0_s1_agent:rf_source_startofpacket -> hex0_s1_agent_rsp_fifo:in_startofpacket
	wire          hex0_s1_agent_rf_source_endofpacket;                                                          // hex0_s1_agent:rf_source_endofpacket -> hex0_s1_agent_rsp_fifo:in_endofpacket
	wire          hex0_s1_agent_rsp_fifo_out_valid;                                                             // hex0_s1_agent_rsp_fifo:out_valid -> hex0_s1_agent:rf_sink_valid
	wire  [111:0] hex0_s1_agent_rsp_fifo_out_data;                                                              // hex0_s1_agent_rsp_fifo:out_data -> hex0_s1_agent:rf_sink_data
	wire          hex0_s1_agent_rsp_fifo_out_ready;                                                             // hex0_s1_agent:rf_sink_ready -> hex0_s1_agent_rsp_fifo:out_ready
	wire          hex0_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex0_s1_agent_rsp_fifo:out_startofpacket -> hex0_s1_agent:rf_sink_startofpacket
	wire          hex0_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex0_s1_agent_rsp_fifo:out_endofpacket -> hex0_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_013_src_valid;                                                                        // cmd_mux_013:src_valid -> hex0_s1_agent:cp_valid
	wire  [110:0] cmd_mux_013_src_data;                                                                         // cmd_mux_013:src_data -> hex0_s1_agent:cp_data
	wire          cmd_mux_013_src_ready;                                                                        // hex0_s1_agent:cp_ready -> cmd_mux_013:src_ready
	wire   [22:0] cmd_mux_013_src_channel;                                                                      // cmd_mux_013:src_channel -> hex0_s1_agent:cp_channel
	wire          cmd_mux_013_src_startofpacket;                                                                // cmd_mux_013:src_startofpacket -> hex0_s1_agent:cp_startofpacket
	wire          cmd_mux_013_src_endofpacket;                                                                  // cmd_mux_013:src_endofpacket -> hex0_s1_agent:cp_endofpacket
	wire   [31:0] hex1_s1_agent_m0_readdata;                                                                    // hex1_s1_translator:uav_readdata -> hex1_s1_agent:m0_readdata
	wire          hex1_s1_agent_m0_waitrequest;                                                                 // hex1_s1_translator:uav_waitrequest -> hex1_s1_agent:m0_waitrequest
	wire          hex1_s1_agent_m0_debugaccess;                                                                 // hex1_s1_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess
	wire   [27:0] hex1_s1_agent_m0_address;                                                                     // hex1_s1_agent:m0_address -> hex1_s1_translator:uav_address
	wire    [3:0] hex1_s1_agent_m0_byteenable;                                                                  // hex1_s1_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable
	wire          hex1_s1_agent_m0_read;                                                                        // hex1_s1_agent:m0_read -> hex1_s1_translator:uav_read
	wire          hex1_s1_agent_m0_readdatavalid;                                                               // hex1_s1_translator:uav_readdatavalid -> hex1_s1_agent:m0_readdatavalid
	wire          hex1_s1_agent_m0_lock;                                                                        // hex1_s1_agent:m0_lock -> hex1_s1_translator:uav_lock
	wire   [31:0] hex1_s1_agent_m0_writedata;                                                                   // hex1_s1_agent:m0_writedata -> hex1_s1_translator:uav_writedata
	wire          hex1_s1_agent_m0_write;                                                                       // hex1_s1_agent:m0_write -> hex1_s1_translator:uav_write
	wire    [2:0] hex1_s1_agent_m0_burstcount;                                                                  // hex1_s1_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount
	wire          hex1_s1_agent_rf_source_valid;                                                                // hex1_s1_agent:rf_source_valid -> hex1_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex1_s1_agent_rf_source_data;                                                                 // hex1_s1_agent:rf_source_data -> hex1_s1_agent_rsp_fifo:in_data
	wire          hex1_s1_agent_rf_source_ready;                                                                // hex1_s1_agent_rsp_fifo:in_ready -> hex1_s1_agent:rf_source_ready
	wire          hex1_s1_agent_rf_source_startofpacket;                                                        // hex1_s1_agent:rf_source_startofpacket -> hex1_s1_agent_rsp_fifo:in_startofpacket
	wire          hex1_s1_agent_rf_source_endofpacket;                                                          // hex1_s1_agent:rf_source_endofpacket -> hex1_s1_agent_rsp_fifo:in_endofpacket
	wire          hex1_s1_agent_rsp_fifo_out_valid;                                                             // hex1_s1_agent_rsp_fifo:out_valid -> hex1_s1_agent:rf_sink_valid
	wire  [111:0] hex1_s1_agent_rsp_fifo_out_data;                                                              // hex1_s1_agent_rsp_fifo:out_data -> hex1_s1_agent:rf_sink_data
	wire          hex1_s1_agent_rsp_fifo_out_ready;                                                             // hex1_s1_agent:rf_sink_ready -> hex1_s1_agent_rsp_fifo:out_ready
	wire          hex1_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex1_s1_agent_rsp_fifo:out_startofpacket -> hex1_s1_agent:rf_sink_startofpacket
	wire          hex1_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex1_s1_agent_rsp_fifo:out_endofpacket -> hex1_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_014_src_valid;                                                                        // cmd_mux_014:src_valid -> hex1_s1_agent:cp_valid
	wire  [110:0] cmd_mux_014_src_data;                                                                         // cmd_mux_014:src_data -> hex1_s1_agent:cp_data
	wire          cmd_mux_014_src_ready;                                                                        // hex1_s1_agent:cp_ready -> cmd_mux_014:src_ready
	wire   [22:0] cmd_mux_014_src_channel;                                                                      // cmd_mux_014:src_channel -> hex1_s1_agent:cp_channel
	wire          cmd_mux_014_src_startofpacket;                                                                // cmd_mux_014:src_startofpacket -> hex1_s1_agent:cp_startofpacket
	wire          cmd_mux_014_src_endofpacket;                                                                  // cmd_mux_014:src_endofpacket -> hex1_s1_agent:cp_endofpacket
	wire   [31:0] hex2_s1_agent_m0_readdata;                                                                    // hex2_s1_translator:uav_readdata -> hex2_s1_agent:m0_readdata
	wire          hex2_s1_agent_m0_waitrequest;                                                                 // hex2_s1_translator:uav_waitrequest -> hex2_s1_agent:m0_waitrequest
	wire          hex2_s1_agent_m0_debugaccess;                                                                 // hex2_s1_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess
	wire   [27:0] hex2_s1_agent_m0_address;                                                                     // hex2_s1_agent:m0_address -> hex2_s1_translator:uav_address
	wire    [3:0] hex2_s1_agent_m0_byteenable;                                                                  // hex2_s1_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable
	wire          hex2_s1_agent_m0_read;                                                                        // hex2_s1_agent:m0_read -> hex2_s1_translator:uav_read
	wire          hex2_s1_agent_m0_readdatavalid;                                                               // hex2_s1_translator:uav_readdatavalid -> hex2_s1_agent:m0_readdatavalid
	wire          hex2_s1_agent_m0_lock;                                                                        // hex2_s1_agent:m0_lock -> hex2_s1_translator:uav_lock
	wire   [31:0] hex2_s1_agent_m0_writedata;                                                                   // hex2_s1_agent:m0_writedata -> hex2_s1_translator:uav_writedata
	wire          hex2_s1_agent_m0_write;                                                                       // hex2_s1_agent:m0_write -> hex2_s1_translator:uav_write
	wire    [2:0] hex2_s1_agent_m0_burstcount;                                                                  // hex2_s1_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount
	wire          hex2_s1_agent_rf_source_valid;                                                                // hex2_s1_agent:rf_source_valid -> hex2_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex2_s1_agent_rf_source_data;                                                                 // hex2_s1_agent:rf_source_data -> hex2_s1_agent_rsp_fifo:in_data
	wire          hex2_s1_agent_rf_source_ready;                                                                // hex2_s1_agent_rsp_fifo:in_ready -> hex2_s1_agent:rf_source_ready
	wire          hex2_s1_agent_rf_source_startofpacket;                                                        // hex2_s1_agent:rf_source_startofpacket -> hex2_s1_agent_rsp_fifo:in_startofpacket
	wire          hex2_s1_agent_rf_source_endofpacket;                                                          // hex2_s1_agent:rf_source_endofpacket -> hex2_s1_agent_rsp_fifo:in_endofpacket
	wire          hex2_s1_agent_rsp_fifo_out_valid;                                                             // hex2_s1_agent_rsp_fifo:out_valid -> hex2_s1_agent:rf_sink_valid
	wire  [111:0] hex2_s1_agent_rsp_fifo_out_data;                                                              // hex2_s1_agent_rsp_fifo:out_data -> hex2_s1_agent:rf_sink_data
	wire          hex2_s1_agent_rsp_fifo_out_ready;                                                             // hex2_s1_agent:rf_sink_ready -> hex2_s1_agent_rsp_fifo:out_ready
	wire          hex2_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex2_s1_agent_rsp_fifo:out_startofpacket -> hex2_s1_agent:rf_sink_startofpacket
	wire          hex2_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex2_s1_agent_rsp_fifo:out_endofpacket -> hex2_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_015_src_valid;                                                                        // cmd_mux_015:src_valid -> hex2_s1_agent:cp_valid
	wire  [110:0] cmd_mux_015_src_data;                                                                         // cmd_mux_015:src_data -> hex2_s1_agent:cp_data
	wire          cmd_mux_015_src_ready;                                                                        // hex2_s1_agent:cp_ready -> cmd_mux_015:src_ready
	wire   [22:0] cmd_mux_015_src_channel;                                                                      // cmd_mux_015:src_channel -> hex2_s1_agent:cp_channel
	wire          cmd_mux_015_src_startofpacket;                                                                // cmd_mux_015:src_startofpacket -> hex2_s1_agent:cp_startofpacket
	wire          cmd_mux_015_src_endofpacket;                                                                  // cmd_mux_015:src_endofpacket -> hex2_s1_agent:cp_endofpacket
	wire   [31:0] hex3_s1_agent_m0_readdata;                                                                    // hex3_s1_translator:uav_readdata -> hex3_s1_agent:m0_readdata
	wire          hex3_s1_agent_m0_waitrequest;                                                                 // hex3_s1_translator:uav_waitrequest -> hex3_s1_agent:m0_waitrequest
	wire          hex3_s1_agent_m0_debugaccess;                                                                 // hex3_s1_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess
	wire   [27:0] hex3_s1_agent_m0_address;                                                                     // hex3_s1_agent:m0_address -> hex3_s1_translator:uav_address
	wire    [3:0] hex3_s1_agent_m0_byteenable;                                                                  // hex3_s1_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable
	wire          hex3_s1_agent_m0_read;                                                                        // hex3_s1_agent:m0_read -> hex3_s1_translator:uav_read
	wire          hex3_s1_agent_m0_readdatavalid;                                                               // hex3_s1_translator:uav_readdatavalid -> hex3_s1_agent:m0_readdatavalid
	wire          hex3_s1_agent_m0_lock;                                                                        // hex3_s1_agent:m0_lock -> hex3_s1_translator:uav_lock
	wire   [31:0] hex3_s1_agent_m0_writedata;                                                                   // hex3_s1_agent:m0_writedata -> hex3_s1_translator:uav_writedata
	wire          hex3_s1_agent_m0_write;                                                                       // hex3_s1_agent:m0_write -> hex3_s1_translator:uav_write
	wire    [2:0] hex3_s1_agent_m0_burstcount;                                                                  // hex3_s1_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount
	wire          hex3_s1_agent_rf_source_valid;                                                                // hex3_s1_agent:rf_source_valid -> hex3_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex3_s1_agent_rf_source_data;                                                                 // hex3_s1_agent:rf_source_data -> hex3_s1_agent_rsp_fifo:in_data
	wire          hex3_s1_agent_rf_source_ready;                                                                // hex3_s1_agent_rsp_fifo:in_ready -> hex3_s1_agent:rf_source_ready
	wire          hex3_s1_agent_rf_source_startofpacket;                                                        // hex3_s1_agent:rf_source_startofpacket -> hex3_s1_agent_rsp_fifo:in_startofpacket
	wire          hex3_s1_agent_rf_source_endofpacket;                                                          // hex3_s1_agent:rf_source_endofpacket -> hex3_s1_agent_rsp_fifo:in_endofpacket
	wire          hex3_s1_agent_rsp_fifo_out_valid;                                                             // hex3_s1_agent_rsp_fifo:out_valid -> hex3_s1_agent:rf_sink_valid
	wire  [111:0] hex3_s1_agent_rsp_fifo_out_data;                                                              // hex3_s1_agent_rsp_fifo:out_data -> hex3_s1_agent:rf_sink_data
	wire          hex3_s1_agent_rsp_fifo_out_ready;                                                             // hex3_s1_agent:rf_sink_ready -> hex3_s1_agent_rsp_fifo:out_ready
	wire          hex3_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex3_s1_agent_rsp_fifo:out_startofpacket -> hex3_s1_agent:rf_sink_startofpacket
	wire          hex3_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex3_s1_agent_rsp_fifo:out_endofpacket -> hex3_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_016_src_valid;                                                                        // cmd_mux_016:src_valid -> hex3_s1_agent:cp_valid
	wire  [110:0] cmd_mux_016_src_data;                                                                         // cmd_mux_016:src_data -> hex3_s1_agent:cp_data
	wire          cmd_mux_016_src_ready;                                                                        // hex3_s1_agent:cp_ready -> cmd_mux_016:src_ready
	wire   [22:0] cmd_mux_016_src_channel;                                                                      // cmd_mux_016:src_channel -> hex3_s1_agent:cp_channel
	wire          cmd_mux_016_src_startofpacket;                                                                // cmd_mux_016:src_startofpacket -> hex3_s1_agent:cp_startofpacket
	wire          cmd_mux_016_src_endofpacket;                                                                  // cmd_mux_016:src_endofpacket -> hex3_s1_agent:cp_endofpacket
	wire   [31:0] hex4_s1_agent_m0_readdata;                                                                    // hex4_s1_translator:uav_readdata -> hex4_s1_agent:m0_readdata
	wire          hex4_s1_agent_m0_waitrequest;                                                                 // hex4_s1_translator:uav_waitrequest -> hex4_s1_agent:m0_waitrequest
	wire          hex4_s1_agent_m0_debugaccess;                                                                 // hex4_s1_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess
	wire   [27:0] hex4_s1_agent_m0_address;                                                                     // hex4_s1_agent:m0_address -> hex4_s1_translator:uav_address
	wire    [3:0] hex4_s1_agent_m0_byteenable;                                                                  // hex4_s1_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable
	wire          hex4_s1_agent_m0_read;                                                                        // hex4_s1_agent:m0_read -> hex4_s1_translator:uav_read
	wire          hex4_s1_agent_m0_readdatavalid;                                                               // hex4_s1_translator:uav_readdatavalid -> hex4_s1_agent:m0_readdatavalid
	wire          hex4_s1_agent_m0_lock;                                                                        // hex4_s1_agent:m0_lock -> hex4_s1_translator:uav_lock
	wire   [31:0] hex4_s1_agent_m0_writedata;                                                                   // hex4_s1_agent:m0_writedata -> hex4_s1_translator:uav_writedata
	wire          hex4_s1_agent_m0_write;                                                                       // hex4_s1_agent:m0_write -> hex4_s1_translator:uav_write
	wire    [2:0] hex4_s1_agent_m0_burstcount;                                                                  // hex4_s1_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount
	wire          hex4_s1_agent_rf_source_valid;                                                                // hex4_s1_agent:rf_source_valid -> hex4_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex4_s1_agent_rf_source_data;                                                                 // hex4_s1_agent:rf_source_data -> hex4_s1_agent_rsp_fifo:in_data
	wire          hex4_s1_agent_rf_source_ready;                                                                // hex4_s1_agent_rsp_fifo:in_ready -> hex4_s1_agent:rf_source_ready
	wire          hex4_s1_agent_rf_source_startofpacket;                                                        // hex4_s1_agent:rf_source_startofpacket -> hex4_s1_agent_rsp_fifo:in_startofpacket
	wire          hex4_s1_agent_rf_source_endofpacket;                                                          // hex4_s1_agent:rf_source_endofpacket -> hex4_s1_agent_rsp_fifo:in_endofpacket
	wire          hex4_s1_agent_rsp_fifo_out_valid;                                                             // hex4_s1_agent_rsp_fifo:out_valid -> hex4_s1_agent:rf_sink_valid
	wire  [111:0] hex4_s1_agent_rsp_fifo_out_data;                                                              // hex4_s1_agent_rsp_fifo:out_data -> hex4_s1_agent:rf_sink_data
	wire          hex4_s1_agent_rsp_fifo_out_ready;                                                             // hex4_s1_agent:rf_sink_ready -> hex4_s1_agent_rsp_fifo:out_ready
	wire          hex4_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex4_s1_agent_rsp_fifo:out_startofpacket -> hex4_s1_agent:rf_sink_startofpacket
	wire          hex4_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex4_s1_agent_rsp_fifo:out_endofpacket -> hex4_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_017_src_valid;                                                                        // cmd_mux_017:src_valid -> hex4_s1_agent:cp_valid
	wire  [110:0] cmd_mux_017_src_data;                                                                         // cmd_mux_017:src_data -> hex4_s1_agent:cp_data
	wire          cmd_mux_017_src_ready;                                                                        // hex4_s1_agent:cp_ready -> cmd_mux_017:src_ready
	wire   [22:0] cmd_mux_017_src_channel;                                                                      // cmd_mux_017:src_channel -> hex4_s1_agent:cp_channel
	wire          cmd_mux_017_src_startofpacket;                                                                // cmd_mux_017:src_startofpacket -> hex4_s1_agent:cp_startofpacket
	wire          cmd_mux_017_src_endofpacket;                                                                  // cmd_mux_017:src_endofpacket -> hex4_s1_agent:cp_endofpacket
	wire   [31:0] hex5_s1_agent_m0_readdata;                                                                    // hex5_s1_translator:uav_readdata -> hex5_s1_agent:m0_readdata
	wire          hex5_s1_agent_m0_waitrequest;                                                                 // hex5_s1_translator:uav_waitrequest -> hex5_s1_agent:m0_waitrequest
	wire          hex5_s1_agent_m0_debugaccess;                                                                 // hex5_s1_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess
	wire   [27:0] hex5_s1_agent_m0_address;                                                                     // hex5_s1_agent:m0_address -> hex5_s1_translator:uav_address
	wire    [3:0] hex5_s1_agent_m0_byteenable;                                                                  // hex5_s1_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable
	wire          hex5_s1_agent_m0_read;                                                                        // hex5_s1_agent:m0_read -> hex5_s1_translator:uav_read
	wire          hex5_s1_agent_m0_readdatavalid;                                                               // hex5_s1_translator:uav_readdatavalid -> hex5_s1_agent:m0_readdatavalid
	wire          hex5_s1_agent_m0_lock;                                                                        // hex5_s1_agent:m0_lock -> hex5_s1_translator:uav_lock
	wire   [31:0] hex5_s1_agent_m0_writedata;                                                                   // hex5_s1_agent:m0_writedata -> hex5_s1_translator:uav_writedata
	wire          hex5_s1_agent_m0_write;                                                                       // hex5_s1_agent:m0_write -> hex5_s1_translator:uav_write
	wire    [2:0] hex5_s1_agent_m0_burstcount;                                                                  // hex5_s1_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount
	wire          hex5_s1_agent_rf_source_valid;                                                                // hex5_s1_agent:rf_source_valid -> hex5_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hex5_s1_agent_rf_source_data;                                                                 // hex5_s1_agent:rf_source_data -> hex5_s1_agent_rsp_fifo:in_data
	wire          hex5_s1_agent_rf_source_ready;                                                                // hex5_s1_agent_rsp_fifo:in_ready -> hex5_s1_agent:rf_source_ready
	wire          hex5_s1_agent_rf_source_startofpacket;                                                        // hex5_s1_agent:rf_source_startofpacket -> hex5_s1_agent_rsp_fifo:in_startofpacket
	wire          hex5_s1_agent_rf_source_endofpacket;                                                          // hex5_s1_agent:rf_source_endofpacket -> hex5_s1_agent_rsp_fifo:in_endofpacket
	wire          hex5_s1_agent_rsp_fifo_out_valid;                                                             // hex5_s1_agent_rsp_fifo:out_valid -> hex5_s1_agent:rf_sink_valid
	wire  [111:0] hex5_s1_agent_rsp_fifo_out_data;                                                              // hex5_s1_agent_rsp_fifo:out_data -> hex5_s1_agent:rf_sink_data
	wire          hex5_s1_agent_rsp_fifo_out_ready;                                                             // hex5_s1_agent:rf_sink_ready -> hex5_s1_agent_rsp_fifo:out_ready
	wire          hex5_s1_agent_rsp_fifo_out_startofpacket;                                                     // hex5_s1_agent_rsp_fifo:out_startofpacket -> hex5_s1_agent:rf_sink_startofpacket
	wire          hex5_s1_agent_rsp_fifo_out_endofpacket;                                                       // hex5_s1_agent_rsp_fifo:out_endofpacket -> hex5_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_018_src_valid;                                                                        // cmd_mux_018:src_valid -> hex5_s1_agent:cp_valid
	wire  [110:0] cmd_mux_018_src_data;                                                                         // cmd_mux_018:src_data -> hex5_s1_agent:cp_data
	wire          cmd_mux_018_src_ready;                                                                        // hex5_s1_agent:cp_ready -> cmd_mux_018:src_ready
	wire   [22:0] cmd_mux_018_src_channel;                                                                      // cmd_mux_018:src_channel -> hex5_s1_agent:cp_channel
	wire          cmd_mux_018_src_startofpacket;                                                                // cmd_mux_018:src_startofpacket -> hex5_s1_agent:cp_startofpacket
	wire          cmd_mux_018_src_endofpacket;                                                                  // cmd_mux_018:src_endofpacket -> hex5_s1_agent:cp_endofpacket
	wire   [31:0] hexdot_s1_agent_m0_readdata;                                                                  // hexdot_s1_translator:uav_readdata -> hexdot_s1_agent:m0_readdata
	wire          hexdot_s1_agent_m0_waitrequest;                                                               // hexdot_s1_translator:uav_waitrequest -> hexdot_s1_agent:m0_waitrequest
	wire          hexdot_s1_agent_m0_debugaccess;                                                               // hexdot_s1_agent:m0_debugaccess -> hexdot_s1_translator:uav_debugaccess
	wire   [27:0] hexdot_s1_agent_m0_address;                                                                   // hexdot_s1_agent:m0_address -> hexdot_s1_translator:uav_address
	wire    [3:0] hexdot_s1_agent_m0_byteenable;                                                                // hexdot_s1_agent:m0_byteenable -> hexdot_s1_translator:uav_byteenable
	wire          hexdot_s1_agent_m0_read;                                                                      // hexdot_s1_agent:m0_read -> hexdot_s1_translator:uav_read
	wire          hexdot_s1_agent_m0_readdatavalid;                                                             // hexdot_s1_translator:uav_readdatavalid -> hexdot_s1_agent:m0_readdatavalid
	wire          hexdot_s1_agent_m0_lock;                                                                      // hexdot_s1_agent:m0_lock -> hexdot_s1_translator:uav_lock
	wire   [31:0] hexdot_s1_agent_m0_writedata;                                                                 // hexdot_s1_agent:m0_writedata -> hexdot_s1_translator:uav_writedata
	wire          hexdot_s1_agent_m0_write;                                                                     // hexdot_s1_agent:m0_write -> hexdot_s1_translator:uav_write
	wire    [2:0] hexdot_s1_agent_m0_burstcount;                                                                // hexdot_s1_agent:m0_burstcount -> hexdot_s1_translator:uav_burstcount
	wire          hexdot_s1_agent_rf_source_valid;                                                              // hexdot_s1_agent:rf_source_valid -> hexdot_s1_agent_rsp_fifo:in_valid
	wire  [111:0] hexdot_s1_agent_rf_source_data;                                                               // hexdot_s1_agent:rf_source_data -> hexdot_s1_agent_rsp_fifo:in_data
	wire          hexdot_s1_agent_rf_source_ready;                                                              // hexdot_s1_agent_rsp_fifo:in_ready -> hexdot_s1_agent:rf_source_ready
	wire          hexdot_s1_agent_rf_source_startofpacket;                                                      // hexdot_s1_agent:rf_source_startofpacket -> hexdot_s1_agent_rsp_fifo:in_startofpacket
	wire          hexdot_s1_agent_rf_source_endofpacket;                                                        // hexdot_s1_agent:rf_source_endofpacket -> hexdot_s1_agent_rsp_fifo:in_endofpacket
	wire          hexdot_s1_agent_rsp_fifo_out_valid;                                                           // hexdot_s1_agent_rsp_fifo:out_valid -> hexdot_s1_agent:rf_sink_valid
	wire  [111:0] hexdot_s1_agent_rsp_fifo_out_data;                                                            // hexdot_s1_agent_rsp_fifo:out_data -> hexdot_s1_agent:rf_sink_data
	wire          hexdot_s1_agent_rsp_fifo_out_ready;                                                           // hexdot_s1_agent:rf_sink_ready -> hexdot_s1_agent_rsp_fifo:out_ready
	wire          hexdot_s1_agent_rsp_fifo_out_startofpacket;                                                   // hexdot_s1_agent_rsp_fifo:out_startofpacket -> hexdot_s1_agent:rf_sink_startofpacket
	wire          hexdot_s1_agent_rsp_fifo_out_endofpacket;                                                     // hexdot_s1_agent_rsp_fifo:out_endofpacket -> hexdot_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_019_src_valid;                                                                        // cmd_mux_019:src_valid -> hexdot_s1_agent:cp_valid
	wire  [110:0] cmd_mux_019_src_data;                                                                         // cmd_mux_019:src_data -> hexdot_s1_agent:cp_data
	wire          cmd_mux_019_src_ready;                                                                        // hexdot_s1_agent:cp_ready -> cmd_mux_019:src_ready
	wire   [22:0] cmd_mux_019_src_channel;                                                                      // cmd_mux_019:src_channel -> hexdot_s1_agent:cp_channel
	wire          cmd_mux_019_src_startofpacket;                                                                // cmd_mux_019:src_startofpacket -> hexdot_s1_agent:cp_startofpacket
	wire          cmd_mux_019_src_endofpacket;                                                                  // cmd_mux_019:src_endofpacket -> hexdot_s1_agent:cp_endofpacket
	wire   [31:0] spi_sync_s1_agent_m0_readdata;                                                                // spi_sync_s1_translator:uav_readdata -> spi_sync_s1_agent:m0_readdata
	wire          spi_sync_s1_agent_m0_waitrequest;                                                             // spi_sync_s1_translator:uav_waitrequest -> spi_sync_s1_agent:m0_waitrequest
	wire          spi_sync_s1_agent_m0_debugaccess;                                                             // spi_sync_s1_agent:m0_debugaccess -> spi_sync_s1_translator:uav_debugaccess
	wire   [27:0] spi_sync_s1_agent_m0_address;                                                                 // spi_sync_s1_agent:m0_address -> spi_sync_s1_translator:uav_address
	wire    [3:0] spi_sync_s1_agent_m0_byteenable;                                                              // spi_sync_s1_agent:m0_byteenable -> spi_sync_s1_translator:uav_byteenable
	wire          spi_sync_s1_agent_m0_read;                                                                    // spi_sync_s1_agent:m0_read -> spi_sync_s1_translator:uav_read
	wire          spi_sync_s1_agent_m0_readdatavalid;                                                           // spi_sync_s1_translator:uav_readdatavalid -> spi_sync_s1_agent:m0_readdatavalid
	wire          spi_sync_s1_agent_m0_lock;                                                                    // spi_sync_s1_agent:m0_lock -> spi_sync_s1_translator:uav_lock
	wire   [31:0] spi_sync_s1_agent_m0_writedata;                                                               // spi_sync_s1_agent:m0_writedata -> spi_sync_s1_translator:uav_writedata
	wire          spi_sync_s1_agent_m0_write;                                                                   // spi_sync_s1_agent:m0_write -> spi_sync_s1_translator:uav_write
	wire    [2:0] spi_sync_s1_agent_m0_burstcount;                                                              // spi_sync_s1_agent:m0_burstcount -> spi_sync_s1_translator:uav_burstcount
	wire          spi_sync_s1_agent_rf_source_valid;                                                            // spi_sync_s1_agent:rf_source_valid -> spi_sync_s1_agent_rsp_fifo:in_valid
	wire  [111:0] spi_sync_s1_agent_rf_source_data;                                                             // spi_sync_s1_agent:rf_source_data -> spi_sync_s1_agent_rsp_fifo:in_data
	wire          spi_sync_s1_agent_rf_source_ready;                                                            // spi_sync_s1_agent_rsp_fifo:in_ready -> spi_sync_s1_agent:rf_source_ready
	wire          spi_sync_s1_agent_rf_source_startofpacket;                                                    // spi_sync_s1_agent:rf_source_startofpacket -> spi_sync_s1_agent_rsp_fifo:in_startofpacket
	wire          spi_sync_s1_agent_rf_source_endofpacket;                                                      // spi_sync_s1_agent:rf_source_endofpacket -> spi_sync_s1_agent_rsp_fifo:in_endofpacket
	wire          spi_sync_s1_agent_rsp_fifo_out_valid;                                                         // spi_sync_s1_agent_rsp_fifo:out_valid -> spi_sync_s1_agent:rf_sink_valid
	wire  [111:0] spi_sync_s1_agent_rsp_fifo_out_data;                                                          // spi_sync_s1_agent_rsp_fifo:out_data -> spi_sync_s1_agent:rf_sink_data
	wire          spi_sync_s1_agent_rsp_fifo_out_ready;                                                         // spi_sync_s1_agent:rf_sink_ready -> spi_sync_s1_agent_rsp_fifo:out_ready
	wire          spi_sync_s1_agent_rsp_fifo_out_startofpacket;                                                 // spi_sync_s1_agent_rsp_fifo:out_startofpacket -> spi_sync_s1_agent:rf_sink_startofpacket
	wire          spi_sync_s1_agent_rsp_fifo_out_endofpacket;                                                   // spi_sync_s1_agent_rsp_fifo:out_endofpacket -> spi_sync_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_020_src_valid;                                                                        // cmd_mux_020:src_valid -> spi_sync_s1_agent:cp_valid
	wire  [110:0] cmd_mux_020_src_data;                                                                         // cmd_mux_020:src_data -> spi_sync_s1_agent:cp_data
	wire          cmd_mux_020_src_ready;                                                                        // spi_sync_s1_agent:cp_ready -> cmd_mux_020:src_ready
	wire   [22:0] cmd_mux_020_src_channel;                                                                      // cmd_mux_020:src_channel -> spi_sync_s1_agent:cp_channel
	wire          cmd_mux_020_src_startofpacket;                                                                // cmd_mux_020:src_startofpacket -> spi_sync_s1_agent:cp_startofpacket
	wire          cmd_mux_020_src_endofpacket;                                                                  // cmd_mux_020:src_endofpacket -> spi_sync_s1_agent:cp_endofpacket
	wire   [31:0] extra_leds_s1_agent_m0_readdata;                                                              // extra_leds_s1_translator:uav_readdata -> extra_leds_s1_agent:m0_readdata
	wire          extra_leds_s1_agent_m0_waitrequest;                                                           // extra_leds_s1_translator:uav_waitrequest -> extra_leds_s1_agent:m0_waitrequest
	wire          extra_leds_s1_agent_m0_debugaccess;                                                           // extra_leds_s1_agent:m0_debugaccess -> extra_leds_s1_translator:uav_debugaccess
	wire   [27:0] extra_leds_s1_agent_m0_address;                                                               // extra_leds_s1_agent:m0_address -> extra_leds_s1_translator:uav_address
	wire    [3:0] extra_leds_s1_agent_m0_byteenable;                                                            // extra_leds_s1_agent:m0_byteenable -> extra_leds_s1_translator:uav_byteenable
	wire          extra_leds_s1_agent_m0_read;                                                                  // extra_leds_s1_agent:m0_read -> extra_leds_s1_translator:uav_read
	wire          extra_leds_s1_agent_m0_readdatavalid;                                                         // extra_leds_s1_translator:uav_readdatavalid -> extra_leds_s1_agent:m0_readdatavalid
	wire          extra_leds_s1_agent_m0_lock;                                                                  // extra_leds_s1_agent:m0_lock -> extra_leds_s1_translator:uav_lock
	wire   [31:0] extra_leds_s1_agent_m0_writedata;                                                             // extra_leds_s1_agent:m0_writedata -> extra_leds_s1_translator:uav_writedata
	wire          extra_leds_s1_agent_m0_write;                                                                 // extra_leds_s1_agent:m0_write -> extra_leds_s1_translator:uav_write
	wire    [2:0] extra_leds_s1_agent_m0_burstcount;                                                            // extra_leds_s1_agent:m0_burstcount -> extra_leds_s1_translator:uav_burstcount
	wire          extra_leds_s1_agent_rf_source_valid;                                                          // extra_leds_s1_agent:rf_source_valid -> extra_leds_s1_agent_rsp_fifo:in_valid
	wire  [111:0] extra_leds_s1_agent_rf_source_data;                                                           // extra_leds_s1_agent:rf_source_data -> extra_leds_s1_agent_rsp_fifo:in_data
	wire          extra_leds_s1_agent_rf_source_ready;                                                          // extra_leds_s1_agent_rsp_fifo:in_ready -> extra_leds_s1_agent:rf_source_ready
	wire          extra_leds_s1_agent_rf_source_startofpacket;                                                  // extra_leds_s1_agent:rf_source_startofpacket -> extra_leds_s1_agent_rsp_fifo:in_startofpacket
	wire          extra_leds_s1_agent_rf_source_endofpacket;                                                    // extra_leds_s1_agent:rf_source_endofpacket -> extra_leds_s1_agent_rsp_fifo:in_endofpacket
	wire          extra_leds_s1_agent_rsp_fifo_out_valid;                                                       // extra_leds_s1_agent_rsp_fifo:out_valid -> extra_leds_s1_agent:rf_sink_valid
	wire  [111:0] extra_leds_s1_agent_rsp_fifo_out_data;                                                        // extra_leds_s1_agent_rsp_fifo:out_data -> extra_leds_s1_agent:rf_sink_data
	wire          extra_leds_s1_agent_rsp_fifo_out_ready;                                                       // extra_leds_s1_agent:rf_sink_ready -> extra_leds_s1_agent_rsp_fifo:out_ready
	wire          extra_leds_s1_agent_rsp_fifo_out_startofpacket;                                               // extra_leds_s1_agent_rsp_fifo:out_startofpacket -> extra_leds_s1_agent:rf_sink_startofpacket
	wire          extra_leds_s1_agent_rsp_fifo_out_endofpacket;                                                 // extra_leds_s1_agent_rsp_fifo:out_endofpacket -> extra_leds_s1_agent:rf_sink_endofpacket
	wire          cmd_mux_021_src_valid;                                                                        // cmd_mux_021:src_valid -> extra_leds_s1_agent:cp_valid
	wire  [110:0] cmd_mux_021_src_data;                                                                         // cmd_mux_021:src_data -> extra_leds_s1_agent:cp_data
	wire          cmd_mux_021_src_ready;                                                                        // extra_leds_s1_agent:cp_ready -> cmd_mux_021:src_ready
	wire   [22:0] cmd_mux_021_src_channel;                                                                      // cmd_mux_021:src_channel -> extra_leds_s1_agent:cp_channel
	wire          cmd_mux_021_src_startofpacket;                                                                // cmd_mux_021:src_startofpacket -> extra_leds_s1_agent:cp_startofpacket
	wire          cmd_mux_021_src_endofpacket;                                                                  // cmd_mux_021:src_endofpacket -> extra_leds_s1_agent:cp_endofpacket
	wire   [31:0] spi_stm32_spi_control_port_agent_m0_readdata;                                                 // spi_stm32_spi_control_port_translator:uav_readdata -> spi_stm32_spi_control_port_agent:m0_readdata
	wire          spi_stm32_spi_control_port_agent_m0_waitrequest;                                              // spi_stm32_spi_control_port_translator:uav_waitrequest -> spi_stm32_spi_control_port_agent:m0_waitrequest
	wire          spi_stm32_spi_control_port_agent_m0_debugaccess;                                              // spi_stm32_spi_control_port_agent:m0_debugaccess -> spi_stm32_spi_control_port_translator:uav_debugaccess
	wire   [27:0] spi_stm32_spi_control_port_agent_m0_address;                                                  // spi_stm32_spi_control_port_agent:m0_address -> spi_stm32_spi_control_port_translator:uav_address
	wire    [3:0] spi_stm32_spi_control_port_agent_m0_byteenable;                                               // spi_stm32_spi_control_port_agent:m0_byteenable -> spi_stm32_spi_control_port_translator:uav_byteenable
	wire          spi_stm32_spi_control_port_agent_m0_read;                                                     // spi_stm32_spi_control_port_agent:m0_read -> spi_stm32_spi_control_port_translator:uav_read
	wire          spi_stm32_spi_control_port_agent_m0_readdatavalid;                                            // spi_stm32_spi_control_port_translator:uav_readdatavalid -> spi_stm32_spi_control_port_agent:m0_readdatavalid
	wire          spi_stm32_spi_control_port_agent_m0_lock;                                                     // spi_stm32_spi_control_port_agent:m0_lock -> spi_stm32_spi_control_port_translator:uav_lock
	wire   [31:0] spi_stm32_spi_control_port_agent_m0_writedata;                                                // spi_stm32_spi_control_port_agent:m0_writedata -> spi_stm32_spi_control_port_translator:uav_writedata
	wire          spi_stm32_spi_control_port_agent_m0_write;                                                    // spi_stm32_spi_control_port_agent:m0_write -> spi_stm32_spi_control_port_translator:uav_write
	wire    [2:0] spi_stm32_spi_control_port_agent_m0_burstcount;                                               // spi_stm32_spi_control_port_agent:m0_burstcount -> spi_stm32_spi_control_port_translator:uav_burstcount
	wire          spi_stm32_spi_control_port_agent_rf_source_valid;                                             // spi_stm32_spi_control_port_agent:rf_source_valid -> spi_stm32_spi_control_port_agent_rsp_fifo:in_valid
	wire  [111:0] spi_stm32_spi_control_port_agent_rf_source_data;                                              // spi_stm32_spi_control_port_agent:rf_source_data -> spi_stm32_spi_control_port_agent_rsp_fifo:in_data
	wire          spi_stm32_spi_control_port_agent_rf_source_ready;                                             // spi_stm32_spi_control_port_agent_rsp_fifo:in_ready -> spi_stm32_spi_control_port_agent:rf_source_ready
	wire          spi_stm32_spi_control_port_agent_rf_source_startofpacket;                                     // spi_stm32_spi_control_port_agent:rf_source_startofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_startofpacket
	wire          spi_stm32_spi_control_port_agent_rf_source_endofpacket;                                       // spi_stm32_spi_control_port_agent:rf_source_endofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_endofpacket
	wire          spi_stm32_spi_control_port_agent_rsp_fifo_out_valid;                                          // spi_stm32_spi_control_port_agent_rsp_fifo:out_valid -> spi_stm32_spi_control_port_agent:rf_sink_valid
	wire  [111:0] spi_stm32_spi_control_port_agent_rsp_fifo_out_data;                                           // spi_stm32_spi_control_port_agent_rsp_fifo:out_data -> spi_stm32_spi_control_port_agent:rf_sink_data
	wire          spi_stm32_spi_control_port_agent_rsp_fifo_out_ready;                                          // spi_stm32_spi_control_port_agent:rf_sink_ready -> spi_stm32_spi_control_port_agent_rsp_fifo:out_ready
	wire          spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket;                                  // spi_stm32_spi_control_port_agent_rsp_fifo:out_startofpacket -> spi_stm32_spi_control_port_agent:rf_sink_startofpacket
	wire          spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket;                                    // spi_stm32_spi_control_port_agent_rsp_fifo:out_endofpacket -> spi_stm32_spi_control_port_agent:rf_sink_endofpacket
	wire          cmd_mux_022_src_valid;                                                                        // cmd_mux_022:src_valid -> spi_stm32_spi_control_port_agent:cp_valid
	wire  [110:0] cmd_mux_022_src_data;                                                                         // cmd_mux_022:src_data -> spi_stm32_spi_control_port_agent:cp_data
	wire          cmd_mux_022_src_ready;                                                                        // spi_stm32_spi_control_port_agent:cp_ready -> cmd_mux_022:src_ready
	wire   [22:0] cmd_mux_022_src_channel;                                                                      // cmd_mux_022:src_channel -> spi_stm32_spi_control_port_agent:cp_channel
	wire          cmd_mux_022_src_startofpacket;                                                                // cmd_mux_022:src_startofpacket -> spi_stm32_spi_control_port_agent:cp_startofpacket
	wire          cmd_mux_022_src_endofpacket;                                                                  // cmd_mux_022:src_endofpacket -> spi_stm32_spi_control_port_agent:cp_endofpacket
	wire          abus_slave_0_avalon_master_agent_cp_valid;                                                    // abus_slave_0_avalon_master_agent:cp_valid -> router:sink_valid
	wire   [92:0] abus_slave_0_avalon_master_agent_cp_data;                                                     // abus_slave_0_avalon_master_agent:cp_data -> router:sink_data
	wire          abus_slave_0_avalon_master_agent_cp_ready;                                                    // router:sink_ready -> abus_slave_0_avalon_master_agent:cp_ready
	wire          abus_slave_0_avalon_master_agent_cp_startofpacket;                                            // abus_slave_0_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          abus_slave_0_avalon_master_agent_cp_endofpacket;                                              // abus_slave_0_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          nios2_gen2_0_data_master_agent_cp_valid;                                                      // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
	wire  [110:0] nios2_gen2_0_data_master_agent_cp_data;                                                       // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
	wire          nios2_gen2_0_data_master_agent_cp_ready;                                                      // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
	wire          nios2_gen2_0_data_master_agent_cp_startofpacket;                                              // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          nios2_gen2_0_data_master_agent_cp_endofpacket;                                                // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                         // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [110:0] router_001_src_data;                                                                          // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                                         // cmd_demux_001:sink_ready -> router_001:src_ready
	wire   [22:0] router_001_src_channel;                                                                       // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                                                 // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                                   // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          nios2_gen2_0_instruction_master_agent_cp_valid;                                               // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
	wire  [110:0] nios2_gen2_0_instruction_master_agent_cp_data;                                                // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
	wire          nios2_gen2_0_instruction_master_agent_cp_ready;                                               // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
	wire          nios2_gen2_0_instruction_master_agent_cp_startofpacket;                                       // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
	wire          nios2_gen2_0_instruction_master_agent_cp_endofpacket;                                         // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                                         // router_002:src_valid -> cmd_demux_002:sink_valid
	wire  [110:0] router_002_src_data;                                                                          // router_002:src_data -> cmd_demux_002:sink_data
	wire          router_002_src_ready;                                                                         // cmd_demux_002:sink_ready -> router_002:src_ready
	wire   [22:0] router_002_src_channel;                                                                       // router_002:src_channel -> cmd_demux_002:sink_channel
	wire          router_002_src_startofpacket;                                                                 // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          router_002_src_endofpacket;                                                                   // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          external_sdram_controller_s1_agent_rp_valid;                                                  // external_sdram_controller_s1_agent:rp_valid -> router_003:sink_valid
	wire   [92:0] external_sdram_controller_s1_agent_rp_data;                                                   // external_sdram_controller_s1_agent:rp_data -> router_003:sink_data
	wire          external_sdram_controller_s1_agent_rp_ready;                                                  // router_003:sink_ready -> external_sdram_controller_s1_agent:rp_ready
	wire          external_sdram_controller_s1_agent_rp_startofpacket;                                          // external_sdram_controller_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          external_sdram_controller_s1_agent_rp_endofpacket;                                            // external_sdram_controller_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                                                         // router_003:src_valid -> rsp_demux:sink_valid
	wire   [92:0] router_003_src_data;                                                                          // router_003:src_data -> rsp_demux:sink_data
	wire          router_003_src_ready;                                                                         // rsp_demux:sink_ready -> router_003:src_ready
	wire   [22:0] router_003_src_channel;                                                                       // router_003:src_channel -> rsp_demux:sink_channel
	wire          router_003_src_startofpacket;                                                                 // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_003_src_endofpacket;                                                                   // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          onchip_memory2_1_s1_agent_rp_valid;                                                           // onchip_memory2_1_s1_agent:rp_valid -> router_004:sink_valid
	wire  [110:0] onchip_memory2_1_s1_agent_rp_data;                                                            // onchip_memory2_1_s1_agent:rp_data -> router_004:sink_data
	wire          onchip_memory2_1_s1_agent_rp_ready;                                                           // router_004:sink_ready -> onchip_memory2_1_s1_agent:rp_ready
	wire          onchip_memory2_1_s1_agent_rp_startofpacket;                                                   // onchip_memory2_1_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          onchip_memory2_1_s1_agent_rp_endofpacket;                                                     // onchip_memory2_1_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                                         // router_004:src_valid -> rsp_demux_001:sink_valid
	wire  [110:0] router_004_src_data;                                                                          // router_004:src_data -> rsp_demux_001:sink_data
	wire          router_004_src_ready;                                                                         // rsp_demux_001:sink_ready -> router_004:src_ready
	wire   [22:0] router_004_src_channel;                                                                       // router_004:src_channel -> rsp_demux_001:sink_channel
	wire          router_004_src_startofpacket;                                                                 // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_004_src_endofpacket;                                                                   // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          abus_slave_0_avalon_nios_agent_rp_valid;                                                      // abus_slave_0_avalon_nios_agent:rp_valid -> router_005:sink_valid
	wire  [110:0] abus_slave_0_avalon_nios_agent_rp_data;                                                       // abus_slave_0_avalon_nios_agent:rp_data -> router_005:sink_data
	wire          abus_slave_0_avalon_nios_agent_rp_ready;                                                      // router_005:sink_ready -> abus_slave_0_avalon_nios_agent:rp_ready
	wire          abus_slave_0_avalon_nios_agent_rp_startofpacket;                                              // abus_slave_0_avalon_nios_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          abus_slave_0_avalon_nios_agent_rp_endofpacket;                                                // abus_slave_0_avalon_nios_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                                         // router_005:src_valid -> rsp_demux_002:sink_valid
	wire  [110:0] router_005_src_data;                                                                          // router_005:src_data -> rsp_demux_002:sink_data
	wire          router_005_src_ready;                                                                         // rsp_demux_002:sink_ready -> router_005:src_ready
	wire   [22:0] router_005_src_channel;                                                                       // router_005:src_channel -> rsp_demux_002:sink_channel
	wire          router_005_src_startofpacket;                                                                 // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_005_src_endofpacket;                                                                   // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          abus_demux_0_avalon_nios_agent_rp_valid;                                                      // abus_demux_0_avalon_nios_agent:rp_valid -> router_006:sink_valid
	wire  [110:0] abus_demux_0_avalon_nios_agent_rp_data;                                                       // abus_demux_0_avalon_nios_agent:rp_data -> router_006:sink_data
	wire          abus_demux_0_avalon_nios_agent_rp_ready;                                                      // router_006:sink_ready -> abus_demux_0_avalon_nios_agent:rp_ready
	wire          abus_demux_0_avalon_nios_agent_rp_startofpacket;                                              // abus_demux_0_avalon_nios_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          abus_demux_0_avalon_nios_agent_rp_endofpacket;                                                // abus_demux_0_avalon_nios_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                                         // router_006:src_valid -> rsp_demux_003:sink_valid
	wire  [110:0] router_006_src_data;                                                                          // router_006:src_data -> rsp_demux_003:sink_data
	wire          router_006_src_ready;                                                                         // rsp_demux_003:sink_ready -> router_006:src_ready
	wire   [22:0] router_006_src_channel;                                                                       // router_006:src_channel -> rsp_demux_003:sink_channel
	wire          router_006_src_startofpacket;                                                                 // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_006_src_endofpacket;                                                                   // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          performance_counter_0_control_slave_agent_rp_valid;                                           // performance_counter_0_control_slave_agent:rp_valid -> router_007:sink_valid
	wire  [110:0] performance_counter_0_control_slave_agent_rp_data;                                            // performance_counter_0_control_slave_agent:rp_data -> router_007:sink_data
	wire          performance_counter_0_control_slave_agent_rp_ready;                                           // router_007:sink_ready -> performance_counter_0_control_slave_agent:rp_ready
	wire          performance_counter_0_control_slave_agent_rp_startofpacket;                                   // performance_counter_0_control_slave_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          performance_counter_0_control_slave_agent_rp_endofpacket;                                     // performance_counter_0_control_slave_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                                         // router_007:src_valid -> rsp_demux_004:sink_valid
	wire  [110:0] router_007_src_data;                                                                          // router_007:src_data -> rsp_demux_004:sink_data
	wire          router_007_src_ready;                                                                         // rsp_demux_004:sink_ready -> router_007:src_ready
	wire   [22:0] router_007_src_channel;                                                                       // router_007:src_channel -> rsp_demux_004:sink_channel
	wire          router_007_src_startofpacket;                                                                 // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_007_src_endofpacket;                                                                   // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          onchip_flash_0_csr_agent_rp_valid;                                                            // onchip_flash_0_csr_agent:rp_valid -> router_008:sink_valid
	wire  [110:0] onchip_flash_0_csr_agent_rp_data;                                                             // onchip_flash_0_csr_agent:rp_data -> router_008:sink_data
	wire          onchip_flash_0_csr_agent_rp_ready;                                                            // router_008:sink_ready -> onchip_flash_0_csr_agent:rp_ready
	wire          onchip_flash_0_csr_agent_rp_startofpacket;                                                    // onchip_flash_0_csr_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          onchip_flash_0_csr_agent_rp_endofpacket;                                                      // onchip_flash_0_csr_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                                                         // router_008:src_valid -> rsp_demux_005:sink_valid
	wire  [110:0] router_008_src_data;                                                                          // router_008:src_data -> rsp_demux_005:sink_data
	wire          router_008_src_ready;                                                                         // rsp_demux_005:sink_ready -> router_008:src_ready
	wire   [22:0] router_008_src_channel;                                                                       // router_008:src_channel -> rsp_demux_005:sink_channel
	wire          router_008_src_startofpacket;                                                                 // router_008:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_008_src_endofpacket;                                                                   // router_008:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          onchip_flash_0_data_agent_rp_valid;                                                           // onchip_flash_0_data_agent:rp_valid -> router_009:sink_valid
	wire  [110:0] onchip_flash_0_data_agent_rp_data;                                                            // onchip_flash_0_data_agent:rp_data -> router_009:sink_data
	wire          onchip_flash_0_data_agent_rp_ready;                                                           // router_009:sink_ready -> onchip_flash_0_data_agent:rp_ready
	wire          onchip_flash_0_data_agent_rp_startofpacket;                                                   // onchip_flash_0_data_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire          onchip_flash_0_data_agent_rp_endofpacket;                                                     // onchip_flash_0_data_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire          router_009_src_valid;                                                                         // router_009:src_valid -> rsp_demux_006:sink_valid
	wire  [110:0] router_009_src_data;                                                                          // router_009:src_data -> rsp_demux_006:sink_data
	wire          router_009_src_ready;                                                                         // rsp_demux_006:sink_ready -> router_009:src_ready
	wire   [22:0] router_009_src_channel;                                                                       // router_009:src_channel -> rsp_demux_006:sink_channel
	wire          router_009_src_startofpacket;                                                                 // router_009:src_startofpacket -> rsp_demux_006:sink_startofpacket
	wire          router_009_src_endofpacket;                                                                   // router_009:src_endofpacket -> rsp_demux_006:sink_endofpacket
	wire          nios2_gen2_0_debug_mem_slave_agent_rp_valid;                                                  // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_010:sink_valid
	wire  [110:0] nios2_gen2_0_debug_mem_slave_agent_rp_data;                                                   // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_010:sink_data
	wire          nios2_gen2_0_debug_mem_slave_agent_rp_ready;                                                  // router_010:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
	wire          nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket;                                          // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_010:sink_startofpacket
	wire          nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket;                                            // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_010:sink_endofpacket
	wire          router_010_src_valid;                                                                         // router_010:src_valid -> rsp_demux_007:sink_valid
	wire  [110:0] router_010_src_data;                                                                          // router_010:src_data -> rsp_demux_007:sink_data
	wire          router_010_src_ready;                                                                         // rsp_demux_007:sink_ready -> router_010:src_ready
	wire   [22:0] router_010_src_channel;                                                                       // router_010:src_channel -> rsp_demux_007:sink_channel
	wire          router_010_src_startofpacket;                                                                 // router_010:src_startofpacket -> rsp_demux_007:sink_startofpacket
	wire          router_010_src_endofpacket;                                                                   // router_010:src_endofpacket -> rsp_demux_007:sink_endofpacket
	wire          altpll_0_pll_slave_agent_rp_valid;                                                            // altpll_0_pll_slave_agent:rp_valid -> router_011:sink_valid
	wire  [110:0] altpll_0_pll_slave_agent_rp_data;                                                             // altpll_0_pll_slave_agent:rp_data -> router_011:sink_data
	wire          altpll_0_pll_slave_agent_rp_ready;                                                            // router_011:sink_ready -> altpll_0_pll_slave_agent:rp_ready
	wire          altpll_0_pll_slave_agent_rp_startofpacket;                                                    // altpll_0_pll_slave_agent:rp_startofpacket -> router_011:sink_startofpacket
	wire          altpll_0_pll_slave_agent_rp_endofpacket;                                                      // altpll_0_pll_slave_agent:rp_endofpacket -> router_011:sink_endofpacket
	wire          router_011_src_valid;                                                                         // router_011:src_valid -> rsp_demux_008:sink_valid
	wire  [110:0] router_011_src_data;                                                                          // router_011:src_data -> rsp_demux_008:sink_data
	wire          router_011_src_ready;                                                                         // rsp_demux_008:sink_ready -> router_011:src_ready
	wire   [22:0] router_011_src_channel;                                                                       // router_011:src_channel -> rsp_demux_008:sink_channel
	wire          router_011_src_startofpacket;                                                                 // router_011:src_startofpacket -> rsp_demux_008:sink_startofpacket
	wire          router_011_src_endofpacket;                                                                   // router_011:src_endofpacket -> rsp_demux_008:sink_endofpacket
	wire          onchip_memory2_0_s1_agent_rp_valid;                                                           // onchip_memory2_0_s1_agent:rp_valid -> router_012:sink_valid
	wire  [110:0] onchip_memory2_0_s1_agent_rp_data;                                                            // onchip_memory2_0_s1_agent:rp_data -> router_012:sink_data
	wire          onchip_memory2_0_s1_agent_rp_ready;                                                           // router_012:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
	wire          onchip_memory2_0_s1_agent_rp_startofpacket;                                                   // onchip_memory2_0_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
	wire          onchip_memory2_0_s1_agent_rp_endofpacket;                                                     // onchip_memory2_0_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
	wire          router_012_src_valid;                                                                         // router_012:src_valid -> rsp_demux_009:sink_valid
	wire  [110:0] router_012_src_data;                                                                          // router_012:src_data -> rsp_demux_009:sink_data
	wire          router_012_src_ready;                                                                         // rsp_demux_009:sink_ready -> router_012:src_ready
	wire   [22:0] router_012_src_channel;                                                                       // router_012:src_channel -> rsp_demux_009:sink_channel
	wire          router_012_src_startofpacket;                                                                 // router_012:src_startofpacket -> rsp_demux_009:sink_startofpacket
	wire          router_012_src_endofpacket;                                                                   // router_012:src_endofpacket -> rsp_demux_009:sink_endofpacket
	wire          switches_s1_agent_rp_valid;                                                                   // switches_s1_agent:rp_valid -> router_013:sink_valid
	wire  [110:0] switches_s1_agent_rp_data;                                                                    // switches_s1_agent:rp_data -> router_013:sink_data
	wire          switches_s1_agent_rp_ready;                                                                   // router_013:sink_ready -> switches_s1_agent:rp_ready
	wire          switches_s1_agent_rp_startofpacket;                                                           // switches_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
	wire          switches_s1_agent_rp_endofpacket;                                                             // switches_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
	wire          router_013_src_valid;                                                                         // router_013:src_valid -> rsp_demux_010:sink_valid
	wire  [110:0] router_013_src_data;                                                                          // router_013:src_data -> rsp_demux_010:sink_data
	wire          router_013_src_ready;                                                                         // rsp_demux_010:sink_ready -> router_013:src_ready
	wire   [22:0] router_013_src_channel;                                                                       // router_013:src_channel -> rsp_demux_010:sink_channel
	wire          router_013_src_startofpacket;                                                                 // router_013:src_startofpacket -> rsp_demux_010:sink_startofpacket
	wire          router_013_src_endofpacket;                                                                   // router_013:src_endofpacket -> rsp_demux_010:sink_endofpacket
	wire          leds_s1_agent_rp_valid;                                                                       // leds_s1_agent:rp_valid -> router_014:sink_valid
	wire  [110:0] leds_s1_agent_rp_data;                                                                        // leds_s1_agent:rp_data -> router_014:sink_data
	wire          leds_s1_agent_rp_ready;                                                                       // router_014:sink_ready -> leds_s1_agent:rp_ready
	wire          leds_s1_agent_rp_startofpacket;                                                               // leds_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
	wire          leds_s1_agent_rp_endofpacket;                                                                 // leds_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
	wire          router_014_src_valid;                                                                         // router_014:src_valid -> rsp_demux_011:sink_valid
	wire  [110:0] router_014_src_data;                                                                          // router_014:src_data -> rsp_demux_011:sink_data
	wire          router_014_src_ready;                                                                         // rsp_demux_011:sink_ready -> router_014:src_ready
	wire   [22:0] router_014_src_channel;                                                                       // router_014:src_channel -> rsp_demux_011:sink_channel
	wire          router_014_src_startofpacket;                                                                 // router_014:src_startofpacket -> rsp_demux_011:sink_startofpacket
	wire          router_014_src_endofpacket;                                                                   // router_014:src_endofpacket -> rsp_demux_011:sink_endofpacket
	wire          uart_0_s1_agent_rp_valid;                                                                     // uart_0_s1_agent:rp_valid -> router_015:sink_valid
	wire  [110:0] uart_0_s1_agent_rp_data;                                                                      // uart_0_s1_agent:rp_data -> router_015:sink_data
	wire          uart_0_s1_agent_rp_ready;                                                                     // router_015:sink_ready -> uart_0_s1_agent:rp_ready
	wire          uart_0_s1_agent_rp_startofpacket;                                                             // uart_0_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
	wire          uart_0_s1_agent_rp_endofpacket;                                                               // uart_0_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
	wire          router_015_src_valid;                                                                         // router_015:src_valid -> rsp_demux_012:sink_valid
	wire  [110:0] router_015_src_data;                                                                          // router_015:src_data -> rsp_demux_012:sink_data
	wire          router_015_src_ready;                                                                         // rsp_demux_012:sink_ready -> router_015:src_ready
	wire   [22:0] router_015_src_channel;                                                                       // router_015:src_channel -> rsp_demux_012:sink_channel
	wire          router_015_src_startofpacket;                                                                 // router_015:src_startofpacket -> rsp_demux_012:sink_startofpacket
	wire          router_015_src_endofpacket;                                                                   // router_015:src_endofpacket -> rsp_demux_012:sink_endofpacket
	wire          hex0_s1_agent_rp_valid;                                                                       // hex0_s1_agent:rp_valid -> router_016:sink_valid
	wire  [110:0] hex0_s1_agent_rp_data;                                                                        // hex0_s1_agent:rp_data -> router_016:sink_data
	wire          hex0_s1_agent_rp_ready;                                                                       // router_016:sink_ready -> hex0_s1_agent:rp_ready
	wire          hex0_s1_agent_rp_startofpacket;                                                               // hex0_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
	wire          hex0_s1_agent_rp_endofpacket;                                                                 // hex0_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
	wire          router_016_src_valid;                                                                         // router_016:src_valid -> rsp_demux_013:sink_valid
	wire  [110:0] router_016_src_data;                                                                          // router_016:src_data -> rsp_demux_013:sink_data
	wire          router_016_src_ready;                                                                         // rsp_demux_013:sink_ready -> router_016:src_ready
	wire   [22:0] router_016_src_channel;                                                                       // router_016:src_channel -> rsp_demux_013:sink_channel
	wire          router_016_src_startofpacket;                                                                 // router_016:src_startofpacket -> rsp_demux_013:sink_startofpacket
	wire          router_016_src_endofpacket;                                                                   // router_016:src_endofpacket -> rsp_demux_013:sink_endofpacket
	wire          hex1_s1_agent_rp_valid;                                                                       // hex1_s1_agent:rp_valid -> router_017:sink_valid
	wire  [110:0] hex1_s1_agent_rp_data;                                                                        // hex1_s1_agent:rp_data -> router_017:sink_data
	wire          hex1_s1_agent_rp_ready;                                                                       // router_017:sink_ready -> hex1_s1_agent:rp_ready
	wire          hex1_s1_agent_rp_startofpacket;                                                               // hex1_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
	wire          hex1_s1_agent_rp_endofpacket;                                                                 // hex1_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
	wire          router_017_src_valid;                                                                         // router_017:src_valid -> rsp_demux_014:sink_valid
	wire  [110:0] router_017_src_data;                                                                          // router_017:src_data -> rsp_demux_014:sink_data
	wire          router_017_src_ready;                                                                         // rsp_demux_014:sink_ready -> router_017:src_ready
	wire   [22:0] router_017_src_channel;                                                                       // router_017:src_channel -> rsp_demux_014:sink_channel
	wire          router_017_src_startofpacket;                                                                 // router_017:src_startofpacket -> rsp_demux_014:sink_startofpacket
	wire          router_017_src_endofpacket;                                                                   // router_017:src_endofpacket -> rsp_demux_014:sink_endofpacket
	wire          hex2_s1_agent_rp_valid;                                                                       // hex2_s1_agent:rp_valid -> router_018:sink_valid
	wire  [110:0] hex2_s1_agent_rp_data;                                                                        // hex2_s1_agent:rp_data -> router_018:sink_data
	wire          hex2_s1_agent_rp_ready;                                                                       // router_018:sink_ready -> hex2_s1_agent:rp_ready
	wire          hex2_s1_agent_rp_startofpacket;                                                               // hex2_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
	wire          hex2_s1_agent_rp_endofpacket;                                                                 // hex2_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
	wire          router_018_src_valid;                                                                         // router_018:src_valid -> rsp_demux_015:sink_valid
	wire  [110:0] router_018_src_data;                                                                          // router_018:src_data -> rsp_demux_015:sink_data
	wire          router_018_src_ready;                                                                         // rsp_demux_015:sink_ready -> router_018:src_ready
	wire   [22:0] router_018_src_channel;                                                                       // router_018:src_channel -> rsp_demux_015:sink_channel
	wire          router_018_src_startofpacket;                                                                 // router_018:src_startofpacket -> rsp_demux_015:sink_startofpacket
	wire          router_018_src_endofpacket;                                                                   // router_018:src_endofpacket -> rsp_demux_015:sink_endofpacket
	wire          hex3_s1_agent_rp_valid;                                                                       // hex3_s1_agent:rp_valid -> router_019:sink_valid
	wire  [110:0] hex3_s1_agent_rp_data;                                                                        // hex3_s1_agent:rp_data -> router_019:sink_data
	wire          hex3_s1_agent_rp_ready;                                                                       // router_019:sink_ready -> hex3_s1_agent:rp_ready
	wire          hex3_s1_agent_rp_startofpacket;                                                               // hex3_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
	wire          hex3_s1_agent_rp_endofpacket;                                                                 // hex3_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
	wire          router_019_src_valid;                                                                         // router_019:src_valid -> rsp_demux_016:sink_valid
	wire  [110:0] router_019_src_data;                                                                          // router_019:src_data -> rsp_demux_016:sink_data
	wire          router_019_src_ready;                                                                         // rsp_demux_016:sink_ready -> router_019:src_ready
	wire   [22:0] router_019_src_channel;                                                                       // router_019:src_channel -> rsp_demux_016:sink_channel
	wire          router_019_src_startofpacket;                                                                 // router_019:src_startofpacket -> rsp_demux_016:sink_startofpacket
	wire          router_019_src_endofpacket;                                                                   // router_019:src_endofpacket -> rsp_demux_016:sink_endofpacket
	wire          hex4_s1_agent_rp_valid;                                                                       // hex4_s1_agent:rp_valid -> router_020:sink_valid
	wire  [110:0] hex4_s1_agent_rp_data;                                                                        // hex4_s1_agent:rp_data -> router_020:sink_data
	wire          hex4_s1_agent_rp_ready;                                                                       // router_020:sink_ready -> hex4_s1_agent:rp_ready
	wire          hex4_s1_agent_rp_startofpacket;                                                               // hex4_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
	wire          hex4_s1_agent_rp_endofpacket;                                                                 // hex4_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
	wire          router_020_src_valid;                                                                         // router_020:src_valid -> rsp_demux_017:sink_valid
	wire  [110:0] router_020_src_data;                                                                          // router_020:src_data -> rsp_demux_017:sink_data
	wire          router_020_src_ready;                                                                         // rsp_demux_017:sink_ready -> router_020:src_ready
	wire   [22:0] router_020_src_channel;                                                                       // router_020:src_channel -> rsp_demux_017:sink_channel
	wire          router_020_src_startofpacket;                                                                 // router_020:src_startofpacket -> rsp_demux_017:sink_startofpacket
	wire          router_020_src_endofpacket;                                                                   // router_020:src_endofpacket -> rsp_demux_017:sink_endofpacket
	wire          hex5_s1_agent_rp_valid;                                                                       // hex5_s1_agent:rp_valid -> router_021:sink_valid
	wire  [110:0] hex5_s1_agent_rp_data;                                                                        // hex5_s1_agent:rp_data -> router_021:sink_data
	wire          hex5_s1_agent_rp_ready;                                                                       // router_021:sink_ready -> hex5_s1_agent:rp_ready
	wire          hex5_s1_agent_rp_startofpacket;                                                               // hex5_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
	wire          hex5_s1_agent_rp_endofpacket;                                                                 // hex5_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
	wire          router_021_src_valid;                                                                         // router_021:src_valid -> rsp_demux_018:sink_valid
	wire  [110:0] router_021_src_data;                                                                          // router_021:src_data -> rsp_demux_018:sink_data
	wire          router_021_src_ready;                                                                         // rsp_demux_018:sink_ready -> router_021:src_ready
	wire   [22:0] router_021_src_channel;                                                                       // router_021:src_channel -> rsp_demux_018:sink_channel
	wire          router_021_src_startofpacket;                                                                 // router_021:src_startofpacket -> rsp_demux_018:sink_startofpacket
	wire          router_021_src_endofpacket;                                                                   // router_021:src_endofpacket -> rsp_demux_018:sink_endofpacket
	wire          hexdot_s1_agent_rp_valid;                                                                     // hexdot_s1_agent:rp_valid -> router_022:sink_valid
	wire  [110:0] hexdot_s1_agent_rp_data;                                                                      // hexdot_s1_agent:rp_data -> router_022:sink_data
	wire          hexdot_s1_agent_rp_ready;                                                                     // router_022:sink_ready -> hexdot_s1_agent:rp_ready
	wire          hexdot_s1_agent_rp_startofpacket;                                                             // hexdot_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
	wire          hexdot_s1_agent_rp_endofpacket;                                                               // hexdot_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
	wire          router_022_src_valid;                                                                         // router_022:src_valid -> rsp_demux_019:sink_valid
	wire  [110:0] router_022_src_data;                                                                          // router_022:src_data -> rsp_demux_019:sink_data
	wire          router_022_src_ready;                                                                         // rsp_demux_019:sink_ready -> router_022:src_ready
	wire   [22:0] router_022_src_channel;                                                                       // router_022:src_channel -> rsp_demux_019:sink_channel
	wire          router_022_src_startofpacket;                                                                 // router_022:src_startofpacket -> rsp_demux_019:sink_startofpacket
	wire          router_022_src_endofpacket;                                                                   // router_022:src_endofpacket -> rsp_demux_019:sink_endofpacket
	wire          spi_sync_s1_agent_rp_valid;                                                                   // spi_sync_s1_agent:rp_valid -> router_023:sink_valid
	wire  [110:0] spi_sync_s1_agent_rp_data;                                                                    // spi_sync_s1_agent:rp_data -> router_023:sink_data
	wire          spi_sync_s1_agent_rp_ready;                                                                   // router_023:sink_ready -> spi_sync_s1_agent:rp_ready
	wire          spi_sync_s1_agent_rp_startofpacket;                                                           // spi_sync_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
	wire          spi_sync_s1_agent_rp_endofpacket;                                                             // spi_sync_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
	wire          router_023_src_valid;                                                                         // router_023:src_valid -> rsp_demux_020:sink_valid
	wire  [110:0] router_023_src_data;                                                                          // router_023:src_data -> rsp_demux_020:sink_data
	wire          router_023_src_ready;                                                                         // rsp_demux_020:sink_ready -> router_023:src_ready
	wire   [22:0] router_023_src_channel;                                                                       // router_023:src_channel -> rsp_demux_020:sink_channel
	wire          router_023_src_startofpacket;                                                                 // router_023:src_startofpacket -> rsp_demux_020:sink_startofpacket
	wire          router_023_src_endofpacket;                                                                   // router_023:src_endofpacket -> rsp_demux_020:sink_endofpacket
	wire          extra_leds_s1_agent_rp_valid;                                                                 // extra_leds_s1_agent:rp_valid -> router_024:sink_valid
	wire  [110:0] extra_leds_s1_agent_rp_data;                                                                  // extra_leds_s1_agent:rp_data -> router_024:sink_data
	wire          extra_leds_s1_agent_rp_ready;                                                                 // router_024:sink_ready -> extra_leds_s1_agent:rp_ready
	wire          extra_leds_s1_agent_rp_startofpacket;                                                         // extra_leds_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
	wire          extra_leds_s1_agent_rp_endofpacket;                                                           // extra_leds_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
	wire          router_024_src_valid;                                                                         // router_024:src_valid -> rsp_demux_021:sink_valid
	wire  [110:0] router_024_src_data;                                                                          // router_024:src_data -> rsp_demux_021:sink_data
	wire          router_024_src_ready;                                                                         // rsp_demux_021:sink_ready -> router_024:src_ready
	wire   [22:0] router_024_src_channel;                                                                       // router_024:src_channel -> rsp_demux_021:sink_channel
	wire          router_024_src_startofpacket;                                                                 // router_024:src_startofpacket -> rsp_demux_021:sink_startofpacket
	wire          router_024_src_endofpacket;                                                                   // router_024:src_endofpacket -> rsp_demux_021:sink_endofpacket
	wire          spi_stm32_spi_control_port_agent_rp_valid;                                                    // spi_stm32_spi_control_port_agent:rp_valid -> router_025:sink_valid
	wire  [110:0] spi_stm32_spi_control_port_agent_rp_data;                                                     // spi_stm32_spi_control_port_agent:rp_data -> router_025:sink_data
	wire          spi_stm32_spi_control_port_agent_rp_ready;                                                    // router_025:sink_ready -> spi_stm32_spi_control_port_agent:rp_ready
	wire          spi_stm32_spi_control_port_agent_rp_startofpacket;                                            // spi_stm32_spi_control_port_agent:rp_startofpacket -> router_025:sink_startofpacket
	wire          spi_stm32_spi_control_port_agent_rp_endofpacket;                                              // spi_stm32_spi_control_port_agent:rp_endofpacket -> router_025:sink_endofpacket
	wire          router_025_src_valid;                                                                         // router_025:src_valid -> rsp_demux_022:sink_valid
	wire  [110:0] router_025_src_data;                                                                          // router_025:src_data -> rsp_demux_022:sink_data
	wire          router_025_src_ready;                                                                         // rsp_demux_022:sink_ready -> router_025:src_ready
	wire   [22:0] router_025_src_channel;                                                                       // router_025:src_channel -> rsp_demux_022:sink_channel
	wire          router_025_src_startofpacket;                                                                 // router_025:src_startofpacket -> rsp_demux_022:sink_startofpacket
	wire          router_025_src_endofpacket;                                                                   // router_025:src_endofpacket -> rsp_demux_022:sink_endofpacket
	wire          router_src_valid;                                                                             // router:src_valid -> abus_slave_0_avalon_master_limiter:cmd_sink_valid
	wire   [92:0] router_src_data;                                                                              // router:src_data -> abus_slave_0_avalon_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                                             // abus_slave_0_avalon_master_limiter:cmd_sink_ready -> router:src_ready
	wire   [22:0] router_src_channel;                                                                           // router:src_channel -> abus_slave_0_avalon_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                                     // router:src_startofpacket -> abus_slave_0_avalon_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                                       // router:src_endofpacket -> abus_slave_0_avalon_master_limiter:cmd_sink_endofpacket
	wire   [92:0] abus_slave_0_avalon_master_limiter_cmd_src_data;                                              // abus_slave_0_avalon_master_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          abus_slave_0_avalon_master_limiter_cmd_src_ready;                                             // cmd_demux:sink_ready -> abus_slave_0_avalon_master_limiter:cmd_src_ready
	wire   [22:0] abus_slave_0_avalon_master_limiter_cmd_src_channel;                                           // abus_slave_0_avalon_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          abus_slave_0_avalon_master_limiter_cmd_src_startofpacket;                                     // abus_slave_0_avalon_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          abus_slave_0_avalon_master_limiter_cmd_src_endofpacket;                                       // abus_slave_0_avalon_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                            // rsp_mux:src_valid -> abus_slave_0_avalon_master_limiter:rsp_sink_valid
	wire   [92:0] rsp_mux_src_data;                                                                             // rsp_mux:src_data -> abus_slave_0_avalon_master_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                                            // abus_slave_0_avalon_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire   [22:0] rsp_mux_src_channel;                                                                          // rsp_mux:src_channel -> abus_slave_0_avalon_master_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                                    // rsp_mux:src_startofpacket -> abus_slave_0_avalon_master_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                                      // rsp_mux:src_endofpacket -> abus_slave_0_avalon_master_limiter:rsp_sink_endofpacket
	wire          abus_slave_0_avalon_master_limiter_rsp_src_valid;                                             // abus_slave_0_avalon_master_limiter:rsp_src_valid -> abus_slave_0_avalon_master_agent:rp_valid
	wire   [92:0] abus_slave_0_avalon_master_limiter_rsp_src_data;                                              // abus_slave_0_avalon_master_limiter:rsp_src_data -> abus_slave_0_avalon_master_agent:rp_data
	wire          abus_slave_0_avalon_master_limiter_rsp_src_ready;                                             // abus_slave_0_avalon_master_agent:rp_ready -> abus_slave_0_avalon_master_limiter:rsp_src_ready
	wire   [22:0] abus_slave_0_avalon_master_limiter_rsp_src_channel;                                           // abus_slave_0_avalon_master_limiter:rsp_src_channel -> abus_slave_0_avalon_master_agent:rp_channel
	wire          abus_slave_0_avalon_master_limiter_rsp_src_startofpacket;                                     // abus_slave_0_avalon_master_limiter:rsp_src_startofpacket -> abus_slave_0_avalon_master_agent:rp_startofpacket
	wire          abus_slave_0_avalon_master_limiter_rsp_src_endofpacket;                                       // abus_slave_0_avalon_master_limiter:rsp_src_endofpacket -> abus_slave_0_avalon_master_agent:rp_endofpacket
	wire          cmd_mux_src_valid;                                                                            // cmd_mux:src_valid -> external_sdram_controller_s1_burst_adapter:sink0_valid
	wire   [92:0] cmd_mux_src_data;                                                                             // cmd_mux:src_data -> external_sdram_controller_s1_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                                            // external_sdram_controller_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire   [22:0] cmd_mux_src_channel;                                                                          // cmd_mux:src_channel -> external_sdram_controller_s1_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                                                    // cmd_mux:src_startofpacket -> external_sdram_controller_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                                                      // cmd_mux:src_endofpacket -> external_sdram_controller_s1_burst_adapter:sink0_endofpacket
	wire          external_sdram_controller_s1_burst_adapter_source0_valid;                                     // external_sdram_controller_s1_burst_adapter:source0_valid -> external_sdram_controller_s1_agent:cp_valid
	wire   [92:0] external_sdram_controller_s1_burst_adapter_source0_data;                                      // external_sdram_controller_s1_burst_adapter:source0_data -> external_sdram_controller_s1_agent:cp_data
	wire          external_sdram_controller_s1_burst_adapter_source0_ready;                                     // external_sdram_controller_s1_agent:cp_ready -> external_sdram_controller_s1_burst_adapter:source0_ready
	wire   [22:0] external_sdram_controller_s1_burst_adapter_source0_channel;                                   // external_sdram_controller_s1_burst_adapter:source0_channel -> external_sdram_controller_s1_agent:cp_channel
	wire          external_sdram_controller_s1_burst_adapter_source0_startofpacket;                             // external_sdram_controller_s1_burst_adapter:source0_startofpacket -> external_sdram_controller_s1_agent:cp_startofpacket
	wire          external_sdram_controller_s1_burst_adapter_source0_endofpacket;                               // external_sdram_controller_s1_burst_adapter:source0_endofpacket -> external_sdram_controller_s1_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                                         // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire   [92:0] cmd_demux_src0_data;                                                                          // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                                         // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire   [22:0] cmd_demux_src0_channel;                                                                       // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                                 // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                                   // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src1_valid;                                                                     // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
	wire  [110:0] cmd_demux_001_src1_data;                                                                      // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_001_src1_ready;                                                                     // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
	wire   [22:0] cmd_demux_001_src1_channel;                                                                   // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_001_src1_startofpacket;                                                             // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                                               // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_001_src2_valid;                                                                     // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
	wire  [110:0] cmd_demux_001_src2_data;                                                                      // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_001_src2_ready;                                                                     // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
	wire   [22:0] cmd_demux_001_src2_channel;                                                                   // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_001_src2_startofpacket;                                                             // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                                               // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_001_src3_valid;                                                                     // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
	wire  [110:0] cmd_demux_001_src3_data;                                                                      // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_001_src3_ready;                                                                     // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
	wire   [22:0] cmd_demux_001_src3_channel;                                                                   // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_001_src3_startofpacket;                                                             // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_001_src3_endofpacket;                                                               // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_001_src4_valid;                                                                     // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
	wire  [110:0] cmd_demux_001_src4_data;                                                                      // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_001_src4_ready;                                                                     // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
	wire   [22:0] cmd_demux_001_src4_channel;                                                                   // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_001_src4_startofpacket;                                                             // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_001_src4_endofpacket;                                                               // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_001_src5_valid;                                                                     // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
	wire  [110:0] cmd_demux_001_src5_data;                                                                      // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_001_src5_ready;                                                                     // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
	wire   [22:0] cmd_demux_001_src5_channel;                                                                   // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_001_src5_startofpacket;                                                             // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_001_src5_endofpacket;                                                               // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_001_src6_valid;                                                                     // cmd_demux_001:src6_valid -> cmd_mux_006:sink0_valid
	wire  [110:0] cmd_demux_001_src6_data;                                                                      // cmd_demux_001:src6_data -> cmd_mux_006:sink0_data
	wire          cmd_demux_001_src6_ready;                                                                     // cmd_mux_006:sink0_ready -> cmd_demux_001:src6_ready
	wire   [22:0] cmd_demux_001_src6_channel;                                                                   // cmd_demux_001:src6_channel -> cmd_mux_006:sink0_channel
	wire          cmd_demux_001_src6_startofpacket;                                                             // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	wire          cmd_demux_001_src6_endofpacket;                                                               // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	wire          cmd_demux_001_src7_valid;                                                                     // cmd_demux_001:src7_valid -> cmd_mux_007:sink0_valid
	wire  [110:0] cmd_demux_001_src7_data;                                                                      // cmd_demux_001:src7_data -> cmd_mux_007:sink0_data
	wire          cmd_demux_001_src7_ready;                                                                     // cmd_mux_007:sink0_ready -> cmd_demux_001:src7_ready
	wire   [22:0] cmd_demux_001_src7_channel;                                                                   // cmd_demux_001:src7_channel -> cmd_mux_007:sink0_channel
	wire          cmd_demux_001_src7_startofpacket;                                                             // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
	wire          cmd_demux_001_src7_endofpacket;                                                               // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
	wire          cmd_demux_001_src9_valid;                                                                     // cmd_demux_001:src9_valid -> cmd_mux_009:sink0_valid
	wire  [110:0] cmd_demux_001_src9_data;                                                                      // cmd_demux_001:src9_data -> cmd_mux_009:sink0_data
	wire          cmd_demux_001_src9_ready;                                                                     // cmd_mux_009:sink0_ready -> cmd_demux_001:src9_ready
	wire   [22:0] cmd_demux_001_src9_channel;                                                                   // cmd_demux_001:src9_channel -> cmd_mux_009:sink0_channel
	wire          cmd_demux_001_src9_startofpacket;                                                             // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
	wire          cmd_demux_001_src9_endofpacket;                                                               // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
	wire          cmd_demux_001_src10_valid;                                                                    // cmd_demux_001:src10_valid -> cmd_mux_010:sink0_valid
	wire  [110:0] cmd_demux_001_src10_data;                                                                     // cmd_demux_001:src10_data -> cmd_mux_010:sink0_data
	wire          cmd_demux_001_src10_ready;                                                                    // cmd_mux_010:sink0_ready -> cmd_demux_001:src10_ready
	wire   [22:0] cmd_demux_001_src10_channel;                                                                  // cmd_demux_001:src10_channel -> cmd_mux_010:sink0_channel
	wire          cmd_demux_001_src10_startofpacket;                                                            // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
	wire          cmd_demux_001_src10_endofpacket;                                                              // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
	wire          cmd_demux_001_src11_valid;                                                                    // cmd_demux_001:src11_valid -> cmd_mux_011:sink0_valid
	wire  [110:0] cmd_demux_001_src11_data;                                                                     // cmd_demux_001:src11_data -> cmd_mux_011:sink0_data
	wire          cmd_demux_001_src11_ready;                                                                    // cmd_mux_011:sink0_ready -> cmd_demux_001:src11_ready
	wire   [22:0] cmd_demux_001_src11_channel;                                                                  // cmd_demux_001:src11_channel -> cmd_mux_011:sink0_channel
	wire          cmd_demux_001_src11_startofpacket;                                                            // cmd_demux_001:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
	wire          cmd_demux_001_src11_endofpacket;                                                              // cmd_demux_001:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
	wire          cmd_demux_001_src12_valid;                                                                    // cmd_demux_001:src12_valid -> cmd_mux_012:sink0_valid
	wire  [110:0] cmd_demux_001_src12_data;                                                                     // cmd_demux_001:src12_data -> cmd_mux_012:sink0_data
	wire          cmd_demux_001_src12_ready;                                                                    // cmd_mux_012:sink0_ready -> cmd_demux_001:src12_ready
	wire   [22:0] cmd_demux_001_src12_channel;                                                                  // cmd_demux_001:src12_channel -> cmd_mux_012:sink0_channel
	wire          cmd_demux_001_src12_startofpacket;                                                            // cmd_demux_001:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
	wire          cmd_demux_001_src12_endofpacket;                                                              // cmd_demux_001:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
	wire          cmd_demux_001_src13_valid;                                                                    // cmd_demux_001:src13_valid -> cmd_mux_013:sink0_valid
	wire  [110:0] cmd_demux_001_src13_data;                                                                     // cmd_demux_001:src13_data -> cmd_mux_013:sink0_data
	wire          cmd_demux_001_src13_ready;                                                                    // cmd_mux_013:sink0_ready -> cmd_demux_001:src13_ready
	wire   [22:0] cmd_demux_001_src13_channel;                                                                  // cmd_demux_001:src13_channel -> cmd_mux_013:sink0_channel
	wire          cmd_demux_001_src13_startofpacket;                                                            // cmd_demux_001:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
	wire          cmd_demux_001_src13_endofpacket;                                                              // cmd_demux_001:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
	wire          cmd_demux_001_src14_valid;                                                                    // cmd_demux_001:src14_valid -> cmd_mux_014:sink0_valid
	wire  [110:0] cmd_demux_001_src14_data;                                                                     // cmd_demux_001:src14_data -> cmd_mux_014:sink0_data
	wire          cmd_demux_001_src14_ready;                                                                    // cmd_mux_014:sink0_ready -> cmd_demux_001:src14_ready
	wire   [22:0] cmd_demux_001_src14_channel;                                                                  // cmd_demux_001:src14_channel -> cmd_mux_014:sink0_channel
	wire          cmd_demux_001_src14_startofpacket;                                                            // cmd_demux_001:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
	wire          cmd_demux_001_src14_endofpacket;                                                              // cmd_demux_001:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
	wire          cmd_demux_001_src15_valid;                                                                    // cmd_demux_001:src15_valid -> cmd_mux_015:sink0_valid
	wire  [110:0] cmd_demux_001_src15_data;                                                                     // cmd_demux_001:src15_data -> cmd_mux_015:sink0_data
	wire          cmd_demux_001_src15_ready;                                                                    // cmd_mux_015:sink0_ready -> cmd_demux_001:src15_ready
	wire   [22:0] cmd_demux_001_src15_channel;                                                                  // cmd_demux_001:src15_channel -> cmd_mux_015:sink0_channel
	wire          cmd_demux_001_src15_startofpacket;                                                            // cmd_demux_001:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
	wire          cmd_demux_001_src15_endofpacket;                                                              // cmd_demux_001:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
	wire          cmd_demux_001_src16_valid;                                                                    // cmd_demux_001:src16_valid -> cmd_mux_016:sink0_valid
	wire  [110:0] cmd_demux_001_src16_data;                                                                     // cmd_demux_001:src16_data -> cmd_mux_016:sink0_data
	wire          cmd_demux_001_src16_ready;                                                                    // cmd_mux_016:sink0_ready -> cmd_demux_001:src16_ready
	wire   [22:0] cmd_demux_001_src16_channel;                                                                  // cmd_demux_001:src16_channel -> cmd_mux_016:sink0_channel
	wire          cmd_demux_001_src16_startofpacket;                                                            // cmd_demux_001:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
	wire          cmd_demux_001_src16_endofpacket;                                                              // cmd_demux_001:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
	wire          cmd_demux_001_src17_valid;                                                                    // cmd_demux_001:src17_valid -> cmd_mux_017:sink0_valid
	wire  [110:0] cmd_demux_001_src17_data;                                                                     // cmd_demux_001:src17_data -> cmd_mux_017:sink0_data
	wire          cmd_demux_001_src17_ready;                                                                    // cmd_mux_017:sink0_ready -> cmd_demux_001:src17_ready
	wire   [22:0] cmd_demux_001_src17_channel;                                                                  // cmd_demux_001:src17_channel -> cmd_mux_017:sink0_channel
	wire          cmd_demux_001_src17_startofpacket;                                                            // cmd_demux_001:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
	wire          cmd_demux_001_src17_endofpacket;                                                              // cmd_demux_001:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
	wire          cmd_demux_001_src18_valid;                                                                    // cmd_demux_001:src18_valid -> cmd_mux_018:sink0_valid
	wire  [110:0] cmd_demux_001_src18_data;                                                                     // cmd_demux_001:src18_data -> cmd_mux_018:sink0_data
	wire          cmd_demux_001_src18_ready;                                                                    // cmd_mux_018:sink0_ready -> cmd_demux_001:src18_ready
	wire   [22:0] cmd_demux_001_src18_channel;                                                                  // cmd_demux_001:src18_channel -> cmd_mux_018:sink0_channel
	wire          cmd_demux_001_src18_startofpacket;                                                            // cmd_demux_001:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
	wire          cmd_demux_001_src18_endofpacket;                                                              // cmd_demux_001:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
	wire          cmd_demux_001_src19_valid;                                                                    // cmd_demux_001:src19_valid -> cmd_mux_019:sink0_valid
	wire  [110:0] cmd_demux_001_src19_data;                                                                     // cmd_demux_001:src19_data -> cmd_mux_019:sink0_data
	wire          cmd_demux_001_src19_ready;                                                                    // cmd_mux_019:sink0_ready -> cmd_demux_001:src19_ready
	wire   [22:0] cmd_demux_001_src19_channel;                                                                  // cmd_demux_001:src19_channel -> cmd_mux_019:sink0_channel
	wire          cmd_demux_001_src19_startofpacket;                                                            // cmd_demux_001:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
	wire          cmd_demux_001_src19_endofpacket;                                                              // cmd_demux_001:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
	wire          cmd_demux_001_src20_valid;                                                                    // cmd_demux_001:src20_valid -> cmd_mux_020:sink0_valid
	wire  [110:0] cmd_demux_001_src20_data;                                                                     // cmd_demux_001:src20_data -> cmd_mux_020:sink0_data
	wire          cmd_demux_001_src20_ready;                                                                    // cmd_mux_020:sink0_ready -> cmd_demux_001:src20_ready
	wire   [22:0] cmd_demux_001_src20_channel;                                                                  // cmd_demux_001:src20_channel -> cmd_mux_020:sink0_channel
	wire          cmd_demux_001_src20_startofpacket;                                                            // cmd_demux_001:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
	wire          cmd_demux_001_src20_endofpacket;                                                              // cmd_demux_001:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
	wire          cmd_demux_001_src21_valid;                                                                    // cmd_demux_001:src21_valid -> cmd_mux_021:sink0_valid
	wire  [110:0] cmd_demux_001_src21_data;                                                                     // cmd_demux_001:src21_data -> cmd_mux_021:sink0_data
	wire          cmd_demux_001_src21_ready;                                                                    // cmd_mux_021:sink0_ready -> cmd_demux_001:src21_ready
	wire   [22:0] cmd_demux_001_src21_channel;                                                                  // cmd_demux_001:src21_channel -> cmd_mux_021:sink0_channel
	wire          cmd_demux_001_src21_startofpacket;                                                            // cmd_demux_001:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
	wire          cmd_demux_001_src21_endofpacket;                                                              // cmd_demux_001:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
	wire          cmd_demux_001_src22_valid;                                                                    // cmd_demux_001:src22_valid -> cmd_mux_022:sink0_valid
	wire  [110:0] cmd_demux_001_src22_data;                                                                     // cmd_demux_001:src22_data -> cmd_mux_022:sink0_data
	wire          cmd_demux_001_src22_ready;                                                                    // cmd_mux_022:sink0_ready -> cmd_demux_001:src22_ready
	wire   [22:0] cmd_demux_001_src22_channel;                                                                  // cmd_demux_001:src22_channel -> cmd_mux_022:sink0_channel
	wire          cmd_demux_001_src22_startofpacket;                                                            // cmd_demux_001:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
	wire          cmd_demux_001_src22_endofpacket;                                                              // cmd_demux_001:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
	wire          cmd_demux_002_src0_valid;                                                                     // cmd_demux_002:src0_valid -> cmd_mux_001:sink2_valid
	wire  [110:0] cmd_demux_002_src0_data;                                                                      // cmd_demux_002:src0_data -> cmd_mux_001:sink2_data
	wire          cmd_demux_002_src0_ready;                                                                     // cmd_mux_001:sink2_ready -> cmd_demux_002:src0_ready
	wire   [22:0] cmd_demux_002_src0_channel;                                                                   // cmd_demux_002:src0_channel -> cmd_mux_001:sink2_channel
	wire          cmd_demux_002_src0_startofpacket;                                                             // cmd_demux_002:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                                               // cmd_demux_002:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
	wire          cmd_demux_002_src1_valid;                                                                     // cmd_demux_002:src1_valid -> cmd_mux_006:sink1_valid
	wire  [110:0] cmd_demux_002_src1_data;                                                                      // cmd_demux_002:src1_data -> cmd_mux_006:sink1_data
	wire          cmd_demux_002_src1_ready;                                                                     // cmd_mux_006:sink1_ready -> cmd_demux_002:src1_ready
	wire   [22:0] cmd_demux_002_src1_channel;                                                                   // cmd_demux_002:src1_channel -> cmd_mux_006:sink1_channel
	wire          cmd_demux_002_src1_startofpacket;                                                             // cmd_demux_002:src1_startofpacket -> cmd_mux_006:sink1_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                                               // cmd_demux_002:src1_endofpacket -> cmd_mux_006:sink1_endofpacket
	wire          cmd_demux_002_src2_valid;                                                                     // cmd_demux_002:src2_valid -> cmd_mux_007:sink1_valid
	wire  [110:0] cmd_demux_002_src2_data;                                                                      // cmd_demux_002:src2_data -> cmd_mux_007:sink1_data
	wire          cmd_demux_002_src2_ready;                                                                     // cmd_mux_007:sink1_ready -> cmd_demux_002:src2_ready
	wire   [22:0] cmd_demux_002_src2_channel;                                                                   // cmd_demux_002:src2_channel -> cmd_mux_007:sink1_channel
	wire          cmd_demux_002_src2_startofpacket;                                                             // cmd_demux_002:src2_startofpacket -> cmd_mux_007:sink1_startofpacket
	wire          cmd_demux_002_src2_endofpacket;                                                               // cmd_demux_002:src2_endofpacket -> cmd_mux_007:sink1_endofpacket
	wire          cmd_demux_002_src3_valid;                                                                     // cmd_demux_002:src3_valid -> cmd_mux_009:sink1_valid
	wire  [110:0] cmd_demux_002_src3_data;                                                                      // cmd_demux_002:src3_data -> cmd_mux_009:sink1_data
	wire          cmd_demux_002_src3_ready;                                                                     // cmd_mux_009:sink1_ready -> cmd_demux_002:src3_ready
	wire   [22:0] cmd_demux_002_src3_channel;                                                                   // cmd_demux_002:src3_channel -> cmd_mux_009:sink1_channel
	wire          cmd_demux_002_src3_startofpacket;                                                             // cmd_demux_002:src3_startofpacket -> cmd_mux_009:sink1_startofpacket
	wire          cmd_demux_002_src3_endofpacket;                                                               // cmd_demux_002:src3_endofpacket -> cmd_mux_009:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                                         // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire   [92:0] rsp_demux_src0_data;                                                                          // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                                         // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire   [22:0] rsp_demux_src0_channel;                                                                       // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                                 // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                                   // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src1_valid;                                                                     // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
	wire  [110:0] rsp_demux_001_src1_data;                                                                      // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_001_src1_ready;                                                                     // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
	wire   [22:0] rsp_demux_001_src1_channel;                                                                   // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_001_src1_startofpacket;                                                             // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                                               // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_001_src2_valid;                                                                     // rsp_demux_001:src2_valid -> rsp_mux_002:sink0_valid
	wire  [110:0] rsp_demux_001_src2_data;                                                                      // rsp_demux_001:src2_data -> rsp_mux_002:sink0_data
	wire          rsp_demux_001_src2_ready;                                                                     // rsp_mux_002:sink0_ready -> rsp_demux_001:src2_ready
	wire   [22:0] rsp_demux_001_src2_channel;                                                                   // rsp_demux_001:src2_channel -> rsp_mux_002:sink0_channel
	wire          rsp_demux_001_src2_startofpacket;                                                             // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          rsp_demux_001_src2_endofpacket;                                                               // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_002_src0_valid;                                                                     // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
	wire  [110:0] rsp_demux_002_src0_data;                                                                      // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_002_src0_ready;                                                                     // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
	wire   [22:0] rsp_demux_002_src0_channel;                                                                   // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                                             // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                               // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                                     // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
	wire  [110:0] rsp_demux_003_src0_data;                                                                      // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
	wire          rsp_demux_003_src0_ready;                                                                     // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
	wire   [22:0] rsp_demux_003_src0_channel;                                                                   // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                                             // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                               // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                                                     // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
	wire  [110:0] rsp_demux_004_src0_data;                                                                      // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
	wire          rsp_demux_004_src0_ready;                                                                     // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
	wire   [22:0] rsp_demux_004_src0_channel;                                                                   // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                                             // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                                               // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                                                     // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
	wire  [110:0] rsp_demux_005_src0_data;                                                                      // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
	wire          rsp_demux_005_src0_ready;                                                                     // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
	wire   [22:0] rsp_demux_005_src0_channel;                                                                   // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                                                             // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                                               // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
	wire          rsp_demux_006_src0_valid;                                                                     // rsp_demux_006:src0_valid -> rsp_mux_001:sink6_valid
	wire  [110:0] rsp_demux_006_src0_data;                                                                      // rsp_demux_006:src0_data -> rsp_mux_001:sink6_data
	wire          rsp_demux_006_src0_ready;                                                                     // rsp_mux_001:sink6_ready -> rsp_demux_006:src0_ready
	wire   [22:0] rsp_demux_006_src0_channel;                                                                   // rsp_demux_006:src0_channel -> rsp_mux_001:sink6_channel
	wire          rsp_demux_006_src0_startofpacket;                                                             // rsp_demux_006:src0_startofpacket -> rsp_mux_001:sink6_startofpacket
	wire          rsp_demux_006_src0_endofpacket;                                                               // rsp_demux_006:src0_endofpacket -> rsp_mux_001:sink6_endofpacket
	wire          rsp_demux_006_src1_valid;                                                                     // rsp_demux_006:src1_valid -> rsp_mux_002:sink1_valid
	wire  [110:0] rsp_demux_006_src1_data;                                                                      // rsp_demux_006:src1_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_006_src1_ready;                                                                     // rsp_mux_002:sink1_ready -> rsp_demux_006:src1_ready
	wire   [22:0] rsp_demux_006_src1_channel;                                                                   // rsp_demux_006:src1_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_006_src1_startofpacket;                                                             // rsp_demux_006:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_006_src1_endofpacket;                                                               // rsp_demux_006:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_007_src0_valid;                                                                     // rsp_demux_007:src0_valid -> rsp_mux_001:sink7_valid
	wire  [110:0] rsp_demux_007_src0_data;                                                                      // rsp_demux_007:src0_data -> rsp_mux_001:sink7_data
	wire          rsp_demux_007_src0_ready;                                                                     // rsp_mux_001:sink7_ready -> rsp_demux_007:src0_ready
	wire   [22:0] rsp_demux_007_src0_channel;                                                                   // rsp_demux_007:src0_channel -> rsp_mux_001:sink7_channel
	wire          rsp_demux_007_src0_startofpacket;                                                             // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink7_startofpacket
	wire          rsp_demux_007_src0_endofpacket;                                                               // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink7_endofpacket
	wire          rsp_demux_007_src1_valid;                                                                     // rsp_demux_007:src1_valid -> rsp_mux_002:sink2_valid
	wire  [110:0] rsp_demux_007_src1_data;                                                                      // rsp_demux_007:src1_data -> rsp_mux_002:sink2_data
	wire          rsp_demux_007_src1_ready;                                                                     // rsp_mux_002:sink2_ready -> rsp_demux_007:src1_ready
	wire   [22:0] rsp_demux_007_src1_channel;                                                                   // rsp_demux_007:src1_channel -> rsp_mux_002:sink2_channel
	wire          rsp_demux_007_src1_startofpacket;                                                             // rsp_demux_007:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
	wire          rsp_demux_007_src1_endofpacket;                                                               // rsp_demux_007:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
	wire          rsp_demux_009_src0_valid;                                                                     // rsp_demux_009:src0_valid -> rsp_mux_001:sink9_valid
	wire  [110:0] rsp_demux_009_src0_data;                                                                      // rsp_demux_009:src0_data -> rsp_mux_001:sink9_data
	wire          rsp_demux_009_src0_ready;                                                                     // rsp_mux_001:sink9_ready -> rsp_demux_009:src0_ready
	wire   [22:0] rsp_demux_009_src0_channel;                                                                   // rsp_demux_009:src0_channel -> rsp_mux_001:sink9_channel
	wire          rsp_demux_009_src0_startofpacket;                                                             // rsp_demux_009:src0_startofpacket -> rsp_mux_001:sink9_startofpacket
	wire          rsp_demux_009_src0_endofpacket;                                                               // rsp_demux_009:src0_endofpacket -> rsp_mux_001:sink9_endofpacket
	wire          rsp_demux_009_src1_valid;                                                                     // rsp_demux_009:src1_valid -> rsp_mux_002:sink3_valid
	wire  [110:0] rsp_demux_009_src1_data;                                                                      // rsp_demux_009:src1_data -> rsp_mux_002:sink3_data
	wire          rsp_demux_009_src1_ready;                                                                     // rsp_mux_002:sink3_ready -> rsp_demux_009:src1_ready
	wire   [22:0] rsp_demux_009_src1_channel;                                                                   // rsp_demux_009:src1_channel -> rsp_mux_002:sink3_channel
	wire          rsp_demux_009_src1_startofpacket;                                                             // rsp_demux_009:src1_startofpacket -> rsp_mux_002:sink3_startofpacket
	wire          rsp_demux_009_src1_endofpacket;                                                               // rsp_demux_009:src1_endofpacket -> rsp_mux_002:sink3_endofpacket
	wire          rsp_demux_010_src0_valid;                                                                     // rsp_demux_010:src0_valid -> rsp_mux_001:sink10_valid
	wire  [110:0] rsp_demux_010_src0_data;                                                                      // rsp_demux_010:src0_data -> rsp_mux_001:sink10_data
	wire          rsp_demux_010_src0_ready;                                                                     // rsp_mux_001:sink10_ready -> rsp_demux_010:src0_ready
	wire   [22:0] rsp_demux_010_src0_channel;                                                                   // rsp_demux_010:src0_channel -> rsp_mux_001:sink10_channel
	wire          rsp_demux_010_src0_startofpacket;                                                             // rsp_demux_010:src0_startofpacket -> rsp_mux_001:sink10_startofpacket
	wire          rsp_demux_010_src0_endofpacket;                                                               // rsp_demux_010:src0_endofpacket -> rsp_mux_001:sink10_endofpacket
	wire          rsp_demux_011_src0_valid;                                                                     // rsp_demux_011:src0_valid -> rsp_mux_001:sink11_valid
	wire  [110:0] rsp_demux_011_src0_data;                                                                      // rsp_demux_011:src0_data -> rsp_mux_001:sink11_data
	wire          rsp_demux_011_src0_ready;                                                                     // rsp_mux_001:sink11_ready -> rsp_demux_011:src0_ready
	wire   [22:0] rsp_demux_011_src0_channel;                                                                   // rsp_demux_011:src0_channel -> rsp_mux_001:sink11_channel
	wire          rsp_demux_011_src0_startofpacket;                                                             // rsp_demux_011:src0_startofpacket -> rsp_mux_001:sink11_startofpacket
	wire          rsp_demux_011_src0_endofpacket;                                                               // rsp_demux_011:src0_endofpacket -> rsp_mux_001:sink11_endofpacket
	wire          rsp_demux_012_src0_valid;                                                                     // rsp_demux_012:src0_valid -> rsp_mux_001:sink12_valid
	wire  [110:0] rsp_demux_012_src0_data;                                                                      // rsp_demux_012:src0_data -> rsp_mux_001:sink12_data
	wire          rsp_demux_012_src0_ready;                                                                     // rsp_mux_001:sink12_ready -> rsp_demux_012:src0_ready
	wire   [22:0] rsp_demux_012_src0_channel;                                                                   // rsp_demux_012:src0_channel -> rsp_mux_001:sink12_channel
	wire          rsp_demux_012_src0_startofpacket;                                                             // rsp_demux_012:src0_startofpacket -> rsp_mux_001:sink12_startofpacket
	wire          rsp_demux_012_src0_endofpacket;                                                               // rsp_demux_012:src0_endofpacket -> rsp_mux_001:sink12_endofpacket
	wire          rsp_demux_013_src0_valid;                                                                     // rsp_demux_013:src0_valid -> rsp_mux_001:sink13_valid
	wire  [110:0] rsp_demux_013_src0_data;                                                                      // rsp_demux_013:src0_data -> rsp_mux_001:sink13_data
	wire          rsp_demux_013_src0_ready;                                                                     // rsp_mux_001:sink13_ready -> rsp_demux_013:src0_ready
	wire   [22:0] rsp_demux_013_src0_channel;                                                                   // rsp_demux_013:src0_channel -> rsp_mux_001:sink13_channel
	wire          rsp_demux_013_src0_startofpacket;                                                             // rsp_demux_013:src0_startofpacket -> rsp_mux_001:sink13_startofpacket
	wire          rsp_demux_013_src0_endofpacket;                                                               // rsp_demux_013:src0_endofpacket -> rsp_mux_001:sink13_endofpacket
	wire          rsp_demux_014_src0_valid;                                                                     // rsp_demux_014:src0_valid -> rsp_mux_001:sink14_valid
	wire  [110:0] rsp_demux_014_src0_data;                                                                      // rsp_demux_014:src0_data -> rsp_mux_001:sink14_data
	wire          rsp_demux_014_src0_ready;                                                                     // rsp_mux_001:sink14_ready -> rsp_demux_014:src0_ready
	wire   [22:0] rsp_demux_014_src0_channel;                                                                   // rsp_demux_014:src0_channel -> rsp_mux_001:sink14_channel
	wire          rsp_demux_014_src0_startofpacket;                                                             // rsp_demux_014:src0_startofpacket -> rsp_mux_001:sink14_startofpacket
	wire          rsp_demux_014_src0_endofpacket;                                                               // rsp_demux_014:src0_endofpacket -> rsp_mux_001:sink14_endofpacket
	wire          rsp_demux_015_src0_valid;                                                                     // rsp_demux_015:src0_valid -> rsp_mux_001:sink15_valid
	wire  [110:0] rsp_demux_015_src0_data;                                                                      // rsp_demux_015:src0_data -> rsp_mux_001:sink15_data
	wire          rsp_demux_015_src0_ready;                                                                     // rsp_mux_001:sink15_ready -> rsp_demux_015:src0_ready
	wire   [22:0] rsp_demux_015_src0_channel;                                                                   // rsp_demux_015:src0_channel -> rsp_mux_001:sink15_channel
	wire          rsp_demux_015_src0_startofpacket;                                                             // rsp_demux_015:src0_startofpacket -> rsp_mux_001:sink15_startofpacket
	wire          rsp_demux_015_src0_endofpacket;                                                               // rsp_demux_015:src0_endofpacket -> rsp_mux_001:sink15_endofpacket
	wire          rsp_demux_016_src0_valid;                                                                     // rsp_demux_016:src0_valid -> rsp_mux_001:sink16_valid
	wire  [110:0] rsp_demux_016_src0_data;                                                                      // rsp_demux_016:src0_data -> rsp_mux_001:sink16_data
	wire          rsp_demux_016_src0_ready;                                                                     // rsp_mux_001:sink16_ready -> rsp_demux_016:src0_ready
	wire   [22:0] rsp_demux_016_src0_channel;                                                                   // rsp_demux_016:src0_channel -> rsp_mux_001:sink16_channel
	wire          rsp_demux_016_src0_startofpacket;                                                             // rsp_demux_016:src0_startofpacket -> rsp_mux_001:sink16_startofpacket
	wire          rsp_demux_016_src0_endofpacket;                                                               // rsp_demux_016:src0_endofpacket -> rsp_mux_001:sink16_endofpacket
	wire          rsp_demux_017_src0_valid;                                                                     // rsp_demux_017:src0_valid -> rsp_mux_001:sink17_valid
	wire  [110:0] rsp_demux_017_src0_data;                                                                      // rsp_demux_017:src0_data -> rsp_mux_001:sink17_data
	wire          rsp_demux_017_src0_ready;                                                                     // rsp_mux_001:sink17_ready -> rsp_demux_017:src0_ready
	wire   [22:0] rsp_demux_017_src0_channel;                                                                   // rsp_demux_017:src0_channel -> rsp_mux_001:sink17_channel
	wire          rsp_demux_017_src0_startofpacket;                                                             // rsp_demux_017:src0_startofpacket -> rsp_mux_001:sink17_startofpacket
	wire          rsp_demux_017_src0_endofpacket;                                                               // rsp_demux_017:src0_endofpacket -> rsp_mux_001:sink17_endofpacket
	wire          rsp_demux_018_src0_valid;                                                                     // rsp_demux_018:src0_valid -> rsp_mux_001:sink18_valid
	wire  [110:0] rsp_demux_018_src0_data;                                                                      // rsp_demux_018:src0_data -> rsp_mux_001:sink18_data
	wire          rsp_demux_018_src0_ready;                                                                     // rsp_mux_001:sink18_ready -> rsp_demux_018:src0_ready
	wire   [22:0] rsp_demux_018_src0_channel;                                                                   // rsp_demux_018:src0_channel -> rsp_mux_001:sink18_channel
	wire          rsp_demux_018_src0_startofpacket;                                                             // rsp_demux_018:src0_startofpacket -> rsp_mux_001:sink18_startofpacket
	wire          rsp_demux_018_src0_endofpacket;                                                               // rsp_demux_018:src0_endofpacket -> rsp_mux_001:sink18_endofpacket
	wire          rsp_demux_019_src0_valid;                                                                     // rsp_demux_019:src0_valid -> rsp_mux_001:sink19_valid
	wire  [110:0] rsp_demux_019_src0_data;                                                                      // rsp_demux_019:src0_data -> rsp_mux_001:sink19_data
	wire          rsp_demux_019_src0_ready;                                                                     // rsp_mux_001:sink19_ready -> rsp_demux_019:src0_ready
	wire   [22:0] rsp_demux_019_src0_channel;                                                                   // rsp_demux_019:src0_channel -> rsp_mux_001:sink19_channel
	wire          rsp_demux_019_src0_startofpacket;                                                             // rsp_demux_019:src0_startofpacket -> rsp_mux_001:sink19_startofpacket
	wire          rsp_demux_019_src0_endofpacket;                                                               // rsp_demux_019:src0_endofpacket -> rsp_mux_001:sink19_endofpacket
	wire          rsp_demux_020_src0_valid;                                                                     // rsp_demux_020:src0_valid -> rsp_mux_001:sink20_valid
	wire  [110:0] rsp_demux_020_src0_data;                                                                      // rsp_demux_020:src0_data -> rsp_mux_001:sink20_data
	wire          rsp_demux_020_src0_ready;                                                                     // rsp_mux_001:sink20_ready -> rsp_demux_020:src0_ready
	wire   [22:0] rsp_demux_020_src0_channel;                                                                   // rsp_demux_020:src0_channel -> rsp_mux_001:sink20_channel
	wire          rsp_demux_020_src0_startofpacket;                                                             // rsp_demux_020:src0_startofpacket -> rsp_mux_001:sink20_startofpacket
	wire          rsp_demux_020_src0_endofpacket;                                                               // rsp_demux_020:src0_endofpacket -> rsp_mux_001:sink20_endofpacket
	wire          rsp_demux_021_src0_valid;                                                                     // rsp_demux_021:src0_valid -> rsp_mux_001:sink21_valid
	wire  [110:0] rsp_demux_021_src0_data;                                                                      // rsp_demux_021:src0_data -> rsp_mux_001:sink21_data
	wire          rsp_demux_021_src0_ready;                                                                     // rsp_mux_001:sink21_ready -> rsp_demux_021:src0_ready
	wire   [22:0] rsp_demux_021_src0_channel;                                                                   // rsp_demux_021:src0_channel -> rsp_mux_001:sink21_channel
	wire          rsp_demux_021_src0_startofpacket;                                                             // rsp_demux_021:src0_startofpacket -> rsp_mux_001:sink21_startofpacket
	wire          rsp_demux_021_src0_endofpacket;                                                               // rsp_demux_021:src0_endofpacket -> rsp_mux_001:sink21_endofpacket
	wire          rsp_demux_022_src0_valid;                                                                     // rsp_demux_022:src0_valid -> rsp_mux_001:sink22_valid
	wire  [110:0] rsp_demux_022_src0_data;                                                                      // rsp_demux_022:src0_data -> rsp_mux_001:sink22_data
	wire          rsp_demux_022_src0_ready;                                                                     // rsp_mux_001:sink22_ready -> rsp_demux_022:src0_ready
	wire   [22:0] rsp_demux_022_src0_channel;                                                                   // rsp_demux_022:src0_channel -> rsp_mux_001:sink22_channel
	wire          rsp_demux_022_src0_startofpacket;                                                             // rsp_demux_022:src0_startofpacket -> rsp_mux_001:sink22_startofpacket
	wire          rsp_demux_022_src0_endofpacket;                                                               // rsp_demux_022:src0_endofpacket -> rsp_mux_001:sink22_endofpacket
	wire          cmd_demux_src1_valid;                                                                         // cmd_demux:src1_valid -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_valid
	wire   [92:0] cmd_demux_src1_data;                                                                          // cmd_demux:src1_data -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_data
	wire          cmd_demux_src1_ready;                                                                         // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_ready -> cmd_demux:src1_ready
	wire   [22:0] cmd_demux_src1_channel;                                                                       // cmd_demux:src1_channel -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_channel
	wire          cmd_demux_src1_startofpacket;                                                                 // cmd_demux:src1_startofpacket -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                                   // cmd_demux:src1_endofpacket -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_endofpacket
	wire          abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid;                // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_valid -> cmd_mux_001:sink0_valid
	wire  [110:0] abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data;                 // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_data -> cmd_mux_001:sink0_data
	wire          abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready;                // cmd_mux_001:sink0_ready -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_ready
	wire   [22:0] abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel;              // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_channel -> cmd_mux_001:sink0_channel
	wire          abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket;        // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket;          // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                                     // cmd_demux_001:src0_valid -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_valid
	wire  [110:0] cmd_demux_001_src0_data;                                                                      // cmd_demux_001:src0_data -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_data
	wire          cmd_demux_001_src0_ready;                                                                     // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_ready -> cmd_demux_001:src0_ready
	wire   [22:0] cmd_demux_001_src0_channel;                                                                   // cmd_demux_001:src0_channel -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_channel
	wire          cmd_demux_001_src0_startofpacket;                                                             // cmd_demux_001:src0_startofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                               // cmd_demux_001:src0_endofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_endofpacket
	wire          nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid;         // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_valid -> cmd_mux:sink1_valid
	wire   [92:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data;          // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_data -> cmd_mux:sink1_data
	wire          nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready;         // cmd_mux:sink1_ready -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_ready
	wire   [22:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel;       // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_channel -> cmd_mux:sink1_channel
	wire          nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink1_startofpacket
	wire          nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket;   // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src1_valid;                                                                         // rsp_demux:src1_valid -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_valid
	wire   [92:0] rsp_demux_src1_data;                                                                          // rsp_demux:src1_data -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_data
	wire          rsp_demux_src1_ready;                                                                         // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_ready -> rsp_demux:src1_ready
	wire   [22:0] rsp_demux_src1_channel;                                                                       // rsp_demux:src1_channel -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_channel
	wire          rsp_demux_src1_startofpacket;                                                                 // rsp_demux:src1_startofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                                   // rsp_demux:src1_endofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_endofpacket
	wire          external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid;         // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_valid -> rsp_mux_001:sink0_valid
	wire  [110:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data;          // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_data -> rsp_mux_001:sink0_data
	wire          external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready;         // rsp_mux_001:sink0_ready -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_ready
	wire   [22:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel;       // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_channel -> rsp_mux_001:sink0_channel
	wire          external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket;   // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                                     // rsp_demux_001:src0_valid -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_valid
	wire  [110:0] rsp_demux_001_src0_data;                                                                      // rsp_demux_001:src0_data -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_data
	wire          rsp_demux_001_src0_ready;                                                                     // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_ready -> rsp_demux_001:src0_ready
	wire   [22:0] rsp_demux_001_src0_channel;                                                                   // rsp_demux_001:src0_channel -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                                             // rsp_demux_001:src0_startofpacket -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                               // rsp_demux_001:src0_endofpacket -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_endofpacket
	wire          onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid;                // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_valid -> rsp_mux:sink1_valid
	wire   [92:0] onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data;                 // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_data -> rsp_mux:sink1_data
	wire          onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready;                // rsp_mux:sink1_ready -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_ready
	wire   [22:0] onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel;              // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_channel -> rsp_mux:sink1_channel
	wire          onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket;        // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket;          // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire          cmd_demux_001_src8_valid;                                                                     // cmd_demux_001:src8_valid -> crosser:in_valid
	wire  [110:0] cmd_demux_001_src8_data;                                                                      // cmd_demux_001:src8_data -> crosser:in_data
	wire          cmd_demux_001_src8_ready;                                                                     // crosser:in_ready -> cmd_demux_001:src8_ready
	wire   [22:0] cmd_demux_001_src8_channel;                                                                   // cmd_demux_001:src8_channel -> crosser:in_channel
	wire          cmd_demux_001_src8_startofpacket;                                                             // cmd_demux_001:src8_startofpacket -> crosser:in_startofpacket
	wire          cmd_demux_001_src8_endofpacket;                                                               // cmd_demux_001:src8_endofpacket -> crosser:in_endofpacket
	wire          crosser_out_valid;                                                                            // crosser:out_valid -> cmd_mux_008:sink0_valid
	wire  [110:0] crosser_out_data;                                                                             // crosser:out_data -> cmd_mux_008:sink0_data
	wire          crosser_out_ready;                                                                            // cmd_mux_008:sink0_ready -> crosser:out_ready
	wire   [22:0] crosser_out_channel;                                                                          // crosser:out_channel -> cmd_mux_008:sink0_channel
	wire          crosser_out_startofpacket;                                                                    // crosser:out_startofpacket -> cmd_mux_008:sink0_startofpacket
	wire          crosser_out_endofpacket;                                                                      // crosser:out_endofpacket -> cmd_mux_008:sink0_endofpacket
	wire          rsp_demux_008_src0_valid;                                                                     // rsp_demux_008:src0_valid -> crosser_001:in_valid
	wire  [110:0] rsp_demux_008_src0_data;                                                                      // rsp_demux_008:src0_data -> crosser_001:in_data
	wire          rsp_demux_008_src0_ready;                                                                     // crosser_001:in_ready -> rsp_demux_008:src0_ready
	wire   [22:0] rsp_demux_008_src0_channel;                                                                   // rsp_demux_008:src0_channel -> crosser_001:in_channel
	wire          rsp_demux_008_src0_startofpacket;                                                             // rsp_demux_008:src0_startofpacket -> crosser_001:in_startofpacket
	wire          rsp_demux_008_src0_endofpacket;                                                               // rsp_demux_008:src0_endofpacket -> crosser_001:in_endofpacket
	wire          crosser_001_out_valid;                                                                        // crosser_001:out_valid -> rsp_mux_001:sink8_valid
	wire  [110:0] crosser_001_out_data;                                                                         // crosser_001:out_data -> rsp_mux_001:sink8_data
	wire          crosser_001_out_ready;                                                                        // rsp_mux_001:sink8_ready -> crosser_001:out_ready
	wire   [22:0] crosser_001_out_channel;                                                                      // crosser_001:out_channel -> rsp_mux_001:sink8_channel
	wire          crosser_001_out_startofpacket;                                                                // crosser_001:out_startofpacket -> rsp_mux_001:sink8_startofpacket
	wire          crosser_001_out_endofpacket;                                                                  // crosser_001:out_endofpacket -> rsp_mux_001:sink8_endofpacket
	wire   [22:0] abus_slave_0_avalon_master_limiter_cmd_valid_data;                                            // abus_slave_0_avalon_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire          external_sdram_controller_s1_agent_rdata_fifo_out_valid;                                      // external_sdram_controller_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
	wire   [17:0] external_sdram_controller_s1_agent_rdata_fifo_out_data;                                       // external_sdram_controller_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
	wire          external_sdram_controller_s1_agent_rdata_fifo_out_ready;                                      // avalon_st_adapter:in_0_ready -> external_sdram_controller_s1_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_out_0_valid;                                                                // avalon_st_adapter:out_0_valid -> external_sdram_controller_s1_agent:rdata_fifo_sink_valid
	wire   [17:0] avalon_st_adapter_out_0_data;                                                                 // avalon_st_adapter:out_0_data -> external_sdram_controller_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_out_0_ready;                                                                // external_sdram_controller_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	wire    [0:0] avalon_st_adapter_out_0_error;                                                                // avalon_st_adapter:out_0_error -> external_sdram_controller_s1_agent:rdata_fifo_sink_error
	wire          onchip_memory2_1_s1_agent_rdata_fifo_src_valid;                                               // onchip_memory2_1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	wire   [33:0] onchip_memory2_1_s1_agent_rdata_fifo_src_data;                                                // onchip_memory2_1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	wire          onchip_memory2_1_s1_agent_rdata_fifo_src_ready;                                               // avalon_st_adapter_001:in_0_ready -> onchip_memory2_1_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_001_out_0_valid;                                                            // avalon_st_adapter_001:out_0_valid -> onchip_memory2_1_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_001_out_0_data;                                                             // avalon_st_adapter_001:out_0_data -> onchip_memory2_1_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_001_out_0_ready;                                                            // onchip_memory2_1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	wire    [0:0] avalon_st_adapter_001_out_0_error;                                                            // avalon_st_adapter_001:out_0_error -> onchip_memory2_1_s1_agent:rdata_fifo_sink_error
	wire          abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid;                                          // abus_slave_0_avalon_nios_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
	wire   [33:0] abus_slave_0_avalon_nios_agent_rdata_fifo_src_data;                                           // abus_slave_0_avalon_nios_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
	wire          abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready;                                          // avalon_st_adapter_002:in_0_ready -> abus_slave_0_avalon_nios_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_002_out_0_valid;                                                            // avalon_st_adapter_002:out_0_valid -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_002_out_0_data;                                                             // avalon_st_adapter_002:out_0_data -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_002_out_0_ready;                                                            // abus_slave_0_avalon_nios_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	wire    [0:0] avalon_st_adapter_002_out_0_error;                                                            // avalon_st_adapter_002:out_0_error -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_error
	wire          abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid;                                          // abus_demux_0_avalon_nios_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
	wire   [33:0] abus_demux_0_avalon_nios_agent_rdata_fifo_src_data;                                           // abus_demux_0_avalon_nios_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
	wire          abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready;                                          // avalon_st_adapter_003:in_0_ready -> abus_demux_0_avalon_nios_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_003_out_0_valid;                                                            // avalon_st_adapter_003:out_0_valid -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_003_out_0_data;                                                             // avalon_st_adapter_003:out_0_data -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_003_out_0_ready;                                                            // abus_demux_0_avalon_nios_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
	wire    [0:0] avalon_st_adapter_003_out_0_error;                                                            // avalon_st_adapter_003:out_0_error -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_error
	wire          performance_counter_0_control_slave_agent_rdata_fifo_src_valid;                               // performance_counter_0_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
	wire   [33:0] performance_counter_0_control_slave_agent_rdata_fifo_src_data;                                // performance_counter_0_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
	wire          performance_counter_0_control_slave_agent_rdata_fifo_src_ready;                               // avalon_st_adapter_004:in_0_ready -> performance_counter_0_control_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_004_out_0_valid;                                                            // avalon_st_adapter_004:out_0_valid -> performance_counter_0_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_004_out_0_data;                                                             // avalon_st_adapter_004:out_0_data -> performance_counter_0_control_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_004_out_0_ready;                                                            // performance_counter_0_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
	wire    [0:0] avalon_st_adapter_004_out_0_error;                                                            // avalon_st_adapter_004:out_0_error -> performance_counter_0_control_slave_agent:rdata_fifo_sink_error
	wire          onchip_flash_0_csr_agent_rdata_fifo_src_valid;                                                // onchip_flash_0_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
	wire   [33:0] onchip_flash_0_csr_agent_rdata_fifo_src_data;                                                 // onchip_flash_0_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
	wire          onchip_flash_0_csr_agent_rdata_fifo_src_ready;                                                // avalon_st_adapter_005:in_0_ready -> onchip_flash_0_csr_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_005_out_0_valid;                                                            // avalon_st_adapter_005:out_0_valid -> onchip_flash_0_csr_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_005_out_0_data;                                                             // avalon_st_adapter_005:out_0_data -> onchip_flash_0_csr_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_005_out_0_ready;                                                            // onchip_flash_0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
	wire    [0:0] avalon_st_adapter_005_out_0_error;                                                            // avalon_st_adapter_005:out_0_error -> onchip_flash_0_csr_agent:rdata_fifo_sink_error
	wire          onchip_flash_0_data_agent_rdata_fifo_src_valid;                                               // onchip_flash_0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
	wire   [33:0] onchip_flash_0_data_agent_rdata_fifo_src_data;                                                // onchip_flash_0_data_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
	wire          onchip_flash_0_data_agent_rdata_fifo_src_ready;                                               // avalon_st_adapter_006:in_0_ready -> onchip_flash_0_data_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_006_out_0_valid;                                                            // avalon_st_adapter_006:out_0_valid -> onchip_flash_0_data_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_006_out_0_data;                                                             // avalon_st_adapter_006:out_0_data -> onchip_flash_0_data_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_006_out_0_ready;                                                            // onchip_flash_0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
	wire    [0:0] avalon_st_adapter_006_out_0_error;                                                            // avalon_st_adapter_006:out_0_error -> onchip_flash_0_data_agent:rdata_fifo_sink_error
	wire          nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid;                                      // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
	wire   [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data;                                       // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
	wire          nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready;                                      // avalon_st_adapter_007:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_007_out_0_valid;                                                            // avalon_st_adapter_007:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_007_out_0_data;                                                             // avalon_st_adapter_007:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_007_out_0_ready;                                                            // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
	wire    [0:0] avalon_st_adapter_007_out_0_error;                                                            // avalon_st_adapter_007:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
	wire          altpll_0_pll_slave_agent_rdata_fifo_out_valid;                                                // altpll_0_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_008:in_0_valid
	wire   [33:0] altpll_0_pll_slave_agent_rdata_fifo_out_data;                                                 // altpll_0_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_008:in_0_data
	wire          altpll_0_pll_slave_agent_rdata_fifo_out_ready;                                                // avalon_st_adapter_008:in_0_ready -> altpll_0_pll_slave_agent_rdata_fifo:out_ready
	wire          avalon_st_adapter_008_out_0_valid;                                                            // avalon_st_adapter_008:out_0_valid -> altpll_0_pll_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_008_out_0_data;                                                             // avalon_st_adapter_008:out_0_data -> altpll_0_pll_slave_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_008_out_0_ready;                                                            // altpll_0_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
	wire    [0:0] avalon_st_adapter_008_out_0_error;                                                            // avalon_st_adapter_008:out_0_error -> altpll_0_pll_slave_agent:rdata_fifo_sink_error
	wire          onchip_memory2_0_s1_agent_rdata_fifo_src_valid;                                               // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
	wire   [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data;                                                // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
	wire          onchip_memory2_0_s1_agent_rdata_fifo_src_ready;                                               // avalon_st_adapter_009:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_009_out_0_valid;                                                            // avalon_st_adapter_009:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_009_out_0_data;                                                             // avalon_st_adapter_009:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_009_out_0_ready;                                                            // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
	wire    [0:0] avalon_st_adapter_009_out_0_error;                                                            // avalon_st_adapter_009:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
	wire          switches_s1_agent_rdata_fifo_src_valid;                                                       // switches_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
	wire   [33:0] switches_s1_agent_rdata_fifo_src_data;                                                        // switches_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
	wire          switches_s1_agent_rdata_fifo_src_ready;                                                       // avalon_st_adapter_010:in_0_ready -> switches_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_010_out_0_valid;                                                            // avalon_st_adapter_010:out_0_valid -> switches_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_010_out_0_data;                                                             // avalon_st_adapter_010:out_0_data -> switches_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_010_out_0_ready;                                                            // switches_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
	wire    [0:0] avalon_st_adapter_010_out_0_error;                                                            // avalon_st_adapter_010:out_0_error -> switches_s1_agent:rdata_fifo_sink_error
	wire          leds_s1_agent_rdata_fifo_src_valid;                                                           // leds_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_011:in_0_valid
	wire   [33:0] leds_s1_agent_rdata_fifo_src_data;                                                            // leds_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_011:in_0_data
	wire          leds_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_011:in_0_ready -> leds_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_011_out_0_valid;                                                            // avalon_st_adapter_011:out_0_valid -> leds_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_011_out_0_data;                                                             // avalon_st_adapter_011:out_0_data -> leds_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_011_out_0_ready;                                                            // leds_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_011:out_0_ready
	wire    [0:0] avalon_st_adapter_011_out_0_error;                                                            // avalon_st_adapter_011:out_0_error -> leds_s1_agent:rdata_fifo_sink_error
	wire          uart_0_s1_agent_rdata_fifo_src_valid;                                                         // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_012:in_0_valid
	wire   [33:0] uart_0_s1_agent_rdata_fifo_src_data;                                                          // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_012:in_0_data
	wire          uart_0_s1_agent_rdata_fifo_src_ready;                                                         // avalon_st_adapter_012:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_012_out_0_valid;                                                            // avalon_st_adapter_012:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_012_out_0_data;                                                             // avalon_st_adapter_012:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_012_out_0_ready;                                                            // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_012:out_0_ready
	wire    [0:0] avalon_st_adapter_012_out_0_error;                                                            // avalon_st_adapter_012:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
	wire          hex0_s1_agent_rdata_fifo_src_valid;                                                           // hex0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_013:in_0_valid
	wire   [33:0] hex0_s1_agent_rdata_fifo_src_data;                                                            // hex0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_013:in_0_data
	wire          hex0_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_013:in_0_ready -> hex0_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_013_out_0_valid;                                                            // avalon_st_adapter_013:out_0_valid -> hex0_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_013_out_0_data;                                                             // avalon_st_adapter_013:out_0_data -> hex0_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_013_out_0_ready;                                                            // hex0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_013:out_0_ready
	wire    [0:0] avalon_st_adapter_013_out_0_error;                                                            // avalon_st_adapter_013:out_0_error -> hex0_s1_agent:rdata_fifo_sink_error
	wire          hex1_s1_agent_rdata_fifo_src_valid;                                                           // hex1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_014:in_0_valid
	wire   [33:0] hex1_s1_agent_rdata_fifo_src_data;                                                            // hex1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_014:in_0_data
	wire          hex1_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_014:in_0_ready -> hex1_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_014_out_0_valid;                                                            // avalon_st_adapter_014:out_0_valid -> hex1_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_014_out_0_data;                                                             // avalon_st_adapter_014:out_0_data -> hex1_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_014_out_0_ready;                                                            // hex1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_014:out_0_ready
	wire    [0:0] avalon_st_adapter_014_out_0_error;                                                            // avalon_st_adapter_014:out_0_error -> hex1_s1_agent:rdata_fifo_sink_error
	wire          hex2_s1_agent_rdata_fifo_src_valid;                                                           // hex2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_015:in_0_valid
	wire   [33:0] hex2_s1_agent_rdata_fifo_src_data;                                                            // hex2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_015:in_0_data
	wire          hex2_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_015:in_0_ready -> hex2_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_015_out_0_valid;                                                            // avalon_st_adapter_015:out_0_valid -> hex2_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_015_out_0_data;                                                             // avalon_st_adapter_015:out_0_data -> hex2_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_015_out_0_ready;                                                            // hex2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_015:out_0_ready
	wire    [0:0] avalon_st_adapter_015_out_0_error;                                                            // avalon_st_adapter_015:out_0_error -> hex2_s1_agent:rdata_fifo_sink_error
	wire          hex3_s1_agent_rdata_fifo_src_valid;                                                           // hex3_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_016:in_0_valid
	wire   [33:0] hex3_s1_agent_rdata_fifo_src_data;                                                            // hex3_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_016:in_0_data
	wire          hex3_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_016:in_0_ready -> hex3_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_016_out_0_valid;                                                            // avalon_st_adapter_016:out_0_valid -> hex3_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_016_out_0_data;                                                             // avalon_st_adapter_016:out_0_data -> hex3_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_016_out_0_ready;                                                            // hex3_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_016:out_0_ready
	wire    [0:0] avalon_st_adapter_016_out_0_error;                                                            // avalon_st_adapter_016:out_0_error -> hex3_s1_agent:rdata_fifo_sink_error
	wire          hex4_s1_agent_rdata_fifo_src_valid;                                                           // hex4_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_017:in_0_valid
	wire   [33:0] hex4_s1_agent_rdata_fifo_src_data;                                                            // hex4_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_017:in_0_data
	wire          hex4_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_017:in_0_ready -> hex4_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_017_out_0_valid;                                                            // avalon_st_adapter_017:out_0_valid -> hex4_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_017_out_0_data;                                                             // avalon_st_adapter_017:out_0_data -> hex4_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_017_out_0_ready;                                                            // hex4_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_017:out_0_ready
	wire    [0:0] avalon_st_adapter_017_out_0_error;                                                            // avalon_st_adapter_017:out_0_error -> hex4_s1_agent:rdata_fifo_sink_error
	wire          hex5_s1_agent_rdata_fifo_src_valid;                                                           // hex5_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_018:in_0_valid
	wire   [33:0] hex5_s1_agent_rdata_fifo_src_data;                                                            // hex5_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_018:in_0_data
	wire          hex5_s1_agent_rdata_fifo_src_ready;                                                           // avalon_st_adapter_018:in_0_ready -> hex5_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_018_out_0_valid;                                                            // avalon_st_adapter_018:out_0_valid -> hex5_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_018_out_0_data;                                                             // avalon_st_adapter_018:out_0_data -> hex5_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_018_out_0_ready;                                                            // hex5_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_018:out_0_ready
	wire    [0:0] avalon_st_adapter_018_out_0_error;                                                            // avalon_st_adapter_018:out_0_error -> hex5_s1_agent:rdata_fifo_sink_error
	wire          hexdot_s1_agent_rdata_fifo_src_valid;                                                         // hexdot_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_019:in_0_valid
	wire   [33:0] hexdot_s1_agent_rdata_fifo_src_data;                                                          // hexdot_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_019:in_0_data
	wire          hexdot_s1_agent_rdata_fifo_src_ready;                                                         // avalon_st_adapter_019:in_0_ready -> hexdot_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_019_out_0_valid;                                                            // avalon_st_adapter_019:out_0_valid -> hexdot_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_019_out_0_data;                                                             // avalon_st_adapter_019:out_0_data -> hexdot_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_019_out_0_ready;                                                            // hexdot_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_019:out_0_ready
	wire    [0:0] avalon_st_adapter_019_out_0_error;                                                            // avalon_st_adapter_019:out_0_error -> hexdot_s1_agent:rdata_fifo_sink_error
	wire          spi_sync_s1_agent_rdata_fifo_src_valid;                                                       // spi_sync_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_020:in_0_valid
	wire   [33:0] spi_sync_s1_agent_rdata_fifo_src_data;                                                        // spi_sync_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_020:in_0_data
	wire          spi_sync_s1_agent_rdata_fifo_src_ready;                                                       // avalon_st_adapter_020:in_0_ready -> spi_sync_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_020_out_0_valid;                                                            // avalon_st_adapter_020:out_0_valid -> spi_sync_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_020_out_0_data;                                                             // avalon_st_adapter_020:out_0_data -> spi_sync_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_020_out_0_ready;                                                            // spi_sync_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_020:out_0_ready
	wire    [0:0] avalon_st_adapter_020_out_0_error;                                                            // avalon_st_adapter_020:out_0_error -> spi_sync_s1_agent:rdata_fifo_sink_error
	wire          extra_leds_s1_agent_rdata_fifo_src_valid;                                                     // extra_leds_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_021:in_0_valid
	wire   [33:0] extra_leds_s1_agent_rdata_fifo_src_data;                                                      // extra_leds_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_021:in_0_data
	wire          extra_leds_s1_agent_rdata_fifo_src_ready;                                                     // avalon_st_adapter_021:in_0_ready -> extra_leds_s1_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_021_out_0_valid;                                                            // avalon_st_adapter_021:out_0_valid -> extra_leds_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_021_out_0_data;                                                             // avalon_st_adapter_021:out_0_data -> extra_leds_s1_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_021_out_0_ready;                                                            // extra_leds_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_021:out_0_ready
	wire    [0:0] avalon_st_adapter_021_out_0_error;                                                            // avalon_st_adapter_021:out_0_error -> extra_leds_s1_agent:rdata_fifo_sink_error
	wire          spi_stm32_spi_control_port_agent_rdata_fifo_src_valid;                                        // spi_stm32_spi_control_port_agent:rdata_fifo_src_valid -> avalon_st_adapter_022:in_0_valid
	wire   [33:0] spi_stm32_spi_control_port_agent_rdata_fifo_src_data;                                         // spi_stm32_spi_control_port_agent:rdata_fifo_src_data -> avalon_st_adapter_022:in_0_data
	wire          spi_stm32_spi_control_port_agent_rdata_fifo_src_ready;                                        // avalon_st_adapter_022:in_0_ready -> spi_stm32_spi_control_port_agent:rdata_fifo_src_ready
	wire          avalon_st_adapter_022_out_0_valid;                                                            // avalon_st_adapter_022:out_0_valid -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_valid
	wire   [33:0] avalon_st_adapter_022_out_0_data;                                                             // avalon_st_adapter_022:out_0_data -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_data
	wire          avalon_st_adapter_022_out_0_ready;                                                            // spi_stm32_spi_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_022:out_0_ready
	wire    [0:0] avalon_st_adapter_022_out_0_error;                                                            // avalon_st_adapter_022:out_0_error -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_error

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (28),
		.AV_DATA_W                   (16),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (2),
		.UAV_ADDRESS_W               (28),
		.UAV_BURSTCOUNT_W            (2),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (2),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) abus_slave_0_avalon_master_translator (
		.clk                    (altpll_0_c0_clk),                                                               //                       clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),                                //                     reset.reset
		.uav_address            (abus_slave_0_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (abus_slave_0_avalon_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (abus_slave_0_avalon_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (abus_slave_0_avalon_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (abus_slave_0_avalon_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount          (abus_slave_0_avalon_master_burstcount),                                         //                          .burstcount
		.av_byteenable          (abus_slave_0_avalon_master_byteenable),                                         //                          .byteenable
		.av_read                (abus_slave_0_avalon_master_read),                                               //                          .read
		.av_readdata            (abus_slave_0_avalon_master_readdata),                                           //                          .readdata
		.av_readdatavalid       (abus_slave_0_avalon_master_readdatavalid),                                      //                          .readdatavalid
		.av_write               (abus_slave_0_avalon_master_write),                                              //                          .write
		.av_writedata           (abus_slave_0_avalon_master_writedata),                                          //                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                          //               (terminated)
		.av_begintransfer       (1'b0),                                                                          //               (terminated)
		.av_chipselect          (1'b0),                                                                          //               (terminated)
		.av_lock                (1'b0),                                                                          //               (terminated)
		.av_debugaccess         (1'b0),                                                                          //               (terminated)
		.uav_clken              (),                                                                              //               (terminated)
		.av_clken               (1'b1),                                                                          //               (terminated)
		.uav_response           (2'b00),                                                                         //               (terminated)
		.av_response            (),                                                                              //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                          //               (terminated)
		.av_writeresponsevalid  ()                                                                               //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (28),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (28),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) nios2_gen2_0_data_master_translator (
		.clk                    (altpll_0_c0_clk),                                                             //                       clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),                              //                     reset.reset
		.uav_address            (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (nios2_gen2_0_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (nios2_gen2_0_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (nios2_gen2_0_data_master_byteenable),                                         //                          .byteenable
		.av_read                (nios2_gen2_0_data_master_read),                                               //                          .read
		.av_readdata            (nios2_gen2_0_data_master_readdata),                                           //                          .readdata
		.av_write               (nios2_gen2_0_data_master_write),                                              //                          .write
		.av_writedata           (nios2_gen2_0_data_master_writedata),                                          //                          .writedata
		.av_debugaccess         (nios2_gen2_0_data_master_debugaccess),                                        //                          .debugaccess
		.av_burstcount          (1'b1),                                                                        //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                        //               (terminated)
		.av_begintransfer       (1'b0),                                                                        //               (terminated)
		.av_chipselect          (1'b0),                                                                        //               (terminated)
		.av_readdatavalid       (),                                                                            //               (terminated)
		.av_lock                (1'b0),                                                                        //               (terminated)
		.uav_clken              (),                                                                            //               (terminated)
		.av_clken               (1'b1),                                                                        //               (terminated)
		.uav_response           (2'b00),                                                                       //               (terminated)
		.av_response            (),                                                                            //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                        //               (terminated)
		.av_writeresponsevalid  ()                                                                             //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (28),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (28),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) nios2_gen2_0_instruction_master_translator (
		.clk                    (altpll_0_c0_clk),                                                                    //                       clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),                                     //                     reset.reset
		.uav_address            (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (nios2_gen2_0_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (nios2_gen2_0_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read                (nios2_gen2_0_instruction_master_read),                                               //                          .read
		.av_readdata            (nios2_gen2_0_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount          (1'b1),                                                                               //               (terminated)
		.av_byteenable          (4'b1111),                                                                            //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                               //               (terminated)
		.av_begintransfer       (1'b0),                                                                               //               (terminated)
		.av_chipselect          (1'b0),                                                                               //               (terminated)
		.av_readdatavalid       (),                                                                                   //               (terminated)
		.av_write               (1'b0),                                                                               //               (terminated)
		.av_writedata           (32'b00000000000000000000000000000000),                                               //               (terminated)
		.av_lock                (1'b0),                                                                               //               (terminated)
		.av_debugaccess         (1'b0),                                                                               //               (terminated)
		.uav_clken              (),                                                                                   //               (terminated)
		.av_clken               (1'b1),                                                                               //               (terminated)
		.uav_response           (2'b00),                                                                              //               (terminated)
		.av_response            (),                                                                                   //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                               //               (terminated)
		.av_writeresponsevalid  ()                                                                                    //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (16),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (2),
		.UAV_BYTEENABLE_W               (2),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (2),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (2),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) external_sdram_controller_s1_translator (
		.clk                    (altpll_0_c0_clk),                                     //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),      //                    reset.reset
		.uav_address            (external_sdram_controller_s1_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (external_sdram_controller_s1_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (external_sdram_controller_s1_agent_m0_read),          //                         .read
		.uav_write              (external_sdram_controller_s1_agent_m0_write),         //                         .write
		.uav_waitrequest        (external_sdram_controller_s1_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (external_sdram_controller_s1_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (external_sdram_controller_s1_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (external_sdram_controller_s1_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (external_sdram_controller_s1_agent_m0_writedata),     //                         .writedata
		.uav_lock               (external_sdram_controller_s1_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (external_sdram_controller_s1_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (external_sdram_controller_s1_address),                //      avalon_anti_slave_0.address
		.av_write               (external_sdram_controller_s1_write),                  //                         .write
		.av_read                (external_sdram_controller_s1_read),                   //                         .read
		.av_readdata            (external_sdram_controller_s1_readdata),               //                         .readdata
		.av_writedata           (external_sdram_controller_s1_writedata),              //                         .writedata
		.av_byteenable          (external_sdram_controller_s1_byteenable),             //                         .byteenable
		.av_readdatavalid       (external_sdram_controller_s1_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (external_sdram_controller_s1_waitrequest),            //                         .waitrequest
		.av_chipselect          (external_sdram_controller_s1_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                    //              (terminated)
		.av_beginbursttransfer  (),                                                    //              (terminated)
		.av_burstcount          (),                                                    //              (terminated)
		.av_writebyteenable     (),                                                    //              (terminated)
		.av_lock                (),                                                    //              (terminated)
		.av_clken               (),                                                    //              (terminated)
		.uav_clken              (1'b0),                                                //              (terminated)
		.av_debugaccess         (),                                                    //              (terminated)
		.av_outputenable        (),                                                    //              (terminated)
		.uav_response           (),                                                    //              (terminated)
		.av_response            (2'b00),                                               //              (terminated)
		.uav_writeresponsevalid (),                                                    //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (10),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_memory2_1_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_memory2_1_s1_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_memory2_1_s1_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (onchip_memory2_1_s1_agent_m0_read),              //                         .read
		.uav_write              (onchip_memory2_1_s1_agent_m0_write),             //                         .write
		.uav_waitrequest        (onchip_memory2_1_s1_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (onchip_memory2_1_s1_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (onchip_memory2_1_s1_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (onchip_memory2_1_s1_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (onchip_memory2_1_s1_agent_m0_writedata),         //                         .writedata
		.uav_lock               (onchip_memory2_1_s1_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (onchip_memory2_1_s1_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (onchip_memory2_1_s1_address),                    //      avalon_anti_slave_0.address
		.av_write               (onchip_memory2_1_s1_write),                      //                         .write
		.av_readdata            (onchip_memory2_1_s1_readdata),                   //                         .readdata
		.av_writedata           (onchip_memory2_1_s1_writedata),                  //                         .writedata
		.av_byteenable          (onchip_memory2_1_s1_byteenable),                 //                         .byteenable
		.av_chipselect          (onchip_memory2_1_s1_chipselect),                 //                         .chipselect
		.av_clken               (onchip_memory2_1_s1_clken),                      //                         .clken
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) abus_slave_0_avalon_nios_translator (
		.clk                    (altpll_0_c0_clk),                                 //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),  //                    reset.reset
		.uav_address            (abus_slave_0_avalon_nios_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (abus_slave_0_avalon_nios_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (abus_slave_0_avalon_nios_agent_m0_read),          //                         .read
		.uav_write              (abus_slave_0_avalon_nios_agent_m0_write),         //                         .write
		.uav_waitrequest        (abus_slave_0_avalon_nios_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (abus_slave_0_avalon_nios_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (abus_slave_0_avalon_nios_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (abus_slave_0_avalon_nios_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (abus_slave_0_avalon_nios_agent_m0_writedata),     //                         .writedata
		.uav_lock               (abus_slave_0_avalon_nios_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (abus_slave_0_avalon_nios_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (abus_slave_0_avalon_nios_address),                //      avalon_anti_slave_0.address
		.av_write               (abus_slave_0_avalon_nios_write),                  //                         .write
		.av_read                (abus_slave_0_avalon_nios_read),                   //                         .read
		.av_readdata            (abus_slave_0_avalon_nios_readdata),               //                         .readdata
		.av_writedata           (abus_slave_0_avalon_nios_writedata),              //                         .writedata
		.av_burstcount          (abus_slave_0_avalon_nios_burstcount),             //                         .burstcount
		.av_readdatavalid       (abus_slave_0_avalon_nios_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (abus_slave_0_avalon_nios_waitrequest),            //                         .waitrequest
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (8),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) abus_demux_0_avalon_nios_translator (
		.clk                    (altpll_0_c0_clk),                                 //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),  //                    reset.reset
		.uav_address            (abus_demux_0_avalon_nios_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (abus_demux_0_avalon_nios_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (abus_demux_0_avalon_nios_agent_m0_read),          //                         .read
		.uav_write              (abus_demux_0_avalon_nios_agent_m0_write),         //                         .write
		.uav_waitrequest        (abus_demux_0_avalon_nios_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (abus_demux_0_avalon_nios_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (abus_demux_0_avalon_nios_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (abus_demux_0_avalon_nios_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (abus_demux_0_avalon_nios_agent_m0_writedata),     //                         .writedata
		.uav_lock               (abus_demux_0_avalon_nios_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (abus_demux_0_avalon_nios_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (abus_demux_0_avalon_nios_address),                //      avalon_anti_slave_0.address
		.av_write               (abus_demux_0_avalon_nios_write),                  //                         .write
		.av_read                (abus_demux_0_avalon_nios_read),                   //                         .read
		.av_readdata            (abus_demux_0_avalon_nios_readdata),               //                         .readdata
		.av_writedata           (abus_demux_0_avalon_nios_writedata),              //                         .writedata
		.av_burstcount          (abus_demux_0_avalon_nios_burstcount),             //                         .burstcount
		.av_readdatavalid       (abus_demux_0_avalon_nios_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (abus_demux_0_avalon_nios_waitrequest),            //                         .waitrequest
		.av_begintransfer       (),                                                //              (terminated)
		.av_beginbursttransfer  (),                                                //              (terminated)
		.av_byteenable          (),                                                //              (terminated)
		.av_writebyteenable     (),                                                //              (terminated)
		.av_lock                (),                                                //              (terminated)
		.av_chipselect          (),                                                //              (terminated)
		.av_clken               (),                                                //              (terminated)
		.uav_clken              (1'b0),                                            //              (terminated)
		.av_debugaccess         (),                                                //              (terminated)
		.av_outputenable        (),                                                //              (terminated)
		.uav_response           (),                                                //              (terminated)
		.av_response            (2'b00),                                           //              (terminated)
		.uav_writeresponsevalid (),                                                //              (terminated)
		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) performance_counter_0_control_slave_translator (
		.clk                    (altpll_0_c0_clk),                                            //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),             //                    reset.reset
		.uav_address            (performance_counter_0_control_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (performance_counter_0_control_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (performance_counter_0_control_slave_agent_m0_read),          //                         .read
		.uav_write              (performance_counter_0_control_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (performance_counter_0_control_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (performance_counter_0_control_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (performance_counter_0_control_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (performance_counter_0_control_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (performance_counter_0_control_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (performance_counter_0_control_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (performance_counter_0_control_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (performance_counter_0_control_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (performance_counter_0_control_slave_write),                  //                         .write
		.av_readdata            (performance_counter_0_control_slave_readdata),               //                         .readdata
		.av_writedata           (performance_counter_0_control_slave_writedata),              //                         .writedata
		.av_begintransfer       (performance_counter_0_control_slave_begintransfer),          //                         .begintransfer
		.av_read                (),                                                           //              (terminated)
		.av_beginbursttransfer  (),                                                           //              (terminated)
		.av_burstcount          (),                                                           //              (terminated)
		.av_byteenable          (),                                                           //              (terminated)
		.av_readdatavalid       (1'b0),                                                       //              (terminated)
		.av_waitrequest         (1'b0),                                                       //              (terminated)
		.av_writebyteenable     (),                                                           //              (terminated)
		.av_lock                (),                                                           //              (terminated)
		.av_chipselect          (),                                                           //              (terminated)
		.av_clken               (),                                                           //              (terminated)
		.uav_clken              (1'b0),                                                       //              (terminated)
		.av_debugaccess         (),                                                           //              (terminated)
		.av_outputenable        (),                                                           //              (terminated)
		.uav_response           (),                                                           //              (terminated)
		.av_response            (2'b00),                                                      //              (terminated)
		.uav_writeresponsevalid (),                                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_flash_0_csr_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_flash_0_csr_agent_m0_address),            // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_flash_0_csr_agent_m0_burstcount),         //                         .burstcount
		.uav_read               (onchip_flash_0_csr_agent_m0_read),               //                         .read
		.uav_write              (onchip_flash_0_csr_agent_m0_write),              //                         .write
		.uav_waitrequest        (onchip_flash_0_csr_agent_m0_waitrequest),        //                         .waitrequest
		.uav_readdatavalid      (onchip_flash_0_csr_agent_m0_readdatavalid),      //                         .readdatavalid
		.uav_byteenable         (onchip_flash_0_csr_agent_m0_byteenable),         //                         .byteenable
		.uav_readdata           (onchip_flash_0_csr_agent_m0_readdata),           //                         .readdata
		.uav_writedata          (onchip_flash_0_csr_agent_m0_writedata),          //                         .writedata
		.uav_lock               (onchip_flash_0_csr_agent_m0_lock),               //                         .lock
		.uav_debugaccess        (onchip_flash_0_csr_agent_m0_debugaccess),        //                         .debugaccess
		.av_address             (onchip_flash_0_csr_address),                     //      avalon_anti_slave_0.address
		.av_write               (onchip_flash_0_csr_write),                       //                         .write
		.av_read                (onchip_flash_0_csr_read),                        //                         .read
		.av_readdata            (onchip_flash_0_csr_readdata),                    //                         .readdata
		.av_writedata           (onchip_flash_0_csr_writedata),                   //                         .writedata
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (19),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (4),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (6),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_flash_0_data_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_flash_0_data_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_flash_0_data_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (onchip_flash_0_data_agent_m0_read),              //                         .read
		.uav_write              (onchip_flash_0_data_agent_m0_write),             //                         .write
		.uav_waitrequest        (onchip_flash_0_data_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (onchip_flash_0_data_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (onchip_flash_0_data_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (onchip_flash_0_data_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (onchip_flash_0_data_agent_m0_writedata),         //                         .writedata
		.uav_lock               (onchip_flash_0_data_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (onchip_flash_0_data_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (onchip_flash_0_data_address),                    //      avalon_anti_slave_0.address
		.av_write               (onchip_flash_0_data_write),                      //                         .write
		.av_read                (onchip_flash_0_data_read),                       //                         .read
		.av_readdata            (onchip_flash_0_data_readdata),                   //                         .readdata
		.av_writedata           (onchip_flash_0_data_writedata),                  //                         .writedata
		.av_burstcount          (onchip_flash_0_data_burstcount),                 //                         .burstcount
		.av_readdatavalid       (onchip_flash_0_data_readdatavalid),              //                         .readdatavalid
		.av_waitrequest         (onchip_flash_0_data_waitrequest),                //                         .waitrequest
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) nios2_gen2_0_debug_mem_slave_translator (
		.clk                    (altpll_0_c0_clk),                                     //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),      //                    reset.reset
		.uav_address            (nios2_gen2_0_debug_mem_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (nios2_gen2_0_debug_mem_slave_agent_m0_read),          //                         .read
		.uav_write              (nios2_gen2_0_debug_mem_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (nios2_gen2_0_debug_mem_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (nios2_gen2_0_debug_mem_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (nios2_gen2_0_debug_mem_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (nios2_gen2_0_debug_mem_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (nios2_gen2_0_debug_mem_slave_write),                  //                         .write
		.av_read                (nios2_gen2_0_debug_mem_slave_read),                   //                         .read
		.av_readdata            (nios2_gen2_0_debug_mem_slave_readdata),               //                         .readdata
		.av_writedata           (nios2_gen2_0_debug_mem_slave_writedata),              //                         .writedata
		.av_byteenable          (nios2_gen2_0_debug_mem_slave_byteenable),             //                         .byteenable
		.av_waitrequest         (nios2_gen2_0_debug_mem_slave_waitrequest),            //                         .waitrequest
		.av_debugaccess         (nios2_gen2_0_debug_mem_slave_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                                    //              (terminated)
		.av_beginbursttransfer  (),                                                    //              (terminated)
		.av_burstcount          (),                                                    //              (terminated)
		.av_readdatavalid       (1'b0),                                                //              (terminated)
		.av_writebyteenable     (),                                                    //              (terminated)
		.av_lock                (),                                                    //              (terminated)
		.av_chipselect          (),                                                    //              (terminated)
		.av_clken               (),                                                    //              (terminated)
		.uav_clken              (1'b0),                                                //              (terminated)
		.av_outputenable        (),                                                    //              (terminated)
		.uav_response           (),                                                    //              (terminated)
		.av_response            (2'b00),                                               //              (terminated)
		.uav_writeresponsevalid (),                                                    //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) altpll_0_pll_slave_translator (
		.clk                    (clk_0_clk_clk),                                              //                      clk.clk
		.reset                  (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (altpll_0_pll_slave_agent_m0_address),                        // avalon_universal_slave_0.address
		.uav_burstcount         (altpll_0_pll_slave_agent_m0_burstcount),                     //                         .burstcount
		.uav_read               (altpll_0_pll_slave_agent_m0_read),                           //                         .read
		.uav_write              (altpll_0_pll_slave_agent_m0_write),                          //                         .write
		.uav_waitrequest        (altpll_0_pll_slave_agent_m0_waitrequest),                    //                         .waitrequest
		.uav_readdatavalid      (altpll_0_pll_slave_agent_m0_readdatavalid),                  //                         .readdatavalid
		.uav_byteenable         (altpll_0_pll_slave_agent_m0_byteenable),                     //                         .byteenable
		.uav_readdata           (altpll_0_pll_slave_agent_m0_readdata),                       //                         .readdata
		.uav_writedata          (altpll_0_pll_slave_agent_m0_writedata),                      //                         .writedata
		.uav_lock               (altpll_0_pll_slave_agent_m0_lock),                           //                         .lock
		.uav_debugaccess        (altpll_0_pll_slave_agent_m0_debugaccess),                    //                         .debugaccess
		.av_address             (altpll_0_pll_slave_address),                                 //      avalon_anti_slave_0.address
		.av_write               (altpll_0_pll_slave_write),                                   //                         .write
		.av_read                (altpll_0_pll_slave_read),                                    //                         .read
		.av_readdata            (altpll_0_pll_slave_readdata),                                //                         .readdata
		.av_writedata           (altpll_0_pll_slave_writedata),                               //                         .writedata
		.av_begintransfer       (),                                                           //              (terminated)
		.av_beginbursttransfer  (),                                                           //              (terminated)
		.av_burstcount          (),                                                           //              (terminated)
		.av_byteenable          (),                                                           //              (terminated)
		.av_readdatavalid       (1'b0),                                                       //              (terminated)
		.av_waitrequest         (1'b0),                                                       //              (terminated)
		.av_writebyteenable     (),                                                           //              (terminated)
		.av_lock                (),                                                           //              (terminated)
		.av_chipselect          (),                                                           //              (terminated)
		.av_clken               (),                                                           //              (terminated)
		.uav_clken              (1'b0),                                                       //              (terminated)
		.av_debugaccess         (),                                                           //              (terminated)
		.av_outputenable        (),                                                           //              (terminated)
		.uav_response           (),                                                           //              (terminated)
		.av_response            (2'b00),                                                      //              (terminated)
		.uav_writeresponsevalid (),                                                           //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_memory2_0_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (onchip_memory2_0_s1_agent_m0_address),           // avalon_universal_slave_0.address
		.uav_burstcount         (onchip_memory2_0_s1_agent_m0_burstcount),        //                         .burstcount
		.uav_read               (onchip_memory2_0_s1_agent_m0_read),              //                         .read
		.uav_write              (onchip_memory2_0_s1_agent_m0_write),             //                         .write
		.uav_waitrequest        (onchip_memory2_0_s1_agent_m0_waitrequest),       //                         .waitrequest
		.uav_readdatavalid      (onchip_memory2_0_s1_agent_m0_readdatavalid),     //                         .readdatavalid
		.uav_byteenable         (onchip_memory2_0_s1_agent_m0_byteenable),        //                         .byteenable
		.uav_readdata           (onchip_memory2_0_s1_agent_m0_readdata),          //                         .readdata
		.uav_writedata          (onchip_memory2_0_s1_agent_m0_writedata),         //                         .writedata
		.uav_lock               (onchip_memory2_0_s1_agent_m0_lock),              //                         .lock
		.uav_debugaccess        (onchip_memory2_0_s1_agent_m0_debugaccess),       //                         .debugaccess
		.av_address             (onchip_memory2_0_s1_address),                    //      avalon_anti_slave_0.address
		.av_write               (onchip_memory2_0_s1_write),                      //                         .write
		.av_readdata            (onchip_memory2_0_s1_readdata),                   //                         .readdata
		.av_writedata           (onchip_memory2_0_s1_writedata),                  //                         .writedata
		.av_byteenable          (onchip_memory2_0_s1_byteenable),                 //                         .byteenable
		.av_chipselect          (onchip_memory2_0_s1_chipselect),                 //                         .chipselect
		.av_clken               (onchip_memory2_0_s1_clken),                      //                         .clken
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) switches_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (switches_s1_agent_m0_address),                   // avalon_universal_slave_0.address
		.uav_burstcount         (switches_s1_agent_m0_burstcount),                //                         .burstcount
		.uav_read               (switches_s1_agent_m0_read),                      //                         .read
		.uav_write              (switches_s1_agent_m0_write),                     //                         .write
		.uav_waitrequest        (switches_s1_agent_m0_waitrequest),               //                         .waitrequest
		.uav_readdatavalid      (switches_s1_agent_m0_readdatavalid),             //                         .readdatavalid
		.uav_byteenable         (switches_s1_agent_m0_byteenable),                //                         .byteenable
		.uav_readdata           (switches_s1_agent_m0_readdata),                  //                         .readdata
		.uav_writedata          (switches_s1_agent_m0_writedata),                 //                         .writedata
		.uav_lock               (switches_s1_agent_m0_lock),                      //                         .lock
		.uav_debugaccess        (switches_s1_agent_m0_debugaccess),               //                         .debugaccess
		.av_address             (switches_s1_address),                            //      avalon_anti_slave_0.address
		.av_readdata            (switches_s1_readdata),                           //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) leds_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (leds_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (leds_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (leds_s1_agent_m0_read),                          //                         .read
		.uav_write              (leds_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (leds_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (leds_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (leds_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (leds_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (leds_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (leds_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (leds_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (leds_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (leds_s1_write),                                  //                         .write
		.av_readdata            (leds_s1_readdata),                               //                         .readdata
		.av_writedata           (leds_s1_writedata),                              //                         .writedata
		.av_chipselect          (leds_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) uart_0_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (uart_0_s1_agent_m0_address),                     // avalon_universal_slave_0.address
		.uav_burstcount         (uart_0_s1_agent_m0_burstcount),                  //                         .burstcount
		.uav_read               (uart_0_s1_agent_m0_read),                        //                         .read
		.uav_write              (uart_0_s1_agent_m0_write),                       //                         .write
		.uav_waitrequest        (uart_0_s1_agent_m0_waitrequest),                 //                         .waitrequest
		.uav_readdatavalid      (uart_0_s1_agent_m0_readdatavalid),               //                         .readdatavalid
		.uav_byteenable         (uart_0_s1_agent_m0_byteenable),                  //                         .byteenable
		.uav_readdata           (uart_0_s1_agent_m0_readdata),                    //                         .readdata
		.uav_writedata          (uart_0_s1_agent_m0_writedata),                   //                         .writedata
		.uav_lock               (uart_0_s1_agent_m0_lock),                        //                         .lock
		.uav_debugaccess        (uart_0_s1_agent_m0_debugaccess),                 //                         .debugaccess
		.av_address             (uart_0_s1_address),                              //      avalon_anti_slave_0.address
		.av_write               (uart_0_s1_write),                                //                         .write
		.av_read                (uart_0_s1_read),                                 //                         .read
		.av_readdata            (uart_0_s1_readdata),                             //                         .readdata
		.av_writedata           (uart_0_s1_writedata),                            //                         .writedata
		.av_begintransfer       (uart_0_s1_begintransfer),                        //                         .begintransfer
		.av_chipselect          (uart_0_s1_chipselect),                           //                         .chipselect
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex0_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex0_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex0_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex0_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex0_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex0_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex0_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex0_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex0_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex0_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex0_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex0_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex0_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex0_s1_write),                                  //                         .write
		.av_readdata            (hex0_s1_readdata),                               //                         .readdata
		.av_writedata           (hex0_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex0_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex1_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex1_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex1_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex1_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex1_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex1_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex1_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex1_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex1_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex1_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex1_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex1_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex1_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex1_s1_write),                                  //                         .write
		.av_readdata            (hex1_s1_readdata),                               //                         .readdata
		.av_writedata           (hex1_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex1_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex2_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex2_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex2_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex2_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex2_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex2_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex2_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex2_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex2_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex2_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex2_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex2_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex2_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex2_s1_write),                                  //                         .write
		.av_readdata            (hex2_s1_readdata),                               //                         .readdata
		.av_writedata           (hex2_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex2_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex3_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex3_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex3_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex3_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex3_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex3_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex3_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex3_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex3_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex3_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex3_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex3_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex3_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex3_s1_write),                                  //                         .write
		.av_readdata            (hex3_s1_readdata),                               //                         .readdata
		.av_writedata           (hex3_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex3_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex4_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex4_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex4_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex4_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex4_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex4_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex4_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex4_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex4_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex4_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex4_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex4_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex4_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex4_s1_write),                                  //                         .write
		.av_readdata            (hex4_s1_readdata),                               //                         .readdata
		.av_writedata           (hex4_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex4_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hex5_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hex5_s1_agent_m0_address),                       // avalon_universal_slave_0.address
		.uav_burstcount         (hex5_s1_agent_m0_burstcount),                    //                         .burstcount
		.uav_read               (hex5_s1_agent_m0_read),                          //                         .read
		.uav_write              (hex5_s1_agent_m0_write),                         //                         .write
		.uav_waitrequest        (hex5_s1_agent_m0_waitrequest),                   //                         .waitrequest
		.uav_readdatavalid      (hex5_s1_agent_m0_readdatavalid),                 //                         .readdatavalid
		.uav_byteenable         (hex5_s1_agent_m0_byteenable),                    //                         .byteenable
		.uav_readdata           (hex5_s1_agent_m0_readdata),                      //                         .readdata
		.uav_writedata          (hex5_s1_agent_m0_writedata),                     //                         .writedata
		.uav_lock               (hex5_s1_agent_m0_lock),                          //                         .lock
		.uav_debugaccess        (hex5_s1_agent_m0_debugaccess),                   //                         .debugaccess
		.av_address             (hex5_s1_address),                                //      avalon_anti_slave_0.address
		.av_write               (hex5_s1_write),                                  //                         .write
		.av_readdata            (hex5_s1_readdata),                               //                         .readdata
		.av_writedata           (hex5_s1_writedata),                              //                         .writedata
		.av_chipselect          (hex5_s1_chipselect),                             //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hexdot_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (hexdot_s1_agent_m0_address),                     // avalon_universal_slave_0.address
		.uav_burstcount         (hexdot_s1_agent_m0_burstcount),                  //                         .burstcount
		.uav_read               (hexdot_s1_agent_m0_read),                        //                         .read
		.uav_write              (hexdot_s1_agent_m0_write),                       //                         .write
		.uav_waitrequest        (hexdot_s1_agent_m0_waitrequest),                 //                         .waitrequest
		.uav_readdatavalid      (hexdot_s1_agent_m0_readdatavalid),               //                         .readdatavalid
		.uav_byteenable         (hexdot_s1_agent_m0_byteenable),                  //                         .byteenable
		.uav_readdata           (hexdot_s1_agent_m0_readdata),                    //                         .readdata
		.uav_writedata          (hexdot_s1_agent_m0_writedata),                   //                         .writedata
		.uav_lock               (hexdot_s1_agent_m0_lock),                        //                         .lock
		.uav_debugaccess        (hexdot_s1_agent_m0_debugaccess),                 //                         .debugaccess
		.av_address             (hexdot_s1_address),                              //      avalon_anti_slave_0.address
		.av_write               (hexdot_s1_write),                                //                         .write
		.av_readdata            (hexdot_s1_readdata),                             //                         .readdata
		.av_writedata           (hexdot_s1_writedata),                            //                         .writedata
		.av_chipselect          (hexdot_s1_chipselect),                           //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) spi_sync_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (spi_sync_s1_agent_m0_address),                   // avalon_universal_slave_0.address
		.uav_burstcount         (spi_sync_s1_agent_m0_burstcount),                //                         .burstcount
		.uav_read               (spi_sync_s1_agent_m0_read),                      //                         .read
		.uav_write              (spi_sync_s1_agent_m0_write),                     //                         .write
		.uav_waitrequest        (spi_sync_s1_agent_m0_waitrequest),               //                         .waitrequest
		.uav_readdatavalid      (spi_sync_s1_agent_m0_readdatavalid),             //                         .readdatavalid
		.uav_byteenable         (spi_sync_s1_agent_m0_byteenable),                //                         .byteenable
		.uav_readdata           (spi_sync_s1_agent_m0_readdata),                  //                         .readdata
		.uav_writedata          (spi_sync_s1_agent_m0_writedata),                 //                         .writedata
		.uav_lock               (spi_sync_s1_agent_m0_lock),                      //                         .lock
		.uav_debugaccess        (spi_sync_s1_agent_m0_debugaccess),               //                         .debugaccess
		.av_address             (spi_sync_s1_address),                            //      avalon_anti_slave_0.address
		.av_readdata            (spi_sync_s1_readdata),                           //                         .readdata
		.av_write               (),                                               //              (terminated)
		.av_read                (),                                               //              (terminated)
		.av_writedata           (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_chipselect          (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) extra_leds_s1_translator (
		.clk                    (altpll_0_c0_clk),                                //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (extra_leds_s1_agent_m0_address),                 // avalon_universal_slave_0.address
		.uav_burstcount         (extra_leds_s1_agent_m0_burstcount),              //                         .burstcount
		.uav_read               (extra_leds_s1_agent_m0_read),                    //                         .read
		.uav_write              (extra_leds_s1_agent_m0_write),                   //                         .write
		.uav_waitrequest        (extra_leds_s1_agent_m0_waitrequest),             //                         .waitrequest
		.uav_readdatavalid      (extra_leds_s1_agent_m0_readdatavalid),           //                         .readdatavalid
		.uav_byteenable         (extra_leds_s1_agent_m0_byteenable),              //                         .byteenable
		.uav_readdata           (extra_leds_s1_agent_m0_readdata),                //                         .readdata
		.uav_writedata          (extra_leds_s1_agent_m0_writedata),               //                         .writedata
		.uav_lock               (extra_leds_s1_agent_m0_lock),                    //                         .lock
		.uav_debugaccess        (extra_leds_s1_agent_m0_debugaccess),             //                         .debugaccess
		.av_address             (extra_leds_s1_address),                          //      avalon_anti_slave_0.address
		.av_write               (extra_leds_s1_write),                            //                         .write
		.av_readdata            (extra_leds_s1_readdata),                         //                         .readdata
		.av_writedata           (extra_leds_s1_writedata),                        //                         .writedata
		.av_chipselect          (extra_leds_s1_chipselect),                       //                         .chipselect
		.av_read                (),                                               //              (terminated)
		.av_begintransfer       (),                                               //              (terminated)
		.av_beginbursttransfer  (),                                               //              (terminated)
		.av_burstcount          (),                                               //              (terminated)
		.av_byteenable          (),                                               //              (terminated)
		.av_readdatavalid       (1'b0),                                           //              (terminated)
		.av_waitrequest         (1'b0),                                           //              (terminated)
		.av_writebyteenable     (),                                               //              (terminated)
		.av_lock                (),                                               //              (terminated)
		.av_clken               (),                                               //              (terminated)
		.uav_clken              (1'b0),                                           //              (terminated)
		.av_debugaccess         (),                                               //              (terminated)
		.av_outputenable        (),                                               //              (terminated)
		.uav_response           (),                                               //              (terminated)
		.av_response            (2'b00),                                          //              (terminated)
		.uav_writeresponsevalid (),                                               //              (terminated)
		.av_writeresponsevalid  (1'b0)                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (28),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) spi_stm32_spi_control_port_translator (
		.clk                    (altpll_0_c0_clk),                                   //                      clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),    //                    reset.reset
		.uav_address            (spi_stm32_spi_control_port_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (spi_stm32_spi_control_port_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (spi_stm32_spi_control_port_agent_m0_read),          //                         .read
		.uav_write              (spi_stm32_spi_control_port_agent_m0_write),         //                         .write
		.uav_waitrequest        (spi_stm32_spi_control_port_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (spi_stm32_spi_control_port_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (spi_stm32_spi_control_port_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (spi_stm32_spi_control_port_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (spi_stm32_spi_control_port_agent_m0_writedata),     //                         .writedata
		.uav_lock               (spi_stm32_spi_control_port_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (spi_stm32_spi_control_port_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (spi_stm32_spi_control_port_address),                //      avalon_anti_slave_0.address
		.av_write               (spi_stm32_spi_control_port_write),                  //                         .write
		.av_read                (spi_stm32_spi_control_port_read),                   //                         .read
		.av_readdata            (spi_stm32_spi_control_port_readdata),               //                         .readdata
		.av_writedata           (spi_stm32_spi_control_port_writedata),              //                         .writedata
		.av_chipselect          (spi_stm32_spi_control_port_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                  //              (terminated)
		.av_beginbursttransfer  (),                                                  //              (terminated)
		.av_burstcount          (),                                                  //              (terminated)
		.av_byteenable          (),                                                  //              (terminated)
		.av_readdatavalid       (1'b0),                                              //              (terminated)
		.av_waitrequest         (1'b0),                                              //              (terminated)
		.av_writebyteenable     (),                                                  //              (terminated)
		.av_lock                (),                                                  //              (terminated)
		.av_clken               (),                                                  //              (terminated)
		.uav_clken              (1'b0),                                              //              (terminated)
		.av_debugaccess         (),                                                  //              (terminated)
		.av_outputenable        (),                                                  //              (terminated)
		.uav_response           (),                                                  //              (terminated)
		.av_response            (2'b00),                                             //              (terminated)
		.uav_writeresponsevalid (),                                                  //              (terminated)
		.av_writeresponsevalid  (1'b0)                                               //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (92),
		.PKT_ORI_BURST_SIZE_L      (90),
		.PKT_RESPONSE_STATUS_H     (89),
		.PKT_RESPONSE_STATUS_L     (88),
		.PKT_QOS_H                 (69),
		.PKT_QOS_L                 (69),
		.PKT_DATA_SIDEBAND_H       (67),
		.PKT_DATA_SIDEBAND_L       (67),
		.PKT_ADDR_SIDEBAND_H       (66),
		.PKT_ADDR_SIDEBAND_L       (66),
		.PKT_BURST_TYPE_H          (65),
		.PKT_BURST_TYPE_L          (64),
		.PKT_CACHE_H               (87),
		.PKT_CACHE_L               (84),
		.PKT_THREAD_ID_H           (80),
		.PKT_THREAD_ID_L           (80),
		.PKT_BURST_SIZE_H          (63),
		.PKT_BURST_SIZE_L          (61),
		.PKT_TRANS_EXCLUSIVE       (51),
		.PKT_TRANS_LOCK            (50),
		.PKT_BEGIN_BURST           (68),
		.PKT_PROTECTION_H          (83),
		.PKT_PROTECTION_L          (81),
		.PKT_BURSTWRAP_H           (60),
		.PKT_BURSTWRAP_L           (58),
		.PKT_BYTE_CNT_H            (57),
		.PKT_BYTE_CNT_L            (52),
		.PKT_ADDR_H                (45),
		.PKT_ADDR_L                (18),
		.PKT_TRANS_COMPRESSED_READ (46),
		.PKT_TRANS_POSTED          (47),
		.PKT_TRANS_WRITE           (48),
		.PKT_TRANS_READ            (49),
		.PKT_DATA_H                (15),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (70),
		.PKT_DEST_ID_H             (79),
		.PKT_DEST_ID_L             (75),
		.ST_DATA_W                 (93),
		.ST_CHANNEL_W              (23),
		.AV_BURSTCOUNT_W           (2),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) abus_slave_0_avalon_master_agent (
		.clk                   (altpll_0_c0_clk),                                                               //       clk.clk
		.reset                 (abus_slave_0_reset_reset_bridge_in_reset_reset),                                // clk_reset.reset
		.av_address            (abus_slave_0_avalon_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (abus_slave_0_avalon_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (abus_slave_0_avalon_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (abus_slave_0_avalon_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (abus_slave_0_avalon_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (abus_slave_0_avalon_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (abus_slave_0_avalon_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (abus_slave_0_avalon_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (abus_slave_0_avalon_master_limiter_rsp_src_valid),                              //        rp.valid
		.rp_data               (abus_slave_0_avalon_master_limiter_rsp_src_data),                               //          .data
		.rp_channel            (abus_slave_0_avalon_master_limiter_rsp_src_channel),                            //          .channel
		.rp_startofpacket      (abus_slave_0_avalon_master_limiter_rsp_src_startofpacket),                      //          .startofpacket
		.rp_endofpacket        (abus_slave_0_avalon_master_limiter_rsp_src_endofpacket),                        //          .endofpacket
		.rp_ready              (abus_slave_0_avalon_master_limiter_rsp_src_ready),                              //          .ready
		.av_response           (),                                                                              // (terminated)
		.av_writeresponsevalid ()                                                                               // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_QOS_H                 (87),
		.PKT_QOS_L                 (87),
		.PKT_DATA_SIDEBAND_H       (85),
		.PKT_DATA_SIDEBAND_L       (85),
		.PKT_ADDR_SIDEBAND_H       (84),
		.PKT_ADDR_SIDEBAND_L       (84),
		.PKT_BURST_TYPE_H          (83),
		.PKT_BURST_TYPE_L          (82),
		.PKT_CACHE_H               (105),
		.PKT_CACHE_L               (102),
		.PKT_THREAD_ID_H           (98),
		.PKT_THREAD_ID_L           (98),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_EXCLUSIVE       (69),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.ST_DATA_W                 (111),
		.ST_CHANNEL_W              (23),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) nios2_gen2_0_data_master_agent (
		.clk                   (altpll_0_c0_clk),                                                             //       clk.clk
		.reset                 (abus_slave_0_reset_reset_bridge_in_reset_reset),                              // clk_reset.reset
		.av_address            (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (nios2_gen2_0_data_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (nios2_gen2_0_data_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (nios2_gen2_0_data_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (nios2_gen2_0_data_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (nios2_gen2_0_data_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                       //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                        //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                                     //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                               //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                                 //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                       //          .ready
		.av_response           (),                                                                            // (terminated)
		.av_writeresponsevalid ()                                                                             // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_QOS_H                 (87),
		.PKT_QOS_L                 (87),
		.PKT_DATA_SIDEBAND_H       (85),
		.PKT_DATA_SIDEBAND_L       (85),
		.PKT_ADDR_SIDEBAND_H       (84),
		.PKT_ADDR_SIDEBAND_L       (84),
		.PKT_BURST_TYPE_H          (83),
		.PKT_BURST_TYPE_L          (82),
		.PKT_CACHE_H               (105),
		.PKT_CACHE_L               (102),
		.PKT_THREAD_ID_H           (98),
		.PKT_THREAD_ID_L           (98),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_EXCLUSIVE       (69),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.ST_DATA_W                 (111),
		.ST_CHANNEL_W              (23),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (3),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) nios2_gen2_0_instruction_master_agent (
		.clk                   (altpll_0_c0_clk),                                                                    //       clk.clk
		.reset                 (abus_slave_0_reset_reset_bridge_in_reset_reset),                                     // clk_reset.reset
		.av_address            (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (nios2_gen2_0_instruction_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (nios2_gen2_0_instruction_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (nios2_gen2_0_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (nios2_gen2_0_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (nios2_gen2_0_instruction_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_002_src_valid),                                                              //        rp.valid
		.rp_data               (rsp_mux_002_src_data),                                                               //          .data
		.rp_channel            (rsp_mux_002_src_channel),                                                            //          .channel
		.rp_startofpacket      (rsp_mux_002_src_startofpacket),                                                      //          .startofpacket
		.rp_endofpacket        (rsp_mux_002_src_endofpacket),                                                        //          .endofpacket
		.rp_ready              (rsp_mux_002_src_ready),                                                              //          .ready
		.av_response           (),                                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                                    // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (92),
		.PKT_ORI_BURST_SIZE_L      (90),
		.PKT_RESPONSE_STATUS_H     (89),
		.PKT_RESPONSE_STATUS_L     (88),
		.PKT_BURST_SIZE_H          (63),
		.PKT_BURST_SIZE_L          (61),
		.PKT_TRANS_LOCK            (50),
		.PKT_BEGIN_BURST           (68),
		.PKT_PROTECTION_H          (83),
		.PKT_PROTECTION_L          (81),
		.PKT_BURSTWRAP_H           (60),
		.PKT_BURSTWRAP_L           (58),
		.PKT_BYTE_CNT_H            (57),
		.PKT_BYTE_CNT_L            (52),
		.PKT_ADDR_H                (45),
		.PKT_ADDR_L                (18),
		.PKT_TRANS_COMPRESSED_READ (46),
		.PKT_TRANS_POSTED          (47),
		.PKT_TRANS_WRITE           (48),
		.PKT_TRANS_READ            (49),
		.PKT_DATA_H                (15),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (70),
		.PKT_DEST_ID_H             (79),
		.PKT_DEST_ID_L             (75),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (93),
		.AVS_BURSTCOUNT_W          (2),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) external_sdram_controller_s1_agent (
		.clk                     (altpll_0_c0_clk),                                                  //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),                   //       clk_reset.reset
		.m0_address              (external_sdram_controller_s1_agent_m0_address),                    //              m0.address
		.m0_burstcount           (external_sdram_controller_s1_agent_m0_burstcount),                 //                .burstcount
		.m0_byteenable           (external_sdram_controller_s1_agent_m0_byteenable),                 //                .byteenable
		.m0_debugaccess          (external_sdram_controller_s1_agent_m0_debugaccess),                //                .debugaccess
		.m0_lock                 (external_sdram_controller_s1_agent_m0_lock),                       //                .lock
		.m0_readdata             (external_sdram_controller_s1_agent_m0_readdata),                   //                .readdata
		.m0_readdatavalid        (external_sdram_controller_s1_agent_m0_readdatavalid),              //                .readdatavalid
		.m0_read                 (external_sdram_controller_s1_agent_m0_read),                       //                .read
		.m0_waitrequest          (external_sdram_controller_s1_agent_m0_waitrequest),                //                .waitrequest
		.m0_writedata            (external_sdram_controller_s1_agent_m0_writedata),                  //                .writedata
		.m0_write                (external_sdram_controller_s1_agent_m0_write),                      //                .write
		.rp_endofpacket          (external_sdram_controller_s1_agent_rp_endofpacket),                //              rp.endofpacket
		.rp_ready                (external_sdram_controller_s1_agent_rp_ready),                      //                .ready
		.rp_valid                (external_sdram_controller_s1_agent_rp_valid),                      //                .valid
		.rp_data                 (external_sdram_controller_s1_agent_rp_data),                       //                .data
		.rp_startofpacket        (external_sdram_controller_s1_agent_rp_startofpacket),              //                .startofpacket
		.cp_ready                (external_sdram_controller_s1_burst_adapter_source0_ready),         //              cp.ready
		.cp_valid                (external_sdram_controller_s1_burst_adapter_source0_valid),         //                .valid
		.cp_data                 (external_sdram_controller_s1_burst_adapter_source0_data),          //                .data
		.cp_startofpacket        (external_sdram_controller_s1_burst_adapter_source0_startofpacket), //                .startofpacket
		.cp_endofpacket          (external_sdram_controller_s1_burst_adapter_source0_endofpacket),   //                .endofpacket
		.cp_channel              (external_sdram_controller_s1_burst_adapter_source0_channel),       //                .channel
		.rf_sink_ready           (external_sdram_controller_s1_agent_rsp_fifo_out_ready),            //         rf_sink.ready
		.rf_sink_valid           (external_sdram_controller_s1_agent_rsp_fifo_out_valid),            //                .valid
		.rf_sink_startofpacket   (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket),    //                .startofpacket
		.rf_sink_endofpacket     (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket),      //                .endofpacket
		.rf_sink_data            (external_sdram_controller_s1_agent_rsp_fifo_out_data),             //                .data
		.rf_source_ready         (external_sdram_controller_s1_agent_rf_source_ready),               //       rf_source.ready
		.rf_source_valid         (external_sdram_controller_s1_agent_rf_source_valid),               //                .valid
		.rf_source_startofpacket (external_sdram_controller_s1_agent_rf_source_startofpacket),       //                .startofpacket
		.rf_source_endofpacket   (external_sdram_controller_s1_agent_rf_source_endofpacket),         //                .endofpacket
		.rf_source_data          (external_sdram_controller_s1_agent_rf_source_data),                //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                                    //                .error
		.rdata_fifo_src_ready    (external_sdram_controller_s1_agent_rdata_fifo_src_ready),          //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (external_sdram_controller_s1_agent_rdata_fifo_src_valid),          //                .valid
		.rdata_fifo_src_data     (external_sdram_controller_s1_agent_rdata_fifo_src_data),           //                .data
		.m0_response             (2'b00),                                                            //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                              //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (94),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) external_sdram_controller_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                               //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_data           (external_sdram_controller_s1_agent_rf_source_data),             //        in.data
		.in_valid          (external_sdram_controller_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (external_sdram_controller_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (external_sdram_controller_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (external_sdram_controller_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (external_sdram_controller_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (external_sdram_controller_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (external_sdram_controller_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated)
		.csr_read          (1'b0),                                                          // (terminated)
		.csr_write         (1'b0),                                                          // (terminated)
		.csr_readdata      (),                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated)
		.almost_full_data  (),                                                              // (terminated)
		.almost_empty_data (),                                                              // (terminated)
		.in_empty          (1'b0),                                                          // (terminated)
		.out_empty         (),                                                              // (terminated)
		.in_error          (1'b0),                                                          // (terminated)
		.out_error         (),                                                              // (terminated)
		.in_channel        (1'b0),                                                          // (terminated)
		.out_channel       ()                                                               // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (18),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) external_sdram_controller_s1_agent_rdata_fifo (
		.clk               (altpll_0_c0_clk),                                         //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),          // clk_reset.reset
		.in_data           (external_sdram_controller_s1_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (external_sdram_controller_s1_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (external_sdram_controller_s1_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (external_sdram_controller_s1_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (external_sdram_controller_s1_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (external_sdram_controller_s1_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                   // (terminated)
		.csr_read          (1'b0),                                                    // (terminated)
		.csr_write         (1'b0),                                                    // (terminated)
		.csr_readdata      (),                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated)
		.almost_full_data  (),                                                        // (terminated)
		.almost_empty_data (),                                                        // (terminated)
		.in_startofpacket  (1'b0),                                                    // (terminated)
		.in_endofpacket    (1'b0),                                                    // (terminated)
		.out_startofpacket (),                                                        // (terminated)
		.out_endofpacket   (),                                                        // (terminated)
		.in_empty          (1'b0),                                                    // (terminated)
		.out_empty         (),                                                        // (terminated)
		.in_error          (1'b0),                                                    // (terminated)
		.out_error         (),                                                        // (terminated)
		.in_channel        (1'b0),                                                    // (terminated)
		.out_channel       ()                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) onchip_memory2_1_s1_agent (
		.clk                     (altpll_0_c0_clk),                                      //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),       //       clk_reset.reset
		.m0_address              (onchip_memory2_1_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_memory2_1_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_memory2_1_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_memory2_1_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_memory2_1_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_memory2_1_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_memory2_1_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_memory2_1_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_memory2_1_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_memory2_1_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_memory2_1_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_memory2_1_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_memory2_1_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_memory2_1_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_memory2_1_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_memory2_1_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                //              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                //                .valid
		.cp_data                 (cmd_mux_001_src_data),                                 //                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                          //                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                              //                .channel
		.rf_sink_ready           (onchip_memory2_1_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_memory2_1_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_memory2_1_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_memory2_1_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_memory2_1_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_memory2_1_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_memory2_1_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_memory2_1_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                    //                .error
		.rdata_fifo_src_ready    (onchip_memory2_1_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory2_1_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_memory2_1_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_1_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                      //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (onchip_memory2_1_s1_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_memory2_1_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_memory2_1_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_memory2_1_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_memory2_1_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_memory2_1_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_memory2_1_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_memory2_1_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) abus_slave_0_avalon_nios_agent (
		.clk                     (altpll_0_c0_clk),                                           //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
		.m0_address              (abus_slave_0_avalon_nios_agent_m0_address),                 //              m0.address
		.m0_burstcount           (abus_slave_0_avalon_nios_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (abus_slave_0_avalon_nios_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (abus_slave_0_avalon_nios_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (abus_slave_0_avalon_nios_agent_m0_lock),                    //                .lock
		.m0_readdata             (abus_slave_0_avalon_nios_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (abus_slave_0_avalon_nios_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (abus_slave_0_avalon_nios_agent_m0_read),                    //                .read
		.m0_waitrequest          (abus_slave_0_avalon_nios_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (abus_slave_0_avalon_nios_agent_m0_writedata),               //                .writedata
		.m0_write                (abus_slave_0_avalon_nios_agent_m0_write),                   //                .write
		.rp_endofpacket          (abus_slave_0_avalon_nios_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (abus_slave_0_avalon_nios_agent_rp_ready),                   //                .ready
		.rp_valid                (abus_slave_0_avalon_nios_agent_rp_valid),                   //                .valid
		.rp_data                 (abus_slave_0_avalon_nios_agent_rp_data),                    //                .data
		.rp_startofpacket        (abus_slave_0_avalon_nios_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                                     //              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                                     //                .valid
		.cp_data                 (cmd_mux_002_src_data),                                      //                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                             //                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                               //                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                                   //                .channel
		.rf_sink_ready           (abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (abus_slave_0_avalon_nios_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (abus_slave_0_avalon_nios_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (abus_slave_0_avalon_nios_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (abus_slave_0_avalon_nios_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (abus_slave_0_avalon_nios_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (abus_slave_0_avalon_nios_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_002_out_0_ready),                         // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_002_out_0_valid),                         //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_002_out_0_data),                          //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_002_out_0_error),                         //                .error
		.rdata_fifo_src_ready    (abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (abus_slave_0_avalon_nios_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                     //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) abus_slave_0_avalon_nios_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                           //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
		.in_data           (abus_slave_0_avalon_nios_agent_rf_source_data),             //        in.data
		.in_valid          (abus_slave_0_avalon_nios_agent_rf_source_valid),            //          .valid
		.in_ready          (abus_slave_0_avalon_nios_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (abus_slave_0_avalon_nios_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (abus_slave_0_avalon_nios_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (abus_slave_0_avalon_nios_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) abus_demux_0_avalon_nios_agent (
		.clk                     (altpll_0_c0_clk),                                           //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),            //       clk_reset.reset
		.m0_address              (abus_demux_0_avalon_nios_agent_m0_address),                 //              m0.address
		.m0_burstcount           (abus_demux_0_avalon_nios_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (abus_demux_0_avalon_nios_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (abus_demux_0_avalon_nios_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (abus_demux_0_avalon_nios_agent_m0_lock),                    //                .lock
		.m0_readdata             (abus_demux_0_avalon_nios_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (abus_demux_0_avalon_nios_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (abus_demux_0_avalon_nios_agent_m0_read),                    //                .read
		.m0_waitrequest          (abus_demux_0_avalon_nios_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (abus_demux_0_avalon_nios_agent_m0_writedata),               //                .writedata
		.m0_write                (abus_demux_0_avalon_nios_agent_m0_write),                   //                .write
		.rp_endofpacket          (abus_demux_0_avalon_nios_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (abus_demux_0_avalon_nios_agent_rp_ready),                   //                .ready
		.rp_valid                (abus_demux_0_avalon_nios_agent_rp_valid),                   //                .valid
		.rp_data                 (abus_demux_0_avalon_nios_agent_rp_data),                    //                .data
		.rp_startofpacket        (abus_demux_0_avalon_nios_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                     //              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                     //                .valid
		.cp_data                 (cmd_mux_003_src_data),                                      //                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                             //                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                               //                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                                   //                .channel
		.rf_sink_ready           (abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (abus_demux_0_avalon_nios_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (abus_demux_0_avalon_nios_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (abus_demux_0_avalon_nios_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (abus_demux_0_avalon_nios_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (abus_demux_0_avalon_nios_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (abus_demux_0_avalon_nios_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_003_out_0_ready),                         // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_003_out_0_valid),                         //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_003_out_0_data),                          //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_003_out_0_error),                         //                .error
		.rdata_fifo_src_ready    (abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (abus_demux_0_avalon_nios_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                     //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                       //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) abus_demux_0_avalon_nios_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                           //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),            // clk_reset.reset
		.in_data           (abus_demux_0_avalon_nios_agent_rf_source_data),             //        in.data
		.in_valid          (abus_demux_0_avalon_nios_agent_rf_source_valid),            //          .valid
		.in_ready          (abus_demux_0_avalon_nios_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (abus_demux_0_avalon_nios_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (abus_demux_0_avalon_nios_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (abus_demux_0_avalon_nios_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated)
		.csr_read          (1'b0),                                                      // (terminated)
		.csr_write         (1'b0),                                                      // (terminated)
		.csr_readdata      (),                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated)
		.almost_full_data  (),                                                          // (terminated)
		.almost_empty_data (),                                                          // (terminated)
		.in_empty          (1'b0),                                                      // (terminated)
		.out_empty         (),                                                          // (terminated)
		.in_error          (1'b0),                                                      // (terminated)
		.out_error         (),                                                          // (terminated)
		.in_channel        (1'b0),                                                      // (terminated)
		.out_channel       ()                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) performance_counter_0_control_slave_agent (
		.clk                     (altpll_0_c0_clk),                                                      //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),                       //       clk_reset.reset
		.m0_address              (performance_counter_0_control_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (performance_counter_0_control_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (performance_counter_0_control_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (performance_counter_0_control_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (performance_counter_0_control_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (performance_counter_0_control_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (performance_counter_0_control_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (performance_counter_0_control_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (performance_counter_0_control_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (performance_counter_0_control_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (performance_counter_0_control_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (performance_counter_0_control_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (performance_counter_0_control_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (performance_counter_0_control_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (performance_counter_0_control_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (performance_counter_0_control_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_004_src_ready),                                                //              cp.ready
		.cp_valid                (cmd_mux_004_src_valid),                                                //                .valid
		.cp_data                 (cmd_mux_004_src_data),                                                 //                .data
		.cp_startofpacket        (cmd_mux_004_src_startofpacket),                                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_004_src_endofpacket),                                          //                .endofpacket
		.cp_channel              (cmd_mux_004_src_channel),                                              //                .channel
		.rf_sink_ready           (performance_counter_0_control_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (performance_counter_0_control_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (performance_counter_0_control_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (performance_counter_0_control_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (performance_counter_0_control_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (performance_counter_0_control_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (performance_counter_0_control_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (performance_counter_0_control_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_004_out_0_ready),                                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_004_out_0_valid),                                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_004_out_0_data),                                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_004_out_0_error),                                    //                .error
		.rdata_fifo_src_ready    (performance_counter_0_control_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (performance_counter_0_control_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (performance_counter_0_control_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) performance_counter_0_control_slave_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                                      //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),                       // clk_reset.reset
		.in_data           (performance_counter_0_control_slave_agent_rf_source_data),             //        in.data
		.in_valid          (performance_counter_0_control_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (performance_counter_0_control_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (performance_counter_0_control_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (performance_counter_0_control_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (performance_counter_0_control_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (performance_counter_0_control_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (performance_counter_0_control_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                // (terminated)
		.csr_read          (1'b0),                                                                 // (terminated)
		.csr_write         (1'b0),                                                                 // (terminated)
		.csr_readdata      (),                                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                 // (terminated)
		.almost_full_data  (),                                                                     // (terminated)
		.almost_empty_data (),                                                                     // (terminated)
		.in_empty          (1'b0),                                                                 // (terminated)
		.out_empty         (),                                                                     // (terminated)
		.in_error          (1'b0),                                                                 // (terminated)
		.out_error         (),                                                                     // (terminated)
		.in_channel        (1'b0),                                                                 // (terminated)
		.out_channel       ()                                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) onchip_flash_0_csr_agent (
		.clk                     (altpll_0_c0_clk),                                     //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),      //       clk_reset.reset
		.m0_address              (onchip_flash_0_csr_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_flash_0_csr_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_flash_0_csr_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_flash_0_csr_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_flash_0_csr_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_flash_0_csr_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_flash_0_csr_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_flash_0_csr_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_flash_0_csr_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_flash_0_csr_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_flash_0_csr_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_flash_0_csr_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_flash_0_csr_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_flash_0_csr_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_flash_0_csr_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_flash_0_csr_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_005_src_ready),                               //              cp.ready
		.cp_valid                (cmd_mux_005_src_valid),                               //                .valid
		.cp_data                 (cmd_mux_005_src_data),                                //                .data
		.cp_startofpacket        (cmd_mux_005_src_startofpacket),                       //                .startofpacket
		.cp_endofpacket          (cmd_mux_005_src_endofpacket),                         //                .endofpacket
		.cp_channel              (cmd_mux_005_src_channel),                             //                .channel
		.rf_sink_ready           (onchip_flash_0_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_flash_0_csr_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_flash_0_csr_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_flash_0_csr_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_flash_0_csr_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_flash_0_csr_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_flash_0_csr_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_flash_0_csr_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_005_out_0_ready),                   // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_005_out_0_valid),                   //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_005_out_0_data),                    //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_005_out_0_error),                   //                .error
		.rdata_fifo_src_ready    (onchip_flash_0_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_flash_0_csr_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_flash_0_csr_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                               //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                 //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_flash_0_csr_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                     //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
		.in_data           (onchip_flash_0_csr_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_flash_0_csr_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_flash_0_csr_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_flash_0_csr_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_flash_0_csr_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_flash_0_csr_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_flash_0_csr_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_flash_0_csr_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                               // (terminated)
		.csr_read          (1'b0),                                                // (terminated)
		.csr_write         (1'b0),                                                // (terminated)
		.csr_readdata      (),                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated)
		.almost_full_data  (),                                                    // (terminated)
		.almost_empty_data (),                                                    // (terminated)
		.in_empty          (1'b0),                                                // (terminated)
		.out_empty         (),                                                    // (terminated)
		.in_error          (1'b0),                                                // (terminated)
		.out_error         (),                                                    // (terminated)
		.in_channel        (1'b0),                                                // (terminated)
		.out_channel       ()                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (6),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) onchip_flash_0_data_agent (
		.clk                     (altpll_0_c0_clk),                                      //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),       //       clk_reset.reset
		.m0_address              (onchip_flash_0_data_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_flash_0_data_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_flash_0_data_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_flash_0_data_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_flash_0_data_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_flash_0_data_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_flash_0_data_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_flash_0_data_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_flash_0_data_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_flash_0_data_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_flash_0_data_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_flash_0_data_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_flash_0_data_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_flash_0_data_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_flash_0_data_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_flash_0_data_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_006_src_ready),                                //              cp.ready
		.cp_valid                (cmd_mux_006_src_valid),                                //                .valid
		.cp_data                 (cmd_mux_006_src_data),                                 //                .data
		.cp_startofpacket        (cmd_mux_006_src_startofpacket),                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_006_src_endofpacket),                          //                .endofpacket
		.cp_channel              (cmd_mux_006_src_channel),                              //                .channel
		.rf_sink_ready           (onchip_flash_0_data_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_flash_0_data_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_flash_0_data_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_flash_0_data_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_flash_0_data_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_flash_0_data_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_flash_0_data_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_006_out_0_ready),                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_006_out_0_valid),                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_006_out_0_data),                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_006_out_0_error),                    //                .error
		.rdata_fifo_src_ready    (onchip_flash_0_data_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_flash_0_data_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_flash_0_data_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_flash_0_data_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                      //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (onchip_flash_0_data_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_flash_0_data_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_flash_0_data_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_flash_0_data_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_flash_0_data_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_flash_0_data_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_flash_0_data_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_flash_0_data_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) nios2_gen2_0_debug_mem_slave_agent (
		.clk                     (altpll_0_c0_clk),                                               //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),                //       clk_reset.reset
		.m0_address              (nios2_gen2_0_debug_mem_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (nios2_gen2_0_debug_mem_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (nios2_gen2_0_debug_mem_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (nios2_gen2_0_debug_mem_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (nios2_gen2_0_debug_mem_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (nios2_gen2_0_debug_mem_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (nios2_gen2_0_debug_mem_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (nios2_gen2_0_debug_mem_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (nios2_gen2_0_debug_mem_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_007_src_ready),                                         //              cp.ready
		.cp_valid                (cmd_mux_007_src_valid),                                         //                .valid
		.cp_data                 (cmd_mux_007_src_data),                                          //                .data
		.cp_startofpacket        (cmd_mux_007_src_startofpacket),                                 //                .startofpacket
		.cp_endofpacket          (cmd_mux_007_src_endofpacket),                                   //                .endofpacket
		.cp_channel              (cmd_mux_007_src_channel),                                       //                .channel
		.rf_sink_ready           (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (nios2_gen2_0_debug_mem_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_007_out_0_ready),                             // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_007_out_0_valid),                             //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_007_out_0_data),                              //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_007_out_0_error),                             //                .error
		.rdata_fifo_src_ready    (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                         //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                           //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                               //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_data           (nios2_gen2_0_debug_mem_slave_agent_rf_source_data),             //        in.data
		.in_valid          (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated)
		.csr_read          (1'b0),                                                          // (terminated)
		.csr_write         (1'b0),                                                          // (terminated)
		.csr_readdata      (),                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated)
		.almost_full_data  (),                                                              // (terminated)
		.almost_empty_data (),                                                              // (terminated)
		.in_empty          (1'b0),                                                          // (terminated)
		.out_empty         (),                                                              // (terminated)
		.in_error          (1'b0),                                                          // (terminated)
		.out_error         (),                                                              // (terminated)
		.in_channel        (1'b0),                                                          // (terminated)
		.out_channel       ()                                                               // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) altpll_0_pll_slave_agent (
		.clk                     (clk_0_clk_clk),                                              //             clk.clk
		.reset                   (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (altpll_0_pll_slave_agent_m0_address),                        //              m0.address
		.m0_burstcount           (altpll_0_pll_slave_agent_m0_burstcount),                     //                .burstcount
		.m0_byteenable           (altpll_0_pll_slave_agent_m0_byteenable),                     //                .byteenable
		.m0_debugaccess          (altpll_0_pll_slave_agent_m0_debugaccess),                    //                .debugaccess
		.m0_lock                 (altpll_0_pll_slave_agent_m0_lock),                           //                .lock
		.m0_readdata             (altpll_0_pll_slave_agent_m0_readdata),                       //                .readdata
		.m0_readdatavalid        (altpll_0_pll_slave_agent_m0_readdatavalid),                  //                .readdatavalid
		.m0_read                 (altpll_0_pll_slave_agent_m0_read),                           //                .read
		.m0_waitrequest          (altpll_0_pll_slave_agent_m0_waitrequest),                    //                .waitrequest
		.m0_writedata            (altpll_0_pll_slave_agent_m0_writedata),                      //                .writedata
		.m0_write                (altpll_0_pll_slave_agent_m0_write),                          //                .write
		.rp_endofpacket          (altpll_0_pll_slave_agent_rp_endofpacket),                    //              rp.endofpacket
		.rp_ready                (altpll_0_pll_slave_agent_rp_ready),                          //                .ready
		.rp_valid                (altpll_0_pll_slave_agent_rp_valid),                          //                .valid
		.rp_data                 (altpll_0_pll_slave_agent_rp_data),                           //                .data
		.rp_startofpacket        (altpll_0_pll_slave_agent_rp_startofpacket),                  //                .startofpacket
		.cp_ready                (cmd_mux_008_src_ready),                                      //              cp.ready
		.cp_valid                (cmd_mux_008_src_valid),                                      //                .valid
		.cp_data                 (cmd_mux_008_src_data),                                       //                .data
		.cp_startofpacket        (cmd_mux_008_src_startofpacket),                              //                .startofpacket
		.cp_endofpacket          (cmd_mux_008_src_endofpacket),                                //                .endofpacket
		.cp_channel              (cmd_mux_008_src_channel),                                    //                .channel
		.rf_sink_ready           (altpll_0_pll_slave_agent_rsp_fifo_out_ready),                //         rf_sink.ready
		.rf_sink_valid           (altpll_0_pll_slave_agent_rsp_fifo_out_valid),                //                .valid
		.rf_sink_startofpacket   (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket),        //                .startofpacket
		.rf_sink_endofpacket     (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket),          //                .endofpacket
		.rf_sink_data            (altpll_0_pll_slave_agent_rsp_fifo_out_data),                 //                .data
		.rf_source_ready         (altpll_0_pll_slave_agent_rf_source_ready),                   //       rf_source.ready
		.rf_source_valid         (altpll_0_pll_slave_agent_rf_source_valid),                   //                .valid
		.rf_source_startofpacket (altpll_0_pll_slave_agent_rf_source_startofpacket),           //                .startofpacket
		.rf_source_endofpacket   (altpll_0_pll_slave_agent_rf_source_endofpacket),             //                .endofpacket
		.rf_source_data          (altpll_0_pll_slave_agent_rf_source_data),                    //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_008_out_0_ready),                          // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_008_out_0_valid),                          //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_008_out_0_data),                           //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_008_out_0_error),                          //                .error
		.rdata_fifo_src_ready    (altpll_0_pll_slave_agent_rdata_fifo_src_ready),              //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (altpll_0_pll_slave_agent_rdata_fifo_src_valid),              //                .valid
		.rdata_fifo_src_data     (altpll_0_pll_slave_agent_rdata_fifo_src_data),               //                .data
		.m0_response             (2'b00),                                                      //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                        //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) altpll_0_pll_slave_agent_rsp_fifo (
		.clk               (clk_0_clk_clk),                                              //       clk.clk
		.reset             (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (altpll_0_pll_slave_agent_rf_source_data),                    //        in.data
		.in_valid          (altpll_0_pll_slave_agent_rf_source_valid),                   //          .valid
		.in_ready          (altpll_0_pll_slave_agent_rf_source_ready),                   //          .ready
		.in_startofpacket  (altpll_0_pll_slave_agent_rf_source_startofpacket),           //          .startofpacket
		.in_endofpacket    (altpll_0_pll_slave_agent_rf_source_endofpacket),             //          .endofpacket
		.out_data          (altpll_0_pll_slave_agent_rsp_fifo_out_data),                 //       out.data
		.out_valid         (altpll_0_pll_slave_agent_rsp_fifo_out_valid),                //          .valid
		.out_ready         (altpll_0_pll_slave_agent_rsp_fifo_out_ready),                //          .ready
		.out_startofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket),        //          .startofpacket
		.out_endofpacket   (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket),          //          .endofpacket
		.csr_address       (2'b00),                                                      // (terminated)
		.csr_read          (1'b0),                                                       // (terminated)
		.csr_write         (1'b0),                                                       // (terminated)
		.csr_readdata      (),                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated)
		.almost_full_data  (),                                                           // (terminated)
		.almost_empty_data (),                                                           // (terminated)
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_channel        (1'b0),                                                       // (terminated)
		.out_channel       ()                                                            // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) altpll_0_pll_slave_agent_rdata_fifo (
		.clk               (clk_0_clk_clk),                                              //       clk.clk
		.reset             (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (altpll_0_pll_slave_agent_rdata_fifo_src_data),               //        in.data
		.in_valid          (altpll_0_pll_slave_agent_rdata_fifo_src_valid),              //          .valid
		.in_ready          (altpll_0_pll_slave_agent_rdata_fifo_src_ready),              //          .ready
		.out_data          (altpll_0_pll_slave_agent_rdata_fifo_out_data),               //       out.data
		.out_valid         (altpll_0_pll_slave_agent_rdata_fifo_out_valid),              //          .valid
		.out_ready         (altpll_0_pll_slave_agent_rdata_fifo_out_ready),              //          .ready
		.csr_address       (2'b00),                                                      // (terminated)
		.csr_read          (1'b0),                                                       // (terminated)
		.csr_write         (1'b0),                                                       // (terminated)
		.csr_readdata      (),                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated)
		.almost_full_data  (),                                                           // (terminated)
		.almost_empty_data (),                                                           // (terminated)
		.in_startofpacket  (1'b0),                                                       // (terminated)
		.in_endofpacket    (1'b0),                                                       // (terminated)
		.out_startofpacket (),                                                           // (terminated)
		.out_endofpacket   (),                                                           // (terminated)
		.in_empty          (1'b0),                                                       // (terminated)
		.out_empty         (),                                                           // (terminated)
		.in_error          (1'b0),                                                       // (terminated)
		.out_error         (),                                                           // (terminated)
		.in_channel        (1'b0),                                                       // (terminated)
		.out_channel       ()                                                            // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) onchip_memory2_0_s1_agent (
		.clk                     (altpll_0_c0_clk),                                      //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),       //       clk_reset.reset
		.m0_address              (onchip_memory2_0_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_memory2_0_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_memory2_0_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_memory2_0_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_memory2_0_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_memory2_0_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_memory2_0_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_memory2_0_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_memory2_0_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_memory2_0_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_memory2_0_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_memory2_0_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_memory2_0_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_memory2_0_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_memory2_0_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_memory2_0_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_009_src_ready),                                //              cp.ready
		.cp_valid                (cmd_mux_009_src_valid),                                //                .valid
		.cp_data                 (cmd_mux_009_src_data),                                 //                .data
		.cp_startofpacket        (cmd_mux_009_src_startofpacket),                        //                .startofpacket
		.cp_endofpacket          (cmd_mux_009_src_endofpacket),                          //                .endofpacket
		.cp_channel              (cmd_mux_009_src_channel),                              //                .channel
		.rf_sink_ready           (onchip_memory2_0_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_memory2_0_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_memory2_0_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_memory2_0_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_memory2_0_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_memory2_0_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_memory2_0_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_009_out_0_ready),                    // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_009_out_0_valid),                    //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_009_out_0_data),                     //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_009_out_0_error),                    //                .error
		.rdata_fifo_src_ready    (onchip_memory2_0_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory2_0_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_memory2_0_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                  //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_0_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                      //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),       // clk_reset.reset
		.in_data           (onchip_memory2_0_s1_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_memory2_0_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_memory2_0_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_memory2_0_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_memory2_0_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_memory2_0_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_memory2_0_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_memory2_0_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                // (terminated)
		.csr_read          (1'b0),                                                 // (terminated)
		.csr_write         (1'b0),                                                 // (terminated)
		.csr_readdata      (),                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated)
		.almost_full_data  (),                                                     // (terminated)
		.almost_empty_data (),                                                     // (terminated)
		.in_empty          (1'b0),                                                 // (terminated)
		.out_empty         (),                                                     // (terminated)
		.in_error          (1'b0),                                                 // (terminated)
		.out_error         (),                                                     // (terminated)
		.in_channel        (1'b0),                                                 // (terminated)
		.out_channel       ()                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) switches_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (switches_s1_agent_m0_address),                   //              m0.address
		.m0_burstcount           (switches_s1_agent_m0_burstcount),                //                .burstcount
		.m0_byteenable           (switches_s1_agent_m0_byteenable),                //                .byteenable
		.m0_debugaccess          (switches_s1_agent_m0_debugaccess),               //                .debugaccess
		.m0_lock                 (switches_s1_agent_m0_lock),                      //                .lock
		.m0_readdata             (switches_s1_agent_m0_readdata),                  //                .readdata
		.m0_readdatavalid        (switches_s1_agent_m0_readdatavalid),             //                .readdatavalid
		.m0_read                 (switches_s1_agent_m0_read),                      //                .read
		.m0_waitrequest          (switches_s1_agent_m0_waitrequest),               //                .waitrequest
		.m0_writedata            (switches_s1_agent_m0_writedata),                 //                .writedata
		.m0_write                (switches_s1_agent_m0_write),                     //                .write
		.rp_endofpacket          (switches_s1_agent_rp_endofpacket),               //              rp.endofpacket
		.rp_ready                (switches_s1_agent_rp_ready),                     //                .ready
		.rp_valid                (switches_s1_agent_rp_valid),                     //                .valid
		.rp_data                 (switches_s1_agent_rp_data),                      //                .data
		.rp_startofpacket        (switches_s1_agent_rp_startofpacket),             //                .startofpacket
		.cp_ready                (cmd_mux_010_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_010_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_010_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_010_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_010_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_010_src_channel),                        //                .channel
		.rf_sink_ready           (switches_s1_agent_rsp_fifo_out_ready),           //         rf_sink.ready
		.rf_sink_valid           (switches_s1_agent_rsp_fifo_out_valid),           //                .valid
		.rf_sink_startofpacket   (switches_s1_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
		.rf_sink_endofpacket     (switches_s1_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
		.rf_sink_data            (switches_s1_agent_rsp_fifo_out_data),            //                .data
		.rf_source_ready         (switches_s1_agent_rf_source_ready),              //       rf_source.ready
		.rf_source_valid         (switches_s1_agent_rf_source_valid),              //                .valid
		.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket),      //                .startofpacket
		.rf_source_endofpacket   (switches_s1_agent_rf_source_endofpacket),        //                .endofpacket
		.rf_source_data          (switches_s1_agent_rf_source_data),               //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_010_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_010_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_010_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_010_out_0_error),              //                .error
		.rdata_fifo_src_ready    (switches_s1_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (switches_s1_agent_rdata_fifo_src_valid),         //                .valid
		.rdata_fifo_src_data     (switches_s1_agent_rdata_fifo_src_data),          //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) switches_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (switches_s1_agent_rf_source_data),               //        in.data
		.in_valid          (switches_s1_agent_rf_source_valid),              //          .valid
		.in_ready          (switches_s1_agent_rf_source_ready),              //          .ready
		.in_startofpacket  (switches_s1_agent_rf_source_startofpacket),      //          .startofpacket
		.in_endofpacket    (switches_s1_agent_rf_source_endofpacket),        //          .endofpacket
		.out_data          (switches_s1_agent_rsp_fifo_out_data),            //       out.data
		.out_valid         (switches_s1_agent_rsp_fifo_out_valid),           //          .valid
		.out_ready         (switches_s1_agent_rsp_fifo_out_ready),           //          .ready
		.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
		.out_endofpacket   (switches_s1_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) leds_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (leds_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (leds_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (leds_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (leds_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (leds_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (leds_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (leds_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (leds_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (leds_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (leds_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (leds_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (leds_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (leds_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (leds_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (leds_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (leds_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_011_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_011_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_011_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_011_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_011_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_011_src_channel),                        //                .channel
		.rf_sink_ready           (leds_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (leds_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (leds_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (leds_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (leds_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (leds_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (leds_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (leds_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (leds_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_011_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_011_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_011_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_011_out_0_error),              //                .error
		.rdata_fifo_src_ready    (leds_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (leds_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (leds_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) leds_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (leds_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (leds_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (leds_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (leds_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (leds_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (leds_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (leds_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (leds_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (leds_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) uart_0_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (uart_0_s1_agent_m0_address),                     //              m0.address
		.m0_burstcount           (uart_0_s1_agent_m0_burstcount),                  //                .burstcount
		.m0_byteenable           (uart_0_s1_agent_m0_byteenable),                  //                .byteenable
		.m0_debugaccess          (uart_0_s1_agent_m0_debugaccess),                 //                .debugaccess
		.m0_lock                 (uart_0_s1_agent_m0_lock),                        //                .lock
		.m0_readdata             (uart_0_s1_agent_m0_readdata),                    //                .readdata
		.m0_readdatavalid        (uart_0_s1_agent_m0_readdatavalid),               //                .readdatavalid
		.m0_read                 (uart_0_s1_agent_m0_read),                        //                .read
		.m0_waitrequest          (uart_0_s1_agent_m0_waitrequest),                 //                .waitrequest
		.m0_writedata            (uart_0_s1_agent_m0_writedata),                   //                .writedata
		.m0_write                (uart_0_s1_agent_m0_write),                       //                .write
		.rp_endofpacket          (uart_0_s1_agent_rp_endofpacket),                 //              rp.endofpacket
		.rp_ready                (uart_0_s1_agent_rp_ready),                       //                .ready
		.rp_valid                (uart_0_s1_agent_rp_valid),                       //                .valid
		.rp_data                 (uart_0_s1_agent_rp_data),                        //                .data
		.rp_startofpacket        (uart_0_s1_agent_rp_startofpacket),               //                .startofpacket
		.cp_ready                (cmd_mux_012_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_012_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_012_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_012_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_012_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_012_src_channel),                        //                .channel
		.rf_sink_ready           (uart_0_s1_agent_rsp_fifo_out_ready),             //         rf_sink.ready
		.rf_sink_valid           (uart_0_s1_agent_rsp_fifo_out_valid),             //                .valid
		.rf_sink_startofpacket   (uart_0_s1_agent_rsp_fifo_out_startofpacket),     //                .startofpacket
		.rf_sink_endofpacket     (uart_0_s1_agent_rsp_fifo_out_endofpacket),       //                .endofpacket
		.rf_sink_data            (uart_0_s1_agent_rsp_fifo_out_data),              //                .data
		.rf_source_ready         (uart_0_s1_agent_rf_source_ready),                //       rf_source.ready
		.rf_source_valid         (uart_0_s1_agent_rf_source_valid),                //                .valid
		.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket),        //                .startofpacket
		.rf_source_endofpacket   (uart_0_s1_agent_rf_source_endofpacket),          //                .endofpacket
		.rf_source_data          (uart_0_s1_agent_rf_source_data),                 //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_012_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_012_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_012_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_012_out_0_error),              //                .error
		.rdata_fifo_src_ready    (uart_0_s1_agent_rdata_fifo_src_ready),           //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (uart_0_s1_agent_rdata_fifo_src_valid),           //                .valid
		.rdata_fifo_src_data     (uart_0_s1_agent_rdata_fifo_src_data),            //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uart_0_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (uart_0_s1_agent_rf_source_data),                 //        in.data
		.in_valid          (uart_0_s1_agent_rf_source_valid),                //          .valid
		.in_ready          (uart_0_s1_agent_rf_source_ready),                //          .ready
		.in_startofpacket  (uart_0_s1_agent_rf_source_startofpacket),        //          .startofpacket
		.in_endofpacket    (uart_0_s1_agent_rf_source_endofpacket),          //          .endofpacket
		.out_data          (uart_0_s1_agent_rsp_fifo_out_data),              //       out.data
		.out_valid         (uart_0_s1_agent_rsp_fifo_out_valid),             //          .valid
		.out_ready         (uart_0_s1_agent_rsp_fifo_out_ready),             //          .ready
		.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket),     //          .startofpacket
		.out_endofpacket   (uart_0_s1_agent_rsp_fifo_out_endofpacket),       //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex0_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex0_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex0_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex0_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex0_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex0_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex0_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex0_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex0_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex0_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex0_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex0_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex0_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex0_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex0_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex0_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex0_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_013_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_013_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_013_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_013_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_013_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_013_src_channel),                        //                .channel
		.rf_sink_ready           (hex0_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex0_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex0_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex0_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex0_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex0_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex0_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex0_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex0_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex0_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_013_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_013_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_013_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_013_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex0_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex0_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex0_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex0_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex0_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex0_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex0_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex0_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex0_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex0_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex0_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex0_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex0_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex0_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex1_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex1_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex1_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex1_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex1_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex1_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex1_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex1_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex1_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex1_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex1_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex1_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex1_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex1_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex1_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex1_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex1_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_014_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_014_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_014_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_014_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_014_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_014_src_channel),                        //                .channel
		.rf_sink_ready           (hex1_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex1_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex1_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex1_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex1_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex1_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex1_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex1_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex1_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex1_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_014_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_014_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_014_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_014_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex1_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex1_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex1_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex1_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex1_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex1_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex1_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex1_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex1_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex1_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex1_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex1_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex1_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex1_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex2_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex2_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex2_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex2_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex2_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex2_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex2_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex2_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex2_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex2_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex2_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex2_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex2_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex2_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex2_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex2_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex2_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_015_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_015_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_015_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_015_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_015_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_015_src_channel),                        //                .channel
		.rf_sink_ready           (hex2_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex2_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex2_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex2_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex2_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex2_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex2_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex2_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex2_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex2_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_015_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_015_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_015_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_015_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex2_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex2_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex2_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex2_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex2_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex2_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex2_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex2_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex2_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex2_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex2_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex2_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex2_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex2_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex3_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex3_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex3_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex3_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex3_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex3_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex3_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex3_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex3_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex3_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex3_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex3_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex3_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex3_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex3_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex3_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex3_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_016_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_016_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_016_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_016_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_016_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_016_src_channel),                        //                .channel
		.rf_sink_ready           (hex3_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex3_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex3_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex3_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex3_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex3_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex3_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex3_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex3_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex3_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_016_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_016_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_016_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_016_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex3_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex3_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex3_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex3_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex3_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex3_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex3_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex3_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex3_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex3_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex3_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex3_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex3_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex3_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex4_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex4_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex4_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex4_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex4_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex4_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex4_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex4_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex4_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex4_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex4_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex4_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex4_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex4_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex4_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex4_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex4_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_017_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_017_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_017_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_017_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_017_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_017_src_channel),                        //                .channel
		.rf_sink_ready           (hex4_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex4_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex4_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex4_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex4_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex4_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex4_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex4_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex4_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex4_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_017_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_017_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_017_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_017_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex4_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex4_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex4_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex4_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex4_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex4_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex4_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex4_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex4_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex4_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex4_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex4_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex4_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex4_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hex5_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hex5_s1_agent_m0_address),                       //              m0.address
		.m0_burstcount           (hex5_s1_agent_m0_burstcount),                    //                .burstcount
		.m0_byteenable           (hex5_s1_agent_m0_byteenable),                    //                .byteenable
		.m0_debugaccess          (hex5_s1_agent_m0_debugaccess),                   //                .debugaccess
		.m0_lock                 (hex5_s1_agent_m0_lock),                          //                .lock
		.m0_readdata             (hex5_s1_agent_m0_readdata),                      //                .readdata
		.m0_readdatavalid        (hex5_s1_agent_m0_readdatavalid),                 //                .readdatavalid
		.m0_read                 (hex5_s1_agent_m0_read),                          //                .read
		.m0_waitrequest          (hex5_s1_agent_m0_waitrequest),                   //                .waitrequest
		.m0_writedata            (hex5_s1_agent_m0_writedata),                     //                .writedata
		.m0_write                (hex5_s1_agent_m0_write),                         //                .write
		.rp_endofpacket          (hex5_s1_agent_rp_endofpacket),                   //              rp.endofpacket
		.rp_ready                (hex5_s1_agent_rp_ready),                         //                .ready
		.rp_valid                (hex5_s1_agent_rp_valid),                         //                .valid
		.rp_data                 (hex5_s1_agent_rp_data),                          //                .data
		.rp_startofpacket        (hex5_s1_agent_rp_startofpacket),                 //                .startofpacket
		.cp_ready                (cmd_mux_018_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_018_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_018_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_018_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_018_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_018_src_channel),                        //                .channel
		.rf_sink_ready           (hex5_s1_agent_rsp_fifo_out_ready),               //         rf_sink.ready
		.rf_sink_valid           (hex5_s1_agent_rsp_fifo_out_valid),               //                .valid
		.rf_sink_startofpacket   (hex5_s1_agent_rsp_fifo_out_startofpacket),       //                .startofpacket
		.rf_sink_endofpacket     (hex5_s1_agent_rsp_fifo_out_endofpacket),         //                .endofpacket
		.rf_sink_data            (hex5_s1_agent_rsp_fifo_out_data),                //                .data
		.rf_source_ready         (hex5_s1_agent_rf_source_ready),                  //       rf_source.ready
		.rf_source_valid         (hex5_s1_agent_rf_source_valid),                  //                .valid
		.rf_source_startofpacket (hex5_s1_agent_rf_source_startofpacket),          //                .startofpacket
		.rf_source_endofpacket   (hex5_s1_agent_rf_source_endofpacket),            //                .endofpacket
		.rf_source_data          (hex5_s1_agent_rf_source_data),                   //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_018_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_018_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_018_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_018_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hex5_s1_agent_rdata_fifo_src_ready),             //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hex5_s1_agent_rdata_fifo_src_valid),             //                .valid
		.rdata_fifo_src_data     (hex5_s1_agent_rdata_fifo_src_data),              //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hex5_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hex5_s1_agent_rf_source_data),                   //        in.data
		.in_valid          (hex5_s1_agent_rf_source_valid),                  //          .valid
		.in_ready          (hex5_s1_agent_rf_source_ready),                  //          .ready
		.in_startofpacket  (hex5_s1_agent_rf_source_startofpacket),          //          .startofpacket
		.in_endofpacket    (hex5_s1_agent_rf_source_endofpacket),            //          .endofpacket
		.out_data          (hex5_s1_agent_rsp_fifo_out_data),                //       out.data
		.out_valid         (hex5_s1_agent_rsp_fifo_out_valid),               //          .valid
		.out_ready         (hex5_s1_agent_rsp_fifo_out_ready),               //          .ready
		.out_startofpacket (hex5_s1_agent_rsp_fifo_out_startofpacket),       //          .startofpacket
		.out_endofpacket   (hex5_s1_agent_rsp_fifo_out_endofpacket),         //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) hexdot_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (hexdot_s1_agent_m0_address),                     //              m0.address
		.m0_burstcount           (hexdot_s1_agent_m0_burstcount),                  //                .burstcount
		.m0_byteenable           (hexdot_s1_agent_m0_byteenable),                  //                .byteenable
		.m0_debugaccess          (hexdot_s1_agent_m0_debugaccess),                 //                .debugaccess
		.m0_lock                 (hexdot_s1_agent_m0_lock),                        //                .lock
		.m0_readdata             (hexdot_s1_agent_m0_readdata),                    //                .readdata
		.m0_readdatavalid        (hexdot_s1_agent_m0_readdatavalid),               //                .readdatavalid
		.m0_read                 (hexdot_s1_agent_m0_read),                        //                .read
		.m0_waitrequest          (hexdot_s1_agent_m0_waitrequest),                 //                .waitrequest
		.m0_writedata            (hexdot_s1_agent_m0_writedata),                   //                .writedata
		.m0_write                (hexdot_s1_agent_m0_write),                       //                .write
		.rp_endofpacket          (hexdot_s1_agent_rp_endofpacket),                 //              rp.endofpacket
		.rp_ready                (hexdot_s1_agent_rp_ready),                       //                .ready
		.rp_valid                (hexdot_s1_agent_rp_valid),                       //                .valid
		.rp_data                 (hexdot_s1_agent_rp_data),                        //                .data
		.rp_startofpacket        (hexdot_s1_agent_rp_startofpacket),               //                .startofpacket
		.cp_ready                (cmd_mux_019_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_019_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_019_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_019_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_019_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_019_src_channel),                        //                .channel
		.rf_sink_ready           (hexdot_s1_agent_rsp_fifo_out_ready),             //         rf_sink.ready
		.rf_sink_valid           (hexdot_s1_agent_rsp_fifo_out_valid),             //                .valid
		.rf_sink_startofpacket   (hexdot_s1_agent_rsp_fifo_out_startofpacket),     //                .startofpacket
		.rf_sink_endofpacket     (hexdot_s1_agent_rsp_fifo_out_endofpacket),       //                .endofpacket
		.rf_sink_data            (hexdot_s1_agent_rsp_fifo_out_data),              //                .data
		.rf_source_ready         (hexdot_s1_agent_rf_source_ready),                //       rf_source.ready
		.rf_source_valid         (hexdot_s1_agent_rf_source_valid),                //                .valid
		.rf_source_startofpacket (hexdot_s1_agent_rf_source_startofpacket),        //                .startofpacket
		.rf_source_endofpacket   (hexdot_s1_agent_rf_source_endofpacket),          //                .endofpacket
		.rf_source_data          (hexdot_s1_agent_rf_source_data),                 //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_019_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_019_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_019_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_019_out_0_error),              //                .error
		.rdata_fifo_src_ready    (hexdot_s1_agent_rdata_fifo_src_ready),           //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hexdot_s1_agent_rdata_fifo_src_valid),           //                .valid
		.rdata_fifo_src_data     (hexdot_s1_agent_rdata_fifo_src_data),            //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hexdot_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (hexdot_s1_agent_rf_source_data),                 //        in.data
		.in_valid          (hexdot_s1_agent_rf_source_valid),                //          .valid
		.in_ready          (hexdot_s1_agent_rf_source_ready),                //          .ready
		.in_startofpacket  (hexdot_s1_agent_rf_source_startofpacket),        //          .startofpacket
		.in_endofpacket    (hexdot_s1_agent_rf_source_endofpacket),          //          .endofpacket
		.out_data          (hexdot_s1_agent_rsp_fifo_out_data),              //       out.data
		.out_valid         (hexdot_s1_agent_rsp_fifo_out_valid),             //          .valid
		.out_ready         (hexdot_s1_agent_rsp_fifo_out_ready),             //          .ready
		.out_startofpacket (hexdot_s1_agent_rsp_fifo_out_startofpacket),     //          .startofpacket
		.out_endofpacket   (hexdot_s1_agent_rsp_fifo_out_endofpacket),       //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) spi_sync_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (spi_sync_s1_agent_m0_address),                   //              m0.address
		.m0_burstcount           (spi_sync_s1_agent_m0_burstcount),                //                .burstcount
		.m0_byteenable           (spi_sync_s1_agent_m0_byteenable),                //                .byteenable
		.m0_debugaccess          (spi_sync_s1_agent_m0_debugaccess),               //                .debugaccess
		.m0_lock                 (spi_sync_s1_agent_m0_lock),                      //                .lock
		.m0_readdata             (spi_sync_s1_agent_m0_readdata),                  //                .readdata
		.m0_readdatavalid        (spi_sync_s1_agent_m0_readdatavalid),             //                .readdatavalid
		.m0_read                 (spi_sync_s1_agent_m0_read),                      //                .read
		.m0_waitrequest          (spi_sync_s1_agent_m0_waitrequest),               //                .waitrequest
		.m0_writedata            (spi_sync_s1_agent_m0_writedata),                 //                .writedata
		.m0_write                (spi_sync_s1_agent_m0_write),                     //                .write
		.rp_endofpacket          (spi_sync_s1_agent_rp_endofpacket),               //              rp.endofpacket
		.rp_ready                (spi_sync_s1_agent_rp_ready),                     //                .ready
		.rp_valid                (spi_sync_s1_agent_rp_valid),                     //                .valid
		.rp_data                 (spi_sync_s1_agent_rp_data),                      //                .data
		.rp_startofpacket        (spi_sync_s1_agent_rp_startofpacket),             //                .startofpacket
		.cp_ready                (cmd_mux_020_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_020_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_020_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_020_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_020_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_020_src_channel),                        //                .channel
		.rf_sink_ready           (spi_sync_s1_agent_rsp_fifo_out_ready),           //         rf_sink.ready
		.rf_sink_valid           (spi_sync_s1_agent_rsp_fifo_out_valid),           //                .valid
		.rf_sink_startofpacket   (spi_sync_s1_agent_rsp_fifo_out_startofpacket),   //                .startofpacket
		.rf_sink_endofpacket     (spi_sync_s1_agent_rsp_fifo_out_endofpacket),     //                .endofpacket
		.rf_sink_data            (spi_sync_s1_agent_rsp_fifo_out_data),            //                .data
		.rf_source_ready         (spi_sync_s1_agent_rf_source_ready),              //       rf_source.ready
		.rf_source_valid         (spi_sync_s1_agent_rf_source_valid),              //                .valid
		.rf_source_startofpacket (spi_sync_s1_agent_rf_source_startofpacket),      //                .startofpacket
		.rf_source_endofpacket   (spi_sync_s1_agent_rf_source_endofpacket),        //                .endofpacket
		.rf_source_data          (spi_sync_s1_agent_rf_source_data),               //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_020_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_020_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_020_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_020_out_0_error),              //                .error
		.rdata_fifo_src_ready    (spi_sync_s1_agent_rdata_fifo_src_ready),         //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (spi_sync_s1_agent_rdata_fifo_src_valid),         //                .valid
		.rdata_fifo_src_data     (spi_sync_s1_agent_rdata_fifo_src_data),          //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) spi_sync_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (spi_sync_s1_agent_rf_source_data),               //        in.data
		.in_valid          (spi_sync_s1_agent_rf_source_valid),              //          .valid
		.in_ready          (spi_sync_s1_agent_rf_source_ready),              //          .ready
		.in_startofpacket  (spi_sync_s1_agent_rf_source_startofpacket),      //          .startofpacket
		.in_endofpacket    (spi_sync_s1_agent_rf_source_endofpacket),        //          .endofpacket
		.out_data          (spi_sync_s1_agent_rsp_fifo_out_data),            //       out.data
		.out_valid         (spi_sync_s1_agent_rsp_fifo_out_valid),           //          .valid
		.out_ready         (spi_sync_s1_agent_rsp_fifo_out_ready),           //          .ready
		.out_startofpacket (spi_sync_s1_agent_rsp_fifo_out_startofpacket),   //          .startofpacket
		.out_endofpacket   (spi_sync_s1_agent_rsp_fifo_out_endofpacket),     //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) extra_leds_s1_agent (
		.clk                     (altpll_0_c0_clk),                                //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset), //       clk_reset.reset
		.m0_address              (extra_leds_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (extra_leds_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (extra_leds_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (extra_leds_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (extra_leds_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (extra_leds_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (extra_leds_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (extra_leds_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (extra_leds_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (extra_leds_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (extra_leds_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (extra_leds_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (extra_leds_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (extra_leds_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (extra_leds_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (extra_leds_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_021_src_ready),                          //              cp.ready
		.cp_valid                (cmd_mux_021_src_valid),                          //                .valid
		.cp_data                 (cmd_mux_021_src_data),                           //                .data
		.cp_startofpacket        (cmd_mux_021_src_startofpacket),                  //                .startofpacket
		.cp_endofpacket          (cmd_mux_021_src_endofpacket),                    //                .endofpacket
		.cp_channel              (cmd_mux_021_src_channel),                        //                .channel
		.rf_sink_ready           (extra_leds_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (extra_leds_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (extra_leds_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (extra_leds_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (extra_leds_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (extra_leds_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (extra_leds_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (extra_leds_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (extra_leds_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (extra_leds_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_021_out_0_ready),              // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_021_out_0_valid),              //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_021_out_0_data),               //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_021_out_0_error),              //                .error
		.rdata_fifo_src_ready    (extra_leds_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (extra_leds_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (extra_leds_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                          //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                            //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) extra_leds_s1_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (extra_leds_s1_agent_rf_source_data),             //        in.data
		.in_valid          (extra_leds_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (extra_leds_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (extra_leds_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (extra_leds_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (extra_leds_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (extra_leds_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (extra_leds_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (extra_leds_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (extra_leds_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                          // (terminated)
		.csr_read          (1'b0),                                           // (terminated)
		.csr_write         (1'b0),                                           // (terminated)
		.csr_readdata      (),                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated)
		.almost_full_data  (),                                               // (terminated)
		.almost_empty_data (),                                               // (terminated)
		.in_empty          (1'b0),                                           // (terminated)
		.out_empty         (),                                               // (terminated)
		.in_error          (1'b0),                                           // (terminated)
		.out_error         (),                                               // (terminated)
		.in_channel        (1'b0),                                           // (terminated)
		.out_channel       ()                                                // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (110),
		.PKT_ORI_BURST_SIZE_L      (108),
		.PKT_RESPONSE_STATUS_H     (107),
		.PKT_RESPONSE_STATUS_L     (106),
		.PKT_BURST_SIZE_H          (81),
		.PKT_BURST_SIZE_L          (79),
		.PKT_TRANS_LOCK            (68),
		.PKT_BEGIN_BURST           (86),
		.PKT_PROTECTION_H          (101),
		.PKT_PROTECTION_L          (99),
		.PKT_BURSTWRAP_H           (78),
		.PKT_BURSTWRAP_L           (76),
		.PKT_BYTE_CNT_H            (75),
		.PKT_BYTE_CNT_L            (70),
		.PKT_ADDR_H                (63),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (64),
		.PKT_TRANS_POSTED          (65),
		.PKT_TRANS_WRITE           (66),
		.PKT_TRANS_READ            (67),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (92),
		.PKT_SRC_ID_L              (88),
		.PKT_DEST_ID_H             (97),
		.PKT_DEST_ID_L             (93),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (111),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0)
	) spi_stm32_spi_control_port_agent (
		.clk                     (altpll_0_c0_clk),                                             //             clk.clk
		.reset                   (abus_slave_0_reset_reset_bridge_in_reset_reset),              //       clk_reset.reset
		.m0_address              (spi_stm32_spi_control_port_agent_m0_address),                 //              m0.address
		.m0_burstcount           (spi_stm32_spi_control_port_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (spi_stm32_spi_control_port_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (spi_stm32_spi_control_port_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (spi_stm32_spi_control_port_agent_m0_lock),                    //                .lock
		.m0_readdata             (spi_stm32_spi_control_port_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (spi_stm32_spi_control_port_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (spi_stm32_spi_control_port_agent_m0_read),                    //                .read
		.m0_waitrequest          (spi_stm32_spi_control_port_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (spi_stm32_spi_control_port_agent_m0_writedata),               //                .writedata
		.m0_write                (spi_stm32_spi_control_port_agent_m0_write),                   //                .write
		.rp_endofpacket          (spi_stm32_spi_control_port_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (spi_stm32_spi_control_port_agent_rp_ready),                   //                .ready
		.rp_valid                (spi_stm32_spi_control_port_agent_rp_valid),                   //                .valid
		.rp_data                 (spi_stm32_spi_control_port_agent_rp_data),                    //                .data
		.rp_startofpacket        (spi_stm32_spi_control_port_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_022_src_ready),                                       //              cp.ready
		.cp_valid                (cmd_mux_022_src_valid),                                       //                .valid
		.cp_data                 (cmd_mux_022_src_data),                                        //                .data
		.cp_startofpacket        (cmd_mux_022_src_startofpacket),                               //                .startofpacket
		.cp_endofpacket          (cmd_mux_022_src_endofpacket),                                 //                .endofpacket
		.cp_channel              (cmd_mux_022_src_channel),                                     //                .channel
		.rf_sink_ready           (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (spi_stm32_spi_control_port_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (spi_stm32_spi_control_port_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (spi_stm32_spi_control_port_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (spi_stm32_spi_control_port_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (spi_stm32_spi_control_port_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (spi_stm32_spi_control_port_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (avalon_st_adapter_022_out_0_ready),                           // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (avalon_st_adapter_022_out_0_valid),                           //                .valid
		.rdata_fifo_sink_data    (avalon_st_adapter_022_out_0_data),                            //                .data
		.rdata_fifo_sink_error   (avalon_st_adapter_022_out_0_error),                           //                .error
		.rdata_fifo_src_ready    (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (spi_stm32_spi_control_port_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                       //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                         //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (112),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) spi_stm32_spi_control_port_agent_rsp_fifo (
		.clk               (altpll_0_c0_clk),                                             //       clk.clk
		.reset             (abus_slave_0_reset_reset_bridge_in_reset_reset),              // clk_reset.reset
		.in_data           (spi_stm32_spi_control_port_agent_rf_source_data),             //        in.data
		.in_valid          (spi_stm32_spi_control_port_agent_rf_source_valid),            //          .valid
		.in_ready          (spi_stm32_spi_control_port_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (spi_stm32_spi_control_port_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (spi_stm32_spi_control_port_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (spi_stm32_spi_control_port_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                       // (terminated)
		.csr_read          (1'b0),                                                        // (terminated)
		.csr_write         (1'b0),                                                        // (terminated)
		.csr_readdata      (),                                                            // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                        // (terminated)
		.almost_full_data  (),                                                            // (terminated)
		.almost_empty_data (),                                                            // (terminated)
		.in_empty          (1'b0),                                                        // (terminated)
		.out_empty         (),                                                            // (terminated)
		.in_error          (1'b0),                                                        // (terminated)
		.out_error         (),                                                            // (terminated)
		.in_channel        (1'b0),                                                        // (terminated)
		.out_channel       ()                                                             // (terminated)
	);

	wasca_mm_interconnect_0_router router (
		.sink_ready         (abus_slave_0_avalon_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (abus_slave_0_avalon_master_agent_cp_valid),         //          .valid
		.sink_data          (abus_slave_0_avalon_master_agent_cp_data),          //          .data
		.sink_startofpacket (abus_slave_0_avalon_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (abus_slave_0_avalon_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                   //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
		.src_ready          (router_src_ready),                                  //       src.ready
		.src_valid          (router_src_valid),                                  //          .valid
		.src_data           (router_src_data),                                   //          .data
		.src_channel        (router_src_channel),                                //          .channel
		.src_startofpacket  (router_src_startofpacket),                          //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                             //          .endofpacket
	);

	wasca_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (nios2_gen2_0_data_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (nios2_gen2_0_data_master_agent_cp_valid),         //          .valid
		.sink_data          (nios2_gen2_0_data_master_agent_cp_data),          //          .data
		.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (nios2_gen2_0_data_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                 //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.src_ready          (router_001_src_ready),                            //       src.ready
		.src_valid          (router_001_src_valid),                            //          .valid
		.src_data           (router_001_src_data),                             //          .data
		.src_channel        (router_001_src_channel),                          //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                       //          .endofpacket
	);

	wasca_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (nios2_gen2_0_instruction_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (nios2_gen2_0_instruction_master_agent_cp_valid),         //          .valid
		.sink_data          (nios2_gen2_0_instruction_master_agent_cp_data),          //          .data
		.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (nios2_gen2_0_instruction_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                        //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),         // clk_reset.reset
		.src_ready          (router_002_src_ready),                                   //       src.ready
		.src_valid          (router_002_src_valid),                                   //          .valid
		.src_data           (router_002_src_data),                                    //          .data
		.src_channel        (router_002_src_channel),                                 //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                           //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                              //          .endofpacket
	);

	wasca_mm_interconnect_0_router_003 router_003 (
		.sink_ready         (external_sdram_controller_s1_agent_rp_ready),         //      sink.ready
		.sink_valid         (external_sdram_controller_s1_agent_rp_valid),         //          .valid
		.sink_data          (external_sdram_controller_s1_agent_rp_data),          //          .data
		.sink_startofpacket (external_sdram_controller_s1_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (external_sdram_controller_s1_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                     //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
		.src_ready          (router_003_src_ready),                                //       src.ready
		.src_valid          (router_003_src_valid),                                //          .valid
		.src_data           (router_003_src_data),                                 //          .data
		.src_channel        (router_003_src_channel),                              //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                           //          .endofpacket
	);

	wasca_mm_interconnect_0_router_004 router_004 (
		.sink_ready         (onchip_memory2_1_s1_agent_rp_ready),             //      sink.ready
		.sink_valid         (onchip_memory2_1_s1_agent_rp_valid),             //          .valid
		.sink_data          (onchip_memory2_1_s1_agent_rp_data),              //          .data
		.sink_startofpacket (onchip_memory2_1_s1_agent_rp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (onchip_memory2_1_s1_agent_rp_endofpacket),       //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                           //       src.ready
		.src_valid          (router_004_src_valid),                           //          .valid
		.src_data           (router_004_src_data),                            //          .data
		.src_channel        (router_004_src_channel),                         //          .channel
		.src_startofpacket  (router_004_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_005 (
		.sink_ready         (abus_slave_0_avalon_nios_agent_rp_ready),         //      sink.ready
		.sink_valid         (abus_slave_0_avalon_nios_agent_rp_valid),         //          .valid
		.sink_data          (abus_slave_0_avalon_nios_agent_rp_data),          //          .data
		.sink_startofpacket (abus_slave_0_avalon_nios_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (abus_slave_0_avalon_nios_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                 //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.src_ready          (router_005_src_ready),                            //       src.ready
		.src_valid          (router_005_src_valid),                            //          .valid
		.src_data           (router_005_src_data),                             //          .data
		.src_channel        (router_005_src_channel),                          //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                       //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_006 (
		.sink_ready         (abus_demux_0_avalon_nios_agent_rp_ready),         //      sink.ready
		.sink_valid         (abus_demux_0_avalon_nios_agent_rp_valid),         //          .valid
		.sink_data          (abus_demux_0_avalon_nios_agent_rp_data),          //          .data
		.sink_startofpacket (abus_demux_0_avalon_nios_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (abus_demux_0_avalon_nios_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                 //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),  // clk_reset.reset
		.src_ready          (router_006_src_ready),                            //       src.ready
		.src_valid          (router_006_src_valid),                            //          .valid
		.src_data           (router_006_src_data),                             //          .data
		.src_channel        (router_006_src_channel),                          //          .channel
		.src_startofpacket  (router_006_src_startofpacket),                    //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                       //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_007 (
		.sink_ready         (performance_counter_0_control_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (performance_counter_0_control_slave_agent_rp_valid),         //          .valid
		.sink_data          (performance_counter_0_control_slave_agent_rp_data),          //          .data
		.sink_startofpacket (performance_counter_0_control_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (performance_counter_0_control_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                            //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),             // clk_reset.reset
		.src_ready          (router_007_src_ready),                                       //       src.ready
		.src_valid          (router_007_src_valid),                                       //          .valid
		.src_data           (router_007_src_data),                                        //          .data
		.src_channel        (router_007_src_channel),                                     //          .channel
		.src_startofpacket  (router_007_src_startofpacket),                               //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                                  //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_008 (
		.sink_ready         (onchip_flash_0_csr_agent_rp_ready),              //      sink.ready
		.sink_valid         (onchip_flash_0_csr_agent_rp_valid),              //          .valid
		.sink_data          (onchip_flash_0_csr_agent_rp_data),               //          .data
		.sink_startofpacket (onchip_flash_0_csr_agent_rp_startofpacket),      //          .startofpacket
		.sink_endofpacket   (onchip_flash_0_csr_agent_rp_endofpacket),        //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_008_src_ready),                           //       src.ready
		.src_valid          (router_008_src_valid),                           //          .valid
		.src_data           (router_008_src_data),                            //          .data
		.src_channel        (router_008_src_channel),                         //          .channel
		.src_startofpacket  (router_008_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_009 router_009 (
		.sink_ready         (onchip_flash_0_data_agent_rp_ready),             //      sink.ready
		.sink_valid         (onchip_flash_0_data_agent_rp_valid),             //          .valid
		.sink_data          (onchip_flash_0_data_agent_rp_data),              //          .data
		.sink_startofpacket (onchip_flash_0_data_agent_rp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (onchip_flash_0_data_agent_rp_endofpacket),       //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_009_src_ready),                           //       src.ready
		.src_valid          (router_009_src_valid),                           //          .valid
		.src_data           (router_009_src_data),                            //          .data
		.src_channel        (router_009_src_channel),                         //          .channel
		.src_startofpacket  (router_009_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_009_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_009 router_010 (
		.sink_ready         (nios2_gen2_0_debug_mem_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (nios2_gen2_0_debug_mem_slave_agent_rp_valid),         //          .valid
		.sink_data          (nios2_gen2_0_debug_mem_slave_agent_rp_data),          //          .data
		.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                     //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),      // clk_reset.reset
		.src_ready          (router_010_src_ready),                                //       src.ready
		.src_valid          (router_010_src_valid),                                //          .valid
		.src_data           (router_010_src_data),                                 //          .data
		.src_channel        (router_010_src_channel),                              //          .channel
		.src_startofpacket  (router_010_src_startofpacket),                        //          .startofpacket
		.src_endofpacket    (router_010_src_endofpacket)                           //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_011 (
		.sink_ready         (altpll_0_pll_slave_agent_rp_ready),                          //      sink.ready
		.sink_valid         (altpll_0_pll_slave_agent_rp_valid),                          //          .valid
		.sink_data          (altpll_0_pll_slave_agent_rp_data),                           //          .data
		.sink_startofpacket (altpll_0_pll_slave_agent_rp_startofpacket),                  //          .startofpacket
		.sink_endofpacket   (altpll_0_pll_slave_agent_rp_endofpacket),                    //          .endofpacket
		.clk                (clk_0_clk_clk),                                              //       clk.clk
		.reset              (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_011_src_ready),                                       //       src.ready
		.src_valid          (router_011_src_valid),                                       //          .valid
		.src_data           (router_011_src_data),                                        //          .data
		.src_channel        (router_011_src_channel),                                     //          .channel
		.src_startofpacket  (router_011_src_startofpacket),                               //          .startofpacket
		.src_endofpacket    (router_011_src_endofpacket)                                  //          .endofpacket
	);

	wasca_mm_interconnect_0_router_009 router_012 (
		.sink_ready         (onchip_memory2_0_s1_agent_rp_ready),             //      sink.ready
		.sink_valid         (onchip_memory2_0_s1_agent_rp_valid),             //          .valid
		.sink_data          (onchip_memory2_0_s1_agent_rp_data),              //          .data
		.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket),     //          .startofpacket
		.sink_endofpacket   (onchip_memory2_0_s1_agent_rp_endofpacket),       //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_012_src_ready),                           //       src.ready
		.src_valid          (router_012_src_valid),                           //          .valid
		.src_data           (router_012_src_data),                            //          .data
		.src_channel        (router_012_src_channel),                         //          .channel
		.src_startofpacket  (router_012_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_012_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_013 (
		.sink_ready         (switches_s1_agent_rp_ready),                     //      sink.ready
		.sink_valid         (switches_s1_agent_rp_valid),                     //          .valid
		.sink_data          (switches_s1_agent_rp_data),                      //          .data
		.sink_startofpacket (switches_s1_agent_rp_startofpacket),             //          .startofpacket
		.sink_endofpacket   (switches_s1_agent_rp_endofpacket),               //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_013_src_ready),                           //       src.ready
		.src_valid          (router_013_src_valid),                           //          .valid
		.src_data           (router_013_src_data),                            //          .data
		.src_channel        (router_013_src_channel),                         //          .channel
		.src_startofpacket  (router_013_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_013_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_014 (
		.sink_ready         (leds_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (leds_s1_agent_rp_valid),                         //          .valid
		.sink_data          (leds_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (leds_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (leds_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_014_src_ready),                           //       src.ready
		.src_valid          (router_014_src_valid),                           //          .valid
		.src_data           (router_014_src_data),                            //          .data
		.src_channel        (router_014_src_channel),                         //          .channel
		.src_startofpacket  (router_014_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_014_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_015 (
		.sink_ready         (uart_0_s1_agent_rp_ready),                       //      sink.ready
		.sink_valid         (uart_0_s1_agent_rp_valid),                       //          .valid
		.sink_data          (uart_0_s1_agent_rp_data),                        //          .data
		.sink_startofpacket (uart_0_s1_agent_rp_startofpacket),               //          .startofpacket
		.sink_endofpacket   (uart_0_s1_agent_rp_endofpacket),                 //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_015_src_ready),                           //       src.ready
		.src_valid          (router_015_src_valid),                           //          .valid
		.src_data           (router_015_src_data),                            //          .data
		.src_channel        (router_015_src_channel),                         //          .channel
		.src_startofpacket  (router_015_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_015_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_016 (
		.sink_ready         (hex0_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex0_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex0_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex0_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex0_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_016_src_ready),                           //       src.ready
		.src_valid          (router_016_src_valid),                           //          .valid
		.src_data           (router_016_src_data),                            //          .data
		.src_channel        (router_016_src_channel),                         //          .channel
		.src_startofpacket  (router_016_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_016_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_017 (
		.sink_ready         (hex1_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex1_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex1_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex1_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex1_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_017_src_ready),                           //       src.ready
		.src_valid          (router_017_src_valid),                           //          .valid
		.src_data           (router_017_src_data),                            //          .data
		.src_channel        (router_017_src_channel),                         //          .channel
		.src_startofpacket  (router_017_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_017_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_018 (
		.sink_ready         (hex2_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex2_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex2_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex2_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex2_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_018_src_ready),                           //       src.ready
		.src_valid          (router_018_src_valid),                           //          .valid
		.src_data           (router_018_src_data),                            //          .data
		.src_channel        (router_018_src_channel),                         //          .channel
		.src_startofpacket  (router_018_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_018_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_019 (
		.sink_ready         (hex3_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex3_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex3_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex3_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex3_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_019_src_ready),                           //       src.ready
		.src_valid          (router_019_src_valid),                           //          .valid
		.src_data           (router_019_src_data),                            //          .data
		.src_channel        (router_019_src_channel),                         //          .channel
		.src_startofpacket  (router_019_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_019_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_020 (
		.sink_ready         (hex4_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex4_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex4_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex4_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex4_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_020_src_ready),                           //       src.ready
		.src_valid          (router_020_src_valid),                           //          .valid
		.src_data           (router_020_src_data),                            //          .data
		.src_channel        (router_020_src_channel),                         //          .channel
		.src_startofpacket  (router_020_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_020_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_021 (
		.sink_ready         (hex5_s1_agent_rp_ready),                         //      sink.ready
		.sink_valid         (hex5_s1_agent_rp_valid),                         //          .valid
		.sink_data          (hex5_s1_agent_rp_data),                          //          .data
		.sink_startofpacket (hex5_s1_agent_rp_startofpacket),                 //          .startofpacket
		.sink_endofpacket   (hex5_s1_agent_rp_endofpacket),                   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_021_src_ready),                           //       src.ready
		.src_valid          (router_021_src_valid),                           //          .valid
		.src_data           (router_021_src_data),                            //          .data
		.src_channel        (router_021_src_channel),                         //          .channel
		.src_startofpacket  (router_021_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_021_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_022 (
		.sink_ready         (hexdot_s1_agent_rp_ready),                       //      sink.ready
		.sink_valid         (hexdot_s1_agent_rp_valid),                       //          .valid
		.sink_data          (hexdot_s1_agent_rp_data),                        //          .data
		.sink_startofpacket (hexdot_s1_agent_rp_startofpacket),               //          .startofpacket
		.sink_endofpacket   (hexdot_s1_agent_rp_endofpacket),                 //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_022_src_ready),                           //       src.ready
		.src_valid          (router_022_src_valid),                           //          .valid
		.src_data           (router_022_src_data),                            //          .data
		.src_channel        (router_022_src_channel),                         //          .channel
		.src_startofpacket  (router_022_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_022_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_023 (
		.sink_ready         (spi_sync_s1_agent_rp_ready),                     //      sink.ready
		.sink_valid         (spi_sync_s1_agent_rp_valid),                     //          .valid
		.sink_data          (spi_sync_s1_agent_rp_data),                      //          .data
		.sink_startofpacket (spi_sync_s1_agent_rp_startofpacket),             //          .startofpacket
		.sink_endofpacket   (spi_sync_s1_agent_rp_endofpacket),               //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_023_src_ready),                           //       src.ready
		.src_valid          (router_023_src_valid),                           //          .valid
		.src_data           (router_023_src_data),                            //          .data
		.src_channel        (router_023_src_channel),                         //          .channel
		.src_startofpacket  (router_023_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_023_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_024 (
		.sink_ready         (extra_leds_s1_agent_rp_ready),                   //      sink.ready
		.sink_valid         (extra_leds_s1_agent_rp_valid),                   //          .valid
		.sink_data          (extra_leds_s1_agent_rp_data),                    //          .data
		.sink_startofpacket (extra_leds_s1_agent_rp_startofpacket),           //          .startofpacket
		.sink_endofpacket   (extra_leds_s1_agent_rp_endofpacket),             //          .endofpacket
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_024_src_ready),                           //       src.ready
		.src_valid          (router_024_src_valid),                           //          .valid
		.src_data           (router_024_src_data),                            //          .data
		.src_channel        (router_024_src_channel),                         //          .channel
		.src_startofpacket  (router_024_src_startofpacket),                   //          .startofpacket
		.src_endofpacket    (router_024_src_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_router_005 router_025 (
		.sink_ready         (spi_stm32_spi_control_port_agent_rp_ready),         //      sink.ready
		.sink_valid         (spi_stm32_spi_control_port_agent_rp_valid),         //          .valid
		.sink_data          (spi_stm32_spi_control_port_agent_rp_data),          //          .data
		.sink_startofpacket (spi_stm32_spi_control_port_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (spi_stm32_spi_control_port_agent_rp_endofpacket),   //          .endofpacket
		.clk                (altpll_0_c0_clk),                                   //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
		.src_ready          (router_025_src_ready),                              //       src.ready
		.src_valid          (router_025_src_valid),                              //          .valid
		.src_data           (router_025_src_data),                               //          .data
		.src_channel        (router_025_src_channel),                            //          .channel
		.src_startofpacket  (router_025_src_startofpacket),                      //          .startofpacket
		.src_endofpacket    (router_025_src_endofpacket)                         //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (79),
		.PKT_DEST_ID_L             (75),
		.PKT_SRC_ID_H              (74),
		.PKT_SRC_ID_L              (70),
		.PKT_BYTE_CNT_H            (57),
		.PKT_BYTE_CNT_L            (52),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_TRANS_POSTED          (47),
		.PKT_TRANS_WRITE           (48),
		.MAX_OUTSTANDING_RESPONSES (9),
		.PIPELINED                 (0),
		.ST_DATA_W                 (93),
		.ST_CHANNEL_W              (23),
		.VALID_WIDTH               (23),
		.ENFORCE_ORDER             (1),
		.PREVENT_HAZARDS           (0),
		.SUPPORTS_POSTED_WRITES    (1),
		.SUPPORTS_NONPOSTED_WRITES (0),
		.REORDER                   (0)
	) abus_slave_0_avalon_master_limiter (
		.clk                    (altpll_0_c0_clk),                                          //       clk.clk
		.reset                  (abus_slave_0_reset_reset_bridge_in_reset_reset),           // clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                         //  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                         //          .valid
		.cmd_sink_data          (router_src_data),                                          //          .data
		.cmd_sink_channel       (router_src_channel),                                       //          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                 //          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                   //          .endofpacket
		.cmd_src_ready          (abus_slave_0_avalon_master_limiter_cmd_src_ready),         //   cmd_src.ready
		.cmd_src_data           (abus_slave_0_avalon_master_limiter_cmd_src_data),          //          .data
		.cmd_src_channel        (abus_slave_0_avalon_master_limiter_cmd_src_channel),       //          .channel
		.cmd_src_startofpacket  (abus_slave_0_avalon_master_limiter_cmd_src_startofpacket), //          .startofpacket
		.cmd_src_endofpacket    (abus_slave_0_avalon_master_limiter_cmd_src_endofpacket),   //          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                        //  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                        //          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                      //          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                         //          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                //          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                  //          .endofpacket
		.rsp_src_ready          (abus_slave_0_avalon_master_limiter_rsp_src_ready),         //   rsp_src.ready
		.rsp_src_valid          (abus_slave_0_avalon_master_limiter_rsp_src_valid),         //          .valid
		.rsp_src_data           (abus_slave_0_avalon_master_limiter_rsp_src_data),          //          .data
		.rsp_src_channel        (abus_slave_0_avalon_master_limiter_rsp_src_channel),       //          .channel
		.rsp_src_startofpacket  (abus_slave_0_avalon_master_limiter_rsp_src_startofpacket), //          .startofpacket
		.rsp_src_endofpacket    (abus_slave_0_avalon_master_limiter_rsp_src_endofpacket),   //          .endofpacket
		.cmd_src_valid          (abus_slave_0_avalon_master_limiter_cmd_valid_data)         // cmd_valid.data
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (45),
		.PKT_ADDR_L                (18),
		.PKT_BEGIN_BURST           (68),
		.PKT_BYTE_CNT_H            (57),
		.PKT_BYTE_CNT_L            (52),
		.PKT_BYTEEN_H              (17),
		.PKT_BYTEEN_L              (16),
		.PKT_BURST_SIZE_H          (63),
		.PKT_BURST_SIZE_L          (61),
		.PKT_BURST_TYPE_H          (65),
		.PKT_BURST_TYPE_L          (64),
		.PKT_BURSTWRAP_H           (60),
		.PKT_BURSTWRAP_L           (58),
		.PKT_TRANS_COMPRESSED_READ (46),
		.PKT_TRANS_WRITE           (48),
		.PKT_TRANS_READ            (49),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (0),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.ST_DATA_W                 (93),
		.ST_CHANNEL_W              (23),
		.OUT_BYTE_CNT_H            (53),
		.OUT_BURSTWRAP_H           (60),
		.COMPRESSED_READ_SUPPORT   (0),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (7),
		.BURSTWRAP_CONST_VALUE     (7),
		.ADAPTER_VERSION           ("13.1")
	) external_sdram_controller_s1_burst_adapter (
		.clk                   (altpll_0_c0_clk),                                                  //       cr0.clk
		.reset                 (abus_slave_0_reset_reset_bridge_in_reset_reset),                   // cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                                //     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                                 //          .data
		.sink0_channel         (cmd_mux_src_channel),                                              //          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                                        //          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                          //          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                                //          .ready
		.source0_valid         (external_sdram_controller_s1_burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (external_sdram_controller_s1_burst_adapter_source0_data),          //          .data
		.source0_channel       (external_sdram_controller_s1_burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (external_sdram_controller_s1_burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (external_sdram_controller_s1_burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (external_sdram_controller_s1_burst_adapter_source0_ready)          //          .ready
	);

	wasca_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (altpll_0_c0_clk),                                          //        clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset),           //  clk_reset.reset
		.sink_ready         (abus_slave_0_avalon_master_limiter_cmd_src_ready),         //       sink.ready
		.sink_channel       (abus_slave_0_avalon_master_limiter_cmd_src_channel),       //           .channel
		.sink_data          (abus_slave_0_avalon_master_limiter_cmd_src_data),          //           .data
		.sink_startofpacket (abus_slave_0_avalon_master_limiter_cmd_src_startofpacket), //           .startofpacket
		.sink_endofpacket   (abus_slave_0_avalon_master_limiter_cmd_src_endofpacket),   //           .endofpacket
		.sink_valid         (abus_slave_0_avalon_master_limiter_cmd_valid_data),        // sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                     //       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                     //           .valid
		.src0_data          (cmd_demux_src0_data),                                      //           .data
		.src0_channel       (cmd_demux_src0_channel),                                   //           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                             //           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                               //           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                     //       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                     //           .valid
		.src1_data          (cmd_demux_src1_data),                                      //           .data
		.src1_channel       (cmd_demux_src1_channel),                                   //           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                             //           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                //           .endofpacket
	);

	wasca_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready          (router_001_src_ready),                           //      sink.ready
		.sink_channel        (router_001_src_channel),                         //          .channel
		.sink_data           (router_001_src_data),                            //          .data
		.sink_startofpacket  (router_001_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket    (router_001_src_endofpacket),                     //          .endofpacket
		.sink_valid          (router_001_src_valid),                           //          .valid
		.src0_ready          (cmd_demux_001_src0_ready),                       //      src0.ready
		.src0_valid          (cmd_demux_001_src0_valid),                       //          .valid
		.src0_data           (cmd_demux_001_src0_data),                        //          .data
		.src0_channel        (cmd_demux_001_src0_channel),                     //          .channel
		.src0_startofpacket  (cmd_demux_001_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket    (cmd_demux_001_src0_endofpacket),                 //          .endofpacket
		.src1_ready          (cmd_demux_001_src1_ready),                       //      src1.ready
		.src1_valid          (cmd_demux_001_src1_valid),                       //          .valid
		.src1_data           (cmd_demux_001_src1_data),                        //          .data
		.src1_channel        (cmd_demux_001_src1_channel),                     //          .channel
		.src1_startofpacket  (cmd_demux_001_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket    (cmd_demux_001_src1_endofpacket),                 //          .endofpacket
		.src2_ready          (cmd_demux_001_src2_ready),                       //      src2.ready
		.src2_valid          (cmd_demux_001_src2_valid),                       //          .valid
		.src2_data           (cmd_demux_001_src2_data),                        //          .data
		.src2_channel        (cmd_demux_001_src2_channel),                     //          .channel
		.src2_startofpacket  (cmd_demux_001_src2_startofpacket),               //          .startofpacket
		.src2_endofpacket    (cmd_demux_001_src2_endofpacket),                 //          .endofpacket
		.src3_ready          (cmd_demux_001_src3_ready),                       //      src3.ready
		.src3_valid          (cmd_demux_001_src3_valid),                       //          .valid
		.src3_data           (cmd_demux_001_src3_data),                        //          .data
		.src3_channel        (cmd_demux_001_src3_channel),                     //          .channel
		.src3_startofpacket  (cmd_demux_001_src3_startofpacket),               //          .startofpacket
		.src3_endofpacket    (cmd_demux_001_src3_endofpacket),                 //          .endofpacket
		.src4_ready          (cmd_demux_001_src4_ready),                       //      src4.ready
		.src4_valid          (cmd_demux_001_src4_valid),                       //          .valid
		.src4_data           (cmd_demux_001_src4_data),                        //          .data
		.src4_channel        (cmd_demux_001_src4_channel),                     //          .channel
		.src4_startofpacket  (cmd_demux_001_src4_startofpacket),               //          .startofpacket
		.src4_endofpacket    (cmd_demux_001_src4_endofpacket),                 //          .endofpacket
		.src5_ready          (cmd_demux_001_src5_ready),                       //      src5.ready
		.src5_valid          (cmd_demux_001_src5_valid),                       //          .valid
		.src5_data           (cmd_demux_001_src5_data),                        //          .data
		.src5_channel        (cmd_demux_001_src5_channel),                     //          .channel
		.src5_startofpacket  (cmd_demux_001_src5_startofpacket),               //          .startofpacket
		.src5_endofpacket    (cmd_demux_001_src5_endofpacket),                 //          .endofpacket
		.src6_ready          (cmd_demux_001_src6_ready),                       //      src6.ready
		.src6_valid          (cmd_demux_001_src6_valid),                       //          .valid
		.src6_data           (cmd_demux_001_src6_data),                        //          .data
		.src6_channel        (cmd_demux_001_src6_channel),                     //          .channel
		.src6_startofpacket  (cmd_demux_001_src6_startofpacket),               //          .startofpacket
		.src6_endofpacket    (cmd_demux_001_src6_endofpacket),                 //          .endofpacket
		.src7_ready          (cmd_demux_001_src7_ready),                       //      src7.ready
		.src7_valid          (cmd_demux_001_src7_valid),                       //          .valid
		.src7_data           (cmd_demux_001_src7_data),                        //          .data
		.src7_channel        (cmd_demux_001_src7_channel),                     //          .channel
		.src7_startofpacket  (cmd_demux_001_src7_startofpacket),               //          .startofpacket
		.src7_endofpacket    (cmd_demux_001_src7_endofpacket),                 //          .endofpacket
		.src8_ready          (cmd_demux_001_src8_ready),                       //      src8.ready
		.src8_valid          (cmd_demux_001_src8_valid),                       //          .valid
		.src8_data           (cmd_demux_001_src8_data),                        //          .data
		.src8_channel        (cmd_demux_001_src8_channel),                     //          .channel
		.src8_startofpacket  (cmd_demux_001_src8_startofpacket),               //          .startofpacket
		.src8_endofpacket    (cmd_demux_001_src8_endofpacket),                 //          .endofpacket
		.src9_ready          (cmd_demux_001_src9_ready),                       //      src9.ready
		.src9_valid          (cmd_demux_001_src9_valid),                       //          .valid
		.src9_data           (cmd_demux_001_src9_data),                        //          .data
		.src9_channel        (cmd_demux_001_src9_channel),                     //          .channel
		.src9_startofpacket  (cmd_demux_001_src9_startofpacket),               //          .startofpacket
		.src9_endofpacket    (cmd_demux_001_src9_endofpacket),                 //          .endofpacket
		.src10_ready         (cmd_demux_001_src10_ready),                      //     src10.ready
		.src10_valid         (cmd_demux_001_src10_valid),                      //          .valid
		.src10_data          (cmd_demux_001_src10_data),                       //          .data
		.src10_channel       (cmd_demux_001_src10_channel),                    //          .channel
		.src10_startofpacket (cmd_demux_001_src10_startofpacket),              //          .startofpacket
		.src10_endofpacket   (cmd_demux_001_src10_endofpacket),                //          .endofpacket
		.src11_ready         (cmd_demux_001_src11_ready),                      //     src11.ready
		.src11_valid         (cmd_demux_001_src11_valid),                      //          .valid
		.src11_data          (cmd_demux_001_src11_data),                       //          .data
		.src11_channel       (cmd_demux_001_src11_channel),                    //          .channel
		.src11_startofpacket (cmd_demux_001_src11_startofpacket),              //          .startofpacket
		.src11_endofpacket   (cmd_demux_001_src11_endofpacket),                //          .endofpacket
		.src12_ready         (cmd_demux_001_src12_ready),                      //     src12.ready
		.src12_valid         (cmd_demux_001_src12_valid),                      //          .valid
		.src12_data          (cmd_demux_001_src12_data),                       //          .data
		.src12_channel       (cmd_demux_001_src12_channel),                    //          .channel
		.src12_startofpacket (cmd_demux_001_src12_startofpacket),              //          .startofpacket
		.src12_endofpacket   (cmd_demux_001_src12_endofpacket),                //          .endofpacket
		.src13_ready         (cmd_demux_001_src13_ready),                      //     src13.ready
		.src13_valid         (cmd_demux_001_src13_valid),                      //          .valid
		.src13_data          (cmd_demux_001_src13_data),                       //          .data
		.src13_channel       (cmd_demux_001_src13_channel),                    //          .channel
		.src13_startofpacket (cmd_demux_001_src13_startofpacket),              //          .startofpacket
		.src13_endofpacket   (cmd_demux_001_src13_endofpacket),                //          .endofpacket
		.src14_ready         (cmd_demux_001_src14_ready),                      //     src14.ready
		.src14_valid         (cmd_demux_001_src14_valid),                      //          .valid
		.src14_data          (cmd_demux_001_src14_data),                       //          .data
		.src14_channel       (cmd_demux_001_src14_channel),                    //          .channel
		.src14_startofpacket (cmd_demux_001_src14_startofpacket),              //          .startofpacket
		.src14_endofpacket   (cmd_demux_001_src14_endofpacket),                //          .endofpacket
		.src15_ready         (cmd_demux_001_src15_ready),                      //     src15.ready
		.src15_valid         (cmd_demux_001_src15_valid),                      //          .valid
		.src15_data          (cmd_demux_001_src15_data),                       //          .data
		.src15_channel       (cmd_demux_001_src15_channel),                    //          .channel
		.src15_startofpacket (cmd_demux_001_src15_startofpacket),              //          .startofpacket
		.src15_endofpacket   (cmd_demux_001_src15_endofpacket),                //          .endofpacket
		.src16_ready         (cmd_demux_001_src16_ready),                      //     src16.ready
		.src16_valid         (cmd_demux_001_src16_valid),                      //          .valid
		.src16_data          (cmd_demux_001_src16_data),                       //          .data
		.src16_channel       (cmd_demux_001_src16_channel),                    //          .channel
		.src16_startofpacket (cmd_demux_001_src16_startofpacket),              //          .startofpacket
		.src16_endofpacket   (cmd_demux_001_src16_endofpacket),                //          .endofpacket
		.src17_ready         (cmd_demux_001_src17_ready),                      //     src17.ready
		.src17_valid         (cmd_demux_001_src17_valid),                      //          .valid
		.src17_data          (cmd_demux_001_src17_data),                       //          .data
		.src17_channel       (cmd_demux_001_src17_channel),                    //          .channel
		.src17_startofpacket (cmd_demux_001_src17_startofpacket),              //          .startofpacket
		.src17_endofpacket   (cmd_demux_001_src17_endofpacket),                //          .endofpacket
		.src18_ready         (cmd_demux_001_src18_ready),                      //     src18.ready
		.src18_valid         (cmd_demux_001_src18_valid),                      //          .valid
		.src18_data          (cmd_demux_001_src18_data),                       //          .data
		.src18_channel       (cmd_demux_001_src18_channel),                    //          .channel
		.src18_startofpacket (cmd_demux_001_src18_startofpacket),              //          .startofpacket
		.src18_endofpacket   (cmd_demux_001_src18_endofpacket),                //          .endofpacket
		.src19_ready         (cmd_demux_001_src19_ready),                      //     src19.ready
		.src19_valid         (cmd_demux_001_src19_valid),                      //          .valid
		.src19_data          (cmd_demux_001_src19_data),                       //          .data
		.src19_channel       (cmd_demux_001_src19_channel),                    //          .channel
		.src19_startofpacket (cmd_demux_001_src19_startofpacket),              //          .startofpacket
		.src19_endofpacket   (cmd_demux_001_src19_endofpacket),                //          .endofpacket
		.src20_ready         (cmd_demux_001_src20_ready),                      //     src20.ready
		.src20_valid         (cmd_demux_001_src20_valid),                      //          .valid
		.src20_data          (cmd_demux_001_src20_data),                       //          .data
		.src20_channel       (cmd_demux_001_src20_channel),                    //          .channel
		.src20_startofpacket (cmd_demux_001_src20_startofpacket),              //          .startofpacket
		.src20_endofpacket   (cmd_demux_001_src20_endofpacket),                //          .endofpacket
		.src21_ready         (cmd_demux_001_src21_ready),                      //     src21.ready
		.src21_valid         (cmd_demux_001_src21_valid),                      //          .valid
		.src21_data          (cmd_demux_001_src21_data),                       //          .data
		.src21_channel       (cmd_demux_001_src21_channel),                    //          .channel
		.src21_startofpacket (cmd_demux_001_src21_startofpacket),              //          .startofpacket
		.src21_endofpacket   (cmd_demux_001_src21_endofpacket),                //          .endofpacket
		.src22_ready         (cmd_demux_001_src22_ready),                      //     src22.ready
		.src22_valid         (cmd_demux_001_src22_valid),                      //          .valid
		.src22_data          (cmd_demux_001_src22_data),                       //          .data
		.src22_channel       (cmd_demux_001_src22_channel),                    //          .channel
		.src22_startofpacket (cmd_demux_001_src22_startofpacket),              //          .startofpacket
		.src22_endofpacket   (cmd_demux_001_src22_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                           //      sink.ready
		.sink_channel       (router_002_src_channel),                         //          .channel
		.sink_data          (router_002_src_data),                            //          .data
		.sink_startofpacket (router_002_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_002_src_valid),                           //          .valid
		.src0_ready         (cmd_demux_002_src0_ready),                       //      src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                       //          .valid
		.src0_data          (cmd_demux_002_src0_data),                        //          .data
		.src0_channel       (cmd_demux_002_src0_channel),                     //          .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),                 //          .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                       //      src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                       //          .valid
		.src1_data          (cmd_demux_002_src1_data),                        //          .data
		.src1_channel       (cmd_demux_002_src1_channel),                     //          .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket),                 //          .endofpacket
		.src2_ready         (cmd_demux_002_src2_ready),                       //      src2.ready
		.src2_valid         (cmd_demux_002_src2_valid),                       //          .valid
		.src2_data          (cmd_demux_002_src2_data),                        //          .data
		.src2_channel       (cmd_demux_002_src2_channel),                     //          .channel
		.src2_startofpacket (cmd_demux_002_src2_startofpacket),               //          .startofpacket
		.src2_endofpacket   (cmd_demux_002_src2_endofpacket),                 //          .endofpacket
		.src3_ready         (cmd_demux_002_src3_ready),                       //      src3.ready
		.src3_valid         (cmd_demux_002_src3_valid),                       //          .valid
		.src3_data          (cmd_demux_002_src3_data),                        //          .data
		.src3_channel       (cmd_demux_002_src3_channel),                     //          .channel
		.src3_startofpacket (cmd_demux_002_src3_startofpacket),               //          .startofpacket
		.src3_endofpacket   (cmd_demux_002_src3_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (altpll_0_c0_clk),                                                                              //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                                            //       src.ready
		.src_valid           (cmd_mux_src_valid),                                                                            //          .valid
		.src_data            (cmd_mux_src_data),                                                                             //          .data
		.src_channel         (cmd_mux_src_channel),                                                                          //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                                                    //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                                      //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                                                         //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                                                         //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                                                       //          .channel
		.sink0_data          (cmd_demux_src0_data),                                                                          //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                                                 //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                                                                   //          .endofpacket
		.sink1_ready         (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready),         //     sink1.ready
		.sink1_valid         (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid),         //          .valid
		.sink1_channel       (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel),       //          .channel
		.sink1_data          (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data),          //          .data
		.sink1_startofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink1_endofpacket   (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket)    //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
		.clk                 (altpll_0_c0_clk),                                                                       //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset),                                        // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                                                 //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                                                 //          .valid
		.src_data            (cmd_mux_001_src_data),                                                                  //          .data
		.src_channel         (cmd_mux_001_src_channel),                                                               //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                                         //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                                           //          .endofpacket
		.sink0_ready         (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready),         //     sink0.ready
		.sink0_valid         (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid),         //          .valid
		.sink0_channel       (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel),       //          .channel
		.sink0_data          (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data),          //          .data
		.sink0_startofpacket (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket   (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket),   //          .endofpacket
		.sink1_ready         (cmd_demux_001_src1_ready),                                                              //     sink1.ready
		.sink1_valid         (cmd_demux_001_src1_valid),                                                              //          .valid
		.sink1_channel       (cmd_demux_001_src1_channel),                                                            //          .channel
		.sink1_data          (cmd_demux_001_src1_data),                                                               //          .data
		.sink1_startofpacket (cmd_demux_001_src1_startofpacket),                                                      //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src1_endofpacket),                                                        //          .endofpacket
		.sink2_ready         (cmd_demux_002_src0_ready),                                                              //     sink2.ready
		.sink2_valid         (cmd_demux_002_src0_valid),                                                              //          .valid
		.sink2_channel       (cmd_demux_002_src0_channel),                                                            //          .channel
		.sink2_data          (cmd_demux_002_src0_data),                                                               //          .data
		.sink2_startofpacket (cmd_demux_002_src0_startofpacket),                                                      //          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src0_endofpacket)                                                         //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                          //          .valid
		.src_data            (cmd_mux_002_src_data),                           //          .data
		.src_channel         (cmd_mux_002_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src2_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src2_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src2_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src2_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src2_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src2_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                          //          .valid
		.src_data            (cmd_mux_003_src_data),                           //          .data
		.src_channel         (cmd_mux_003_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src3_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src3_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src3_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src3_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src3_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src3_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_004_src_valid),                          //          .valid
		.src_data            (cmd_mux_004_src_data),                           //          .data
		.src_channel         (cmd_mux_004_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src4_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src4_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src4_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src4_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src4_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src4_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_005 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_005_src_valid),                          //          .valid
		.src_data            (cmd_mux_005_src_data),                           //          .data
		.src_channel         (cmd_mux_005_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src5_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src5_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src5_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src5_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src5_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src5_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_006 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_006_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_006_src_valid),                          //          .valid
		.src_data            (cmd_mux_006_src_data),                           //          .data
		.src_channel         (cmd_mux_006_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_006_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_006_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src6_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src6_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src6_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src6_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src6_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src6_endofpacket),                 //          .endofpacket
		.sink1_ready         (cmd_demux_002_src1_ready),                       //     sink1.ready
		.sink1_valid         (cmd_demux_002_src1_valid),                       //          .valid
		.sink1_channel       (cmd_demux_002_src1_channel),                     //          .channel
		.sink1_data          (cmd_demux_002_src1_data),                        //          .data
		.sink1_startofpacket (cmd_demux_002_src1_startofpacket),               //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src1_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_007 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_007_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_007_src_valid),                          //          .valid
		.src_data            (cmd_mux_007_src_data),                           //          .data
		.src_channel         (cmd_mux_007_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_007_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_007_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src7_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src7_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src7_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src7_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src7_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src7_endofpacket),                 //          .endofpacket
		.sink1_ready         (cmd_demux_002_src2_ready),                       //     sink1.ready
		.sink1_valid         (cmd_demux_002_src2_valid),                       //          .valid
		.sink1_channel       (cmd_demux_002_src2_channel),                     //          .channel
		.sink1_data          (cmd_demux_002_src2_data),                        //          .data
		.sink1_startofpacket (cmd_demux_002_src2_startofpacket),               //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src2_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_008 (
		.clk                 (clk_0_clk_clk),                                              //       clk.clk
		.reset               (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_008_src_ready),                                      //       src.ready
		.src_valid           (cmd_mux_008_src_valid),                                      //          .valid
		.src_data            (cmd_mux_008_src_data),                                       //          .data
		.src_channel         (cmd_mux_008_src_channel),                                    //          .channel
		.src_startofpacket   (cmd_mux_008_src_startofpacket),                              //          .startofpacket
		.src_endofpacket     (cmd_mux_008_src_endofpacket),                                //          .endofpacket
		.sink0_ready         (crosser_out_ready),                                          //     sink0.ready
		.sink0_valid         (crosser_out_valid),                                          //          .valid
		.sink0_channel       (crosser_out_channel),                                        //          .channel
		.sink0_data          (crosser_out_data),                                           //          .data
		.sink0_startofpacket (crosser_out_startofpacket),                                  //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket)                                     //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_009 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_009_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_009_src_valid),                          //          .valid
		.src_data            (cmd_mux_009_src_data),                           //          .data
		.src_channel         (cmd_mux_009_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_009_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_009_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src9_ready),                       //     sink0.ready
		.sink0_valid         (cmd_demux_001_src9_valid),                       //          .valid
		.sink0_channel       (cmd_demux_001_src9_channel),                     //          .channel
		.sink0_data          (cmd_demux_001_src9_data),                        //          .data
		.sink0_startofpacket (cmd_demux_001_src9_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src9_endofpacket),                 //          .endofpacket
		.sink1_ready         (cmd_demux_002_src3_ready),                       //     sink1.ready
		.sink1_valid         (cmd_demux_002_src3_valid),                       //          .valid
		.sink1_channel       (cmd_demux_002_src3_channel),                     //          .channel
		.sink1_data          (cmd_demux_002_src3_data),                        //          .data
		.sink1_startofpacket (cmd_demux_002_src3_startofpacket),               //          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src3_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_010 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_010_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_010_src_valid),                          //          .valid
		.src_data            (cmd_mux_010_src_data),                           //          .data
		.src_channel         (cmd_mux_010_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_010_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_010_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src10_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src10_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src10_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src10_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src10_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src10_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_011 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_011_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_011_src_valid),                          //          .valid
		.src_data            (cmd_mux_011_src_data),                           //          .data
		.src_channel         (cmd_mux_011_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_011_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_011_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src11_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src11_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src11_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src11_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src11_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src11_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_012 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_012_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_012_src_valid),                          //          .valid
		.src_data            (cmd_mux_012_src_data),                           //          .data
		.src_channel         (cmd_mux_012_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_012_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_012_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src12_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src12_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src12_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src12_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src12_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src12_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_013 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_013_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_013_src_valid),                          //          .valid
		.src_data            (cmd_mux_013_src_data),                           //          .data
		.src_channel         (cmd_mux_013_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_013_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_013_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src13_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src13_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src13_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src13_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src13_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src13_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_014 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_014_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_014_src_valid),                          //          .valid
		.src_data            (cmd_mux_014_src_data),                           //          .data
		.src_channel         (cmd_mux_014_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_014_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_014_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src14_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src14_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src14_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src14_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src14_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src14_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_015 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_015_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_015_src_valid),                          //          .valid
		.src_data            (cmd_mux_015_src_data),                           //          .data
		.src_channel         (cmd_mux_015_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_015_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_015_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src15_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src15_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src15_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src15_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src15_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src15_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_016 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_016_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_016_src_valid),                          //          .valid
		.src_data            (cmd_mux_016_src_data),                           //          .data
		.src_channel         (cmd_mux_016_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_016_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_016_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src16_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src16_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src16_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src16_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src16_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src16_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_017 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_017_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_017_src_valid),                          //          .valid
		.src_data            (cmd_mux_017_src_data),                           //          .data
		.src_channel         (cmd_mux_017_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_017_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_017_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src17_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src17_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src17_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src17_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src17_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src17_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_018 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_018_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_018_src_valid),                          //          .valid
		.src_data            (cmd_mux_018_src_data),                           //          .data
		.src_channel         (cmd_mux_018_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_018_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_018_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src18_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src18_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src18_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src18_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src18_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src18_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_019 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_019_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_019_src_valid),                          //          .valid
		.src_data            (cmd_mux_019_src_data),                           //          .data
		.src_channel         (cmd_mux_019_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_019_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_019_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src19_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src19_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src19_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src19_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src19_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src19_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_020 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_020_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_020_src_valid),                          //          .valid
		.src_data            (cmd_mux_020_src_data),                           //          .data
		.src_channel         (cmd_mux_020_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_020_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_020_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src20_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src20_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src20_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src20_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src20_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src20_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_021 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_021_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_021_src_valid),                          //          .valid
		.src_data            (cmd_mux_021_src_data),                           //          .data
		.src_channel         (cmd_mux_021_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_021_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_021_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src21_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src21_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src21_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src21_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src21_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src21_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_022 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_022_src_ready),                          //       src.ready
		.src_valid           (cmd_mux_022_src_valid),                          //          .valid
		.src_data            (cmd_mux_022_src_data),                           //          .data
		.src_channel         (cmd_mux_022_src_channel),                        //          .channel
		.src_startofpacket   (cmd_mux_022_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (cmd_mux_022_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (cmd_demux_001_src22_ready),                      //     sink0.ready
		.sink0_valid         (cmd_demux_001_src22_valid),                      //          .valid
		.sink0_channel       (cmd_demux_001_src22_channel),                    //          .channel
		.sink0_data          (cmd_demux_001_src22_data),                       //          .data
		.sink0_startofpacket (cmd_demux_001_src22_startofpacket),              //          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src22_endofpacket)                 //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                           //      sink.ready
		.sink_channel       (router_003_src_channel),                         //          .channel
		.sink_data          (router_003_src_data),                            //          .data
		.sink_startofpacket (router_003_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_003_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_src0_ready),                           //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                           //          .valid
		.src0_data          (rsp_demux_src0_data),                            //          .data
		.src0_channel       (rsp_demux_src0_channel),                         //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                   //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                     //          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                           //      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                           //          .valid
		.src1_data          (rsp_demux_src1_data),                            //          .data
		.src1_channel       (rsp_demux_src1_channel),                         //          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                   //          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                      //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                           //      sink.ready
		.sink_channel       (router_004_src_channel),                         //          .channel
		.sink_data          (router_004_src_data),                            //          .data
		.sink_startofpacket (router_004_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_004_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_001_src0_data),                        //          .data
		.src0_channel       (rsp_demux_001_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                 //          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                       //      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                       //          .valid
		.src1_data          (rsp_demux_001_src1_data),                        //          .data
		.src1_channel       (rsp_demux_001_src1_channel),                     //          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket),                 //          .endofpacket
		.src2_ready         (rsp_demux_001_src2_ready),                       //      src2.ready
		.src2_valid         (rsp_demux_001_src2_valid),                       //          .valid
		.src2_data          (rsp_demux_001_src2_data),                        //          .data
		.src2_channel       (rsp_demux_001_src2_channel),                     //          .channel
		.src2_startofpacket (rsp_demux_001_src2_startofpacket),               //          .startofpacket
		.src2_endofpacket   (rsp_demux_001_src2_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                           //      sink.ready
		.sink_channel       (router_005_src_channel),                         //          .channel
		.sink_data          (router_005_src_data),                            //          .data
		.sink_startofpacket (router_005_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_005_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_002_src0_data),                        //          .data
		.src0_channel       (rsp_demux_002_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                           //      sink.ready
		.sink_channel       (router_006_src_channel),                         //          .channel
		.sink_data          (router_006_src_data),                            //          .data
		.sink_startofpacket (router_006_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_006_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_003_src0_data),                        //          .data
		.src0_channel       (rsp_demux_003_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_004 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                           //      sink.ready
		.sink_channel       (router_007_src_channel),                         //          .channel
		.sink_data          (router_007_src_data),                            //          .data
		.sink_startofpacket (router_007_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_007_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_004_src0_data),                        //          .data
		.src0_channel       (rsp_demux_004_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_005 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_008_src_ready),                           //      sink.ready
		.sink_channel       (router_008_src_channel),                         //          .channel
		.sink_data          (router_008_src_data),                            //          .data
		.sink_startofpacket (router_008_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_008_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_005_src0_data),                        //          .data
		.src0_channel       (rsp_demux_005_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_006 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_009_src_ready),                           //      sink.ready
		.sink_channel       (router_009_src_channel),                         //          .channel
		.sink_data          (router_009_src_data),                            //          .data
		.sink_startofpacket (router_009_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_009_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_009_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_006_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_006_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_006_src0_data),                        //          .data
		.src0_channel       (rsp_demux_006_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_006_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_006_src0_endofpacket),                 //          .endofpacket
		.src1_ready         (rsp_demux_006_src1_ready),                       //      src1.ready
		.src1_valid         (rsp_demux_006_src1_valid),                       //          .valid
		.src1_data          (rsp_demux_006_src1_data),                        //          .data
		.src1_channel       (rsp_demux_006_src1_channel),                     //          .channel
		.src1_startofpacket (rsp_demux_006_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket   (rsp_demux_006_src1_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_007 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_010_src_ready),                           //      sink.ready
		.sink_channel       (router_010_src_channel),                         //          .channel
		.sink_data          (router_010_src_data),                            //          .data
		.sink_startofpacket (router_010_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_010_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_010_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_007_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_007_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_007_src0_data),                        //          .data
		.src0_channel       (rsp_demux_007_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_007_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_007_src0_endofpacket),                 //          .endofpacket
		.src1_ready         (rsp_demux_007_src1_ready),                       //      src1.ready
		.src1_valid         (rsp_demux_007_src1_valid),                       //          .valid
		.src1_data          (rsp_demux_007_src1_data),                        //          .data
		.src1_channel       (rsp_demux_007_src1_channel),                     //          .channel
		.src1_startofpacket (rsp_demux_007_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket   (rsp_demux_007_src1_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_008 rsp_demux_008 (
		.clk                (clk_0_clk_clk),                                              //       clk.clk
		.reset              (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_011_src_ready),                                       //      sink.ready
		.sink_channel       (router_011_src_channel),                                     //          .channel
		.sink_data          (router_011_src_data),                                        //          .data
		.sink_startofpacket (router_011_src_startofpacket),                               //          .startofpacket
		.sink_endofpacket   (router_011_src_endofpacket),                                 //          .endofpacket
		.sink_valid         (router_011_src_valid),                                       //          .valid
		.src0_ready         (rsp_demux_008_src0_ready),                                   //      src0.ready
		.src0_valid         (rsp_demux_008_src0_valid),                                   //          .valid
		.src0_data          (rsp_demux_008_src0_data),                                    //          .data
		.src0_channel       (rsp_demux_008_src0_channel),                                 //          .channel
		.src0_startofpacket (rsp_demux_008_src0_startofpacket),                           //          .startofpacket
		.src0_endofpacket   (rsp_demux_008_src0_endofpacket)                              //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_009 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_012_src_ready),                           //      sink.ready
		.sink_channel       (router_012_src_channel),                         //          .channel
		.sink_data          (router_012_src_data),                            //          .data
		.sink_startofpacket (router_012_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_012_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_012_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_009_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_009_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_009_src0_data),                        //          .data
		.src0_channel       (rsp_demux_009_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_009_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_009_src0_endofpacket),                 //          .endofpacket
		.src1_ready         (rsp_demux_009_src1_ready),                       //      src1.ready
		.src1_valid         (rsp_demux_009_src1_valid),                       //          .valid
		.src1_data          (rsp_demux_009_src1_data),                        //          .data
		.src1_channel       (rsp_demux_009_src1_channel),                     //          .channel
		.src1_startofpacket (rsp_demux_009_src1_startofpacket),               //          .startofpacket
		.src1_endofpacket   (rsp_demux_009_src1_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_010 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_013_src_ready),                           //      sink.ready
		.sink_channel       (router_013_src_channel),                         //          .channel
		.sink_data          (router_013_src_data),                            //          .data
		.sink_startofpacket (router_013_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_013_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_013_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_010_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_010_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_010_src0_data),                        //          .data
		.src0_channel       (rsp_demux_010_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_010_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_010_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_011 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_014_src_ready),                           //      sink.ready
		.sink_channel       (router_014_src_channel),                         //          .channel
		.sink_data          (router_014_src_data),                            //          .data
		.sink_startofpacket (router_014_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_014_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_014_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_011_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_011_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_011_src0_data),                        //          .data
		.src0_channel       (rsp_demux_011_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_011_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_011_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_012 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_015_src_ready),                           //      sink.ready
		.sink_channel       (router_015_src_channel),                         //          .channel
		.sink_data          (router_015_src_data),                            //          .data
		.sink_startofpacket (router_015_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_015_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_015_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_012_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_012_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_012_src0_data),                        //          .data
		.src0_channel       (rsp_demux_012_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_012_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_012_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_013 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_016_src_ready),                           //      sink.ready
		.sink_channel       (router_016_src_channel),                         //          .channel
		.sink_data          (router_016_src_data),                            //          .data
		.sink_startofpacket (router_016_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_016_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_016_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_013_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_013_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_013_src0_data),                        //          .data
		.src0_channel       (rsp_demux_013_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_013_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_013_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_014 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_017_src_ready),                           //      sink.ready
		.sink_channel       (router_017_src_channel),                         //          .channel
		.sink_data          (router_017_src_data),                            //          .data
		.sink_startofpacket (router_017_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_017_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_017_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_014_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_014_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_014_src0_data),                        //          .data
		.src0_channel       (rsp_demux_014_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_014_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_014_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_015 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_018_src_ready),                           //      sink.ready
		.sink_channel       (router_018_src_channel),                         //          .channel
		.sink_data          (router_018_src_data),                            //          .data
		.sink_startofpacket (router_018_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_018_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_018_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_015_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_015_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_015_src0_data),                        //          .data
		.src0_channel       (rsp_demux_015_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_015_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_015_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_016 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_019_src_ready),                           //      sink.ready
		.sink_channel       (router_019_src_channel),                         //          .channel
		.sink_data          (router_019_src_data),                            //          .data
		.sink_startofpacket (router_019_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_019_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_019_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_016_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_016_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_016_src0_data),                        //          .data
		.src0_channel       (rsp_demux_016_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_016_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_016_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_017 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_020_src_ready),                           //      sink.ready
		.sink_channel       (router_020_src_channel),                         //          .channel
		.sink_data          (router_020_src_data),                            //          .data
		.sink_startofpacket (router_020_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_020_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_020_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_017_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_017_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_017_src0_data),                        //          .data
		.src0_channel       (rsp_demux_017_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_017_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_017_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_018 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_021_src_ready),                           //      sink.ready
		.sink_channel       (router_021_src_channel),                         //          .channel
		.sink_data          (router_021_src_data),                            //          .data
		.sink_startofpacket (router_021_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_021_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_021_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_018_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_018_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_018_src0_data),                        //          .data
		.src0_channel       (rsp_demux_018_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_018_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_018_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_019 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_022_src_ready),                           //      sink.ready
		.sink_channel       (router_022_src_channel),                         //          .channel
		.sink_data          (router_022_src_data),                            //          .data
		.sink_startofpacket (router_022_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_022_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_022_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_019_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_019_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_019_src0_data),                        //          .data
		.src0_channel       (rsp_demux_019_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_019_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_019_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_020 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_023_src_ready),                           //      sink.ready
		.sink_channel       (router_023_src_channel),                         //          .channel
		.sink_data          (router_023_src_data),                            //          .data
		.sink_startofpacket (router_023_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_023_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_023_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_020_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_020_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_020_src0_data),                        //          .data
		.src0_channel       (rsp_demux_020_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_020_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_020_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_021 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_024_src_ready),                           //      sink.ready
		.sink_channel       (router_024_src_channel),                         //          .channel
		.sink_data          (router_024_src_data),                            //          .data
		.sink_startofpacket (router_024_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_024_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_024_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_021_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_021_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_021_src0_data),                        //          .data
		.src0_channel       (rsp_demux_021_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_021_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_021_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_022 (
		.clk                (altpll_0_c0_clk),                                //       clk.clk
		.reset              (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_025_src_ready),                           //      sink.ready
		.sink_channel       (router_025_src_channel),                         //          .channel
		.sink_data          (router_025_src_data),                            //          .data
		.sink_startofpacket (router_025_src_startofpacket),                   //          .startofpacket
		.sink_endofpacket   (router_025_src_endofpacket),                     //          .endofpacket
		.sink_valid         (router_025_src_valid),                           //          .valid
		.src0_ready         (rsp_demux_022_src0_ready),                       //      src0.ready
		.src0_valid         (rsp_demux_022_src0_valid),                       //          .valid
		.src0_data          (rsp_demux_022_src0_data),                        //          .data
		.src0_channel       (rsp_demux_022_src0_channel),                     //          .channel
		.src0_startofpacket (rsp_demux_022_src0_startofpacket),               //          .startofpacket
		.src0_endofpacket   (rsp_demux_022_src0_endofpacket)                  //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (altpll_0_c0_clk),                                                                       //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset),                                        // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                                     //       src.ready
		.src_valid           (rsp_mux_src_valid),                                                                     //          .valid
		.src_data            (rsp_mux_src_data),                                                                      //          .data
		.src_channel         (rsp_mux_src_channel),                                                                   //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                                             //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                               //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                                                  //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                                                  //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                                                //          .channel
		.sink0_data          (rsp_demux_src0_data),                                                                   //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                                                          //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                                                            //          .endofpacket
		.sink1_ready         (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready),         //     sink1.ready
		.sink1_valid         (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid),         //          .valid
		.sink1_channel       (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel),       //          .channel
		.sink1_data          (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data),          //          .data
		.sink1_startofpacket (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink1_endofpacket   (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket)    //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
		.clk                  (altpll_0_c0_clk),                                                                              //       clk.clk
		.reset                (abus_slave_0_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
		.src_ready            (rsp_mux_001_src_ready),                                                                        //       src.ready
		.src_valid            (rsp_mux_001_src_valid),                                                                        //          .valid
		.src_data             (rsp_mux_001_src_data),                                                                         //          .data
		.src_channel          (rsp_mux_001_src_channel),                                                                      //          .channel
		.src_startofpacket    (rsp_mux_001_src_startofpacket),                                                                //          .startofpacket
		.src_endofpacket      (rsp_mux_001_src_endofpacket),                                                                  //          .endofpacket
		.sink0_ready          (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready),         //     sink0.ready
		.sink0_valid          (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid),         //          .valid
		.sink0_channel        (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel),       //          .channel
		.sink0_data           (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data),          //          .data
		.sink0_startofpacket  (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.sink0_endofpacket    (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket),   //          .endofpacket
		.sink1_ready          (rsp_demux_001_src1_ready),                                                                     //     sink1.ready
		.sink1_valid          (rsp_demux_001_src1_valid),                                                                     //          .valid
		.sink1_channel        (rsp_demux_001_src1_channel),                                                                   //          .channel
		.sink1_data           (rsp_demux_001_src1_data),                                                                      //          .data
		.sink1_startofpacket  (rsp_demux_001_src1_startofpacket),                                                             //          .startofpacket
		.sink1_endofpacket    (rsp_demux_001_src1_endofpacket),                                                               //          .endofpacket
		.sink2_ready          (rsp_demux_002_src0_ready),                                                                     //     sink2.ready
		.sink2_valid          (rsp_demux_002_src0_valid),                                                                     //          .valid
		.sink2_channel        (rsp_demux_002_src0_channel),                                                                   //          .channel
		.sink2_data           (rsp_demux_002_src0_data),                                                                      //          .data
		.sink2_startofpacket  (rsp_demux_002_src0_startofpacket),                                                             //          .startofpacket
		.sink2_endofpacket    (rsp_demux_002_src0_endofpacket),                                                               //          .endofpacket
		.sink3_ready          (rsp_demux_003_src0_ready),                                                                     //     sink3.ready
		.sink3_valid          (rsp_demux_003_src0_valid),                                                                     //          .valid
		.sink3_channel        (rsp_demux_003_src0_channel),                                                                   //          .channel
		.sink3_data           (rsp_demux_003_src0_data),                                                                      //          .data
		.sink3_startofpacket  (rsp_demux_003_src0_startofpacket),                                                             //          .startofpacket
		.sink3_endofpacket    (rsp_demux_003_src0_endofpacket),                                                               //          .endofpacket
		.sink4_ready          (rsp_demux_004_src0_ready),                                                                     //     sink4.ready
		.sink4_valid          (rsp_demux_004_src0_valid),                                                                     //          .valid
		.sink4_channel        (rsp_demux_004_src0_channel),                                                                   //          .channel
		.sink4_data           (rsp_demux_004_src0_data),                                                                      //          .data
		.sink4_startofpacket  (rsp_demux_004_src0_startofpacket),                                                             //          .startofpacket
		.sink4_endofpacket    (rsp_demux_004_src0_endofpacket),                                                               //          .endofpacket
		.sink5_ready          (rsp_demux_005_src0_ready),                                                                     //     sink5.ready
		.sink5_valid          (rsp_demux_005_src0_valid),                                                                     //          .valid
		.sink5_channel        (rsp_demux_005_src0_channel),                                                                   //          .channel
		.sink5_data           (rsp_demux_005_src0_data),                                                                      //          .data
		.sink5_startofpacket  (rsp_demux_005_src0_startofpacket),                                                             //          .startofpacket
		.sink5_endofpacket    (rsp_demux_005_src0_endofpacket),                                                               //          .endofpacket
		.sink6_ready          (rsp_demux_006_src0_ready),                                                                     //     sink6.ready
		.sink6_valid          (rsp_demux_006_src0_valid),                                                                     //          .valid
		.sink6_channel        (rsp_demux_006_src0_channel),                                                                   //          .channel
		.sink6_data           (rsp_demux_006_src0_data),                                                                      //          .data
		.sink6_startofpacket  (rsp_demux_006_src0_startofpacket),                                                             //          .startofpacket
		.sink6_endofpacket    (rsp_demux_006_src0_endofpacket),                                                               //          .endofpacket
		.sink7_ready          (rsp_demux_007_src0_ready),                                                                     //     sink7.ready
		.sink7_valid          (rsp_demux_007_src0_valid),                                                                     //          .valid
		.sink7_channel        (rsp_demux_007_src0_channel),                                                                   //          .channel
		.sink7_data           (rsp_demux_007_src0_data),                                                                      //          .data
		.sink7_startofpacket  (rsp_demux_007_src0_startofpacket),                                                             //          .startofpacket
		.sink7_endofpacket    (rsp_demux_007_src0_endofpacket),                                                               //          .endofpacket
		.sink8_ready          (crosser_001_out_ready),                                                                        //     sink8.ready
		.sink8_valid          (crosser_001_out_valid),                                                                        //          .valid
		.sink8_channel        (crosser_001_out_channel),                                                                      //          .channel
		.sink8_data           (crosser_001_out_data),                                                                         //          .data
		.sink8_startofpacket  (crosser_001_out_startofpacket),                                                                //          .startofpacket
		.sink8_endofpacket    (crosser_001_out_endofpacket),                                                                  //          .endofpacket
		.sink9_ready          (rsp_demux_009_src0_ready),                                                                     //     sink9.ready
		.sink9_valid          (rsp_demux_009_src0_valid),                                                                     //          .valid
		.sink9_channel        (rsp_demux_009_src0_channel),                                                                   //          .channel
		.sink9_data           (rsp_demux_009_src0_data),                                                                      //          .data
		.sink9_startofpacket  (rsp_demux_009_src0_startofpacket),                                                             //          .startofpacket
		.sink9_endofpacket    (rsp_demux_009_src0_endofpacket),                                                               //          .endofpacket
		.sink10_ready         (rsp_demux_010_src0_ready),                                                                     //    sink10.ready
		.sink10_valid         (rsp_demux_010_src0_valid),                                                                     //          .valid
		.sink10_channel       (rsp_demux_010_src0_channel),                                                                   //          .channel
		.sink10_data          (rsp_demux_010_src0_data),                                                                      //          .data
		.sink10_startofpacket (rsp_demux_010_src0_startofpacket),                                                             //          .startofpacket
		.sink10_endofpacket   (rsp_demux_010_src0_endofpacket),                                                               //          .endofpacket
		.sink11_ready         (rsp_demux_011_src0_ready),                                                                     //    sink11.ready
		.sink11_valid         (rsp_demux_011_src0_valid),                                                                     //          .valid
		.sink11_channel       (rsp_demux_011_src0_channel),                                                                   //          .channel
		.sink11_data          (rsp_demux_011_src0_data),                                                                      //          .data
		.sink11_startofpacket (rsp_demux_011_src0_startofpacket),                                                             //          .startofpacket
		.sink11_endofpacket   (rsp_demux_011_src0_endofpacket),                                                               //          .endofpacket
		.sink12_ready         (rsp_demux_012_src0_ready),                                                                     //    sink12.ready
		.sink12_valid         (rsp_demux_012_src0_valid),                                                                     //          .valid
		.sink12_channel       (rsp_demux_012_src0_channel),                                                                   //          .channel
		.sink12_data          (rsp_demux_012_src0_data),                                                                      //          .data
		.sink12_startofpacket (rsp_demux_012_src0_startofpacket),                                                             //          .startofpacket
		.sink12_endofpacket   (rsp_demux_012_src0_endofpacket),                                                               //          .endofpacket
		.sink13_ready         (rsp_demux_013_src0_ready),                                                                     //    sink13.ready
		.sink13_valid         (rsp_demux_013_src0_valid),                                                                     //          .valid
		.sink13_channel       (rsp_demux_013_src0_channel),                                                                   //          .channel
		.sink13_data          (rsp_demux_013_src0_data),                                                                      //          .data
		.sink13_startofpacket (rsp_demux_013_src0_startofpacket),                                                             //          .startofpacket
		.sink13_endofpacket   (rsp_demux_013_src0_endofpacket),                                                               //          .endofpacket
		.sink14_ready         (rsp_demux_014_src0_ready),                                                                     //    sink14.ready
		.sink14_valid         (rsp_demux_014_src0_valid),                                                                     //          .valid
		.sink14_channel       (rsp_demux_014_src0_channel),                                                                   //          .channel
		.sink14_data          (rsp_demux_014_src0_data),                                                                      //          .data
		.sink14_startofpacket (rsp_demux_014_src0_startofpacket),                                                             //          .startofpacket
		.sink14_endofpacket   (rsp_demux_014_src0_endofpacket),                                                               //          .endofpacket
		.sink15_ready         (rsp_demux_015_src0_ready),                                                                     //    sink15.ready
		.sink15_valid         (rsp_demux_015_src0_valid),                                                                     //          .valid
		.sink15_channel       (rsp_demux_015_src0_channel),                                                                   //          .channel
		.sink15_data          (rsp_demux_015_src0_data),                                                                      //          .data
		.sink15_startofpacket (rsp_demux_015_src0_startofpacket),                                                             //          .startofpacket
		.sink15_endofpacket   (rsp_demux_015_src0_endofpacket),                                                               //          .endofpacket
		.sink16_ready         (rsp_demux_016_src0_ready),                                                                     //    sink16.ready
		.sink16_valid         (rsp_demux_016_src0_valid),                                                                     //          .valid
		.sink16_channel       (rsp_demux_016_src0_channel),                                                                   //          .channel
		.sink16_data          (rsp_demux_016_src0_data),                                                                      //          .data
		.sink16_startofpacket (rsp_demux_016_src0_startofpacket),                                                             //          .startofpacket
		.sink16_endofpacket   (rsp_demux_016_src0_endofpacket),                                                               //          .endofpacket
		.sink17_ready         (rsp_demux_017_src0_ready),                                                                     //    sink17.ready
		.sink17_valid         (rsp_demux_017_src0_valid),                                                                     //          .valid
		.sink17_channel       (rsp_demux_017_src0_channel),                                                                   //          .channel
		.sink17_data          (rsp_demux_017_src0_data),                                                                      //          .data
		.sink17_startofpacket (rsp_demux_017_src0_startofpacket),                                                             //          .startofpacket
		.sink17_endofpacket   (rsp_demux_017_src0_endofpacket),                                                               //          .endofpacket
		.sink18_ready         (rsp_demux_018_src0_ready),                                                                     //    sink18.ready
		.sink18_valid         (rsp_demux_018_src0_valid),                                                                     //          .valid
		.sink18_channel       (rsp_demux_018_src0_channel),                                                                   //          .channel
		.sink18_data          (rsp_demux_018_src0_data),                                                                      //          .data
		.sink18_startofpacket (rsp_demux_018_src0_startofpacket),                                                             //          .startofpacket
		.sink18_endofpacket   (rsp_demux_018_src0_endofpacket),                                                               //          .endofpacket
		.sink19_ready         (rsp_demux_019_src0_ready),                                                                     //    sink19.ready
		.sink19_valid         (rsp_demux_019_src0_valid),                                                                     //          .valid
		.sink19_channel       (rsp_demux_019_src0_channel),                                                                   //          .channel
		.sink19_data          (rsp_demux_019_src0_data),                                                                      //          .data
		.sink19_startofpacket (rsp_demux_019_src0_startofpacket),                                                             //          .startofpacket
		.sink19_endofpacket   (rsp_demux_019_src0_endofpacket),                                                               //          .endofpacket
		.sink20_ready         (rsp_demux_020_src0_ready),                                                                     //    sink20.ready
		.sink20_valid         (rsp_demux_020_src0_valid),                                                                     //          .valid
		.sink20_channel       (rsp_demux_020_src0_channel),                                                                   //          .channel
		.sink20_data          (rsp_demux_020_src0_data),                                                                      //          .data
		.sink20_startofpacket (rsp_demux_020_src0_startofpacket),                                                             //          .startofpacket
		.sink20_endofpacket   (rsp_demux_020_src0_endofpacket),                                                               //          .endofpacket
		.sink21_ready         (rsp_demux_021_src0_ready),                                                                     //    sink21.ready
		.sink21_valid         (rsp_demux_021_src0_valid),                                                                     //          .valid
		.sink21_channel       (rsp_demux_021_src0_channel),                                                                   //          .channel
		.sink21_data          (rsp_demux_021_src0_data),                                                                      //          .data
		.sink21_startofpacket (rsp_demux_021_src0_startofpacket),                                                             //          .startofpacket
		.sink21_endofpacket   (rsp_demux_021_src0_endofpacket),                                                               //          .endofpacket
		.sink22_ready         (rsp_demux_022_src0_ready),                                                                     //    sink22.ready
		.sink22_valid         (rsp_demux_022_src0_valid),                                                                     //          .valid
		.sink22_channel       (rsp_demux_022_src0_channel),                                                                   //          .channel
		.sink22_data          (rsp_demux_022_src0_data),                                                                      //          .data
		.sink22_startofpacket (rsp_demux_022_src0_startofpacket),                                                             //          .startofpacket
		.sink22_endofpacket   (rsp_demux_022_src0_endofpacket)                                                                //          .endofpacket
	);

	wasca_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
		.clk                 (altpll_0_c0_clk),                                //       clk.clk
		.reset               (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                          //       src.ready
		.src_valid           (rsp_mux_002_src_valid),                          //          .valid
		.src_data            (rsp_mux_002_src_data),                           //          .data
		.src_channel         (rsp_mux_002_src_channel),                        //          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                  //          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                    //          .endofpacket
		.sink0_ready         (rsp_demux_001_src2_ready),                       //     sink0.ready
		.sink0_valid         (rsp_demux_001_src2_valid),                       //          .valid
		.sink0_channel       (rsp_demux_001_src2_channel),                     //          .channel
		.sink0_data          (rsp_demux_001_src2_data),                        //          .data
		.sink0_startofpacket (rsp_demux_001_src2_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src2_endofpacket),                 //          .endofpacket
		.sink1_ready         (rsp_demux_006_src1_ready),                       //     sink1.ready
		.sink1_valid         (rsp_demux_006_src1_valid),                       //          .valid
		.sink1_channel       (rsp_demux_006_src1_channel),                     //          .channel
		.sink1_data          (rsp_demux_006_src1_data),                        //          .data
		.sink1_startofpacket (rsp_demux_006_src1_startofpacket),               //          .startofpacket
		.sink1_endofpacket   (rsp_demux_006_src1_endofpacket),                 //          .endofpacket
		.sink2_ready         (rsp_demux_007_src1_ready),                       //     sink2.ready
		.sink2_valid         (rsp_demux_007_src1_valid),                       //          .valid
		.sink2_channel       (rsp_demux_007_src1_channel),                     //          .channel
		.sink2_data          (rsp_demux_007_src1_data),                        //          .data
		.sink2_startofpacket (rsp_demux_007_src1_startofpacket),               //          .startofpacket
		.sink2_endofpacket   (rsp_demux_007_src1_endofpacket),                 //          .endofpacket
		.sink3_ready         (rsp_demux_009_src1_ready),                       //     sink3.ready
		.sink3_valid         (rsp_demux_009_src1_valid),                       //          .valid
		.sink3_channel       (rsp_demux_009_src1_channel),                     //          .channel
		.sink3_data          (rsp_demux_009_src1_data),                        //          .data
		.sink3_startofpacket (rsp_demux_009_src1_startofpacket),               //          .startofpacket
		.sink3_endofpacket   (rsp_demux_009_src1_endofpacket)                  //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (45),
		.IN_PKT_ADDR_L                 (18),
		.IN_PKT_DATA_H                 (15),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (17),
		.IN_PKT_BYTEEN_L               (16),
		.IN_PKT_BYTE_CNT_H             (57),
		.IN_PKT_BYTE_CNT_L             (52),
		.IN_PKT_TRANS_COMPRESSED_READ  (46),
		.IN_PKT_TRANS_WRITE            (48),
		.IN_PKT_BURSTWRAP_H            (60),
		.IN_PKT_BURSTWRAP_L            (58),
		.IN_PKT_BURST_SIZE_H           (63),
		.IN_PKT_BURST_SIZE_L           (61),
		.IN_PKT_RESPONSE_STATUS_H      (89),
		.IN_PKT_RESPONSE_STATUS_L      (88),
		.IN_PKT_TRANS_EXCLUSIVE        (51),
		.IN_PKT_BURST_TYPE_H           (65),
		.IN_PKT_BURST_TYPE_L           (64),
		.IN_PKT_ORI_BURST_SIZE_L       (90),
		.IN_PKT_ORI_BURST_SIZE_H       (92),
		.IN_ST_DATA_W                  (93),
		.OUT_PKT_ADDR_H                (63),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (75),
		.OUT_PKT_BYTE_CNT_L            (70),
		.OUT_PKT_TRANS_COMPRESSED_READ (64),
		.OUT_PKT_BURST_SIZE_H          (81),
		.OUT_PKT_BURST_SIZE_L          (79),
		.OUT_PKT_RESPONSE_STATUS_H     (107),
		.OUT_PKT_RESPONSE_STATUS_L     (106),
		.OUT_PKT_TRANS_EXCLUSIVE       (69),
		.OUT_PKT_BURST_TYPE_H          (83),
		.OUT_PKT_BURST_TYPE_L          (82),
		.OUT_PKT_ORI_BURST_SIZE_L      (108),
		.OUT_PKT_ORI_BURST_SIZE_H      (110),
		.OUT_ST_DATA_W                 (111),
		.ST_CHANNEL_W                  (23),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter (
		.clk                  (altpll_0_c0_clk),                                                                       //       clk.clk
		.reset                (abus_slave_0_reset_reset_bridge_in_reset_reset),                                        // clk_reset.reset
		.in_valid             (cmd_demux_src1_valid),                                                                  //      sink.valid
		.in_channel           (cmd_demux_src1_channel),                                                                //          .channel
		.in_startofpacket     (cmd_demux_src1_startofpacket),                                                          //          .startofpacket
		.in_endofpacket       (cmd_demux_src1_endofpacket),                                                            //          .endofpacket
		.in_ready             (cmd_demux_src1_ready),                                                                  //          .ready
		.in_data              (cmd_demux_src1_data),                                                                   //          .data
		.out_endofpacket      (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data),          //          .data
		.out_channel          (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                                 // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (63),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (75),
		.IN_PKT_BYTE_CNT_L             (70),
		.IN_PKT_TRANS_COMPRESSED_READ  (64),
		.IN_PKT_TRANS_WRITE            (66),
		.IN_PKT_BURSTWRAP_H            (78),
		.IN_PKT_BURSTWRAP_L            (76),
		.IN_PKT_BURST_SIZE_H           (81),
		.IN_PKT_BURST_SIZE_L           (79),
		.IN_PKT_RESPONSE_STATUS_H      (107),
		.IN_PKT_RESPONSE_STATUS_L      (106),
		.IN_PKT_TRANS_EXCLUSIVE        (69),
		.IN_PKT_BURST_TYPE_H           (83),
		.IN_PKT_BURST_TYPE_L           (82),
		.IN_PKT_ORI_BURST_SIZE_L       (108),
		.IN_PKT_ORI_BURST_SIZE_H       (110),
		.IN_ST_DATA_W                  (111),
		.OUT_PKT_ADDR_H                (45),
		.OUT_PKT_ADDR_L                (18),
		.OUT_PKT_DATA_H                (15),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (17),
		.OUT_PKT_BYTEEN_L              (16),
		.OUT_PKT_BYTE_CNT_H            (57),
		.OUT_PKT_BYTE_CNT_L            (52),
		.OUT_PKT_TRANS_COMPRESSED_READ (46),
		.OUT_PKT_BURST_SIZE_H          (63),
		.OUT_PKT_BURST_SIZE_L          (61),
		.OUT_PKT_RESPONSE_STATUS_H     (89),
		.OUT_PKT_RESPONSE_STATUS_L     (88),
		.OUT_PKT_TRANS_EXCLUSIVE       (51),
		.OUT_PKT_BURST_TYPE_H          (65),
		.OUT_PKT_BURST_TYPE_L          (64),
		.OUT_PKT_ORI_BURST_SIZE_L      (90),
		.OUT_PKT_ORI_BURST_SIZE_H      (92),
		.OUT_ST_DATA_W                 (93),
		.ST_CHANNEL_W                  (23),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter (
		.clk                  (altpll_0_c0_clk),                                                                              //       clk.clk
		.reset                (abus_slave_0_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
		.in_valid             (cmd_demux_001_src0_valid),                                                                     //      sink.valid
		.in_channel           (cmd_demux_001_src0_channel),                                                                   //          .channel
		.in_startofpacket     (cmd_demux_001_src0_startofpacket),                                                             //          .startofpacket
		.in_endofpacket       (cmd_demux_001_src0_endofpacket),                                                               //          .endofpacket
		.in_ready             (cmd_demux_001_src0_ready),                                                                     //          .ready
		.in_data              (cmd_demux_001_src0_data),                                                                      //          .data
		.out_endofpacket      (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data),          //          .data
		.out_channel          (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel),       //          .channel
		.out_valid            (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid),         //          .valid
		.out_ready            (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (45),
		.IN_PKT_ADDR_L                 (18),
		.IN_PKT_DATA_H                 (15),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (17),
		.IN_PKT_BYTEEN_L               (16),
		.IN_PKT_BYTE_CNT_H             (57),
		.IN_PKT_BYTE_CNT_L             (52),
		.IN_PKT_TRANS_COMPRESSED_READ  (46),
		.IN_PKT_TRANS_WRITE            (48),
		.IN_PKT_BURSTWRAP_H            (60),
		.IN_PKT_BURSTWRAP_L            (58),
		.IN_PKT_BURST_SIZE_H           (63),
		.IN_PKT_BURST_SIZE_L           (61),
		.IN_PKT_RESPONSE_STATUS_H      (89),
		.IN_PKT_RESPONSE_STATUS_L      (88),
		.IN_PKT_TRANS_EXCLUSIVE        (51),
		.IN_PKT_BURST_TYPE_H           (65),
		.IN_PKT_BURST_TYPE_L           (64),
		.IN_PKT_ORI_BURST_SIZE_L       (90),
		.IN_PKT_ORI_BURST_SIZE_H       (92),
		.IN_ST_DATA_W                  (93),
		.OUT_PKT_ADDR_H                (63),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (75),
		.OUT_PKT_BYTE_CNT_L            (70),
		.OUT_PKT_TRANS_COMPRESSED_READ (64),
		.OUT_PKT_BURST_SIZE_H          (81),
		.OUT_PKT_BURST_SIZE_L          (79),
		.OUT_PKT_RESPONSE_STATUS_H     (107),
		.OUT_PKT_RESPONSE_STATUS_L     (106),
		.OUT_PKT_TRANS_EXCLUSIVE       (69),
		.OUT_PKT_BURST_TYPE_H          (83),
		.OUT_PKT_BURST_TYPE_L          (82),
		.OUT_PKT_ORI_BURST_SIZE_L      (108),
		.OUT_PKT_ORI_BURST_SIZE_H      (110),
		.OUT_ST_DATA_W                 (111),
		.ST_CHANNEL_W                  (23),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter (
		.clk                  (altpll_0_c0_clk),                                                                              //       clk.clk
		.reset                (abus_slave_0_reset_reset_bridge_in_reset_reset),                                               // clk_reset.reset
		.in_valid             (rsp_demux_src1_valid),                                                                         //      sink.valid
		.in_channel           (rsp_demux_src1_channel),                                                                       //          .channel
		.in_startofpacket     (rsp_demux_src1_startofpacket),                                                                 //          .startofpacket
		.in_endofpacket       (rsp_demux_src1_endofpacket),                                                                   //          .endofpacket
		.in_ready             (rsp_demux_src1_ready),                                                                         //          .ready
		.in_data              (rsp_demux_src1_data),                                                                          //          .data
		.out_endofpacket      (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data),          //          .data
		.out_channel          (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated)
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (63),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (75),
		.IN_PKT_BYTE_CNT_L             (70),
		.IN_PKT_TRANS_COMPRESSED_READ  (64),
		.IN_PKT_TRANS_WRITE            (66),
		.IN_PKT_BURSTWRAP_H            (78),
		.IN_PKT_BURSTWRAP_L            (76),
		.IN_PKT_BURST_SIZE_H           (81),
		.IN_PKT_BURST_SIZE_L           (79),
		.IN_PKT_RESPONSE_STATUS_H      (107),
		.IN_PKT_RESPONSE_STATUS_L      (106),
		.IN_PKT_TRANS_EXCLUSIVE        (69),
		.IN_PKT_BURST_TYPE_H           (83),
		.IN_PKT_BURST_TYPE_L           (82),
		.IN_PKT_ORI_BURST_SIZE_L       (108),
		.IN_PKT_ORI_BURST_SIZE_H       (110),
		.IN_ST_DATA_W                  (111),
		.OUT_PKT_ADDR_H                (45),
		.OUT_PKT_ADDR_L                (18),
		.OUT_PKT_DATA_H                (15),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (17),
		.OUT_PKT_BYTEEN_L              (16),
		.OUT_PKT_BYTE_CNT_H            (57),
		.OUT_PKT_BYTE_CNT_L            (52),
		.OUT_PKT_TRANS_COMPRESSED_READ (46),
		.OUT_PKT_BURST_SIZE_H          (63),
		.OUT_PKT_BURST_SIZE_L          (61),
		.OUT_PKT_RESPONSE_STATUS_H     (89),
		.OUT_PKT_RESPONSE_STATUS_L     (88),
		.OUT_PKT_TRANS_EXCLUSIVE       (51),
		.OUT_PKT_BURST_TYPE_H          (65),
		.OUT_PKT_BURST_TYPE_L          (64),
		.OUT_PKT_ORI_BURST_SIZE_L      (90),
		.OUT_PKT_ORI_BURST_SIZE_H      (92),
		.OUT_ST_DATA_W                 (93),
		.ST_CHANNEL_W                  (23),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (1),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0)
	) onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter (
		.clk                  (altpll_0_c0_clk),                                                                       //       clk.clk
		.reset                (abus_slave_0_reset_reset_bridge_in_reset_reset),                                        // clk_reset.reset
		.in_valid             (rsp_demux_001_src0_valid),                                                              //      sink.valid
		.in_channel           (rsp_demux_001_src0_channel),                                                            //          .channel
		.in_startofpacket     (rsp_demux_001_src0_startofpacket),                                                      //          .startofpacket
		.in_endofpacket       (rsp_demux_001_src0_endofpacket),                                                        //          .endofpacket
		.in_ready             (rsp_demux_001_src0_ready),                                                              //          .ready
		.in_data              (rsp_demux_001_src0_data),                                                               //          .data
		.out_endofpacket      (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket),   //       src.endofpacket
		.out_data             (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data),          //          .data
		.out_channel          (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel),       //          .channel
		.out_valid            (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid),         //          .valid
		.out_ready            (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready),         //          .ready
		.out_startofpacket    (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket), //          .startofpacket
		.in_command_size_data (3'b000)                                                                                 // (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (111),
		.BITS_PER_SYMBOL     (111),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (23),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (altpll_0_c0_clk),                                            //        in_clk.clk
		.in_reset          (abus_slave_0_reset_reset_bridge_in_reset_reset),             //  in_clk_reset.reset
		.out_clk           (clk_0_clk_clk),                                              //       out_clk.clk
		.out_reset         (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_001_src8_ready),                                   //            in.ready
		.in_valid          (cmd_demux_001_src8_valid),                                   //              .valid
		.in_startofpacket  (cmd_demux_001_src8_startofpacket),                           //              .startofpacket
		.in_endofpacket    (cmd_demux_001_src8_endofpacket),                             //              .endofpacket
		.in_channel        (cmd_demux_001_src8_channel),                                 //              .channel
		.in_data           (cmd_demux_001_src8_data),                                    //              .data
		.out_ready         (crosser_out_ready),                                          //           out.ready
		.out_valid         (crosser_out_valid),                                          //              .valid
		.out_startofpacket (crosser_out_startofpacket),                                  //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                    //              .endofpacket
		.out_channel       (crosser_out_channel),                                        //              .channel
		.out_data          (crosser_out_data),                                           //              .data
		.in_empty          (1'b0),                                                       //   (terminated)
		.in_error          (1'b0),                                                       //   (terminated)
		.out_empty         (),                                                           //   (terminated)
		.out_error         ()                                                            //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (111),
		.BITS_PER_SYMBOL     (111),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (23),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk_0_clk_clk),                                              //        in_clk.clk
		.in_reset          (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (altpll_0_c0_clk),                                            //       out_clk.clk
		.out_reset         (abus_slave_0_reset_reset_bridge_in_reset_reset),             // out_clk_reset.reset
		.in_ready          (rsp_demux_008_src0_ready),                                   //            in.ready
		.in_valid          (rsp_demux_008_src0_valid),                                   //              .valid
		.in_startofpacket  (rsp_demux_008_src0_startofpacket),                           //              .startofpacket
		.in_endofpacket    (rsp_demux_008_src0_endofpacket),                             //              .endofpacket
		.in_channel        (rsp_demux_008_src0_channel),                                 //              .channel
		.in_data           (rsp_demux_008_src0_data),                                    //              .data
		.out_ready         (crosser_001_out_ready),                                      //           out.ready
		.out_valid         (crosser_001_out_valid),                                      //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                              //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                                //              .endofpacket
		.out_channel       (crosser_001_out_channel),                                    //              .channel
		.out_data          (crosser_001_out_data),                                       //              .data
		.in_empty          (1'b0),                                                       //   (terminated)
		.in_error          (1'b0),                                                       //   (terminated)
		.out_empty         (),                                                           //   (terminated)
		.out_error         ()                                                            //   (terminated)
	);

	wasca_mm_interconnect_0_avalon_st_adapter #(
		.inBitsPerSymbol (18),
		.inUsePackets    (0),
		.inDataWidth     (18),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (18),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter (
		.in_clk_0_clk   (altpll_0_c0_clk),                                         // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),          // in_rst_0.reset
		.in_0_data      (external_sdram_controller_s1_agent_rdata_fifo_out_data),  //     in_0.data
		.in_0_valid     (external_sdram_controller_s1_agent_rdata_fifo_out_valid), //         .valid
		.in_0_ready     (external_sdram_controller_s1_agent_rdata_fifo_out_ready), //         .ready
		.out_0_data     (avalon_st_adapter_out_0_data),                            //    out_0.data
		.out_0_valid    (avalon_st_adapter_out_0_valid),                           //         .valid
		.out_0_ready    (avalon_st_adapter_out_0_ready),                           //         .ready
		.out_0_error    (avalon_st_adapter_out_0_error)                            //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_001 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (onchip_memory2_1_s1_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (onchip_memory2_1_s1_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (onchip_memory2_1_s1_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_001_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_001_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_001_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_001_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_002 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                     // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),      // in_rst_0.reset
		.in_0_data      (abus_slave_0_avalon_nios_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_002_out_0_data),                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_002_out_0_valid),                   //         .valid
		.out_0_ready    (avalon_st_adapter_002_out_0_ready),                   //         .ready
		.out_0_error    (avalon_st_adapter_002_out_0_error)                    //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_003 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                     // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),      // in_rst_0.reset
		.in_0_data      (abus_demux_0_avalon_nios_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_003_out_0_data),                    //    out_0.data
		.out_0_valid    (avalon_st_adapter_003_out_0_valid),                   //         .valid
		.out_0_ready    (avalon_st_adapter_003_out_0_ready),                   //         .ready
		.out_0_error    (avalon_st_adapter_003_out_0_error)                    //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_004 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),                 // in_rst_0.reset
		.in_0_data      (performance_counter_0_control_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (performance_counter_0_control_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (performance_counter_0_control_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_004_out_0_data),                               //    out_0.data
		.out_0_valid    (avalon_st_adapter_004_out_0_valid),                              //         .valid
		.out_0_ready    (avalon_st_adapter_004_out_0_ready),                              //         .ready
		.out_0_error    (avalon_st_adapter_004_out_0_error)                               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_005 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (onchip_flash_0_csr_agent_rdata_fifo_src_data),   //     in_0.data
		.in_0_valid     (onchip_flash_0_csr_agent_rdata_fifo_src_valid),  //         .valid
		.in_0_ready     (onchip_flash_0_csr_agent_rdata_fifo_src_ready),  //         .ready
		.out_0_data     (avalon_st_adapter_005_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_005_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_005_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_005_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_006 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (onchip_flash_0_data_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (onchip_flash_0_data_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (onchip_flash_0_data_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_006_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_006_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_006_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_006_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_007 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                         // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),          // in_rst_0.reset
		.in_0_data      (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_007_out_0_data),                        //    out_0.data
		.out_0_valid    (avalon_st_adapter_007_out_0_valid),                       //         .valid
		.out_0_ready    (avalon_st_adapter_007_out_0_ready),                       //         .ready
		.out_0_error    (avalon_st_adapter_007_out_0_error)                        //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_008 (
		.in_clk_0_clk   (clk_0_clk_clk),                                              // in_clk_0.clk
		.in_rst_0_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (altpll_0_pll_slave_agent_rdata_fifo_out_data),               //     in_0.data
		.in_0_valid     (altpll_0_pll_slave_agent_rdata_fifo_out_valid),              //         .valid
		.in_0_ready     (altpll_0_pll_slave_agent_rdata_fifo_out_ready),              //         .ready
		.out_0_data     (avalon_st_adapter_008_out_0_data),                           //    out_0.data
		.out_0_valid    (avalon_st_adapter_008_out_0_valid),                          //         .valid
		.out_0_ready    (avalon_st_adapter_008_out_0_ready),                          //         .ready
		.out_0_error    (avalon_st_adapter_008_out_0_error)                           //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_009 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (onchip_memory2_0_s1_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_009_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_009_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_009_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_009_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_010 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (switches_s1_agent_rdata_fifo_src_data),          //     in_0.data
		.in_0_valid     (switches_s1_agent_rdata_fifo_src_valid),         //         .valid
		.in_0_ready     (switches_s1_agent_rdata_fifo_src_ready),         //         .ready
		.out_0_data     (avalon_st_adapter_010_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_010_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_010_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_010_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_011 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (leds_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (leds_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (leds_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_011_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_011_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_011_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_011_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_012 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (uart_0_s1_agent_rdata_fifo_src_data),            //     in_0.data
		.in_0_valid     (uart_0_s1_agent_rdata_fifo_src_valid),           //         .valid
		.in_0_ready     (uart_0_s1_agent_rdata_fifo_src_ready),           //         .ready
		.out_0_data     (avalon_st_adapter_012_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_012_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_012_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_012_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_013 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex0_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex0_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex0_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_013_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_013_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_013_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_013_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_014 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex1_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex1_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex1_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_014_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_014_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_014_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_014_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_015 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex2_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex2_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex2_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_015_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_015_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_015_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_015_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_016 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex3_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex3_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex3_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_016_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_016_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_016_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_016_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_017 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex4_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex4_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex4_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_017_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_017_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_017_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_017_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_018 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hex5_s1_agent_rdata_fifo_src_data),              //     in_0.data
		.in_0_valid     (hex5_s1_agent_rdata_fifo_src_valid),             //         .valid
		.in_0_ready     (hex5_s1_agent_rdata_fifo_src_ready),             //         .ready
		.out_0_data     (avalon_st_adapter_018_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_018_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_018_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_018_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_019 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (hexdot_s1_agent_rdata_fifo_src_data),            //     in_0.data
		.in_0_valid     (hexdot_s1_agent_rdata_fifo_src_valid),           //         .valid
		.in_0_ready     (hexdot_s1_agent_rdata_fifo_src_ready),           //         .ready
		.out_0_data     (avalon_st_adapter_019_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_019_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_019_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_019_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_020 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (spi_sync_s1_agent_rdata_fifo_src_data),          //     in_0.data
		.in_0_valid     (spi_sync_s1_agent_rdata_fifo_src_valid),         //         .valid
		.in_0_ready     (spi_sync_s1_agent_rdata_fifo_src_ready),         //         .ready
		.out_0_data     (avalon_st_adapter_020_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_020_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_020_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_020_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_021 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
		.in_0_data      (extra_leds_s1_agent_rdata_fifo_src_data),        //     in_0.data
		.in_0_valid     (extra_leds_s1_agent_rdata_fifo_src_valid),       //         .valid
		.in_0_ready     (extra_leds_s1_agent_rdata_fifo_src_ready),       //         .ready
		.out_0_data     (avalon_st_adapter_021_out_0_data),               //    out_0.data
		.out_0_valid    (avalon_st_adapter_021_out_0_valid),              //         .valid
		.out_0_ready    (avalon_st_adapter_021_out_0_ready),              //         .ready
		.out_0_error    (avalon_st_adapter_021_out_0_error)               //         .error
	);

	wasca_mm_interconnect_0_avalon_st_adapter_001 #(
		.inBitsPerSymbol (34),
		.inUsePackets    (0),
		.inDataWidth     (34),
		.inChannelWidth  (0),
		.inErrorWidth    (0),
		.inUseEmptyPort  (0),
		.inUseValid      (1),
		.inUseReady      (1),
		.inReadyLatency  (0),
		.outDataWidth    (34),
		.outChannelWidth (0),
		.outErrorWidth   (1),
		.outUseEmptyPort (0),
		.outUseValid     (1),
		.outUseReady     (1),
		.outReadyLatency (0)
	) avalon_st_adapter_022 (
		.in_clk_0_clk   (altpll_0_c0_clk),                                       // in_clk_0.clk
		.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset),        // in_rst_0.reset
		.in_0_data      (spi_stm32_spi_control_port_agent_rdata_fifo_src_data),  //     in_0.data
		.in_0_valid     (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid), //         .valid
		.in_0_ready     (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready), //         .ready
		.out_0_data     (avalon_st_adapter_022_out_0_data),                      //    out_0.data
		.out_0_valid    (avalon_st_adapter_022_out_0_valid),                     //         .valid
		.out_0_ready    (avalon_st_adapter_022_out_0_ready),                     //         .ready
		.out_0_error    (avalon_st_adapter_022_out_0_error)                      //         .error
	);

endmodule
