// finalproject_mm_interconnect_0.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 14.1 186 at 2015.04.23.00:32:39

`timescale 1 ps / 1 ps
module finalproject_mm_interconnect_0 (
		input  wire        clk_clk_clk,                             //                           clk_clk.clk
		input  wire        clocks_c0_clk,                           //                         clocks_c0.clk
		input  wire        cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
		input  wire        sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
		input  wire [28:0] cpu_data_master_address,                 //                   cpu_data_master.address
		output wire        cpu_data_master_waitrequest,             //                                  .waitrequest
		input  wire [3:0]  cpu_data_master_byteenable,              //                                  .byteenable
		input  wire        cpu_data_master_read,                    //                                  .read
		output wire [31:0] cpu_data_master_readdata,                //                                  .readdata
		input  wire        cpu_data_master_write,                   //                                  .write
		input  wire [31:0] cpu_data_master_writedata,               //                                  .writedata
		input  wire        cpu_data_master_debugaccess,             //                                  .debugaccess
		input  wire [28:0] cpu_instruction_master_address,          //            cpu_instruction_master.address
		output wire        cpu_instruction_master_waitrequest,      //                                  .waitrequest
		input  wire        cpu_instruction_master_read,             //                                  .read
		output wire [31:0] cpu_instruction_master_readdata,         //                                  .readdata
		output wire [21:0] clock_crossing_io_s0_address,            //              clock_crossing_io_s0.address
		output wire        clock_crossing_io_s0_write,              //                                  .write
		output wire        clock_crossing_io_s0_read,               //                                  .read
		input  wire [31:0] clock_crossing_io_s0_readdata,           //                                  .readdata
		output wire [31:0] clock_crossing_io_s0_writedata,          //                                  .writedata
		output wire [0:0]  clock_crossing_io_s0_burstcount,         //                                  .burstcount
		output wire [3:0]  clock_crossing_io_s0_byteenable,         //                                  .byteenable
		input  wire        clock_crossing_io_s0_readdatavalid,      //                                  .readdatavalid
		input  wire        clock_crossing_io_s0_waitrequest,        //                                  .waitrequest
		output wire        clock_crossing_io_s0_debugaccess,        //                                  .debugaccess
		output wire [1:0]  clocks_pll_slave_address,                //                  clocks_pll_slave.address
		output wire        clocks_pll_slave_write,                  //                                  .write
		output wire        clocks_pll_slave_read,                   //                                  .read
		input  wire [31:0] clocks_pll_slave_readdata,               //                                  .readdata
		output wire [31:0] clocks_pll_slave_writedata,              //                                  .writedata
		output wire [8:0]  cpu_jtag_debug_module_address,           //             cpu_jtag_debug_module.address
		output wire        cpu_jtag_debug_module_write,             //                                  .write
		output wire        cpu_jtag_debug_module_read,              //                                  .read
		input  wire [31:0] cpu_jtag_debug_module_readdata,          //                                  .readdata
		output wire [31:0] cpu_jtag_debug_module_writedata,         //                                  .writedata
		output wire [3:0]  cpu_jtag_debug_module_byteenable,        //                                  .byteenable
		input  wire        cpu_jtag_debug_module_waitrequest,       //                                  .waitrequest
		output wire        cpu_jtag_debug_module_debugaccess,       //                                  .debugaccess
		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,     //       jtag_uart_avalon_jtag_slave.address
		output wire        jtag_uart_avalon_jtag_slave_write,       //                                  .write
		output wire        jtag_uart_avalon_jtag_slave_read,        //                                  .read
		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,    //                                  .readdata
		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,   //                                  .writedata
		input  wire        jtag_uart_avalon_jtag_slave_waitrequest, //                                  .waitrequest
		output wire        jtag_uart_avalon_jtag_slave_chipselect,  //                                  .chipselect
		output wire [1:0]  keycode_s1_address,                      //                        keycode_s1.address
		output wire        keycode_s1_write,                        //                                  .write
		input  wire [31:0] keycode_s1_readdata,                     //                                  .readdata
		output wire [31:0] keycode_s1_writedata,                    //                                  .writedata
		output wire        keycode_s1_chipselect,                   //                                  .chipselect
		output wire [24:0] sdram_s1_address,                        //                          sdram_s1.address
		output wire        sdram_s1_write,                          //                                  .write
		output wire        sdram_s1_read,                           //                                  .read
		input  wire [31:0] sdram_s1_readdata,                       //                                  .readdata
		output wire [31:0] sdram_s1_writedata,                      //                                  .writedata
		output wire [3:0]  sdram_s1_byteenable,                     //                                  .byteenable
		input  wire        sdram_s1_readdatavalid,                  //                                  .readdatavalid
		input  wire        sdram_s1_waitrequest,                    //                                  .waitrequest
		output wire        sdram_s1_chipselect                      //                                  .chipselect
	);

	wire          cpu_data_master_translator_avalon_universal_master_0_waitrequest;          // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
	wire   [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata;             // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
	wire          cpu_data_master_translator_avalon_universal_master_0_debugaccess;          // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
	wire   [28:0] cpu_data_master_translator_avalon_universal_master_0_address;              // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
	wire          cpu_data_master_translator_avalon_universal_master_0_read;                 // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
	wire    [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable;           // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
	wire          cpu_data_master_translator_avalon_universal_master_0_readdatavalid;        // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
	wire          cpu_data_master_translator_avalon_universal_master_0_lock;                 // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
	wire          cpu_data_master_translator_avalon_universal_master_0_write;                // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
	wire   [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata;            // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
	wire    [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount;           // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                         // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
	wire  [104:0] rsp_mux_src_data;                                                          // rsp_mux:src_data -> cpu_data_master_agent:rp_data
	wire          rsp_mux_src_ready;                                                         // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
	wire    [5:0] rsp_mux_src_channel;                                                       // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                 // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                   // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
	wire          cpu_instruction_master_translator_avalon_universal_master_0_waitrequest;   // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
	wire   [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata;      // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
	wire          cpu_instruction_master_translator_avalon_universal_master_0_debugaccess;   // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
	wire   [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address;       // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
	wire          cpu_instruction_master_translator_avalon_universal_master_0_read;          // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
	wire    [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable;    // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
	wire          cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
	wire          cpu_instruction_master_translator_avalon_universal_master_0_lock;          // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
	wire          cpu_instruction_master_translator_avalon_universal_master_0_write;         // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
	wire   [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata;     // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
	wire    [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount;    // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
	wire          rsp_mux_001_src_valid;                                                     // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
	wire  [104:0] rsp_mux_001_src_data;                                                      // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
	wire          rsp_mux_001_src_ready;                                                     // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
	wire    [5:0] rsp_mux_001_src_channel;                                                   // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
	wire          rsp_mux_001_src_startofpacket;                                             // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                               // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                             // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                          // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
	wire          jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                          // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire   [28:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                              // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire    [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                           // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire          jtag_uart_avalon_jtag_slave_agent_m0_read;                                 // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire          jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                        // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
	wire          jtag_uart_avalon_jtag_slave_agent_m0_lock;                                 // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                            // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_write;                                // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire    [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                           // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                         // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [105:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                          // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                         // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;                 // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;                   // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                      // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
	wire  [105:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                       // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                      // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;              // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;                    // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                     // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;                    // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_src_valid;                                                         // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
	wire  [104:0] cmd_mux_src_data;                                                          // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
	wire          cmd_mux_src_ready;                                                         // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
	wire    [5:0] cmd_mux_src_channel;                                                       // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                 // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                   // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
	wire   [31:0] cpu_jtag_debug_module_agent_m0_readdata;                                   // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
	wire          cpu_jtag_debug_module_agent_m0_waitrequest;                                // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
	wire          cpu_jtag_debug_module_agent_m0_debugaccess;                                // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
	wire   [28:0] cpu_jtag_debug_module_agent_m0_address;                                    // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
	wire    [3:0] cpu_jtag_debug_module_agent_m0_byteenable;                                 // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
	wire          cpu_jtag_debug_module_agent_m0_read;                                       // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
	wire          cpu_jtag_debug_module_agent_m0_readdatavalid;                              // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
	wire          cpu_jtag_debug_module_agent_m0_lock;                                       // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
	wire   [31:0] cpu_jtag_debug_module_agent_m0_writedata;                                  // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
	wire          cpu_jtag_debug_module_agent_m0_write;                                      // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
	wire    [2:0] cpu_jtag_debug_module_agent_m0_burstcount;                                 // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
	wire          cpu_jtag_debug_module_agent_rf_source_valid;                               // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
	wire  [105:0] cpu_jtag_debug_module_agent_rf_source_data;                                // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
	wire          cpu_jtag_debug_module_agent_rf_source_ready;                               // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
	wire          cpu_jtag_debug_module_agent_rf_source_startofpacket;                       // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
	wire          cpu_jtag_debug_module_agent_rf_source_endofpacket;                         // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
	wire          cpu_jtag_debug_module_agent_rsp_fifo_out_valid;                            // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
	wire  [105:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data;                             // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
	wire          cpu_jtag_debug_module_agent_rsp_fifo_out_ready;                            // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
	wire          cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket;                    // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
	wire          cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket;                      // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
	wire          cpu_jtag_debug_module_agent_rdata_fifo_src_valid;                          // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
	wire   [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data;                           // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
	wire          cpu_jtag_debug_module_agent_rdata_fifo_src_ready;                          // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
	wire          cmd_mux_001_src_valid;                                                     // cmd_mux_001:src_valid -> cpu_jtag_debug_module_agent:cp_valid
	wire  [104:0] cmd_mux_001_src_data;                                                      // cmd_mux_001:src_data -> cpu_jtag_debug_module_agent:cp_data
	wire          cmd_mux_001_src_ready;                                                     // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_001:src_ready
	wire    [5:0] cmd_mux_001_src_channel;                                                   // cmd_mux_001:src_channel -> cpu_jtag_debug_module_agent:cp_channel
	wire          cmd_mux_001_src_startofpacket;                                             // cmd_mux_001:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                               // cmd_mux_001:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
	wire   [31:0] clocks_pll_slave_agent_m0_readdata;                                        // clocks_pll_slave_translator:uav_readdata -> clocks_pll_slave_agent:m0_readdata
	wire          clocks_pll_slave_agent_m0_waitrequest;                                     // clocks_pll_slave_translator:uav_waitrequest -> clocks_pll_slave_agent:m0_waitrequest
	wire          clocks_pll_slave_agent_m0_debugaccess;                                     // clocks_pll_slave_agent:m0_debugaccess -> clocks_pll_slave_translator:uav_debugaccess
	wire   [28:0] clocks_pll_slave_agent_m0_address;                                         // clocks_pll_slave_agent:m0_address -> clocks_pll_slave_translator:uav_address
	wire    [3:0] clocks_pll_slave_agent_m0_byteenable;                                      // clocks_pll_slave_agent:m0_byteenable -> clocks_pll_slave_translator:uav_byteenable
	wire          clocks_pll_slave_agent_m0_read;                                            // clocks_pll_slave_agent:m0_read -> clocks_pll_slave_translator:uav_read
	wire          clocks_pll_slave_agent_m0_readdatavalid;                                   // clocks_pll_slave_translator:uav_readdatavalid -> clocks_pll_slave_agent:m0_readdatavalid
	wire          clocks_pll_slave_agent_m0_lock;                                            // clocks_pll_slave_agent:m0_lock -> clocks_pll_slave_translator:uav_lock
	wire   [31:0] clocks_pll_slave_agent_m0_writedata;                                       // clocks_pll_slave_agent:m0_writedata -> clocks_pll_slave_translator:uav_writedata
	wire          clocks_pll_slave_agent_m0_write;                                           // clocks_pll_slave_agent:m0_write -> clocks_pll_slave_translator:uav_write
	wire    [2:0] clocks_pll_slave_agent_m0_burstcount;                                      // clocks_pll_slave_agent:m0_burstcount -> clocks_pll_slave_translator:uav_burstcount
	wire          clocks_pll_slave_agent_rf_source_valid;                                    // clocks_pll_slave_agent:rf_source_valid -> clocks_pll_slave_agent_rsp_fifo:in_valid
	wire  [105:0] clocks_pll_slave_agent_rf_source_data;                                     // clocks_pll_slave_agent:rf_source_data -> clocks_pll_slave_agent_rsp_fifo:in_data
	wire          clocks_pll_slave_agent_rf_source_ready;                                    // clocks_pll_slave_agent_rsp_fifo:in_ready -> clocks_pll_slave_agent:rf_source_ready
	wire          clocks_pll_slave_agent_rf_source_startofpacket;                            // clocks_pll_slave_agent:rf_source_startofpacket -> clocks_pll_slave_agent_rsp_fifo:in_startofpacket
	wire          clocks_pll_slave_agent_rf_source_endofpacket;                              // clocks_pll_slave_agent:rf_source_endofpacket -> clocks_pll_slave_agent_rsp_fifo:in_endofpacket
	wire          clocks_pll_slave_agent_rsp_fifo_out_valid;                                 // clocks_pll_slave_agent_rsp_fifo:out_valid -> clocks_pll_slave_agent:rf_sink_valid
	wire  [105:0] clocks_pll_slave_agent_rsp_fifo_out_data;                                  // clocks_pll_slave_agent_rsp_fifo:out_data -> clocks_pll_slave_agent:rf_sink_data
	wire          clocks_pll_slave_agent_rsp_fifo_out_ready;                                 // clocks_pll_slave_agent:rf_sink_ready -> clocks_pll_slave_agent_rsp_fifo:out_ready
	wire          clocks_pll_slave_agent_rsp_fifo_out_startofpacket;                         // clocks_pll_slave_agent_rsp_fifo:out_startofpacket -> clocks_pll_slave_agent:rf_sink_startofpacket
	wire          clocks_pll_slave_agent_rsp_fifo_out_endofpacket;                           // clocks_pll_slave_agent_rsp_fifo:out_endofpacket -> clocks_pll_slave_agent:rf_sink_endofpacket
	wire          clocks_pll_slave_agent_rdata_fifo_src_valid;                               // clocks_pll_slave_agent:rdata_fifo_src_valid -> clocks_pll_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] clocks_pll_slave_agent_rdata_fifo_src_data;                                // clocks_pll_slave_agent:rdata_fifo_src_data -> clocks_pll_slave_agent:rdata_fifo_sink_data
	wire          clocks_pll_slave_agent_rdata_fifo_src_ready;                               // clocks_pll_slave_agent:rdata_fifo_sink_ready -> clocks_pll_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_002_src_valid;                                                     // cmd_mux_002:src_valid -> clocks_pll_slave_agent:cp_valid
	wire  [104:0] cmd_mux_002_src_data;                                                      // cmd_mux_002:src_data -> clocks_pll_slave_agent:cp_data
	wire          cmd_mux_002_src_ready;                                                     // clocks_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
	wire    [5:0] cmd_mux_002_src_channel;                                                   // cmd_mux_002:src_channel -> clocks_pll_slave_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                             // cmd_mux_002:src_startofpacket -> clocks_pll_slave_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                               // cmd_mux_002:src_endofpacket -> clocks_pll_slave_agent:cp_endofpacket
	wire   [31:0] clock_crossing_io_s0_agent_m0_readdata;                                    // clock_crossing_io_s0_translator:uav_readdata -> clock_crossing_io_s0_agent:m0_readdata
	wire          clock_crossing_io_s0_agent_m0_waitrequest;                                 // clock_crossing_io_s0_translator:uav_waitrequest -> clock_crossing_io_s0_agent:m0_waitrequest
	wire          clock_crossing_io_s0_agent_m0_debugaccess;                                 // clock_crossing_io_s0_agent:m0_debugaccess -> clock_crossing_io_s0_translator:uav_debugaccess
	wire   [28:0] clock_crossing_io_s0_agent_m0_address;                                     // clock_crossing_io_s0_agent:m0_address -> clock_crossing_io_s0_translator:uav_address
	wire    [3:0] clock_crossing_io_s0_agent_m0_byteenable;                                  // clock_crossing_io_s0_agent:m0_byteenable -> clock_crossing_io_s0_translator:uav_byteenable
	wire          clock_crossing_io_s0_agent_m0_read;                                        // clock_crossing_io_s0_agent:m0_read -> clock_crossing_io_s0_translator:uav_read
	wire          clock_crossing_io_s0_agent_m0_readdatavalid;                               // clock_crossing_io_s0_translator:uav_readdatavalid -> clock_crossing_io_s0_agent:m0_readdatavalid
	wire          clock_crossing_io_s0_agent_m0_lock;                                        // clock_crossing_io_s0_agent:m0_lock -> clock_crossing_io_s0_translator:uav_lock
	wire   [31:0] clock_crossing_io_s0_agent_m0_writedata;                                   // clock_crossing_io_s0_agent:m0_writedata -> clock_crossing_io_s0_translator:uav_writedata
	wire          clock_crossing_io_s0_agent_m0_write;                                       // clock_crossing_io_s0_agent:m0_write -> clock_crossing_io_s0_translator:uav_write
	wire    [2:0] clock_crossing_io_s0_agent_m0_burstcount;                                  // clock_crossing_io_s0_agent:m0_burstcount -> clock_crossing_io_s0_translator:uav_burstcount
	wire          clock_crossing_io_s0_agent_rf_source_valid;                                // clock_crossing_io_s0_agent:rf_source_valid -> clock_crossing_io_s0_agent_rsp_fifo:in_valid
	wire  [105:0] clock_crossing_io_s0_agent_rf_source_data;                                 // clock_crossing_io_s0_agent:rf_source_data -> clock_crossing_io_s0_agent_rsp_fifo:in_data
	wire          clock_crossing_io_s0_agent_rf_source_ready;                                // clock_crossing_io_s0_agent_rsp_fifo:in_ready -> clock_crossing_io_s0_agent:rf_source_ready
	wire          clock_crossing_io_s0_agent_rf_source_startofpacket;                        // clock_crossing_io_s0_agent:rf_source_startofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_startofpacket
	wire          clock_crossing_io_s0_agent_rf_source_endofpacket;                          // clock_crossing_io_s0_agent:rf_source_endofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_endofpacket
	wire          clock_crossing_io_s0_agent_rsp_fifo_out_valid;                             // clock_crossing_io_s0_agent_rsp_fifo:out_valid -> clock_crossing_io_s0_agent:rf_sink_valid
	wire  [105:0] clock_crossing_io_s0_agent_rsp_fifo_out_data;                              // clock_crossing_io_s0_agent_rsp_fifo:out_data -> clock_crossing_io_s0_agent:rf_sink_data
	wire          clock_crossing_io_s0_agent_rsp_fifo_out_ready;                             // clock_crossing_io_s0_agent:rf_sink_ready -> clock_crossing_io_s0_agent_rsp_fifo:out_ready
	wire          clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket;                     // clock_crossing_io_s0_agent_rsp_fifo:out_startofpacket -> clock_crossing_io_s0_agent:rf_sink_startofpacket
	wire          clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket;                       // clock_crossing_io_s0_agent_rsp_fifo:out_endofpacket -> clock_crossing_io_s0_agent:rf_sink_endofpacket
	wire          clock_crossing_io_s0_agent_rdata_fifo_src_valid;                           // clock_crossing_io_s0_agent:rdata_fifo_src_valid -> clock_crossing_io_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] clock_crossing_io_s0_agent_rdata_fifo_src_data;                            // clock_crossing_io_s0_agent:rdata_fifo_src_data -> clock_crossing_io_s0_agent:rdata_fifo_sink_data
	wire          clock_crossing_io_s0_agent_rdata_fifo_src_ready;                           // clock_crossing_io_s0_agent:rdata_fifo_sink_ready -> clock_crossing_io_s0_agent:rdata_fifo_src_ready
	wire          cmd_mux_003_src_valid;                                                     // cmd_mux_003:src_valid -> clock_crossing_io_s0_agent:cp_valid
	wire  [104:0] cmd_mux_003_src_data;                                                      // cmd_mux_003:src_data -> clock_crossing_io_s0_agent:cp_data
	wire          cmd_mux_003_src_ready;                                                     // clock_crossing_io_s0_agent:cp_ready -> cmd_mux_003:src_ready
	wire    [5:0] cmd_mux_003_src_channel;                                                   // cmd_mux_003:src_channel -> clock_crossing_io_s0_agent:cp_channel
	wire          cmd_mux_003_src_startofpacket;                                             // cmd_mux_003:src_startofpacket -> clock_crossing_io_s0_agent:cp_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                               // cmd_mux_003:src_endofpacket -> clock_crossing_io_s0_agent:cp_endofpacket
	wire   [31:0] keycode_s1_agent_m0_readdata;                                              // keycode_s1_translator:uav_readdata -> keycode_s1_agent:m0_readdata
	wire          keycode_s1_agent_m0_waitrequest;                                           // keycode_s1_translator:uav_waitrequest -> keycode_s1_agent:m0_waitrequest
	wire          keycode_s1_agent_m0_debugaccess;                                           // keycode_s1_agent:m0_debugaccess -> keycode_s1_translator:uav_debugaccess
	wire   [28:0] keycode_s1_agent_m0_address;                                               // keycode_s1_agent:m0_address -> keycode_s1_translator:uav_address
	wire    [3:0] keycode_s1_agent_m0_byteenable;                                            // keycode_s1_agent:m0_byteenable -> keycode_s1_translator:uav_byteenable
	wire          keycode_s1_agent_m0_read;                                                  // keycode_s1_agent:m0_read -> keycode_s1_translator:uav_read
	wire          keycode_s1_agent_m0_readdatavalid;                                         // keycode_s1_translator:uav_readdatavalid -> keycode_s1_agent:m0_readdatavalid
	wire          keycode_s1_agent_m0_lock;                                                  // keycode_s1_agent:m0_lock -> keycode_s1_translator:uav_lock
	wire   [31:0] keycode_s1_agent_m0_writedata;                                             // keycode_s1_agent:m0_writedata -> keycode_s1_translator:uav_writedata
	wire          keycode_s1_agent_m0_write;                                                 // keycode_s1_agent:m0_write -> keycode_s1_translator:uav_write
	wire    [2:0] keycode_s1_agent_m0_burstcount;                                            // keycode_s1_agent:m0_burstcount -> keycode_s1_translator:uav_burstcount
	wire          keycode_s1_agent_rf_source_valid;                                          // keycode_s1_agent:rf_source_valid -> keycode_s1_agent_rsp_fifo:in_valid
	wire  [105:0] keycode_s1_agent_rf_source_data;                                           // keycode_s1_agent:rf_source_data -> keycode_s1_agent_rsp_fifo:in_data
	wire          keycode_s1_agent_rf_source_ready;                                          // keycode_s1_agent_rsp_fifo:in_ready -> keycode_s1_agent:rf_source_ready
	wire          keycode_s1_agent_rf_source_startofpacket;                                  // keycode_s1_agent:rf_source_startofpacket -> keycode_s1_agent_rsp_fifo:in_startofpacket
	wire          keycode_s1_agent_rf_source_endofpacket;                                    // keycode_s1_agent:rf_source_endofpacket -> keycode_s1_agent_rsp_fifo:in_endofpacket
	wire          keycode_s1_agent_rsp_fifo_out_valid;                                       // keycode_s1_agent_rsp_fifo:out_valid -> keycode_s1_agent:rf_sink_valid
	wire  [105:0] keycode_s1_agent_rsp_fifo_out_data;                                        // keycode_s1_agent_rsp_fifo:out_data -> keycode_s1_agent:rf_sink_data
	wire          keycode_s1_agent_rsp_fifo_out_ready;                                       // keycode_s1_agent:rf_sink_ready -> keycode_s1_agent_rsp_fifo:out_ready
	wire          keycode_s1_agent_rsp_fifo_out_startofpacket;                               // keycode_s1_agent_rsp_fifo:out_startofpacket -> keycode_s1_agent:rf_sink_startofpacket
	wire          keycode_s1_agent_rsp_fifo_out_endofpacket;                                 // keycode_s1_agent_rsp_fifo:out_endofpacket -> keycode_s1_agent:rf_sink_endofpacket
	wire          keycode_s1_agent_rdata_fifo_src_valid;                                     // keycode_s1_agent:rdata_fifo_src_valid -> keycode_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] keycode_s1_agent_rdata_fifo_src_data;                                      // keycode_s1_agent:rdata_fifo_src_data -> keycode_s1_agent:rdata_fifo_sink_data
	wire          keycode_s1_agent_rdata_fifo_src_ready;                                     // keycode_s1_agent:rdata_fifo_sink_ready -> keycode_s1_agent:rdata_fifo_src_ready
	wire          cmd_mux_004_src_valid;                                                     // cmd_mux_004:src_valid -> keycode_s1_agent:cp_valid
	wire  [104:0] cmd_mux_004_src_data;                                                      // cmd_mux_004:src_data -> keycode_s1_agent:cp_data
	wire          cmd_mux_004_src_ready;                                                     // keycode_s1_agent:cp_ready -> cmd_mux_004:src_ready
	wire    [5:0] cmd_mux_004_src_channel;                                                   // cmd_mux_004:src_channel -> keycode_s1_agent:cp_channel
	wire          cmd_mux_004_src_startofpacket;                                             // cmd_mux_004:src_startofpacket -> keycode_s1_agent:cp_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                               // cmd_mux_004:src_endofpacket -> keycode_s1_agent:cp_endofpacket
	wire   [31:0] sdram_s1_agent_m0_readdata;                                                // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
	wire          sdram_s1_agent_m0_waitrequest;                                             // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
	wire          sdram_s1_agent_m0_debugaccess;                                             // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
	wire   [28:0] sdram_s1_agent_m0_address;                                                 // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
	wire    [3:0] sdram_s1_agent_m0_byteenable;                                              // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
	wire          sdram_s1_agent_m0_read;                                                    // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
	wire          sdram_s1_agent_m0_readdatavalid;                                           // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
	wire          sdram_s1_agent_m0_lock;                                                    // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
	wire   [31:0] sdram_s1_agent_m0_writedata;                                               // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
	wire          sdram_s1_agent_m0_write;                                                   // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
	wire    [2:0] sdram_s1_agent_m0_burstcount;                                              // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
	wire          sdram_s1_agent_rf_source_valid;                                            // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
	wire  [105:0] sdram_s1_agent_rf_source_data;                                             // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
	wire          sdram_s1_agent_rf_source_ready;                                            // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
	wire          sdram_s1_agent_rf_source_startofpacket;                                    // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
	wire          sdram_s1_agent_rf_source_endofpacket;                                      // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
	wire          sdram_s1_agent_rsp_fifo_out_valid;                                         // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
	wire  [105:0] sdram_s1_agent_rsp_fifo_out_data;                                          // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
	wire          sdram_s1_agent_rsp_fifo_out_ready;                                         // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
	wire          sdram_s1_agent_rsp_fifo_out_startofpacket;                                 // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
	wire          sdram_s1_agent_rsp_fifo_out_endofpacket;                                   // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
	wire          sdram_s1_agent_rdata_fifo_src_valid;                                       // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
	wire   [33:0] sdram_s1_agent_rdata_fifo_src_data;                                        // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
	wire          sdram_s1_agent_rdata_fifo_src_ready;                                       // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
	wire          sdram_s1_agent_rdata_fifo_out_valid;                                       // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] sdram_s1_agent_rdata_fifo_out_data;                                        // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
	wire          sdram_s1_agent_rdata_fifo_out_ready;                                       // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
	wire          cmd_mux_005_src_valid;                                                     // cmd_mux_005:src_valid -> sdram_s1_agent:cp_valid
	wire  [104:0] cmd_mux_005_src_data;                                                      // cmd_mux_005:src_data -> sdram_s1_agent:cp_data
	wire          cmd_mux_005_src_ready;                                                     // sdram_s1_agent:cp_ready -> cmd_mux_005:src_ready
	wire    [5:0] cmd_mux_005_src_channel;                                                   // cmd_mux_005:src_channel -> sdram_s1_agent:cp_channel
	wire          cmd_mux_005_src_startofpacket;                                             // cmd_mux_005:src_startofpacket -> sdram_s1_agent:cp_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                               // cmd_mux_005:src_endofpacket -> sdram_s1_agent:cp_endofpacket
	wire          cpu_data_master_agent_cp_valid;                                            // cpu_data_master_agent:cp_valid -> router:sink_valid
	wire  [104:0] cpu_data_master_agent_cp_data;                                             // cpu_data_master_agent:cp_data -> router:sink_data
	wire          cpu_data_master_agent_cp_ready;                                            // router:sink_ready -> cpu_data_master_agent:cp_ready
	wire          cpu_data_master_agent_cp_startofpacket;                                    // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          cpu_data_master_agent_cp_endofpacket;                                      // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                          // router:src_valid -> cmd_demux:sink_valid
	wire  [104:0] router_src_data;                                                           // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                          // cmd_demux:sink_ready -> router:src_ready
	wire    [5:0] router_src_channel;                                                        // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                  // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                    // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          cpu_instruction_master_agent_cp_valid;                                     // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
	wire  [104:0] cpu_instruction_master_agent_cp_data;                                      // cpu_instruction_master_agent:cp_data -> router_001:sink_data
	wire          cpu_instruction_master_agent_cp_ready;                                     // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
	wire          cpu_instruction_master_agent_cp_startofpacket;                             // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
	wire          cpu_instruction_master_agent_cp_endofpacket;                               // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                      // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [104:0] router_001_src_data;                                                       // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                      // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [5:0] router_001_src_channel;                                                    // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                              // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_valid;                                // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
	wire  [104:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                                 // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rp_ready;                                // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                        // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                          // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                      // router_002:src_valid -> rsp_demux:sink_valid
	wire  [104:0] router_002_src_data;                                                       // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                                      // rsp_demux:sink_ready -> router_002:src_ready
	wire    [5:0] router_002_src_channel;                                                    // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                              // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                                // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cpu_jtag_debug_module_agent_rp_valid;                                      // cpu_jtag_debug_module_agent:rp_valid -> router_003:sink_valid
	wire  [104:0] cpu_jtag_debug_module_agent_rp_data;                                       // cpu_jtag_debug_module_agent:rp_data -> router_003:sink_data
	wire          cpu_jtag_debug_module_agent_rp_ready;                                      // router_003:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
	wire          cpu_jtag_debug_module_agent_rp_startofpacket;                              // cpu_jtag_debug_module_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          cpu_jtag_debug_module_agent_rp_endofpacket;                                // cpu_jtag_debug_module_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                                      // router_003:src_valid -> rsp_demux_001:sink_valid
	wire  [104:0] router_003_src_data;                                                       // router_003:src_data -> rsp_demux_001:sink_data
	wire          router_003_src_ready;                                                      // rsp_demux_001:sink_ready -> router_003:src_ready
	wire    [5:0] router_003_src_channel;                                                    // router_003:src_channel -> rsp_demux_001:sink_channel
	wire          router_003_src_startofpacket;                                              // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_003_src_endofpacket;                                                // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          clocks_pll_slave_agent_rp_valid;                                           // clocks_pll_slave_agent:rp_valid -> router_004:sink_valid
	wire  [104:0] clocks_pll_slave_agent_rp_data;                                            // clocks_pll_slave_agent:rp_data -> router_004:sink_data
	wire          clocks_pll_slave_agent_rp_ready;                                           // router_004:sink_ready -> clocks_pll_slave_agent:rp_ready
	wire          clocks_pll_slave_agent_rp_startofpacket;                                   // clocks_pll_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          clocks_pll_slave_agent_rp_endofpacket;                                     // clocks_pll_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                      // router_004:src_valid -> rsp_demux_002:sink_valid
	wire  [104:0] router_004_src_data;                                                       // router_004:src_data -> rsp_demux_002:sink_data
	wire          router_004_src_ready;                                                      // rsp_demux_002:sink_ready -> router_004:src_ready
	wire    [5:0] router_004_src_channel;                                                    // router_004:src_channel -> rsp_demux_002:sink_channel
	wire          router_004_src_startofpacket;                                              // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_004_src_endofpacket;                                                // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          clock_crossing_io_s0_agent_rp_valid;                                       // clock_crossing_io_s0_agent:rp_valid -> router_005:sink_valid
	wire  [104:0] clock_crossing_io_s0_agent_rp_data;                                        // clock_crossing_io_s0_agent:rp_data -> router_005:sink_data
	wire          clock_crossing_io_s0_agent_rp_ready;                                       // router_005:sink_ready -> clock_crossing_io_s0_agent:rp_ready
	wire          clock_crossing_io_s0_agent_rp_startofpacket;                               // clock_crossing_io_s0_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          clock_crossing_io_s0_agent_rp_endofpacket;                                 // clock_crossing_io_s0_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                      // router_005:src_valid -> rsp_demux_003:sink_valid
	wire  [104:0] router_005_src_data;                                                       // router_005:src_data -> rsp_demux_003:sink_data
	wire          router_005_src_ready;                                                      // rsp_demux_003:sink_ready -> router_005:src_ready
	wire    [5:0] router_005_src_channel;                                                    // router_005:src_channel -> rsp_demux_003:sink_channel
	wire          router_005_src_startofpacket;                                              // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_005_src_endofpacket;                                                // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          keycode_s1_agent_rp_valid;                                                 // keycode_s1_agent:rp_valid -> router_006:sink_valid
	wire  [104:0] keycode_s1_agent_rp_data;                                                  // keycode_s1_agent:rp_data -> router_006:sink_data
	wire          keycode_s1_agent_rp_ready;                                                 // router_006:sink_ready -> keycode_s1_agent:rp_ready
	wire          keycode_s1_agent_rp_startofpacket;                                         // keycode_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          keycode_s1_agent_rp_endofpacket;                                           // keycode_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                      // router_006:src_valid -> rsp_demux_004:sink_valid
	wire  [104:0] router_006_src_data;                                                       // router_006:src_data -> rsp_demux_004:sink_data
	wire          router_006_src_ready;                                                      // rsp_demux_004:sink_ready -> router_006:src_ready
	wire    [5:0] router_006_src_channel;                                                    // router_006:src_channel -> rsp_demux_004:sink_channel
	wire          router_006_src_startofpacket;                                              // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_006_src_endofpacket;                                                // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          sdram_s1_agent_rp_valid;                                                   // sdram_s1_agent:rp_valid -> router_007:sink_valid
	wire  [104:0] sdram_s1_agent_rp_data;                                                    // sdram_s1_agent:rp_data -> router_007:sink_data
	wire          sdram_s1_agent_rp_ready;                                                   // router_007:sink_ready -> sdram_s1_agent:rp_ready
	wire          sdram_s1_agent_rp_startofpacket;                                           // sdram_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          sdram_s1_agent_rp_endofpacket;                                             // sdram_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                      // router_007:src_valid -> rsp_demux_005:sink_valid
	wire  [104:0] router_007_src_data;                                                       // router_007:src_data -> rsp_demux_005:sink_data
	wire          router_007_src_ready;                                                      // rsp_demux_005:sink_ready -> router_007:src_ready
	wire    [5:0] router_007_src_channel;                                                    // router_007:src_channel -> rsp_demux_005:sink_channel
	wire          router_007_src_startofpacket;                                              // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_007_src_endofpacket;                                                // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                      // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [104:0] cmd_demux_src0_data;                                                       // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                      // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [5:0] cmd_demux_src0_channel;                                                    // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                              // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                      // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [104:0] cmd_demux_src1_data;                                                       // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                      // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [5:0] cmd_demux_src1_channel;                                                    // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                              // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                      // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [104:0] cmd_demux_src2_data;                                                       // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                      // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [5:0] cmd_demux_src2_channel;                                                    // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                              // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                      // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [104:0] cmd_demux_src3_data;                                                       // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                                      // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire    [5:0] cmd_demux_src3_channel;                                                    // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                              // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                                // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                                      // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire  [104:0] cmd_demux_src4_data;                                                       // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                                      // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire    [5:0] cmd_demux_src4_channel;                                                    // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                              // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                                // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                  // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
	wire  [104:0] cmd_demux_001_src0_data;                                                   // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_001_src0_ready;                                                  // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
	wire    [5:0] cmd_demux_001_src0_channel;                                                // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                          // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                            // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_001_src1_valid;                                                  // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
	wire  [104:0] cmd_demux_001_src1_data;                                                   // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_001_src1_ready;                                                  // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
	wire    [5:0] cmd_demux_001_src1_channel;                                                // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_001_src1_startofpacket;                                          // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                            // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                      // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [104:0] rsp_demux_src0_data;                                                       // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                      // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [5:0] rsp_demux_src0_channel;                                                    // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                              // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                  // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [104:0] rsp_demux_001_src0_data;                                                   // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                  // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [5:0] rsp_demux_001_src0_channel;                                                // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                          // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                            // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                                  // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
	wire  [104:0] rsp_demux_001_src1_data;                                                   // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_001_src1_ready;                                                  // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
	wire    [5:0] rsp_demux_001_src1_channel;                                                // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_001_src1_startofpacket;                                          // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                            // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_002_src0_valid;                                                  // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [104:0] rsp_demux_002_src0_data;                                                   // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                                  // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [5:0] rsp_demux_002_src0_channel;                                                // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                          // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                            // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_002_src1_valid;                                                  // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
	wire  [104:0] rsp_demux_002_src1_data;                                                   // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_002_src1_ready;                                                  // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
	wire    [5:0] rsp_demux_002_src1_channel;                                                // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_002_src1_startofpacket;                                          // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                            // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_003_src0_valid;                                                  // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [104:0] rsp_demux_003_src0_data;                                                   // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                                  // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire    [5:0] rsp_demux_003_src0_channel;                                                // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                          // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                            // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                                  // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire  [104:0] rsp_demux_004_src0_data;                                                   // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                                  // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire    [5:0] rsp_demux_004_src0_channel;                                                // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                          // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                            // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          cmd_demux_src5_valid;                                                      // cmd_demux:src5_valid -> crosser:in_valid
	wire  [104:0] cmd_demux_src5_data;                                                       // cmd_demux:src5_data -> crosser:in_data
	wire          cmd_demux_src5_ready;                                                      // crosser:in_ready -> cmd_demux:src5_ready
	wire    [5:0] cmd_demux_src5_channel;                                                    // cmd_demux:src5_channel -> crosser:in_channel
	wire          cmd_demux_src5_startofpacket;                                              // cmd_demux:src5_startofpacket -> crosser:in_startofpacket
	wire          cmd_demux_src5_endofpacket;                                                // cmd_demux:src5_endofpacket -> crosser:in_endofpacket
	wire          crosser_out_valid;                                                         // crosser:out_valid -> cmd_mux_005:sink0_valid
	wire  [104:0] crosser_out_data;                                                          // crosser:out_data -> cmd_mux_005:sink0_data
	wire          crosser_out_ready;                                                         // cmd_mux_005:sink0_ready -> crosser:out_ready
	wire    [5:0] crosser_out_channel;                                                       // crosser:out_channel -> cmd_mux_005:sink0_channel
	wire          crosser_out_startofpacket;                                                 // crosser:out_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          crosser_out_endofpacket;                                                   // crosser:out_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_001_src2_valid;                                                  // cmd_demux_001:src2_valid -> crosser_001:in_valid
	wire  [104:0] cmd_demux_001_src2_data;                                                   // cmd_demux_001:src2_data -> crosser_001:in_data
	wire          cmd_demux_001_src2_ready;                                                  // crosser_001:in_ready -> cmd_demux_001:src2_ready
	wire    [5:0] cmd_demux_001_src2_channel;                                                // cmd_demux_001:src2_channel -> crosser_001:in_channel
	wire          cmd_demux_001_src2_startofpacket;                                          // cmd_demux_001:src2_startofpacket -> crosser_001:in_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                            // cmd_demux_001:src2_endofpacket -> crosser_001:in_endofpacket
	wire          crosser_001_out_valid;                                                     // crosser_001:out_valid -> cmd_mux_005:sink1_valid
	wire  [104:0] crosser_001_out_data;                                                      // crosser_001:out_data -> cmd_mux_005:sink1_data
	wire          crosser_001_out_ready;                                                     // cmd_mux_005:sink1_ready -> crosser_001:out_ready
	wire    [5:0] crosser_001_out_channel;                                                   // crosser_001:out_channel -> cmd_mux_005:sink1_channel
	wire          crosser_001_out_startofpacket;                                             // crosser_001:out_startofpacket -> cmd_mux_005:sink1_startofpacket
	wire          crosser_001_out_endofpacket;                                               // crosser_001:out_endofpacket -> cmd_mux_005:sink1_endofpacket
	wire          rsp_demux_005_src0_valid;                                                  // rsp_demux_005:src0_valid -> crosser_002:in_valid
	wire  [104:0] rsp_demux_005_src0_data;                                                   // rsp_demux_005:src0_data -> crosser_002:in_data
	wire          rsp_demux_005_src0_ready;                                                  // crosser_002:in_ready -> rsp_demux_005:src0_ready
	wire    [5:0] rsp_demux_005_src0_channel;                                                // rsp_demux_005:src0_channel -> crosser_002:in_channel
	wire          rsp_demux_005_src0_startofpacket;                                          // rsp_demux_005:src0_startofpacket -> crosser_002:in_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                            // rsp_demux_005:src0_endofpacket -> crosser_002:in_endofpacket
	wire          crosser_002_out_valid;                                                     // crosser_002:out_valid -> rsp_mux:sink5_valid
	wire  [104:0] crosser_002_out_data;                                                      // crosser_002:out_data -> rsp_mux:sink5_data
	wire          crosser_002_out_ready;                                                     // rsp_mux:sink5_ready -> crosser_002:out_ready
	wire    [5:0] crosser_002_out_channel;                                                   // crosser_002:out_channel -> rsp_mux:sink5_channel
	wire          crosser_002_out_startofpacket;                                             // crosser_002:out_startofpacket -> rsp_mux:sink5_startofpacket
	wire          crosser_002_out_endofpacket;                                               // crosser_002:out_endofpacket -> rsp_mux:sink5_endofpacket
	wire          rsp_demux_005_src1_valid;                                                  // rsp_demux_005:src1_valid -> crosser_003:in_valid
	wire  [104:0] rsp_demux_005_src1_data;                                                   // rsp_demux_005:src1_data -> crosser_003:in_data
	wire          rsp_demux_005_src1_ready;                                                  // crosser_003:in_ready -> rsp_demux_005:src1_ready
	wire    [5:0] rsp_demux_005_src1_channel;                                                // rsp_demux_005:src1_channel -> crosser_003:in_channel
	wire          rsp_demux_005_src1_startofpacket;                                          // rsp_demux_005:src1_startofpacket -> crosser_003:in_startofpacket
	wire          rsp_demux_005_src1_endofpacket;                                            // rsp_demux_005:src1_endofpacket -> crosser_003:in_endofpacket
	wire          crosser_003_out_valid;                                                     // crosser_003:out_valid -> rsp_mux_001:sink2_valid
	wire  [104:0] crosser_003_out_data;                                                      // crosser_003:out_data -> rsp_mux_001:sink2_data
	wire          crosser_003_out_ready;                                                     // rsp_mux_001:sink2_ready -> crosser_003:out_ready
	wire    [5:0] crosser_003_out_channel;                                                   // crosser_003:out_channel -> rsp_mux_001:sink2_channel
	wire          crosser_003_out_startofpacket;                                             // crosser_003:out_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          crosser_003_out_endofpacket;                                               // crosser_003:out_endofpacket -> rsp_mux_001:sink2_endofpacket

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (29),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (29),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) cpu_data_master_translator (
		.clk                    (clk_clk_clk),                                                        //                       clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset),                            //                     reset.reset
		.uav_address            (cpu_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable          (cpu_data_master_byteenable),                                         //                          .byteenable
		.av_read                (cpu_data_master_read),                                               //                          .read
		.av_readdata            (cpu_data_master_readdata),                                           //                          .readdata
		.av_write               (cpu_data_master_write),                                              //                          .write
		.av_writedata           (cpu_data_master_writedata),                                          //                          .writedata
		.av_debugaccess         (cpu_data_master_debugaccess),                                        //                          .debugaccess
		.av_burstcount          (1'b1),                                                               //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                               //               (terminated)
		.av_begintransfer       (1'b0),                                                               //               (terminated)
		.av_chipselect          (1'b0),                                                               //               (terminated)
		.av_readdatavalid       (),                                                                   //               (terminated)
		.av_lock                (1'b0),                                                               //               (terminated)
		.uav_clken              (),                                                                   //               (terminated)
		.av_clken               (1'b1),                                                               //               (terminated)
		.uav_response           (2'b00),                                                              //               (terminated)
		.av_response            (),                                                                   //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                               //               (terminated)
		.av_writeresponsevalid  ()                                                                    //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (29),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (29),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_instruction_master_translator (
		.clk                    (clk_clk_clk),                                                               //                       clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset),                                   //                     reset.reset
		.uav_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address             (cpu_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest         (cpu_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read                (cpu_instruction_master_read),                                               //                          .read
		.av_readdata            (cpu_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount          (1'b1),                                                                      //               (terminated)
		.av_byteenable          (4'b1111),                                                                   //               (terminated)
		.av_beginbursttransfer  (1'b0),                                                                      //               (terminated)
		.av_begintransfer       (1'b0),                                                                      //               (terminated)
		.av_chipselect          (1'b0),                                                                      //               (terminated)
		.av_readdatavalid       (),                                                                          //               (terminated)
		.av_write               (1'b0),                                                                      //               (terminated)
		.av_writedata           (32'b00000000000000000000000000000000),                                      //               (terminated)
		.av_lock                (1'b0),                                                                      //               (terminated)
		.av_debugaccess         (1'b0),                                                                      //               (terminated)
		.uav_clken              (),                                                                          //               (terminated)
		.av_clken               (1'b1),                                                                      //               (terminated)
		.uav_response           (2'b00),                                                                     //               (terminated)
		.av_response            (),                                                                          //               (terminated)
		.uav_writeresponsevalid (1'b0),                                                                      //               (terminated)
		.av_writeresponsevalid  ()                                                                           //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                    (clk_clk_clk),                                        //                      clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset),            //                    reset.reset
		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),          //                         .read
		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (jtag_uart_avalon_jtag_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (jtag_uart_avalon_jtag_slave_write),                  //                         .write
		.av_read                (jtag_uart_avalon_jtag_slave_read),                   //                         .read
		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),               //                         .readdata
		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),              //                         .writedata
		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),            //                         .waitrequest
		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),             //                         .chipselect
		.av_begintransfer       (),                                                   //              (terminated)
		.av_beginbursttransfer  (),                                                   //              (terminated)
		.av_burstcount          (),                                                   //              (terminated)
		.av_byteenable          (),                                                   //              (terminated)
		.av_readdatavalid       (1'b0),                                               //              (terminated)
		.av_writebyteenable     (),                                                   //              (terminated)
		.av_lock                (),                                                   //              (terminated)
		.av_clken               (),                                                   //              (terminated)
		.uav_clken              (1'b0),                                               //              (terminated)
		.av_debugaccess         (),                                                   //              (terminated)
		.av_outputenable        (),                                                   //              (terminated)
		.uav_response           (),                                                   //              (terminated)
		.av_response            (2'b00),                                              //              (terminated)
		.uav_writeresponsevalid (),                                                   //              (terminated)
		.av_writeresponsevalid  (1'b0)                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) cpu_jtag_debug_module_translator (
		.clk                    (clk_clk_clk),                                  //                      clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset),      //                    reset.reset
		.uav_address            (cpu_jtag_debug_module_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (cpu_jtag_debug_module_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (cpu_jtag_debug_module_agent_m0_read),          //                         .read
		.uav_write              (cpu_jtag_debug_module_agent_m0_write),         //                         .write
		.uav_waitrequest        (cpu_jtag_debug_module_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (cpu_jtag_debug_module_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (cpu_jtag_debug_module_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (cpu_jtag_debug_module_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (cpu_jtag_debug_module_agent_m0_writedata),     //                         .writedata
		.uav_lock               (cpu_jtag_debug_module_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (cpu_jtag_debug_module_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (cpu_jtag_debug_module_address),                //      avalon_anti_slave_0.address
		.av_write               (cpu_jtag_debug_module_write),                  //                         .write
		.av_read                (cpu_jtag_debug_module_read),                   //                         .read
		.av_readdata            (cpu_jtag_debug_module_readdata),               //                         .readdata
		.av_writedata           (cpu_jtag_debug_module_writedata),              //                         .writedata
		.av_byteenable          (cpu_jtag_debug_module_byteenable),             //                         .byteenable
		.av_waitrequest         (cpu_jtag_debug_module_waitrequest),            //                         .waitrequest
		.av_debugaccess         (cpu_jtag_debug_module_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                             //              (terminated)
		.av_beginbursttransfer  (),                                             //              (terminated)
		.av_burstcount          (),                                             //              (terminated)
		.av_readdatavalid       (1'b0),                                         //              (terminated)
		.av_writebyteenable     (),                                             //              (terminated)
		.av_lock                (),                                             //              (terminated)
		.av_chipselect          (),                                             //              (terminated)
		.av_clken               (),                                             //              (terminated)
		.uav_clken              (1'b0),                                         //              (terminated)
		.av_outputenable        (),                                             //              (terminated)
		.uav_response           (),                                             //              (terminated)
		.av_response            (2'b00),                                        //              (terminated)
		.uav_writeresponsevalid (),                                             //              (terminated)
		.av_writeresponsevalid  (1'b0)                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) clocks_pll_slave_translator (
		.clk                    (clk_clk_clk),                             //                      clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (clocks_pll_slave_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (clocks_pll_slave_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (clocks_pll_slave_agent_m0_read),          //                         .read
		.uav_write              (clocks_pll_slave_agent_m0_write),         //                         .write
		.uav_waitrequest        (clocks_pll_slave_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (clocks_pll_slave_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (clocks_pll_slave_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (clocks_pll_slave_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (clocks_pll_slave_agent_m0_writedata),     //                         .writedata
		.uav_lock               (clocks_pll_slave_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (clocks_pll_slave_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (clocks_pll_slave_address),                //      avalon_anti_slave_0.address
		.av_write               (clocks_pll_slave_write),                  //                         .write
		.av_read                (clocks_pll_slave_read),                   //                         .read
		.av_readdata            (clocks_pll_slave_readdata),               //                         .readdata
		.av_writedata           (clocks_pll_slave_writedata),              //                         .writedata
		.av_begintransfer       (),                                        //              (terminated)
		.av_beginbursttransfer  (),                                        //              (terminated)
		.av_burstcount          (),                                        //              (terminated)
		.av_byteenable          (),                                        //              (terminated)
		.av_readdatavalid       (1'b0),                                    //              (terminated)
		.av_waitrequest         (1'b0),                                    //              (terminated)
		.av_writebyteenable     (),                                        //              (terminated)
		.av_lock                (),                                        //              (terminated)
		.av_chipselect          (),                                        //              (terminated)
		.av_clken               (),                                        //              (terminated)
		.uav_clken              (1'b0),                                    //              (terminated)
		.av_debugaccess         (),                                        //              (terminated)
		.av_outputenable        (),                                        //              (terminated)
		.uav_response           (),                                        //              (terminated)
		.av_response            (2'b00),                                   //              (terminated)
		.uav_writeresponsevalid (),                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (22),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) clock_crossing_io_s0_translator (
		.clk                    (clk_clk_clk),                                 //                      clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset),     //                    reset.reset
		.uav_address            (clock_crossing_io_s0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount         (clock_crossing_io_s0_agent_m0_burstcount),    //                         .burstcount
		.uav_read               (clock_crossing_io_s0_agent_m0_read),          //                         .read
		.uav_write              (clock_crossing_io_s0_agent_m0_write),         //                         .write
		.uav_waitrequest        (clock_crossing_io_s0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid      (clock_crossing_io_s0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable         (clock_crossing_io_s0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata           (clock_crossing_io_s0_agent_m0_readdata),      //                         .readdata
		.uav_writedata          (clock_crossing_io_s0_agent_m0_writedata),     //                         .writedata
		.uav_lock               (clock_crossing_io_s0_agent_m0_lock),          //                         .lock
		.uav_debugaccess        (clock_crossing_io_s0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address             (clock_crossing_io_s0_address),                //      avalon_anti_slave_0.address
		.av_write               (clock_crossing_io_s0_write),                  //                         .write
		.av_read                (clock_crossing_io_s0_read),                   //                         .read
		.av_readdata            (clock_crossing_io_s0_readdata),               //                         .readdata
		.av_writedata           (clock_crossing_io_s0_writedata),              //                         .writedata
		.av_burstcount          (clock_crossing_io_s0_burstcount),             //                         .burstcount
		.av_byteenable          (clock_crossing_io_s0_byteenable),             //                         .byteenable
		.av_readdatavalid       (clock_crossing_io_s0_readdatavalid),          //                         .readdatavalid
		.av_waitrequest         (clock_crossing_io_s0_waitrequest),            //                         .waitrequest
		.av_debugaccess         (clock_crossing_io_s0_debugaccess),            //                         .debugaccess
		.av_begintransfer       (),                                            //              (terminated)
		.av_beginbursttransfer  (),                                            //              (terminated)
		.av_writebyteenable     (),                                            //              (terminated)
		.av_lock                (),                                            //              (terminated)
		.av_chipselect          (),                                            //              (terminated)
		.av_clken               (),                                            //              (terminated)
		.uav_clken              (1'b0),                                        //              (terminated)
		.av_outputenable        (),                                            //              (terminated)
		.uav_response           (),                                            //              (terminated)
		.av_response            (2'b00),                                       //              (terminated)
		.uav_writeresponsevalid (),                                            //              (terminated)
		.av_writeresponsevalid  (1'b0)                                         //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) keycode_s1_translator (
		.clk                    (clk_clk_clk),                             //                      clk.clk
		.reset                  (cpu_reset_n_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (keycode_s1_agent_m0_address),             // avalon_universal_slave_0.address
		.uav_burstcount         (keycode_s1_agent_m0_burstcount),          //                         .burstcount
		.uav_read               (keycode_s1_agent_m0_read),                //                         .read
		.uav_write              (keycode_s1_agent_m0_write),               //                         .write
		.uav_waitrequest        (keycode_s1_agent_m0_waitrequest),         //                         .waitrequest
		.uav_readdatavalid      (keycode_s1_agent_m0_readdatavalid),       //                         .readdatavalid
		.uav_byteenable         (keycode_s1_agent_m0_byteenable),          //                         .byteenable
		.uav_readdata           (keycode_s1_agent_m0_readdata),            //                         .readdata
		.uav_writedata          (keycode_s1_agent_m0_writedata),           //                         .writedata
		.uav_lock               (keycode_s1_agent_m0_lock),                //                         .lock
		.uav_debugaccess        (keycode_s1_agent_m0_debugaccess),         //                         .debugaccess
		.av_address             (keycode_s1_address),                      //      avalon_anti_slave_0.address
		.av_write               (keycode_s1_write),                        //                         .write
		.av_readdata            (keycode_s1_readdata),                     //                         .readdata
		.av_writedata           (keycode_s1_writedata),                    //                         .writedata
		.av_chipselect          (keycode_s1_chipselect),                   //                         .chipselect
		.av_read                (),                                        //              (terminated)
		.av_begintransfer       (),                                        //              (terminated)
		.av_beginbursttransfer  (),                                        //              (terminated)
		.av_burstcount          (),                                        //              (terminated)
		.av_byteenable          (),                                        //              (terminated)
		.av_readdatavalid       (1'b0),                                    //              (terminated)
		.av_waitrequest         (1'b0),                                    //              (terminated)
		.av_writebyteenable     (),                                        //              (terminated)
		.av_lock                (),                                        //              (terminated)
		.av_clken               (),                                        //              (terminated)
		.uav_clken              (1'b0),                                    //              (terminated)
		.av_debugaccess         (),                                        //              (terminated)
		.av_outputenable        (),                                        //              (terminated)
		.uav_response           (),                                        //              (terminated)
		.av_response            (2'b00),                                   //              (terminated)
		.uav_writeresponsevalid (),                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sdram_s1_translator (
		.clk                    (clocks_c0_clk),                           //                      clk.clk
		.reset                  (sdram_reset_reset_bridge_in_reset_reset), //                    reset.reset
		.uav_address            (sdram_s1_agent_m0_address),               // avalon_universal_slave_0.address
		.uav_burstcount         (sdram_s1_agent_m0_burstcount),            //                         .burstcount
		.uav_read               (sdram_s1_agent_m0_read),                  //                         .read
		.uav_write              (sdram_s1_agent_m0_write),                 //                         .write
		.uav_waitrequest        (sdram_s1_agent_m0_waitrequest),           //                         .waitrequest
		.uav_readdatavalid      (sdram_s1_agent_m0_readdatavalid),         //                         .readdatavalid
		.uav_byteenable         (sdram_s1_agent_m0_byteenable),            //                         .byteenable
		.uav_readdata           (sdram_s1_agent_m0_readdata),              //                         .readdata
		.uav_writedata          (sdram_s1_agent_m0_writedata),             //                         .writedata
		.uav_lock               (sdram_s1_agent_m0_lock),                  //                         .lock
		.uav_debugaccess        (sdram_s1_agent_m0_debugaccess),           //                         .debugaccess
		.av_address             (sdram_s1_address),                        //      avalon_anti_slave_0.address
		.av_write               (sdram_s1_write),                          //                         .write
		.av_read                (sdram_s1_read),                           //                         .read
		.av_readdata            (sdram_s1_readdata),                       //                         .readdata
		.av_writedata           (sdram_s1_writedata),                      //                         .writedata
		.av_byteenable          (sdram_s1_byteenable),                     //                         .byteenable
		.av_readdatavalid       (sdram_s1_readdatavalid),                  //                         .readdatavalid
		.av_waitrequest         (sdram_s1_waitrequest),                    //                         .waitrequest
		.av_chipselect          (sdram_s1_chipselect),                     //                         .chipselect
		.av_begintransfer       (),                                        //              (terminated)
		.av_beginbursttransfer  (),                                        //              (terminated)
		.av_burstcount          (),                                        //              (terminated)
		.av_writebyteenable     (),                                        //              (terminated)
		.av_lock                (),                                        //              (terminated)
		.av_clken               (),                                        //              (terminated)
		.uav_clken              (1'b0),                                    //              (terminated)
		.av_debugaccess         (),                                        //              (terminated)
		.av_outputenable        (),                                        //              (terminated)
		.uav_response           (),                                        //              (terminated)
		.av_response            (2'b00),                                   //              (terminated)
		.uav_writeresponsevalid (),                                        //              (terminated)
		.av_writeresponsevalid  (1'b0)                                     //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_QOS_H                 (85),
		.PKT_QOS_L                 (85),
		.PKT_DATA_SIDEBAND_H       (83),
		.PKT_DATA_SIDEBAND_L       (83),
		.PKT_ADDR_SIDEBAND_H       (82),
		.PKT_ADDR_SIDEBAND_L       (82),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_CACHE_H               (99),
		.PKT_CACHE_L               (96),
		.PKT_THREAD_ID_H           (92),
		.PKT_THREAD_ID_L           (92),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_EXCLUSIVE       (70),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.ST_DATA_W                 (105),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_data_master_agent (
		.clk                   (clk_clk_clk),                                                        //       clk.clk
		.reset                 (cpu_reset_n_reset_bridge_in_reset_reset),                            // clk_reset.reset
		.av_address            (cpu_data_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_data_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_data_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_data_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_data_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_data_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_data_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_data_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_data_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_data_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_data_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_src_valid),                                                  //        rp.valid
		.rp_data               (rsp_mux_src_data),                                                   //          .data
		.rp_channel            (rsp_mux_src_channel),                                                //          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                          //          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                            //          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                  //          .ready
		.av_response           (),                                                                   // (terminated)
		.av_writeresponsevalid ()                                                                    // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_QOS_H                 (85),
		.PKT_QOS_L                 (85),
		.PKT_DATA_SIDEBAND_H       (83),
		.PKT_DATA_SIDEBAND_L       (83),
		.PKT_ADDR_SIDEBAND_H       (82),
		.PKT_ADDR_SIDEBAND_L       (82),
		.PKT_BURST_TYPE_H          (81),
		.PKT_BURST_TYPE_L          (80),
		.PKT_CACHE_H               (99),
		.PKT_CACHE_L               (96),
		.PKT_THREAD_ID_H           (92),
		.PKT_THREAD_ID_L           (92),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_EXCLUSIVE       (70),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.ST_DATA_W                 (105),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_instruction_master_agent (
		.clk                   (clk_clk_clk),                                                               //       clk.clk
		.reset                 (cpu_reset_n_reset_bridge_in_reset_reset),                                   // clk_reset.reset
		.av_address            (cpu_instruction_master_translator_avalon_universal_master_0_address),       //        av.address
		.av_write              (cpu_instruction_master_translator_avalon_universal_master_0_write),         //          .write
		.av_read               (cpu_instruction_master_translator_avalon_universal_master_0_read),          //          .read
		.av_writedata          (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //          .writedata
		.av_readdata           (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //          .readdata
		.av_waitrequest        (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
		.av_readdatavalid      (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
		.av_byteenable         (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
		.av_burstcount         (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
		.av_debugaccess        (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
		.av_lock               (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //          .lock
		.cp_valid              (cpu_instruction_master_agent_cp_valid),                                     //        cp.valid
		.cp_data               (cpu_instruction_master_agent_cp_data),                                      //          .data
		.cp_startofpacket      (cpu_instruction_master_agent_cp_startofpacket),                             //          .startofpacket
		.cp_endofpacket        (cpu_instruction_master_agent_cp_endofpacket),                               //          .endofpacket
		.cp_ready              (cpu_instruction_master_agent_cp_ready),                                     //          .ready
		.rp_valid              (rsp_mux_001_src_valid),                                                     //        rp.valid
		.rp_data               (rsp_mux_001_src_data),                                                      //          .data
		.rp_channel            (rsp_mux_001_src_channel),                                                   //          .channel
		.rp_startofpacket      (rsp_mux_001_src_startofpacket),                                             //          .startofpacket
		.rp_endofpacket        (rsp_mux_001_src_endofpacket),                                               //          .endofpacket
		.rp_ready              (rsp_mux_001_src_ready),                                                     //          .ready
		.av_response           (),                                                                          // (terminated)
		.av_writeresponsevalid ()                                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) jtag_uart_avalon_jtag_slave_agent (
		.clk                     (clk_clk_clk),                                                  //             clk.clk
		.reset                   (cpu_reset_n_reset_bridge_in_reset_reset),                      //       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                            //              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                            //                .valid
		.cp_data                 (cmd_mux_src_data),                                             //                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                          //                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                        //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                          //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                                  //       clk.clk
		.reset             (cpu_reset_n_reset_bridge_in_reset_reset),                      // clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated)
		.csr_read          (1'b0),                                                         // (terminated)
		.csr_write         (1'b0),                                                         // (terminated)
		.csr_readdata      (),                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated)
		.almost_full_data  (),                                                             // (terminated)
		.almost_empty_data (),                                                             // (terminated)
		.in_empty          (1'b0),                                                         // (terminated)
		.out_empty         (),                                                             // (terminated)
		.in_error          (1'b0),                                                         // (terminated)
		.out_error         (),                                                             // (terminated)
		.in_channel        (1'b0),                                                         // (terminated)
		.out_channel       ()                                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) cpu_jtag_debug_module_agent (
		.clk                     (clk_clk_clk),                                            //             clk.clk
		.reset                   (cpu_reset_n_reset_bridge_in_reset_reset),                //       clk_reset.reset
		.m0_address              (cpu_jtag_debug_module_agent_m0_address),                 //              m0.address
		.m0_burstcount           (cpu_jtag_debug_module_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (cpu_jtag_debug_module_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (cpu_jtag_debug_module_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (cpu_jtag_debug_module_agent_m0_lock),                    //                .lock
		.m0_readdata             (cpu_jtag_debug_module_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (cpu_jtag_debug_module_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (cpu_jtag_debug_module_agent_m0_read),                    //                .read
		.m0_waitrequest          (cpu_jtag_debug_module_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (cpu_jtag_debug_module_agent_m0_writedata),               //                .writedata
		.m0_write                (cpu_jtag_debug_module_agent_m0_write),                   //                .write
		.rp_endofpacket          (cpu_jtag_debug_module_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (cpu_jtag_debug_module_agent_rp_ready),                   //                .ready
		.rp_valid                (cpu_jtag_debug_module_agent_rp_valid),                   //                .valid
		.rp_data                 (cpu_jtag_debug_module_agent_rp_data),                    //                .data
		.rp_startofpacket        (cpu_jtag_debug_module_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                  //              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                  //                .valid
		.cp_data                 (cmd_mux_001_src_data),                                   //                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                          //                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                            //                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                //                .channel
		.rf_sink_ready           (cpu_jtag_debug_module_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (cpu_jtag_debug_module_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (cpu_jtag_debug_module_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (cpu_jtag_debug_module_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (cpu_jtag_debug_module_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (cpu_jtag_debug_module_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (cpu_jtag_debug_module_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (cpu_jtag_debug_module_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (cpu_jtag_debug_module_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (cpu_jtag_debug_module_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (cpu_jtag_debug_module_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (cpu_jtag_debug_module_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (cpu_jtag_debug_module_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                  //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                    //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) cpu_jtag_debug_module_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                            //       clk.clk
		.reset             (cpu_reset_n_reset_bridge_in_reset_reset),                // clk_reset.reset
		.in_data           (cpu_jtag_debug_module_agent_rf_source_data),             //        in.data
		.in_valid          (cpu_jtag_debug_module_agent_rf_source_valid),            //          .valid
		.in_ready          (cpu_jtag_debug_module_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (cpu_jtag_debug_module_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (cpu_jtag_debug_module_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (cpu_jtag_debug_module_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (cpu_jtag_debug_module_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (cpu_jtag_debug_module_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                  // (terminated)
		.csr_read          (1'b0),                                                   // (terminated)
		.csr_write         (1'b0),                                                   // (terminated)
		.csr_readdata      (),                                                       // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated)
		.almost_full_data  (),                                                       // (terminated)
		.almost_empty_data (),                                                       // (terminated)
		.in_empty          (1'b0),                                                   // (terminated)
		.out_empty         (),                                                       // (terminated)
		.in_error          (1'b0),                                                   // (terminated)
		.out_error         (),                                                       // (terminated)
		.in_channel        (1'b0),                                                   // (terminated)
		.out_channel       ()                                                        // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) clocks_pll_slave_agent (
		.clk                     (clk_clk_clk),                                       //             clk.clk
		.reset                   (cpu_reset_n_reset_bridge_in_reset_reset),           //       clk_reset.reset
		.m0_address              (clocks_pll_slave_agent_m0_address),                 //              m0.address
		.m0_burstcount           (clocks_pll_slave_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (clocks_pll_slave_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (clocks_pll_slave_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (clocks_pll_slave_agent_m0_lock),                    //                .lock
		.m0_readdata             (clocks_pll_slave_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (clocks_pll_slave_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (clocks_pll_slave_agent_m0_read),                    //                .read
		.m0_waitrequest          (clocks_pll_slave_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (clocks_pll_slave_agent_m0_writedata),               //                .writedata
		.m0_write                (clocks_pll_slave_agent_m0_write),                   //                .write
		.rp_endofpacket          (clocks_pll_slave_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (clocks_pll_slave_agent_rp_ready),                   //                .ready
		.rp_valid                (clocks_pll_slave_agent_rp_valid),                   //                .valid
		.rp_data                 (clocks_pll_slave_agent_rp_data),                    //                .data
		.rp_startofpacket        (clocks_pll_slave_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                             //              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                             //                .valid
		.cp_data                 (cmd_mux_002_src_data),                              //                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                     //                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                       //                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                           //                .channel
		.rf_sink_ready           (clocks_pll_slave_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (clocks_pll_slave_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (clocks_pll_slave_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (clocks_pll_slave_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (clocks_pll_slave_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (clocks_pll_slave_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (clocks_pll_slave_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (clocks_pll_slave_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (clocks_pll_slave_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (clocks_pll_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (clocks_pll_slave_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (clocks_pll_slave_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (clocks_pll_slave_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (clocks_pll_slave_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                             //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                               //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) clocks_pll_slave_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                       //       clk.clk
		.reset             (cpu_reset_n_reset_bridge_in_reset_reset),           // clk_reset.reset
		.in_data           (clocks_pll_slave_agent_rf_source_data),             //        in.data
		.in_valid          (clocks_pll_slave_agent_rf_source_valid),            //          .valid
		.in_ready          (clocks_pll_slave_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (clocks_pll_slave_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (clocks_pll_slave_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (clocks_pll_slave_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (clocks_pll_slave_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (clocks_pll_slave_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (clocks_pll_slave_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                             // (terminated)
		.csr_read          (1'b0),                                              // (terminated)
		.csr_write         (1'b0),                                              // (terminated)
		.csr_readdata      (),                                                  // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated)
		.almost_full_data  (),                                                  // (terminated)
		.almost_empty_data (),                                                  // (terminated)
		.in_empty          (1'b0),                                              // (terminated)
		.out_empty         (),                                                  // (terminated)
		.in_error          (1'b0),                                              // (terminated)
		.out_error         (),                                                  // (terminated)
		.in_channel        (1'b0),                                              // (terminated)
		.out_channel       ()                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) clock_crossing_io_s0_agent (
		.clk                     (clk_clk_clk),                                           //             clk.clk
		.reset                   (cpu_reset_n_reset_bridge_in_reset_reset),               //       clk_reset.reset
		.m0_address              (clock_crossing_io_s0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (clock_crossing_io_s0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (clock_crossing_io_s0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (clock_crossing_io_s0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (clock_crossing_io_s0_agent_m0_lock),                    //                .lock
		.m0_readdata             (clock_crossing_io_s0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (clock_crossing_io_s0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (clock_crossing_io_s0_agent_m0_read),                    //                .read
		.m0_waitrequest          (clock_crossing_io_s0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (clock_crossing_io_s0_agent_m0_writedata),               //                .writedata
		.m0_write                (clock_crossing_io_s0_agent_m0_write),                   //                .write
		.rp_endofpacket          (clock_crossing_io_s0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (clock_crossing_io_s0_agent_rp_ready),                   //                .ready
		.rp_valid                (clock_crossing_io_s0_agent_rp_valid),                   //                .valid
		.rp_data                 (clock_crossing_io_s0_agent_rp_data),                    //                .data
		.rp_startofpacket        (clock_crossing_io_s0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                 //              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                 //                .valid
		.cp_data                 (cmd_mux_003_src_data),                                  //                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                         //                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                           //                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                               //                .channel
		.rf_sink_ready           (clock_crossing_io_s0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (clock_crossing_io_s0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (clock_crossing_io_s0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (clock_crossing_io_s0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (clock_crossing_io_s0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (clock_crossing_io_s0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (clock_crossing_io_s0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (clock_crossing_io_s0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (clock_crossing_io_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (clock_crossing_io_s0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (clock_crossing_io_s0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (clock_crossing_io_s0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (clock_crossing_io_s0_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                                 //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                                   //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (129),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) clock_crossing_io_s0_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                           //       clk.clk
		.reset             (cpu_reset_n_reset_bridge_in_reset_reset),               // clk_reset.reset
		.in_data           (clock_crossing_io_s0_agent_rf_source_data),             //        in.data
		.in_valid          (clock_crossing_io_s0_agent_rf_source_valid),            //          .valid
		.in_ready          (clock_crossing_io_s0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (clock_crossing_io_s0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (clock_crossing_io_s0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (clock_crossing_io_s0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (clock_crossing_io_s0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (clock_crossing_io_s0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                 // (terminated)
		.csr_read          (1'b0),                                                  // (terminated)
		.csr_write         (1'b0),                                                  // (terminated)
		.csr_readdata      (),                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                  // (terminated)
		.almost_full_data  (),                                                      // (terminated)
		.almost_empty_data (),                                                      // (terminated)
		.in_empty          (1'b0),                                                  // (terminated)
		.out_empty         (),                                                      // (terminated)
		.in_error          (1'b0),                                                  // (terminated)
		.out_error         (),                                                      // (terminated)
		.in_channel        (1'b0),                                                  // (terminated)
		.out_channel       ()                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) keycode_s1_agent (
		.clk                     (clk_clk_clk),                                 //             clk.clk
		.reset                   (cpu_reset_n_reset_bridge_in_reset_reset),     //       clk_reset.reset
		.m0_address              (keycode_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (keycode_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (keycode_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (keycode_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (keycode_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (keycode_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (keycode_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (keycode_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (keycode_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (keycode_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (keycode_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (keycode_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (keycode_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (keycode_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (keycode_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (keycode_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_004_src_ready),                       //              cp.ready
		.cp_valid                (cmd_mux_004_src_valid),                       //                .valid
		.cp_data                 (cmd_mux_004_src_data),                        //                .data
		.cp_startofpacket        (cmd_mux_004_src_startofpacket),               //                .startofpacket
		.cp_endofpacket          (cmd_mux_004_src_endofpacket),                 //                .endofpacket
		.cp_channel              (cmd_mux_004_src_channel),                     //                .channel
		.rf_sink_ready           (keycode_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (keycode_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (keycode_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (keycode_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (keycode_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (keycode_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (keycode_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (keycode_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (keycode_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (keycode_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (keycode_s1_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (keycode_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (keycode_s1_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (keycode_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (keycode_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (keycode_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                       //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                         //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) keycode_s1_agent_rsp_fifo (
		.clk               (clk_clk_clk),                                 //       clk.clk
		.reset             (cpu_reset_n_reset_bridge_in_reset_reset),     // clk_reset.reset
		.in_data           (keycode_s1_agent_rf_source_data),             //        in.data
		.in_valid          (keycode_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (keycode_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (keycode_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (keycode_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (keycode_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (keycode_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (keycode_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (keycode_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                       // (terminated)
		.csr_read          (1'b0),                                        // (terminated)
		.csr_write         (1'b0),                                        // (terminated)
		.csr_readdata      (),                                            // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated)
		.almost_full_data  (),                                            // (terminated)
		.almost_empty_data (),                                            // (terminated)
		.in_empty          (1'b0),                                        // (terminated)
		.out_empty         (),                                            // (terminated)
		.in_error          (1'b0),                                        // (terminated)
		.out_error         (),                                            // (terminated)
		.in_channel        (1'b0),                                        // (terminated)
		.out_channel       ()                                             // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_ORI_BURST_SIZE_H      (104),
		.PKT_ORI_BURST_SIZE_L      (102),
		.PKT_RESPONSE_STATUS_H     (101),
		.PKT_RESPONSE_STATUS_L     (100),
		.PKT_BURST_SIZE_H          (79),
		.PKT_BURST_SIZE_L          (77),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (84),
		.PKT_PROTECTION_H          (95),
		.PKT_PROTECTION_L          (93),
		.PKT_BURSTWRAP_H           (76),
		.PKT_BURSTWRAP_L           (74),
		.PKT_BYTE_CNT_H            (73),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (88),
		.PKT_SRC_ID_L              (86),
		.PKT_DEST_ID_H             (91),
		.PKT_DEST_ID_L             (89),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (105),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0)
	) sdram_s1_agent (
		.clk                     (clocks_c0_clk),                             //             clk.clk
		.reset                   (sdram_reset_reset_bridge_in_reset_reset),   //       clk_reset.reset
		.m0_address              (sdram_s1_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sdram_s1_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sdram_s1_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sdram_s1_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sdram_s1_agent_m0_lock),                    //                .lock
		.m0_readdata             (sdram_s1_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sdram_s1_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sdram_s1_agent_m0_read),                    //                .read
		.m0_waitrequest          (sdram_s1_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sdram_s1_agent_m0_writedata),               //                .writedata
		.m0_write                (sdram_s1_agent_m0_write),                   //                .write
		.rp_endofpacket          (sdram_s1_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sdram_s1_agent_rp_ready),                   //                .ready
		.rp_valid                (sdram_s1_agent_rp_valid),                   //                .valid
		.rp_data                 (sdram_s1_agent_rp_data),                    //                .data
		.rp_startofpacket        (sdram_s1_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_mux_005_src_ready),                     //              cp.ready
		.cp_valid                (cmd_mux_005_src_valid),                     //                .valid
		.cp_data                 (cmd_mux_005_src_data),                      //                .data
		.cp_startofpacket        (cmd_mux_005_src_startofpacket),             //                .startofpacket
		.cp_endofpacket          (cmd_mux_005_src_endofpacket),               //                .endofpacket
		.cp_channel              (cmd_mux_005_src_channel),                   //                .channel
		.rf_sink_ready           (sdram_s1_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sdram_s1_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sdram_s1_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sdram_s1_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sdram_s1_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sdram_s1_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sdram_s1_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sdram_s1_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sdram_s1_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sdram_s1_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sdram_s1_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (sdram_s1_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (sdram_s1_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sdram_s1_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sdram_s1_agent_rdata_fifo_src_data),        //                .data
		.m0_response             (2'b00),                                     //     (terminated)
		.m0_writeresponsevalid   (1'b0)                                       //     (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (106),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sdram_s1_agent_rsp_fifo (
		.clk               (clocks_c0_clk),                             //       clk.clk
		.reset             (sdram_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
		.in_data           (sdram_s1_agent_rf_source_data),             //        in.data
		.in_valid          (sdram_s1_agent_rf_source_valid),            //          .valid
		.in_ready          (sdram_s1_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sdram_s1_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sdram_s1_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sdram_s1_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sdram_s1_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sdram_s1_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sdram_s1_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                     // (terminated)
		.csr_read          (1'b0),                                      // (terminated)
		.csr_write         (1'b0),                                      // (terminated)
		.csr_readdata      (),                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),      // (terminated)
		.almost_full_data  (),                                          // (terminated)
		.almost_empty_data (),                                          // (terminated)
		.in_empty          (1'b0),                                      // (terminated)
		.out_empty         (),                                          // (terminated)
		.in_error          (1'b0),                                      // (terminated)
		.out_error         (),                                          // (terminated)
		.in_channel        (1'b0),                                      // (terminated)
		.out_channel       ()                                           // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (8),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sdram_s1_agent_rdata_fifo (
		.clk               (clocks_c0_clk),                           //       clk.clk
		.reset             (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.in_data           (sdram_s1_agent_rdata_fifo_src_data),      //        in.data
		.in_valid          (sdram_s1_agent_rdata_fifo_src_valid),     //          .valid
		.in_ready          (sdram_s1_agent_rdata_fifo_src_ready),     //          .ready
		.out_data          (sdram_s1_agent_rdata_fifo_out_data),      //       out.data
		.out_valid         (sdram_s1_agent_rdata_fifo_out_valid),     //          .valid
		.out_ready         (sdram_s1_agent_rdata_fifo_out_ready),     //          .ready
		.csr_address       (2'b00),                                   // (terminated)
		.csr_read          (1'b0),                                    // (terminated)
		.csr_write         (1'b0),                                    // (terminated)
		.csr_readdata      (),                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),    // (terminated)
		.almost_full_data  (),                                        // (terminated)
		.almost_empty_data (),                                        // (terminated)
		.in_startofpacket  (1'b0),                                    // (terminated)
		.in_endofpacket    (1'b0),                                    // (terminated)
		.out_startofpacket (),                                        // (terminated)
		.out_endofpacket   (),                                        // (terminated)
		.in_empty          (1'b0),                                    // (terminated)
		.out_empty         (),                                        // (terminated)
		.in_error          (1'b0),                                    // (terminated)
		.out_error         (),                                        // (terminated)
		.in_channel        (1'b0),                                    // (terminated)
		.out_channel       ()                                         // (terminated)
	);

	finalproject_mm_interconnect_0_router router (
		.sink_ready         (cpu_data_master_agent_cp_ready),          //      sink.ready
		.sink_valid         (cpu_data_master_agent_cp_valid),          //          .valid
		.sink_data          (cpu_data_master_agent_cp_data),           //          .data
		.sink_startofpacket (cpu_data_master_agent_cp_startofpacket),  //          .startofpacket
		.sink_endofpacket   (cpu_data_master_agent_cp_endofpacket),    //          .endofpacket
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_src_ready),                        //       src.ready
		.src_valid          (router_src_valid),                        //          .valid
		.src_data           (router_src_data),                         //          .data
		.src_channel        (router_src_channel),                      //          .channel
		.src_startofpacket  (router_src_startofpacket),                //          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                   //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_001 router_001 (
		.sink_ready         (cpu_instruction_master_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_instruction_master_agent_cp_valid),         //          .valid
		.sink_data          (cpu_instruction_master_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_instruction_master_agent_cp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                   //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset),       // clk_reset.reset
		.src_ready          (router_001_src_ready),                          //       src.ready
		.src_valid          (router_001_src_valid),                          //          .valid
		.src_data           (router_001_src_data),                           //          .data
		.src_channel        (router_001_src_channel),                        //          .channel
		.src_startofpacket  (router_001_src_startofpacket),                  //          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                     //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_002 router_002 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),         //          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),          //          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                        //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset),            // clk_reset.reset
		.src_ready          (router_002_src_ready),                               //       src.ready
		.src_valid          (router_002_src_valid),                               //          .valid
		.src_data           (router_002_src_data),                                //          .data
		.src_channel        (router_002_src_channel),                             //          .channel
		.src_startofpacket  (router_002_src_startofpacket),                       //          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                          //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_003 router_003 (
		.sink_ready         (cpu_jtag_debug_module_agent_rp_ready),         //      sink.ready
		.sink_valid         (cpu_jtag_debug_module_agent_rp_valid),         //          .valid
		.sink_data          (cpu_jtag_debug_module_agent_rp_data),          //          .data
		.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_jtag_debug_module_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                  //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset),      // clk_reset.reset
		.src_ready          (router_003_src_ready),                         //       src.ready
		.src_valid          (router_003_src_valid),                         //          .valid
		.src_data           (router_003_src_data),                          //          .data
		.src_channel        (router_003_src_channel),                       //          .channel
		.src_startofpacket  (router_003_src_startofpacket),                 //          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                    //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_003 router_004 (
		.sink_ready         (clocks_pll_slave_agent_rp_ready),         //      sink.ready
		.sink_valid         (clocks_pll_slave_agent_rp_valid),         //          .valid
		.sink_data          (clocks_pll_slave_agent_rp_data),          //          .data
		.sink_startofpacket (clocks_pll_slave_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (clocks_pll_slave_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_004_src_ready),                    //       src.ready
		.src_valid          (router_004_src_valid),                    //          .valid
		.src_data           (router_004_src_data),                     //          .data
		.src_channel        (router_004_src_channel),                  //          .channel
		.src_startofpacket  (router_004_src_startofpacket),            //          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_002 router_005 (
		.sink_ready         (clock_crossing_io_s0_agent_rp_ready),         //      sink.ready
		.sink_valid         (clock_crossing_io_s0_agent_rp_valid),         //          .valid
		.sink_data          (clock_crossing_io_s0_agent_rp_data),          //          .data
		.sink_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (clock_crossing_io_s0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk_clk_clk),                                 //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset),     // clk_reset.reset
		.src_ready          (router_005_src_ready),                        //       src.ready
		.src_valid          (router_005_src_valid),                        //          .valid
		.src_data           (router_005_src_data),                         //          .data
		.src_channel        (router_005_src_channel),                      //          .channel
		.src_startofpacket  (router_005_src_startofpacket),                //          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                   //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_002 router_006 (
		.sink_ready         (keycode_s1_agent_rp_ready),               //      sink.ready
		.sink_valid         (keycode_s1_agent_rp_valid),               //          .valid
		.sink_data          (keycode_s1_agent_rp_data),                //          .data
		.sink_startofpacket (keycode_s1_agent_rp_startofpacket),       //          .startofpacket
		.sink_endofpacket   (keycode_s1_agent_rp_endofpacket),         //          .endofpacket
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_006_src_ready),                    //       src.ready
		.src_valid          (router_006_src_valid),                    //          .valid
		.src_data           (router_006_src_data),                     //          .data
		.src_channel        (router_006_src_channel),                  //          .channel
		.src_startofpacket  (router_006_src_startofpacket),            //          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_router_003 router_007 (
		.sink_ready         (sdram_s1_agent_rp_ready),                 //      sink.ready
		.sink_valid         (sdram_s1_agent_rp_valid),                 //          .valid
		.sink_data          (sdram_s1_agent_rp_data),                  //          .data
		.sink_startofpacket (sdram_s1_agent_rp_startofpacket),         //          .startofpacket
		.sink_endofpacket   (sdram_s1_agent_rp_endofpacket),           //          .endofpacket
		.clk                (clocks_c0_clk),                           //       clk.clk
		.reset              (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready          (router_007_src_ready),                    //       src.ready
		.src_valid          (router_007_src_valid),                    //          .valid
		.src_data           (router_007_src_data),                     //          .data
		.src_channel        (router_007_src_channel),                  //          .channel
		.src_startofpacket  (router_007_src_startofpacket),            //          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_demux cmd_demux (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_src_ready),                        //      sink.ready
		.sink_channel       (router_src_channel),                      //          .channel
		.sink_data          (router_src_data),                         //          .data
		.sink_startofpacket (router_src_startofpacket),                //          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                  //          .endofpacket
		.sink_valid         (router_src_valid),                        //          .valid
		.src0_ready         (cmd_demux_src0_ready),                    //      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                    //          .valid
		.src0_data          (cmd_demux_src0_data),                     //          .data
		.src0_channel       (cmd_demux_src0_channel),                  //          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),            //          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),              //          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                    //      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                    //          .valid
		.src1_data          (cmd_demux_src1_data),                     //          .data
		.src1_channel       (cmd_demux_src1_channel),                  //          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),            //          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),              //          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                    //      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                    //          .valid
		.src2_data          (cmd_demux_src2_data),                     //          .data
		.src2_channel       (cmd_demux_src2_channel),                  //          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),            //          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),              //          .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                    //      src3.ready
		.src3_valid         (cmd_demux_src3_valid),                    //          .valid
		.src3_data          (cmd_demux_src3_data),                     //          .data
		.src3_channel       (cmd_demux_src3_channel),                  //          .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),            //          .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket),              //          .endofpacket
		.src4_ready         (cmd_demux_src4_ready),                    //      src4.ready
		.src4_valid         (cmd_demux_src4_valid),                    //          .valid
		.src4_data          (cmd_demux_src4_data),                     //          .data
		.src4_channel       (cmd_demux_src4_channel),                  //          .channel
		.src4_startofpacket (cmd_demux_src4_startofpacket),            //          .startofpacket
		.src4_endofpacket   (cmd_demux_src4_endofpacket),              //          .endofpacket
		.src5_ready         (cmd_demux_src5_ready),                    //      src5.ready
		.src5_valid         (cmd_demux_src5_valid),                    //          .valid
		.src5_data          (cmd_demux_src5_data),                     //          .data
		.src5_channel       (cmd_demux_src5_channel),                  //          .channel
		.src5_startofpacket (cmd_demux_src5_startofpacket),            //          .startofpacket
		.src5_endofpacket   (cmd_demux_src5_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_001_src_ready),                    //      sink.ready
		.sink_channel       (router_001_src_channel),                  //          .channel
		.sink_data          (router_001_src_data),                     //          .data
		.sink_startofpacket (router_001_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_001_src_valid),                    //          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                //      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                //          .valid
		.src0_data          (cmd_demux_001_src0_data),                 //          .data
		.src0_channel       (cmd_demux_001_src0_channel),              //          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),          //          .endofpacket
		.src1_ready         (cmd_demux_001_src1_ready),                //      src1.ready
		.src1_valid         (cmd_demux_001_src1_valid),                //          .valid
		.src1_data          (cmd_demux_001_src1_data),                 //          .data
		.src1_channel       (cmd_demux_001_src1_channel),              //          .channel
		.src1_startofpacket (cmd_demux_001_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),          //          .endofpacket
		.src2_ready         (cmd_demux_001_src2_ready),                //      src2.ready
		.src2_valid         (cmd_demux_001_src2_valid),                //          .valid
		.src2_data          (cmd_demux_001_src2_data),                 //          .data
		.src2_channel       (cmd_demux_001_src2_channel),              //          .channel
		.src2_startofpacket (cmd_demux_001_src2_startofpacket),        //          .startofpacket
		.src2_endofpacket   (cmd_demux_001_src2_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux cmd_mux (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                       //       src.ready
		.src_valid           (cmd_mux_src_valid),                       //          .valid
		.src_data            (cmd_mux_src_data),                        //          .data
		.src_channel         (cmd_mux_src_channel),                     //          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),               //          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                 //          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                    //     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                    //          .valid
		.sink0_channel       (cmd_demux_src0_channel),                  //          .channel
		.sink0_data          (cmd_demux_src0_data),                     //          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                   //       src.ready
		.src_valid           (cmd_mux_001_src_valid),                   //          .valid
		.src_data            (cmd_mux_001_src_data),                    //          .data
		.src_channel         (cmd_mux_001_src_channel),                 //          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                    //     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                    //          .valid
		.sink0_channel       (cmd_demux_src1_channel),                  //          .channel
		.sink0_data          (cmd_demux_src1_data),                     //          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket),              //          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                //     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                //          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),              //          .channel
		.sink1_data          (cmd_demux_001_src0_data),                 //          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                   //       src.ready
		.src_valid           (cmd_mux_002_src_valid),                   //          .valid
		.src_data            (cmd_mux_002_src_data),                    //          .data
		.src_channel         (cmd_mux_002_src_channel),                 //          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                    //     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                    //          .valid
		.sink0_channel       (cmd_demux_src2_channel),                  //          .channel
		.sink0_data          (cmd_demux_src2_data),                     //          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket),              //          .endofpacket
		.sink1_ready         (cmd_demux_001_src1_ready),                //     sink1.ready
		.sink1_valid         (cmd_demux_001_src1_valid),                //          .valid
		.sink1_channel       (cmd_demux_001_src1_channel),              //          .channel
		.sink1_data          (cmd_demux_001_src1_data),                 //          .data
		.sink1_startofpacket (cmd_demux_001_src1_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src1_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux cmd_mux_003 (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                   //       src.ready
		.src_valid           (cmd_mux_003_src_valid),                   //          .valid
		.src_data            (cmd_mux_003_src_data),                    //          .data
		.src_channel         (cmd_mux_003_src_channel),                 //          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                    //     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                    //          .valid
		.sink0_channel       (cmd_demux_src3_channel),                  //          .channel
		.sink0_data          (cmd_demux_src3_data),                     //          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux cmd_mux_004 (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                   //       src.ready
		.src_valid           (cmd_mux_004_src_valid),                   //          .valid
		.src_data            (cmd_mux_004_src_data),                    //          .data
		.src_channel         (cmd_mux_004_src_channel),                 //          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),             //          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                    //     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                    //          .valid
		.sink0_channel       (cmd_demux_src4_channel),                  //          .channel
		.sink0_data          (cmd_demux_src4_data),                     //          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_005 (
		.clk                 (clocks_c0_clk),                           //       clk.clk
		.reset               (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                   //       src.ready
		.src_valid           (cmd_mux_005_src_valid),                   //          .valid
		.src_data            (cmd_mux_005_src_data),                    //          .data
		.src_channel         (cmd_mux_005_src_channel),                 //          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),             //          .endofpacket
		.sink0_ready         (crosser_out_ready),                       //     sink0.ready
		.sink0_valid         (crosser_out_valid),                       //          .valid
		.sink0_channel       (crosser_out_channel),                     //          .channel
		.sink0_data          (crosser_out_data),                        //          .data
		.sink0_startofpacket (crosser_out_startofpacket),               //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket),                 //          .endofpacket
		.sink1_ready         (crosser_001_out_ready),                   //     sink1.ready
		.sink1_valid         (crosser_001_out_valid),                   //          .valid
		.sink1_channel       (crosser_001_out_channel),                 //          .channel
		.sink1_data          (crosser_001_out_data),                    //          .data
		.sink1_startofpacket (crosser_001_out_startofpacket),           //          .startofpacket
		.sink1_endofpacket   (crosser_001_out_endofpacket)              //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux rsp_demux (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_002_src_ready),                    //      sink.ready
		.sink_channel       (router_002_src_channel),                  //          .channel
		.sink_data          (router_002_src_data),                     //          .data
		.sink_startofpacket (router_002_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_002_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_src0_ready),                    //      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                    //          .valid
		.src0_data          (rsp_demux_src0_data),                     //          .data
		.src0_channel       (rsp_demux_src0_channel),                  //          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),            //          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)               //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_003_src_ready),                    //      sink.ready
		.sink_channel       (router_003_src_channel),                  //          .channel
		.sink_data          (router_003_src_data),                     //          .data
		.sink_startofpacket (router_003_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_003_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                //      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                //          .valid
		.src0_data          (rsp_demux_001_src0_data),                 //          .data
		.src0_channel       (rsp_demux_001_src0_channel),              //          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),          //          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                //      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                //          .valid
		.src1_data          (rsp_demux_001_src1_data),                 //          .data
		.src1_channel       (rsp_demux_001_src1_channel),              //          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_004_src_ready),                    //      sink.ready
		.sink_channel       (router_004_src_channel),                  //          .channel
		.sink_data          (router_004_src_data),                     //          .data
		.sink_startofpacket (router_004_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_004_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                //      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                //          .valid
		.src0_data          (rsp_demux_002_src0_data),                 //          .data
		.src0_channel       (rsp_demux_002_src0_channel),              //          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),          //          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                //      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                //          .valid
		.src1_data          (rsp_demux_002_src1_data),                 //          .data
		.src1_channel       (rsp_demux_002_src1_channel),              //          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux rsp_demux_003 (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_005_src_ready),                    //      sink.ready
		.sink_channel       (router_005_src_channel),                  //          .channel
		.sink_data          (router_005_src_data),                     //          .data
		.sink_startofpacket (router_005_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_005_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                //      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                //          .valid
		.src0_data          (rsp_demux_003_src0_data),                 //          .data
		.src0_channel       (rsp_demux_003_src0_channel),              //          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux rsp_demux_004 (
		.clk                (clk_clk_clk),                             //       clk.clk
		.reset              (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_006_src_ready),                    //      sink.ready
		.sink_channel       (router_006_src_channel),                  //          .channel
		.sink_data          (router_006_src_data),                     //          .data
		.sink_startofpacket (router_006_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_006_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                //      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                //          .valid
		.src0_data          (rsp_demux_004_src0_data),                 //          .data
		.src0_channel       (rsp_demux_004_src0_channel),              //          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_005 (
		.clk                (clocks_c0_clk),                           //       clk.clk
		.reset              (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
		.sink_ready         (router_007_src_ready),                    //      sink.ready
		.sink_channel       (router_007_src_channel),                  //          .channel
		.sink_data          (router_007_src_data),                     //          .data
		.sink_startofpacket (router_007_src_startofpacket),            //          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),              //          .endofpacket
		.sink_valid         (router_007_src_valid),                    //          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                //      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                //          .valid
		.src0_data          (rsp_demux_005_src0_data),                 //          .data
		.src0_channel       (rsp_demux_005_src0_channel),              //          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),        //          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket),          //          .endofpacket
		.src1_ready         (rsp_demux_005_src1_ready),                //      src1.ready
		.src1_valid         (rsp_demux_005_src1_valid),                //          .valid
		.src1_data          (rsp_demux_005_src1_data),                 //          .data
		.src1_channel       (rsp_demux_005_src1_channel),              //          .channel
		.src1_startofpacket (rsp_demux_005_src1_startofpacket),        //          .startofpacket
		.src1_endofpacket   (rsp_demux_005_src1_endofpacket)           //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_mux rsp_mux (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                       //       src.ready
		.src_valid           (rsp_mux_src_valid),                       //          .valid
		.src_data            (rsp_mux_src_data),                        //          .data
		.src_channel         (rsp_mux_src_channel),                     //          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),               //          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                 //          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                    //     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                    //          .valid
		.sink0_channel       (rsp_demux_src0_channel),                  //          .channel
		.sink0_data          (rsp_demux_src0_data),                     //          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),            //          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),              //          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                //     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                //          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),              //          .channel
		.sink1_data          (rsp_demux_001_src0_data),                 //          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),          //          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                //     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                //          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),              //          .channel
		.sink2_data          (rsp_demux_002_src0_data),                 //          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),        //          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),          //          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                //     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                //          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),              //          .channel
		.sink3_data          (rsp_demux_003_src0_data),                 //          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),        //          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket),          //          .endofpacket
		.sink4_ready         (rsp_demux_004_src0_ready),                //     sink4.ready
		.sink4_valid         (rsp_demux_004_src0_valid),                //          .valid
		.sink4_channel       (rsp_demux_004_src0_channel),              //          .channel
		.sink4_data          (rsp_demux_004_src0_data),                 //          .data
		.sink4_startofpacket (rsp_demux_004_src0_startofpacket),        //          .startofpacket
		.sink4_endofpacket   (rsp_demux_004_src0_endofpacket),          //          .endofpacket
		.sink5_ready         (crosser_002_out_ready),                   //     sink5.ready
		.sink5_valid         (crosser_002_out_valid),                   //          .valid
		.sink5_channel       (crosser_002_out_channel),                 //          .channel
		.sink5_data          (crosser_002_out_data),                    //          .data
		.sink5_startofpacket (crosser_002_out_startofpacket),           //          .startofpacket
		.sink5_endofpacket   (crosser_002_out_endofpacket)              //          .endofpacket
	);

	finalproject_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
		.clk                 (clk_clk_clk),                             //       clk.clk
		.reset               (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                   //       src.ready
		.src_valid           (rsp_mux_001_src_valid),                   //          .valid
		.src_data            (rsp_mux_001_src_data),                    //          .data
		.src_channel         (rsp_mux_001_src_channel),                 //          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),           //          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),             //          .endofpacket
		.sink0_ready         (rsp_demux_001_src1_ready),                //     sink0.ready
		.sink0_valid         (rsp_demux_001_src1_valid),                //          .valid
		.sink0_channel       (rsp_demux_001_src1_channel),              //          .channel
		.sink0_data          (rsp_demux_001_src1_data),                 //          .data
		.sink0_startofpacket (rsp_demux_001_src1_startofpacket),        //          .startofpacket
		.sink0_endofpacket   (rsp_demux_001_src1_endofpacket),          //          .endofpacket
		.sink1_ready         (rsp_demux_002_src1_ready),                //     sink1.ready
		.sink1_valid         (rsp_demux_002_src1_valid),                //          .valid
		.sink1_channel       (rsp_demux_002_src1_channel),              //          .channel
		.sink1_data          (rsp_demux_002_src1_data),                 //          .data
		.sink1_startofpacket (rsp_demux_002_src1_startofpacket),        //          .startofpacket
		.sink1_endofpacket   (rsp_demux_002_src1_endofpacket),          //          .endofpacket
		.sink2_ready         (crosser_003_out_ready),                   //     sink2.ready
		.sink2_valid         (crosser_003_out_valid),                   //          .valid
		.sink2_channel       (crosser_003_out_channel),                 //          .channel
		.sink2_data          (crosser_003_out_data),                    //          .data
		.sink2_startofpacket (crosser_003_out_startofpacket),           //          .startofpacket
		.sink2_endofpacket   (crosser_003_out_endofpacket)              //          .endofpacket
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (105),
		.BITS_PER_SYMBOL     (105),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (clk_clk_clk),                             //        in_clk.clk
		.in_reset          (cpu_reset_n_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clocks_c0_clk),                           //       out_clk.clk
		.out_reset         (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_src5_ready),                    //            in.ready
		.in_valid          (cmd_demux_src5_valid),                    //              .valid
		.in_startofpacket  (cmd_demux_src5_startofpacket),            //              .startofpacket
		.in_endofpacket    (cmd_demux_src5_endofpacket),              //              .endofpacket
		.in_channel        (cmd_demux_src5_channel),                  //              .channel
		.in_data           (cmd_demux_src5_data),                     //              .data
		.out_ready         (crosser_out_ready),                       //           out.ready
		.out_valid         (crosser_out_valid),                       //              .valid
		.out_startofpacket (crosser_out_startofpacket),               //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                 //              .endofpacket
		.out_channel       (crosser_out_channel),                     //              .channel
		.out_data          (crosser_out_data),                        //              .data
		.in_empty          (1'b0),                                    //   (terminated)
		.in_error          (1'b0),                                    //   (terminated)
		.out_empty         (),                                        //   (terminated)
		.out_error         ()                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (105),
		.BITS_PER_SYMBOL     (105),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk_clk_clk),                             //        in_clk.clk
		.in_reset          (cpu_reset_n_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clocks_c0_clk),                           //       out_clk.clk
		.out_reset         (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (cmd_demux_001_src2_ready),                //            in.ready
		.in_valid          (cmd_demux_001_src2_valid),                //              .valid
		.in_startofpacket  (cmd_demux_001_src2_startofpacket),        //              .startofpacket
		.in_endofpacket    (cmd_demux_001_src2_endofpacket),          //              .endofpacket
		.in_channel        (cmd_demux_001_src2_channel),              //              .channel
		.in_data           (cmd_demux_001_src2_data),                 //              .data
		.out_ready         (crosser_001_out_ready),                   //           out.ready
		.out_valid         (crosser_001_out_valid),                   //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),           //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),             //              .endofpacket
		.out_channel       (crosser_001_out_channel),                 //              .channel
		.out_data          (crosser_001_out_data),                    //              .data
		.in_empty          (1'b0),                                    //   (terminated)
		.in_error          (1'b0),                                    //   (terminated)
		.out_empty         (),                                        //   (terminated)
		.out_error         ()                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (105),
		.BITS_PER_SYMBOL     (105),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_002 (
		.in_clk            (clocks_c0_clk),                           //        in_clk.clk
		.in_reset          (sdram_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                             //       out_clk.clk
		.out_reset         (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_demux_005_src0_ready),                //            in.ready
		.in_valid          (rsp_demux_005_src0_valid),                //              .valid
		.in_startofpacket  (rsp_demux_005_src0_startofpacket),        //              .startofpacket
		.in_endofpacket    (rsp_demux_005_src0_endofpacket),          //              .endofpacket
		.in_channel        (rsp_demux_005_src0_channel),              //              .channel
		.in_data           (rsp_demux_005_src0_data),                 //              .data
		.out_ready         (crosser_002_out_ready),                   //           out.ready
		.out_valid         (crosser_002_out_valid),                   //              .valid
		.out_startofpacket (crosser_002_out_startofpacket),           //              .startofpacket
		.out_endofpacket   (crosser_002_out_endofpacket),             //              .endofpacket
		.out_channel       (crosser_002_out_channel),                 //              .channel
		.out_data          (crosser_002_out_data),                    //              .data
		.in_empty          (1'b0),                                    //   (terminated)
		.in_error          (1'b0),                                    //   (terminated)
		.out_empty         (),                                        //   (terminated)
		.out_error         ()                                         //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (105),
		.BITS_PER_SYMBOL     (105),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_003 (
		.in_clk            (clocks_c0_clk),                           //        in_clk.clk
		.in_reset          (sdram_reset_reset_bridge_in_reset_reset), //  in_clk_reset.reset
		.out_clk           (clk_clk_clk),                             //       out_clk.clk
		.out_reset         (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
		.in_ready          (rsp_demux_005_src1_ready),                //            in.ready
		.in_valid          (rsp_demux_005_src1_valid),                //              .valid
		.in_startofpacket  (rsp_demux_005_src1_startofpacket),        //              .startofpacket
		.in_endofpacket    (rsp_demux_005_src1_endofpacket),          //              .endofpacket
		.in_channel        (rsp_demux_005_src1_channel),              //              .channel
		.in_data           (rsp_demux_005_src1_data),                 //              .data
		.out_ready         (crosser_003_out_ready),                   //           out.ready
		.out_valid         (crosser_003_out_valid),                   //              .valid
		.out_startofpacket (crosser_003_out_startofpacket),           //              .startofpacket
		.out_endofpacket   (crosser_003_out_endofpacket),             //              .endofpacket
		.out_channel       (crosser_003_out_channel),                 //              .channel
		.out_data          (crosser_003_out_data),                    //              .data
		.in_empty          (1'b0),                                    //   (terminated)
		.in_error          (1'b0),                                    //   (terminated)
		.out_empty         (),                                        //   (terminated)
		.out_error         ()                                         //   (terminated)
	);

endmodule
