// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
//  by:  wig
//  on:  Tue Jun 27 05:12:12 2006
//  cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_b.v,v $
// Revision 1.6  2006/07/04 09:54:11  wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v 
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp 
//
// Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------


`timescale 1ns/10ps



//
//
// Start of Generated Module rtl of ent_b
//

// No user `defines in this module


module ent_b
//
// Generated Module inst_b
//
	(
		port_b_1,	// Will create p_mix_sig_1_go port
		port_b_3,	// Interhierachy link, will create p_mix_sig_3_go
		port_b_4,	// Interhierachy link, will create p_mix_sig_4_gi
		port_b_5_1,	// Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
		port_b_5_2,	// Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
		port_b_6i,	// Conflicting definition
		port_b_6o,	// Conflicting definition
		sig_07,	// Conflicting definition, IN false!
		sig_08	// VHDL intermediate needed (port name)
	);

	// Generated Module Inputs:
		input		port_b_1;
		input		port_b_3;
		input		port_b_5_1;
		input		port_b_5_2;
		input	[3:0]	port_b_6i;
		input	[5:0]	sig_07;
		input	[8:2]	sig_08;
	// Generated Module Outputs:
		output		port_b_4;
		output	[3:0]	port_b_6o;
	// Generated Wires:
		wire		port_b_1;
		wire		port_b_3;
		wire		port_b_4;
		wire		port_b_5_1;
		wire		port_b_5_2;
		wire	[3:0]	port_b_6i;
		wire	[3:0]	port_b_6o;
		wire	[5:0]	sig_07;
		wire	[8:2]	sig_08;
// End of generated module header


	// Internal signals

	//
	// Generated Signal List
	//
	//
	// End of Generated Signal List
	//


	// %COMPILER_OPTS%

	//
	// Generated Signal Assignments
	//




	//
	// Generated Instances and Port Mappings
	//
		// Generated Instance Port Map for inst_ba
		ent_ba inst_ba (

		);
		// End of Generated Instance Port Map for inst_ba

		// Generated Instance Port Map for inst_bb
		ent_bb inst_bb (

		);
		// End of Generated Instance Port Map for inst_bb



endmodule
//
// End of Generated Module rtl of ent_b
//

//
//!End of Module/s
// --------------------------------------------------------------
