// Module m_paper implements all features of the 4-bit paper processor.

module m_paper;
	reg r_low = 1'b0;												// logic low register
	reg r_high = 1'b1;												// logic high register
	reg r_clock = 1'b0;												// clock pulse register
	reg r_reset = 1'b1;												// reset value register

	wire w_low, w_high, w_clock, w_reset;										// low, high, clock, and reset wires

	assign w_low = r_low;												// assign low wire to low register
	assign w_high = r_high;												// assign high wire to high register
	assign w_clock = r_clock;											// assign clock wire to clock register
	assign w_reset = r_reset;											// assign reset wire to reset register

	wire [1:0] w_bus_addr; 												// address bus/program counter output bus)
	wire [3:0] w_bus_data; 												// data bus

	wire w_inc, w_jno, w_hlt, w_nop;										// inc, jno, hlt, and nop wires

	wire [1:0] w_bus_pc_in;												// program counter input bus
	wire [1:0] w_bus_pr_out, w_bus_pr_in;										// program register i/o buses
	wire w_sr_out, w_sr_in;												// status register i/o wires
	
	m_memory mem_0 (w_bus_data, w_bus_addr);									// instantiate memory module
	
	m_program_counter pc_0 (w_bus_addr, w_bus_pc_in, w_clock, w_reset);						// instantiate program counter
	m_program_register pr_0 (w_bus_pr_out, w_bus_pr_in, w_clock, w_reset);						// instantiate program register
	m_status_register sr_0 (w_sr_out, w_sr_in, w_clock, w_reset);							// instantiate status register

	m_opdecode opdc_0 (w_inc, w_jno, w_hlt, w_nop, w_bus_data);							// instantiate opdecode module

	m_ckt_inc ckt_inc_0 (w_bus_pr_in, w_sr_in, w_bus_pr_out, w_inc, w_low);						// instantiate increment circuit
	m_ckt_jno ckt_jno_0 (w_bus_pc_in, w_bus_addr, w_bus_data, w_jno, w_sr_out, w_low, w_high);			// instantiate jump if not overflowed circuit
	//m_ckt_hlt ckt_hlt_0 ();											// instantiate halt circuit
	//m_ckt_nop ckt_nop_0 ();											// instantiate no operation circuit

	initial begin													// do initially:
		$dumpfile ("paper.vcd");										// dump output to paper.vcd
		$dumpvars (0, m_paper);											// dump variables from mpaper module
		$monitor ("pc: %b, pr: %b, s: %b, data: %b", w_bus_addr, w_bus_pr_out, w_sr_out, w_bus_data);
		
		#2 r_reset = 1'b0;											// wait 2s, reset all circuit elements
	end
	
	always #1 begin													// every 1s:
		r_clock = ~w_clock;											// invert clock signal
		if (w_hlt) begin
			$display ("HLT call: Halting system.");
			$finish;											// halt simulation if hlt called
		end
	end
endmodule

