// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
// 
// ==============================================================


`timescale 1ns/1ps

module feedforward_fpext_32ns_64_1
#(parameter
    ID         = 4,
    NUM_STAGE  = 1,
    din0_WIDTH = 32,
    dout_WIDTH = 64
)(
    input  wire [din0_WIDTH-1:0] din0,
    output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire        a_tvalid;
wire [31:0] a_tdata;
wire        r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
feedforward_ap_fpext_0_no_dsp_32 feedforward_ap_fpext_0_no_dsp_32_u (
    .s_axis_a_tvalid      ( a_tvalid ),
    .s_axis_a_tdata       ( a_tdata ),
    .m_axis_result_tvalid ( r_tvalid ),
    .m_axis_result_tdata  ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata  = din0==='bx ? 'b0 : din0;
assign dout     = r_tdata;

endmodule
