// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb 

// ============================================================
// File Name: pcie_4243_hip_s4gx_gen2_x8_128_serdes.v
// Megafunction Name(s):
// 			alt4gxb
//
// Simulation Library Files(s):
// 			
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=34 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x8" tx_channel_width=8 tx_clkout_width=8 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
//VERSION_BEGIN 10.1SP1 cbx_alt4gxb 2011:01:19:21:23:40:SJ cbx_mgl 2011:01:19:21:24:50:SJ cbx_tgx 2011:01:19:21:23:40:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463


//synthesis_resources = reg 20 stratixiv_hssi_calibration_block 2 stratixiv_hssi_clock_divider 2 stratixiv_hssi_cmu 2 stratixiv_hssi_pll 9 stratixiv_hssi_rx_pcs 8 stratixiv_hssi_rx_pma 8 stratixiv_hssi_tx_pcs 8 stratixiv_hssi_tx_pma 8 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module  pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa
	( 
	cal_blk_clk,
	coreclkout,
	fixedclk,
	gxb_powerdown,
	hip_tx_clkout,
	pipe8b10binvpolarity,
	pipedatavalid,
	pipeelecidle,
	pipephydonestatus,
	pipestatus,
	pll_inclk,
	pll_locked,
	pll_powerdown,
	powerdn,
	rateswitch,
	rateswitchbaseclock,
	reconfig_clk,
	reconfig_fromgxb,
	reconfig_togxb,
	rx_analogreset,
	rx_cruclk,
	rx_ctrldetect,
	rx_datain,
	rx_dataout,
	rx_digitalreset,
	rx_elecidleinfersel,
	rx_freqlocked,
	rx_patterndetect,
	rx_pll_locked,
	rx_signaldetect,
	rx_syncstatus,
	tx_ctrlenable,
	tx_datain,
	tx_dataout,
	tx_detectrxloop,
	tx_digitalreset,
	tx_forcedispcompliance,
	tx_forceelecidle,
	tx_pipedeemph,
	tx_pipemargin) /* synthesis synthesis_clearbox=2 */;
	input   cal_blk_clk;
	output   [0:0]  coreclkout;
	input   fixedclk;
	input   [0:0]  gxb_powerdown;
	output   [7:0]  hip_tx_clkout;
	input   [7:0]  pipe8b10binvpolarity;
	output   [7:0]  pipedatavalid;
	output   [7:0]  pipeelecidle;
	output   [7:0]  pipephydonestatus;
	output   [23:0]  pipestatus;
	input   pll_inclk;
	output   [0:0]  pll_locked;
	input   [0:0]  pll_powerdown;
	input   [15:0]  powerdn;
	input   [0:0]  rateswitch;
	output   [1:0]  rateswitchbaseclock;
	input   reconfig_clk;
	output   [33:0]  reconfig_fromgxb;
	input   [3:0]  reconfig_togxb;
	input   [0:0]  rx_analogreset;
	input   [7:0]  rx_cruclk;
	output   [7:0]  rx_ctrldetect;
	input   [7:0]  rx_datain;
	output   [63:0]  rx_dataout;
	input   [0:0]  rx_digitalreset;
	input   [23:0]  rx_elecidleinfersel;
	output   [7:0]  rx_freqlocked;
	output   [7:0]  rx_patterndetect;
	output   [7:0]  rx_pll_locked;
	output   [7:0]  rx_signaldetect;
	output   [7:0]  rx_syncstatus;
	input   [7:0]  tx_ctrlenable;
	input   [63:0]  tx_datain;
	output   [7:0]  tx_dataout;
	input   [7:0]  tx_detectrxloop;
	input   [0:0]  tx_digitalreset;
	input   [7:0]  tx_forcedispcompliance;
	input   [7:0]  tx_forceelecidle;
	input   [7:0]  tx_pipedeemph;
	input   [23:0]  tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   cal_blk_clk;
	tri0   fixedclk;
	tri0   [0:0]  gxb_powerdown;
	tri0   [7:0]  pipe8b10binvpolarity;
	tri0   pll_inclk;
	tri0   [0:0]  pll_powerdown;
	tri0   [15:0]  powerdn;
	tri0   [0:0]  rateswitch;
	tri0   reconfig_clk;
	tri0   [0:0]  rx_analogreset;
	tri0   [7:0]  rx_cruclk;
	tri0   [0:0]  rx_digitalreset;
	tri0   [23:0]  rx_elecidleinfersel;
	tri0   [7:0]  tx_ctrlenable;
	tri0   [63:0]  tx_datain;
	tri0   [7:0]  tx_detectrxloop;
	tri0   [0:0]  tx_digitalreset;
	tri0   [7:0]  tx_forcedispcompliance;
	tri0   [7:0]  tx_forceelecidle;
	tri0   [7:0]  tx_pipedeemph;
	tri0   [23:0]  tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif


	parameter	starting_channel_number = 0;


	reg	fixedclk_div0quad0c;
	wire	wire_fixedclk_div0quad0c_clk;
	reg	fixedclk_div0quad1c;
	wire	wire_fixedclk_div0quad1c_clk;
	reg	fixedclk_div1quad0c;
	wire	wire_fixedclk_div1quad0c_clk;
	reg	fixedclk_div1quad1c;
	wire	wire_fixedclk_div1quad1c_clk;
	reg	fixedclk_div2quad0c;
	wire	wire_fixedclk_div2quad0c_clk;
	reg	fixedclk_div2quad1c;
	wire	wire_fixedclk_div2quad1c_clk;
	reg	fixedclk_div3quad0c;
	wire	wire_fixedclk_div3quad0c_clk;
	reg	fixedclk_div3quad1c;
	wire	wire_fixedclk_div3quad1c_clk;
	reg	fixedclk_div4quad0c;
	wire	wire_fixedclk_div4quad0c_clk;
	reg	fixedclk_div4quad1c;
	wire	wire_fixedclk_div4quad1c_clk;
	reg	fixedclk_div5quad0c;
	wire	wire_fixedclk_div5quad0c_clk;
	reg	fixedclk_div5quad1c;
	wire	wire_fixedclk_div5quad1c_clk;
	reg	[1:0]	reconfig_togxb_busy_reg;
	wire	[2:0]	wire_rx_digitalreset_reg0c_d;
	reg	[2:0]	rx_digitalreset_reg0c;
	wire	[2:0]	wire_rx_digitalreset_reg0c_clk;
	wire	[2:0]	wire_tx_digitalreset_reg0c_d;
	reg	[2:0]	tx_digitalreset_reg0c;
	wire	[2:0]	wire_tx_digitalreset_reg0c_clk;
	wire  wire_cal_blk0_nonusertocmu;
	wire  wire_cal_blk1_nonusertocmu;
	wire  [1:0]   wire_central_clk_div0_analogfastrefclkout;
	wire  [1:0]   wire_central_clk_div0_analogrefclkout;
	wire  wire_central_clk_div0_analogrefclkpulse;
	wire  wire_central_clk_div0_coreclkout;
	wire  [99:0]   wire_central_clk_div0_dprioout;
	wire  wire_central_clk_div0_rateswitchbaseclock;
	wire  wire_central_clk_div0_rateswitchdone;
	wire  wire_central_clk_div0_refclkout;
	wire  [1:0]   wire_central_clk_div1_analogfastrefclkout;
	wire  [1:0]   wire_central_clk_div1_analogrefclkout;
	wire  wire_central_clk_div1_analogrefclkpulse;
	wire  wire_central_clk_div1_coreclkout;
	wire  [99:0]   wire_central_clk_div1_dprioout;
	wire  wire_central_clk_div1_rateswitchbaseclock;
	wire  wire_central_clk_div1_rateswitchdone;
	wire  wire_central_clk_div1_refclkout;
	wire  wire_cent_unit0_autospdx4configsel;
	wire  wire_cent_unit0_autospdx4rateswitchout;
	wire  wire_cent_unit0_autospdx4spdchg;
	wire  [1:0]   wire_cent_unit0_clkdivpowerdn;
	wire  [599:0]   wire_cent_unit0_cmudividerdprioout;
	wire  [1799:0]   wire_cent_unit0_cmuplldprioout;
	wire  wire_cent_unit0_dpriodisableout;
	wire  wire_cent_unit0_dprioout;
	wire  wire_cent_unit0_phfifiox4ptrsreset;
	wire  [1:0]   wire_cent_unit0_pllpowerdn;
	wire  [1:0]   wire_cent_unit0_pllresetout;
	wire  wire_cent_unit0_quadresetout;
	wire  [5:0]   wire_cent_unit0_rxanalogresetout;
	wire  [5:0]   wire_cent_unit0_rxcrupowerdown;
	wire  [5:0]   wire_cent_unit0_rxcruresetout;
	wire  [3:0]   wire_cent_unit0_rxdigitalresetout;
	wire  [5:0]   wire_cent_unit0_rxibpowerdown;
	wire  [1599:0]   wire_cent_unit0_rxpcsdprioout;
	wire  wire_cent_unit0_rxphfifox4byteselout;
	wire  wire_cent_unit0_rxphfifox4rdenableout;
	wire  wire_cent_unit0_rxphfifox4wrclkout;
	wire  wire_cent_unit0_rxphfifox4wrenableout;
	wire  [1799:0]   wire_cent_unit0_rxpmadprioout;
	wire  [5:0]   wire_cent_unit0_txanalogresetout;
	wire  [3:0]   wire_cent_unit0_txctrlout;
	wire  [31:0]   wire_cent_unit0_txdataout;
	wire  [5:0]   wire_cent_unit0_txdetectrxpowerdown;
	wire  [3:0]   wire_cent_unit0_txdigitalresetout;
	wire  [5:0]   wire_cent_unit0_txobpowerdown;
	wire  [599:0]   wire_cent_unit0_txpcsdprioout;
	wire  wire_cent_unit0_txphfifox4byteselout;
	wire  wire_cent_unit0_txphfifox4rdclkout;
	wire  wire_cent_unit0_txphfifox4rdenableout;
	wire  wire_cent_unit0_txphfifox4wrenableout;
	wire  [1799:0]   wire_cent_unit0_txpmadprioout;
	wire  wire_cent_unit1_autospdx4configsel;
	wire  wire_cent_unit1_autospdx4rateswitchout;
	wire  wire_cent_unit1_autospdx4spdchg;
	wire  [1:0]   wire_cent_unit1_clkdivpowerdn;
	wire  [599:0]   wire_cent_unit1_cmudividerdprioout;
	wire  [1799:0]   wire_cent_unit1_cmuplldprioout;
	wire  wire_cent_unit1_dpriodisableout;
	wire  wire_cent_unit1_dprioout;
	wire  wire_cent_unit1_phfifiox4ptrsreset;
	wire  [1:0]   wire_cent_unit1_pllpowerdn;
	wire  [1:0]   wire_cent_unit1_pllresetout;
	wire  wire_cent_unit1_quadresetout;
	wire  [5:0]   wire_cent_unit1_rxanalogresetout;
	wire  [5:0]   wire_cent_unit1_rxcrupowerdown;
	wire  [5:0]   wire_cent_unit1_rxcruresetout;
	wire  [3:0]   wire_cent_unit1_rxdigitalresetout;
	wire  [5:0]   wire_cent_unit1_rxibpowerdown;
	wire  [1599:0]   wire_cent_unit1_rxpcsdprioout;
	wire  wire_cent_unit1_rxphfifox4byteselout;
	wire  wire_cent_unit1_rxphfifox4rdenableout;
	wire  wire_cent_unit1_rxphfifox4wrclkout;
	wire  wire_cent_unit1_rxphfifox4wrenableout;
	wire  [1799:0]   wire_cent_unit1_rxpmadprioout;
	wire  [5:0]   wire_cent_unit1_txanalogresetout;
	wire  [3:0]   wire_cent_unit1_txctrlout;
	wire  [31:0]   wire_cent_unit1_txdataout;
	wire  [5:0]   wire_cent_unit1_txdetectrxpowerdown;
	wire  [3:0]   wire_cent_unit1_txdigitalresetout;
	wire  [5:0]   wire_cent_unit1_txobpowerdown;
	wire  [599:0]   wire_cent_unit1_txpcsdprioout;
	wire  wire_cent_unit1_txphfifox4byteselout;
	wire  wire_cent_unit1_txphfifox4rdclkout;
	wire  wire_cent_unit1_txphfifox4rdenableout;
	wire  wire_cent_unit1_txphfifox4wrenableout;
	wire  [1799:0]   wire_cent_unit1_txpmadprioout;
	wire  [3:0]   wire_rx_cdr_pll0_clk;
	wire  [1:0]   wire_rx_cdr_pll0_dataout;
	wire  [299:0]   wire_rx_cdr_pll0_dprioout;
	wire  wire_rx_cdr_pll0_freqlocked;
	wire  wire_rx_cdr_pll0_locked;
	wire  wire_rx_cdr_pll0_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll1_clk;
	wire  [1:0]   wire_rx_cdr_pll1_dataout;
	wire  [299:0]   wire_rx_cdr_pll1_dprioout;
	wire  wire_rx_cdr_pll1_freqlocked;
	wire  wire_rx_cdr_pll1_locked;
	wire  wire_rx_cdr_pll1_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll2_clk;
	wire  [1:0]   wire_rx_cdr_pll2_dataout;
	wire  [299:0]   wire_rx_cdr_pll2_dprioout;
	wire  wire_rx_cdr_pll2_freqlocked;
	wire  wire_rx_cdr_pll2_locked;
	wire  wire_rx_cdr_pll2_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll3_clk;
	wire  [1:0]   wire_rx_cdr_pll3_dataout;
	wire  [299:0]   wire_rx_cdr_pll3_dprioout;
	wire  wire_rx_cdr_pll3_freqlocked;
	wire  wire_rx_cdr_pll3_locked;
	wire  wire_rx_cdr_pll3_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll4_clk;
	wire  [1:0]   wire_rx_cdr_pll4_dataout;
	wire  [299:0]   wire_rx_cdr_pll4_dprioout;
	wire  wire_rx_cdr_pll4_freqlocked;
	wire  wire_rx_cdr_pll4_locked;
	wire  wire_rx_cdr_pll4_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll5_clk;
	wire  [1:0]   wire_rx_cdr_pll5_dataout;
	wire  [299:0]   wire_rx_cdr_pll5_dprioout;
	wire  wire_rx_cdr_pll5_freqlocked;
	wire  wire_rx_cdr_pll5_locked;
	wire  wire_rx_cdr_pll5_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll6_clk;
	wire  [1:0]   wire_rx_cdr_pll6_dataout;
	wire  [299:0]   wire_rx_cdr_pll6_dprioout;
	wire  wire_rx_cdr_pll6_freqlocked;
	wire  wire_rx_cdr_pll6_locked;
	wire  wire_rx_cdr_pll6_pfdrefclkout;
	wire  [3:0]   wire_rx_cdr_pll7_clk;
	wire  [1:0]   wire_rx_cdr_pll7_dataout;
	wire  [299:0]   wire_rx_cdr_pll7_dprioout;
	wire  wire_rx_cdr_pll7_freqlocked;
	wire  wire_rx_cdr_pll7_locked;
	wire  wire_rx_cdr_pll7_pfdrefclkout;
	wire  [3:0]   wire_tx_pll0_clk;
	wire  [299:0]   wire_tx_pll0_dprioout;
	wire  wire_tx_pll0_locked;
	wire  wire_receive_pcs0_autospdrateswitchout;
	wire  wire_receive_pcs0_autospdspdchgout;
	wire  wire_receive_pcs0_cdrctrlearlyeios;
	wire  wire_receive_pcs0_cdrctrllocktorefclkout;
	wire  wire_receive_pcs0_coreclkout;
	wire  [399:0]   wire_receive_pcs0_dprioout;
	wire  [8:0]   wire_receive_pcs0_hipdataout;
	wire  wire_receive_pcs0_hipdatavalid;
	wire  wire_receive_pcs0_hipelecidle;
	wire  wire_receive_pcs0_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs0_hipstatus;
	wire  wire_receive_pcs0_iqpphfifobyteselout;
	wire  wire_receive_pcs0_iqpphfifoptrsresetout;
	wire  wire_receive_pcs0_iqpphfifordenableout;
	wire  wire_receive_pcs0_iqpphfifowrclkout;
	wire  wire_receive_pcs0_iqpphfifowrenableout;
	wire  wire_receive_pcs0_phfifobyteserdisableout;
	wire  wire_receive_pcs0_phfifoptrsresetout;
	wire  wire_receive_pcs0_phfifordenableout;
	wire  wire_receive_pcs0_phfiforesetout;
	wire  wire_receive_pcs0_phfifowrdisableout;
	wire  wire_receive_pcs0_pipestatetransdoneout;
	wire  wire_receive_pcs0_rateswitchout;
	wire  [19:0]   wire_receive_pcs0_revparallelfdbkdata;
	wire  wire_receive_pcs0_signaldetect;
	wire  wire_receive_pcs1_autospdrateswitchout;
	wire  wire_receive_pcs1_autospdspdchgout;
	wire  wire_receive_pcs1_cdrctrlearlyeios;
	wire  wire_receive_pcs1_cdrctrllocktorefclkout;
	wire  wire_receive_pcs1_coreclkout;
	wire  [399:0]   wire_receive_pcs1_dprioout;
	wire  [8:0]   wire_receive_pcs1_hipdataout;
	wire  wire_receive_pcs1_hipdatavalid;
	wire  wire_receive_pcs1_hipelecidle;
	wire  wire_receive_pcs1_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs1_hipstatus;
	wire  wire_receive_pcs1_iqpphfifobyteselout;
	wire  wire_receive_pcs1_iqpphfifoptrsresetout;
	wire  wire_receive_pcs1_iqpphfifordenableout;
	wire  wire_receive_pcs1_iqpphfifowrclkout;
	wire  wire_receive_pcs1_iqpphfifowrenableout;
	wire  wire_receive_pcs1_phfifobyteserdisableout;
	wire  wire_receive_pcs1_phfifoptrsresetout;
	wire  wire_receive_pcs1_phfifordenableout;
	wire  wire_receive_pcs1_phfiforesetout;
	wire  wire_receive_pcs1_phfifowrdisableout;
	wire  wire_receive_pcs1_pipestatetransdoneout;
	wire  wire_receive_pcs1_rateswitchout;
	wire  [19:0]   wire_receive_pcs1_revparallelfdbkdata;
	wire  wire_receive_pcs1_signaldetect;
	wire  wire_receive_pcs2_autospdrateswitchout;
	wire  wire_receive_pcs2_autospdspdchgout;
	wire  wire_receive_pcs2_cdrctrlearlyeios;
	wire  wire_receive_pcs2_cdrctrllocktorefclkout;
	wire  wire_receive_pcs2_coreclkout;
	wire  [399:0]   wire_receive_pcs2_dprioout;
	wire  [8:0]   wire_receive_pcs2_hipdataout;
	wire  wire_receive_pcs2_hipdatavalid;
	wire  wire_receive_pcs2_hipelecidle;
	wire  wire_receive_pcs2_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs2_hipstatus;
	wire  wire_receive_pcs2_iqpphfifobyteselout;
	wire  wire_receive_pcs2_iqpphfifoptrsresetout;
	wire  wire_receive_pcs2_iqpphfifordenableout;
	wire  wire_receive_pcs2_iqpphfifowrclkout;
	wire  wire_receive_pcs2_iqpphfifowrenableout;
	wire  wire_receive_pcs2_phfifobyteserdisableout;
	wire  wire_receive_pcs2_phfifoptrsresetout;
	wire  wire_receive_pcs2_phfifordenableout;
	wire  wire_receive_pcs2_phfiforesetout;
	wire  wire_receive_pcs2_phfifowrdisableout;
	wire  wire_receive_pcs2_pipestatetransdoneout;
	wire  wire_receive_pcs2_rateswitchout;
	wire  [19:0]   wire_receive_pcs2_revparallelfdbkdata;
	wire  wire_receive_pcs2_signaldetect;
	wire  wire_receive_pcs3_autospdrateswitchout;
	wire  wire_receive_pcs3_autospdspdchgout;
	wire  wire_receive_pcs3_cdrctrlearlyeios;
	wire  wire_receive_pcs3_cdrctrllocktorefclkout;
	wire  wire_receive_pcs3_coreclkout;
	wire  [399:0]   wire_receive_pcs3_dprioout;
	wire  [8:0]   wire_receive_pcs3_hipdataout;
	wire  wire_receive_pcs3_hipdatavalid;
	wire  wire_receive_pcs3_hipelecidle;
	wire  wire_receive_pcs3_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs3_hipstatus;
	wire  wire_receive_pcs3_iqpphfifobyteselout;
	wire  wire_receive_pcs3_iqpphfifoptrsresetout;
	wire  wire_receive_pcs3_iqpphfifordenableout;
	wire  wire_receive_pcs3_iqpphfifowrclkout;
	wire  wire_receive_pcs3_iqpphfifowrenableout;
	wire  wire_receive_pcs3_phfifobyteserdisableout;
	wire  wire_receive_pcs3_phfifoptrsresetout;
	wire  wire_receive_pcs3_phfifordenableout;
	wire  wire_receive_pcs3_phfiforesetout;
	wire  wire_receive_pcs3_phfifowrdisableout;
	wire  wire_receive_pcs3_pipestatetransdoneout;
	wire  wire_receive_pcs3_rateswitchout;
	wire  [19:0]   wire_receive_pcs3_revparallelfdbkdata;
	wire  wire_receive_pcs3_signaldetect;
	wire  wire_receive_pcs4_autospdrateswitchout;
	wire  wire_receive_pcs4_autospdspdchgout;
	wire  wire_receive_pcs4_cdrctrlearlyeios;
	wire  wire_receive_pcs4_cdrctrllocktorefclkout;
	wire  wire_receive_pcs4_coreclkout;
	wire  [399:0]   wire_receive_pcs4_dprioout;
	wire  [8:0]   wire_receive_pcs4_hipdataout;
	wire  wire_receive_pcs4_hipdatavalid;
	wire  wire_receive_pcs4_hipelecidle;
	wire  wire_receive_pcs4_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs4_hipstatus;
	wire  wire_receive_pcs4_iqpphfifobyteselout;
	wire  wire_receive_pcs4_iqpphfifoptrsresetout;
	wire  wire_receive_pcs4_iqpphfifordenableout;
	wire  wire_receive_pcs4_iqpphfifowrclkout;
	wire  wire_receive_pcs4_iqpphfifowrenableout;
	wire  wire_receive_pcs4_phfifobyteserdisableout;
	wire  wire_receive_pcs4_phfifoptrsresetout;
	wire  wire_receive_pcs4_phfifordenableout;
	wire  wire_receive_pcs4_phfiforesetout;
	wire  wire_receive_pcs4_phfifowrdisableout;
	wire  wire_receive_pcs4_pipestatetransdoneout;
	wire  wire_receive_pcs4_rateswitchout;
	wire  [19:0]   wire_receive_pcs4_revparallelfdbkdata;
	wire  wire_receive_pcs4_signaldetect;
	wire  wire_receive_pcs5_autospdrateswitchout;
	wire  wire_receive_pcs5_autospdspdchgout;
	wire  wire_receive_pcs5_cdrctrlearlyeios;
	wire  wire_receive_pcs5_cdrctrllocktorefclkout;
	wire  wire_receive_pcs5_coreclkout;
	wire  [399:0]   wire_receive_pcs5_dprioout;
	wire  [8:0]   wire_receive_pcs5_hipdataout;
	wire  wire_receive_pcs5_hipdatavalid;
	wire  wire_receive_pcs5_hipelecidle;
	wire  wire_receive_pcs5_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs5_hipstatus;
	wire  wire_receive_pcs5_iqpphfifobyteselout;
	wire  wire_receive_pcs5_iqpphfifoptrsresetout;
	wire  wire_receive_pcs5_iqpphfifordenableout;
	wire  wire_receive_pcs5_iqpphfifowrclkout;
	wire  wire_receive_pcs5_iqpphfifowrenableout;
	wire  wire_receive_pcs5_phfifobyteserdisableout;
	wire  wire_receive_pcs5_phfifoptrsresetout;
	wire  wire_receive_pcs5_phfifordenableout;
	wire  wire_receive_pcs5_phfiforesetout;
	wire  wire_receive_pcs5_phfifowrdisableout;
	wire  wire_receive_pcs5_pipestatetransdoneout;
	wire  wire_receive_pcs5_rateswitchout;
	wire  [19:0]   wire_receive_pcs5_revparallelfdbkdata;
	wire  wire_receive_pcs5_signaldetect;
	wire  wire_receive_pcs6_autospdrateswitchout;
	wire  wire_receive_pcs6_autospdspdchgout;
	wire  wire_receive_pcs6_cdrctrlearlyeios;
	wire  wire_receive_pcs6_cdrctrllocktorefclkout;
	wire  wire_receive_pcs6_coreclkout;
	wire  [399:0]   wire_receive_pcs6_dprioout;
	wire  [8:0]   wire_receive_pcs6_hipdataout;
	wire  wire_receive_pcs6_hipdatavalid;
	wire  wire_receive_pcs6_hipelecidle;
	wire  wire_receive_pcs6_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs6_hipstatus;
	wire  wire_receive_pcs6_iqpphfifobyteselout;
	wire  wire_receive_pcs6_iqpphfifoptrsresetout;
	wire  wire_receive_pcs6_iqpphfifordenableout;
	wire  wire_receive_pcs6_iqpphfifowrclkout;
	wire  wire_receive_pcs6_iqpphfifowrenableout;
	wire  wire_receive_pcs6_phfifobyteserdisableout;
	wire  wire_receive_pcs6_phfifoptrsresetout;
	wire  wire_receive_pcs6_phfifordenableout;
	wire  wire_receive_pcs6_phfiforesetout;
	wire  wire_receive_pcs6_phfifowrdisableout;
	wire  wire_receive_pcs6_pipestatetransdoneout;
	wire  wire_receive_pcs6_rateswitchout;
	wire  [19:0]   wire_receive_pcs6_revparallelfdbkdata;
	wire  wire_receive_pcs6_signaldetect;
	wire  wire_receive_pcs7_autospdrateswitchout;
	wire  wire_receive_pcs7_autospdspdchgout;
	wire  wire_receive_pcs7_cdrctrlearlyeios;
	wire  wire_receive_pcs7_cdrctrllocktorefclkout;
	wire  wire_receive_pcs7_coreclkout;
	wire  [399:0]   wire_receive_pcs7_dprioout;
	wire  [8:0]   wire_receive_pcs7_hipdataout;
	wire  wire_receive_pcs7_hipdatavalid;
	wire  wire_receive_pcs7_hipelecidle;
	wire  wire_receive_pcs7_hipphydonestatus;
	wire  [2:0]   wire_receive_pcs7_hipstatus;
	wire  wire_receive_pcs7_iqpphfifobyteselout;
	wire  wire_receive_pcs7_iqpphfifoptrsresetout;
	wire  wire_receive_pcs7_iqpphfifordenableout;
	wire  wire_receive_pcs7_iqpphfifowrclkout;
	wire  wire_receive_pcs7_iqpphfifowrenableout;
	wire  wire_receive_pcs7_phfifobyteserdisableout;
	wire  wire_receive_pcs7_phfifoptrsresetout;
	wire  wire_receive_pcs7_phfifordenableout;
	wire  wire_receive_pcs7_phfiforesetout;
	wire  wire_receive_pcs7_phfifowrdisableout;
	wire  wire_receive_pcs7_pipestatetransdoneout;
	wire  wire_receive_pcs7_rateswitchout;
	wire  [19:0]   wire_receive_pcs7_revparallelfdbkdata;
	wire  wire_receive_pcs7_signaldetect;
	wire  [7:0]   wire_receive_pma0_analogtestbus;
	wire  wire_receive_pma0_clockout;
	wire  wire_receive_pma0_dataout;
	wire  [299:0]   wire_receive_pma0_dprioout;
	wire  wire_receive_pma0_locktorefout;
	wire  [63:0]   wire_receive_pma0_recoverdataout;
	wire  wire_receive_pma0_signaldetect;
	wire  [7:0]   wire_receive_pma1_analogtestbus;
	wire  wire_receive_pma1_clockout;
	wire  wire_receive_pma1_dataout;
	wire  [299:0]   wire_receive_pma1_dprioout;
	wire  wire_receive_pma1_locktorefout;
	wire  [63:0]   wire_receive_pma1_recoverdataout;
	wire  wire_receive_pma1_signaldetect;
	wire  [7:0]   wire_receive_pma2_analogtestbus;
	wire  wire_receive_pma2_clockout;
	wire  wire_receive_pma2_dataout;
	wire  [299:0]   wire_receive_pma2_dprioout;
	wire  wire_receive_pma2_locktorefout;
	wire  [63:0]   wire_receive_pma2_recoverdataout;
	wire  wire_receive_pma2_signaldetect;
	wire  [7:0]   wire_receive_pma3_analogtestbus;
	wire  wire_receive_pma3_clockout;
	wire  wire_receive_pma3_dataout;
	wire  [299:0]   wire_receive_pma3_dprioout;
	wire  wire_receive_pma3_locktorefout;
	wire  [63:0]   wire_receive_pma3_recoverdataout;
	wire  wire_receive_pma3_signaldetect;
	wire  [7:0]   wire_receive_pma4_analogtestbus;
	wire  wire_receive_pma4_clockout;
	wire  wire_receive_pma4_dataout;
	wire  [299:0]   wire_receive_pma4_dprioout;
	wire  wire_receive_pma4_locktorefout;
	wire  [63:0]   wire_receive_pma4_recoverdataout;
	wire  wire_receive_pma4_signaldetect;
	wire  [7:0]   wire_receive_pma5_analogtestbus;
	wire  wire_receive_pma5_clockout;
	wire  wire_receive_pma5_dataout;
	wire  [299:0]   wire_receive_pma5_dprioout;
	wire  wire_receive_pma5_locktorefout;
	wire  [63:0]   wire_receive_pma5_recoverdataout;
	wire  wire_receive_pma5_signaldetect;
	wire  [7:0]   wire_receive_pma6_analogtestbus;
	wire  wire_receive_pma6_clockout;
	wire  wire_receive_pma6_dataout;
	wire  [299:0]   wire_receive_pma6_dprioout;
	wire  wire_receive_pma6_locktorefout;
	wire  [63:0]   wire_receive_pma6_recoverdataout;
	wire  wire_receive_pma6_signaldetect;
	wire  [7:0]   wire_receive_pma7_analogtestbus;
	wire  wire_receive_pma7_clockout;
	wire  wire_receive_pma7_dataout;
	wire  [299:0]   wire_receive_pma7_dprioout;
	wire  wire_receive_pma7_locktorefout;
	wire  [63:0]   wire_receive_pma7_recoverdataout;
	wire  wire_receive_pma7_signaldetect;
	wire  wire_transmit_pcs0_coreclkout;
	wire  [19:0]   wire_transmit_pcs0_dataout;
	wire  [149:0]   wire_transmit_pcs0_dprioout;
	wire  wire_transmit_pcs0_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs0_grayelecidleinferselout;
	wire  wire_transmit_pcs0_iqpphfifobyteselout;
	wire  wire_transmit_pcs0_iqpphfifordclkout;
	wire  wire_transmit_pcs0_iqpphfifordenableout;
	wire  wire_transmit_pcs0_iqpphfifowrenableout;
	wire  wire_transmit_pcs0_phfiforddisableout;
	wire  wire_transmit_pcs0_phfiforesetout;
	wire  wire_transmit_pcs0_phfifowrenableout;
	wire  wire_transmit_pcs0_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs0_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs0_pipepowerstateout;
	wire  wire_transmit_pcs0_txdetectrx;
	wire  wire_transmit_pcs1_coreclkout;
	wire  [19:0]   wire_transmit_pcs1_dataout;
	wire  [149:0]   wire_transmit_pcs1_dprioout;
	wire  wire_transmit_pcs1_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs1_grayelecidleinferselout;
	wire  wire_transmit_pcs1_iqpphfifobyteselout;
	wire  wire_transmit_pcs1_iqpphfifordclkout;
	wire  wire_transmit_pcs1_iqpphfifordenableout;
	wire  wire_transmit_pcs1_iqpphfifowrenableout;
	wire  wire_transmit_pcs1_phfiforddisableout;
	wire  wire_transmit_pcs1_phfiforesetout;
	wire  wire_transmit_pcs1_phfifowrenableout;
	wire  wire_transmit_pcs1_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs1_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs1_pipepowerstateout;
	wire  wire_transmit_pcs1_txdetectrx;
	wire  wire_transmit_pcs2_coreclkout;
	wire  [19:0]   wire_transmit_pcs2_dataout;
	wire  [149:0]   wire_transmit_pcs2_dprioout;
	wire  wire_transmit_pcs2_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs2_grayelecidleinferselout;
	wire  wire_transmit_pcs2_iqpphfifobyteselout;
	wire  wire_transmit_pcs2_iqpphfifordclkout;
	wire  wire_transmit_pcs2_iqpphfifordenableout;
	wire  wire_transmit_pcs2_iqpphfifowrenableout;
	wire  wire_transmit_pcs2_phfiforddisableout;
	wire  wire_transmit_pcs2_phfiforesetout;
	wire  wire_transmit_pcs2_phfifowrenableout;
	wire  wire_transmit_pcs2_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs2_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs2_pipepowerstateout;
	wire  wire_transmit_pcs2_txdetectrx;
	wire  wire_transmit_pcs3_coreclkout;
	wire  [19:0]   wire_transmit_pcs3_dataout;
	wire  [149:0]   wire_transmit_pcs3_dprioout;
	wire  wire_transmit_pcs3_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs3_grayelecidleinferselout;
	wire  wire_transmit_pcs3_iqpphfifobyteselout;
	wire  wire_transmit_pcs3_iqpphfifordclkout;
	wire  wire_transmit_pcs3_iqpphfifordenableout;
	wire  wire_transmit_pcs3_iqpphfifowrenableout;
	wire  wire_transmit_pcs3_phfiforddisableout;
	wire  wire_transmit_pcs3_phfiforesetout;
	wire  wire_transmit_pcs3_phfifowrenableout;
	wire  wire_transmit_pcs3_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs3_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs3_pipepowerstateout;
	wire  wire_transmit_pcs3_txdetectrx;
	wire  wire_transmit_pcs4_coreclkout;
	wire  [19:0]   wire_transmit_pcs4_dataout;
	wire  [149:0]   wire_transmit_pcs4_dprioout;
	wire  wire_transmit_pcs4_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs4_grayelecidleinferselout;
	wire  wire_transmit_pcs4_iqpphfifobyteselout;
	wire  wire_transmit_pcs4_iqpphfifordclkout;
	wire  wire_transmit_pcs4_iqpphfifordenableout;
	wire  wire_transmit_pcs4_iqpphfifowrenableout;
	wire  wire_transmit_pcs4_phfiforddisableout;
	wire  wire_transmit_pcs4_phfiforesetout;
	wire  wire_transmit_pcs4_phfifowrenableout;
	wire  wire_transmit_pcs4_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs4_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs4_pipepowerstateout;
	wire  wire_transmit_pcs4_txdetectrx;
	wire  wire_transmit_pcs5_coreclkout;
	wire  [19:0]   wire_transmit_pcs5_dataout;
	wire  [149:0]   wire_transmit_pcs5_dprioout;
	wire  wire_transmit_pcs5_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs5_grayelecidleinferselout;
	wire  wire_transmit_pcs5_iqpphfifobyteselout;
	wire  wire_transmit_pcs5_iqpphfifordclkout;
	wire  wire_transmit_pcs5_iqpphfifordenableout;
	wire  wire_transmit_pcs5_iqpphfifowrenableout;
	wire  wire_transmit_pcs5_phfiforddisableout;
	wire  wire_transmit_pcs5_phfiforesetout;
	wire  wire_transmit_pcs5_phfifowrenableout;
	wire  wire_transmit_pcs5_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs5_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs5_pipepowerstateout;
	wire  wire_transmit_pcs5_txdetectrx;
	wire  wire_transmit_pcs6_coreclkout;
	wire  [19:0]   wire_transmit_pcs6_dataout;
	wire  [149:0]   wire_transmit_pcs6_dprioout;
	wire  wire_transmit_pcs6_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs6_grayelecidleinferselout;
	wire  wire_transmit_pcs6_iqpphfifobyteselout;
	wire  wire_transmit_pcs6_iqpphfifordclkout;
	wire  wire_transmit_pcs6_iqpphfifordenableout;
	wire  wire_transmit_pcs6_iqpphfifowrenableout;
	wire  wire_transmit_pcs6_phfiforddisableout;
	wire  wire_transmit_pcs6_phfiforesetout;
	wire  wire_transmit_pcs6_phfifowrenableout;
	wire  wire_transmit_pcs6_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs6_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs6_pipepowerstateout;
	wire  wire_transmit_pcs6_txdetectrx;
	wire  wire_transmit_pcs7_coreclkout;
	wire  [19:0]   wire_transmit_pcs7_dataout;
	wire  [149:0]   wire_transmit_pcs7_dprioout;
	wire  wire_transmit_pcs7_forceelecidleout;
	wire  [2:0]   wire_transmit_pcs7_grayelecidleinferselout;
	wire  wire_transmit_pcs7_iqpphfifobyteselout;
	wire  wire_transmit_pcs7_iqpphfifordclkout;
	wire  wire_transmit_pcs7_iqpphfifordenableout;
	wire  wire_transmit_pcs7_iqpphfifowrenableout;
	wire  wire_transmit_pcs7_phfiforddisableout;
	wire  wire_transmit_pcs7_phfiforesetout;
	wire  wire_transmit_pcs7_phfifowrenableout;
	wire  wire_transmit_pcs7_pipeenrevparallellpbkout;
	wire  [1:0]   wire_transmit_pcs7_pipepowerdownout;
	wire  [3:0]   wire_transmit_pcs7_pipepowerstateout;
	wire  wire_transmit_pcs7_txdetectrx;
	wire  wire_transmit_pma0_clockout;
	wire  wire_transmit_pma0_dataout;
	wire  [299:0]   wire_transmit_pma0_dprioout;
	wire  wire_transmit_pma0_rxdetectvalidout;
	wire  wire_transmit_pma0_rxfoundout;
	wire  wire_transmit_pma1_clockout;
	wire  wire_transmit_pma1_dataout;
	wire  [299:0]   wire_transmit_pma1_dprioout;
	wire  wire_transmit_pma1_rxdetectvalidout;
	wire  wire_transmit_pma1_rxfoundout;
	wire  wire_transmit_pma2_clockout;
	wire  wire_transmit_pma2_dataout;
	wire  [299:0]   wire_transmit_pma2_dprioout;
	wire  wire_transmit_pma2_rxdetectvalidout;
	wire  wire_transmit_pma2_rxfoundout;
	wire  wire_transmit_pma3_clockout;
	wire  wire_transmit_pma3_dataout;
	wire  [299:0]   wire_transmit_pma3_dprioout;
	wire  wire_transmit_pma3_rxdetectvalidout;
	wire  wire_transmit_pma3_rxfoundout;
	wire  wire_transmit_pma4_clockout;
	wire  wire_transmit_pma4_dataout;
	wire  [299:0]   wire_transmit_pma4_dprioout;
	wire  wire_transmit_pma4_rxdetectvalidout;
	wire  wire_transmit_pma4_rxfoundout;
	wire  wire_transmit_pma5_clockout;
	wire  wire_transmit_pma5_dataout;
	wire  [299:0]   wire_transmit_pma5_dprioout;
	wire  wire_transmit_pma5_rxdetectvalidout;
	wire  wire_transmit_pma5_rxfoundout;
	wire  wire_transmit_pma6_clockout;
	wire  wire_transmit_pma6_dataout;
	wire  [299:0]   wire_transmit_pma6_dprioout;
	wire  wire_transmit_pma6_rxdetectvalidout;
	wire  wire_transmit_pma6_rxfoundout;
	wire  wire_transmit_pma7_clockout;
	wire  wire_transmit_pma7_dataout;
	wire  [299:0]   wire_transmit_pma7_dprioout;
	wire  wire_transmit_pma7_rxdetectvalidout;
	wire  wire_transmit_pma7_rxfoundout;
	wire cal_blk_powerdown;
	wire  [1:0]  cent_unit_clkdivpowerdn;
	wire  [1199:0]  cent_unit_cmudividerdprioout;
	wire  [3599:0]  cent_unit_cmuplldprioout;
	wire  [3:0]  cent_unit_pllpowerdn;
	wire  [3:0]  cent_unit_pllresetout;
	wire  [1:0]  cent_unit_quadresetout;
	wire  [11:0]  cent_unit_rxcrupowerdn;
	wire  [11:0]  cent_unit_rxibpowerdn;
	wire  [3199:0]  cent_unit_rxpcsdprioin;
	wire  [3199:0]  cent_unit_rxpcsdprioout;
	wire  [3599:0]  cent_unit_rxpmadprioin;
	wire  [3599:0]  cent_unit_rxpmadprioout;
	wire  [2399:0]  cent_unit_tx_dprioin;
	wire  [63:0]  cent_unit_tx_xgmdataout;
	wire  [7:0]  cent_unit_txctrlout;
	wire  [11:0]  cent_unit_txdetectrxpowerdn;
	wire  [1199:0]  cent_unit_txdprioout;
	wire  [11:0]  cent_unit_txobpowerdn;
	wire  [3599:0]  cent_unit_txpmadprioin;
	wire  [3599:0]  cent_unit_txpmadprioout;
	wire  [7:0]  clk_div_clk0in;
	wire  [1199:0]  clk_div_cmudividerdprioin;
	wire  [1:0]  clk_div_pclkin;
	wire  [3:0]  cmu_analogfastrefclkout;
	wire  [3:0]  cmu_analogrefclkout;
	wire  [1:0]  cmu_analogrefclkpulse;
	wire  [1:0]  coreclkout_wire;
	wire  [11:0]  fixedclk_div_in;
	wire  [0:0]  fixedclk_enable;
	wire [11:0]  fixedclk_fast;
	wire  [11:0]  fixedclk_in;
	wire  [0:0]  fixedclk_sel;
	wire  [11:0]  fixedclk_to_cmu;
	wire  [1:0]  int_autospdx4configsel;
	wire  [1:0]  int_autospdx4rateswitchout;
	wire  [1:0]  int_autospdx4spdchg;
	wire  [7:0]  int_hipautospdrateswitchout;
	wire  [1:0]  int_hiprateswtichdone;
	wire  [1:0]  int_phfifiox4ptrsreset;
	wire  [7:0]  int_pipeenrevparallellpbkfromtx;
	wire  [1:0]  int_rateswitch;
	wire  [7:0]  int_rx_autospdspdchgout;
	wire  [23:0]  int_rx_autospdxnconfigsel;
	wire  [23:0]  int_rx_autospdxnspdchg;
	wire  [7:0]  int_rx_coreclkout;
	wire  [0:0]  int_rx_digitalreset_reg;
	wire  [15:0]  int_rx_iqpautospdxnspgchg;
	wire  [7:0]  int_rx_iqpphfifobyteselout;
	wire  [7:0]  int_rx_iqpphfifoptrsresetout;
	wire  [7:0]  int_rx_iqpphfifordenableout;
	wire  [7:0]  int_rx_iqpphfifowrclkout;
	wire  [7:0]  int_rx_iqpphfifowrenableout;
	wire  [15:0]  int_rx_iqpphfifoxnbytesel;
	wire  [15:0]  int_rx_iqpphfifoxnptrsreset;
	wire  [15:0]  int_rx_iqpphfifoxnrdenable;
	wire  [15:0]  int_rx_iqpphfifoxnwrclk;
	wire  [15:0]  int_rx_iqpphfifoxnwrenable;
	wire  [23:0]  int_rx_phfifioxnptrsreset;
	wire  [7:0]  int_rx_phfifobyteserdisable;
	wire  [7:0]  int_rx_phfifoptrsresetout;
	wire  [7:0]  int_rx_phfifordenableout;
	wire  [7:0]  int_rx_phfiforesetout;
	wire  [7:0]  int_rx_phfifowrdisableout;
	wire  [23:0]  int_rx_phfifoxnbytesel;
	wire  [23:0]  int_rx_phfifoxnrdenable;
	wire  [23:0]  int_rx_phfifoxnwrclk;
	wire  [23:0]  int_rx_phfifoxnwrenable;
	wire  [7:0]  int_rx_rateswitchout;
	wire  [1:0]  int_rxcoreclk;
	wire  [7:0]  int_rxpcs_cdrctrlearlyeios;
	wire  [1:0]  int_rxphfifordenable;
	wire  [1:0]  int_rxphfiforeset;
	wire  [1:0]  int_rxphfifox4byteselout;
	wire  [1:0]  int_rxphfifox4rdenableout;
	wire  [1:0]  int_rxphfifox4wrclkout;
	wire  [1:0]  int_rxphfifox4wrenableout;
	wire  [7:0]  int_tx_coreclkout;
	wire  [0:0]  int_tx_digitalreset_reg;
	wire  [7:0]  int_tx_iqpphfifobyteselout;
	wire  [7:0]  int_tx_iqpphfifordclkout;
	wire  [7:0]  int_tx_iqpphfifordenableout;
	wire  [7:0]  int_tx_iqpphfifowrenableout;
	wire  [15:0]  int_tx_iqpphfifoxnbytesel;
	wire  [15:0]  int_tx_iqpphfifoxnrdclk;
	wire  [15:0]  int_tx_iqpphfifoxnrdenable;
	wire  [15:0]  int_tx_iqpphfifoxnwrenable;
	wire  [23:0]  int_tx_phfifioxnptrsreset;
	wire  [7:0]  int_tx_phfiforddisableout;
	wire  [7:0]  int_tx_phfiforesetout;
	wire  [7:0]  int_tx_phfifowrenableout;
	wire  [23:0]  int_tx_phfifoxnbytesel;
	wire  [23:0]  int_tx_phfifoxnrdclk;
	wire  [23:0]  int_tx_phfifoxnrdenable;
	wire  [23:0]  int_tx_phfifoxnwrenable;
	wire  [1:0]  int_txcoreclk;
	wire  [1:0]  int_txphfiforddisable;
	wire  [1:0]  int_txphfiforeset;
	wire  [1:0]  int_txphfifowrenable;
	wire  [1:0]  int_txphfifox4byteselout;
	wire  [1:0]  int_txphfifox4rdclkout;
	wire  [1:0]  int_txphfifox4rdenableout;
	wire  [1:0]  int_txphfifox4wrenableout;
	wire  [1:0]  nonusertocmu_out;
	wire  [7:0]  pipedatavalid_out;
	wire  [7:0]  pipeelecidle_out;
	wire  [19:0]  pll0_clkin;
	wire  [599:0]  pll0_dprioin;
	wire  [599:0]  pll0_dprioout;
	wire  [7:0]  pll0_out;
	wire  [15:0]  pll_ch_dataout_wire;
	wire  [2399:0]  pll_ch_dprioout;
	wire  [3599:0]  pll_cmuplldprioout;
	wire  [0:0]  pll_inclk_wire;
	wire  [1:0]  pll_locked_out;
	wire  [3:0]  pllpowerdn_in;
	wire  [3:0]  pllreset_in;
	wire  [0:0]  reconfig_togxb_busy;
	wire  [0:0]  reconfig_togxb_disable;
	wire  [0:0]  reconfig_togxb_in;
	wire  [0:0]  reconfig_togxb_load;
	wire  [1:0]  refclk_pma;
	wire  [11:0]  rx_analogreset_in;
	wire  [11:0]  rx_analogreset_out;
	wire  [79:0]  rx_cruclk_in;
	wire  [31:0]  rx_deserclock_in;
	wire  [7:0]  rx_digitalreset_in;
	wire  [7:0]  rx_digitalreset_out;
	wire [7:0]  rx_enapatternalign;
	wire  [7:0]  rx_freqlocked_wire;
	wire [7:0]  rx_locktodata;
	wire  [7:0]  rx_locktodata_wire;
	wire  [7:0]  rx_locktorefclk_wire;
	wire  [63:0]  rx_out_wire;
	wire  [15:0]  rx_pcs_rxfound_wire;
	wire  [3199:0]  rx_pcsdprioin_wire;
	wire  [3199:0]  rx_pcsdprioout;
	wire [7:0]  rx_phfifordenable;
	wire [7:0]  rx_phfiforeset;
	wire [7:0]  rx_phfifowrdisable;
	wire  [7:0]  rx_pipestatetransdoneout;
	wire  [7:0]  rx_pldcruclk_in;
	wire  [31:0]  rx_pll_clkout;
	wire  [7:0]  rx_pll_pfdrefclkout_wire;
	wire  [7:0]  rx_plllocked_wire;
	wire  [135:0]  rx_pma_analogtestbus;
	wire  [7:0]  rx_pma_clockout;
	wire  [7:0]  rx_pma_dataout;
	wire  [7:0]  rx_pma_locktorefout;
	wire  [159:0]  rx_pma_recoverdataout_wire;
	wire  [3599:0]  rx_pmadprioin_wire;
	wire  [3599:0]  rx_pmadprioout;
	wire [7:0]  rx_powerdown;
	wire  [11:0]  rx_powerdown_in;
	wire [7:0]  rx_prbscidenable;
	wire  [159:0]  rx_revparallelfdbkdata;
	wire [7:0]  rx_rmfiforeset;
	wire  [11:0]  rx_rxcruresetout;
	wire  [7:0]  rx_signaldetect_wire;
	wire  [7:0]  rx_signaldetectout_wire;
	wire  [1:0]  rxphfifowrdisable;
	wire  [3599:0]  rxpll_dprioin;
	wire  [11:0]  tx_analogreset_out;
	wire  [7:0]  tx_clkout_int_wire;
	wire  [63:0]  tx_datain_wire;
	wire  [159:0]  tx_dataout_pcs_to_pma;
	wire  [7:0]  tx_digitalreset_in;
	wire  [7:0]  tx_digitalreset_out;
	wire  [2399:0]  tx_dprioin_wire;
	wire [7:0]  tx_invpolarity;
	wire  [7:0]  tx_localrefclk;
	wire  [7:0]  tx_pcs_forceelecidleout;
	wire [7:0]  tx_phfiforeset;
	wire  [15:0]  tx_pipepowerdownout;
	wire  [31:0]  tx_pipepowerstateout;
	wire [7:0]  tx_pipeswing;
	wire  [3599:0]  tx_pmadprioin_wire;
	wire  [3599:0]  tx_pmadprioout;
	wire [7:0]  tx_revparallellpbken;
	wire  [7:0]  tx_rxdetectvalidout;
	wire  [7:0]  tx_rxfoundout;
	wire  [1199:0]  tx_txdprioout;
	wire  [7:0]  txdetectrxout;
	wire  [1:0]  w_cent_unit_dpriodisableout1w;

	// synopsys translate_off
	initial
		fixedclk_div0quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div0quad0c_clk)
		  fixedclk_div0quad0c <= (~ fixedclk_div_in[0]);
	assign
		wire_fixedclk_div0quad0c_clk = fixedclk_in[0];
	// synopsys translate_off
	initial
		fixedclk_div0quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div0quad1c_clk)
		  fixedclk_div0quad1c <= (~ fixedclk_div_in[6]);
	assign
		wire_fixedclk_div0quad1c_clk = fixedclk_in[6];
	// synopsys translate_off
	initial
		fixedclk_div1quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div1quad0c_clk)
		  fixedclk_div1quad0c <= (~ fixedclk_div_in[1]);
	assign
		wire_fixedclk_div1quad0c_clk = fixedclk_in[1];
	// synopsys translate_off
	initial
		fixedclk_div1quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div1quad1c_clk)
		  fixedclk_div1quad1c <= (~ fixedclk_div_in[7]);
	assign
		wire_fixedclk_div1quad1c_clk = fixedclk_in[7];
	// synopsys translate_off
	initial
		fixedclk_div2quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div2quad0c_clk)
		  fixedclk_div2quad0c <= (~ fixedclk_div_in[2]);
	assign
		wire_fixedclk_div2quad0c_clk = fixedclk_in[2];
	// synopsys translate_off
	initial
		fixedclk_div2quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div2quad1c_clk)
		  fixedclk_div2quad1c <= (~ fixedclk_div_in[8]);
	assign
		wire_fixedclk_div2quad1c_clk = fixedclk_in[8];
	// synopsys translate_off
	initial
		fixedclk_div3quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div3quad0c_clk)
		  fixedclk_div3quad0c <= (~ fixedclk_div_in[3]);
	assign
		wire_fixedclk_div3quad0c_clk = fixedclk_in[3];
	// synopsys translate_off
	initial
		fixedclk_div3quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div3quad1c_clk)
		  fixedclk_div3quad1c <= (~ fixedclk_div_in[9]);
	assign
		wire_fixedclk_div3quad1c_clk = fixedclk_in[9];
	// synopsys translate_off
	initial
		fixedclk_div4quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div4quad0c_clk)
		  fixedclk_div4quad0c <= (~ fixedclk_div_in[4]);
	assign
		wire_fixedclk_div4quad0c_clk = fixedclk_in[4];
	// synopsys translate_off
	initial
		fixedclk_div4quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div4quad1c_clk)
		  fixedclk_div4quad1c <= (~ fixedclk_div_in[10]);
	assign
		wire_fixedclk_div4quad1c_clk = fixedclk_in[10];
	// synopsys translate_off
	initial
		fixedclk_div5quad0c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div5quad0c_clk)
		  fixedclk_div5quad0c <= (~ fixedclk_div_in[5]);
	assign
		wire_fixedclk_div5quad0c_clk = fixedclk_in[5];
	// synopsys translate_off
	initial
		fixedclk_div5quad1c = 0;
	// synopsys translate_on
	always @ ( posedge wire_fixedclk_div5quad1c_clk)
		  fixedclk_div5quad1c <= (~ fixedclk_div_in[11]);
	assign
		wire_fixedclk_div5quad1c_clk = fixedclk_in[11];
	// synopsys translate_off
	initial
		reconfig_togxb_busy_reg = 0;
	// synopsys translate_on
	always @ ( negedge fixedclk)
		  reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
	// synopsys translate_off
	initial
		rx_digitalreset_reg0c[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
		  rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
	// synopsys translate_off
	initial
		rx_digitalreset_reg0c[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
		  rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
	// synopsys translate_off
	initial
		rx_digitalreset_reg0c[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
		  rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
	assign
		wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
	assign
		wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
		  tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
		  tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
	// synopsys translate_off
	initial
		tx_digitalreset_reg0c[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
		  tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
	assign
		wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
	assign
		wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
	stratixiv_hssi_calibration_block   cal_blk0
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.enabletestbus(1'b1),
	.nonusertocmu(wire_cal_blk0_nonusertocmu),
	.powerdn(cal_blk_powerdown)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.testctrl(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	stratixiv_hssi_calibration_block   cal_blk1
	( 
	.calibrationstatus(),
	.clk(cal_blk_clk),
	.enabletestbus(1'b1),
	.nonusertocmu(wire_cal_blk1_nonusertocmu),
	.powerdn(cal_blk_powerdown)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.testctrl(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	stratixiv_hssi_clock_divider   central_clk_div0
	( 
	.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
	.analogfastrefclkoutshifted(),
	.analogrefclkout(wire_central_clk_div0_analogrefclkout),
	.analogrefclkoutshifted(),
	.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
	.analogrefclkpulseshifted(),
	.clk0in(clk_div_clk0in[3:0]),
	.coreclkout(wire_central_clk_div0_coreclkout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(cent_unit_cmudividerdprioout[499:400]),
	.dprioout(wire_central_clk_div0_dprioout),
	.powerdn(cent_unit_clkdivpowerdn[0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitch(int_autospdx4rateswitchout[0]),
	.rateswitchbaseclock(wire_central_clk_div0_rateswitchbaseclock),
	.rateswitchdone(wire_central_clk_div0_rateswitchdone),
	.rateswitchout(),
	.refclkout(wire_central_clk_div0_refclkout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.clk1in({4{1'b0}}),
	.rateswitchbaseclkin({2{1'b0}}),
	.rateswitchdonein({2{1'b0}}),
	.refclkdig(1'b0),
	.refclkin({2{1'b0}}),
	.vcobypassin(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		central_clk_div0.divide_by = 5,
		central_clk_div0.divider_type = "CENTRAL_ENHANCED",
		central_clk_div0.effective_data_rate = "5000 Mbps",
		central_clk_div0.enable_dynamic_divider = "true",
		central_clk_div0.enable_refclk_out = "true",
		central_clk_div0.inclk_select = 0,
		central_clk_div0.logical_channel_address = 0,
		central_clk_div0.pre_divide_by = 1,
		central_clk_div0.refclkin_select = 0,
		central_clk_div0.select_local_rate_switch_base_clock = "true",
		central_clk_div0.select_local_rate_switch_done = "true",
		central_clk_div0.select_local_refclk = "true",
		central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
		central_clk_div0.sim_analogrefclkout_phase_shift = 0,
		central_clk_div0.sim_coreclkout_phase_shift = 0,
		central_clk_div0.sim_refclkout_phase_shift = 0,
		central_clk_div0.use_coreclk_out_post_divider = "false",
		central_clk_div0.use_refclk_post_divider = "false",
		central_clk_div0.use_vco_bypass = "false",
		central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
	stratixiv_hssi_clock_divider   central_clk_div1
	( 
	.analogfastrefclkout(wire_central_clk_div1_analogfastrefclkout),
	.analogfastrefclkoutshifted(),
	.analogrefclkout(wire_central_clk_div1_analogrefclkout),
	.analogrefclkoutshifted(),
	.analogrefclkpulse(wire_central_clk_div1_analogrefclkpulse),
	.analogrefclkpulseshifted(),
	.clk0in(clk_div_clk0in[7:4]),
	.coreclkout(wire_central_clk_div1_coreclkout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(cent_unit_cmudividerdprioout[1099:1000]),
	.dprioout(wire_central_clk_div1_dprioout),
	.powerdn(cent_unit_clkdivpowerdn[1]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchbaseclock(wire_central_clk_div1_rateswitchbaseclock),
	.rateswitchdone(wire_central_clk_div1_rateswitchdone),
	.rateswitchdonein({{1{1'b0}}, int_hiprateswtichdone[0]}),
	.rateswitchout(),
	.refclkin({{1{1'b0}}, clk_div_pclkin[1]}),
	.refclkout(wire_central_clk_div1_refclkout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.clk1in({4{1'b0}}),
	.rateswitch(1'b0),
	.rateswitchbaseclkin({2{1'b0}}),
	.refclkdig(1'b0),
	.vcobypassin(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		central_clk_div1.divide_by = 5,
		central_clk_div1.divider_type = "CENTRAL_ENHANCED",
		central_clk_div1.effective_data_rate = "5000 Mbps",
		central_clk_div1.enable_dynamic_divider = "true",
		central_clk_div1.enable_refclk_out = "true",
		central_clk_div1.inclk_select = 0,
		central_clk_div1.logical_channel_address = 0,
		central_clk_div1.pre_divide_by = 1,
		central_clk_div1.refclkin_select = 0,
		central_clk_div1.select_local_rate_switch_done = "false",
		central_clk_div1.select_local_refclk = "false",
		central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
		central_clk_div1.sim_analogrefclkout_phase_shift = 0,
		central_clk_div1.sim_coreclkout_phase_shift = 0,
		central_clk_div1.sim_refclkout_phase_shift = 0,
		central_clk_div1.use_coreclk_out_post_divider = "false",
		central_clk_div1.use_refclk_post_divider = "false",
		central_clk_div1.use_vco_bypass = "false",
		central_clk_div1.lpm_type = "stratixiv_hssi_clock_divider";
	stratixiv_hssi_cmu   cent_unit0
	( 
	.adet({4{1'b0}}),
	.alignstatus(),
	.autospdx4configsel(wire_cent_unit0_autospdx4configsel),
	.autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
	.autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
	.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
	.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
	.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
	.cmuplldprioin(pll_cmuplldprioout[1799:0]),
	.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
	.digitaltestout(),
	.dpclk(reconfig_clk),
	.dpriodisable(reconfig_togxb_disable),
	.dpriodisableout(wire_cent_unit0_dpriodisableout),
	.dprioin(reconfig_togxb_in),
	.dprioload(reconfig_togxb_load),
	.dpriooe(),
	.dprioout(wire_cent_unit0_dprioout),
	.enabledeskew(),
	.extra10gout(),
	.fiforesetrd(),
	.fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
	.lccmutestbus(),
	.nonuserfromcal(nonusertocmu_out[0]),
	.phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
	.pllpowerdn(wire_cent_unit0_pllpowerdn),
	.pllresetout(wire_cent_unit0_pllresetout),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_cent_unit0_quadresetout),
	.rateswitch(int_rateswitch[0]),
	.rateswitchdonein(int_hiprateswtichdone[0]),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b0),
	.recovclk(1'b0),
	.refclkdividerdprioin({2{1'b0}}),
	.refclkdividerdprioout(),
	.rxadcepowerdown(),
	.rxadceresetout(),
	.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
	.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
	.rxclk(refclk_pma[0]),
	.rxcoreclk(int_rxcoreclk[0]),
	.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
	.rxcruresetout(wire_cent_unit0_rxcruresetout),
	.rxctrl({4{1'b0}}),
	.rxctrlout(),
	.rxdatain({32{1'b0}}),
	.rxdataout(),
	.rxdatavalid({4{1'b0}}),
	.rxdigitalreset({rx_digitalreset_in[3:0]}),
	.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
	.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
	.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
	.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
	.rxphfifordenable(int_rxphfifordenable[0]),
	.rxphfiforeset(int_rxphfiforeset[0]),
	.rxphfifowrdisable(rxphfifowrdisable[0]),
	.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
	.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
	.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
	.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
	.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
	.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
	.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
	.rxrunningdisp({4{1'b0}}),
	.scanout(),
	.syncstatus({4{1'b0}}),
	.testout(),
	.txanalogresetout(wire_cent_unit0_txanalogresetout),
	.txclk(refclk_pma[0]),
	.txcoreclk(int_txcoreclk[0]),
	.txctrl({4{1'b0}}),
	.txctrlout(wire_cent_unit0_txctrlout),
	.txdatain({32{1'b0}}),
	.txdataout(wire_cent_unit0_txdataout),
	.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
	.txdigitalreset({tx_digitalreset_in[3:0]}),
	.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
	.txdividerpowerdown(),
	.txobpowerdown(wire_cent_unit0_txobpowerdown),
	.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
	.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
	.txphfiforddisable(int_txphfiforddisable[0]),
	.txphfiforeset(int_txphfiforeset[0]),
	.txphfifowrenable(int_txphfifowrenable[0]),
	.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
	.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
	.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
	.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
	.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
	.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
	.txpmadprioout(wire_cent_unit0_txpmadprioout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({7{1'b0}}),
	.lccmurtestbussel({3{1'b0}}),
	.pmacramtest(1'b0),
	.scanclk(1'b0),
	.scanin({23{1'b0}}),
	.scanmode(1'b0),
	.scanshift(1'b0),
	.testin({10000{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
		cent_unit0.auto_spd_phystatus_notify_count = 14,
		cent_unit0.bonded_quad_mode = "driver",
		cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
		cent_unit0.in_xaui_mode = "false",
		cent_unit0.offset_all_errors_align = "false",
		cent_unit0.pipe_auto_speed_nego_enable = "true",
		cent_unit0.pipe_freq_scale_mode = "Frequency",
		cent_unit0.pma_done_count = 249950,
		cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
		cent_unit0.rx0_auto_spd_self_switch_enable = "true",
		cent_unit0.rx0_channel_bonding = "x8",
		cent_unit0.rx0_clk1_mux_select = "recovered clock",
		cent_unit0.rx0_clk2_mux_select = "digital reference clock",
		cent_unit0.rx0_ph_fifo_reg_mode = "true",
		cent_unit0.rx0_rd_clk_mux_select = "int clock",
		cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
		cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
		cent_unit0.rx0_use_double_data_mode = "false",
		cent_unit0.tx0_auto_spd_self_switch_enable = "true",
		cent_unit0.tx0_channel_bonding = "x8",
		cent_unit0.tx0_ph_fifo_reg_mode = "true",
		cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
		cent_unit0.tx0_use_double_data_mode = "false",
		cent_unit0.tx0_wr_clk_mux_select = "int_clk",
		cent_unit0.use_deskew_fifo = "false",
		cent_unit0.vcceh_voltage = "Auto",
		cent_unit0.lpm_type = "stratixiv_hssi_cmu";
	stratixiv_hssi_cmu   cent_unit1
	( 
	.adet({4{1'b0}}),
	.alignstatus(),
	.autospdx4configsel(wire_cent_unit1_autospdx4configsel),
	.autospdx4rateswitchout(wire_cent_unit1_autospdx4rateswitchout),
	.autospdx4spdchg(wire_cent_unit1_autospdx4spdchg),
	.clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
	.cmudividerdprioin({clk_div_cmudividerdprioin[1199:600]}),
	.cmudividerdprioout(wire_cent_unit1_cmudividerdprioout),
	.cmuplldprioin(pll_cmuplldprioout[3599:1800]),
	.cmuplldprioout(wire_cent_unit1_cmuplldprioout),
	.digitaltestout(),
	.dpclk(reconfig_clk),
	.dpriodisable(reconfig_togxb_disable),
	.dpriodisableout(wire_cent_unit1_dpriodisableout),
	.dprioin(reconfig_togxb_in),
	.dprioload(reconfig_togxb_load),
	.dpriooe(),
	.dprioout(wire_cent_unit1_dprioout),
	.enabledeskew(),
	.extra10gout(),
	.fiforesetrd(),
	.fixedclk({{2{1'b0}}, fixedclk_to_cmu[9:6]}),
	.lccmutestbus(),
	.nonuserfromcal(nonusertocmu_out[1]),
	.phfifiox4ptrsreset(wire_cent_unit1_phfifiox4ptrsreset),
	.pllpowerdn(wire_cent_unit1_pllpowerdn),
	.pllresetout(wire_cent_unit1_pllresetout),
	.quadreset(gxb_powerdown[0]),
	.quadresetout(wire_cent_unit1_quadresetout),
	.rateswitch(int_rateswitch[1]),
	.rateswitchdonein(int_hiprateswtichdone[1]),
	.rdalign({4{1'b0}}),
	.rdenablesync(1'b0),
	.recovclk(1'b0),
	.refclkdividerdprioin({2{1'b0}}),
	.refclkdividerdprioout(),
	.rxadcepowerdown(),
	.rxadceresetout(),
	.rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
	.rxanalogresetout(wire_cent_unit1_rxanalogresetout),
	.rxclk(refclk_pma[1]),
	.rxcoreclk(int_rxcoreclk[1]),
	.rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
	.rxcruresetout(wire_cent_unit1_rxcruresetout),
	.rxctrl({4{1'b0}}),
	.rxctrlout(),
	.rxdatain({32{1'b0}}),
	.rxdataout(),
	.rxdatavalid({4{1'b0}}),
	.rxdigitalreset({rx_digitalreset_in[7:4]}),
	.rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
	.rxibpowerdown(wire_cent_unit1_rxibpowerdown),
	.rxpcsdprioin({cent_unit_rxpcsdprioin[3199:1600]}),
	.rxpcsdprioout(wire_cent_unit1_rxpcsdprioout),
	.rxphfifordenable(int_rxphfifordenable[1]),
	.rxphfiforeset(int_rxphfiforeset[1]),
	.rxphfifowrdisable(rxphfifowrdisable[1]),
	.rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
	.rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
	.rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
	.rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
	.rxpmadprioin({cent_unit_rxpmadprioin[3599:1800]}),
	.rxpmadprioout(wire_cent_unit1_rxpmadprioout),
	.rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
	.rxrunningdisp({4{1'b0}}),
	.scanout(),
	.syncstatus({4{1'b0}}),
	.testout(),
	.txanalogresetout(wire_cent_unit1_txanalogresetout),
	.txclk(refclk_pma[1]),
	.txcoreclk(int_txcoreclk[1]),
	.txctrl({4{1'b0}}),
	.txctrlout(wire_cent_unit1_txctrlout),
	.txdatain({32{1'b0}}),
	.txdataout(wire_cent_unit1_txdataout),
	.txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
	.txdigitalreset({tx_digitalreset_in[7:4]}),
	.txdigitalresetout(wire_cent_unit1_txdigitalresetout),
	.txdividerpowerdown(),
	.txobpowerdown(wire_cent_unit1_txobpowerdown),
	.txpcsdprioin({cent_unit_tx_dprioin[1199:600]}),
	.txpcsdprioout(wire_cent_unit1_txpcsdprioout),
	.txphfiforddisable(int_txphfiforddisable[1]),
	.txphfiforeset(int_txphfiforeset[1]),
	.txphfifowrenable(int_txphfifowrenable[1]),
	.txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
	.txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
	.txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
	.txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
	.txpmadprioin({cent_unit_txpmadprioin[3599:1800]}),
	.txpmadprioout(wire_cent_unit1_txpmadprioout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({7{1'b0}}),
	.lccmurtestbussel({3{1'b0}}),
	.pmacramtest(1'b0),
	.scanclk(1'b0),
	.scanin({23{1'b0}}),
	.scanmode(1'b0),
	.scanshift(1'b0),
	.testin({10000{1'b0}}),
	.txpllreset({2{1'b0}})
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
		cent_unit1.auto_spd_phystatus_notify_count = 14,
		cent_unit1.bonded_quad_mode = "receiver",
		cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
		cent_unit1.in_xaui_mode = "false",
		cent_unit1.offset_all_errors_align = "false",
		cent_unit1.pipe_auto_speed_nego_enable = "true",
		cent_unit1.pipe_freq_scale_mode = "Frequency",
		cent_unit1.pma_done_count = 249950,
		cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
		cent_unit1.rx0_auto_spd_self_switch_enable = "true",
		cent_unit1.rx0_channel_bonding = "x8",
		cent_unit1.rx0_clk1_mux_select = "recovered clock",
		cent_unit1.rx0_clk2_mux_select = "digital reference clock",
		cent_unit1.rx0_ph_fifo_reg_mode = "true",
		cent_unit1.rx0_rd_clk_mux_select = "int clock",
		cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
		cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
		cent_unit1.rx0_use_double_data_mode = "false",
		cent_unit1.tx0_auto_spd_self_switch_enable = "true",
		cent_unit1.tx0_channel_bonding = "x8",
		cent_unit1.tx0_ph_fifo_reg_mode = "true",
		cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
		cent_unit1.tx0_use_double_data_mode = "false",
		cent_unit1.tx0_wr_clk_mux_select = "int_clk",
		cent_unit1.use_deskew_fifo = "false",
		cent_unit1.vcceh_voltage = "Auto",
		cent_unit1.lpm_type = "stratixiv_hssi_cmu";
	stratixiv_hssi_pll   rx_cdr_pll0
	( 
	.areset(rx_rxcruresetout[0]),
	.clk(wire_rx_cdr_pll0_clk),
	.datain(rx_pma_dataout[0]),
	.dataout(wire_rx_cdr_pll0_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rxpll_dprioin[299:0]),
	.dprioout(wire_rx_cdr_pll0_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
	.freqlocked(wire_rx_cdr_pll0_freqlocked),
	.inclk({rx_cruclk_in[9:0]}),
	.locked(wire_rx_cdr_pll0_locked),
	.locktorefclk(rx_pma_locktorefout[0]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[0]),
	.rateswitch(int_hipautospdrateswitchout[0]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll0.bandwidth_type = "Auto",
		rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
		rx_cdr_pll0.dprio_config_mode = 6'h00,
		rx_cdr_pll0.effective_data_rate = "5000 Mbps",
		rx_cdr_pll0.enable_dynamic_divider = "true",
		rx_cdr_pll0.fast_lock_control = "false",
		rx_cdr_pll0.inclk0_input_period = 10000,
		rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll0.m = 25,
		rx_cdr_pll0.n = 1,
		rx_cdr_pll0.pfd_clk_select = 0,
		rx_cdr_pll0.pll_type = "RX CDR",
		rx_cdr_pll0.use_refclk_pin = "false",
		rx_cdr_pll0.vco_post_scale = 1,
		rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll1
	( 
	.areset(rx_rxcruresetout[1]),
	.clk(wire_rx_cdr_pll1_clk),
	.datain(rx_pma_dataout[1]),
	.dataout(wire_rx_cdr_pll1_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rxpll_dprioin[599:300]),
	.dprioout(wire_rx_cdr_pll1_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
	.freqlocked(wire_rx_cdr_pll1_freqlocked),
	.inclk({rx_cruclk_in[19:10]}),
	.locked(wire_rx_cdr_pll1_locked),
	.locktorefclk(rx_pma_locktorefout[1]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[1]),
	.rateswitch(int_hipautospdrateswitchout[1]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll1.bandwidth_type = "Auto",
		rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
		rx_cdr_pll1.dprio_config_mode = 6'h00,
		rx_cdr_pll1.effective_data_rate = "5000 Mbps",
		rx_cdr_pll1.enable_dynamic_divider = "true",
		rx_cdr_pll1.fast_lock_control = "false",
		rx_cdr_pll1.inclk0_input_period = 10000,
		rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll1.m = 25,
		rx_cdr_pll1.n = 1,
		rx_cdr_pll1.pfd_clk_select = 0,
		rx_cdr_pll1.pll_type = "RX CDR",
		rx_cdr_pll1.use_refclk_pin = "false",
		rx_cdr_pll1.vco_post_scale = 1,
		rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll2
	( 
	.areset(rx_rxcruresetout[2]),
	.clk(wire_rx_cdr_pll2_clk),
	.datain(rx_pma_dataout[2]),
	.dataout(wire_rx_cdr_pll2_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rxpll_dprioin[899:600]),
	.dprioout(wire_rx_cdr_pll2_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
	.freqlocked(wire_rx_cdr_pll2_freqlocked),
	.inclk({rx_cruclk_in[29:20]}),
	.locked(wire_rx_cdr_pll2_locked),
	.locktorefclk(rx_pma_locktorefout[2]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[2]),
	.rateswitch(int_hipautospdrateswitchout[2]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll2.bandwidth_type = "Auto",
		rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
		rx_cdr_pll2.dprio_config_mode = 6'h00,
		rx_cdr_pll2.effective_data_rate = "5000 Mbps",
		rx_cdr_pll2.enable_dynamic_divider = "true",
		rx_cdr_pll2.fast_lock_control = "false",
		rx_cdr_pll2.inclk0_input_period = 10000,
		rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll2.m = 25,
		rx_cdr_pll2.n = 1,
		rx_cdr_pll2.pfd_clk_select = 0,
		rx_cdr_pll2.pll_type = "RX CDR",
		rx_cdr_pll2.use_refclk_pin = "false",
		rx_cdr_pll2.vco_post_scale = 1,
		rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll3
	( 
	.areset(rx_rxcruresetout[3]),
	.clk(wire_rx_cdr_pll3_clk),
	.datain(rx_pma_dataout[3]),
	.dataout(wire_rx_cdr_pll3_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rxpll_dprioin[1199:900]),
	.dprioout(wire_rx_cdr_pll3_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
	.freqlocked(wire_rx_cdr_pll3_freqlocked),
	.inclk({rx_cruclk_in[39:30]}),
	.locked(wire_rx_cdr_pll3_locked),
	.locktorefclk(rx_pma_locktorefout[3]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[3]),
	.rateswitch(int_hipautospdrateswitchout[3]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll3.bandwidth_type = "Auto",
		rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
		rx_cdr_pll3.dprio_config_mode = 6'h00,
		rx_cdr_pll3.effective_data_rate = "5000 Mbps",
		rx_cdr_pll3.enable_dynamic_divider = "true",
		rx_cdr_pll3.fast_lock_control = "false",
		rx_cdr_pll3.inclk0_input_period = 10000,
		rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll3.m = 25,
		rx_cdr_pll3.n = 1,
		rx_cdr_pll3.pfd_clk_select = 0,
		rx_cdr_pll3.pll_type = "RX CDR",
		rx_cdr_pll3.use_refclk_pin = "false",
		rx_cdr_pll3.vco_post_scale = 1,
		rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll4
	( 
	.areset(rx_rxcruresetout[6]),
	.clk(wire_rx_cdr_pll4_clk),
	.datain(rx_pma_dataout[4]),
	.dataout(wire_rx_cdr_pll4_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rxpll_dprioin[2099:1800]),
	.dprioout(wire_rx_cdr_pll4_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[4]),
	.freqlocked(wire_rx_cdr_pll4_freqlocked),
	.inclk({rx_cruclk_in[49:40]}),
	.locked(wire_rx_cdr_pll4_locked),
	.locktorefclk(rx_pma_locktorefout[4]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[6]),
	.rateswitch(int_hipautospdrateswitchout[4]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll4.bandwidth_type = "Auto",
		rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
		rx_cdr_pll4.dprio_config_mode = 6'h00,
		rx_cdr_pll4.effective_data_rate = "5000 Mbps",
		rx_cdr_pll4.enable_dynamic_divider = "true",
		rx_cdr_pll4.fast_lock_control = "false",
		rx_cdr_pll4.inclk0_input_period = 10000,
		rx_cdr_pll4.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll4.m = 25,
		rx_cdr_pll4.n = 1,
		rx_cdr_pll4.pfd_clk_select = 0,
		rx_cdr_pll4.pll_type = "RX CDR",
		rx_cdr_pll4.use_refclk_pin = "false",
		rx_cdr_pll4.vco_post_scale = 1,
		rx_cdr_pll4.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll5
	( 
	.areset(rx_rxcruresetout[7]),
	.clk(wire_rx_cdr_pll5_clk),
	.datain(rx_pma_dataout[5]),
	.dataout(wire_rx_cdr_pll5_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rxpll_dprioin[2399:2100]),
	.dprioout(wire_rx_cdr_pll5_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[5]),
	.freqlocked(wire_rx_cdr_pll5_freqlocked),
	.inclk({rx_cruclk_in[59:50]}),
	.locked(wire_rx_cdr_pll5_locked),
	.locktorefclk(rx_pma_locktorefout[5]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[7]),
	.rateswitch(int_hipautospdrateswitchout[5]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll5.bandwidth_type = "Auto",
		rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
		rx_cdr_pll5.dprio_config_mode = 6'h00,
		rx_cdr_pll5.effective_data_rate = "5000 Mbps",
		rx_cdr_pll5.enable_dynamic_divider = "true",
		rx_cdr_pll5.fast_lock_control = "false",
		rx_cdr_pll5.inclk0_input_period = 10000,
		rx_cdr_pll5.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll5.m = 25,
		rx_cdr_pll5.n = 1,
		rx_cdr_pll5.pfd_clk_select = 0,
		rx_cdr_pll5.pll_type = "RX CDR",
		rx_cdr_pll5.use_refclk_pin = "false",
		rx_cdr_pll5.vco_post_scale = 1,
		rx_cdr_pll5.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll6
	( 
	.areset(rx_rxcruresetout[8]),
	.clk(wire_rx_cdr_pll6_clk),
	.datain(rx_pma_dataout[6]),
	.dataout(wire_rx_cdr_pll6_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rxpll_dprioin[2699:2400]),
	.dprioout(wire_rx_cdr_pll6_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[6]),
	.freqlocked(wire_rx_cdr_pll6_freqlocked),
	.inclk({rx_cruclk_in[69:60]}),
	.locked(wire_rx_cdr_pll6_locked),
	.locktorefclk(rx_pma_locktorefout[6]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[8]),
	.rateswitch(int_hipautospdrateswitchout[6]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll6.bandwidth_type = "Auto",
		rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
		rx_cdr_pll6.dprio_config_mode = 6'h00,
		rx_cdr_pll6.effective_data_rate = "5000 Mbps",
		rx_cdr_pll6.enable_dynamic_divider = "true",
		rx_cdr_pll6.fast_lock_control = "false",
		rx_cdr_pll6.inclk0_input_period = 10000,
		rx_cdr_pll6.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll6.m = 25,
		rx_cdr_pll6.n = 1,
		rx_cdr_pll6.pfd_clk_select = 0,
		rx_cdr_pll6.pll_type = "RX CDR",
		rx_cdr_pll6.use_refclk_pin = "false",
		rx_cdr_pll6.vco_post_scale = 1,
		rx_cdr_pll6.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   rx_cdr_pll7
	( 
	.areset(rx_rxcruresetout[9]),
	.clk(wire_rx_cdr_pll7_clk),
	.datain(rx_pma_dataout[7]),
	.dataout(wire_rx_cdr_pll7_dataout),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rxpll_dprioin[2999:2700]),
	.dprioout(wire_rx_cdr_pll7_dprioout),
	.earlyeios(int_rxpcs_cdrctrlearlyeios[7]),
	.freqlocked(wire_rx_cdr_pll7_freqlocked),
	.inclk({rx_cruclk_in[79:70]}),
	.locked(wire_rx_cdr_pll7_locked),
	.locktorefclk(rx_pma_locktorefout[7]),
	.pfdfbclkout(),
	.pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
	.powerdown(cent_unit_rxcrupowerdn[9]),
	.rateswitch(int_hipautospdrateswitchout[7]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.extra10gin({6{1'b0}}),
	.pfdfbclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		rx_cdr_pll7.bandwidth_type = "Auto",
		rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
		rx_cdr_pll7.dprio_config_mode = 6'h00,
		rx_cdr_pll7.effective_data_rate = "5000 Mbps",
		rx_cdr_pll7.enable_dynamic_divider = "true",
		rx_cdr_pll7.fast_lock_control = "false",
		rx_cdr_pll7.inclk0_input_period = 10000,
		rx_cdr_pll7.input_clock_frequency = "100.0 MHz",
		rx_cdr_pll7.m = 25,
		rx_cdr_pll7.n = 1,
		rx_cdr_pll7.pfd_clk_select = 0,
		rx_cdr_pll7.pll_type = "RX CDR",
		rx_cdr_pll7.use_refclk_pin = "false",
		rx_cdr_pll7.vco_post_scale = 1,
		rx_cdr_pll7.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_pll   tx_pll0
	( 
	.areset(pllreset_in[0]),
	.clk(wire_tx_pll0_clk),
	.dataout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(pll0_dprioin[299:0]),
	.dprioout(wire_tx_pll0_dprioout),
	.freqlocked(),
	.inclk({pll0_clkin[9:0]}),
	.locked(wire_tx_pll0_locked),
	.pfdfbclkout(),
	.pfdrefclkout(),
	.powerdown(pllpowerdn_in[0]),
	.vcobypassout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datain(1'b0),
	.earlyeios(1'b0),
	.extra10gin({6{1'b0}}),
	.locktorefclk(1'b1),
	.pfdfbclk(1'b0),
	.rateswitch(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		tx_pll0.bandwidth_type = "High",
		tx_pll0.channel_num = 4,
		tx_pll0.dprio_config_mode = 6'h00,
		tx_pll0.inclk0_input_period = 10000,
		tx_pll0.input_clock_frequency = "100.0 MHz",
		tx_pll0.logical_tx_pll_number = 0,
		tx_pll0.m = 25,
		tx_pll0.n = 1,
		tx_pll0.pfd_clk_select = 0,
		tx_pll0.pfd_fb_select = "internal",
		tx_pll0.pll_type = "CMU",
		tx_pll0.use_refclk_pin = "false",
		tx_pll0.vco_post_scale = 1,
		tx_pll0.lpm_type = "stratixiv_hssi_pll";
	stratixiv_hssi_rx_pcs   receive_pcs0
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs0_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs0_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[19:0]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[0]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pcsdprioin_wire[399:0]),
	.dprioout(wire_receive_pcs0_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[0]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[0]),
	.hipdataout(wire_receive_pcs0_hipdataout),
	.hipdatavalid(wire_receive_pcs0_hipdatavalid),
	.hipelecidle(wire_receive_pcs0_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs0_hipphydonestatus),
	.hippowerdown(powerdn[1:0]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs0_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[1:0]),
	.iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs0_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[1:0]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[0]),
	.phfifordenableout(wire_receive_pcs0_phfifordenableout),
	.phfiforeset(rx_phfiforeset[0]),
	.phfiforesetout(wire_receive_pcs0_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[0]),
	.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[1:0]),
	.pipepowerstate(tx_pipepowerstateout[3:0]),
	.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(wire_receive_pcs0_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[0]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[0]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[0]),
	.rxfound(rx_pcs_rxfound_wire[1:0]),
	.signaldetect(wire_receive_pcs0_signaldetect),
	.signaldetected(rx_signaldetect_wire[0]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs0.align_pattern = "0101111100",
		receive_pcs0.align_pattern_length = 10,
		receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs0.allow_align_polarity_inversion = "false",
		receive_pcs0.allow_pipe_polarity_inversion = "true",
		receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs0.auto_spd_phystatus_notify_count = 14,
		receive_pcs0.auto_spd_self_switch_enable = "true",
		receive_pcs0.bit_slip_enable = "false",
		receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs0.byte_order_mode = "none",
		receive_pcs0.byte_order_pad_pattern = "0",
		receive_pcs0.byte_order_pattern = "0",
		receive_pcs0.byte_order_pld_ctrl_enable = "false",
		receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs0.cdrctrl_cid_mode_enable = "true",
		receive_pcs0.cdrctrl_enable = "true",
		receive_pcs0.cdrctrl_rxvalid_mask = "true",
		receive_pcs0.channel_bonding = "x8",
		receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
		receive_pcs0.channel_width = 8,
		receive_pcs0.clk1_mux_select = "recovered clock",
		receive_pcs0.clk2_mux_select = "digital reference clock",
		receive_pcs0.core_clock_0ppm = "false",
		receive_pcs0.datapath_low_latency_mode = "false",
		receive_pcs0.datapath_protocol = "pipe",
		receive_pcs0.dec_8b_10b_compatibility_mode = "true",
		receive_pcs0.dec_8b_10b_mode = "normal",
		receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs0.deskew_pattern = "0",
		receive_pcs0.disable_auto_idle_insertion = "false",
		receive_pcs0.disable_running_disp_in_word_align = "false",
		receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs0.dprio_config_mode = 6'h01,
		receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs0.elec_idle_infer_enable = "false",
		receive_pcs0.elec_idle_num_com_detect = 3,
		receive_pcs0.enable_bit_reversal = "false",
		receive_pcs0.enable_deep_align = "false",
		receive_pcs0.enable_deep_align_byte_swap = "false",
		receive_pcs0.enable_self_test_mode = "false",
		receive_pcs0.enable_true_complement_match_in_word_align = "false",
		receive_pcs0.force_signal_detect_dig = "true",
		receive_pcs0.hip_enable = "true",
		receive_pcs0.infiniband_invalid_code = 0,
		receive_pcs0.insert_pad_on_underflow = "false",
		receive_pcs0.logical_channel_address = (starting_channel_number + 0),
		receive_pcs0.num_align_code_groups_in_ordered_set = 0,
		receive_pcs0.num_align_cons_good_data = 16,
		receive_pcs0.num_align_cons_pat = 4,
		receive_pcs0.num_align_loss_sync_error = 17,
		receive_pcs0.ph_fifo_low_latency_enable = "true",
		receive_pcs0.ph_fifo_reg_mode = "true",
		receive_pcs0.ph_fifo_xn_mapping0 = "none",
		receive_pcs0.ph_fifo_xn_mapping1 = "none",
		receive_pcs0.ph_fifo_xn_mapping2 = "central",
		receive_pcs0.ph_fifo_xn_select = 2,
		receive_pcs0.pipe_auto_speed_nego_enable = "true",
		receive_pcs0.pipe_freq_scale_mode = "Frequency",
		receive_pcs0.pma_done_count = 249950,
		receive_pcs0.protocol_hint = "pcie2",
		receive_pcs0.rate_match_almost_empty_threshold = 11,
		receive_pcs0.rate_match_almost_full_threshold = 13,
		receive_pcs0.rate_match_back_to_back = "false",
		receive_pcs0.rate_match_delete_threshold = 13,
		receive_pcs0.rate_match_empty_threshold = 5,
		receive_pcs0.rate_match_fifo_mode = "true",
		receive_pcs0.rate_match_full_threshold = 20,
		receive_pcs0.rate_match_insert_threshold = 11,
		receive_pcs0.rate_match_ordered_set_based = "false",
		receive_pcs0.rate_match_pattern1 = "11010000111010000011",
		receive_pcs0.rate_match_pattern2 = "00101111000101111100",
		receive_pcs0.rate_match_pattern_size = 20,
		receive_pcs0.rate_match_pipe_enable = "true",
		receive_pcs0.rate_match_reset_enable = "false",
		receive_pcs0.rate_match_skip_set_based = "true",
		receive_pcs0.rate_match_start_threshold = 7,
		receive_pcs0.rd_clk_mux_select = "int clock",
		receive_pcs0.recovered_clk_mux_select = "recovered clock",
		receive_pcs0.run_length = 40,
		receive_pcs0.run_length_enable = "true",
		receive_pcs0.rx_detect_bypass = "false",
		receive_pcs0.rx_phfifo_wait_cnt = 32,
		receive_pcs0.rxstatus_error_report_mode = 1,
		receive_pcs0.self_test_mode = "incremental",
		receive_pcs0.use_alignment_state_machine = "true",
		receive_pcs0.use_deserializer_double_data_mode = "false",
		receive_pcs0.use_deskew_fifo = "false",
		receive_pcs0.use_double_data_mode = "false",
		receive_pcs0.use_parallel_loopback = "false",
		receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs1
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs1_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs1_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[39:20]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[1]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pcsdprioin_wire[799:400]),
	.dprioout(wire_receive_pcs1_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[1]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[1]),
	.hipdataout(wire_receive_pcs1_hipdataout),
	.hipdatavalid(wire_receive_pcs1_hipdatavalid),
	.hipelecidle(wire_receive_pcs1_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs1_hipphydonestatus),
	.hippowerdown(powerdn[3:2]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs1_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[3:2]),
	.iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs1_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[3:2]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[1]),
	.phfifordenableout(wire_receive_pcs1_phfifordenableout),
	.phfiforeset(rx_phfiforeset[1]),
	.phfiforesetout(wire_receive_pcs1_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[1]),
	.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[3:2]),
	.pipepowerstate(tx_pipepowerstateout[7:4]),
	.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[1]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(wire_receive_pcs1_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[1]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[1]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[1]),
	.rxfound(rx_pcs_rxfound_wire[3:2]),
	.signaldetect(wire_receive_pcs1_signaldetect),
	.signaldetected(rx_signaldetect_wire[1]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs1.align_pattern = "0101111100",
		receive_pcs1.align_pattern_length = 10,
		receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs1.allow_align_polarity_inversion = "false",
		receive_pcs1.allow_pipe_polarity_inversion = "true",
		receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs1.auto_spd_phystatus_notify_count = 14,
		receive_pcs1.auto_spd_self_switch_enable = "true",
		receive_pcs1.bit_slip_enable = "false",
		receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs1.byte_order_mode = "none",
		receive_pcs1.byte_order_pad_pattern = "0",
		receive_pcs1.byte_order_pattern = "0",
		receive_pcs1.byte_order_pld_ctrl_enable = "false",
		receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs1.cdrctrl_cid_mode_enable = "true",
		receive_pcs1.cdrctrl_enable = "true",
		receive_pcs1.cdrctrl_rxvalid_mask = "true",
		receive_pcs1.channel_bonding = "x8",
		receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
		receive_pcs1.channel_width = 8,
		receive_pcs1.clk1_mux_select = "recovered clock",
		receive_pcs1.clk2_mux_select = "digital reference clock",
		receive_pcs1.core_clock_0ppm = "false",
		receive_pcs1.datapath_low_latency_mode = "false",
		receive_pcs1.datapath_protocol = "pipe",
		receive_pcs1.dec_8b_10b_compatibility_mode = "true",
		receive_pcs1.dec_8b_10b_mode = "normal",
		receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs1.deskew_pattern = "0",
		receive_pcs1.disable_auto_idle_insertion = "false",
		receive_pcs1.disable_running_disp_in_word_align = "false",
		receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs1.dprio_config_mode = 6'h01,
		receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs1.elec_idle_infer_enable = "false",
		receive_pcs1.elec_idle_num_com_detect = 3,
		receive_pcs1.enable_bit_reversal = "false",
		receive_pcs1.enable_deep_align = "false",
		receive_pcs1.enable_deep_align_byte_swap = "false",
		receive_pcs1.enable_self_test_mode = "false",
		receive_pcs1.enable_true_complement_match_in_word_align = "false",
		receive_pcs1.force_signal_detect_dig = "true",
		receive_pcs1.hip_enable = "true",
		receive_pcs1.infiniband_invalid_code = 0,
		receive_pcs1.insert_pad_on_underflow = "false",
		receive_pcs1.logical_channel_address = (starting_channel_number + 1),
		receive_pcs1.num_align_code_groups_in_ordered_set = 0,
		receive_pcs1.num_align_cons_good_data = 16,
		receive_pcs1.num_align_cons_pat = 4,
		receive_pcs1.num_align_loss_sync_error = 17,
		receive_pcs1.ph_fifo_low_latency_enable = "true",
		receive_pcs1.ph_fifo_reg_mode = "true",
		receive_pcs1.ph_fifo_xn_mapping0 = "none",
		receive_pcs1.ph_fifo_xn_mapping1 = "none",
		receive_pcs1.ph_fifo_xn_mapping2 = "central",
		receive_pcs1.ph_fifo_xn_select = 2,
		receive_pcs1.pipe_auto_speed_nego_enable = "true",
		receive_pcs1.pipe_freq_scale_mode = "Frequency",
		receive_pcs1.pma_done_count = 249950,
		receive_pcs1.protocol_hint = "pcie2",
		receive_pcs1.rate_match_almost_empty_threshold = 11,
		receive_pcs1.rate_match_almost_full_threshold = 13,
		receive_pcs1.rate_match_back_to_back = "false",
		receive_pcs1.rate_match_delete_threshold = 13,
		receive_pcs1.rate_match_empty_threshold = 5,
		receive_pcs1.rate_match_fifo_mode = "true",
		receive_pcs1.rate_match_full_threshold = 20,
		receive_pcs1.rate_match_insert_threshold = 11,
		receive_pcs1.rate_match_ordered_set_based = "false",
		receive_pcs1.rate_match_pattern1 = "11010000111010000011",
		receive_pcs1.rate_match_pattern2 = "00101111000101111100",
		receive_pcs1.rate_match_pattern_size = 20,
		receive_pcs1.rate_match_pipe_enable = "true",
		receive_pcs1.rate_match_reset_enable = "false",
		receive_pcs1.rate_match_skip_set_based = "true",
		receive_pcs1.rate_match_start_threshold = 7,
		receive_pcs1.rd_clk_mux_select = "int clock",
		receive_pcs1.recovered_clk_mux_select = "recovered clock",
		receive_pcs1.run_length = 40,
		receive_pcs1.run_length_enable = "true",
		receive_pcs1.rx_detect_bypass = "false",
		receive_pcs1.rx_phfifo_wait_cnt = 32,
		receive_pcs1.rxstatus_error_report_mode = 1,
		receive_pcs1.self_test_mode = "incremental",
		receive_pcs1.use_alignment_state_machine = "true",
		receive_pcs1.use_deserializer_double_data_mode = "false",
		receive_pcs1.use_deskew_fifo = "false",
		receive_pcs1.use_double_data_mode = "false",
		receive_pcs1.use_parallel_loopback = "false",
		receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs2
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs2_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs2_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[59:40]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[2]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pcsdprioin_wire[1199:800]),
	.dprioout(wire_receive_pcs2_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[2]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[2]),
	.hipdataout(wire_receive_pcs2_hipdataout),
	.hipdatavalid(wire_receive_pcs2_hipdatavalid),
	.hipelecidle(wire_receive_pcs2_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs2_hipphydonestatus),
	.hippowerdown(powerdn[5:4]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs2_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[5:4]),
	.iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs2_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[5:4]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[2]),
	.phfifordenableout(wire_receive_pcs2_phfifordenableout),
	.phfiforeset(rx_phfiforeset[2]),
	.phfiforesetout(wire_receive_pcs2_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[2]),
	.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[5:4]),
	.pipepowerstate(tx_pipepowerstateout[11:8]),
	.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[2]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(wire_receive_pcs2_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[2]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[2]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[2]),
	.rxfound(rx_pcs_rxfound_wire[5:4]),
	.signaldetect(wire_receive_pcs2_signaldetect),
	.signaldetected(rx_signaldetect_wire[2]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs2.align_pattern = "0101111100",
		receive_pcs2.align_pattern_length = 10,
		receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs2.allow_align_polarity_inversion = "false",
		receive_pcs2.allow_pipe_polarity_inversion = "true",
		receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs2.auto_spd_phystatus_notify_count = 14,
		receive_pcs2.auto_spd_self_switch_enable = "true",
		receive_pcs2.bit_slip_enable = "false",
		receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs2.byte_order_mode = "none",
		receive_pcs2.byte_order_pad_pattern = "0",
		receive_pcs2.byte_order_pattern = "0",
		receive_pcs2.byte_order_pld_ctrl_enable = "false",
		receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs2.cdrctrl_cid_mode_enable = "true",
		receive_pcs2.cdrctrl_enable = "true",
		receive_pcs2.cdrctrl_rxvalid_mask = "true",
		receive_pcs2.channel_bonding = "x8",
		receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
		receive_pcs2.channel_width = 8,
		receive_pcs2.clk1_mux_select = "recovered clock",
		receive_pcs2.clk2_mux_select = "digital reference clock",
		receive_pcs2.core_clock_0ppm = "false",
		receive_pcs2.datapath_low_latency_mode = "false",
		receive_pcs2.datapath_protocol = "pipe",
		receive_pcs2.dec_8b_10b_compatibility_mode = "true",
		receive_pcs2.dec_8b_10b_mode = "normal",
		receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs2.deskew_pattern = "0",
		receive_pcs2.disable_auto_idle_insertion = "false",
		receive_pcs2.disable_running_disp_in_word_align = "false",
		receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs2.dprio_config_mode = 6'h01,
		receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs2.elec_idle_infer_enable = "false",
		receive_pcs2.elec_idle_num_com_detect = 3,
		receive_pcs2.enable_bit_reversal = "false",
		receive_pcs2.enable_deep_align = "false",
		receive_pcs2.enable_deep_align_byte_swap = "false",
		receive_pcs2.enable_self_test_mode = "false",
		receive_pcs2.enable_true_complement_match_in_word_align = "false",
		receive_pcs2.force_signal_detect_dig = "true",
		receive_pcs2.hip_enable = "true",
		receive_pcs2.infiniband_invalid_code = 0,
		receive_pcs2.insert_pad_on_underflow = "false",
		receive_pcs2.logical_channel_address = (starting_channel_number + 2),
		receive_pcs2.num_align_code_groups_in_ordered_set = 0,
		receive_pcs2.num_align_cons_good_data = 16,
		receive_pcs2.num_align_cons_pat = 4,
		receive_pcs2.num_align_loss_sync_error = 17,
		receive_pcs2.ph_fifo_low_latency_enable = "true",
		receive_pcs2.ph_fifo_reg_mode = "true",
		receive_pcs2.ph_fifo_xn_mapping0 = "none",
		receive_pcs2.ph_fifo_xn_mapping1 = "none",
		receive_pcs2.ph_fifo_xn_mapping2 = "central",
		receive_pcs2.ph_fifo_xn_select = 2,
		receive_pcs2.pipe_auto_speed_nego_enable = "true",
		receive_pcs2.pipe_freq_scale_mode = "Frequency",
		receive_pcs2.pma_done_count = 249950,
		receive_pcs2.protocol_hint = "pcie2",
		receive_pcs2.rate_match_almost_empty_threshold = 11,
		receive_pcs2.rate_match_almost_full_threshold = 13,
		receive_pcs2.rate_match_back_to_back = "false",
		receive_pcs2.rate_match_delete_threshold = 13,
		receive_pcs2.rate_match_empty_threshold = 5,
		receive_pcs2.rate_match_fifo_mode = "true",
		receive_pcs2.rate_match_full_threshold = 20,
		receive_pcs2.rate_match_insert_threshold = 11,
		receive_pcs2.rate_match_ordered_set_based = "false",
		receive_pcs2.rate_match_pattern1 = "11010000111010000011",
		receive_pcs2.rate_match_pattern2 = "00101111000101111100",
		receive_pcs2.rate_match_pattern_size = 20,
		receive_pcs2.rate_match_pipe_enable = "true",
		receive_pcs2.rate_match_reset_enable = "false",
		receive_pcs2.rate_match_skip_set_based = "true",
		receive_pcs2.rate_match_start_threshold = 7,
		receive_pcs2.rd_clk_mux_select = "int clock",
		receive_pcs2.recovered_clk_mux_select = "recovered clock",
		receive_pcs2.run_length = 40,
		receive_pcs2.run_length_enable = "true",
		receive_pcs2.rx_detect_bypass = "false",
		receive_pcs2.rx_phfifo_wait_cnt = 32,
		receive_pcs2.rxstatus_error_report_mode = 1,
		receive_pcs2.self_test_mode = "incremental",
		receive_pcs2.use_alignment_state_machine = "true",
		receive_pcs2.use_deserializer_double_data_mode = "false",
		receive_pcs2.use_deskew_fifo = "false",
		receive_pcs2.use_double_data_mode = "false",
		receive_pcs2.use_parallel_loopback = "false",
		receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs3
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs3_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs3_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[79:60]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[3]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pcsdprioin_wire[1599:1200]),
	.dprioout(wire_receive_pcs3_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[3]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[3]),
	.hipdataout(wire_receive_pcs3_hipdataout),
	.hipdatavalid(wire_receive_pcs3_hipdatavalid),
	.hipelecidle(wire_receive_pcs3_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs3_hipphydonestatus),
	.hippowerdown(powerdn[7:6]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs3_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[7:6]),
	.iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs3_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[7:6]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[3]),
	.phfifordenableout(wire_receive_pcs3_phfifordenableout),
	.phfiforeset(rx_phfiforeset[3]),
	.phfiforesetout(wire_receive_pcs3_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[3]),
	.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[7:6]),
	.pipepowerstate(tx_pipepowerstateout[15:12]),
	.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[3]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(wire_receive_pcs3_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[0]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[3]),
	.refclk(refclk_pma[0]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[3]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[3]),
	.rxfound(rx_pcs_rxfound_wire[7:6]),
	.signaldetect(wire_receive_pcs3_signaldetect),
	.signaldetected(rx_signaldetect_wire[3]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs3.align_pattern = "0101111100",
		receive_pcs3.align_pattern_length = 10,
		receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs3.allow_align_polarity_inversion = "false",
		receive_pcs3.allow_pipe_polarity_inversion = "true",
		receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs3.auto_spd_phystatus_notify_count = 14,
		receive_pcs3.auto_spd_self_switch_enable = "true",
		receive_pcs3.bit_slip_enable = "false",
		receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs3.byte_order_mode = "none",
		receive_pcs3.byte_order_pad_pattern = "0",
		receive_pcs3.byte_order_pattern = "0",
		receive_pcs3.byte_order_pld_ctrl_enable = "false",
		receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs3.cdrctrl_cid_mode_enable = "true",
		receive_pcs3.cdrctrl_enable = "true",
		receive_pcs3.cdrctrl_rxvalid_mask = "true",
		receive_pcs3.channel_bonding = "x8",
		receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
		receive_pcs3.channel_width = 8,
		receive_pcs3.clk1_mux_select = "recovered clock",
		receive_pcs3.clk2_mux_select = "digital reference clock",
		receive_pcs3.core_clock_0ppm = "false",
		receive_pcs3.datapath_low_latency_mode = "false",
		receive_pcs3.datapath_protocol = "pipe",
		receive_pcs3.dec_8b_10b_compatibility_mode = "true",
		receive_pcs3.dec_8b_10b_mode = "normal",
		receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs3.deskew_pattern = "0",
		receive_pcs3.disable_auto_idle_insertion = "false",
		receive_pcs3.disable_running_disp_in_word_align = "false",
		receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs3.dprio_config_mode = 6'h01,
		receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs3.elec_idle_infer_enable = "false",
		receive_pcs3.elec_idle_num_com_detect = 3,
		receive_pcs3.enable_bit_reversal = "false",
		receive_pcs3.enable_deep_align = "false",
		receive_pcs3.enable_deep_align_byte_swap = "false",
		receive_pcs3.enable_self_test_mode = "false",
		receive_pcs3.enable_true_complement_match_in_word_align = "false",
		receive_pcs3.force_signal_detect_dig = "true",
		receive_pcs3.hip_enable = "true",
		receive_pcs3.infiniband_invalid_code = 0,
		receive_pcs3.insert_pad_on_underflow = "false",
		receive_pcs3.logical_channel_address = (starting_channel_number + 3),
		receive_pcs3.num_align_code_groups_in_ordered_set = 0,
		receive_pcs3.num_align_cons_good_data = 16,
		receive_pcs3.num_align_cons_pat = 4,
		receive_pcs3.num_align_loss_sync_error = 17,
		receive_pcs3.ph_fifo_low_latency_enable = "true",
		receive_pcs3.ph_fifo_reg_mode = "true",
		receive_pcs3.ph_fifo_xn_mapping0 = "none",
		receive_pcs3.ph_fifo_xn_mapping1 = "none",
		receive_pcs3.ph_fifo_xn_mapping2 = "central",
		receive_pcs3.ph_fifo_xn_select = 2,
		receive_pcs3.pipe_auto_speed_nego_enable = "true",
		receive_pcs3.pipe_freq_scale_mode = "Frequency",
		receive_pcs3.pma_done_count = 249950,
		receive_pcs3.protocol_hint = "pcie2",
		receive_pcs3.rate_match_almost_empty_threshold = 11,
		receive_pcs3.rate_match_almost_full_threshold = 13,
		receive_pcs3.rate_match_back_to_back = "false",
		receive_pcs3.rate_match_delete_threshold = 13,
		receive_pcs3.rate_match_empty_threshold = 5,
		receive_pcs3.rate_match_fifo_mode = "true",
		receive_pcs3.rate_match_full_threshold = 20,
		receive_pcs3.rate_match_insert_threshold = 11,
		receive_pcs3.rate_match_ordered_set_based = "false",
		receive_pcs3.rate_match_pattern1 = "11010000111010000011",
		receive_pcs3.rate_match_pattern2 = "00101111000101111100",
		receive_pcs3.rate_match_pattern_size = 20,
		receive_pcs3.rate_match_pipe_enable = "true",
		receive_pcs3.rate_match_reset_enable = "false",
		receive_pcs3.rate_match_skip_set_based = "true",
		receive_pcs3.rate_match_start_threshold = 7,
		receive_pcs3.rd_clk_mux_select = "int clock",
		receive_pcs3.recovered_clk_mux_select = "recovered clock",
		receive_pcs3.run_length = 40,
		receive_pcs3.run_length_enable = "true",
		receive_pcs3.rx_detect_bypass = "false",
		receive_pcs3.rx_phfifo_wait_cnt = 32,
		receive_pcs3.rxstatus_error_report_mode = 1,
		receive_pcs3.self_test_mode = "incremental",
		receive_pcs3.use_alignment_state_machine = "true",
		receive_pcs3.use_deserializer_double_data_mode = "false",
		receive_pcs3.use_deskew_fifo = "false",
		receive_pcs3.use_double_data_mode = "false",
		receive_pcs3.use_parallel_loopback = "false",
		receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs4
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs4_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs4_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[14:12]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[14:12]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs4_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs4_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[99:80]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[4]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pcsdprioin_wire[1999:1600]),
	.dprioout(wire_receive_pcs4_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[4]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[4]),
	.hipdataout(wire_receive_pcs4_hipdataout),
	.hipdatavalid(wire_receive_pcs4_hipdatavalid),
	.hipelecidle(wire_receive_pcs4_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs4_hipphydonestatus),
	.hippowerdown(powerdn[9:8]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs4_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[9:8]),
	.iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs4_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[9:8]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[4]),
	.phfifordenableout(wire_receive_pcs4_phfifordenableout),
	.phfiforeset(rx_phfiforeset[4]),
	.phfiforesetout(wire_receive_pcs4_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[4]),
	.phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[14:12]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[4]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[9:8]),
	.pipepowerstate(tx_pipepowerstateout[19:16]),
	.pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[4]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(wire_receive_pcs4_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[1]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[4]),
	.refclk(refclk_pma[1]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[4]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[4]),
	.rxfound(rx_pcs_rxfound_wire[9:8]),
	.signaldetect(wire_receive_pcs4_signaldetect),
	.signaldetected(rx_signaldetect_wire[4]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs4.align_pattern = "0101111100",
		receive_pcs4.align_pattern_length = 10,
		receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs4.allow_align_polarity_inversion = "false",
		receive_pcs4.allow_pipe_polarity_inversion = "true",
		receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs4.auto_spd_phystatus_notify_count = 14,
		receive_pcs4.auto_spd_self_switch_enable = "true",
		receive_pcs4.bit_slip_enable = "false",
		receive_pcs4.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs4.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs4.byte_order_mode = "none",
		receive_pcs4.byte_order_pad_pattern = "0",
		receive_pcs4.byte_order_pattern = "0",
		receive_pcs4.byte_order_pld_ctrl_enable = "false",
		receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs4.cdrctrl_cid_mode_enable = "true",
		receive_pcs4.cdrctrl_enable = "true",
		receive_pcs4.cdrctrl_rxvalid_mask = "true",
		receive_pcs4.channel_bonding = "x8",
		receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
		receive_pcs4.channel_width = 8,
		receive_pcs4.clk1_mux_select = "recovered clock",
		receive_pcs4.clk2_mux_select = "digital reference clock",
		receive_pcs4.core_clock_0ppm = "false",
		receive_pcs4.datapath_low_latency_mode = "false",
		receive_pcs4.datapath_protocol = "pipe",
		receive_pcs4.dec_8b_10b_compatibility_mode = "true",
		receive_pcs4.dec_8b_10b_mode = "normal",
		receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs4.deskew_pattern = "0",
		receive_pcs4.disable_auto_idle_insertion = "false",
		receive_pcs4.disable_running_disp_in_word_align = "false",
		receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs4.dprio_config_mode = 6'h01,
		receive_pcs4.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs4.elec_idle_infer_enable = "false",
		receive_pcs4.elec_idle_num_com_detect = 3,
		receive_pcs4.enable_bit_reversal = "false",
		receive_pcs4.enable_deep_align = "false",
		receive_pcs4.enable_deep_align_byte_swap = "false",
		receive_pcs4.enable_self_test_mode = "false",
		receive_pcs4.enable_true_complement_match_in_word_align = "false",
		receive_pcs4.force_signal_detect_dig = "true",
		receive_pcs4.hip_enable = "true",
		receive_pcs4.infiniband_invalid_code = 0,
		receive_pcs4.insert_pad_on_underflow = "false",
		receive_pcs4.iqp_ph_fifo_xn_select = 1,
		receive_pcs4.logical_channel_address = (starting_channel_number + 4),
		receive_pcs4.num_align_code_groups_in_ordered_set = 0,
		receive_pcs4.num_align_cons_good_data = 16,
		receive_pcs4.num_align_cons_pat = 4,
		receive_pcs4.num_align_loss_sync_error = 17,
		receive_pcs4.ph_fifo_low_latency_enable = "true",
		receive_pcs4.ph_fifo_reg_mode = "true",
		receive_pcs4.ph_fifo_xn_mapping0 = "none",
		receive_pcs4.ph_fifo_xn_mapping1 = "up",
		receive_pcs4.ph_fifo_xn_mapping2 = "none",
		receive_pcs4.ph_fifo_xn_select = 1,
		receive_pcs4.pipe_auto_speed_nego_enable = "true",
		receive_pcs4.pipe_freq_scale_mode = "Frequency",
		receive_pcs4.pma_done_count = 249950,
		receive_pcs4.protocol_hint = "pcie2",
		receive_pcs4.rate_match_almost_empty_threshold = 11,
		receive_pcs4.rate_match_almost_full_threshold = 13,
		receive_pcs4.rate_match_back_to_back = "false",
		receive_pcs4.rate_match_delete_threshold = 13,
		receive_pcs4.rate_match_empty_threshold = 5,
		receive_pcs4.rate_match_fifo_mode = "true",
		receive_pcs4.rate_match_full_threshold = 20,
		receive_pcs4.rate_match_insert_threshold = 11,
		receive_pcs4.rate_match_ordered_set_based = "false",
		receive_pcs4.rate_match_pattern1 = "11010000111010000011",
		receive_pcs4.rate_match_pattern2 = "00101111000101111100",
		receive_pcs4.rate_match_pattern_size = 20,
		receive_pcs4.rate_match_pipe_enable = "true",
		receive_pcs4.rate_match_reset_enable = "false",
		receive_pcs4.rate_match_skip_set_based = "true",
		receive_pcs4.rate_match_start_threshold = 7,
		receive_pcs4.rd_clk_mux_select = "int clock",
		receive_pcs4.recovered_clk_mux_select = "recovered clock",
		receive_pcs4.run_length = 40,
		receive_pcs4.run_length_enable = "true",
		receive_pcs4.rx_detect_bypass = "false",
		receive_pcs4.rx_phfifo_wait_cnt = 32,
		receive_pcs4.rxstatus_error_report_mode = 1,
		receive_pcs4.self_test_mode = "incremental",
		receive_pcs4.use_alignment_state_machine = "true",
		receive_pcs4.use_deserializer_double_data_mode = "false",
		receive_pcs4.use_deskew_fifo = "false",
		receive_pcs4.use_double_data_mode = "false",
		receive_pcs4.use_parallel_loopback = "false",
		receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs4.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs5
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs5_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs5_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[17:15]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[17:15]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs5_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs5_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[119:100]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[5]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pcsdprioin_wire[2399:2000]),
	.dprioout(wire_receive_pcs5_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[5]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[5]),
	.hipdataout(wire_receive_pcs5_hipdataout),
	.hipdatavalid(wire_receive_pcs5_hipdatavalid),
	.hipelecidle(wire_receive_pcs5_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs5_hipphydonestatus),
	.hippowerdown(powerdn[11:10]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs5_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[11:10]),
	.iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs5_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[11:10]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[5]),
	.phfifordenableout(wire_receive_pcs5_phfifordenableout),
	.phfiforeset(rx_phfiforeset[5]),
	.phfiforesetout(wire_receive_pcs5_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[5]),
	.phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[17:15]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[5]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[11:10]),
	.pipepowerstate(tx_pipepowerstateout[23:20]),
	.pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[5]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(wire_receive_pcs5_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[1]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[5]),
	.refclk(refclk_pma[1]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[5]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[5]),
	.rxfound(rx_pcs_rxfound_wire[11:10]),
	.signaldetect(wire_receive_pcs5_signaldetect),
	.signaldetected(rx_signaldetect_wire[5]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs5.align_pattern = "0101111100",
		receive_pcs5.align_pattern_length = 10,
		receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs5.allow_align_polarity_inversion = "false",
		receive_pcs5.allow_pipe_polarity_inversion = "true",
		receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs5.auto_spd_phystatus_notify_count = 14,
		receive_pcs5.auto_spd_self_switch_enable = "true",
		receive_pcs5.bit_slip_enable = "false",
		receive_pcs5.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs5.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs5.byte_order_mode = "none",
		receive_pcs5.byte_order_pad_pattern = "0",
		receive_pcs5.byte_order_pattern = "0",
		receive_pcs5.byte_order_pld_ctrl_enable = "false",
		receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs5.cdrctrl_cid_mode_enable = "true",
		receive_pcs5.cdrctrl_enable = "true",
		receive_pcs5.cdrctrl_rxvalid_mask = "true",
		receive_pcs5.channel_bonding = "x8",
		receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
		receive_pcs5.channel_width = 8,
		receive_pcs5.clk1_mux_select = "recovered clock",
		receive_pcs5.clk2_mux_select = "digital reference clock",
		receive_pcs5.core_clock_0ppm = "false",
		receive_pcs5.datapath_low_latency_mode = "false",
		receive_pcs5.datapath_protocol = "pipe",
		receive_pcs5.dec_8b_10b_compatibility_mode = "true",
		receive_pcs5.dec_8b_10b_mode = "normal",
		receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs5.deskew_pattern = "0",
		receive_pcs5.disable_auto_idle_insertion = "false",
		receive_pcs5.disable_running_disp_in_word_align = "false",
		receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs5.dprio_config_mode = 6'h01,
		receive_pcs5.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs5.elec_idle_infer_enable = "false",
		receive_pcs5.elec_idle_num_com_detect = 3,
		receive_pcs5.enable_bit_reversal = "false",
		receive_pcs5.enable_deep_align = "false",
		receive_pcs5.enable_deep_align_byte_swap = "false",
		receive_pcs5.enable_self_test_mode = "false",
		receive_pcs5.enable_true_complement_match_in_word_align = "false",
		receive_pcs5.force_signal_detect_dig = "true",
		receive_pcs5.hip_enable = "true",
		receive_pcs5.infiniband_invalid_code = 0,
		receive_pcs5.insert_pad_on_underflow = "false",
		receive_pcs5.logical_channel_address = (starting_channel_number + 5),
		receive_pcs5.num_align_code_groups_in_ordered_set = 0,
		receive_pcs5.num_align_cons_good_data = 16,
		receive_pcs5.num_align_cons_pat = 4,
		receive_pcs5.num_align_loss_sync_error = 17,
		receive_pcs5.ph_fifo_low_latency_enable = "true",
		receive_pcs5.ph_fifo_reg_mode = "true",
		receive_pcs5.ph_fifo_xn_mapping0 = "none",
		receive_pcs5.ph_fifo_xn_mapping1 = "up",
		receive_pcs5.ph_fifo_xn_mapping2 = "none",
		receive_pcs5.ph_fifo_xn_select = 1,
		receive_pcs5.pipe_auto_speed_nego_enable = "true",
		receive_pcs5.pipe_freq_scale_mode = "Frequency",
		receive_pcs5.pma_done_count = 249950,
		receive_pcs5.protocol_hint = "pcie2",
		receive_pcs5.rate_match_almost_empty_threshold = 11,
		receive_pcs5.rate_match_almost_full_threshold = 13,
		receive_pcs5.rate_match_back_to_back = "false",
		receive_pcs5.rate_match_delete_threshold = 13,
		receive_pcs5.rate_match_empty_threshold = 5,
		receive_pcs5.rate_match_fifo_mode = "true",
		receive_pcs5.rate_match_full_threshold = 20,
		receive_pcs5.rate_match_insert_threshold = 11,
		receive_pcs5.rate_match_ordered_set_based = "false",
		receive_pcs5.rate_match_pattern1 = "11010000111010000011",
		receive_pcs5.rate_match_pattern2 = "00101111000101111100",
		receive_pcs5.rate_match_pattern_size = 20,
		receive_pcs5.rate_match_pipe_enable = "true",
		receive_pcs5.rate_match_reset_enable = "false",
		receive_pcs5.rate_match_skip_set_based = "true",
		receive_pcs5.rate_match_start_threshold = 7,
		receive_pcs5.rd_clk_mux_select = "int clock",
		receive_pcs5.recovered_clk_mux_select = "recovered clock",
		receive_pcs5.run_length = 40,
		receive_pcs5.run_length_enable = "true",
		receive_pcs5.rx_detect_bypass = "false",
		receive_pcs5.rx_phfifo_wait_cnt = 32,
		receive_pcs5.rxstatus_error_report_mode = 1,
		receive_pcs5.self_test_mode = "incremental",
		receive_pcs5.use_alignment_state_machine = "true",
		receive_pcs5.use_deserializer_double_data_mode = "false",
		receive_pcs5.use_deskew_fifo = "false",
		receive_pcs5.use_double_data_mode = "false",
		receive_pcs5.use_parallel_loopback = "false",
		receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs5.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs6
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs6_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs6_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[20:18]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[20:18]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs6_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs6_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[139:120]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[6]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pcsdprioin_wire[2799:2400]),
	.dprioout(wire_receive_pcs6_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[6]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[6]),
	.hipdataout(wire_receive_pcs6_hipdataout),
	.hipdatavalid(wire_receive_pcs6_hipdatavalid),
	.hipelecidle(wire_receive_pcs6_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs6_hipphydonestatus),
	.hippowerdown(powerdn[13:12]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs6_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[13:12]),
	.iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs6_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[13:12]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[6]),
	.phfifordenableout(wire_receive_pcs6_phfifordenableout),
	.phfiforeset(rx_phfiforeset[6]),
	.phfiforesetout(wire_receive_pcs6_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[6]),
	.phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[20:18]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[6]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[13:12]),
	.pipepowerstate(tx_pipepowerstateout[27:24]),
	.pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[6]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(wire_receive_pcs6_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[1]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[6]),
	.refclk(refclk_pma[1]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[6]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[6]),
	.rxfound(rx_pcs_rxfound_wire[13:12]),
	.signaldetect(wire_receive_pcs6_signaldetect),
	.signaldetected(rx_signaldetect_wire[6]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs6.align_pattern = "0101111100",
		receive_pcs6.align_pattern_length = 10,
		receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs6.allow_align_polarity_inversion = "false",
		receive_pcs6.allow_pipe_polarity_inversion = "true",
		receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs6.auto_spd_phystatus_notify_count = 14,
		receive_pcs6.auto_spd_self_switch_enable = "true",
		receive_pcs6.bit_slip_enable = "false",
		receive_pcs6.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs6.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs6.byte_order_mode = "none",
		receive_pcs6.byte_order_pad_pattern = "0",
		receive_pcs6.byte_order_pattern = "0",
		receive_pcs6.byte_order_pld_ctrl_enable = "false",
		receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs6.cdrctrl_cid_mode_enable = "true",
		receive_pcs6.cdrctrl_enable = "true",
		receive_pcs6.cdrctrl_rxvalid_mask = "true",
		receive_pcs6.channel_bonding = "x8",
		receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
		receive_pcs6.channel_width = 8,
		receive_pcs6.clk1_mux_select = "recovered clock",
		receive_pcs6.clk2_mux_select = "digital reference clock",
		receive_pcs6.core_clock_0ppm = "false",
		receive_pcs6.datapath_low_latency_mode = "false",
		receive_pcs6.datapath_protocol = "pipe",
		receive_pcs6.dec_8b_10b_compatibility_mode = "true",
		receive_pcs6.dec_8b_10b_mode = "normal",
		receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs6.deskew_pattern = "0",
		receive_pcs6.disable_auto_idle_insertion = "false",
		receive_pcs6.disable_running_disp_in_word_align = "false",
		receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs6.dprio_config_mode = 6'h01,
		receive_pcs6.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs6.elec_idle_infer_enable = "false",
		receive_pcs6.elec_idle_num_com_detect = 3,
		receive_pcs6.enable_bit_reversal = "false",
		receive_pcs6.enable_deep_align = "false",
		receive_pcs6.enable_deep_align_byte_swap = "false",
		receive_pcs6.enable_self_test_mode = "false",
		receive_pcs6.enable_true_complement_match_in_word_align = "false",
		receive_pcs6.force_signal_detect_dig = "true",
		receive_pcs6.hip_enable = "true",
		receive_pcs6.infiniband_invalid_code = 0,
		receive_pcs6.insert_pad_on_underflow = "false",
		receive_pcs6.logical_channel_address = (starting_channel_number + 6),
		receive_pcs6.num_align_code_groups_in_ordered_set = 0,
		receive_pcs6.num_align_cons_good_data = 16,
		receive_pcs6.num_align_cons_pat = 4,
		receive_pcs6.num_align_loss_sync_error = 17,
		receive_pcs6.ph_fifo_low_latency_enable = "true",
		receive_pcs6.ph_fifo_reg_mode = "true",
		receive_pcs6.ph_fifo_xn_mapping0 = "none",
		receive_pcs6.ph_fifo_xn_mapping1 = "up",
		receive_pcs6.ph_fifo_xn_mapping2 = "none",
		receive_pcs6.ph_fifo_xn_select = 1,
		receive_pcs6.pipe_auto_speed_nego_enable = "true",
		receive_pcs6.pipe_freq_scale_mode = "Frequency",
		receive_pcs6.pma_done_count = 249950,
		receive_pcs6.protocol_hint = "pcie2",
		receive_pcs6.rate_match_almost_empty_threshold = 11,
		receive_pcs6.rate_match_almost_full_threshold = 13,
		receive_pcs6.rate_match_back_to_back = "false",
		receive_pcs6.rate_match_delete_threshold = 13,
		receive_pcs6.rate_match_empty_threshold = 5,
		receive_pcs6.rate_match_fifo_mode = "true",
		receive_pcs6.rate_match_full_threshold = 20,
		receive_pcs6.rate_match_insert_threshold = 11,
		receive_pcs6.rate_match_ordered_set_based = "false",
		receive_pcs6.rate_match_pattern1 = "11010000111010000011",
		receive_pcs6.rate_match_pattern2 = "00101111000101111100",
		receive_pcs6.rate_match_pattern_size = 20,
		receive_pcs6.rate_match_pipe_enable = "true",
		receive_pcs6.rate_match_reset_enable = "false",
		receive_pcs6.rate_match_skip_set_based = "true",
		receive_pcs6.rate_match_start_threshold = 7,
		receive_pcs6.rd_clk_mux_select = "int clock",
		receive_pcs6.recovered_clk_mux_select = "recovered clock",
		receive_pcs6.run_length = 40,
		receive_pcs6.run_length_enable = "true",
		receive_pcs6.rx_detect_bypass = "false",
		receive_pcs6.rx_phfifo_wait_cnt = 32,
		receive_pcs6.rxstatus_error_report_mode = 1,
		receive_pcs6.self_test_mode = "incremental",
		receive_pcs6.use_alignment_state_machine = "true",
		receive_pcs6.use_deserializer_double_data_mode = "false",
		receive_pcs6.use_deskew_fifo = "false",
		receive_pcs6.use_double_data_mode = "false",
		receive_pcs6.use_parallel_loopback = "false",
		receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs6.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pcs   receive_pcs7
	( 
	.a1a2size(1'b0),
	.a1a2sizeout(),
	.a1detect(),
	.a2detect(),
	.adetectdeskew(),
	.alignstatus(1'b0),
	.alignstatussync(1'b0),
	.alignstatussyncout(),
	.autospdrateswitchout(wire_receive_pcs7_autospdrateswitchout),
	.autospdspdchgout(wire_receive_pcs7_autospdspdchgout),
	.autospdxnconfigsel(int_rx_autospdxnconfigsel[23:21]),
	.autospdxnspdchg(int_rx_autospdxnspdchg[23:21]),
	.bistdone(),
	.bisterr(),
	.bitslipboundaryselectout(),
	.byteorderalignstatus(),
	.cdrctrlearlyeios(wire_receive_pcs7_cdrctrlearlyeios),
	.cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
	.clkout(),
	.coreclkout(wire_receive_pcs7_coreclkout),
	.ctrldetect(),
	.datain(rx_pma_recoverdataout_wire[159:140]),
	.dataout(),
	.dataoutfull(),
	.digitalreset(rx_digitalreset_out[7]),
	.digitaltestout(),
	.disablefifordin(1'b0),
	.disablefifordout(),
	.disablefifowrin(1'b0),
	.disablefifowrout(),
	.disperr(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pcsdprioin_wire[3199:2800]),
	.dprioout(wire_receive_pcs7_dprioout),
	.enabledeskew(1'b0),
	.enabyteord(1'b0),
	.enapatternalign(rx_enapatternalign[7]),
	.errdetect(),
	.fifordin(1'b0),
	.fifordout(),
	.fiforesetrd(1'b0),
	.hip8b10binvpolarity(pipe8b10binvpolarity[7]),
	.hipdataout(wire_receive_pcs7_hipdataout),
	.hipdatavalid(wire_receive_pcs7_hipdatavalid),
	.hipelecidle(wire_receive_pcs7_hipelecidle),
	.hipelecidleinfersel({3{1'b0}}),
	.hipphydonestatus(wire_receive_pcs7_hipphydonestatus),
	.hippowerdown(powerdn[15:14]),
	.hiprateswitch(rateswitch[0]),
	.hipstatus(wire_receive_pcs7_hipstatus),
	.invpol(1'b0),
	.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[15:14]),
	.iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
	.iqpphfifoptrsresetout(wire_receive_pcs7_iqpphfifoptrsresetout),
	.iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
	.iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
	.iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
	.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[15:14]),
	.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
	.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
	.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
	.k1detect(),
	.k2detect(),
	.localrefclk(1'b0),
	.masterclk(1'b0),
	.parallelfdbk({20{1'b0}}),
	.patterndetect(),
	.phfifobyteselout(),
	.phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
	.phfifooverflow(),
	.phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
	.phfifordenable(rx_phfifordenable[7]),
	.phfifordenableout(wire_receive_pcs7_phfifordenableout),
	.phfiforeset(rx_phfiforeset[7]),
	.phfiforesetout(wire_receive_pcs7_phfiforesetout),
	.phfifounderflow(),
	.phfifowrclkout(),
	.phfifowrdisable(rx_phfifowrdisable[7]),
	.phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
	.phfifowrenableout(),
	.phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
	.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[23:21]),
	.phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
	.phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
	.phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
	.pipebufferstat(),
	.pipedatavalid(),
	.pipeelecidle(),
	.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[7]),
	.pipephydonestatus(),
	.pipepowerdown(tx_pipepowerdownout[15:14]),
	.pipepowerstate(tx_pipepowerstateout[31:28]),
	.pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
	.pipestatus(),
	.prbscidenable(rx_prbscidenable[7]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(wire_receive_pcs7_rateswitchout),
	.rateswitchxndone(int_hiprateswtichdone[1]),
	.rdalign(),
	.recoveredclk(rx_pma_clockout[7]),
	.refclk(refclk_pma[1]),
	.revbitorderwa(1'b0),
	.revbyteorderwa(1'b0),
	.revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
	.rlv(),
	.rmfifoalmostempty(),
	.rmfifoalmostfull(),
	.rmfifodatadeleted(),
	.rmfifodatainserted(),
	.rmfifoempty(),
	.rmfifofull(),
	.rmfifordena(1'b0),
	.rmfiforeset(rx_rmfiforeset[7]),
	.rmfifowrena(1'b0),
	.runningdisp(),
	.rxdetectvalid(tx_rxdetectvalidout[7]),
	.rxfound(rx_pcs_rxfound_wire[15:14]),
	.signaldetect(wire_receive_pcs7_signaldetect),
	.signaldetected(rx_signaldetect_wire[7]),
	.syncstatus(),
	.syncstatusdeskew(),
	.xauidelcondmetout(),
	.xauififoovrout(),
	.xauiinsertincompleteout(),
	.xauilatencycompout(),
	.xgmctrldet(),
	.xgmctrlin(1'b0),
	.xgmdatain({8{1'b0}}),
	.xgmdataout(),
	.xgmdatavalid(),
	.xgmrunningdisp()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslip(1'b0),
	.cdrctrllocktorefcl(1'b0),
	.coreclk(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.grayelecidleinferselfromtx({3{1'b0}}),
	.phfifox4bytesel(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrclk(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifox8bytesel(1'b0),
	.phfifox8rdenable(1'b0),
	.phfifox8wrclk(1'b0),
	.phfifox8wrenable(1'b0),
	.pipe8b10binvpolarity(1'b0),
	.pmatestbusin({8{1'b0}}),
	.powerdn({2{1'b0}}),
	.ppmdetectdividedclk(1'b0),
	.ppmdetectrefclk(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rxelecidlerateswitch(1'b0),
	.wareset(1'b0),
	.xauidelcondmet(1'b0),
	.xauififoovr(1'b0),
	.xauiinsertincomplete(1'b0),
	.xauilatencycomp(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pcs7.align_pattern = "0101111100",
		receive_pcs7.align_pattern_length = 10,
		receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
		receive_pcs7.allow_align_polarity_inversion = "false",
		receive_pcs7.allow_pipe_polarity_inversion = "true",
		receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
		receive_pcs7.auto_spd_phystatus_notify_count = 14,
		receive_pcs7.auto_spd_self_switch_enable = "true",
		receive_pcs7.bit_slip_enable = "false",
		receive_pcs7.byte_order_double_data_mode_mask_enable = "false",
		receive_pcs7.byte_order_invalid_code_or_run_disp_error = "true",
		receive_pcs7.byte_order_mode = "none",
		receive_pcs7.byte_order_pad_pattern = "0",
		receive_pcs7.byte_order_pattern = "0",
		receive_pcs7.byte_order_pld_ctrl_enable = "false",
		receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
		receive_pcs7.cdrctrl_cid_mode_enable = "true",
		receive_pcs7.cdrctrl_enable = "true",
		receive_pcs7.cdrctrl_rxvalid_mask = "true",
		receive_pcs7.channel_bonding = "x8",
		receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
		receive_pcs7.channel_width = 8,
		receive_pcs7.clk1_mux_select = "recovered clock",
		receive_pcs7.clk2_mux_select = "digital reference clock",
		receive_pcs7.core_clock_0ppm = "false",
		receive_pcs7.datapath_low_latency_mode = "false",
		receive_pcs7.datapath_protocol = "pipe",
		receive_pcs7.dec_8b_10b_compatibility_mode = "true",
		receive_pcs7.dec_8b_10b_mode = "normal",
		receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
		receive_pcs7.deskew_pattern = "0",
		receive_pcs7.disable_auto_idle_insertion = "false",
		receive_pcs7.disable_running_disp_in_word_align = "false",
		receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
		receive_pcs7.dprio_config_mode = 6'h01,
		receive_pcs7.elec_idle_gen1_sigdet_enable = "true",
		receive_pcs7.elec_idle_infer_enable = "false",
		receive_pcs7.elec_idle_num_com_detect = 3,
		receive_pcs7.enable_bit_reversal = "false",
		receive_pcs7.enable_deep_align = "false",
		receive_pcs7.enable_deep_align_byte_swap = "false",
		receive_pcs7.enable_self_test_mode = "false",
		receive_pcs7.enable_true_complement_match_in_word_align = "false",
		receive_pcs7.force_signal_detect_dig = "true",
		receive_pcs7.hip_enable = "true",
		receive_pcs7.infiniband_invalid_code = 0,
		receive_pcs7.insert_pad_on_underflow = "false",
		receive_pcs7.logical_channel_address = (starting_channel_number + 7),
		receive_pcs7.num_align_code_groups_in_ordered_set = 0,
		receive_pcs7.num_align_cons_good_data = 16,
		receive_pcs7.num_align_cons_pat = 4,
		receive_pcs7.num_align_loss_sync_error = 17,
		receive_pcs7.ph_fifo_low_latency_enable = "true",
		receive_pcs7.ph_fifo_reg_mode = "true",
		receive_pcs7.ph_fifo_xn_mapping0 = "none",
		receive_pcs7.ph_fifo_xn_mapping1 = "up",
		receive_pcs7.ph_fifo_xn_mapping2 = "none",
		receive_pcs7.ph_fifo_xn_select = 1,
		receive_pcs7.pipe_auto_speed_nego_enable = "true",
		receive_pcs7.pipe_freq_scale_mode = "Frequency",
		receive_pcs7.pma_done_count = 249950,
		receive_pcs7.protocol_hint = "pcie2",
		receive_pcs7.rate_match_almost_empty_threshold = 11,
		receive_pcs7.rate_match_almost_full_threshold = 13,
		receive_pcs7.rate_match_back_to_back = "false",
		receive_pcs7.rate_match_delete_threshold = 13,
		receive_pcs7.rate_match_empty_threshold = 5,
		receive_pcs7.rate_match_fifo_mode = "true",
		receive_pcs7.rate_match_full_threshold = 20,
		receive_pcs7.rate_match_insert_threshold = 11,
		receive_pcs7.rate_match_ordered_set_based = "false",
		receive_pcs7.rate_match_pattern1 = "11010000111010000011",
		receive_pcs7.rate_match_pattern2 = "00101111000101111100",
		receive_pcs7.rate_match_pattern_size = 20,
		receive_pcs7.rate_match_pipe_enable = "true",
		receive_pcs7.rate_match_reset_enable = "false",
		receive_pcs7.rate_match_skip_set_based = "true",
		receive_pcs7.rate_match_start_threshold = 7,
		receive_pcs7.rd_clk_mux_select = "int clock",
		receive_pcs7.recovered_clk_mux_select = "recovered clock",
		receive_pcs7.run_length = 40,
		receive_pcs7.run_length_enable = "true",
		receive_pcs7.rx_detect_bypass = "false",
		receive_pcs7.rx_phfifo_wait_cnt = 32,
		receive_pcs7.rxstatus_error_report_mode = 1,
		receive_pcs7.self_test_mode = "incremental",
		receive_pcs7.use_alignment_state_machine = "true",
		receive_pcs7.use_deserializer_double_data_mode = "false",
		receive_pcs7.use_deskew_fifo = "false",
		receive_pcs7.use_double_data_mode = "false",
		receive_pcs7.use_parallel_loopback = "false",
		receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
		receive_pcs7.lpm_type = "stratixiv_hssi_rx_pcs";
	stratixiv_hssi_rx_pma   receive_pma0
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma0_analogtestbus),
	.clockout(wire_receive_pma0_clockout),
	.datain(rx_datain[0]),
	.dataout(wire_receive_pma0_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[3:0]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pmadprioin_wire[299:0]),
	.dprioout(wire_receive_pma0_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[0]),
	.locktoref(rx_locktorefclk_wire[0]),
	.locktorefout(wire_receive_pma0_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[0]),
	.powerdn(cent_unit_rxibpowerdn[0]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
	.recoverdatain(pll_ch_dataout_wire[1:0]),
	.recoverdataout(wire_receive_pma0_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[0]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma0_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma0.adaptive_equalization_mode = "none",
		receive_pma0.allow_serial_loopback = "false",
		receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
		receive_pma0.channel_type = "auto",
		receive_pma0.common_mode = "0.82V",
		receive_pma0.deserialization_factor = 10,
		receive_pma0.dprio_config_mode = 6'h01,
		receive_pma0.enable_ltd = "false",
		receive_pma0.enable_ltr = "true",
		receive_pma0.eq_dc_gain = 3,
		receive_pma0.eqa_ctrl = 0,
		receive_pma0.eqb_ctrl = 0,
		receive_pma0.eqc_ctrl = 0,
		receive_pma0.eqd_ctrl = 0,
		receive_pma0.eqv_ctrl = 0,
		receive_pma0.eyemon_bandwidth = 0,
		receive_pma0.force_signal_detect = "true",
		receive_pma0.logical_channel_address = (starting_channel_number + 0),
		receive_pma0.low_speed_test_select = 0,
		receive_pma0.offset_cancellation = 1,
		receive_pma0.ppmselect = 32,
		receive_pma0.protocol_hint = "pcie2",
		receive_pma0.send_direct_reverse_serial_loopback = "None",
		receive_pma0.signal_detect_hysteresis = 4,
		receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma0.signal_detect_loss_threshold = 3,
		receive_pma0.termination = "OCT 100 Ohms",
		receive_pma0.use_deser_double_data_width = "false",
		receive_pma0.use_external_termination = "false",
		receive_pma0.use_pma_direct = "false",
		receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma1
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma1_analogtestbus),
	.clockout(wire_receive_pma1_clockout),
	.datain(rx_datain[1]),
	.dataout(wire_receive_pma1_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[7:4]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pmadprioin_wire[599:300]),
	.dprioout(wire_receive_pma1_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[1]),
	.locktoref(rx_locktorefclk_wire[1]),
	.locktorefout(wire_receive_pma1_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[1]),
	.powerdn(cent_unit_rxibpowerdn[1]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
	.recoverdatain(pll_ch_dataout_wire[3:2]),
	.recoverdataout(wire_receive_pma1_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[1]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma1_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma1.adaptive_equalization_mode = "none",
		receive_pma1.allow_serial_loopback = "false",
		receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
		receive_pma1.channel_type = "auto",
		receive_pma1.common_mode = "0.82V",
		receive_pma1.deserialization_factor = 10,
		receive_pma1.dprio_config_mode = 6'h01,
		receive_pma1.enable_ltd = "false",
		receive_pma1.enable_ltr = "true",
		receive_pma1.eq_dc_gain = 3,
		receive_pma1.eqa_ctrl = 0,
		receive_pma1.eqb_ctrl = 0,
		receive_pma1.eqc_ctrl = 0,
		receive_pma1.eqd_ctrl = 0,
		receive_pma1.eqv_ctrl = 0,
		receive_pma1.eyemon_bandwidth = 0,
		receive_pma1.force_signal_detect = "true",
		receive_pma1.logical_channel_address = (starting_channel_number + 1),
		receive_pma1.low_speed_test_select = 0,
		receive_pma1.offset_cancellation = 1,
		receive_pma1.ppmselect = 32,
		receive_pma1.protocol_hint = "pcie2",
		receive_pma1.send_direct_reverse_serial_loopback = "None",
		receive_pma1.signal_detect_hysteresis = 4,
		receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma1.signal_detect_loss_threshold = 3,
		receive_pma1.termination = "OCT 100 Ohms",
		receive_pma1.use_deser_double_data_width = "false",
		receive_pma1.use_external_termination = "false",
		receive_pma1.use_pma_direct = "false",
		receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma2
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma2_analogtestbus),
	.clockout(wire_receive_pma2_clockout),
	.datain(rx_datain[2]),
	.dataout(wire_receive_pma2_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[11:8]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pmadprioin_wire[899:600]),
	.dprioout(wire_receive_pma2_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[2]),
	.locktoref(rx_locktorefclk_wire[2]),
	.locktorefout(wire_receive_pma2_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[2]),
	.powerdn(cent_unit_rxibpowerdn[2]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
	.recoverdatain(pll_ch_dataout_wire[5:4]),
	.recoverdataout(wire_receive_pma2_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[2]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma2_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma2.adaptive_equalization_mode = "none",
		receive_pma2.allow_serial_loopback = "false",
		receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
		receive_pma2.channel_type = "auto",
		receive_pma2.common_mode = "0.82V",
		receive_pma2.deserialization_factor = 10,
		receive_pma2.dprio_config_mode = 6'h01,
		receive_pma2.enable_ltd = "false",
		receive_pma2.enable_ltr = "true",
		receive_pma2.eq_dc_gain = 3,
		receive_pma2.eqa_ctrl = 0,
		receive_pma2.eqb_ctrl = 0,
		receive_pma2.eqc_ctrl = 0,
		receive_pma2.eqd_ctrl = 0,
		receive_pma2.eqv_ctrl = 0,
		receive_pma2.eyemon_bandwidth = 0,
		receive_pma2.force_signal_detect = "true",
		receive_pma2.logical_channel_address = (starting_channel_number + 2),
		receive_pma2.low_speed_test_select = 0,
		receive_pma2.offset_cancellation = 1,
		receive_pma2.ppmselect = 32,
		receive_pma2.protocol_hint = "pcie2",
		receive_pma2.send_direct_reverse_serial_loopback = "None",
		receive_pma2.signal_detect_hysteresis = 4,
		receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma2.signal_detect_loss_threshold = 3,
		receive_pma2.termination = "OCT 100 Ohms",
		receive_pma2.use_deser_double_data_width = "false",
		receive_pma2.use_external_termination = "false",
		receive_pma2.use_pma_direct = "false",
		receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma3
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma3_analogtestbus),
	.clockout(wire_receive_pma3_clockout),
	.datain(rx_datain[3]),
	.dataout(wire_receive_pma3_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[15:12]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(rx_pmadprioin_wire[1199:900]),
	.dprioout(wire_receive_pma3_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[3]),
	.locktoref(rx_locktorefclk_wire[3]),
	.locktorefout(wire_receive_pma3_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[3]),
	.powerdn(cent_unit_rxibpowerdn[3]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
	.recoverdatain(pll_ch_dataout_wire[7:6]),
	.recoverdataout(wire_receive_pma3_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[3]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma3_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma3.adaptive_equalization_mode = "none",
		receive_pma3.allow_serial_loopback = "false",
		receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
		receive_pma3.channel_type = "auto",
		receive_pma3.common_mode = "0.82V",
		receive_pma3.deserialization_factor = 10,
		receive_pma3.dprio_config_mode = 6'h01,
		receive_pma3.enable_ltd = "false",
		receive_pma3.enable_ltr = "true",
		receive_pma3.eq_dc_gain = 3,
		receive_pma3.eqa_ctrl = 0,
		receive_pma3.eqb_ctrl = 0,
		receive_pma3.eqc_ctrl = 0,
		receive_pma3.eqd_ctrl = 0,
		receive_pma3.eqv_ctrl = 0,
		receive_pma3.eyemon_bandwidth = 0,
		receive_pma3.force_signal_detect = "true",
		receive_pma3.logical_channel_address = (starting_channel_number + 3),
		receive_pma3.low_speed_test_select = 0,
		receive_pma3.offset_cancellation = 1,
		receive_pma3.ppmselect = 32,
		receive_pma3.protocol_hint = "pcie2",
		receive_pma3.send_direct_reverse_serial_loopback = "None",
		receive_pma3.signal_detect_hysteresis = 4,
		receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma3.signal_detect_loss_threshold = 3,
		receive_pma3.termination = "OCT 100 Ohms",
		receive_pma3.use_deser_double_data_width = "false",
		receive_pma3.use_external_termination = "false",
		receive_pma3.use_pma_direct = "false",
		receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma4
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma4_analogtestbus),
	.clockout(wire_receive_pma4_clockout),
	.datain(rx_datain[4]),
	.dataout(wire_receive_pma4_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[19:16]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pmadprioin_wire[2099:1800]),
	.dprioout(wire_receive_pma4_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[4]),
	.locktoref(rx_locktorefclk_wire[4]),
	.locktorefout(wire_receive_pma4_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[4]),
	.powerdn(cent_unit_rxibpowerdn[6]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
	.recoverdatain(pll_ch_dataout_wire[9:8]),
	.recoverdataout(wire_receive_pma4_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[6]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma4_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma4.adaptive_equalization_mode = "none",
		receive_pma4.allow_serial_loopback = "false",
		receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
		receive_pma4.channel_type = "auto",
		receive_pma4.common_mode = "0.82V",
		receive_pma4.deserialization_factor = 10,
		receive_pma4.dprio_config_mode = 6'h01,
		receive_pma4.enable_ltd = "false",
		receive_pma4.enable_ltr = "true",
		receive_pma4.eq_dc_gain = 3,
		receive_pma4.eqa_ctrl = 0,
		receive_pma4.eqb_ctrl = 0,
		receive_pma4.eqc_ctrl = 0,
		receive_pma4.eqd_ctrl = 0,
		receive_pma4.eqv_ctrl = 0,
		receive_pma4.eyemon_bandwidth = 0,
		receive_pma4.force_signal_detect = "true",
		receive_pma4.logical_channel_address = (starting_channel_number + 4),
		receive_pma4.low_speed_test_select = 0,
		receive_pma4.offset_cancellation = 1,
		receive_pma4.ppmselect = 32,
		receive_pma4.protocol_hint = "pcie2",
		receive_pma4.send_direct_reverse_serial_loopback = "None",
		receive_pma4.signal_detect_hysteresis = 4,
		receive_pma4.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma4.signal_detect_loss_threshold = 3,
		receive_pma4.termination = "OCT 100 Ohms",
		receive_pma4.use_deser_double_data_width = "false",
		receive_pma4.use_external_termination = "false",
		receive_pma4.use_pma_direct = "false",
		receive_pma4.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma5
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma5_analogtestbus),
	.clockout(wire_receive_pma5_clockout),
	.datain(rx_datain[5]),
	.dataout(wire_receive_pma5_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[23:20]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pmadprioin_wire[2399:2100]),
	.dprioout(wire_receive_pma5_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[5]),
	.locktoref(rx_locktorefclk_wire[5]),
	.locktorefout(wire_receive_pma5_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[5]),
	.powerdn(cent_unit_rxibpowerdn[7]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
	.recoverdatain(pll_ch_dataout_wire[11:10]),
	.recoverdataout(wire_receive_pma5_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[7]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma5_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma5.adaptive_equalization_mode = "none",
		receive_pma5.allow_serial_loopback = "false",
		receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
		receive_pma5.channel_type = "auto",
		receive_pma5.common_mode = "0.82V",
		receive_pma5.deserialization_factor = 10,
		receive_pma5.dprio_config_mode = 6'h01,
		receive_pma5.enable_ltd = "false",
		receive_pma5.enable_ltr = "true",
		receive_pma5.eq_dc_gain = 3,
		receive_pma5.eqa_ctrl = 0,
		receive_pma5.eqb_ctrl = 0,
		receive_pma5.eqc_ctrl = 0,
		receive_pma5.eqd_ctrl = 0,
		receive_pma5.eqv_ctrl = 0,
		receive_pma5.eyemon_bandwidth = 0,
		receive_pma5.force_signal_detect = "true",
		receive_pma5.logical_channel_address = (starting_channel_number + 5),
		receive_pma5.low_speed_test_select = 0,
		receive_pma5.offset_cancellation = 1,
		receive_pma5.ppmselect = 32,
		receive_pma5.protocol_hint = "pcie2",
		receive_pma5.send_direct_reverse_serial_loopback = "None",
		receive_pma5.signal_detect_hysteresis = 4,
		receive_pma5.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma5.signal_detect_loss_threshold = 3,
		receive_pma5.termination = "OCT 100 Ohms",
		receive_pma5.use_deser_double_data_width = "false",
		receive_pma5.use_external_termination = "false",
		receive_pma5.use_pma_direct = "false",
		receive_pma5.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma6
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma6_analogtestbus),
	.clockout(wire_receive_pma6_clockout),
	.datain(rx_datain[6]),
	.dataout(wire_receive_pma6_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[27:24]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pmadprioin_wire[2699:2400]),
	.dprioout(wire_receive_pma6_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[6]),
	.locktoref(rx_locktorefclk_wire[6]),
	.locktorefout(wire_receive_pma6_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[6]),
	.powerdn(cent_unit_rxibpowerdn[8]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
	.recoverdatain(pll_ch_dataout_wire[13:12]),
	.recoverdataout(wire_receive_pma6_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[8]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma6_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma6.adaptive_equalization_mode = "none",
		receive_pma6.allow_serial_loopback = "false",
		receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
		receive_pma6.channel_type = "auto",
		receive_pma6.common_mode = "0.82V",
		receive_pma6.deserialization_factor = 10,
		receive_pma6.dprio_config_mode = 6'h01,
		receive_pma6.enable_ltd = "false",
		receive_pma6.enable_ltr = "true",
		receive_pma6.eq_dc_gain = 3,
		receive_pma6.eqa_ctrl = 0,
		receive_pma6.eqb_ctrl = 0,
		receive_pma6.eqc_ctrl = 0,
		receive_pma6.eqd_ctrl = 0,
		receive_pma6.eqv_ctrl = 0,
		receive_pma6.eyemon_bandwidth = 0,
		receive_pma6.force_signal_detect = "true",
		receive_pma6.logical_channel_address = (starting_channel_number + 6),
		receive_pma6.low_speed_test_select = 0,
		receive_pma6.offset_cancellation = 1,
		receive_pma6.ppmselect = 32,
		receive_pma6.protocol_hint = "pcie2",
		receive_pma6.send_direct_reverse_serial_loopback = "None",
		receive_pma6.signal_detect_hysteresis = 4,
		receive_pma6.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma6.signal_detect_loss_threshold = 3,
		receive_pma6.termination = "OCT 100 Ohms",
		receive_pma6.use_deser_double_data_width = "false",
		receive_pma6.use_external_termination = "false",
		receive_pma6.use_pma_direct = "false",
		receive_pma6.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_rx_pma   receive_pma7
	( 
	.adaptdone(),
	.analogtestbus(wire_receive_pma7_analogtestbus),
	.clockout(wire_receive_pma7_clockout),
	.datain(rx_datain[7]),
	.dataout(wire_receive_pma7_dataout),
	.dataoutfull(),
	.deserclock(rx_deserclock_in[31:28]),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(rx_pmadprioin_wire[2999:2700]),
	.dprioout(wire_receive_pma7_dprioout),
	.freqlock(1'b0),
	.ignorephslck(1'b0),
	.locktodata(rx_locktodata_wire[7]),
	.locktoref(rx_locktorefclk_wire[7]),
	.locktorefout(wire_receive_pma7_locktorefout),
	.offsetcancellationen(1'b0),
	.plllocked(rx_plllocked_wire[7]),
	.powerdn(cent_unit_rxibpowerdn[9]),
	.ppmdetectclkrel(),
	.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
	.recoverdatain(pll_ch_dataout_wire[15:14]),
	.recoverdataout(wire_receive_pma7_recoverdataout),
	.reverselpbkout(),
	.revserialfdbkout(),
	.rxpmareset(rx_analogreset_out[9]),
	.seriallpbken(1'b0),
	.seriallpbkin(1'b0),
	.signaldetect(wire_receive_pma7_signaldetect),
	.testbussel(4'b0110)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.adaptcapture(1'b0),
	.adcepowerdn(1'b0),
	.adcereset(1'b0),
	.adcestandby(1'b0),
	.extra10gin({38{1'b0}}),
	.ppmdetectdividedclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		receive_pma7.adaptive_equalization_mode = "none",
		receive_pma7.allow_serial_loopback = "false",
		receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
		receive_pma7.channel_type = "auto",
		receive_pma7.common_mode = "0.82V",
		receive_pma7.deserialization_factor = 10,
		receive_pma7.dprio_config_mode = 6'h01,
		receive_pma7.enable_ltd = "false",
		receive_pma7.enable_ltr = "true",
		receive_pma7.eq_dc_gain = 3,
		receive_pma7.eqa_ctrl = 0,
		receive_pma7.eqb_ctrl = 0,
		receive_pma7.eqc_ctrl = 0,
		receive_pma7.eqd_ctrl = 0,
		receive_pma7.eqv_ctrl = 0,
		receive_pma7.eyemon_bandwidth = 0,
		receive_pma7.force_signal_detect = "true",
		receive_pma7.logical_channel_address = (starting_channel_number + 7),
		receive_pma7.low_speed_test_select = 0,
		receive_pma7.offset_cancellation = 1,
		receive_pma7.ppmselect = 32,
		receive_pma7.protocol_hint = "pcie2",
		receive_pma7.send_direct_reverse_serial_loopback = "None",
		receive_pma7.signal_detect_hysteresis = 4,
		receive_pma7.signal_detect_hysteresis_valid_threshold = 14,
		receive_pma7.signal_detect_loss_threshold = 3,
		receive_pma7.termination = "OCT 100 Ohms",
		receive_pma7.use_deser_double_data_width = "false",
		receive_pma7.use_external_termination = "false",
		receive_pma7.use_pma_direct = "false",
		receive_pma7.lpm_type = "stratixiv_hssi_rx_pma";
	stratixiv_hssi_tx_pcs   transmit_pcs0
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs0_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs0_dataout),
	.digitalreset(tx_digitalreset_out[0]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_dprioin_wire[149:0]),
	.dprioout(wire_transmit_pcs0_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[0]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[0], tx_ctrlenable[0], tx_datain_wire[7:0]}),
	.hipdetectrxloop(tx_detectrxloop[0]),
	.hipelecidleinfersel(rx_elecidleinfersel[2:0]),
	.hipforceelecidle(tx_forceelecidle[0]),
	.hippowerdn(powerdn[1:0]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[0]),
	.hiptxmargin(tx_pipemargin[2:0]),
	.invpol(tx_invpolarity[0]),
	.iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
	.localrefclk(tx_localrefclk[0]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[0]),
	.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
	.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[0]),
	.pipetxswing(tx_pipeswing[0]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
	.txdetectrx(wire_transmit_pcs0_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[0]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs0.allow_polarity_inversion = "false",
		transmit_pcs0.auto_spd_self_switch_enable = "true",
		transmit_pcs0.bitslip_enable = "false",
		transmit_pcs0.channel_bonding = "x8",
		transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
		transmit_pcs0.channel_width = 8,
		transmit_pcs0.core_clock_0ppm = "false",
		transmit_pcs0.datapath_low_latency_mode = "false",
		transmit_pcs0.datapath_protocol = "pipe",
		transmit_pcs0.disable_ph_low_latency_mode = "false",
		transmit_pcs0.disparity_mode = "new",
		transmit_pcs0.dprio_config_mode = 6'h01,
		transmit_pcs0.elec_idle_delay = 6,
		transmit_pcs0.enable_bit_reversal = "false",
		transmit_pcs0.enable_idle_selection = "false",
		transmit_pcs0.enable_reverse_parallel_loopback = "true",
		transmit_pcs0.enable_self_test_mode = "false",
		transmit_pcs0.enable_symbol_swap = "false",
		transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs0.enc_8b_10b_mode = "normal",
		transmit_pcs0.force_echar = "false",
		transmit_pcs0.force_kchar = "false",
		transmit_pcs0.hip_enable = "true",
		transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
		transmit_pcs0.ph_fifo_reg_mode = "true",
		transmit_pcs0.ph_fifo_xn_mapping0 = "none",
		transmit_pcs0.ph_fifo_xn_mapping1 = "none",
		transmit_pcs0.ph_fifo_xn_mapping2 = "central",
		transmit_pcs0.ph_fifo_xn_select = 2,
		transmit_pcs0.pipe_auto_speed_nego_enable = "true",
		transmit_pcs0.pipe_freq_scale_mode = "Frequency",
		transmit_pcs0.pipe_voltage_swing_control = "false",
		transmit_pcs0.prbs_cid_pattern = "false",
		transmit_pcs0.protocol_hint = "pcie2",
		transmit_pcs0.refclk_select = "cmu_clock_divider",
		transmit_pcs0.self_test_mode = "incremental",
		transmit_pcs0.use_double_data_mode = "false",
		transmit_pcs0.use_serializer_double_data_mode = "false",
		transmit_pcs0.wr_clk_mux_select = "int_clk",
		transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs1
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs1_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs1_dataout),
	.digitalreset(tx_digitalreset_out[1]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_dprioin_wire[299:150]),
	.dprioout(wire_transmit_pcs1_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[1]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[1], tx_ctrlenable[1], tx_datain_wire[15:8]}),
	.hipdetectrxloop(tx_detectrxloop[1]),
	.hipelecidleinfersel(rx_elecidleinfersel[5:3]),
	.hipforceelecidle(tx_forceelecidle[1]),
	.hippowerdn(powerdn[3:2]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[1]),
	.hiptxmargin(tx_pipemargin[5:3]),
	.invpol(tx_invpolarity[1]),
	.iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
	.localrefclk(tx_localrefclk[1]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[1]),
	.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
	.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[1]),
	.pipetxswing(tx_pipeswing[1]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
	.txdetectrx(wire_transmit_pcs1_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[1]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs1.allow_polarity_inversion = "false",
		transmit_pcs1.auto_spd_self_switch_enable = "true",
		transmit_pcs1.bitslip_enable = "false",
		transmit_pcs1.channel_bonding = "x8",
		transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
		transmit_pcs1.channel_width = 8,
		transmit_pcs1.core_clock_0ppm = "false",
		transmit_pcs1.datapath_low_latency_mode = "false",
		transmit_pcs1.datapath_protocol = "pipe",
		transmit_pcs1.disable_ph_low_latency_mode = "false",
		transmit_pcs1.disparity_mode = "new",
		transmit_pcs1.dprio_config_mode = 6'h01,
		transmit_pcs1.elec_idle_delay = 6,
		transmit_pcs1.enable_bit_reversal = "false",
		transmit_pcs1.enable_idle_selection = "false",
		transmit_pcs1.enable_reverse_parallel_loopback = "true",
		transmit_pcs1.enable_self_test_mode = "false",
		transmit_pcs1.enable_symbol_swap = "false",
		transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs1.enc_8b_10b_mode = "normal",
		transmit_pcs1.force_echar = "false",
		transmit_pcs1.force_kchar = "false",
		transmit_pcs1.hip_enable = "true",
		transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
		transmit_pcs1.ph_fifo_reg_mode = "true",
		transmit_pcs1.ph_fifo_xn_mapping0 = "none",
		transmit_pcs1.ph_fifo_xn_mapping1 = "none",
		transmit_pcs1.ph_fifo_xn_mapping2 = "central",
		transmit_pcs1.ph_fifo_xn_select = 2,
		transmit_pcs1.pipe_auto_speed_nego_enable = "true",
		transmit_pcs1.pipe_freq_scale_mode = "Frequency",
		transmit_pcs1.pipe_voltage_swing_control = "false",
		transmit_pcs1.prbs_cid_pattern = "false",
		transmit_pcs1.protocol_hint = "pcie2",
		transmit_pcs1.refclk_select = "cmu_clock_divider",
		transmit_pcs1.self_test_mode = "incremental",
		transmit_pcs1.use_double_data_mode = "false",
		transmit_pcs1.use_serializer_double_data_mode = "false",
		transmit_pcs1.wr_clk_mux_select = "int_clk",
		transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs2
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs2_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs2_dataout),
	.digitalreset(tx_digitalreset_out[2]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_dprioin_wire[449:300]),
	.dprioout(wire_transmit_pcs2_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[2]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs2_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[2], tx_ctrlenable[2], tx_datain_wire[23:16]}),
	.hipdetectrxloop(tx_detectrxloop[2]),
	.hipelecidleinfersel(rx_elecidleinfersel[8:6]),
	.hipforceelecidle(tx_forceelecidle[2]),
	.hippowerdn(powerdn[5:4]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[2]),
	.hiptxmargin(tx_pipemargin[8:6]),
	.invpol(tx_invpolarity[2]),
	.iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
	.localrefclk(tx_localrefclk[2]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[2]),
	.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
	.pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[2]),
	.pipetxswing(tx_pipeswing[2]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
	.txdetectrx(wire_transmit_pcs2_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[2]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs2.allow_polarity_inversion = "false",
		transmit_pcs2.auto_spd_self_switch_enable = "true",
		transmit_pcs2.bitslip_enable = "false",
		transmit_pcs2.channel_bonding = "x8",
		transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
		transmit_pcs2.channel_width = 8,
		transmit_pcs2.core_clock_0ppm = "false",
		transmit_pcs2.datapath_low_latency_mode = "false",
		transmit_pcs2.datapath_protocol = "pipe",
		transmit_pcs2.disable_ph_low_latency_mode = "false",
		transmit_pcs2.disparity_mode = "new",
		transmit_pcs2.dprio_config_mode = 6'h01,
		transmit_pcs2.elec_idle_delay = 6,
		transmit_pcs2.enable_bit_reversal = "false",
		transmit_pcs2.enable_idle_selection = "false",
		transmit_pcs2.enable_reverse_parallel_loopback = "true",
		transmit_pcs2.enable_self_test_mode = "false",
		transmit_pcs2.enable_symbol_swap = "false",
		transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs2.enc_8b_10b_mode = "normal",
		transmit_pcs2.force_echar = "false",
		transmit_pcs2.force_kchar = "false",
		transmit_pcs2.hip_enable = "true",
		transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
		transmit_pcs2.ph_fifo_reg_mode = "true",
		transmit_pcs2.ph_fifo_xn_mapping0 = "none",
		transmit_pcs2.ph_fifo_xn_mapping1 = "none",
		transmit_pcs2.ph_fifo_xn_mapping2 = "central",
		transmit_pcs2.ph_fifo_xn_select = 2,
		transmit_pcs2.pipe_auto_speed_nego_enable = "true",
		transmit_pcs2.pipe_freq_scale_mode = "Frequency",
		transmit_pcs2.pipe_voltage_swing_control = "false",
		transmit_pcs2.prbs_cid_pattern = "false",
		transmit_pcs2.protocol_hint = "pcie2",
		transmit_pcs2.refclk_select = "cmu_clock_divider",
		transmit_pcs2.self_test_mode = "incremental",
		transmit_pcs2.use_double_data_mode = "false",
		transmit_pcs2.use_serializer_double_data_mode = "false",
		transmit_pcs2.wr_clk_mux_select = "int_clk",
		transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs3
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs3_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs3_dataout),
	.digitalreset(tx_digitalreset_out[3]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_dprioin_wire[599:450]),
	.dprioout(wire_transmit_pcs3_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[3]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs3_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[3], tx_ctrlenable[3], tx_datain_wire[31:24]}),
	.hipdetectrxloop(tx_detectrxloop[3]),
	.hipelecidleinfersel(rx_elecidleinfersel[11:9]),
	.hipforceelecidle(tx_forceelecidle[3]),
	.hippowerdn(powerdn[7:6]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[3]),
	.hiptxmargin(tx_pipemargin[11:9]),
	.invpol(tx_invpolarity[3]),
	.iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
	.localrefclk(tx_localrefclk[3]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[3]),
	.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
	.pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[3]),
	.pipetxswing(tx_pipeswing[3]),
	.quadreset(cent_unit_quadresetout[0]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[0]),
	.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
	.txdetectrx(wire_transmit_pcs3_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[3]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs3.allow_polarity_inversion = "false",
		transmit_pcs3.auto_spd_self_switch_enable = "true",
		transmit_pcs3.bitslip_enable = "false",
		transmit_pcs3.channel_bonding = "x8",
		transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
		transmit_pcs3.channel_width = 8,
		transmit_pcs3.core_clock_0ppm = "false",
		transmit_pcs3.datapath_low_latency_mode = "false",
		transmit_pcs3.datapath_protocol = "pipe",
		transmit_pcs3.disable_ph_low_latency_mode = "false",
		transmit_pcs3.disparity_mode = "new",
		transmit_pcs3.dprio_config_mode = 6'h01,
		transmit_pcs3.elec_idle_delay = 6,
		transmit_pcs3.enable_bit_reversal = "false",
		transmit_pcs3.enable_idle_selection = "false",
		transmit_pcs3.enable_reverse_parallel_loopback = "true",
		transmit_pcs3.enable_self_test_mode = "false",
		transmit_pcs3.enable_symbol_swap = "false",
		transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs3.enc_8b_10b_mode = "normal",
		transmit_pcs3.force_echar = "false",
		transmit_pcs3.force_kchar = "false",
		transmit_pcs3.hip_enable = "true",
		transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
		transmit_pcs3.ph_fifo_reg_mode = "true",
		transmit_pcs3.ph_fifo_xn_mapping0 = "none",
		transmit_pcs3.ph_fifo_xn_mapping1 = "none",
		transmit_pcs3.ph_fifo_xn_mapping2 = "central",
		transmit_pcs3.ph_fifo_xn_select = 2,
		transmit_pcs3.pipe_auto_speed_nego_enable = "true",
		transmit_pcs3.pipe_freq_scale_mode = "Frequency",
		transmit_pcs3.pipe_voltage_swing_control = "false",
		transmit_pcs3.prbs_cid_pattern = "false",
		transmit_pcs3.protocol_hint = "pcie2",
		transmit_pcs3.refclk_select = "cmu_clock_divider",
		transmit_pcs3.self_test_mode = "incremental",
		transmit_pcs3.use_double_data_mode = "false",
		transmit_pcs3.use_serializer_double_data_mode = "false",
		transmit_pcs3.wr_clk_mux_select = "int_clk",
		transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs4
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs4_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs4_dataout),
	.digitalreset(tx_digitalreset_out[4]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_dprioin_wire[749:600]),
	.dprioout(wire_transmit_pcs4_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[4]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs4_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs4_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[4], tx_ctrlenable[4], tx_datain_wire[39:32]}),
	.hipdetectrxloop(tx_detectrxloop[4]),
	.hipelecidleinfersel(rx_elecidleinfersel[14:12]),
	.hipforceelecidle(tx_forceelecidle[4]),
	.hippowerdn(powerdn[9:8]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[4]),
	.hiptxmargin(tx_pipemargin[14:12]),
	.invpol(tx_invpolarity[4]),
	.iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
	.localrefclk(tx_localrefclk[4]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[4]),
	.phfiforesetout(wire_transmit_pcs4_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[14:12]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
	.pipeenrevparallellpbkout(wire_transmit_pcs4_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[4]),
	.pipetxswing(tx_pipeswing[4]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[1]),
	.revparallelfdbk(rx_revparallelfdbkdata[99:80]),
	.txdetectrx(wire_transmit_pcs4_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[4]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[39:32]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs4.allow_polarity_inversion = "false",
		transmit_pcs4.auto_spd_self_switch_enable = "true",
		transmit_pcs4.bitslip_enable = "false",
		transmit_pcs4.channel_bonding = "x8",
		transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
		transmit_pcs4.channel_width = 8,
		transmit_pcs4.core_clock_0ppm = "false",
		transmit_pcs4.datapath_low_latency_mode = "false",
		transmit_pcs4.datapath_protocol = "pipe",
		transmit_pcs4.disable_ph_low_latency_mode = "false",
		transmit_pcs4.disparity_mode = "new",
		transmit_pcs4.dprio_config_mode = 6'h01,
		transmit_pcs4.elec_idle_delay = 6,
		transmit_pcs4.enable_bit_reversal = "false",
		transmit_pcs4.enable_idle_selection = "false",
		transmit_pcs4.enable_reverse_parallel_loopback = "true",
		transmit_pcs4.enable_self_test_mode = "false",
		transmit_pcs4.enable_symbol_swap = "false",
		transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs4.enc_8b_10b_mode = "normal",
		transmit_pcs4.force_echar = "false",
		transmit_pcs4.force_kchar = "false",
		transmit_pcs4.hip_enable = "true",
		transmit_pcs4.iqp_ph_fifo_xn_select = 1,
		transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
		transmit_pcs4.ph_fifo_reg_mode = "true",
		transmit_pcs4.ph_fifo_xn_mapping0 = "none",
		transmit_pcs4.ph_fifo_xn_mapping1 = "up",
		transmit_pcs4.ph_fifo_xn_mapping2 = "none",
		transmit_pcs4.ph_fifo_xn_select = 1,
		transmit_pcs4.pipe_auto_speed_nego_enable = "true",
		transmit_pcs4.pipe_freq_scale_mode = "Frequency",
		transmit_pcs4.pipe_voltage_swing_control = "false",
		transmit_pcs4.prbs_cid_pattern = "false",
		transmit_pcs4.protocol_hint = "pcie2",
		transmit_pcs4.refclk_select = "cmu_clock_divider",
		transmit_pcs4.self_test_mode = "incremental",
		transmit_pcs4.use_double_data_mode = "false",
		transmit_pcs4.use_serializer_double_data_mode = "false",
		transmit_pcs4.wr_clk_mux_select = "int_clk",
		transmit_pcs4.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs5
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs5_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs5_dataout),
	.digitalreset(tx_digitalreset_out[5]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_dprioin_wire[899:750]),
	.dprioout(wire_transmit_pcs5_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[5]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs5_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs5_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[5], tx_ctrlenable[5], tx_datain_wire[47:40]}),
	.hipdetectrxloop(tx_detectrxloop[5]),
	.hipelecidleinfersel(rx_elecidleinfersel[17:15]),
	.hipforceelecidle(tx_forceelecidle[5]),
	.hippowerdn(powerdn[11:10]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[5]),
	.hiptxmargin(tx_pipemargin[17:15]),
	.invpol(tx_invpolarity[5]),
	.iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
	.localrefclk(tx_localrefclk[5]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[5]),
	.phfiforesetout(wire_transmit_pcs5_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[17:15]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
	.pipeenrevparallellpbkout(wire_transmit_pcs5_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[5]),
	.pipetxswing(tx_pipeswing[5]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[1]),
	.revparallelfdbk(rx_revparallelfdbkdata[119:100]),
	.txdetectrx(wire_transmit_pcs5_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[5]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[47:40]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs5.allow_polarity_inversion = "false",
		transmit_pcs5.auto_spd_self_switch_enable = "true",
		transmit_pcs5.bitslip_enable = "false",
		transmit_pcs5.channel_bonding = "x8",
		transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
		transmit_pcs5.channel_width = 8,
		transmit_pcs5.core_clock_0ppm = "false",
		transmit_pcs5.datapath_low_latency_mode = "false",
		transmit_pcs5.datapath_protocol = "pipe",
		transmit_pcs5.disable_ph_low_latency_mode = "false",
		transmit_pcs5.disparity_mode = "new",
		transmit_pcs5.dprio_config_mode = 6'h01,
		transmit_pcs5.elec_idle_delay = 6,
		transmit_pcs5.enable_bit_reversal = "false",
		transmit_pcs5.enable_idle_selection = "false",
		transmit_pcs5.enable_reverse_parallel_loopback = "true",
		transmit_pcs5.enable_self_test_mode = "false",
		transmit_pcs5.enable_symbol_swap = "false",
		transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs5.enc_8b_10b_mode = "normal",
		transmit_pcs5.force_echar = "false",
		transmit_pcs5.force_kchar = "false",
		transmit_pcs5.hip_enable = "true",
		transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
		transmit_pcs5.ph_fifo_reg_mode = "true",
		transmit_pcs5.ph_fifo_xn_mapping0 = "none",
		transmit_pcs5.ph_fifo_xn_mapping1 = "up",
		transmit_pcs5.ph_fifo_xn_mapping2 = "none",
		transmit_pcs5.ph_fifo_xn_select = 1,
		transmit_pcs5.pipe_auto_speed_nego_enable = "true",
		transmit_pcs5.pipe_freq_scale_mode = "Frequency",
		transmit_pcs5.pipe_voltage_swing_control = "false",
		transmit_pcs5.prbs_cid_pattern = "false",
		transmit_pcs5.protocol_hint = "pcie2",
		transmit_pcs5.refclk_select = "cmu_clock_divider",
		transmit_pcs5.self_test_mode = "incremental",
		transmit_pcs5.use_double_data_mode = "false",
		transmit_pcs5.use_serializer_double_data_mode = "false",
		transmit_pcs5.wr_clk_mux_select = "int_clk",
		transmit_pcs5.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs6
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs6_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs6_dataout),
	.digitalreset(tx_digitalreset_out[6]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_dprioin_wire[1049:900]),
	.dprioout(wire_transmit_pcs6_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[6]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs6_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs6_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[6], tx_ctrlenable[6], tx_datain_wire[55:48]}),
	.hipdetectrxloop(tx_detectrxloop[6]),
	.hipelecidleinfersel(rx_elecidleinfersel[20:18]),
	.hipforceelecidle(tx_forceelecidle[6]),
	.hippowerdn(powerdn[13:12]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[6]),
	.hiptxmargin(tx_pipemargin[20:18]),
	.invpol(tx_invpolarity[6]),
	.iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
	.localrefclk(tx_localrefclk[6]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[6]),
	.phfiforesetout(wire_transmit_pcs6_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[20:18]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
	.pipeenrevparallellpbkout(wire_transmit_pcs6_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[6]),
	.pipetxswing(tx_pipeswing[6]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[1]),
	.revparallelfdbk(rx_revparallelfdbkdata[139:120]),
	.txdetectrx(wire_transmit_pcs6_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[6]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[55:48]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs6.allow_polarity_inversion = "false",
		transmit_pcs6.auto_spd_self_switch_enable = "true",
		transmit_pcs6.bitslip_enable = "false",
		transmit_pcs6.channel_bonding = "x8",
		transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
		transmit_pcs6.channel_width = 8,
		transmit_pcs6.core_clock_0ppm = "false",
		transmit_pcs6.datapath_low_latency_mode = "false",
		transmit_pcs6.datapath_protocol = "pipe",
		transmit_pcs6.disable_ph_low_latency_mode = "false",
		transmit_pcs6.disparity_mode = "new",
		transmit_pcs6.dprio_config_mode = 6'h01,
		transmit_pcs6.elec_idle_delay = 6,
		transmit_pcs6.enable_bit_reversal = "false",
		transmit_pcs6.enable_idle_selection = "false",
		transmit_pcs6.enable_reverse_parallel_loopback = "true",
		transmit_pcs6.enable_self_test_mode = "false",
		transmit_pcs6.enable_symbol_swap = "false",
		transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs6.enc_8b_10b_mode = "normal",
		transmit_pcs6.force_echar = "false",
		transmit_pcs6.force_kchar = "false",
		transmit_pcs6.hip_enable = "true",
		transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
		transmit_pcs6.ph_fifo_reg_mode = "true",
		transmit_pcs6.ph_fifo_xn_mapping0 = "none",
		transmit_pcs6.ph_fifo_xn_mapping1 = "up",
		transmit_pcs6.ph_fifo_xn_mapping2 = "none",
		transmit_pcs6.ph_fifo_xn_select = 1,
		transmit_pcs6.pipe_auto_speed_nego_enable = "true",
		transmit_pcs6.pipe_freq_scale_mode = "Frequency",
		transmit_pcs6.pipe_voltage_swing_control = "false",
		transmit_pcs6.prbs_cid_pattern = "false",
		transmit_pcs6.protocol_hint = "pcie2",
		transmit_pcs6.refclk_select = "cmu_clock_divider",
		transmit_pcs6.self_test_mode = "incremental",
		transmit_pcs6.use_double_data_mode = "false",
		transmit_pcs6.use_serializer_double_data_mode = "false",
		transmit_pcs6.wr_clk_mux_select = "int_clk",
		transmit_pcs6.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pcs   transmit_pcs7
	( 
	.clkout(),
	.coreclkout(wire_transmit_pcs7_coreclkout),
	.ctrlenable({{3{1'b0}}, 1'b0}),
	.datainfull({44{1'b0}}),
	.dataout(wire_transmit_pcs7_dataout),
	.digitalreset(tx_digitalreset_out[7]),
	.dispval({{3{1'b0}}, 1'b0}),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_dprioin_wire[1199:1050]),
	.dprioout(wire_transmit_pcs7_dprioout),
	.enrevparallellpbk(tx_revparallellpbken[7]),
	.forcedisp({{3{1'b0}}, 1'b0}),
	.forcedispcompliance(1'b0),
	.forceelecidleout(wire_transmit_pcs7_forceelecidleout),
	.grayelecidleinferselout(wire_transmit_pcs7_grayelecidleinferselout),
	.hipdatain({tx_forcedispcompliance[7], tx_ctrlenable[7], tx_datain_wire[63:56]}),
	.hipdetectrxloop(tx_detectrxloop[7]),
	.hipelecidleinfersel(rx_elecidleinfersel[23:21]),
	.hipforceelecidle(tx_forceelecidle[7]),
	.hippowerdn(powerdn[15:14]),
	.hiptxclkout(),
	.hiptxdeemph(tx_pipedeemph[7]),
	.hiptxmargin(tx_pipemargin[23:21]),
	.invpol(tx_invpolarity[7]),
	.iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
	.iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
	.iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
	.iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
	.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
	.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
	.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
	.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
	.localrefclk(tx_localrefclk[7]),
	.parallelfdbkout(),
	.phfifobyteselout(),
	.phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
	.phfifooverflow(),
	.phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
	.phfifordclkout(),
	.phfiforddisable(1'b0),
	.phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
	.phfifordenableout(),
	.phfiforeset(tx_phfiforeset[7]),
	.phfiforesetout(wire_transmit_pcs7_phfiforesetout),
	.phfifounderflow(),
	.phfifowrenable(1'b1),
	.phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
	.phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
	.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[23:21]),
	.phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
	.phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
	.phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
	.pipeenrevparallellpbkout(wire_transmit_pcs7_pipeenrevparallellpbkout),
	.pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
	.pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
	.pipestatetransdone(rx_pipestatetransdoneout[7]),
	.pipetxswing(tx_pipeswing[7]),
	.quadreset(cent_unit_quadresetout[1]),
	.rateswitchout(),
	.rdenablesync(),
	.refclk(refclk_pma[1]),
	.revparallelfdbk(rx_revparallelfdbkdata[159:140]),
	.txdetectrx(wire_transmit_pcs7_txdetectrx),
	.xgmctrl(cent_unit_txctrlout[7]),
	.xgmctrlenable(),
	.xgmdatain(cent_unit_tx_xgmdataout[63:56]),
	.xgmdataout()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.bitslipboundaryselect({5{1'b0}}),
	.coreclk(1'b0),
	.datain({40{1'b0}}),
	.detectrxloop(1'b0),
	.elecidleinfersel({3{1'b0}}),
	.forceelecidle(1'b0),
	.freezptr(1'b0),
	.phfifox4bytesel(1'b0),
	.phfifox4rdclk(1'b0),
	.phfifox4rdenable(1'b0),
	.phfifox4wrenable(1'b0),
	.phfifoxnbottombytesel(1'b0),
	.phfifoxnbottomrdclk(1'b0),
	.phfifoxnbottomrdenable(1'b0),
	.phfifoxnbottomwrenable(1'b0),
	.phfifoxntopbytesel(1'b0),
	.phfifoxntoprdclk(1'b0),
	.phfifoxntoprdenable(1'b0),
	.phfifoxntopwrenable(1'b0),
	.pipetxdeemph(1'b0),
	.pipetxmargin({3{1'b0}}),
	.powerdn({2{1'b0}}),
	.prbscidenable(1'b0),
	.rateswitch(1'b0),
	.rateswitchisdone(1'b0),
	.rateswitchxndone(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pcs7.allow_polarity_inversion = "false",
		transmit_pcs7.auto_spd_self_switch_enable = "true",
		transmit_pcs7.bitslip_enable = "false",
		transmit_pcs7.channel_bonding = "x8",
		transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
		transmit_pcs7.channel_width = 8,
		transmit_pcs7.core_clock_0ppm = "false",
		transmit_pcs7.datapath_low_latency_mode = "false",
		transmit_pcs7.datapath_protocol = "pipe",
		transmit_pcs7.disable_ph_low_latency_mode = "false",
		transmit_pcs7.disparity_mode = "new",
		transmit_pcs7.dprio_config_mode = 6'h01,
		transmit_pcs7.elec_idle_delay = 6,
		transmit_pcs7.enable_bit_reversal = "false",
		transmit_pcs7.enable_idle_selection = "false",
		transmit_pcs7.enable_reverse_parallel_loopback = "true",
		transmit_pcs7.enable_self_test_mode = "false",
		transmit_pcs7.enable_symbol_swap = "false",
		transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
		transmit_pcs7.enc_8b_10b_mode = "normal",
		transmit_pcs7.force_echar = "false",
		transmit_pcs7.force_kchar = "false",
		transmit_pcs7.hip_enable = "true",
		transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
		transmit_pcs7.ph_fifo_reg_mode = "true",
		transmit_pcs7.ph_fifo_xn_mapping0 = "none",
		transmit_pcs7.ph_fifo_xn_mapping1 = "up",
		transmit_pcs7.ph_fifo_xn_mapping2 = "none",
		transmit_pcs7.ph_fifo_xn_select = 1,
		transmit_pcs7.pipe_auto_speed_nego_enable = "true",
		transmit_pcs7.pipe_freq_scale_mode = "Frequency",
		transmit_pcs7.pipe_voltage_swing_control = "false",
		transmit_pcs7.prbs_cid_pattern = "false",
		transmit_pcs7.protocol_hint = "pcie2",
		transmit_pcs7.refclk_select = "cmu_clock_divider",
		transmit_pcs7.self_test_mode = "incremental",
		transmit_pcs7.use_double_data_mode = "false",
		transmit_pcs7.use_serializer_double_data_mode = "false",
		transmit_pcs7.wr_clk_mux_select = "int_clk",
		transmit_pcs7.lpm_type = "stratixiv_hssi_tx_pcs";
	stratixiv_hssi_tx_pma   transmit_pma0
	( 
	.clockout(wire_transmit_pma0_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
	.dataout(wire_transmit_pma0_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_pmadprioin_wire[299:0]),
	.dprioout(wire_transmit_pma0_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[0]),
	.powerdn(cent_unit_txobpowerdn[0]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[0]),
	.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma0_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[0])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma0.analog_power = "auto",
		transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
		transmit_pma0.channel_type = "auto",
		transmit_pma0.clkin_select = 1,
		transmit_pma0.clkmux_delay = "false",
		transmit_pma0.common_mode = "0.65V",
		transmit_pma0.dprio_config_mode = 6'h01,
		transmit_pma0.enable_reverse_serial_loopback = "false",
		transmit_pma0.logical_channel_address = (starting_channel_number + 0),
		transmit_pma0.logical_protocol_hint_0 = "pcie2",
		transmit_pma0.low_speed_test_select = 0,
		transmit_pma0.physical_clkin1_mapping = "x4",
		transmit_pma0.preemp_pretap = 0,
		transmit_pma0.preemp_pretap_inv = "false",
		transmit_pma0.preemp_tap_1 = 0,
		transmit_pma0.preemp_tap_1_a = 28,
		transmit_pma0.preemp_tap_1_b = 22,
		transmit_pma0.preemp_tap_1_c = 7,
		transmit_pma0.preemp_tap_2 = 0,
		transmit_pma0.preemp_tap_2_inv = "false",
		transmit_pma0.protocol_hint = "pcie2",
		transmit_pma0.rx_detect = 0,
		transmit_pma0.serialization_factor = 10,
		transmit_pma0.slew_rate = "off",
		transmit_pma0.termination = "OCT 100 Ohms",
		transmit_pma0.use_external_termination = "false",
		transmit_pma0.use_pma_direct = "false",
		transmit_pma0.use_ser_double_data_mode = "false",
		transmit_pma0.vod_selection = 3,
		transmit_pma0.vod_selection_a = 6,
		transmit_pma0.vod_selection_c = 1,
		transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma1
	( 
	.clockout(wire_transmit_pma1_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
	.dataout(wire_transmit_pma1_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_pmadprioin_wire[599:300]),
	.dprioout(wire_transmit_pma1_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[1]),
	.powerdn(cent_unit_txobpowerdn[1]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[1]),
	.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma1_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[1])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma1.analog_power = "auto",
		transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
		transmit_pma1.channel_type = "auto",
		transmit_pma1.clkin_select = 1,
		transmit_pma1.clkmux_delay = "false",
		transmit_pma1.common_mode = "0.65V",
		transmit_pma1.dprio_config_mode = 6'h01,
		transmit_pma1.enable_reverse_serial_loopback = "false",
		transmit_pma1.logical_channel_address = (starting_channel_number + 1),
		transmit_pma1.logical_protocol_hint_0 = "pcie2",
		transmit_pma1.low_speed_test_select = 0,
		transmit_pma1.physical_clkin1_mapping = "x4",
		transmit_pma1.preemp_pretap = 0,
		transmit_pma1.preemp_pretap_inv = "false",
		transmit_pma1.preemp_tap_1 = 0,
		transmit_pma1.preemp_tap_1_a = 28,
		transmit_pma1.preemp_tap_1_b = 22,
		transmit_pma1.preemp_tap_1_c = 7,
		transmit_pma1.preemp_tap_2 = 0,
		transmit_pma1.preemp_tap_2_inv = "false",
		transmit_pma1.protocol_hint = "pcie2",
		transmit_pma1.rx_detect = 0,
		transmit_pma1.serialization_factor = 10,
		transmit_pma1.slew_rate = "off",
		transmit_pma1.termination = "OCT 100 Ohms",
		transmit_pma1.use_external_termination = "false",
		transmit_pma1.use_pma_direct = "false",
		transmit_pma1.use_ser_double_data_mode = "false",
		transmit_pma1.vod_selection = 3,
		transmit_pma1.vod_selection_a = 6,
		transmit_pma1.vod_selection_c = 1,
		transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma2
	( 
	.clockout(wire_transmit_pma2_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
	.dataout(wire_transmit_pma2_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_pmadprioin_wire[899:600]),
	.dprioout(wire_transmit_pma2_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[2]),
	.powerdn(cent_unit_txobpowerdn[2]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[2]),
	.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma2_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[2])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma2.analog_power = "auto",
		transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
		transmit_pma2.channel_type = "auto",
		transmit_pma2.clkin_select = 1,
		transmit_pma2.clkmux_delay = "false",
		transmit_pma2.common_mode = "0.65V",
		transmit_pma2.dprio_config_mode = 6'h01,
		transmit_pma2.enable_reverse_serial_loopback = "false",
		transmit_pma2.logical_channel_address = (starting_channel_number + 2),
		transmit_pma2.logical_protocol_hint_0 = "pcie2",
		transmit_pma2.low_speed_test_select = 0,
		transmit_pma2.physical_clkin1_mapping = "x4",
		transmit_pma2.preemp_pretap = 0,
		transmit_pma2.preemp_pretap_inv = "false",
		transmit_pma2.preemp_tap_1 = 0,
		transmit_pma2.preemp_tap_1_a = 28,
		transmit_pma2.preemp_tap_1_b = 22,
		transmit_pma2.preemp_tap_1_c = 7,
		transmit_pma2.preemp_tap_2 = 0,
		transmit_pma2.preemp_tap_2_inv = "false",
		transmit_pma2.protocol_hint = "pcie2",
		transmit_pma2.rx_detect = 0,
		transmit_pma2.serialization_factor = 10,
		transmit_pma2.slew_rate = "off",
		transmit_pma2.termination = "OCT 100 Ohms",
		transmit_pma2.use_external_termination = "false",
		transmit_pma2.use_pma_direct = "false",
		transmit_pma2.use_ser_double_data_mode = "false",
		transmit_pma2.vod_selection = 3,
		transmit_pma2.vod_selection_a = 6,
		transmit_pma2.vod_selection_c = 1,
		transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma3
	( 
	.clockout(wire_transmit_pma3_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
	.dataout(wire_transmit_pma3_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
	.dprioin(tx_pmadprioin_wire[1199:900]),
	.dprioout(wire_transmit_pma3_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk2in({2{1'b0}}),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[3]),
	.powerdn(cent_unit_txobpowerdn[3]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in(cmu_analogrefclkout[1:0]),
	.refclk1inpulse(cmu_analogrefclkpulse[0]),
	.refclk2in({2{1'b0}}),
	.refclk2inpulse(1'b0),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[3]),
	.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma3_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[3])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma3.analog_power = "auto",
		transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
		transmit_pma3.channel_type = "auto",
		transmit_pma3.clkin_select = 1,
		transmit_pma3.clkmux_delay = "false",
		transmit_pma3.common_mode = "0.65V",
		transmit_pma3.dprio_config_mode = 6'h01,
		transmit_pma3.enable_reverse_serial_loopback = "false",
		transmit_pma3.logical_channel_address = (starting_channel_number + 3),
		transmit_pma3.logical_protocol_hint_0 = "pcie2",
		transmit_pma3.low_speed_test_select = 0,
		transmit_pma3.physical_clkin1_mapping = "x4",
		transmit_pma3.preemp_pretap = 0,
		transmit_pma3.preemp_pretap_inv = "false",
		transmit_pma3.preemp_tap_1 = 0,
		transmit_pma3.preemp_tap_1_a = 28,
		transmit_pma3.preemp_tap_1_b = 22,
		transmit_pma3.preemp_tap_1_c = 7,
		transmit_pma3.preemp_tap_2 = 0,
		transmit_pma3.preemp_tap_2_inv = "false",
		transmit_pma3.protocol_hint = "pcie2",
		transmit_pma3.rx_detect = 0,
		transmit_pma3.serialization_factor = 10,
		transmit_pma3.slew_rate = "off",
		transmit_pma3.termination = "OCT 100 Ohms",
		transmit_pma3.use_external_termination = "false",
		transmit_pma3.use_pma_direct = "false",
		transmit_pma3.use_ser_double_data_mode = "false",
		transmit_pma3.vod_selection = 3,
		transmit_pma3.vod_selection_a = 6,
		transmit_pma3.vod_selection_c = 1,
		transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma4
	( 
	.clockout(wire_transmit_pma4_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[99:80]}),
	.dataout(wire_transmit_pma4_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_pmadprioin_wire[2099:1800]),
	.dprioout(wire_transmit_pma4_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in({2{1'b0}}),
	.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[4]),
	.powerdn(cent_unit_txobpowerdn[6]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in({2{1'b0}}),
	.refclk1inpulse(1'b0),
	.refclk2in(cmu_analogrefclkout[1:0]),
	.refclk2inpulse(cmu_analogrefclkpulse[0]),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[4]),
	.rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma4_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[6])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma4.analog_power = "auto",
		transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
		transmit_pma4.channel_type = "auto",
		transmit_pma4.clkin_select = 2,
		transmit_pma4.clkmux_delay = "false",
		transmit_pma4.common_mode = "0.65V",
		transmit_pma4.dprio_config_mode = 6'h01,
		transmit_pma4.enable_reverse_serial_loopback = "false",
		transmit_pma4.logical_channel_address = (starting_channel_number + 4),
		transmit_pma4.logical_protocol_hint_0 = "pcie2",
		transmit_pma4.low_speed_test_select = 0,
		transmit_pma4.physical_clkin2_mapping = "xn_top",
		transmit_pma4.preemp_pretap = 0,
		transmit_pma4.preemp_pretap_inv = "false",
		transmit_pma4.preemp_tap_1 = 0,
		transmit_pma4.preemp_tap_1_a = 28,
		transmit_pma4.preemp_tap_1_b = 22,
		transmit_pma4.preemp_tap_1_c = 7,
		transmit_pma4.preemp_tap_2 = 0,
		transmit_pma4.preemp_tap_2_inv = "false",
		transmit_pma4.protocol_hint = "pcie2",
		transmit_pma4.rx_detect = 0,
		transmit_pma4.serialization_factor = 10,
		transmit_pma4.slew_rate = "off",
		transmit_pma4.termination = "OCT 100 Ohms",
		transmit_pma4.use_external_termination = "false",
		transmit_pma4.use_pma_direct = "false",
		transmit_pma4.use_ser_double_data_mode = "false",
		transmit_pma4.vod_selection = 3,
		transmit_pma4.vod_selection_a = 6,
		transmit_pma4.vod_selection_c = 1,
		transmit_pma4.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma5
	( 
	.clockout(wire_transmit_pma5_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[119:100]}),
	.dataout(wire_transmit_pma5_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_pmadprioin_wire[2399:2100]),
	.dprioout(wire_transmit_pma5_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in({2{1'b0}}),
	.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[5]),
	.powerdn(cent_unit_txobpowerdn[7]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in({2{1'b0}}),
	.refclk1inpulse(1'b0),
	.refclk2in(cmu_analogrefclkout[1:0]),
	.refclk2inpulse(cmu_analogrefclkpulse[0]),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[5]),
	.rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma5_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[7])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma5.analog_power = "auto",
		transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
		transmit_pma5.channel_type = "auto",
		transmit_pma5.clkin_select = 2,
		transmit_pma5.clkmux_delay = "false",
		transmit_pma5.common_mode = "0.65V",
		transmit_pma5.dprio_config_mode = 6'h01,
		transmit_pma5.enable_reverse_serial_loopback = "false",
		transmit_pma5.logical_channel_address = (starting_channel_number + 5),
		transmit_pma5.logical_protocol_hint_0 = "pcie2",
		transmit_pma5.low_speed_test_select = 0,
		transmit_pma5.physical_clkin2_mapping = "xn_top",
		transmit_pma5.preemp_pretap = 0,
		transmit_pma5.preemp_pretap_inv = "false",
		transmit_pma5.preemp_tap_1 = 0,
		transmit_pma5.preemp_tap_1_a = 28,
		transmit_pma5.preemp_tap_1_b = 22,
		transmit_pma5.preemp_tap_1_c = 7,
		transmit_pma5.preemp_tap_2 = 0,
		transmit_pma5.preemp_tap_2_inv = "false",
		transmit_pma5.protocol_hint = "pcie2",
		transmit_pma5.rx_detect = 0,
		transmit_pma5.serialization_factor = 10,
		transmit_pma5.slew_rate = "off",
		transmit_pma5.termination = "OCT 100 Ohms",
		transmit_pma5.use_external_termination = "false",
		transmit_pma5.use_pma_direct = "false",
		transmit_pma5.use_ser_double_data_mode = "false",
		transmit_pma5.vod_selection = 3,
		transmit_pma5.vod_selection_a = 6,
		transmit_pma5.vod_selection_c = 1,
		transmit_pma5.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma6
	( 
	.clockout(wire_transmit_pma6_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[139:120]}),
	.dataout(wire_transmit_pma6_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[8]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_pmadprioin_wire[2699:2400]),
	.dprioout(wire_transmit_pma6_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in({2{1'b0}}),
	.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[6]),
	.powerdn(cent_unit_txobpowerdn[8]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in({2{1'b0}}),
	.refclk1inpulse(1'b0),
	.refclk2in(cmu_analogrefclkout[1:0]),
	.refclk2inpulse(cmu_analogrefclkpulse[0]),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[6]),
	.rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma6_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[8])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma6.analog_power = "auto",
		transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
		transmit_pma6.channel_type = "auto",
		transmit_pma6.clkin_select = 2,
		transmit_pma6.clkmux_delay = "false",
		transmit_pma6.common_mode = "0.65V",
		transmit_pma6.dprio_config_mode = 6'h01,
		transmit_pma6.enable_reverse_serial_loopback = "false",
		transmit_pma6.logical_channel_address = (starting_channel_number + 6),
		transmit_pma6.logical_protocol_hint_0 = "pcie2",
		transmit_pma6.low_speed_test_select = 0,
		transmit_pma6.physical_clkin2_mapping = "xn_top",
		transmit_pma6.preemp_pretap = 0,
		transmit_pma6.preemp_pretap_inv = "false",
		transmit_pma6.preemp_tap_1 = 0,
		transmit_pma6.preemp_tap_1_a = 28,
		transmit_pma6.preemp_tap_1_b = 22,
		transmit_pma6.preemp_tap_1_c = 7,
		transmit_pma6.preemp_tap_2 = 0,
		transmit_pma6.preemp_tap_2_inv = "false",
		transmit_pma6.protocol_hint = "pcie2",
		transmit_pma6.rx_detect = 0,
		transmit_pma6.serialization_factor = 10,
		transmit_pma6.slew_rate = "off",
		transmit_pma6.termination = "OCT 100 Ohms",
		transmit_pma6.use_external_termination = "false",
		transmit_pma6.use_pma_direct = "false",
		transmit_pma6.use_ser_double_data_mode = "false",
		transmit_pma6.vod_selection = 3,
		transmit_pma6.vod_selection_a = 6,
		transmit_pma6.vod_selection_c = 1,
		transmit_pma6.lpm_type = "stratixiv_hssi_tx_pma";
	stratixiv_hssi_tx_pma   transmit_pma7
	( 
	.clockout(wire_transmit_pma7_clockout),
	.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[159:140]}),
	.dataout(wire_transmit_pma7_dataout),
	.detectrxpowerdown(cent_unit_txdetectrxpowerdn[9]),
	.dftout(),
	.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
	.dprioin(tx_pmadprioin_wire[2999:2700]),
	.dprioout(wire_transmit_pma7_dprioout),
	.fastrefclk0in({2{1'b0}}),
	.fastrefclk1in({2{1'b0}}),
	.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
	.fastrefclk4in({2{1'b0}}),
	.forceelecidle(tx_pcs_forceelecidleout[7]),
	.powerdn(cent_unit_txobpowerdn[9]),
	.refclk0in({2{1'b0}}),
	.refclk0inpulse(1'b0),
	.refclk1in({2{1'b0}}),
	.refclk1inpulse(1'b0),
	.refclk2in(cmu_analogrefclkout[1:0]),
	.refclk2inpulse(cmu_analogrefclkpulse[0]),
	.refclk4in({2{1'b0}}),
	.refclk4inpulse(1'b0),
	.revserialfdbk(1'b0),
	.rxdetecten(txdetectrxout[7]),
	.rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
	.rxfoundout(wire_transmit_pma7_rxfoundout),
	.seriallpbkout(),
	.txpmareset(tx_analogreset_out[9])
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.datainfull({20{1'b0}}),
	.extra10gin({11{1'b0}}),
	.fastrefclk3in({2{1'b0}}),
	.pclk({5{1'b0}}),
	.refclk3in({2{1'b0}}),
	.refclk3inpulse(1'b0),
	.rxdetectclk(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		transmit_pma7.analog_power = "auto",
		transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
		transmit_pma7.channel_type = "auto",
		transmit_pma7.clkin_select = 2,
		transmit_pma7.clkmux_delay = "false",
		transmit_pma7.common_mode = "0.65V",
		transmit_pma7.dprio_config_mode = 6'h01,
		transmit_pma7.enable_reverse_serial_loopback = "false",
		transmit_pma7.logical_channel_address = (starting_channel_number + 7),
		transmit_pma7.logical_protocol_hint_0 = "pcie2",
		transmit_pma7.low_speed_test_select = 0,
		transmit_pma7.physical_clkin2_mapping = "xn_top",
		transmit_pma7.preemp_pretap = 0,
		transmit_pma7.preemp_pretap_inv = "false",
		transmit_pma7.preemp_tap_1 = 0,
		transmit_pma7.preemp_tap_1_a = 28,
		transmit_pma7.preemp_tap_1_b = 22,
		transmit_pma7.preemp_tap_1_c = 7,
		transmit_pma7.preemp_tap_2 = 0,
		transmit_pma7.preemp_tap_2_inv = "false",
		transmit_pma7.protocol_hint = "pcie2",
		transmit_pma7.rx_detect = 0,
		transmit_pma7.serialization_factor = 10,
		transmit_pma7.slew_rate = "off",
		transmit_pma7.termination = "OCT 100 Ohms",
		transmit_pma7.use_external_termination = "false",
		transmit_pma7.use_pma_direct = "false",
		transmit_pma7.use_ser_double_data_mode = "false",
		transmit_pma7.vod_selection = 3,
		transmit_pma7.vod_selection_a = 6,
		transmit_pma7.vod_selection_c = 1,
		transmit_pma7.lpm_type = "stratixiv_hssi_tx_pma";
	assign
		cal_blk_powerdown = 1'b0,
		cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
		cent_unit_cmudividerdprioout = {wire_cent_unit1_cmudividerdprioout, wire_cent_unit0_cmudividerdprioout},
		cent_unit_cmuplldprioout = {wire_cent_unit1_cmuplldprioout, wire_cent_unit0_cmuplldprioout},
		cent_unit_pllpowerdn = {wire_cent_unit1_pllpowerdn[1:0], wire_cent_unit0_pllpowerdn[1:0]},
		cent_unit_pllresetout = {wire_cent_unit1_pllresetout[1:0], wire_cent_unit0_pllresetout[1:0]},
		cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
		cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
		cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
		cent_unit_rxpcsdprioin = {rx_pcsdprioout[3199:0]},
		cent_unit_rxpcsdprioout = {wire_cent_unit1_rxpcsdprioout[1599:0], wire_cent_unit0_rxpcsdprioout[1599:0]},
		cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
		cent_unit_rxpmadprioout = {wire_cent_unit1_rxpmadprioout[1799:0], wire_cent_unit0_rxpmadprioout[1799:0]},
		cent_unit_tx_dprioin = {{1200{1'b0}}, tx_txdprioout[1199:0]},
		cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout[31:0], wire_cent_unit0_txdataout[31:0]},
		cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
		cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[5:0], wire_cent_unit0_txdetectrxpowerdown[5:0]},
		cent_unit_txdprioout = {wire_cent_unit1_txpcsdprioout[599:0], wire_cent_unit0_txpcsdprioout[599:0]},
		cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
		cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
		cent_unit_txpmadprioout = {wire_cent_unit1_txpmadprioout[1799:0], wire_cent_unit0_txpmadprioout[1799:0]},
		clk_div_clk0in = {pll0_out[7:0]},
		clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div1_dprioout, {400{1'b0}}, {100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
		clk_div_pclkin = {refclk_pma[0], 1'b0},
		cmu_analogfastrefclkout = {wire_central_clk_div1_analogfastrefclkout, wire_central_clk_div0_analogfastrefclkout},
		cmu_analogrefclkout = {wire_central_clk_div1_analogrefclkout, wire_central_clk_div0_analogrefclkout},
		cmu_analogrefclkpulse = {wire_central_clk_div1_analogrefclkpulse, wire_central_clk_div0_analogrefclkpulse},
		coreclkout = {coreclkout_wire[0]},
		coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
		fixedclk_div_in = {fixedclk_div5quad1c, fixedclk_div4quad1c, fixedclk_div3quad1c, fixedclk_div2quad1c, fixedclk_div1quad1c, fixedclk_div0quad1c, fixedclk_div5quad0c, fixedclk_div4quad0c, fixedclk_div3quad0c, fixedclk_div2quad0c, fixedclk_div1quad0c, fixedclk_div0quad0c},
		fixedclk_enable = reconfig_togxb_busy_reg[0],
		fixedclk_fast = {12{1'b1}},
		fixedclk_in = {{2{1'b0}}, {4{fixedclk}}, {2{1'b0}}, {4{fixedclk}}},
		fixedclk_sel = reconfig_togxb_busy_reg[1],
		fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[11]) & fixedclk_div_in[11]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[11])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[10]) & fixedclk_div_in[10]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[10])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[9]) & fixedclk_div_in[9]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[9])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[8]) & fixedclk_div_in[8]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[8])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[7]) & fixedclk_div_in[7]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[7])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[6]) & fixedclk_div_in[6]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[6])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[5]) & fixedclk_div_in[5]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[5])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[4]) & fixedclk_div_in[4]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[4])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in[3]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[3])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in[2]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[2])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in[1]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[1])), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in[0]) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk_in[0]))},
		hip_tx_clkout = {{3{1'b0}}, wire_central_clk_div1_refclkout, {3{1'b0}}, wire_central_clk_div0_refclkout},
		int_autospdx4configsel = {wire_cent_unit1_autospdx4configsel, wire_cent_unit0_autospdx4configsel},
		int_autospdx4rateswitchout = {wire_cent_unit1_autospdx4rateswitchout, wire_cent_unit0_autospdx4rateswitchout},
		int_autospdx4spdchg = {wire_cent_unit1_autospdx4spdchg, wire_cent_unit0_autospdx4spdchg},
		int_hipautospdrateswitchout = {wire_receive_pcs7_autospdrateswitchout, wire_receive_pcs6_autospdrateswitchout, wire_receive_pcs5_autospdrateswitchout, wire_receive_pcs4_autospdrateswitchout, wire_receive_pcs3_autospdrateswitchout, wire_receive_pcs2_autospdrateswitchout, wire_receive_pcs1_autospdrateswitchout, wire_receive_pcs0_autospdrateswitchout},
		int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
		int_phfifiox4ptrsreset = {wire_cent_unit1_phfifiox4ptrsreset, wire_cent_unit0_phfifiox4ptrsreset},
		int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs7_pipeenrevparallellpbkout, wire_transmit_pcs6_pipeenrevparallellpbkout, wire_transmit_pcs5_pipeenrevparallellpbkout, wire_transmit_pcs4_pipeenrevparallellpbkout, wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
		int_rateswitch = {int_rx_rateswitchout[4], int_rx_rateswitchout[0]},
		int_rx_autospdspdchgout = {wire_receive_pcs7_autospdspdchgout, wire_receive_pcs6_autospdspdchgout, wire_receive_pcs5_autospdspdchgout, wire_receive_pcs4_autospdspdchgout, wire_receive_pcs3_autospdspdchgout, wire_receive_pcs2_autospdspdchgout, wire_receive_pcs1_autospdspdchgout, wire_receive_pcs0_autospdspdchgout},
		int_rx_autospdxnconfigsel = {1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], 1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
		int_rx_autospdxnspdchg = {1'b0, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], 1'b0, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
		int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
		int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
		int_rx_iqpautospdxnspgchg = {{3{{2{1'b0}}}}, int_rx_autospdspdchgout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
		int_rx_iqpphfifoptrsresetout = {wire_receive_pcs7_iqpphfifoptrsresetout, wire_receive_pcs6_iqpphfifoptrsresetout, wire_receive_pcs5_iqpphfifoptrsresetout, wire_receive_pcs4_iqpphfifoptrsresetout, wire_receive_pcs3_iqpphfifoptrsresetout, wire_receive_pcs2_iqpphfifoptrsresetout, wire_receive_pcs1_iqpphfifoptrsresetout, wire_receive_pcs0_iqpphfifoptrsresetout},
		int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
		int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
		int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
		int_rx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_iqpphfifoxnptrsreset = {{3{{2{1'b0}}}}, int_rx_iqpphfifoptrsresetout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_iqpphfifoxnwrclk = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
		int_rx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
		int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
		int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
		int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
		int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
		int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
		int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
		int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
		int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
		int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
		int_rx_rateswitchout = {wire_receive_pcs7_rateswitchout, wire_receive_pcs6_rateswitchout, wire_receive_pcs5_rateswitchout, wire_receive_pcs4_rateswitchout, wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
		int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
		int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs7_cdrctrlearlyeios, wire_receive_pcs6_cdrctrlearlyeios, wire_receive_pcs5_cdrctrlearlyeios, wire_receive_pcs4_cdrctrlearlyeios, wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
		int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
		int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
		int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
		int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
		int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
		int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
		int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
		int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
		int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
		int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
		int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
		int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
		int_tx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
		int_tx_iqpphfifoxnrdclk = {{3{{2{1'b0}}}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{{2{1'b0}}}}},
		int_tx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
		int_tx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
		int_tx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
		int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
		int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
		int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
		int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
		int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
		int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
		int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
		int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
		int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
		int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
		int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
		int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
		int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
		int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
		int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
		nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
		pipedatavalid = {pipedatavalid_out[7:0]},
		pipedatavalid_out = {wire_receive_pcs7_hipdatavalid, wire_receive_pcs6_hipdatavalid, wire_receive_pcs5_hipdatavalid, wire_receive_pcs4_hipdatavalid, wire_receive_pcs3_hipdatavalid, wire_receive_pcs2_hipdatavalid, wire_receive_pcs1_hipdatavalid, wire_receive_pcs0_hipdatavalid},
		pipeelecidle = {pipeelecidle_out[7:0]},
		pipeelecidle_out = {wire_receive_pcs7_hipelecidle, wire_receive_pcs6_hipelecidle, wire_receive_pcs5_hipelecidle, wire_receive_pcs4_hipelecidle, wire_receive_pcs3_hipelecidle, wire_receive_pcs2_hipelecidle, wire_receive_pcs1_hipelecidle, wire_receive_pcs0_hipelecidle},
		pipephydonestatus = {wire_receive_pcs7_hipphydonestatus, wire_receive_pcs6_hipphydonestatus, wire_receive_pcs5_hipphydonestatus, wire_receive_pcs4_hipphydonestatus, wire_receive_pcs3_hipphydonestatus, wire_receive_pcs2_hipphydonestatus, wire_receive_pcs1_hipphydonestatus, wire_receive_pcs0_hipphydonestatus},
		pipestatus = {wire_receive_pcs7_hipstatus, wire_receive_pcs6_hipstatus, wire_receive_pcs5_hipstatus, wire_receive_pcs4_hipstatus, wire_receive_pcs3_hipstatus, wire_receive_pcs2_hipstatus, wire_receive_pcs1_hipstatus, wire_receive_pcs0_hipstatus},
		pll0_clkin = {{10{1'b0}}, {9{1'b0}}, pll_inclk_wire[0]},
		pll0_dprioin = {{300{1'b0}}, cent_unit_cmuplldprioout[1499:1200]},
		pll0_dprioout = {{300{1'b0}}, wire_tx_pll0_dprioout},
		pll0_out = {{4{1'b0}}, wire_tx_pll0_clk[3:0]},
		pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
		pll_ch_dprioout = {wire_rx_cdr_pll7_dprioout, wire_rx_cdr_pll6_dprioout, wire_rx_cdr_pll5_dprioout, wire_rx_cdr_pll4_dprioout, wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
		pll_cmuplldprioout = {{600{1'b0}}, pll_ch_dprioout[2399:1200], {300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
		pll_inclk_wire = {pll_inclk},
		pll_locked = {pll_locked_out[0]},
		pll_locked_out = {1'b0, wire_tx_pll0_locked},
		pllpowerdn_in = {{2{1'b0}}, 1'b0, cent_unit_pllpowerdn[0]},
		pllreset_in = {{2{1'b0}}, 1'b0, cent_unit_pllresetout[0]},
		rateswitchbaseclock = {wire_central_clk_div1_rateswitchbaseclock, wire_central_clk_div0_rateswitchbaseclock},
		reconfig_fromgxb = {rx_pma_analogtestbus[33:18], wire_cent_unit1_dprioout, rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
		reconfig_togxb_busy = reconfig_togxb[3],
		reconfig_togxb_disable = reconfig_togxb[1],
		reconfig_togxb_in = reconfig_togxb[0],
		reconfig_togxb_load = reconfig_togxb[2],
		refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
		rx_analogreset_in = {{4{1'b0}}, {8{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
		rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
		rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[7], {9{1'b0}}, rx_pldcruclk_in[6], {9{1'b0}}, rx_pldcruclk_in[5], {9{1'b0}}, rx_pldcruclk_in[4], {9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
		rx_ctrldetect = {wire_receive_pcs7_hipdataout[8], wire_receive_pcs6_hipdataout[8], wire_receive_pcs5_hipdataout[8], wire_receive_pcs4_hipdataout[8], wire_receive_pcs3_hipdataout[8], wire_receive_pcs2_hipdataout[8], wire_receive_pcs1_hipdataout[8], wire_receive_pcs0_hipdataout[8]},
		rx_dataout = {rx_out_wire[63:0]},
		rx_deserclock_in = {rx_pll_clkout[31:0]},
		rx_digitalreset_in = {8{int_rx_digitalreset_reg[0]}},
		rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout[3:0], wire_cent_unit0_rxdigitalresetout[3:0]},
		rx_enapatternalign = {8{1'b0}},
		rx_freqlocked = {(rx_freqlocked_wire[7] & (~ rx_analogreset[0])), (rx_freqlocked_wire[6] & (~ rx_analogreset[0])), (rx_freqlocked_wire[5] & (~ rx_analogreset[0])), (rx_freqlocked_wire[4] & (~ rx_analogreset[0])), (rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
		rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
		rx_locktodata = {8{1'b0}},
		rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[7]), ((~ reconfig_togxb_busy) & rx_locktodata[6]), ((~ reconfig_togxb_busy) & rx_locktodata[5]), ((~ reconfig_togxb_busy) & rx_locktodata[4]), ((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
		rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
		rx_out_wire = {wire_receive_pcs7_hipdataout[7:0], wire_receive_pcs6_hipdataout[7:0], wire_receive_pcs5_hipdataout[7:0], wire_receive_pcs4_hipdataout[7:0], wire_receive_pcs3_hipdataout[7:0], wire_receive_pcs2_hipdataout[7:0], wire_receive_pcs1_hipdataout[7:0], wire_receive_pcs0_hipdataout[7:0]},
		rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
		rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[3199:0]},
		rx_pcsdprioout = {wire_receive_pcs7_dprioout, wire_receive_pcs6_dprioout, wire_receive_pcs5_dprioout, wire_receive_pcs4_dprioout, wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
		rx_phfifordenable = {8{1'b1}},
		rx_phfiforeset = {8{1'b0}},
		rx_phfifowrdisable = {8{1'b0}},
		rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
		rx_pldcruclk_in = {rx_cruclk[7:0]},
		rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
		rx_pll_locked = {(rx_plllocked_wire[7] & (~ rx_analogreset[0])), (rx_plllocked_wire[6] & (~ rx_analogreset[0])), (rx_plllocked_wire[5] & (~ rx_analogreset[0])), (rx_plllocked_wire[4] & (~ rx_analogreset[0])), (rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
		rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
		rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
		rx_pma_analogtestbus = {{102{1'b0}}, wire_receive_pma7_analogtestbus[5:2], wire_receive_pma6_analogtestbus[5:2], wire_receive_pma5_analogtestbus[5:2], wire_receive_pma4_analogtestbus[5:2], 1'b0, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
		rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
		rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
		rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
		rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
		rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
		rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma7_dprioout, wire_receive_pma6_dprioout, wire_receive_pma5_dprioout, wire_receive_pma4_dprioout, {2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
		rx_powerdown = {8{1'b0}},
		rx_powerdown_in = {{4{1'b0}}, rx_powerdown[7:0]},
		rx_prbscidenable = {8{1'b0}},
		rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
		rx_rmfiforeset = {8{1'b0}},
		rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
		rx_signaldetect = {rx_signaldetectout_wire[7:0]},
		rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
		rx_signaldetectout_wire = {wire_receive_pcs7_signaldetect, wire_receive_pcs6_signaldetect, wire_receive_pcs5_signaldetect, wire_receive_pcs4_signaldetect, wire_receive_pcs3_signaldetect, wire_receive_pcs2_signaldetect, wire_receive_pcs1_signaldetect, wire_receive_pcs0_signaldetect},
		rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
		rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
		tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
		tx_datain_wire = {tx_datain[63:0]},
		tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
		tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
		tx_digitalreset_in = {8{int_tx_digitalreset_reg[0]}},
		tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout[3:0], wire_cent_unit0_txdigitalresetout[3:0]},
		tx_dprioin_wire = {{1200{1'b0}}, cent_unit_txdprioout[1199:0]},
		tx_invpolarity = {8{1'b0}},
		tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
		tx_pcs_forceelecidleout = {wire_transmit_pcs7_forceelecidleout, wire_transmit_pcs6_forceelecidleout, wire_transmit_pcs5_forceelecidleout, wire_transmit_pcs4_forceelecidleout, wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
		tx_phfiforeset = {8{1'b0}},
		tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
		tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
		tx_pipeswing = {8{1'b0}},
		tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
		tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma7_dprioout, wire_transmit_pma6_dprioout, wire_transmit_pma5_dprioout, wire_transmit_pma4_dprioout, {2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
		tx_revparallellpbken = {8{1'b0}},
		tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
		tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
		tx_txdprioout = {wire_transmit_pcs7_dprioout, wire_transmit_pcs6_dprioout, wire_transmit_pcs5_dprioout, wire_transmit_pcs4_dprioout, wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
		txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
		w_cent_unit_dpriodisableout1w = {wire_cent_unit1_dpriodisableout, wire_cent_unit0_dpriodisableout};
endmodule //pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pcie_4243_hip_s4gx_gen2_x8_128_serdes (
	cal_blk_clk,
	fixedclk,
	gxb_powerdown,
	pipe8b10binvpolarity,
	pll_inclk,
	pll_powerdown,
	powerdn,
	rateswitch,
	reconfig_clk,
	reconfig_togxb,
	rx_analogreset,
	rx_cruclk,
	rx_datain,
	rx_digitalreset,
	rx_elecidleinfersel,
	tx_ctrlenable,
	tx_datain,
	tx_detectrxloop,
	tx_digitalreset,
	tx_forcedispcompliance,
	tx_forceelecidle,
	tx_pipedeemph,
	tx_pipemargin,
	coreclkout,
	hip_tx_clkout,
	pipedatavalid,
	pipeelecidle,
	pipephydonestatus,
	pipestatus,
	pll_locked,
	rateswitchbaseclock,
	reconfig_fromgxb,
	rx_ctrldetect,
	rx_dataout,
	rx_freqlocked,
	rx_patterndetect,
	rx_pll_locked,
	rx_signaldetect,
	rx_syncstatus,
	tx_dataout)/* synthesis synthesis_clearbox = 2 */;

	input	  cal_blk_clk;
	input	  fixedclk;
	input	[0:0]  gxb_powerdown;
	input	[7:0]  pipe8b10binvpolarity;
	input	  pll_inclk;
	input	[0:0]  pll_powerdown;
	input	[15:0]  powerdn;
	input	[0:0]  rateswitch;
	input	  reconfig_clk;
	input	[3:0]  reconfig_togxb;
	input	[0:0]  rx_analogreset;
	input	[7:0]  rx_cruclk;
	input	[7:0]  rx_datain;
	input	[0:0]  rx_digitalreset;
	input	[23:0]  rx_elecidleinfersel;
	input	[7:0]  tx_ctrlenable;
	input	[63:0]  tx_datain;
	input	[7:0]  tx_detectrxloop;
	input	[0:0]  tx_digitalreset;
	input	[7:0]  tx_forcedispcompliance;
	input	[7:0]  tx_forceelecidle;
	input	[7:0]  tx_pipedeemph;
	input	[23:0]  tx_pipemargin;
	output	[0:0]  coreclkout;
	output	[7:0]  hip_tx_clkout;
	output	[7:0]  pipedatavalid;
	output	[7:0]  pipeelecidle;
	output	[7:0]  pipephydonestatus;
	output	[23:0]  pipestatus;
	output	[0:0]  pll_locked;
	output	[1:0]  rateswitchbaseclock;
	output	[33:0]  reconfig_fromgxb;
	output	[7:0]  rx_ctrldetect;
	output	[63:0]  rx_dataout;
	output	[7:0]  rx_freqlocked;
	output	[7:0]  rx_patterndetect;
	output	[7:0]  rx_pll_locked;
	output	[7:0]  rx_signaldetect;
	output	[7:0]  rx_syncstatus;
	output	[7:0]  tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0	[7:0]  rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	parameter		starting_channel_number = 0;


	wire [7:0] sub_wire0;
	wire [7:0] sub_wire1;
	wire [33:0] sub_wire2;
	wire [23:0] sub_wire3;
	wire [7:0] sub_wire4;
	wire [7:0] sub_wire5;
	wire [0:0] sub_wire6;
	wire [63:0] sub_wire7;
	wire [7:0] sub_wire8;
	wire [7:0] sub_wire9;
	wire [1:0] sub_wire10;
	wire [7:0] sub_wire11;
	wire [7:0] sub_wire12;
	wire [7:0] sub_wire13;
	wire [7:0] sub_wire14;
	wire [0:0] sub_wire15;
	wire [7:0] sub_wire16;
	wire [7:0] rx_patterndetect = sub_wire0[7:0];
	wire [7:0] rx_signaldetect = sub_wire1[7:0];
	wire [33:0] reconfig_fromgxb = sub_wire2[33:0];
	wire [23:0] pipestatus = sub_wire3[23:0];
	wire [7:0] rx_pll_locked = sub_wire4[7:0];
	wire [7:0] rx_syncstatus = sub_wire5[7:0];
	wire [0:0] coreclkout = sub_wire6[0:0];
	wire [63:0] rx_dataout = sub_wire7[63:0];
	wire [7:0] hip_tx_clkout = sub_wire8[7:0];
	wire [7:0] pipeelecidle = sub_wire9[7:0];
	wire [1:0] rateswitchbaseclock = sub_wire10[1:0];
	wire [7:0] tx_dataout = sub_wire11[7:0];
	wire [7:0] rx_ctrldetect = sub_wire12[7:0];
	wire [7:0] pipedatavalid = sub_wire13[7:0];
	wire [7:0] pipephydonestatus = sub_wire14[7:0];
	wire [0:0] pll_locked = sub_wire15[0:0];
	wire [7:0] rx_freqlocked = sub_wire16[7:0];

	pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa	pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa_component (
				.reconfig_togxb (reconfig_togxb),
				.cal_blk_clk (cal_blk_clk),
				.tx_forceelecidle (tx_forceelecidle),
				.fixedclk (fixedclk),
				.rx_datain (rx_datain),
				.rx_digitalreset (rx_digitalreset),
				.pipe8b10binvpolarity (pipe8b10binvpolarity),
				.pll_powerdown (pll_powerdown),
				.tx_datain (tx_datain),
				.tx_digitalreset (tx_digitalreset),
				.tx_pipedeemph (tx_pipedeemph),
				.gxb_powerdown (gxb_powerdown),
				.rx_cruclk (rx_cruclk),
				.tx_forcedispcompliance (tx_forcedispcompliance),
				.rateswitch (rateswitch),
				.reconfig_clk (reconfig_clk),
				.rx_analogreset (rx_analogreset),
				.powerdn (powerdn),
				.tx_ctrlenable (tx_ctrlenable),
				.tx_pipemargin (tx_pipemargin),
				.pll_inclk (pll_inclk),
				.rx_elecidleinfersel (rx_elecidleinfersel),
				.tx_detectrxloop (tx_detectrxloop),
				.rx_patterndetect (sub_wire0),
				.rx_signaldetect (sub_wire1),
				.reconfig_fromgxb (sub_wire2),
				.pipestatus (sub_wire3),
				.rx_pll_locked (sub_wire4),
				.rx_syncstatus (sub_wire5),
				.coreclkout (sub_wire6),
				.rx_dataout (sub_wire7),
				.hip_tx_clkout (sub_wire8),
				.pipeelecidle (sub_wire9),
				.rateswitchbaseclock (sub_wire10),
				.tx_dataout (sub_wire11),
				.rx_ctrldetect (sub_wire12),
				.pipedatavalid (sub_wire13),
				.pipephydonestatus (sub_wire14),
				.pll_locked (sub_wire15),
				.rx_freqlocked (sub_wire16))/* synthesis synthesis_clearbox=2
	 clearbox_macroname = alt4gxb
	 clearbox_defparam = "effective_data_rate=5000 Mbps;enable_lc_tx_pll=false;equalizer_ctrl_a_setting=0;equalizer_ctrl_b_setting=0;equalizer_ctrl_c_setting=0;equalizer_ctrl_d_setting=0;equalizer_ctrl_v_setting=0;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gxb_analog_power=AUTO;gx_channel_type=AUTO;input_clock_frequency=100.0 MHz;intended_device_family=Stratix IV;intended_device_speed_grade=2;intended_device_variant=GX;loopback_mode=none;lpm_type=alt4gxb;number_of_channels=8;operation_mode=duplex;pll_control_width=1;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=0;protocol=pcie2;receiver_termination=oct_100_ohms;reconfig_dprio_mode=1;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x8;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_bandwidth_type=Auto;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=5000;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=true;rx_ppmselect=32;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;
	                      rx_use_clkout=false;rx_use_coreclk=false;rx_use_cruclk=true;rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_analog_power=AUTO;tx_channel_bonding=x8;tx_channel_width=8;tx_clkout_width=8;tx_common_mode=0.65v;tx_data_rate=5000;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=High;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=off;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=3;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;gxb_powerdown_width=1;hip_enable=true;number_of_quads=2;rateswitch_control_width=1;reconfig_calibration=true;reconfig_fromgxb_port_width=34;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_cru_m_divider=0;rx_cru_n_divider=1;rx_cru_vco_post_scale_divider=1;rx_dwidth_factor=1;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;tx_dwidth_factor=1;tx_pll_clock_post_divider=1;tx_pll_m_divider=0;tx_pll_n_divider=1;tx_pll_vco_post_scale_divider=1;tx_use_external_termination=false;" */;
	defparam
		pcie_4243_hip_s4gx_gen2_x8_128_serdes_alt4gxb_c0pa_component.starting_channel_number = starting_channel_number;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x8"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: hip_enable STRING "true"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "34"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "0"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: hip_tx_clkout 0 0 8 0 OUTPUT NODEFVAL "hip_tx_clkout[7..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: pll_powerdown 0 0 1 0 INPUT NODEFVAL "pll_powerdown[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
// Retrieval info: USED_PORT: rateswitchbaseclock 0 0 2 0 OUTPUT NODEFVAL "rateswitchbaseclock[1..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 OUTPUT NODEFVAL "reconfig_fromgxb[33..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 24 0 INPUT NODEFVAL "rx_elecidleinfersel[23..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
// Retrieval info: USED_PORT: rx_signaldetect 0 0 8 0 OUTPUT NODEFVAL "rx_signaldetect[7..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
// Retrieval info: USED_PORT: tx_pipedeemph 0 0 8 0 INPUT NODEFVAL "tx_pipedeemph[7..0]"
// Retrieval info: USED_PORT: tx_pipemargin 0 0 24 0 INPUT NODEFVAL "tx_pipemargin[23..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @pll_powerdown 0 0 1 0 pll_powerdown 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 24 0 rx_elecidleinfersel 0 0 24 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
// Retrieval info: CONNECT: @tx_pipedeemph 0 0 8 0 tx_pipedeemph 0 0 8 0
// Retrieval info: CONNECT: @tx_pipemargin 0 0 24 0 tx_pipemargin 0 0 24 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: hip_tx_clkout 0 0 8 0 @hip_tx_clkout 0 0 8 0
// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: rateswitchbaseclock 0 0 2 0 @rateswitchbaseclock 0 0 2 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 34 0 @reconfig_fromgxb 0 0 34 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
// Retrieval info: CONNECT: rx_signaldetect 0 0 8 0 @rx_signaldetect 0 0 8 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pcie_4243_hip_s4gx_gen2_x8_128_serdes_bb.v FALSE
