hat
Kòm mansyone deja, se faz kontwòl an fèmen riban (PLL) pwodiksyon nan peny 7 itilize kontwole frekans lan konpayi asirans la. Sa a kondui pwodiksyon segondè-benefis Silicon Transistor Q1 ak sa a, nan vire, aplike yon vòltaj kontwòl VC1 atravè de résistances 3.3kΩ seri ak 10kΩ izole rezisteur a.
eng
As mentioned previously, the phase lock loop control (PLL) output at pin 7 is used to control the carrier frequency. This output drives high-gain Darlington transistor Q1 and this, in turn, applies a control voltage to VC1 via two 3.3kΩ series resistors and the 10kΩ isolating resistor.