354925
The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features ( packing , copy , compare ) etc. , and unlike the previous methodologies developed independently by the simulator vendors , is an Accellera standard with support from multiple vendors : Aldec , Cadence , Mentor , and Synopsys .
 Cadence, Mentor
Please list all entity words in the text that fit the category. Output format is "word1, word2". 
Option: location, person, organization 
Text: {0} 
Answer:
 Cadence, Mentor