NetBSD/mips
Thomas, Matt
Since NetBSD 5 was released, the support for MIPS on NetBSD has been completely revamped. It is now one of the more advanced ports of NetBSD. This talk is an overview on what has changed and what the current state of MIPS support and a brief look forward to what else is coming. Subjects to be covered: Why? (Big Embedded space, large amounts of memory, etc). Quick Introduction to the MIPS architecture Overview of XLR/XLS/XLP Overview of what changed (toolchain, SMP, pmap, PCU, compat32, new cpu support, use of MIPS features, fast softint) Design decisions why N32 by default? why no separate mips64? Major features 64-bit address space cpu abstraction dynamic fixups (changing indirect calls to direct calls) splsw UVM changes Fast software interrupts SMP (for NetLogic XLR/XLS/XLP) mostly lockless pmap Choosing a new page size COMPAT_NETBSD32 networking filesystem mounting 32-bit systems N32 Kernels Effects on the NetBSD in general PCU direct-mapped UAREAs COMPAT_NETBSD32 common pmap for TLB based MMUs
 Okay. Yeah, no, that's. It doesn't matter. This ends up in the recording. Hello, everybody. Our presenter is Matt Thomas. He's in California at the moment. He couldn't travel today. He has a great and very detailed presentation for you about the PhD MIPS and a bunch of the changes that he's been making. So I will hand you off to him and then I'll just step in to help with fielding questions when we get to that point. And off we go. So basically, I've been in MIPS stuff since 1989. When I first worked on PMAC before that. So, yeah, MIPS is kind of in my blood. About six years later, I had an FBFC in court at the BFC for a light or for the PMAC, which I actually have never looked at. Fine. Generic MIPS stuff was at FBFC when the MIPS court was at N98. Didn't sit in there. There was no one by the MIPS courts, but most of them were done in between 99 and 2003. And pretty much everything is stagnated since then. Most of you are not, oh, you're just going to seem to agree people agree. The first MIPS was MIPS long, which was the R2000, R2000. It was basically, there'd be two bits with delay slots, load delay slots and all the other things. So they had a really simple TLD, but since they were sold, nobody actually thought of having integrated law enforcement and empty on those courts of real money, which we did that unfortunately. Later on, the MIPS came out, that was for 1,000, and it was for 64-bit MIPS. Later on, that came to 64. And along with that came the MIPS 30. It was a 32-bit locking instruction, and pretty much the same TLD as the MIPS 30. And those are all pretty much the same, but have slight differences. Now, the MIPS architecture, it's split into basically kernel and user address spaces. And one significant thing about MIPS architecture, is sign, which means that kernel addresses are negative and user addresses are positive. In addition to kernel address spaces split three ways. Half of it is used with direct map access, and half is with TLD maps, which means you need a TLD entry to translate the version of the system to the flyer. Now, the direct map access only maps the first 512 May, and split into regions that either map it as hashed or uncached. And pretty much all the MIPS systems only address the first 512 May. I've never actually encountered a MIPS that had addresses outside of 512. Now, the 64-bit address rate that was added to the R4000 is split into four segments. Is there a superboxer? That's pretty really interesting. And then you have the kernel direct map, which is hand-to-case 0, case 8, 1, that encompasses the follows memory up to $15 in bits. And then you have another 2-gig, I mean, 62 bits worth of kernel TLD maps. So you have pretty much all the data spatial. Again, as I said, there's still some on. And, you know, also value-sizzling is very much... Negative value-sizzling is a kernel. I'm just gonna make a superboxer since somebody uses it. As I said, case 8, 0, case 8, 1, still map the first 500-bit physical memory. Now, interesting, since addresses are signed, they're also signed extended and linked. So it turns out that case 8, 1, still is. Except for they are in the top four GA-gibrams such that they're at FFF, F, F, F8, blah, blah, blah, blah, blah. So, I mean, they're basically... The kernel space that was added was added below case 8, 0. As I said, X, X, direct map, all of this is on memory. But the way NIFS does it, to have what are called CCAs, or cache-coherent attributes, they say whether you're memory-coherent, uncache, local cache, and you have a big A to the next case, this design such that it splits into eight segments, one for each GA. So every piece of memory is mapped, you'll put the next 50 to any GA you want. But that actually limits the full amount of physical memory. Unless the system's only at 40 or 8 bits or 44 bits, it's called Addisby. This is the amount that a lot of stuff plays in an engine. Now, mid-sway, in terms of looking at this, is the bit-on-list, and that is called the O32-A we got. And it's pretty much what's used even today on the U. But when the R4000 came out with 64-bit architecture, extended O62 and extended it to tags, blah, blah, blah, and then came up with O64, which is pretty much identical to O32-Sep worth 64-bit flight. Now, over time, maybe we learned both of these two in O62, because you really cannot pass enough arguments and registers. And since memory access, it turns out that really can lead to different increases in speed. So they came out with the N64 ADR, which changes the way, but it'll likely pass 8 arguments rather than 4. It also brings up the fact that you can't pass. Later on, they realized that, hmm, this works pretty well. People still need to get the ABI's, because a lot of the, because it's kind of wasteful for the most part. So they come up with the O32-A, and this is the part except for, flighters are now back to their seats. Longs of 32-bit, but everything else is still there. Longs is still 64, and it's still 32, so they still have to change things via 3 to the BFI. Now, I got engaged while I was kind of doing that 64-bit role. I just never got around to it until somebody paid me to do it. That's just the grace of life. And basically, they wanted N64 on the Armon, and that was brought on by bigger fish. The XLR, XLR, these are very big F-stips. They're a multi-core, they're super-scaler, they dress up, they have a lot of I-O, they have a lot of F-stips. The ones that I've been using have a core, and the first core threads are core, up to 32 threads per chip. And there's the actual feet, you can actually tie multiple chips together, so you can actually get up to 120 threads, and they're a planar score, things have been significantly gone, much larger than 320. So that is a very big thing in our 300-inch and a mixed 32-inch, and that required a lot of changes. They use 40 bits, this one is up to 1 terabyte of RAM, but they don't. And unlike the other 4,000, the previous two used, they actually supported a full 30-inch when you mount the stick. Also, the other earlier, you can only mount 1 terabyte, you've seen terabyte, but they're good. So, they've brought the SLP and can actually do full 60 bits. That's actually what you want to do, maybe, really. They also have multiple, no, DIX on the SLR or multiple PCIe on the SLP, they also have, you know, accelerant, hearing, spell, publicity, compression, networking, and other your-to-use, and regular expression mapping. Well, when I started this, there was a 4,000-inch piece of it. But again, all of these 32-inch, which pretty much meant that 64-bitness was never going to be used, in general, the 3-inch of it all. They only used 9-inch B-address, V-address, which also was a little bit over 500-inch, whole-big-map. These users have, slip-ed, you can take a 2-bit fan, 2-bit divider, it's actually much less than a 512 limit. Now, most of the 3-bit and IO is 512, but that was for things that just did not fit in the case I wanted. Of course, it was unicost strong. It kind of worked for the SLP. So obviously, what I can do is, if it uses 64-bit-address basically, be able to use lots of memory, not a whole or one key, it can actually scheme, gate, or more. Add multi-crosses, and as part of the multi-crosses, I added a 4-perf. 3-inch in fact, it's almost done for 3-inch. So, I have a top-to-ground, I'm going to put it in here. Unlike Spark 64, I'm going to put in the power of DC66 for good. You never really like your 3-bit stuff, 4-bit stuff, or the 3-bit stuff. I pretty much just say, and so I avoided that, and there it is, though, it's all installed in, that's easy. It's all conditional compiled, and a lot of keys. I believe it's identical to between N32s and N032s. We use the standard math stuff, we're doing by SBI, we're doing loading a pointer, loading a long loading a rest. So, it just happens that they're right. Now, there are times where you have an afternoon, what each guy, the kernels compile, also they're happy I know what ABI is, that's the process. And for what kernels, where I had DPP macros, that really tell you what the guy is, so the obscure stuff that you see aren't normally used, which when I look at, I can, I just did that a bit earlier. Now, unlike any other secret reports, the mix of the transport uses a 32-metre ABI, all user programs are like, we use N32 because, basic, LS is not the, nor do 99% of the N032s, maybe once a while, if you're compiling a utility, you can do that in a nice step. Okay, so the most part, probably the, for great controlling. Now, the other significant change from our O32 port, is that the N2L SNHR, kind of, so Amy, so I would have to have had a lot of, like, what are the instructions that are used, for N32? I was working a lot more, working a lot more out, and I just planned it in the second change, so we would need to talk a little bit more. And that's probably, that's something we have, does Amy's Fairhouse flooding apply. Now, the other, if you have a 64-bit kernel, and you use a lens, you name that twice, and look at kernel, but you can see the instructions, it's down a little right, and that's kind of, I don't remember what's on the problem, I meant staff, but we are going to be more and more, so let's do that, and we just actually look at, we get the stuff to be as physical, but it's really not that significant. Then the other big advantage, is a lens, is that if you have a, a kernel that's an ultra-intensive, or if you have a kernel that's small, or if it's a portable lens, if you have, you know, for a usual end, you can use an entry to a, use a lens, so this gives you a, you know, to pick what kernel is more working for your environment. Now, the thing that is very, I just said, obviously we have a very, very big use on it, but, you know, there are people that expect you to work with you, but then you see it's a really cool thing, called the MatNet MediaTree32, so long as you run through the programs, and support it's kernel. And it looks pretty well, it's a cool kernel. It was very, it was a lot of syscall, and some syscalls that were made for, neatly emulated. So, one of the things that had to be done was, often the same thing, so you can see, there are people on which it was not possible for IH to do this first of all, so, I had had mount 2, I had to be able to do various mount structures that are used by various hosts, all different, all oral. Also, the writing software was really not 16, 64, to claim, and that had to be changed to actually become 64 bit cool. And those were the biggest items, getting a basically 64 bit cool kernel. Because not only is the writing for putting stuff, it's for the rock, the mandits also is, and you do a, get IH and let's see, but there's a whole bunch, how do they code it? Now, it's getting more and more, you still have all these 3-bit programs, either as far as HRC or IKHS, all the other pieces that we keep on having kernel on, some of those were 64 bit cool. Now, we turn the data structure, that will be the same whether you would be writing a 3-bit, but you know, and for 64 bit, you go like that. And that helps a lot. But there's still a lot of other grantees, that require splitting, that convert to one or the other, especially if it contains pointer segments. And as I said, I have two bodies, that also compatibility, but does that deal with the freezer programs, instead of working with how it's done? And this, that means that I can punch for the kernel, that even works for I386 or I386. Now, the other thing about doing 64 bit addresses is that, you know, it uses a standard two level top. This is getting updated, but that will only get you. That just stays when you're talking 64 bit or KK. Now, obviously you want something larger than this. You can do a couple of levels, and it says, but I said on a three level, there'll be our three level page table, which gives you a two level interbited address table, which seems to be sufficient for now. Now, if you go with an 8K page table, that actually comes with 15 terabyte address tables. And that's an easy fix, or an easy way to get a larger address table, without adding another level of page table tables. Now, given that most of our programs use three to bit address space, just because it optimized that you still only do a two level lookup, even though, you know, your system is compiled for 64 bit addresses. So there's really that part of additional answer page table, that was given for that top level page table. There's really no overhead that is open to the user, in creating two program and in creating two program modern and new program. They both go through that two level lookup in the second section. The other thing that's significant is that you have 64 bit of address space. That state disk can be used to access memory without meeting the user. This is really useful when you do hash flushes, you just back and forth and it requires all the work on the lookup. Also, all the idle drive, all idle drive. Adders is definitely no VMAX, they're just directly accessible. So, I mean, an example of that is that the PGI is 256 GB So, if you map that with 4MIG or 4K by page show on a lot of them and you would feed up most of your time, that's when you can actually use a PIS to avoid all those side positions. Now, one of the other functions of address space is you find out a lot of VMA devices are pretty much 4K. You have 325 VMA analog PCI devices like DHCR, USB. So, obviously when you're doing an IEL, you need to make sure that you're within that first 4K of the device. And it's not you have a bug. So, what you really want to do is partition your memory between those that are below the 4K, and you'll get more of that white edge in a way of the problem. And now, it comes to the Super-Pixel model. It's kind of like when you go in and out of the programming scene, regardless, they are going to have an address model. And you know why that is, is because you can take advantage of that space and it's a hash plus operation. So, you're asking the virtual headers to the region of your active, I mean, are registered. No, registered, which is 16. Which means, my character team, in the next stage, and I don't have to work with that. Do I have to go back to the stage? Do I not have to go back to the stage? And that's the Super-Pixel model of code. Now, the kernels show how loaded the X-Pace is. And the Super-Pixel model, the nice thing is why it's only instruction loaded into the other band is like you can't move the N64 kernel and you can't move the N64 kernel to the top format. And then, you know, if the boot loader doesn't understand that it's 64, you would have been screwed, but they don't have a loader on the kernel. They're personally happy with the N64 kernel and you can avoid problems with boot loader. We had that when using the boot loader that our mind supplies with their Eval board so it just didn't understand how it's 64. And we're going to modify the firmware we can just load 30-bit kernels on all we have. And it works. Now, the one-stimulation difference between the two kernels and the N64 kernel is the amount of space returned. And 30-bit on the space-side of the kernel is limited to one gate. The core kernel is better to stay set, which is limited to 64.x about it. In reality, we limit a lot less than that. Typically, two gates. That seems to be sufficient. The one problem that we have is we're not just dealing with lots of differences in usage. Different CLB needs different needs what register state is and so they have a whole bunch of so we have a whole bunch of parameters that cause what we can do. A jump that which has the clb repeat that's if you switch the gene that tells us very soon that it needs to be done. But a little more comic back that basically has you check your gene, you check your gene. You know, you should be using LLSC, which is a little much more for this lock-ejecting register-y, resurable comic sequence. If your box is not capable of doing NB, there's no reason to use LLSC for a lot of that. So unless you have a system that really is capable of being multi-processed, we can call this a resurable comic sequence. Is there a microsoft? And then we also have what we call low-core switching genes. Some of the helper genes for us, your IO genes, all the mix borders have the same capability of kind of with core-interrupt and so low-core switch allows us to track that out. And finally, each system has a different inner structure. A power hole or a Y that's meant to click blah blah blah. And we extract that from that sequence. Now the nice thing that is that our MIE has a very good inner structure in the channel of that MIE. All of our I's can be exposed to the rest of MIE. And then the rest of MIE plus very strapped that are problem with that is being abstracted and if you want to close multiple for whatever, you're meant to see a indirect call. There's a question. What's the question, Paul? I would just like to ask if is it just the legacy name? Oh it isn't. Those are basically top or priority levels which are like IPL none, I'm being blah blah blah and how does that actually impact your heart for priority? So I mean you can think of a SPL and IPL as a but there's still a refer to a SPL. No problem. That is us. So basically if calls have a call, we all know that and these are really serious problems. So avoid doing the indirect call. So what I've done I have I have all the routines basically you know call the seven that seven routine basically both get a correction and I place all those names as in there in between sub-startants for example. And when it comes up, you know basically you use this time like this jump back of course and all those are nice and different. So you know you would read the call and you would do that the seven things. So I have a call here it will go in literally read each instruction around the sub and you'll edit and figure out where you use this jump and then it will pass that original location to do a direct call to where this is up with itself. So the nine has a nice abstraction of indirect calls and this is real quick so when you think about assembly files it doesn't care you just do a branch over a gene and then that will be you know thinking termatically later on you actually have to have all this gear in your those and it will automatically take it. Now I think permanently all set of stuff some five to six thousand and some three thousand seconds and all that. There's one thing they would do in there. In fact this work is so well on that I think this is probably different from how it is well and it works just all day there. There's a ton of doing this for arm and occasion. That's what it's all about. Now I think you have to worry about it. The loading of an outmaking of a model and every one of the separate things you have to act though because that's called actually the indirect that would have been used by the sets. You need a little help in your models that's deal with it. And it's much easier to do than it is obviously on an architect that I think by the instructor. How? I don't even want to do this correctly. Now the answer is well, yes. Sure. What's the confirmation on your computer? Uh-huh. Nobody here thinks that for very long architecture to be fun. Except Andrew. But yes, different steps are fun than we do. And all we have to do is after the S&P changes we stop working with the sets and do them in the top. The P-map was not that hard to make. It was mostly changes from the walk-less algorithms by your computing. It was actually a lot of changes I mean, I wouldn't say. Again, the set before the low-box sort of conditional only used on machines capable of writing with the multiple-due. I mean, and so, I mean, those are just very standard of this visually as sort of a standard way of getting it to be done differently. Again, that is a pretty old 21% code. You have to have a code for new things to get your possible to get it's normally it's not that hard to get. It's not that hard to get it's the wall for many of the ones. When you have a machine called Cp1 and it says I need to reschedule the CPU and I have to be made into the U1. But surprisingly it's not very good between our computers. It's still the same thing. And I've got a so, and you can print and I did. I don't want you to only go to my license here. Now one of the other changes that I'm having to work with is the page size. And let's extend a little later. Can you talk about this? This is a beautiful little page. When next 3 came up, the deal page is a single image of the CPU. Now I have to say you have the V8 and it's included a low-core processor. So you have one V8 that's what's lower-dash for the processor. And it's actually a console but it's low-level. It doesn't even have much V8 in it. So I thought about that for a while. Well how hard would it be to make a button? It turned out that it was long, easy to make fun and I was able to get rid of a lot of complex interjections that that's not a good thing. But it'll be good. I only have to go one V. And I can exactly see what it has and where it was before I would have let it be used to begin with. The other advantage of the televised or the long-hitch is that it actually needs energy and when talking about your computer which is only used such as long it can have a big problem. It's not going to be easy to do depending on what things you're doing. And by going through a simple PPP that you think is under the third instruction let's say I missed Q of red TQ red means construction. I was able to actually cut out seven instructions. Now the construction is going to be a little bit difficult. Q to 3 is going to be a lot of time spent on the stack. That's where the instructions then start adding up quite a bit. Now as I said, you have to set the next one to have a minute and a two, you have a minute and a two, you have a minute and a eight, then you have a one to take them'll tell you two and a four and a five and six. You have the one left by just one. But there is time and it's sitting in the The RMI is the top note. It's meant to 64 bits. It hasn't on video security, so we had to have a certain form for that. 5040, or so, but it didn't do pretty much. Same as you, if you want to be able to use those to test down your configuration, and then first, you have some PTAQ that require the RMI to have it. And now, this is where you've gotten rid of the question. It's easy to do. We basically need to make this a protocol. We've done all this before. They require some wireless. You really can build it with standard NVC. So it was easy just to update it and just let it go. Now, part of the answers are those you've been asking about. OK. The last two entries you have for XLT, what is the difference? Well, you can use the NVC for this, before this, before this, for XLT, as long as you're not playing You are multi-possessed. If you have a brain or an inter-thinking, you really have a specific code. You have your form and your address, but for some reason, they didn't actually allow the traditional type of code to be used. So you need code to go out and watch the PLV play your game with it. And that's what you have to have, those variants for the RMI. So you don't have to be strong if you don't have to watch this. There's a currency, so you can use the wireless and the wireless. Does that explain it? Back to your minutes. Most mid-systems have 3D-C22, only 2D-C26-A, it's a bit diffract from the others, or any other small systems. Now those are old-school, like the XLRSL. Now anywhere up to 16 gigabranas are different from what we have in the storage services. But again, they only have the storage, they only have the dust and the cotton. I mean, they are what I call big inventors. Now most of the dimensions of the system are 4.5 or 4.5, and the system is 6XX per piece, which means that when you start to do 6XX or 3XX, you push your system to do it, and the way it is or the way it is realized, that was due to the development of the system. So they added a function execution, which is execution has a criterion. So it's basically a variation of another instruction. This is a different function. So 24x8, why are these the days that the HVs won't work correctly? And again, that's part of the exact set. All while you have that covariance. Of course the inventors know the storage set is the most important thing. Most of the systems that know the memory outside of the casing, they are on you pretty much don't have to worry about. How does the system fit? You have memory outside. Again, I'm not going to say that with those you can't do the same thing with the HVs. Now what are the problems? One you get to it in, and the other you get to work with, that's the problem. Problems are different than you want to use for a gigabit of time. Well, the only problem is that you don't have a lot of stress-mappery in the first five calls. And typically you might find out that you really don't have memory in case you have a few old chronologies that you did. How do you prevent that? That is just splitting everything in pieces. So what I did is I added a half or a clue to your test. You basically wire a frequency to atmosphere and treat it as direct-map memory. Thereby the sending contents are divided. So you can't use a certain memory or whatever you need. That's an option of how much more. It means that there are people that use direct-mappery that they expect to have a signal. It's just quite a little easier. The thing that it uses in ST6GIRL are the exact convectors which goes with a steam finっていう thing anyway. They're a good example to see how they have점run relaunched in the protocol and entered them into the protocol. So again, intitled and partirary on all the other sides, what theseVよ вusteArt, handles is to yangkang the preceding variable. These pages separately, this is not the case in terms of the data. But if we not have pages that have to be processed, the pages of course are not the ones that doesn't necessarily have to be done, and then you have the rest of the pages. Now, if you view events out, now we have virtual cache elements. This basically means that there are really deep, sorry, unset files. So on the diagram, there's always a lot of like cache. And if you look at smaller pages like cache on this, this is the demonstration. Now, typically what happens with a third device of a little like cache is that it's always a way because it's more than that. It's a page that's not a cache one, either on one side or the other. Which means you're not really seeing a cache one. Excuse me for that. Good. This is smaller. Okay. Now the problem is that that's the reason you don't properly send cache to us. And for instance, a third of a CPU is basically done. Oh yeah, we have the data cache stuff and railings. Our data cache is the data that's right there. And then our SLP has the data that's not real. That's what we do. It's just that we go to cache and make it. This comes with a whole bunch of problems and complications in a bad example. Now you can prevent this from being taken your page size and maybe it's greater than or equal to way size. Or you can get to see that it's the bottom part of the first method. Share in the same set. You can never have an alien phone. There will be no alien. You can take care of that as long as you manage your math things and how to use them. Very careful. And that's done by splitting your free list such that they manage their pages by color or what's known and what that unit is done for color of the page. Now the good thing is that you can see audience that is not for other people. Or to stop the coloring. It doesn't do a thing. So now you have to have free lists. It also has to manage these free lists as if it had one free list in target. Instead of after the page is connected, all those fun things that go with your free memory. Much like net-based. There's just one local free list. So if you want to sort of one color. I'm going to go grab some pieces of paper. There over time it's not going to be able to out-use that color. And you can just spend time scratching through your page views and you know the problem. That's the cool side. In addition to this, as I mentioned before, you're not going to grab pieces of paper that are directly at one. So you're not going to include other groups of pages to deal with. So there is a solution. This is one of the things that I had to do for the net. I had it in a time called unity page. So normally you select things by calling each page by a tree. And you have to call it a single digital question of pages. Each of them are all free targets. They're all free. And that's the free minimum. Now there are only free pages. And that's the pages. Now all trapped at any time. Now the nice thing about this is, why? Eventually the free paper is going to be free to the pages. So you'll get more concurrent personality from the pages. Here is the idiosync or the demo in which you can actually have pages on this page on these pages on that page and now on this page on this own page. It is easier than you can page the multiple. And it turns out that for an instance, you might have to call all 20 pages or more pages whenever a page is in front. One of the issues is, in some ways, on a Smeeta or a demo, well the HTTP A instance, of course, didn't have hundreds of calls. And that was bad and unexpected. I'm not afraid about that issue. One of the other issues is, we gather pages, we gather them by color. We kind of map them, because they would be less important to us. And part of the problem is to be with current Ios that are going there. So I have to actually map the pages that are going to be useful for page Ios until the page is back up. And part of this needs to be set up. I get a page called in this, but I have to go into the right page that has the color that F. And reverse it out of the right page that I need to map. I need to go on the right one, not the left one. That's seven colors. This is one reason why you can't map things. It's so useful in that you're going to have a lot of people who are going to look at it. That you just reverse the pages and kind of figure out it. Now the other issue is that there are other parts of the arm that you think are going to be helpful. We're cleaning out the pages that we have to have. Which needs a support. And the other one I have to submit is also a whole part. And so what are the other pieces of that? That's a lot of direct mapping. And we really don't have that bar or speed. One of the things that your current set always needs to be done is to map the pages. It's almost like that. Every time you do a bunch of stuff, it's going to be the new concept. That's a bit of a problem. And so what it helps is that I can direct the map that I need to map that whole set. Yeah, I can state this or it's a zero. That's really always doing that over. It will gain you about a hundred years that might come off all these things out. And so based on what I added to there, part of this is that the current set is going to be the most helpful part of it. And that will help eliminate a whole bunch of things that are going to be zero gain. And the decision is not only by next down to the start of the by-off and a-off. And it's not only looking for a change, it's also going to give a pretty noticeable improvement. The other thing that I had next down off to a, is a portion in another set. And I realized that why I read it first, then you have to change the computer's anything. And so I adapted that towards our people's support. And I actually have a mid-sport set out off to use it, that I just haven't had to think of as mid-sport. And that's coming to me. And again, this is again the idea that has more and more comments there. And the point I'm just going to take that we did was, all the parts, they'd be flugging point-as-out. You flugging point and we only switch some point contacts and somebody else won't fling. Now, I think that you would think that all these important things that they don't. And every part of the system is only in a, they're in our box. And so one of the things that we said, I'm going to be honest a long time, some of the other developers, is that maybe this would be the thing that you have to change in your house. You won't be able to use it. And I'll send you loads and we need another various projects. And we turned that into really what we call for CPU units. And it's useful for you to find it's also a part of your team for all your back-end units. And, you know, at same six of them, you can get them. It's also often used as a rinse-slotting point. And maybe you have three repeat-closed devices for an architect. And you have something to do with it. Maybe the same as the CPU unit, you're going to have to load the CPU unit. And when it's done, oh, that's going to be three repeat-closed. No, it's not the CPU unit. It basically has a release called, I think, the device. Next time you reload this, you're going to have to force no loading back-end units. Either via, you know, processor, test unit, error on initial layer. That's basically all the way to the end. And pretty much covers everything that I did, hopefully, in a few fast ways. And so I want to now state where I'm fortunately, but you can't. Oh. So, one, the one side, you can also, the device, the test unit, the device. Yeah. That's one device in the area, the rest in the area. It really doesn't, it's not the actual fee for today, but it's only devices that are meaning up to be on. For this question, I did not spot normalization of the data card. It's probably only a few days back, because it's not the unit. So those DMAs had to be bounced off. But the current is patient. So we are actually, I think, in a current such that, you know, the CPU, a lot of times, it's not the confirmed memory from the low-core treatment in the middle of the unit. And that helps a lot. Turns out, yeah, we can use some of our framework, or just a book by a friend that's from the HGV. Does that help? Yeah. Any other questions? No one. I think they're all scared. Oh, Chris, go ahead. Hello. What's the question to you, Dan? Is that also a good thing? Is it a good thing to do? Is that also a good thing? Like accessing the capacity of the processor to put the way it was, and then I can say that it's a good thing to do. You can do it that way. I've been around since the beginning of the CQs. And I'm friends with the HGV for the CSTs. The CST is not a good thing to do. How can you do that? The one that's budget-supported to ESP is that it's due to pulling out a load index and so I register to the table to register to be a normal double in the inside version of it. Any other questions? Anyone else? Thank you very much.
 Okay. Yeah, no, that's.  It doesn't matter.  This ends up in the recording.  Hello, everybody.  Our presenter is Matt Thomas.  He's in California at the moment.  He couldn't travel today.  He has a great and very detailed presentation for you  about the PhD MIPS and a bunch of the changes  that he's been making.  So I will hand you off to him  and then I'll just step in to help with fielding questions  when we get to that point.  And off we go.  So basically, I've been in MIPS stuff since 1989.  When I first worked on PMAC before that.  So, yeah, MIPS is kind of in my blood.  About six years later,  I had an FBFC in court at the BFC for a light or for the PMAC,  which I actually have never looked at.  Fine.  Generic MIPS stuff was at FBFC when the MIPS court was at N98.  Didn't sit in there.  There was no one by the MIPS courts,  but most of them were done in between 99 and 2003.  And pretty much everything is stagnated since then.  Most of you are not,  oh, you're just going to seem to agree people agree.  The first MIPS was MIPS long, which was the R2000, R2000.  It was basically,  there'd be two bits with delay slots,  load delay slots and all the other things.  So they had a really simple TLD,  but since they were sold,  nobody actually thought of having integrated law enforcement  and empty on those courts of real money,  which we did that unfortunately.  Later on, the MIPS came out,  that was for 1,000, and it was for 64-bit MIPS.  Later on, that came to 64.  And along with that came the MIPS 30.  It was a 32-bit locking instruction,  and pretty much the same TLD as the MIPS 30.  And those are all pretty much the same,  but have slight differences.  Now, the MIPS architecture,  it's split into basically kernel and user address spaces.  And one significant thing about MIPS architecture,  is sign, which means that kernel addresses are negative  and user addresses are positive.  In addition to kernel address spaces split three ways.  Half of it is used with direct map access,  and half is with TLD maps,  which means you need a TLD entry  to translate the version of the system to the flyer.  Now, the direct map access  only maps the first 512 May,  and split into regions that either map it as hashed or uncached.  And pretty much all the MIPS systems  only address the first 512 May.  I've never actually encountered a MIPS  that had addresses outside of 512.  Now, the 64-bit address rate that was added to the R4000  is split into four segments.  Is there a superboxer?  That's pretty really interesting.  And then you have the kernel direct map,  which is hand-to-case 0, case 8, 1,  that encompasses the follows memory up to $15 in bits.  And then you have another 2-gig,  I mean, 62 bits worth of kernel TLD maps.  So you have pretty much all the data spatial.  Again, as I said, there's still some on.  And, you know, also value-sizzling is very much...  Negative value-sizzling is a kernel.  I'm just gonna make a superboxer since somebody uses it.  As I said, case 8, 0, case 8, 1,  still map the first 500-bit physical memory.  Now, interesting, since addresses are signed,  they're also signed extended and linked.  So it turns out that case 8, 1, still is.  Except for they are in the top four GA-gibrams such that  they're at FFF, F, F, F8, blah, blah, blah, blah, blah.  So, I mean, they're basically...  The kernel space that was added was added below case 8, 0.  As I said, X, X, direct map, all of this is on memory.  But the way NIFS does it,  to have what are called CCAs, or cache-coherent attributes,  they say whether you're memory-coherent, uncache, local cache,  and you have a big A to the next case,  this design such that it splits into eight segments,  one for each GA.  So every piece of memory is mapped,  you'll put the next 50 to any GA you want.  But that actually limits the full amount of physical memory.  Unless the system's only at 40 or 8 bits or 44 bits,  it's called Addisby.  This is the amount that a lot of stuff plays in an engine.  Now, mid-sway, in terms of looking at this,  is the bit-on-list, and that is called the O32-A we got.  And it's pretty much what's used even today on the U.  But when the R4000 came out with 64-bit architecture,  extended O62 and extended it to tags, blah, blah, blah,  and then came up with O64,  which is pretty much identical to O32-Sep worth 64-bit flight.  Now, over time, maybe we learned both of these two in O62,  because you really cannot pass enough arguments and registers.  And since memory access,  it turns out that really can lead to different increases in speed.  So they came out with the N64 ADR,  which changes the way,  but it'll likely pass 8 arguments rather than 4.  It also brings up the fact that you can't pass.  Later on, they realized that,  hmm, this works pretty well.  People still need to get the ABI's,  because a lot of the,  because it's kind of wasteful for the most part.  So they come up with the O32-A,  and this is the part except for,  flighters are now back to their seats.  Longs of 32-bit, but everything else is still there.  Longs is still 64,  and it's still 32,  so they still have to change things via 3 to the BFI.  Now, I got engaged while I was kind of doing that 64-bit role.  I just never got around to it until somebody paid me to do it.  That's just the grace of life.  And basically, they wanted N64 on the Armon,  and that was brought on by bigger fish.  The XLR, XLR, these are very big F-stips.  They're a multi-core, they're super-scaler,  they dress up, they have a lot of I-O, they have a lot of F-stips.  The ones that I've been using have a core,  and the first core threads are core, up to 32 threads per chip.  And there's the actual feet, you can actually tie multiple chips together,  so you can actually get up to 120 threads,  and they're a planar score,  things have been significantly gone, much larger than 320.  So that is a very big thing in our 300-inch and a mixed 32-inch,  and that required a lot of changes.  They use 40 bits, this one is up to 1 terabyte of RAM,  but they don't.  And unlike the other 4,000,  the previous two used, they actually supported a full 30-inch when you mount the stick.  Also, the other earlier, you can only mount 1 terabyte,  you've seen terabyte, but they're good.  So, they've brought the SLP and can actually do full 60 bits.  That's actually what you want to do, maybe, really.  They also have multiple, no,  DIX on the SLR or multiple PCIe on the SLP,  they also have, you know,  accelerant,  hearing,  spell,  publicity,  compression, networking,  and other your-to-use,  and regular expression mapping.  Well, when I started this, there was a 4,000-inch piece of it.  But again, all of these 32-inch,  which pretty much meant that 64-bitness was never going to be used,  in general, the 3-inch of it all.  They only used 9-inch B-address,  V-address, which also was a little bit over 500-inch,  whole-big-map.  These users have, slip-ed,  you can take a 2-bit fan,  2-bit divider,  it's actually much less than a 512 limit.  Now, most of the 3-bit and IO is 512,  but that was for things that just did not fit in the case I wanted.  Of course, it was unicost strong.  It kind of worked for the SLP.  So obviously, what I can do is,  if it uses 64-bit-address basically,  be able to use lots of memory,  not a whole or one key,  it can actually scheme, gate, or more.  Add multi-crosses,  and as part of the multi-crosses,  I added a 4-perf.  3-inch in fact,  it's almost done for 3-inch.  So, I have a top-to-ground,  I'm going to put it in here.  Unlike Spark 64,  I'm going to put in the power of DC66 for good.  You never really like your 3-bit stuff,  4-bit stuff,  or the 3-bit stuff.  I pretty much just say,  and so I avoided that,  and there it is, though,  it's all installed in, that's easy.  It's all conditional compiled,  and a lot of keys.  I believe it's identical to between N32s  and N032s.  We use the standard math stuff,  we're doing by SBI,  we're doing loading a pointer,  loading a long loading a rest.  So, it just happens that they're right.  Now, there are times where  you have an afternoon,  what each guy, the kernels compile,  also they're happy I know what ABI is,  that's the process.  And for what kernels,  where I had DPP macros,  that really tell you what the guy is,  so the obscure stuff that you see  aren't normally used,  which when I look at, I can,  I just did that a bit earlier.  Now, unlike any other secret reports,  the mix of the transport uses a 32-metre ABI,  all user programs are like,  we use N32 because, basic,  LS is not the,  nor do 99% of the N032s,  maybe once a while,  if you're compiling a utility,  you can do that in a nice step.  Okay, so the most part,  probably the,  for great controlling.  Now, the other significant change  from our O32 port,  is that the N2L SNHR,  kind of,  so Amy, so I would have to have had a lot of,  like, what are the instructions that are used,  for N32?  I was working a lot more,  working a lot more out,  and I just planned it in the second change,  so we would need to talk a little bit more.  And that's probably,  that's something we have,  does Amy's Fairhouse flooding apply.  Now, the other,  if you have a 64-bit kernel,  and you use a lens,  you name that twice,  and look at kernel,  but you can see the instructions,  it's down a little right,  and that's kind of,  I don't remember what's on the problem,  I meant staff,  but we are going to be more and more,  so let's do that,  and we just actually look at,  we get the stuff to be as physical,  but it's really not that significant.  Then the other big advantage,  is a lens,  is that if you have a,  a kernel that's an ultra-intensive,  or if you have a kernel that's small,  or if it's a portable lens,  if you have,  you know,  for a usual end,  you can use an entry to a,  use a lens,  so this gives you a,  you know, to pick what kernel is more working  for your environment.  Now, the thing that  is very, I just said,  obviously we have a very, very big use on it,  but, you know,  there are people that expect you to work with you,  but then you see it's a really cool thing,  called the MatNet MediaTree32,  so long as you run  through the programs, and support it's kernel.  And it looks pretty well,  it's a cool kernel.  It was very,  it was a lot of  syscall,  and some syscalls that  were made for,  neatly emulated.  So,  one of the things that had to be done was,  often the same thing,  so you can see,  there are people on which it was not  possible for IH to do this  first of all, so, I had had  mount 2, I had to be able to  do various mount structures  that are used by various hosts,  all different, all oral.  Also, the writing software  was really not 16, 64,  to claim,  and that had to be changed  to actually become  64 bit cool. And those were the  biggest items, getting a  basically 64 bit cool kernel.  Because not only is the writing  for putting stuff, it's for  the rock, the mandits also is,  and you do a, get IH  and let's see,  but there's a whole bunch,  how do they code it?  Now,  it's getting more  and more, you still have all these  3-bit programs, either as far  as HRC  or IKHS,  all the other pieces that we keep  on having kernel on, some of those  were 64 bit cool. Now, we  turn the data structure, that will be the same  whether you would be writing a 3-bit,  but you know, and for 64 bit,  you go like that. And that helps a lot.  But there's still a lot of other  grantees, that  require splitting,  that convert to one or the other,  especially if it contains  pointer segments.  And as I said, I have  two bodies,  that also  compatibility, but  does that deal  with the freezer programs,  instead of working with how it's done?  And this, that means that  I can punch  for the kernel,  that even works for I386  or I386.  Now, the other  thing about doing 64 bit  addresses is that, you know,  it uses a standard two level  top.  This is getting updated, but  that will only get you.  That just stays when you're talking  64 bit or KK.  Now, obviously  you want something larger than this.  You can do a couple of levels,  and it says,  but I said on a three level,  there'll be  our three level page table,  which gives you a two level  interbited address table,  which seems to be sufficient for now.  Now, if you go with an 8K page table,  that actually comes with  15 terabyte address tables.  And that's an easy fix,  or an easy way to get a larger address table,  without adding another level  of page table tables.  Now, given that most of our programs  use three to bit address space,  just because it optimized  that you still only do  a two level lookup,  even though, you know, your system is  compiled for 64 bit  addresses. So there's really  that part of additional  answer page table,  that was  given for that top level page table.  There's really no overhead  that is open to the user,  in creating  two program  and in creating two program  modern and new program.  They both go through that  two level lookup  in the second  section.  The other thing that's significant  is that you have 64 bit of address space.  That state disk can be used  to access memory without meeting  the user.  This is really useful when you do  hash flushes,  you just back and forth  and it requires  all the work on the lookup.  Also, all the idle drive,  all idle drive. Adders is definitely  no VMAX, they're just directly  accessible.  So, I mean,  an example of that is  that  the PGI is  256 GB  So, if you map that  with 4MIG  or 4K by page show  on a lot of them  and you would feed up  most of your  time,  that's when you can actually use  a PIS to avoid all those  side positions.  Now, one of the other  functions of address space  is you find out  a lot of VMA devices  are pretty much 4K.  You have  325 VMA analog PCI devices  like DHCR, USB.  So, obviously  when you're doing an IEL, you need to  make sure that you're within that first 4K  of the device.  And it's not you have a bug.  So, what you really want to do is  partition your memory between  those that are below the 4K,  and you'll get more of that  white edge  in a way of the problem.  And now, it comes to the Super-Pixel  model.  It's kind of like when you go  in and out of the  programming scene,  regardless, they are  going to have an address model.  And you know why that is, is because  you can take advantage of that space  and it's a hash plus operation.  So, you're asking the virtual headers  to the region of your active,  I mean, are registered.  No, registered, which is 16.  Which means, my character  team,  in the next stage,  and I don't have to work with that.  Do I have to go back to the stage?  Do I not have to go back to the stage?  And that's  the Super-Pixel model of code.  Now, the kernels  show how  loaded the X-Pace  is.  And the  Super-Pixel model, the nice thing is  why it's only instruction loaded into  the other band is like  you can't move the N64 kernel  and you can't move the N64  kernel to the top format.  And then, you know, if  the boot loader doesn't understand that it's 64,  you would have been screwed, but  they don't have a loader on the  kernel. They're personally happy  with the N64 kernel  and you can  avoid problems with boot loader.  We had that when using  the boot loader that  our mind supplies with their Eval board  so it just didn't understand how it's 64.  And we're going to modify the firmware  we can just load  30-bit kernels on all we have.  And it works.  Now, the one-stimulation  difference between the two kernels  and the N64 kernel is the amount  of space returned.  And 30-bit on the  space-side of the kernel is limited to one gate.  The core kernel is  better to stay set, which is limited to  64.x about it.  In reality, we limit  a lot less than that.  Typically, two gates. That seems to be sufficient.  The one problem that we  have is we're not just dealing with  lots of differences in usage.  Different  CLB  needs  different  needs  what register state is  and so they have a whole bunch of  so  we have a whole bunch of  parameters that cause  what we can do.  A jump that which has the clb  repeat that's if you switch  the gene that tells us  very soon that it needs to be done.  But a little more comic  back that basically has  you check your gene, you  check your gene.  You know, you should be using  LLSC, which is a little  much more  for this lock-ejecting  register-y, resurable  comic sequence.  If your box is not capable  of doing NB,  there's no reason to use LLSC  for a lot of that.  So unless  you have a system that really is capable  of being multi-processed, we can  call this a resurable  comic sequence.  Is there a microsoft?  And then we also have what we call  low-core switching genes.  Some of the helper genes for us,  your IO genes,  all the mix  borders have the same capability  of  kind of with core-interrupt  and so low-core switch allows us  to track that out.  And finally,  each system has  a different inner structure.  A power hole or a Y  that's meant to  click  blah blah blah.  And we extract that from that sequence.  Now the nice thing  that is that our MIE  has a very good inner structure  in the  channel of that MIE.  All of our I's  can be exposed to the rest of MIE.  And then the rest of MIE  plus  very  strapped  that are  problem with that  is being abstracted and  if you want to close multiple  for whatever,  you're meant to see a  indirect call.  There's a question.  What's the question, Paul?  I would  just like to ask  if  is it just the legacy name?  Oh it isn't.  Those are basically  top or priority levels which are  like  IPL none, I'm being  blah blah blah and how does that  actually impact your heart for priority?  So I mean  you can think of a SPL  and IPL as a  but there's still a refer to  a SPL.  No problem.  That is us.  So basically  if  calls have a call, we all know that  and these are really  serious problems.  So  avoid  doing the indirect call.  So what I've done  I have  I have  all the routines basically  you know call the  seven  that seven routine basically  both get a correction  and I place  all those names  as in there  in between sub-startants  for example.  And when it  comes up, you know  basically  you use this time like this  jump back of course  and all those are nice and  different.  So you know  you would read the call  and you would do that the seven  things.  So I have a call here  it will go in  literally  read each instruction  around the sub  and you'll edit and figure out where  you use this jump and then it will  pass that original location  to do a direct call to where this  is up with itself.  So the nine has a nice  abstraction of  indirect calls  and this is real quick  so when you think about assembly files  it doesn't care  you just do a branch over a gene  and then that will be  you know thinking termatically later on  you actually have to have all this  gear in your  those  and it will  automatically  take it.  Now I think permanently  all set of stuff  some  five to six thousand  and some  three thousand seconds  and all that.  There's one thing they would  do in there.  In fact this work is so well on that  I think this is probably  different from how it is well  and it works just all day there.  There's a ton of doing this for arm  and occasion.  That's what it's all about.  Now  I think you have to worry about it.  The loading of an outmaking of a model  and every one of the separate things  you have to act though because that's called  actually the  indirect  that would have been used by the sets.  You need a little help in your models  that's deal with it.  And it's much easier to do than it is  obviously on an architect that I think  by the instructor.  How?  I don't even want to do this  correctly.  Now the answer is  well, yes.  Sure.  What's the confirmation  on your computer?  Uh-huh.  Nobody here thinks that for very long  architecture to be fun.  Except Andrew.  But yes,  different steps are fun  than we do.  And  all we have to do  is after the S&P changes  we stop  working with the sets  and do them in the top.  The P-map was not that hard  to make.  It was mostly changes  from the  walk-less  algorithms  by your computing.  It was actually a lot of changes  I mean, I wouldn't say.  Again, the set before  the low-box sort of conditional  only used on machines capable of  writing with the  multiple-due.  I mean,  and so,  I mean,  those are just  very standard  of this  visually as sort of a  standard way of getting it  to be done differently.  Again, that is  a pretty old  21%  code.  You have to have a code  for new things  to get your possible  to get  it's normally  it's not that hard  to get.  It's not that hard  to get  it's the wall for  many of the  ones.  When  you have a machine called Cp1  and it says  I need to reschedule the CPU  and I have to be made into the U1.  But surprisingly  it's not very good  between our computers.  It's still the same thing.  And I've got a  so, and you can print  and I did.  I don't want you to only go  to my license here.  Now one of the other changes  that I'm having to work with  is the page size.  And let's extend a little later.  Can you talk about this?  This is a beautiful little page.  When  next 3 came up, the deal page  is a single image  of the CPU.  Now  I have to say you have the V8  and it's included  a low-core  processor.  So you have one V8  that's  what's lower-dash  for the processor.  And it's actually a console  but it's low-level.  It doesn't even have much V8 in it.  So  I thought about that for a while.  Well how hard would it be  to make a button?  It turned out that it was  long, easy to make fun  and I was able to  get rid of a lot of complex  interjections  that that's not a good thing.  But it'll be good.  I only have to go one V.  And I can  exactly see what it has  and  where it was before I would have  let it be used  to begin with.  The other advantage of the televised  or the long-hitch  is that  it actually  needs energy  and when talking about your  computer which is only  used such as long  it can have a big  problem.  It's not going to be  easy to do depending on  what things you're doing.  And by going through  a simple PPP  that you think is under the  third instruction  let's say I missed  Q  of red TQ  red means construction.  I was able to actually cut  out seven instructions.  Now the construction  is going to be a little bit  difficult.  Q to 3  is going to be a lot of  time spent on the stack.  That's where the instructions  then start adding up  quite a bit.  Now  as I said, you have to  set the next one  to have a minute and a  two, you have a minute and a  two, you have a minute and a  eight, then you have a one  to take  them'll tell you  two and a  four and a  five and six.  You have the one  left by just  one.  But there is  time and it's  sitting in the  The RMI is the top note.  It's meant to 64 bits.  It hasn't on video security, so we had to have  a certain form for that.  5040, or so, but it didn't do pretty much.  Same as you, if you want to be able to use those  to test down your configuration, and then first,  you have some PTAQ that require the RMI to have it.  And now, this is where you've gotten rid of the question.  It's easy to do.  We basically need to make this a protocol.  We've done all this before.  They require some wireless.  You really can build it with standard NVC.  So it was easy just to update it and just let it go.  Now, part of the answers are those you've  been asking about.  OK.  The last two entries you have for XLT, what is the difference?  Well, you can use the NVC for this, before this, before  this, for XLT, as long as you're not playing  You are multi-possessed.  If you have a brain or an inter-thinking, you really  have a specific code.  You have your form and your address, but for some reason,  they didn't actually allow the traditional  type of code to be used.  So you need code to go out and watch the  PLV play your game with it.  And that's what you have to have, those variants for the  RMI.  So you don't have to be strong if you don't have to  watch this.  There's a currency, so you can use the wireless  and the wireless.  Does that explain it?  Back to your minutes.  Most mid-systems have 3D-C22, only 2D-C26-A,  it's a bit diffract from the others, or any other  small systems.  Now those are old-school, like the XLRSL.  Now anywhere up to 16 gigabranas are different  from what we have in the storage services.  But again, they only have the storage, they only  have the dust and the cotton.  I mean, they are what I call big inventors.  Now most of the dimensions of the system are  4.5 or 4.5, and the system is 6XX per piece,  which means that when you start to do 6XX or 3XX,  you push your system to do it, and the way it is  or the way it is realized, that was due to the  development of the system.  So they added a function execution, which is  execution has a criterion.  So it's basically a variation of another instruction.  This is a different function.  So 24x8, why are these the days that the HVs  won't work correctly?  And again, that's part of the exact set.  All while you have that covariance.  Of course the inventors know the storage  set is the most important thing.  Most of the systems that know the memory  outside of the casing, they are on you pretty much  don't have to worry about.  How does the system fit?  You have memory outside.  Again, I'm not going to say that with those  you can't do the same thing with the HVs.  Now what are the problems?  One you get to it in, and the other you get to  work with, that's the problem.  Problems are different than you want to use for  a gigabit of time.  Well, the only problem is that you don't  have a lot of stress-mappery in the first five  calls.  And typically you might find out that you really  don't have memory in case you have a few old  chronologies that you did.  How do you prevent that?  That is just splitting everything in pieces.  So what I did is I added a half or a clue to your  test.  You basically wire a frequency to  atmosphere and treat it as direct-map memory.  Thereby the sending contents are divided.  So you can't use a certain memory or whatever you  need.  That's an option of how much more.  It means that there are people that use  direct-mappery that they expect to have a  signal.  It's just quite a little easier.  The thing that it uses in ST6GIRL are  the exact convectors which goes with a  steam finっていう thing anyway.  They're a good example to see how they  have점run relaunched in the protocol and  entered them into the protocol.  So again, intitled and  partirary on all the other sides,  what theseVよ вusteArt,  handles is to yangkang the  preceding  variable.  These pages separately, this is not the case in terms of the data.  But if we not have pages that have to be processed, the pages of course are not the ones that doesn't  necessarily have to be done, and then you have the rest of the pages.  Now, if you view events out, now we have virtual cache elements.  This basically means that there are really deep, sorry, unset files.  So on the diagram, there's always a lot of like cache.  And if you look at smaller pages like cache on this, this is the demonstration.  Now, typically what happens with a third device of a little like cache is that it's always a way because it's more than that.  It's a page that's not a cache one, either on one side or the other.  Which means you're not really seeing a cache one.  Excuse me for that. Good. This is smaller.  Okay. Now the problem is that that's the reason you don't properly send cache to us.  And for instance, a third of a CPU is basically done. Oh yeah, we have the data cache stuff and railings.  Our data cache is the data that's right there.  And then our SLP has the data that's not real. That's what we do.  It's just that we go to cache and make it. This comes with a whole bunch of problems and complications in a bad example.  Now you can prevent this from being taken your page size and maybe it's greater than or equal to way size.  Or you can get to see that it's the bottom part of the first method. Share in the same set.  You can never have an alien phone. There will be no alien.  You can take care of that as long as you manage your math things and how to use them.  Very careful. And that's done by splitting your free list such that they manage their pages by color or what's known and what that unit is done for color of the page.  Now the good thing is that you can see audience that is not for other people. Or to stop the coloring.  It doesn't do a thing.  So now you have to have free lists. It also has to manage these free lists as if it had one free list in target.  Instead of after the page is connected, all those fun things that go with your free memory.  Much like net-based. There's just one local free list.  So if you want to sort of one color. I'm going to go grab some pieces of paper.  There over time it's not going to be able to out-use that color.  And you can just spend time scratching through your page views and you know the problem.  That's the cool side.  In addition to this, as I mentioned before, you're not going to grab pieces of paper that are directly at one.  So you're not going to include other groups of pages to deal with.  So there is a solution. This is one of the things that I had to do for the net.  I had it in a time called unity page.  So normally you select things by calling each page by a tree.  And you have to call it a single digital question of pages.  Each of them are all free targets. They're all free.  And that's the free minimum. Now there are only free pages.  And that's the pages. Now all trapped at any time.  Now the nice thing about this is, why?  Eventually the free paper is going to be free to the pages.  So you'll get more concurrent personality from the pages.  Here is the idiosync or the demo in which you can actually have pages on this page  on these pages on that page and now on this page on this own page.  It is easier than you can page the multiple.  And it turns out that for an instance, you might have to call all 20 pages or more pages whenever a page is in front.  One of the issues is, in some ways, on a Smeeta or a demo,  well the HTTP A instance, of course, didn't have hundreds of calls.  And that was bad and unexpected.  I'm not afraid about that issue.  One of the other issues is, we gather pages, we gather them by color.  We kind of map them, because they would be less important to us.  And part of the problem is to be with current Ios that are going there.  So I have to actually map the pages that are going to be useful for page Ios until the page is back up.  And part of this needs to be set up.  I get a page called in this, but I have to go into the right page that has the color that F.  And reverse it out of the right page that I need to map.  I need to go on the right one, not the left one.  That's seven colors.  This is one reason why you can't map things.  It's so useful in that you're going to have a lot of people who are going to look at it.  That you just reverse the pages and kind of figure out it.  Now the other issue is that there are other parts of the arm that you think are going to be helpful.  We're cleaning out the pages that we have to have.  Which needs a support.  And the other one I have to submit is also a whole part.  And so what are the other pieces of that?  That's a lot of direct mapping.  And we really don't have that bar or speed.  One of the things that your current set always needs to be done is to map the pages.  It's almost like that.  Every time you do a bunch of stuff, it's going to be the new concept.  That's a bit of a problem.  And so what it helps is that I can direct the map that I need to map that whole set.  Yeah, I can state this or it's a zero.  That's really always doing that over.  It will gain you about a hundred years that might come off all these things out.  And so based on what I added to there, part of this is that the current set is going to be the most helpful part of it.  And that will help eliminate a whole bunch of things that are going to be zero gain.  And the decision is not only by next down to the start of the by-off and a-off.  And it's not only looking for a change, it's also going to give a pretty noticeable improvement.  The other thing that I had next down off to a, is a portion in another set.  And I realized that why I read it first, then you have to change the computer's anything.  And so I adapted that towards our people's support.  And I actually have a mid-sport set out off to use it, that I just haven't had to think of as mid-sport.  And that's coming to me.  And again, this is again the idea that has more and more comments there.  And the point I'm just going to take that we did was, all the parts, they'd be flugging point-as-out.  You flugging point and we only switch some point contacts and somebody else won't fling.  Now, I think that you would think that all these important things that they don't.  And every part of the system is only in a, they're in our box.  And so one of the things that we said, I'm going to be honest a long time, some of the other developers,  is that maybe this would be the thing that you have to change in your house.  You won't be able to use it.  And I'll send you loads and we need another various projects.  And we turned that into really what we call for CPU units.  And it's useful for you to find it's also a part of your team for all your back-end units.  And, you know, at same six of them, you can get them.  It's also often used as a rinse-slotting point.  And maybe you have three repeat-closed devices for an architect.  And you have something to do with it.  Maybe the same as the CPU unit, you're going to have to load the CPU unit.  And when it's done, oh, that's going to be three repeat-closed.  No, it's not the CPU unit.  It basically has a release called, I think, the device.  Next time you reload this, you're going to have to force no loading back-end units.  Either via, you know, processor, test unit, error on initial layer.  That's basically all the way to the end.  And pretty much covers everything that I did, hopefully, in a few fast ways.  And so I want to now state where I'm fortunately, but you can't.  Oh.  So, one, the one side, you can also, the device, the test unit, the device.  Yeah.  That's one device in the area, the rest in the area.  It really doesn't, it's not the actual fee for today,  but it's only devices that are meaning up to be on.  For this question, I did not spot normalization of the data card.  It's probably only a few days back, because it's not the unit.  So those DMAs had to be bounced off.  But the current is patient.  So we are actually, I think, in a current such that, you know, the CPU,  a lot of times, it's not the confirmed memory from the low-core treatment in the middle of the unit.  And that helps a lot.  Turns out, yeah, we can use some of our framework,  or just a book by a friend that's from the HGV.  Does that help?  Yeah.  Any other questions?  No one.  I think they're all scared.  Oh, Chris, go ahead.  Hello.  What's the question to you, Dan?  Is that also a good thing?  Is it a good thing to do?  Is that also a good thing?  Like accessing the capacity of the processor to put the way it was,  and then I can say that it's a good thing to do.  You can do it that way.  I've been around since the beginning of the CQs.  And I'm friends with the HGV for the CSTs.  The CST is not a good thing to do.  How can you do that?  The one that's budget-supported to ESP  is that it's due to pulling out a load index  and so I register to the table to register to be  a normal double in the inside version of it.  Any other questions?  Anyone else?  Thank you very much.
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Okay. Yeah, no, that's. It doesn't matter. This ends up in the recording. Hello, everybody. Our presenter is Matt Thomas. He's in California at the moment. He couldn't travel today. He has a great and very detailed presentation for you about the PhD MIPS and a bunch of the changes that he's been making. So I will hand you off to him and then I'll just step in to help with fielding questions when we get to that point. And off we go. So basically, I've been in MIPS stuff since 1989. When I first worked on PMAC before that. So, yeah, MIPS is kind of in my blood. About six years later, I had an FBFC in court at the BFC for a light or for the PMAC, which I actually have never looked at. Fine. Generic MIPS stuff was at FBFC when the MIPS court was at N98. Didn't sit in there. There was no one by the MIPS courts, but most of them were done in between 99 and 2003. And pretty much everything is stagnated since then. Most of you are not, oh, you're just going to seem to agree people agree. The first MIPS was MIPS long, which was the R2000, R2000. It was basically, there'd be two bits with delay slots, load delay slots and all the other things. So they had a really simple TLD, but since they were sold, nobody actually thought of having integrated law enforcement and empty on those courts of real money, which we did that unfortunately. Later on, the MIPS came out, that was for 1,000, and it was for 64-bit MIPS. Later on, that came to 64. And along with that came the MIPS 30. It was a 32-bit locking instruction, and pretty much the same TLD as the MIPS 30. And those are all pretty much the same, but have slight differences. Now, the MIPS architecture, it's split into basically kernel and user address spaces. And one significant thing about MIPS architecture, is sign, which means that kernel addresses are negative and user addresses are positive. In addition to kernel address spaces split three ways. Half of it is used with direct map access, and half is with TLD maps, which means you need a TLD entry to translate the version of the system to the flyer. Now, the direct map access only maps the first 512 May, and split into regions that either map it as hashed or uncached. And pretty much all the MIPS systems only address the first 512 May. I've never actually encountered a MIPS that had addresses outside of 512. Now, the 64-bit address rate that was added to the R4000 is split into four segments. Is there a superboxer? That's pretty really interesting. And then you have the kernel direct map, which is hand-to-case 0, case 8, 1, that encompasses the follows memory up to $15 in bits. And then you have another 2-gig, I mean, 62 bits worth of kernel TLD maps. So you have pretty much all the data spatial. Again, as I said, there's still some on. And, you know, also value-sizzling is very much... Negative value-sizzling is a kernel. I'm just gonna make a superboxer since somebody uses it. As I said, case 8, 0, case 8, 1, still map the first 500-bit physical memory. Now, interesting, since addresses are signed, they're also signed extended and linked. So it turns out that case 8, 1, still is. Except for they are in the top four GA-gibrams such that they're at FFF, F, F, F8, blah, blah, blah, blah, blah. So, I mean, they're basically... The kernel space that was added was added below case 8, 0. As I said, X, X, direct map, all of this is on memory. But the way NIFS does it, to have what are called CCAs, or cache-coherent attributes, they say whether you're memory-coherent, uncache, local cache, and you have a big A to the next case, this design such that it splits into eight segments, one for each GA. So every piece of memory is mapped, you'll put the next 50 to any GA you want. But that actually limits the full amount of physical memory. Unless the system's only at 40 or 8 bits or 44 bits, it's called Addisby. This is the amount that a lot of stuff plays in an engine. Now, mid-sway, in terms of looking at this, is the bit-on-list, and that is called the O32-A we got. And it's pretty much what's used even today on the U. But when the R4000 came out with 64-bit architecture, extended O62 and extended it to tags, blah, blah, blah, and then came up with O64, which is pretty much identical to O32-Sep worth 64-bit flight. Now, over time, maybe we learned both of these two in O62, because you really cannot pass enough arguments and registers. And since memory access, it turns out that really can lead to different increases in speed. So they came out with the N64 ADR, which changes the way, but it'll likely pass 8 arguments rather than 4. It also brings up the fact that you can't pass. Later on, they realized that, hmm, this works pretty well. People still need to get the ABI's, because a lot of the, because it's kind of wasteful for the most part. So they come up with the O32-A, and this is the part except for, flighters are now back to their seats. Longs of 32-bit, but everything else is still there. Longs is still 64, and it's still 32, so they still have to change things via 3 to the BFI. Now, I got engaged while I was kind of doing that 64-bit role. I just never got around to it until somebody paid me to do it. That's just the grace of life. And basically, they wanted N64 on the Armon, and that was brought on by bigger fish. The XLR, XLR, these are very big F-stips. They're a multi-core, they're super-scaler, they dress up, they have a lot of I-O, they have a lot of F-stips. The ones that I've been using have a core, and the first core threads are core, up to 32 threads per chip. And there's the actual feet, you can actually tie multiple chips together, so you can actually get up to 120 threads, and they're a planar score, things have been significantly gone, much larger than 320. So that is a very big thing in our 300-inch and a mixed 32-inch, and that required a lot of changes. They use 40 bits, this one is up to 1 terabyte of RAM, but they don't. And unlike the other 4,000, the previous two used, they actually supported a full 30-inch when you mount the stick. Also, the other earlier, you can only mount 1 terabyte, you've seen terabyte, but they're good. So, they've brought the SLP and can actually do full 60 bits. That's actually what you want to do, maybe, really. They also have multiple, no, DIX on the SLR or multiple PCIe on the SLP, they also have, you know, accelerant, hearing, spell, publicity, compression, networking, and other your-to-use, and regular expression mapping. Well, when I started this, there was a 4,000-inch piece of it. But again, all of these 32-inch, which pretty much meant that 64-bitness was never going to be used, in general, the 3-inch of it all. They only used 9-inch B-address, V-address, which also was a little bit over 500-inch, whole-big-map. These users have, slip-ed, you can take a 2-bit fan, 2-bit divider, it's actually much less than a 512 limit. Now, most of the 3-bit and IO is 512, but that was for things that just did not fit in the case I wanted. Of course, it was unicost strong. It kind of worked for the SLP. So obviously, what I can do is, if it uses 64-bit-address basically, be able to use lots of memory, not a whole or one key, it can actually scheme, gate, or more. Add multi-crosses, and as part of the multi-crosses, I added a 4-perf. 3-inch in fact, it's almost done for 3-inch. So, I have a top-to-ground, I'm going to put it in here. Unlike Spark 64, I'm going to put in the power of DC66 for good. You never really like your 3-bit stuff, 4-bit stuff, or the 3-bit stuff. I pretty much just say, and so I avoided that, and there it is, though, it's all installed in, that's easy. It's all conditional compiled, and a lot of keys. I believe it's identical to between N32s and N032s. We use the standard math stuff, we're doing by SBI, we're doing loading a pointer, loading a long loading a rest. So, it just happens that they're right. Now, there are times where you have an afternoon, what each guy, the kernels compile, also they're happy I know what ABI is, that's the process. And for what kernels, where I had DPP macros, that really tell you what the guy is, so the obscure stuff that you see aren't normally used, which when I look at, I can, I just did that a bit earlier. Now, unlike any other secret reports, the mix of the transport uses a 32-metre ABI, all user programs are like, we use N32 because, basic, LS is not the, nor do 99% of the N032s, maybe once a while, if you're compiling a utility, you can do that in a nice step. Okay, so the most part, probably the, for great controlling. Now, the other significant change from our O32 port, is that the N2L SNHR, kind of, so Amy, so I would have to have had a lot of, like, what are the instructions that are used, for N32? I was working a lot more, working a lot more out, and I just planned it in the second change, so we would need to talk a little bit more. And that's probably, that's something we have, does Amy's Fairhouse flooding apply. Now, the other, if you have a 64-bit kernel, and you use a lens, you name that twice, and look at kernel, but you can see the instructions, it's down a little right, and that's kind of, I don't remember what's on the problem, I meant staff, but we are going to be more and more, so let's do that, and we just actually look at, we get the stuff to be as physical, but it's really not that significant. Then the other big advantage, is a lens, is that if you have a, a kernel that's an ultra-intensive, or if you have a kernel that's small, or if it's a portable lens, if you have, you know, for a usual end, you can use an entry to a, use a lens, so this gives you a, you know, to pick what kernel is more working for your environment. Now, the thing that is very, I just said, obviously we have a very, very big use on it, but, you know, there are people that expect you to work with you, but then you see it's a really cool thing, called the MatNet MediaTree32, so long as you run through the programs, and support it's kernel. And it looks pretty well, it's a cool kernel. It was very, it was a lot of syscall, and some syscalls that were made for, neatly emulated. So, one of the things that had to be done was, often the same thing, so you can see, there are people on which it was not possible for IH to do this first of all, so, I had had mount 2, I had to be able to do various mount structures that are used by various hosts, all different, all oral. Also, the writing software was really not 16, 64, to claim, and that had to be changed to actually become 64 bit cool. And those were the biggest items, getting a basically 64 bit cool kernel. Because not only is the writing for putting stuff, it's for the rock, the mandits also is, and you do a, get IH and let's see, but there's a whole bunch, how do they code it? Now, it's getting more and more, you still have all these 3-bit programs, either as far as HRC or IKHS, all the other pieces that we keep on having kernel on, some of those were 64 bit cool. Now, we turn the data structure, that will be the same whether you would be writing a 3-bit, but you know, and for 64 bit, you go like that. And that helps a lot. But there's still a lot of other grantees, that require splitting, that convert to one or the other, especially if it contains pointer segments. And as I said, I have two bodies, that also compatibility, but does that deal with the freezer programs, instead of working with how it's done? And this, that means that I can punch for the kernel, that even works for I386 or I386. Now, the other thing about doing 64 bit addresses is that, you know, it uses a standard two level top. This is getting updated, but that will only get you. That just stays when you're talking 64 bit or KK. Now, obviously you want something larger than this. You can do a couple of levels, and it says, but I said on a three level, there'll be our three level page table, which gives you a two level interbited address table, which seems to be sufficient for now. Now, if you go with an 8K page table, that actually comes with 15 terabyte address tables. And that's an easy fix, or an easy way to get a larger address table, without adding another level of page table tables. Now, given that most of our programs use three to bit address space, just because it optimized that you still only do a two level lookup, even though, you know, your system is compiled for 64 bit addresses. So there's really that part of additional answer page table, that was given for that top level page table. There's really no overhead that is open to the user, in creating two program and in creating two program modern and new program. They both go through that two level lookup in the second section. The other thing that's significant is that you have 64 bit of address space. That state disk can be used to access memory without meeting the user. This is really useful when you do hash flushes, you just back and forth and it requires all the work on the lookup. Also, all the idle drive, all idle drive. Adders is definitely no VMAX, they're just directly accessible. So, I mean, an example of that is that the PGI is 256 GB So, if you map that with 4MIG or 4K by page show on a lot of them and you would feed up most of your time, that's when you can actually use a PIS to avoid all those side positions. Now, one of the other functions of address space is you find out a lot of VMA devices are pretty much 4K. You have 325 VMA analog PCI devices like DHCR, USB. So, obviously when you're doing an IEL, you need to make sure that you're within that first 4K of the device. And it's not you have a bug. So, what you really want to do is partition your memory between those that are below the 4K, and you'll get more of that white edge in a way of the problem. And now, it comes to the Super-Pixel model. It's kind of like when you go in and out of the programming scene, regardless, they are going to have an address model. And you know why that is, is because you can take advantage of that space and it's a hash plus operation. So, you're asking the virtual headers to the region of your active, I mean, are registered. No, registered, which is 16. Which means, my character team, in the next stage, and I don't have to work with that. Do I have to go back to the stage? Do I not have to go back to the stage? And that's the Super-Pixel model of code. Now, the kernels show how loaded the X-Pace is. And the Super-Pixel model, the nice thing is why it's only instruction loaded into the other band is like you can't move the N64 kernel and you can't move the N64 kernel to the top format. And then, you know, if the boot loader doesn't understand that it's 64, you would have been screwed, but they don't have a loader on the kernel. They're personally happy with the N64 kernel and you can avoid problems with boot loader. We had that when using the boot loader that our mind supplies with their Eval board so it just didn't understand how it's 64. And we're going to modify the firmware we can just load 30-bit kernels on all we have. And it works. Now, the one-stimulation difference between the two kernels and the N64 kernel is the amount of space returned. And 30-bit on the space-side of the kernel is limited to one gate. The core kernel is better to stay set, which is limited to 64.x about it. In reality, we limit a lot less than that. Typically, two gates. That seems to be sufficient. The one problem that we have is we're not just dealing with lots of differences in usage. Different CLB needs different needs what register state is and so they have a whole bunch of so we have a whole bunch of parameters that cause what we can do. A jump that which has the clb repeat that's if you switch the gene that tells us very soon that it needs to be done. But a little more comic back that basically has you check your gene, you check your gene. You know, you should be using LLSC, which is a little much more for this lock-ejecting register-y, resurable comic sequence. If your box is not capable of doing NB, there's no reason to use LLSC for a lot of that. So unless you have a system that really is capable of being multi-processed, we can call this a resurable comic sequence. Is there a microsoft? And then we also have what we call low-core switching genes. Some of the helper genes for us, your IO genes, all the mix borders have the same capability of kind of with core-interrupt and so low-core switch allows us to track that out. And finally, each system has a different inner structure. A power hole or a Y that's meant to click blah blah blah. And we extract that from that sequence. Now the nice thing that is that our MIE has a very good inner structure in the channel of that MIE. All of our I's can be exposed to the rest of MIE. And then the rest of MIE plus very strapped that are problem with that is being abstracted and if you want to close multiple for whatever, you're meant to see a indirect call. There's a question. What's the question, Paul? I would just like to ask if is it just the legacy name? Oh it isn't. Those are basically top or priority levels which are like IPL none, I'm being blah blah blah and how does that actually impact your heart for priority? So I mean you can think of a SPL and IPL as a but there's still a refer to a SPL. No problem. That is us. So basically if calls have a call, we all know that and these are really serious problems. So avoid doing the indirect call. So what I've done I have I have all the routines basically you know call the seven that seven routine basically both get a correction and I place all those names as in there in between sub-startants for example. And when it comes up, you know basically you use this time like this jump back of course and all those are nice and different. So you know you would read the call and you would do that the seven things. So I have a call here it will go in literally read each instruction around the sub and you'll edit and figure out where you use this jump and then it will pass that original location to do a direct call to where this is up with itself. So the nine has a nice abstraction of indirect calls and this is real quick so when you think about assembly files it doesn't care you just do a branch over a gene and then that will be you know thinking termatically later on you actually have to have all this gear in your those and it will automatically take it. Now I think permanently all set of stuff some five to six thousand and some three thousand seconds and all that. There's one thing they would do in there. In fact this work is so well on that I think this is probably different from how it is well and it works just all day there. There's a ton of doing this for arm and occasion. That's what it's all about. Now I think you have to worry about it. The loading of an outmaking of a model and every one of the separate things you have to act though because that's called actually the indirect that would have been used by the sets. You need a little help in your models that's deal with it. And it's much easier to do than it is obviously on an architect that I think by the instructor. How? I don't even want to do this correctly. Now the answer is well, yes. Sure. What's the confirmation on your computer? Uh-huh. Nobody here thinks that for very long architecture to be fun. Except Andrew. But yes, different steps are fun than we do. And all we have to do is after the S&P changes we stop working with the sets and do them in the top. The P-map was not that hard to make. It was mostly changes from the walk-less algorithms by your computing. It was actually a lot of changes I mean, I wouldn't say. Again, the set before the low-box sort of conditional only used on machines capable of writing with the multiple-due. I mean, and so, I mean, those are just very standard of this visually as sort of a standard way of getting it to be done differently. Again, that is a pretty old 21% code. You have to have a code for new things to get your possible to get it's normally it's not that hard to get. It's not that hard to get it's the wall for many of the ones. When you have a machine called Cp1 and it says I need to reschedule the CPU and I have to be made into the U1. But surprisingly it's not very good between our computers. It's still the same thing. And I've got a so, and you can print and I did. I don't want you to only go to my license here. Now one of the other changes that I'm having to work with is the page size. And let's extend a little later. Can you talk about this? This is a beautiful little page. When next 3 came up, the deal page is a single image of the CPU. Now I have to say you have the V8 and it's included a low-core processor. So you have one V8 that's what's lower-dash for the processor. And it's actually a console but it's low-level. It doesn't even have much V8 in it. So I thought about that for a while. Well how hard would it be to make a button? It turned out that it was long, easy to make fun and I was able to get rid of a lot of complex interjections that that's not a good thing. But it'll be good. I only have to go one V. And I can exactly see what it has and where it was before I would have let it be used to begin with. The other advantage of the televised or the long-hitch is that it actually needs energy and when talking about your computer which is only used such as long it can have a big problem. It's not going to be easy to do depending on what things you're doing. And by going through a simple PPP that you think is under the third instruction let's say I missed Q of red TQ red means construction. I was able to actually cut out seven instructions. Now the construction is going to be a little bit difficult. Q to 3 is going to be a lot of time spent on the stack. That's where the instructions then start adding up quite a bit. Now as I said, you have to set the next one to have a minute and a two, you have a minute and a two, you have a minute and a eight, then you have a one to take them'll tell you two and a four and a five and six. You have the one left by just one. But there is time and it's sitting in the The RMI is the top note. It's meant to 64 bits. It hasn't on video security, so we had to have a certain form for that. 5040, or so, but it didn't do pretty much. Same as you, if you want to be able to use those to test down your configuration, and then first, you have some PTAQ that require the RMI to have it. And now, this is where you've gotten rid of the question. It's easy to do. We basically need to make this a protocol. We've done all this before. They require some wireless. You really can build it with standard NVC. So it was easy just to update it and just let it go. Now, part of the answers are those you've been asking about. OK. The last two entries you have for XLT, what is the difference? Well, you can use the NVC for this, before this, before this, for XLT, as long as you're not playing You are multi-possessed. If you have a brain or an inter-thinking, you really have a specific code. You have your form and your address, but for some reason, they didn't actually allow the traditional type of code to be used. So you need code to go out and watch the PLV play your game with it. And that's what you have to have, those variants for the RMI. So you don't have to be strong if you don't have to watch this. There's a currency, so you can use the wireless and the wireless. Does that explain it? Back to your minutes. Most mid-systems have 3D-C22, only 2D-C26-A, it's a bit diffract from the others, or any other small systems. Now those are old-school, like the XLRSL. Now anywhere up to 16 gigabranas are different from what we have in the storage services. But again, they only have the storage, they only have the dust and the cotton. I mean, they are what I call big inventors. Now most of the dimensions of the system are 4.5 or 4.5, and the system is 6XX per piece, which means that when you start to do 6XX or 3XX, you push your system to do it, and the way it is or the way it is realized, that was due to the development of the system. So they added a function execution, which is execution has a criterion. So it's basically a variation of another instruction. This is a different function. So 24x8, why are these the days that the HVs won't work correctly? And again, that's part of the exact set. All while you have that covariance. Of course the inventors know the storage set is the most important thing. Most of the systems that know the memory outside of the casing, they are on you pretty much don't have to worry about. How does the system fit? You have memory outside. Again, I'm not going to say that with those you can't do the same thing with the HVs. Now what are the problems? One you get to it in, and the other you get to work with, that's the problem. Problems are different than you want to use for a gigabit of time. Well, the only problem is that you don't have a lot of stress-mappery in the first five calls. And typically you might find out that you really don't have memory in case you have a few old chronologies that you did. How do you prevent that? That is just splitting everything in pieces. So what I did is I added a half or a clue to your test. You basically wire a frequency to atmosphere and treat it as direct-map memory. Thereby the sending contents are divided. So you can't use a certain memory or whatever you need. That's an option of how much more. It means that there are people that use direct-mappery that they expect to have a signal. It's just quite a little easier. The thing that it uses in ST6GIRL are the exact convectors which goes with a steam finっていう thing anyway. They're a good example to see how they have점run relaunched in the protocol and entered them into the protocol. So again, intitled and partirary on all the other sides, what theseVよ вusteArt, handles is to yangkang the preceding variable. These pages separately, this is not the case in terms of the data. But if we not have pages that have to be processed, the pages of course are not the ones that doesn't necessarily have to be done, and then you have the rest of the pages. Now, if you view events out, now we have virtual cache elements. This basically means that there are really deep, sorry, unset files. So on the diagram, there's always a lot of like cache. And if you look at smaller pages like cache on this, this is the demonstration. Now, typically what happens with a third device of a little like cache is that it's always a way because it's more than that. It's a page that's not a cache one, either on one side or the other. Which means you're not really seeing a cache one. Excuse me for that. Good. This is smaller. Okay. Now the problem is that that's the reason you don't properly send cache to us. And for instance, a third of a CPU is basically done. Oh yeah, we have the data cache stuff and railings. Our data cache is the data that's right there. And then our SLP has the data that's not real. That's what we do. It's just that we go to cache and make it. This comes with a whole bunch of problems and complications in a bad example. Now you can prevent this from being taken your page size and maybe it's greater than or equal to way size. Or you can get to see that it's the bottom part of the first method. Share in the same set. You can never have an alien phone. There will be no alien. You can take care of that as long as you manage your math things and how to use them. Very careful. And that's done by splitting your free list such that they manage their pages by color or what's known and what that unit is done for color of the page. Now the good thing is that you can see audience that is not for other people. Or to stop the coloring. It doesn't do a thing. So now you have to have free lists. It also has to manage these free lists as if it had one free list in target. Instead of after the page is connected, all those fun things that go with your free memory. Much like net-based. There's just one local free list. So if you want to sort of one color. I'm going to go grab some pieces of paper. There over time it's not going to be able to out-use that color. And you can just spend time scratching through your page views and you know the problem. That's the cool side. In addition to this, as I mentioned before, you're not going to grab pieces of paper that are directly at one. So you're not going to include other groups of pages to deal with. So there is a solution. This is one of the things that I had to do for the net. I had it in a time called unity page. So normally you select things by calling each page by a tree. And you have to call it a single digital question of pages. Each of them are all free targets. They're all free. And that's the free minimum. Now there are only free pages. And that's the pages. Now all trapped at any time. Now the nice thing about this is, why? Eventually the free paper is going to be free to the pages. So you'll get more concurrent personality from the pages. Here is the idiosync or the demo in which you can actually have pages on this page on these pages on that page and now on this page on this own page. It is easier than you can page the multiple. And it turns out that for an instance, you might have to call all 20 pages or more pages whenever a page is in front. One of the issues is, in some ways, on a Smeeta or a demo, well the HTTP A instance, of course, didn't have hundreds of calls. And that was bad and unexpected. I'm not afraid about that issue. One of the other issues is, we gather pages, we gather them by color. We kind of map them, because they would be less important to us. And part of the problem is to be with current Ios that are going there. So I have to actually map the pages that are going to be useful for page Ios until the page is back up. And part of this needs to be set up. I get a page called in this, but I have to go into the right page that has the color that F. And reverse it out of the right page that I need to map. I need to go on the right one, not the left one. That's seven colors. This is one reason why you can't map things. It's so useful in that you're going to have a lot of people who are going to look at it. That you just reverse the pages and kind of figure out it. Now the other issue is that there are other parts of the arm that you think are going to be helpful. We're cleaning out the pages that we have to have. Which needs a support. And the other one I have to submit is also a whole part. And so what are the other pieces of that? That's a lot of direct mapping. And we really don't have that bar or speed. One of the things that your current set always needs to be done is to map the pages. It's almost like that. Every time you do a bunch of stuff, it's going to be the new concept. That's a bit of a problem. And so what it helps is that I can direct the map that I need to map that whole set. Yeah, I can state this or it's a zero. That's really always doing that over. It will gain you about a hundred years that might come off all these things out. And so based on what I added to there, part of this is that the current set is going to be the most helpful part of it. And that will help eliminate a whole bunch of things that are going to be zero gain. And the decision is not only by next down to the start of the by-off and a-off. And it's not only looking for a change, it's also going to give a pretty noticeable improvement. The other thing that I had next down off to a, is a portion in another set. And I realized that why I read it first, then you have to change the computer's anything. And so I adapted that towards our people's support. And I actually have a mid-sport set out off to use it, that I just haven't had to think of as mid-sport. And that's coming to me. And again, this is again the idea that has more and more comments there. And the point I'm just going to take that we did was, all the parts, they'd be flugging point-as-out. You flugging point and we only switch some point contacts and somebody else won't fling. Now, I think that you would think that all these important things that they don't. And every part of the system is only in a, they're in our box. And so one of the things that we said, I'm going to be honest a long time, some of the other developers, is that maybe this would be the thing that you have to change in your house. You won't be able to use it. And I'll send you loads and we need another various projects. And we turned that into really what we call for CPU units. And it's useful for you to find it's also a part of your team for all your back-end units. And, you know, at same six of them, you can get them. It's also often used as a rinse-slotting point. And maybe you have three repeat-closed devices for an architect. And you have something to do with it. Maybe the same as the CPU unit, you're going to have to load the CPU unit. And when it's done, oh, that's going to be three repeat-closed. No, it's not the CPU unit. It basically has a release called, I think, the device. Next time you reload this, you're going to have to force no loading back-end units. Either via, you know, processor, test unit, error on initial layer. That's basically all the way to the end. And pretty much covers everything that I did, hopefully, in a few fast ways. And so I want to now state where I'm fortunately, but you can't. Oh. So, one, the one side, you can also, the device, the test unit, the device. Yeah. That's one device in the area, the rest in the area. It really doesn't, it's not the actual fee for today, but it's only devices that are meaning up to be on. For this question, I did not spot normalization of the data card. It's probably only a few days back, because it's not the unit. So those DMAs had to be bounced off. But the current is patient. So we are actually, I think, in a current such that, you know, the CPU, a lot of times, it's not the confirmed memory from the low-core treatment in the middle of the unit. And that helps a lot. Turns out, yeah, we can use some of our framework, or just a book by a friend that's from the HGV. Does that help? Yeah. Any other questions? No one. I think they're all scared. Oh, Chris, go ahead. Hello. What's the question to you, Dan? Is that also a good thing? Is it a good thing to do? Is that also a good thing? Like accessing the capacity of the processor to put the way it was, and then I can say that it's a good thing to do. You can do it that way. I've been around since the beginning of the CQs. And I'm friends with the HGV for the CSTs. The CST is not a good thing to do. How can you do that? The one that's budget-supported to ESP is that it's due to pulling out a load index and so I register to the table to register to be a normal double in the inside version of it. Any other questions? Anyone else? Thank you very much.
Didn't sit in there. There was no one by the MIPS slight differences. Now, the MIPS architecture, addresses outside of 512. Now, the 64-bit address seats. Longs of 32-bit, but everything else is used, for N32? I was working a lot more, working you use a lens, you name that twice, and look at of address space. That state disk can be used to problem. And now, it comes to the Super-Pixel going to have an address model. And you know why has a nice abstraction of indirect calls and this to make. It was mostly changes from the walk-less with is the page size. And let's extend a little a minute and a two, you have a minute and a the systems that know the memory outside of the with. So there is a solution. This is one of the page. It is easier than you can page the so what it helps is that I can direct the map And so based on what I added to there, part of this is that the current set is going to be the