Efabless Open ASICs
Kassem, Mohamed
This presentation by Mohammed Kaseem, the CTO of e-Fabless, will outline how e-Fabless is empowering Libre/Open VLSI Hardware development. There are two initiatives: ChipIgnite which provides significantly-reduced cost Shuttle runs, and the Google-sponsored Skywater 130nm Programme.
 Hello, everyone, and good day. My name is Mohammed Kalsim. I am the co-founder and CTO of E-Pedalus. And thank you very much for making the time to join the presentation. And I hope it would follow up with questions that are useful to everyone. So I'm going to give a little bit of an introduction about myself. And basically, I come from the chip world, from a long career in the wireless industry. My background is in analog circuit design. And I joined Texas Instruments when TI was starting the era of the chip development for smartphones in general. And then the smartphones later. And if you know a processor like OMAP, then you'll find that the analog on OMAP Partial F3 and OMAP4 and a bit of OMAP5 were my responsibility. So if you hate it or like it, you may blame it on me. And here are some of the devices that I was involved in indirectly at some point. I also am a thinker and I'm a hardware enthusiast and always design and look for what the chips do in smart devices or any devices. So that's my habit from since I was a kid. I open things down. Sometimes when I was a kid, I wasn't able to bring them back. But now that's my tear down the device. Device doesn't understand how they're constructed and what chips are in. And that's a passion of mine as well pretty much for a lot of the new devices that are out there. So I'm going to dive into the talk right away. And it's basically talking about the chip design and how we can approach the problem of the inaccessibility and the restrictions to innovations for this industry. So I have a friend of mine who just put together this little abstract view. And on the left side, it says, and it shows that as the process technology evolves from down in the feature size, the development cost of the process and the designs around it, they increase actually exponentially, the number of capable companies or people who have access to this technology and can design with it goes down. And that means the number of, generally, number of designs goes down. So it's a very simple view. Now, when the number of designs goes down, or designers rather go down, that means the number of or the freedom to actually thinker and have more ideas move into silicon becomes restricted, which in general restricts innovation. This is another view, it's a financial view. And this would probably be the last financial slide on this. It is actually. And it shows that over the years, that's the number of companies, companies, not individuals even, that have the access to advanced node technologies or process technologies. It's just going down over time. And that didn't change really over beyond 2018, since we're now in 2022. And the net by itself looks like the car companies. As it converges, you end up with a few car companies that have the market and the people who have ideas in the cars and engines. They just can't just come up with an idea anywhere and just say it works. So this is just the dynamics of the industry. Now, on the other side of the industry, the need, so there's so-called the long tail. I'm representing here with orange. And I intend it to drive this way, because I usually call it the very, very long tail. And what is that is that it's the customized applications for specific markets or specific use. And typically, people today, the hardware developers, they use what's available in the FPGA world or standard devices from the standard semiconductor, either processors or chips, which typically leads to different living with the form factor or extra capability on the chip. Or I need the five regulators or three regulators, but I'm getting six or just I need one extra. So there is what I call here. And also that's a term that I got from somebody. For my mind, it's a right-sized compute, right-sized compute, meaning that I can, for every problem that I am facing, I'd like to size the chip or the compute capability and the power, especially if it's a battery-powered device, to the application. Now, on the left-hand side, this is a traditional approach where smartphones, you have tens of millions, maybe tens of millions of units or hundreds of millions of units, which justifies the development cost around these applications. The problem with the yellow or the orange part is that they're lower volume. And generally speaking, it is hard to justify a cost of an ASIC for these orange areas. Now, and then the typical answer for that is the standard product. Then now we believe that the number of these applications are gonna be tens of thousands. So if you wanna achieve both the right-sized compute and the tens of thousands, you really need designer. Or you can't just have one standard product and you need designers around the world, which is the problem. So we wanna have a thousand X developers, roughly, to be able to deliver to that. Now, when people look at the LIMTail, they keep asking me, what's the killer app? I'm like, well, there's no killer app. I don't know what the killer app is. The only way to have this work is to have people try and communicate with the market or the end users and come back with iterations. So in order to do that, it was happening in the software world. It is happening in the software world in a way that is efficient so that you can compile something, make it an app and put it out and get feedback and improve. And you can see that in the software world. The only answer for the demand, to meet the demand for the customization of hardware and chips is a community-based approach, meaning that instead of saying, I need a company or 10 companies to deliver to the world, I will just say, we need the world to deliver to the world. We need to community around the world to learn and become capable of making the custom applications. And it's actually grows with the demand. And also it has a variety of expertise. You can tell from the open source community, for example, you can amere out of expertise that can actually deliver value. And then the last thing is the natural selection. This is beautiful is that people choose what they like to work on and what they're passionate about and probably what they're good at versus working in a restricted environment where you just have to do what you have to do. Now, I'm gonna jump to E-Fabulous. Just a quick overview of why E-Fabulous exists. I'm just gonna say it's for meeting that goal. So in order to get these 1000X account in designer, we need to simplify the process. Typically the process of making ships is very complicated. So we wanna simplify to make it easy and adaptable by a lot of people. And again, our user number 1000X don't quote me on it, but just a multiplier that it is actually hard to achieve with the current traditional approaches. So yeah, so we need the 1000X maybe more, maybe less, but we need a huge multiplier of the people who are able to design. Now, with either we're gonna have to educate people or change the concept or simplify the process, we need to have a combination because actually it's time to simplify the process because I don't need to know everything about the chip to be able to create a chip. That's what's actually achievable a little bit through the FPGA. So that's what we wanna do. The example that I'm gonna use here is that in the software, the app stores, the app stores, before the app stores, in order to develop a piece of software and market it and sell it or expose it to customers, it's a very hard process. When the app stores showed up, whether it's iOS or Android, what happened is that there's a development tool set that is very robust and has unreliable. And then there's a business process, structured flow of quality control or at least feedback and the connections to customers. So now if we can do that, then you can see, you remember in the software or the app stores, it just exploded into millions and millions of developers anywhere from kids all the way to any age that wants to do something on their own without have to worry to actually structure a company or so. And the process also has become simplified because of the tools that are available. Now in the chip world, if you think, some of the chips are actually this, you can be designed by one to four engineers. And there are chips that require 100 people, but my experience says you can get a lot done within 10 people if they know what they're doing. And that's hard to bring in one room if you're hiring, maybe, but if you're working with the community, you'll probably find these for 10 people to do something really great. Now, in order to do that, we need to democratize the access to the needed, what's needed to chip design. It's not as simple as a development kit. And then, again, business process and the connection to customers. So now this is how we're gonna go. Now, in order to get that, there are, it's a little bit, it's much more complex actually than just a development kit because it's not one owner. It doesn't come from one place like Apple, Google, other open markets places. So in order to produce a useful chip and that is usable by the users, and could be the end user of a smart lock, something that sits in an air purifier or air quality sensors or systems, you need to know the access to the market. You need to have knowledge that you may not have. IP or blocks that are currently gated by generally NDAs and on access costs, EDA tools, similarly, PDK and affordable manufacturing and a reduction of the cost of manufacturing. So there are partial solutions that exist and they're admirable work pieces, but it still doesn't provide that, you know, I want it once per all. So what we wanted to do is a complete holistic solution. And in order to do this, it's basically boiling the ocean. So the right thing is to do it one at a time by solving everyone with a different tactic. And generally speaking, I will leave this, the comments maybe for the questions, but that's how we did. So the key is that instead of having just a developing kit, then it becomes like a stack in a box basically that you can be available to everyone and designers can collaborate and define and develop and commercialize their products for application for long-tail applications. To start, we started with the EDA, that's one aspect of it. And one of the things is that we wanted basically to give the EDA's flow to anybody anywhere without cost or without the permission or the violation of any licenses. So we assembled a great variety of tools for analog and digital design from open source engines. And we worked to use them to develop real chips. We also, on the IP, this is kind of a recent view. So these are examples of the places you can find. I'm sure there are more, maybe I've missed, but I just quickly, I think given the programs that we're working on right now, you can go to EFAB to see what people are doing in actual silicon IP that is submitted into the Google projects, for example. And then there are other examples for accessing IP in a structured way, like LibreCores or QSoft. Generally, Google is good to find. I'm always surprised with what individuals or groups have been doing in improving what's available for design. Now, in order, as I said, in order to improve that this is actually work, we took it from ourselves to develop ASICs. And we started with a chip called Raven. This chip is a RISC-5 based on a PicoRV32 from ClearWolf. And the IP and or the blocks are analog are coming from XFAB boundary. And this chip is in 180 nanometer. And one thing we intended to do is to make that chip top-level open source. So if you go to GitHub at this location, you're gonna find the top-level very long is there including behavioral models for the analog so you can simulate the entire chip in a digital simulator actually with the analog presented in real numbers. We also developed another chip called Ravenna. This was based on a request from a customer and it has more resources and it's also open source and it's available for the tinkering and adding additional features. Both of them are available on our platform so you can access in black box mode the IP. These chips are, here we have four major chips that we started with. Now, on the left is that Raven and Ravenna RISC-5 microcontrollers and then the top right is actually an open source chip but the core is ARM based. So it is not when I say open source chip, I mean that the top-level connectivity or a net list. Now, it has a lot of components that are not open source but it is a representation or a step forward in that direction. And then in the bottom right, this is a chip called Hydra that is purely analog for characterization testing. All of these, it's important to say all of these have been completely designed and verified with 100% open source tools period. The Raven chip was actually demonstrated in different places, we partnered with other people to make it a part of the other integrations and then this is the Hydra chip just for those who wanna take a look at it later. It's an array of analog chip. One of the interesting things is that Raven has a top-level open source chip and the core being open source. The NAC, one of the NAC research labs looked at it as this is an ideal for trust through transparency. So they wanted to look at as, use it as a kind of an authenticator for our ACU processor for a little bit of a rooted trust. And they requested Raven, we send them the boards and they developed several applications as you can see here but they also specced with us the Ravena chip and we delivered it to them. Now, this is what general overview of eFabulous, but now as we published a Raven chip all over the world and we had the attention of different places, especially Google. And then Google's philosophy in this involvement was if you can have a continuous integration in software, why don't we have a continuous integration concept in the hardware or specific chip world, design something, build it and measure it or learn from it and then do it again and keep iterating. In order to do that, you really need to have a cost structure and availability and access to make it worse than what. So the Google program was, it started as Google would fund six manufacturing runs and that means and you'll see why it's 240 chips. And now when I say at least, it's because it's actually getting more now, there were four last year and there's another, at least another four this year, 22. And the first of which is in March 21st this year. The submitted designs, and by the way, just to get into this, you don't need to go through big hassle, you can start designing, go to eFabulous.com, just show the intent that you have a project and just write the abstract of the project and then some, if you finish before the deadline, meaning that you pass all the pre-checkers, then, which are available, automated and open source to you, then you're in. So it's a first come, first serve and Google's purpose from that is to just mobilize the wheel in terms of having people to learn and design and learn and re-iterate. So if your design is perfect and you're not taking too much risk or taking risk, so it is okay to get in and learn something. So if you don't be intimidated by that chip concept because it is, with proven that, you know, from a variety of ages and a variety of software and hardware experiences, things worked out. Here are some of the links, you can go and start. And we've proven, as I said, many of the users and designers have been not, almost half from the Google program, haven't designed the chip before and they have chips and they actually demonstrated a success. For more information, go get it and see. One of the programs, I'll go to the eFabric.com and see. The interesting things about the Google program is that the tools are open source and then you get a chip that is as a reference or a platform that you can modify and add to it your design. And then you get development boards, not just the parts and abundance of parts, obviously, if you wanna build your own boards. The key component of that program is a partnership with Google, SkyWater and Feblis. They started with the open sourcing, the PDK, which is a representation of the process technology. It's the models, it's the libraries, the IOs, different views and documentation. So it is available without an NDA, which has never happened in the history of this industry as Foundry would actually open source the PDK of a reliable process as is. Just to give a background, if you're familiar with the PSock devices from Cypress Semiconductors, SkyWater, it was a spin off, is a spin off from Cypress back in 2017, I think. And the process that is being used, the 130 nanometer, is the process that's being used for PSock devices. So it is truly professionally done for industrial grade manufacturing. Now, by people say, what is a 130 nanometer? I work personally on 130 nanometer, 17, actually, almost 20 years ago. That was my part of the development of the analog back then. Well, until today, you can do a lot. If you're gonna see, go see what people did today since the last three years on this link. However, just an example I wanna bring up is, if you look at the Intel chips themselves, back in this, the age of 2001, which is roughly about 20 years ago, you'll see that even 180 nanometer, you're able to get the speed of about 1.7 gigahertz. Of course, Intel has a lot of this customization and so to get there, but I'm saying that transistor pitch doesn't mean you won't get performance. And also some of the data that are borrowed from our friends in URO Practice, they have a very good annual report. It shows here that in the microcosm of use in semiconductors from a URO Practice standpoint, there's about 50% of the process technology or data project on the process or their customers, they're below something that's bigger than 90 nanometer, which is 1.10, 1.30, I don't know, I can see it. Now, part of the project for Google is that we develop almost a new compiler, right, for digital functions. So that means if you know very long, then you develop something in better log. And recently we made that in Python using something like Litux. You compile your code and you get a functioning design, maybe not the best performance, maybe not the best area, but it works so you can iterate. And the intent here was to make it available. The Google partner with me is Dimansal, always says, I'm a software guy, I don't know what a DRC is, I don't know how to fix it, I just want a complete design that works and manufacturable and I can learn from it. So if you do that and you make it look like a compiler, I use the new compilers all over the place, but I don't know how they work exactly. And I get software that I actually use. So if you apply this concept on the digital design, well, that means software developers should be able to do that without a blame. And that opens, starts opening this thousand X more, at least people that are capable of making a digital design. Now it's also in the analog design, same. If you learn the basics or you wanna go further, also that actually with the great help from the community, it's become possible. Now, both of them, this is actually again the community. So we're working closely, this is a collaboration between the Open Road team and the flow it's called Open Lane, that the E-Cab is developed. And it is on several process technologies available now. Analog is the same and it's collaboration with the, for example, in this here, the ZEIS team, Injustice team, and the X-Skeem developer, Stiff and Shippers. Now, part of the project also to simplify, so all of these things that I'm going to notice, I'm going to simplify layer by layer. We use the concept of Caravell because that's the, when you look at it or look it up, it's a ship that has specific properties that the Portuguese used back in the 15th, 16th century. Well, Caravell is a ship that is almost like a ship that has cargo space or project space that you can put your own design in it. It has resources, it's an open source ship, and it's using components from like OpenRAM and the BigRV32, which are open source generators and IP. And this ship, you also open source a new, because of the processes open, you'll see it all over the, it's open on GitHub. And here's the sum of the features of the on-chip features that you can utilize for your design. The way it's being used is this, the designer designs the block and then it gets dropped into the chip and that produces a user-specific Caravell. The designer only focuses on the left side of the slide. They don't have to worry about the Caravell itself except from the models and the behavioral verification to make sure that things work. And we plug it in into the Caravell master. Now the designer also gets actually 300 packaged parts, plus five boards, and I mentioned that early. So it is straight up, you can push it into the, is USB connector and get working. And the board is like here. So this is one example of the Caravell boards with a specific design on it. Now we, there are multiple directions, multiple tracks that we're improving on right now, again with a collaboration with the community. There's also one piece of news here is that because of what Skywater Foundry did, it got the attention of other boundaries. And then there will be, there's a plan for a second foundry and you may hear about announcement of that too. Just the engagement here that we can see when the Skywater PDK was opened, it gave us like, basically it's like a barrier of behavior against projects that are accessible for years. And also it gets downloaded about 700 times a week. We also have the Slack community that is rich with almost 2,500 people. You can join and get your self-invite from there. Now the first shuttle went with Google, was an interesting one, we called it in PW1. You can see the designs up there too. But it had a variety of contributors from individuals to companies. It was a quick book. Again, it's free for the designer funded by Google for the time being. And then, part of PW1 was actually to actually get this picture done. It's the first time the open source hardware, at least to my knowledge, they get engraved on actual chip that is totally open source all the way to GDS. There's no compromise here. And just to mention the community contribution, the John McMaster here, who's pictured in the bottom left, has actually took that chip, decapped it, and he has an electron scanning microscope at home to actually do that. So that's kind of a community interest. And then in PW2, again, I'm not gonna go over the whole design, but you can see the links. If you go to the link below, you'll see the full overview. And as well as the GitHub repositories. This is just a candy for the eye to see the two different, the 80 chips plus the test chips for the foundry up there. Now, the Google, when we found that it's very important that people say, I wanna open source my design and I wanna guarantee my spot and I wanna control my schedule. So we created an offering called Chippick Night. Chippick Night is basically the same thing for Google. Just shift it into eFabulous completely and to you actually, to the designer. He says, okay, I'm gonna get my own design. I don't have to open source it or not, that's up to me. And then I will book my space for 200 bucks starting designing, to start designing. And then you will get actually 10 millimeter squares inside the chip, which is I mentioned earlier, but it is actually, it's still the real state. I always say it's a framed house with plumbing and electricity and then you bring your own appliance. And these are some of the pricing here, but the pricing is actually intended to not to show the dollar numbers. That's it show that comparison. You can either get 100 parts with the QFN 300 with the WSP, which has never happened. Or if you're doing a low volume production, you can pay 20,000 and you get a thousand units, which is almost basically $20 per chip in all includes. These are options of Chip Ignite. Some of them are the same as the Chip Ignite as the area as it is. And then we got requests to say, if I don't wanna use the management area or the logic here, I wanna the area all myself. So we started offering that as well. Here's the schedule for Chip Ignite and MPW for Google. So these are two Chip Ignite data points. One of them is April 8th, the Google shuttle that's upcoming is March 21st. And the next Chip Ignite or second Chip Ignite in 2022 will be in June. Go, you know, can go to eFeders to come to see the details. The users of Chip Ignite, not the Google program, basically started with the universities. Here at Stanford University used it for a course. There was basically the whole course is designed and end up with a go to fabrication and then you come back and test it. Also the IEEE, they created a competition. So they actually got 10 Chip Ignites and then it was a great competition. You can view it and see how the, we had like 56 proposals in it, great designs. Startups also said, okay, I can use Chip Ignite as it is. Basically I can put my own designer like the blue in the middle here design. And then I have a product basically for low volume. I don't have to optimize the area because it makes sense economically and I, but I can get the market very quickly to my customer. This is back to the IEEE. It also shows that these were 10 projects from all over the world. The last six projects, you can see how people utilize one slot to multiple designs instead just having one slot for one project. This is the part where I showed the university. There's multiple aspects of the universities have started talking to us to actually adopt that either in the courses or in parallel sessions like the capstone projects and graduate research. And that's it. So I close here and then when you get the slides, you'll find I'm gonna flash through this very quickly. Fun from the community that I borrowed and just shared different people have posted different pictures and you'll be able to flash through them. And these are all contributors from different places. And they know their names, but you can find them also on Twitter. And it shows how passionate and competent the community and to actually get something done. This is a RAM test chip that Andrew Zonenberg created a board for testing it. This is a met then obviously people know met then they used one slot to create a course that has 16 slots. This is the parallel. This is us. Actually, this is me on my desk. And then other people like TNT or Sylvain Mone. This show you see the quality of the sharing, how people share things and incredible. Never happened before. And get the chance just to take a look at this. And that's my last slide. Thank you. And then open for questions. Ryan. So I look actually or okay now I can hear. Thank you Mohammed for a great talk and if you want to read any questions from the chat you'll be welcome. For instance let's see how much will that normally cost if not using cheap ignite say another shuttle. Well the most important thing I would like to say here is that the word shuttle is kind of a, the word shuttle is actually kind of tricky. As I mentioned a shuttle typically is it gives you an area on silicon so if you want to compare it would be wouldn't compare that's the area because you're getting an area with as I mentioned with the older resources around it to make work like logic analyzer an actual chip around your design. So definitely if you compare it so this would be that 10 millimeters for 10,000 and if you compare at this level even if the cost is the same but you wouldn't get the same resources around it and packaged devices and boards. Okay we have a question about when this lack will be bridged to IRC maybe. It is actually kind of to bridge 100% so if you go to the IRC servers you're going to find the space sky water dash PDK and I should actually I should have maybe I'll send the link later. And what else is Idra a reference design? It is a reference design the design but in the it's open as well but the the blocks in it are not however you can replace them now with a lot of the NPWs coming from blocks are coming from Google N chip Ignite open source. All right I think I'll ask a question myself. Go ahead. Okay what kind of interfaces the the kit has it is high speed can you put a USB maybe. Right now on the the board has USB you can connect it to the the the computer and then it comes with an open source just flashing software and and then you can go from there. Now the chip doesn't have USB yet at least it is right now it's either a UART or a spy interface out there and on top of the GP the general purpose IOS. The general purpose IOS maybe they are high speed what speed could they reach? For this process as they are they they're not high speed they're actually 60 megahertz maximum as they specified by the original design that's Cypress. However we have a flavor where you can designers on on the shuttles actually created their own like LBDS designs so you there will be a variety of highest higher speed IOS that are coming from the community shown you'll see it because people everybody is actually it feels limited by the 60 megahertz. Great so I think we'll wrap up and then anybody which wants to continue the link will be available soon to these two to the room where you could you can continue the chat thank you. Great thank you so much have a good day everyone.
 Hello, everyone, and good day.  My name is Mohammed Kalsim.  I am the co-founder and CTO of E-Pedalus.  And thank you very much for making the time  to join the presentation.  And I hope it would follow up with questions  that are useful to everyone.  So I'm going to give a little bit of an introduction  about myself.  And basically, I come from the chip world,  from a long career in the wireless industry.  My background is in analog circuit design.  And I joined Texas Instruments when  TI was starting the era of the chip development for smartphones  in general.  And then the smartphones later.  And if you know a processor like OMAP,  then you'll find that the analog on OMAP Partial F3 and OMAP4  and a bit of OMAP5 were my responsibility.  So if you hate it or like it, you may blame it on me.  And here are some of the devices that I was involved in  indirectly at some point.  I also am a thinker and I'm a hardware enthusiast  and always design and look for what the chips do  in smart devices or any devices.  So that's my habit from since I was a kid.  I open things down.  Sometimes when I was a kid, I wasn't  able to bring them back.  But now that's my tear down the device.  Device doesn't understand how they're constructed  and what chips are in.  And that's a passion of mine as well pretty much  for a lot of the new devices that are out there.  So I'm going to dive into the talk right away.  And it's basically talking about the chip design  and how we can approach the problem of the inaccessibility  and the restrictions to innovations for this industry.  So I have a friend of mine who just put together  this little abstract view.  And on the left side, it says, and it  shows that as the process technology evolves from down  in the feature size, the development cost of the process  and the designs around it, they increase actually  exponentially, the number of capable companies  or people who have access to this technology  and can design with it goes down.  And that means the number of, generally, number of designs  goes down.  So it's a very simple view.  Now, when the number of designs goes down,  or designers rather go down, that means  the number of or the freedom to actually thinker and have  more ideas move into silicon becomes restricted,  which in general restricts innovation.  This is another view, it's a financial view.  And this would probably be the last financial slide on this.  It is actually.  And it shows that over the years, that's  the number of companies, companies, not individuals  even, that have the access to advanced node technologies  or process technologies.  It's just going down over time.  And that didn't change really over beyond 2018,  since we're now in 2022.  And the net by itself looks like the car companies.  As it converges, you end up with a few car companies that  have the market and the people who  have ideas in the cars and engines.  They just can't just come up with an idea anywhere  and just say it works.  So this is just the dynamics of the industry.  Now, on the other side of the industry, the need,  so there's so-called the long tail.  I'm representing here with orange.  And I intend it to drive this way,  because I usually call it the very, very long tail.  And what is that is that it's the customized applications  for specific markets or specific use.  And typically, people today, the hardware developers,  they use what's available in the FPGA world  or standard devices from the standard semiconductor,  either processors or chips, which typically leads  to different living with the form factor  or extra capability on the chip.  Or I need the five regulators or three regulators,  but I'm getting six or just I need one extra.  So there is what I call here.  And also that's a term that I got from somebody.  For my mind, it's a right-sized compute, right-sized compute,  meaning that I can, for every problem that I am facing,  I'd like to size the chip or the compute capability  and the power, especially if it's a battery-powered device,  to the application.  Now, on the left-hand side,  this is a traditional approach where smartphones,  you have tens of millions, maybe tens of millions of units  or hundreds of millions of units,  which justifies the development cost  around these applications.  The problem with the yellow or the orange part  is that they're lower volume.  And generally speaking, it is hard to justify a cost  of an ASIC for these orange areas.  Now, and then the typical answer for that  is the standard product.  Then now we believe that the number of these applications  are gonna be tens of thousands.  So if you wanna achieve both the right-sized compute  and the tens of thousands, you really need designer.  Or you can't just have one standard product  and you need designers around the world,  which is the problem.  So we wanna have a thousand X developers,  roughly, to be able to deliver to that.  Now, when people look at the LIMTail,  they keep asking me, what's the killer app?  I'm like, well, there's no killer app.  I don't know what the killer app is.  The only way to have this work  is to have people try and communicate with the market  or the end users and come back with iterations.  So in order to do that, it was happening in the software world.  It is happening in the software world  in a way that is efficient so that you can compile something,  make it an app and put it out and get feedback and improve.  And you can see that in the software world.  The only answer for the demand,  to meet the demand for the customization of hardware  and chips is a community-based approach,  meaning that instead of saying,  I need a company or 10 companies  to deliver to the world,  I will just say, we need the world to deliver to the world.  We need to community around the world to learn  and become capable of making the custom applications.  And it's actually grows with the demand.  And also it has a variety of expertise.  You can tell from the open source community, for example,  you can amere out of expertise  that can actually deliver value.  And then the last thing is the natural selection.  This is beautiful is that people choose  what they like to work on and what they're passionate about  and probably what they're good at  versus working in a restricted environment  where you just have to do what you have to do.  Now, I'm gonna jump to E-Fabulous.  Just a quick overview of why E-Fabulous exists.  I'm just gonna say it's for meeting that goal.  So in order to get these 1000X account in designer,  we need to simplify the process.  Typically the process of making ships is very complicated.  So we wanna simplify to make it easy  and adaptable by a lot of people.  And again, our user number 1000X don't quote me on it,  but just a multiplier that it is actually hard to achieve  with the current traditional approaches.  So yeah, so we need the 1000X maybe more, maybe less,  but we need a huge multiplier of the people  who are able to design.  Now, with either we're gonna have to educate people  or change the concept or simplify the process,  we need to have a combination because actually  it's time to simplify the process  because I don't need to know everything about the chip  to be able to create a chip.  That's what's actually achievable a little bit  through the FPGA.  So that's what we wanna do.  The example that I'm gonna use here is that  in the software, the app stores,  the app stores, before the app stores,  in order to develop a piece of software and market it  and sell it or expose it to customers,  it's a very hard process.  When the app stores showed up, whether it's iOS or Android,  what happened is that there's a development tool set  that is very robust and has unreliable.  And then there's a business process,  structured flow of quality control  or at least feedback and the connections to customers.  So now if we can do that, then you can see,  you remember in the software or the app stores,  it just exploded into millions and millions of developers  anywhere from kids all the way to any age  that wants to do something on their own  without have to worry to actually structure a company or so.  And the process also has become simplified  because of the tools that are available.  Now in the chip world, if you think,  some of the chips are actually this,  you can be designed by one to four engineers.  And there are chips that require 100 people,  but my experience says you can get a lot done  within 10 people if they know what they're doing.  And that's hard to bring in one room if you're hiring,  maybe, but if you're working with the community,  you'll probably find these for 10 people  to do something really great.  Now, in order to do that,  we need to democratize the access to the needed,  what's needed to chip design.  It's not as simple as a development kit.  And then, again, business process  and the connection to customers.  So now this is how we're gonna go.  Now, in order to get that, there are,  it's a little bit, it's much more complex actually  than just a development kit because it's not one owner.  It doesn't come from one place like Apple, Google,  other open markets places.  So in order to produce a useful chip  and that is usable by the users,  and could be the end user of a smart lock,  something that sits in an air purifier  or air quality sensors or systems,  you need to know the access to the market.  You need to have knowledge that you may not have.  IP or blocks that are currently gated by generally NDAs  and on access costs, EDA tools, similarly,  PDK and affordable manufacturing  and a reduction of the cost of manufacturing.  So there are partial solutions that exist  and they're admirable work pieces,  but it still doesn't provide that, you know,  I want it once per all.  So what we wanted to do is a complete holistic solution.  And in order to do this, it's basically boiling the ocean.  So the right thing is to do it one at a time  by solving everyone with a different tactic.  And generally speaking, I will leave this,  the comments maybe for the questions,  but that's how we did.  So the key is that instead of having  just a developing kit, then it becomes like a stack  in a box basically that you can be available to everyone  and designers can collaborate and define and develop  and commercialize their products for application  for long-tail applications.  To start, we started with the EDA, that's one aspect of it.  And one of the things is that we wanted basically  to give the EDA's flow to anybody anywhere  without cost or without the permission  or the violation of any licenses.  So we assembled a great variety of tools  for analog and digital design from open source engines.  And we worked to use them to develop real chips.  We also, on the IP, this is kind of a recent view.  So these are examples of the places you can find.  I'm sure there are more, maybe I've missed,  but I just quickly, I think given the programs  that we're working on right now, you can go to EFAB  to see what people are doing in actual silicon IP  that is submitted into the Google projects, for example.  And then there are other examples for accessing IP  in a structured way, like LibreCores or QSoft.  Generally, Google is good to find.  I'm always surprised with what individuals  or groups have been doing in improving  what's available for design.  Now, in order, as I said, in order to improve  that this is actually work, we took it  from ourselves to develop ASICs.  And we started with a chip called Raven.  This chip is a RISC-5 based on a PicoRV32  from ClearWolf.  And the IP and or the blocks are analog  are coming from XFAB boundary.  And this chip is in 180 nanometer.  And one thing we intended to do  is to make that chip top-level open source.  So if you go to GitHub at this location,  you're gonna find the top-level very long  is there including behavioral models for the analog  so you can simulate the entire chip  in a digital simulator actually  with the analog presented in real numbers.  We also developed another chip called Ravenna.  This was based on a request from a customer  and it has more resources and it's also open source  and it's available for the tinkering  and adding additional features.  Both of them are available on our platform  so you can access in black box mode the IP.  These chips are, here we have four major chips  that we started with.  Now, on the left is that Raven and Ravenna RISC-5  microcontrollers and then the top right  is actually an open source chip  but the core is ARM based.  So it is not when I say open source chip,  I mean that the top-level connectivity or a net list.  Now, it has a lot of components that are not open source  but it is a representation or a step forward  in that direction.  And then in the bottom right,  this is a chip called Hydra that is purely analog  for characterization testing.  All of these, it's important to say all of these  have been completely designed and verified  with 100% open source tools period.  The Raven chip was actually demonstrated  in different places, we partnered with other people  to make it a part of the other integrations  and then this is the Hydra chip just for those  who wanna take a look at it later.  It's an array of analog chip.  One of the interesting things is that Raven  has a top-level open source chip  and the core being open source.  The NAC, one of the NAC research labs looked at it  as this is an ideal for trust through transparency.  So they wanted to look at as, use it as a kind of  an authenticator for our ACU processor  for a little bit of a rooted trust.  And they requested Raven, we send them the boards  and they developed several applications as you can see here  but they also specced with us the Ravena chip  and we delivered it to them.  Now, this is what general overview of eFabulous,  but now as we published a Raven chip all over the world  and we had the attention of different places,  especially Google.  And then Google's philosophy in this involvement was  if you can have a continuous integration in software,  why don't we have a continuous integration concept  in the hardware or specific chip world, design something,  build it and measure it or learn from it  and then do it again and keep iterating.  In order to do that, you really need to have  a cost structure and availability and access  to make it worse than what.  So the Google program was, it started as  Google would fund six manufacturing runs  and that means and you'll see why it's 240 chips.  And now when I say at least, it's because it's actually  getting more now, there were four last year  and there's another, at least another four this year, 22.  And the first of which is in March 21st this year.  The submitted designs, and by the way,  just to get into this, you don't need to go through  big hassle, you can start designing,  go to eFabulous.com, just show the intent  that you have a project and just write the abstract  of the project and then some, if you finish  before the deadline, meaning that you pass  all the pre-checkers, then, which are available,  automated and open source to you, then you're in.  So it's a first come, first serve and Google's purpose  from that is to just mobilize the wheel  in terms of having people to learn and design  and learn and re-iterate.  So if your design is perfect and you're not taking  too much risk or taking risk, so it is okay  to get in and learn something.  So if you don't be intimidated by that chip concept  because it is, with proven that, you know,  from a variety of ages and a variety of software  and hardware experiences, things worked out.  Here are some of the links, you can go and start.  And we've proven, as I said, many of the users  and designers have been not, almost half  from the Google program, haven't designed the chip before  and they have chips and they actually demonstrated  a success.  For more information, go get it and see.  One of the programs, I'll go to the eFabric.com and see.  The interesting things about the Google program  is that the tools are open source and then you get a chip  that is as a reference or a platform that you can modify  and add to it your design.  And then you get development boards, not just the parts  and abundance of parts, obviously,  if you wanna build your own boards.  The key component of that program is a partnership  with Google, SkyWater and Feblis.  They started with the open sourcing, the PDK,  which is a representation of the process technology.  It's the models, it's the libraries, the IOs,  different views and documentation.  So it is available without an NDA,  which has never happened in the history of this industry  as Foundry would actually open source the PDK  of a reliable process as is.  Just to give a background, if you're familiar with the  PSock devices from Cypress Semiconductors, SkyWater,  it was a spin off, is a spin off from Cypress  back in 2017, I think.  And the process that is being used, the 130 nanometer,  is the process that's being used for PSock devices.  So it is truly professionally done  for industrial grade manufacturing.  Now, by people say, what is a 130 nanometer?  I work personally on 130 nanometer, 17, actually,  almost 20 years ago.  That was my part of the development of the analog back then.  Well, until today, you can do a lot.  If you're gonna see, go see what people did today  since the last three years on this link.  However, just an example I wanna bring up is,  if you look at the Intel chips themselves,  back in this, the age of 2001,  which is roughly about 20 years ago,  you'll see that even 180 nanometer,  you're able to get the speed of about 1.7 gigahertz.  Of course, Intel has a lot of this customization  and so to get there, but I'm saying  that transistor pitch doesn't mean  you won't get performance.  And also some of the data that are borrowed  from our friends in URO Practice,  they have a very good annual report.  It shows here that in the microcosm of use  in semiconductors from a URO Practice standpoint,  there's about 50% of the process technology  or data project on the process or their customers,  they're below something that's bigger than 90 nanometer,  which is 1.10, 1.30, I don't know, I can see it.  Now, part of the project for Google  is that we develop almost a new compiler,  right, for digital functions.  So that means if you know very long,  then you develop something in better log.  And recently we made that in Python  using something like Litux.  You compile your code and you get a functioning design,  maybe not the best performance,  maybe not the best area, but it works so you can iterate.  And the intent here was to make it available.  The Google partner with me is Dimansal,  always says, I'm a software guy,  I don't know what a DRC is, I don't know how to fix it,  I just want a complete design that works  and manufacturable and I can learn from it.  So if you do that and you make it look like a compiler,  I use the new compilers all over the place,  but I don't know how they work exactly.  And I get software that I actually use.  So if you apply this concept on the digital design,  well, that means software developers  should be able to do that without a blame.  And that opens, starts opening this thousand X more,  at least people that are capable of making a digital design.  Now it's also in the analog design, same.  If you learn the basics or you wanna go further,  also that actually with the great help from the community,  it's become possible.  Now, both of them, this is actually again the community.  So we're working closely,  this is a collaboration between the Open Road team  and the flow it's called Open Lane,  that the E-Cab is developed.  And it is on several process technologies available now.  Analog is the same and it's collaboration  with the, for example, in this here,  the ZEIS team, Injustice team,  and the X-Skeem developer, Stiff and Shippers.  Now, part of the project also to simplify,  so all of these things that I'm going to notice,  I'm going to simplify layer by layer.  We use the concept of Caravell because that's the,  when you look at it or look it up,  it's a ship that has specific properties  that the Portuguese used back in the 15th, 16th century.  Well, Caravell is a ship that is almost like a ship  that has cargo space or project space  that you can put your own design in it.  It has resources, it's an open source ship,  and it's using components from like OpenRAM  and the BigRV32, which are open source generators and IP.  And this ship, you also open source a new,  because of the processes open,  you'll see it all over the, it's open on GitHub.  And here's the sum of the features of the on-chip features  that you can utilize for your design.  The way it's being used is this,  the designer designs the block  and then it gets dropped into the chip  and that produces a user-specific Caravell.  The designer only focuses on the left side of the slide.  They don't have to worry about the Caravell itself  except from the models and the behavioral verification  to make sure that things work.  And we plug it in into the Caravell master.  Now the designer also gets actually 300 packaged parts,  plus five boards, and I mentioned that early.  So it is straight up, you can push it into the,  is USB connector and get working.  And the board is like here.  So this is one example of the Caravell boards  with a specific design on it.  Now we, there are multiple directions,  multiple tracks that we're improving on right now,  again with a collaboration with the community.  There's also one piece of news here is that  because of what Skywater Foundry did,  it got the attention of other boundaries.  And then there will be,  there's a plan for a second foundry  and you may hear about announcement of that too.  Just the engagement here that we can see  when the Skywater PDK was opened,  it gave us like,  basically it's like a barrier of behavior  against projects that are accessible for years.  And also it gets downloaded about 700 times a week.  We also have the Slack community that is rich  with almost 2,500 people.  You can join and get your self-invite from there.  Now the first shuttle went with Google,  was an interesting one, we called it in PW1.  You can see the designs up there too.  But it had a variety of contributors  from individuals to companies.  It was a quick book.  Again, it's free for the designer  funded by Google for the time being.  And then, part of PW1 was actually  to actually get this picture done.  It's the first time the open source hardware,  at least to my knowledge,  they get engraved on actual chip  that is totally open source all the way to GDS.  There's no compromise here.  And just to mention the community contribution,  the John McMaster here,  who's pictured in the bottom left,  has actually took that chip, decapped it,  and he has an electron scanning microscope at home  to actually do that.  So that's kind of a community interest.  And then in PW2,  again, I'm not gonna go over the whole design,  but you can see the links.  If you go to the link below,  you'll see the full overview.  And as well as the GitHub repositories.  This is just a candy for the eye to see  the two different, the 80 chips  plus the test chips for the foundry up there.  Now, the Google, when we found that it's very important  that people say, I wanna open source my design  and I wanna guarantee my spot  and I wanna control my schedule.  So we created an offering called Chippick Night.  Chippick Night is basically the same thing for Google.  Just shift it into eFabulous completely  and to you actually, to the designer.  He says, okay, I'm gonna get my own design.  I don't have to open source it or not, that's up to me.  And then I will book my space for 200 bucks  starting designing, to start designing.  And then you will get actually 10 millimeter squares  inside the chip, which is I mentioned earlier,  but it is actually, it's still the real state.  I always say it's a framed house with plumbing  and electricity and then you bring your own appliance.  And these are some of the pricing here,  but the pricing is actually intended  to not to show the dollar numbers.  That's it show that comparison.  You can either get 100 parts with the QFN 300  with the WSP, which has never happened.  Or if you're doing a low volume production,  you can pay 20,000 and you get a thousand units,  which is almost basically $20 per chip in all includes.  These are options of Chip Ignite.  Some of them are the same as the Chip Ignite  as the area as it is.  And then we got requests to say,  if I don't wanna use the management area or the logic here,  I wanna the area all myself.  So we started offering that as well.  Here's the schedule for Chip Ignite and MPW for Google.  So these are two Chip Ignite data points.  One of them is April 8th,  the Google shuttle that's upcoming is March 21st.  And the next Chip Ignite or second Chip Ignite in 2022  will be in June.  Go, you know, can go to eFeders to come to see the details.  The users of Chip Ignite, not the Google program,  basically started with the universities.  Here at Stanford University used it for a course.  There was basically the whole course is designed  and end up with a go to fabrication  and then you come back and test it.  Also the IEEE, they created a competition.  So they actually got 10 Chip Ignites  and then it was a great competition.  You can view it and see how the,  we had like 56 proposals in it, great designs.  Startups also said, okay, I can use Chip Ignite as it is.  Basically I can put my own designer  like the blue in the middle here design.  And then I have a product basically for low volume.  I don't have to optimize the area  because it makes sense economically  and I, but I can get the market very quickly  to my customer.  This is back to the IEEE.  It also shows that these were 10 projects  from all over the world.  The last six projects, you can see how people utilize  one slot to multiple designs  instead just having one slot for one project.  This is the part where I showed the university.  There's multiple aspects of the universities  have started talking to us to actually adopt that  either in the courses or in parallel sessions  like the capstone projects and graduate research.  And that's it.  So I close here and then when you get the slides,  you'll find I'm gonna flash through this very quickly.  Fun from the community that I borrowed  and just shared different people  have posted different pictures  and you'll be able to flash through them.  And these are all contributors from different places.  And they know their names,  but you can find them also on Twitter.  And it shows how passionate and competent the community  and to actually get something done.  This is a RAM test chip that Andrew Zonenberg  created a board for testing it.  This is a met then obviously people know met then  they used one slot to create a course that has 16 slots.  This is the parallel.  This is us.  Actually, this is me on my desk.  And then other people like TNT or Sylvain Mone.  This show you see the quality of the sharing,  how people share things and incredible.  Never happened before.  And get the chance just to take a look at this.  And that's my last slide.  Thank you.  And then open for questions.  Ryan.  So I look actually or okay now I can hear.  Thank you Mohammed for a great talk and if you want to read any questions from the chat  you'll be welcome.  For instance let's see how much will that normally cost if not using cheap ignite say  another shuttle.  Well the most important thing I would like to say here is that the word shuttle is kind  of a, the word shuttle is actually kind of tricky.  As I mentioned a shuttle typically is it gives you an area on silicon so if you want to compare  it would be wouldn't compare that's the area because you're getting an area with as I mentioned  with the older resources around it to make work like logic analyzer an actual chip around  your design.  So definitely if you compare it so this would be that 10 millimeters for 10,000 and if you  compare at this level even if the cost is the same but you wouldn't get the same resources  around it and packaged devices and boards.  Okay we have a question about when this lack will be bridged to IRC maybe.  It is actually kind of to bridge 100% so if you go to the IRC servers you're going to  find the space sky water dash PDK and I should actually I should have maybe I'll send the  link later.  And what else is Idra a reference design?  It is a reference design the design but in the it's open as well but the the blocks in  it are not however you can replace them now with a lot of the NPWs coming from blocks  are coming from Google N chip Ignite open source.  All right I think I'll ask a question myself.  Go ahead.  Okay what kind of interfaces the the kit has it is high speed can you put a USB maybe.  Right now on the the board has USB you can connect it to the the the computer and then  it comes with an open source just flashing software and and then you can go from there.  Now the chip doesn't have USB yet at least it is right now it's either a UART or a spy  interface out there and on top of the GP the general purpose IOS.  The general purpose IOS maybe they are high speed what speed could they reach?  For this process as they are they they're not high speed they're actually 60 megahertz  maximum as they specified by the original design that's Cypress.  However we have a flavor where you can designers on on the shuttles actually created their  own like LBDS designs so you there will be a variety of highest higher speed IOS that  are coming from the community shown you'll see it because people everybody is actually  it feels limited by the 60 megahertz.  Great so I think we'll wrap up and then anybody which wants to continue the link will be available  soon to these two to the room where you could you can continue the chat thank you.  Great thank you so much have a good day everyone.
efabless_0_167.png efabless_168_17387.png efabless_17388_19739.png efabless_19740_20123.png efabless_20124_20891.png efabless_20892_21755.png efabless_21756_21803.png efabless_21804_22019.png efabless_22020_22091.png efabless_22092_23867.png efabless_23868_25127.png efabless_25128_25523.png efabless_25524_26399.png efabless_26400_30731.png efabless_30732_32507.png efabless_32508_33503.png efabless_33504_39683.png efabless_39684_40343.png efabless_40344_41327.png efabless_41328_41579.png efabless_41580_42071.png efabless_42072_43295.png efabless_43296_44111.png efabless_44112_45407.png efabless_45408_48707.png efabless_48708_48887.png efabless_48888_48983.png efabless_48984_49463.png efabless_49464_50099.png efabless_50100_50171.png efabless_50172_50327.png efabless_50328_50375.png efabless_50376_50423.png efabless_50424_50483.png efabless_50484_50531.png efabless_50532_51155.png efabless_51156_51587.png efabless_51588_52427.png efabless_52428_52583.png efabless_52584_52823.png efabless_52824_52991.png efabless_52992_53579.png efabless_53580_54011.png efabless_54012_54431.png efabless_54432_54659.png efabless_54660_55151.png efabless_55152_55559.png efabless_55560_56219.png efabless_56220_56375.png efabless_56376_56507.png efabless_56508_57227.png efabless_57228_57647.png efabless_57648_58057.png
Hello, everyone, and good day. My name is Mohammed Kalsim. I am the co-founder and CTO of E-Pedalus. And thank you very much for making the time to join the presentation. And I hope it would follow up with questions that are useful to everyone. So I'm going to give a little bit of an introduction about myself. And basically, I come from the chip world, from a long career in the wireless industry. My background is in analog circuit design. And I joined Texas Instruments when TI was starting the era of the chip development for smartphones in general. And then the smartphones later. And if you know a processor like OMAP, then you'll find that the analog on OMAP Partial F3 and OMAP4 and a bit of OMAP5 were my responsibility. So if you hate it or like it, you may blame it on me. And here are some of the devices that I was involved in indirectly at some point. I also am a thinker and I'm a hardware enthusiast and always design and look for what the chips do in smart devices or any devices. So that's my habit from since I was a kid. I open things down. Sometimes when I was a kid, I wasn't able to bring them back. But now that's my tear down the device. Device doesn't understand how they're constructed and what chips are in. And that's a passion of mine as well pretty much for a lot of the new devices that are out there. So I'm going to dive into the talk right away. And it's basically talking about the chip design and how we can approach the problem of the inaccessibility and the restrictions to innovations for this industry. So I have a friend of mine who just put together this little abstract view. And on the left side, it says, and it shows that as the process technology evolves from down in the feature size, the development cost of the process and the designs around it, they increase actually exponentially, the number of capable companies or people who have access to this technology and can design with it goes down. And that means the number of, generally, number of designs goes down. So it's a very simple view. Now, when the number of designs goes down, or designers rather go down, that means the number of or the freedom to actually thinker and have more ideas move into silicon becomes restricted, which in general restricts innovation. This is another view, it's a financial view. And this would probably be the last financial slide on this. It is actually. And it shows that over the years, that's the number of companies, companies, not individuals even, that have the access to advanced node technologies or process technologies. It's just going down over time. And that didn't change really over beyond 2018, since we're now in 2022. And the net by itself looks like the car companies. As it converges, you end up with a few car companies that have the market and the people who have ideas in the cars and engines. They just can't just come up with an idea anywhere and just say it works. So this is just the dynamics of the industry. Now, on the other side of the industry, the need, so there's so-called the long tail. I'm representing here with orange. And I intend it to drive this way, because I usually call it the very, very long tail. And what is that is that it's the customized applications for specific markets or specific use. And typically, people today, the hardware developers, they use what's available in the FPGA world or standard devices from the standard semiconductor, either processors or chips, which typically leads to different living with the form factor or extra capability on the chip. Or I need the five regulators or three regulators, but I'm getting six or just I need one extra. So there is what I call here. And also that's a term that I got from somebody. For my mind, it's a right-sized compute, right-sized compute, meaning that I can, for every problem that I am facing, I'd like to size the chip or the compute capability and the power, especially if it's a battery-powered device, to the application. Now, on the left-hand side, this is a traditional approach where smartphones, you have tens of millions, maybe tens of millions of units or hundreds of millions of units, which justifies the development cost around these applications. The problem with the yellow or the orange part is that they're lower volume. And generally speaking, it is hard to justify a cost of an ASIC for these orange areas. Now, and then the typical answer for that is the standard product. Then now we believe that the number of these applications are gonna be tens of thousands. So if you wanna achieve both the right-sized compute and the tens of thousands, you really need designer. Or you can't just have one standard product and you need designers around the world, which is the problem. So we wanna have a thousand X developers, roughly, to be able to deliver to that. Now, when people look at the LIMTail, they keep asking me, what's the killer app? I'm like, well, there's no killer app. I don't know what the killer app is. The only way to have this work is to have people try and communicate with the market or the end users and come back with iterations. So in order to do that, it was happening in the software world. It is happening in the software world in a way that is efficient so that you can compile something, make it an app and put it out and get feedback and improve. And you can see that in the software world. The only answer for the demand, to meet the demand for the customization of hardware and chips is a community-based approach, meaning that instead of saying, I need a company or 10 companies to deliver to the world, I will just say, we need the world to deliver to the world. We need to community around the world to learn and become capable of making the custom applications. And it's actually grows with the demand. And also it has a variety of expertise. You can tell from the open source community, for example, you can amere out of expertise that can actually deliver value. And then the last thing is the natural selection. This is beautiful is that people choose what they like to work on and what they're passionate about and probably what they're good at versus working in a restricted environment where you just have to do what you have to do. Now, I'm gonna jump to E-Fabulous. Just a quick overview of why E-Fabulous exists. I'm just gonna say it's for meeting that goal. So in order to get these 1000X account in designer, we need to simplify the process. Typically the process of making ships is very complicated. So we wanna simplify to make it easy and adaptable by a lot of people. And again, our user number 1000X don't quote me on it, but just a multiplier that it is actually hard to achieve with the current traditional approaches. So yeah, so we need the 1000X maybe more, maybe less, but we need a huge multiplier of the people who are able to design. Now, with either we're gonna have to educate people or change the concept or simplify the process, we need to have a combination because actually it's time to simplify the process because I don't need to know everything about the chip to be able to create a chip. That's what's actually achievable a little bit through the FPGA. So that's what we wanna do. The example that I'm gonna use here is that in the software, the app stores, the app stores, before the app stores, in order to develop a piece of software and market it and sell it or expose it to customers, it's a very hard process. When the app stores showed up, whether it's iOS or Android, what happened is that there's a development tool set that is very robust and has unreliable. And then there's a business process, structured flow of quality control or at least feedback and the connections to customers. So now if we can do that, then you can see, you remember in the software or the app stores, it just exploded into millions and millions of developers anywhere from kids all the way to any age that wants to do something on their own without have to worry to actually structure a company or so. And the process also has become simplified because of the tools that are available. Now in the chip world, if you think, some of the chips are actually this, you can be designed by one to four engineers. And there are chips that require 100 people, but my experience says you can get a lot done within 10 people if they know what they're doing. And that's hard to bring in one room if you're hiring, maybe, but if you're working with the community, you'll probably find these for 10 people to do something really great. Now, in order to do that, we need to democratize the access to the needed, what's needed to chip design. It's not as simple as a development kit. And then, again, business process and the connection to customers. So now this is how we're gonna go. Now, in order to get that, there are, it's a little bit, it's much more complex actually than just a development kit because it's not one owner. It doesn't come from one place like Apple, Google, other open markets places. So in order to produce a useful chip and that is usable by the users, and could be the end user of a smart lock, something that sits in an air purifier or air quality sensors or systems, you need to know the access to the market. You need to have knowledge that you may not have. IP or blocks that are currently gated by generally NDAs and on access costs, EDA tools, similarly, PDK and affordable manufacturing and a reduction of the cost of manufacturing. So there are partial solutions that exist and they're admirable work pieces, but it still doesn't provide that, you know, I want it once per all. So what we wanted to do is a complete holistic solution. And in order to do this, it's basically boiling the ocean. So the right thing is to do it one at a time by solving everyone with a different tactic. And generally speaking, I will leave this, the comments maybe for the questions, but that's how we did. So the key is that instead of having just a developing kit, then it becomes like a stack in a box basically that you can be available to everyone and designers can collaborate and define and develop and commercialize their products for application for long-tail applications. To start, we started with the EDA, that's one aspect of it. And one of the things is that we wanted basically to give the EDA's flow to anybody anywhere without cost or without the permission or the violation of any licenses. So we assembled a great variety of tools for analog and digital design from open source engines. And we worked to use them to develop real chips. We also, on the IP, this is kind of a recent view. So these are examples of the places you can find. I'm sure there are more, maybe I've missed, but I just quickly, I think given the programs that we're working on right now, you can go to EFAB to see what people are doing in actual silicon IP that is submitted into the Google projects, for example. And then there are other examples for accessing IP in a structured way, like LibreCores or QSoft. Generally, Google is good to find. I'm always surprised with what individuals or groups have been doing in improving what's available for design. Now, in order, as I said, in order to improve that this is actually work, we took it from ourselves to develop ASICs. And we started with a chip called Raven. This chip is a RISC-5 based on a PicoRV32 from ClearWolf. And the IP and or the blocks are analog are coming from XFAB boundary. And this chip is in 180 nanometer. And one thing we intended to do is to make that chip top-level open source. So if you go to GitHub at this location, you're gonna find the top-level very long is there including behavioral models for the analog so you can simulate the entire chip in a digital simulator actually with the analog presented in real numbers. We also developed another chip called Ravenna. This was based on a request from a customer and it has more resources and it's also open source and it's available for the tinkering and adding additional features. Both of them are available on our platform so you can access in black box mode the IP. These chips are, here we have four major chips that we started with. Now, on the left is that Raven and Ravenna RISC-5 microcontrollers and then the top right is actually an open source chip but the core is ARM based. So it is not when I say open source chip, I mean that the top-level connectivity or a net list. Now, it has a lot of components that are not open source but it is a representation or a step forward in that direction. And then in the bottom right, this is a chip called Hydra that is purely analog for characterization testing. All of these, it's important to say all of these have been completely designed and verified with 100% open source tools period. The Raven chip was actually demonstrated in different places, we partnered with other people to make it a part of the other integrations and then this is the Hydra chip just for those who wanna take a look at it later. It's an array of analog chip. One of the interesting things is that Raven has a top-level open source chip and the core being open source. The NAC, one of the NAC research labs looked at it as this is an ideal for trust through transparency. So they wanted to look at as, use it as a kind of an authenticator for our ACU processor for a little bit of a rooted trust. And they requested Raven, we send them the boards and they developed several applications as you can see here but they also specced with us the Ravena chip and we delivered it to them. Now, this is what general overview of eFabulous, but now as we published a Raven chip all over the world and we had the attention of different places, especially Google. And then Google's philosophy in this involvement was if you can have a continuous integration in software, why don't we have a continuous integration concept in the hardware or specific chip world, design something, build it and measure it or learn from it and then do it again and keep iterating. In order to do that, you really need to have a cost structure and availability and access to make it worse than what. So the Google program was, it started as Google would fund six manufacturing runs and that means and you'll see why it's 240 chips. And now when I say at least, it's because it's actually getting more now, there were four last year and there's another, at least another four this year, 22. And the first of which is in March 21st this year. The submitted designs, and by the way, just to get into this, you don't need to go through big hassle, you can start designing, go to eFabulous.com, just show the intent that you have a project and just write the abstract of the project and then some, if you finish before the deadline, meaning that you pass all the pre-checkers, then, which are available, automated and open source to you, then you're in. So it's a first come, first serve and Google's purpose from that is to just mobilize the wheel in terms of having people to learn and design and learn and re-iterate. So if your design is perfect and you're not taking too much risk or taking risk, so it is okay to get in and learn something. So if you don't be intimidated by that chip concept because it is, with proven that, you know, from a variety of ages and a variety of software and hardware experiences, things worked out. Here are some of the links, you can go and start. And we've proven, as I said, many of the users and designers have been not, almost half from the Google program, haven't designed the chip before and they have chips and they actually demonstrated a success. For more information, go get it and see. One of the programs, I'll go to the eFabric.com and see. The interesting things about the Google program is that the tools are open source and then you get a chip that is as a reference or a platform that you can modify and add to it your design. And then you get development boards, not just the parts and abundance of parts, obviously, if you wanna build your own boards. The key component of that program is a partnership with Google, SkyWater and Feblis. They started with the open sourcing, the PDK, which is a representation of the process technology. It's the models, it's the libraries, the IOs, different views and documentation. So it is available without an NDA, which has never happened in the history of this industry as Foundry would actually open source the PDK of a reliable process as is. Just to give a background, if you're familiar with the PSock devices from Cypress Semiconductors, SkyWater, it was a spin off, is a spin off from Cypress back in 2017, I think. And the process that is being used, the 130 nanometer, is the process that's being used for PSock devices. So it is truly professionally done for industrial grade manufacturing. Now, by people say, what is a 130 nanometer? I work personally on 130 nanometer, 17, actually, almost 20 years ago. That was my part of the development of the analog back then. Well, until today, you can do a lot. If you're gonna see, go see what people did today since the last three years on this link. However, just an example I wanna bring up is, if you look at the Intel chips themselves, back in this, the age of 2001, which is roughly about 20 years ago, you'll see that even 180 nanometer, you're able to get the speed of about 1.7 gigahertz. Of course, Intel has a lot of this customization and so to get there, but I'm saying that transistor pitch doesn't mean you won't get performance. And also some of the data that are borrowed from our friends in URO Practice, they have a very good annual report. It shows here that in the microcosm of use in semiconductors from a URO Practice standpoint, there's about 50% of the process technology or data project on the process or their customers, they're below something that's bigger than 90 nanometer, which is 1.10, 1.30, I don't know, I can see it. Now, part of the project for Google is that we develop almost a new compiler, right, for digital functions. So that means if you know very long, then you develop something in better log. And recently we made that in Python using something like Litux. You compile your code and you get a functioning design, maybe not the best performance, maybe not the best area, but it works so you can iterate. And the intent here was to make it available. The Google partner with me is Dimansal, always says, I'm a software guy, I don't know what a DRC is, I don't know how to fix it, I just want a complete design that works and manufacturable and I can learn from it. So if you do that and you make it look like a compiler, I use the new compilers all over the place, but I don't know how they work exactly. And I get software that I actually use. So if you apply this concept on the digital design, well, that means software developers should be able to do that without a blame. And that opens, starts opening this thousand X more, at least people that are capable of making a digital design. Now it's also in the analog design, same. If you learn the basics or you wanna go further, also that actually with the great help from the community, it's become possible. Now, both of them, this is actually again the community. So we're working closely, this is a collaboration between the Open Road team and the flow it's called Open Lane, that the E-Cab is developed. And it is on several process technologies available now. Analog is the same and it's collaboration with the, for example, in this here, the ZEIS team, Injustice team, and the X-Skeem developer, Stiff and Shippers. Now, part of the project also to simplify, so all of these things that I'm going to notice, I'm going to simplify layer by layer. We use the concept of Caravell because that's the, when you look at it or look it up, it's a ship that has specific properties that the Portuguese used back in the 15th, 16th century. Well, Caravell is a ship that is almost like a ship that has cargo space or project space that you can put your own design in it. It has resources, it's an open source ship, and it's using components from like OpenRAM and the BigRV32, which are open source generators and IP. And this ship, you also open source a new, because of the processes open, you'll see it all over the, it's open on GitHub. And here's the sum of the features of the on-chip features that you can utilize for your design. The way it's being used is this, the designer designs the block and then it gets dropped into the chip and that produces a user-specific Caravell. The designer only focuses on the left side of the slide. They don't have to worry about the Caravell itself except from the models and the behavioral verification to make sure that things work. And we plug it in into the Caravell master. Now the designer also gets actually 300 packaged parts, plus five boards, and I mentioned that early. So it is straight up, you can push it into the, is USB connector and get working. And the board is like here. So this is one example of the Caravell boards with a specific design on it. Now we, there are multiple directions, multiple tracks that we're improving on right now, again with a collaboration with the community. There's also one piece of news here is that because of what Skywater Foundry did, it got the attention of other boundaries. And then there will be, there's a plan for a second foundry and you may hear about announcement of that too. Just the engagement here that we can see when the Skywater PDK was opened, it gave us like, basically it's like a barrier of behavior against projects that are accessible for years. And also it gets downloaded about 700 times a week. We also have the Slack community that is rich with almost 2,500 people. You can join and get your self-invite from there. Now the first shuttle went with Google, was an interesting one, we called it in PW1. You can see the designs up there too. But it had a variety of contributors from individuals to companies. It was a quick book. Again, it's free for the designer funded by Google for the time being. And then, part of PW1 was actually to actually get this picture done. It's the first time the open source hardware, at least to my knowledge, they get engraved on actual chip that is totally open source all the way to GDS. There's no compromise here. And just to mention the community contribution, the John McMaster here, who's pictured in the bottom left, has actually took that chip, decapped it, and he has an electron scanning microscope at home to actually do that. So that's kind of a community interest. And then in PW2, again, I'm not gonna go over the whole design, but you can see the links. If you go to the link below, you'll see the full overview. And as well as the GitHub repositories. This is just a candy for the eye to see the two different, the 80 chips plus the test chips for the foundry up there. Now, the Google, when we found that it's very important that people say, I wanna open source my design and I wanna guarantee my spot and I wanna control my schedule. So we created an offering called Chippick Night. Chippick Night is basically the same thing for Google. Just shift it into eFabulous completely and to you actually, to the designer. He says, okay, I'm gonna get my own design. I don't have to open source it or not, that's up to me. And then I will book my space for 200 bucks starting designing, to start designing. And then you will get actually 10 millimeter squares inside the chip, which is I mentioned earlier, but it is actually, it's still the real state. I always say it's a framed house with plumbing and electricity and then you bring your own appliance. And these are some of the pricing here, but the pricing is actually intended to not to show the dollar numbers. That's it show that comparison. You can either get 100 parts with the QFN 300 with the WSP, which has never happened. Or if you're doing a low volume production, you can pay 20,000 and you get a thousand units, which is almost basically $20 per chip in all includes. These are options of Chip Ignite. Some of them are the same as the Chip Ignite as the area as it is. And then we got requests to say, if I don't wanna use the management area or the logic here, I wanna the area all myself. So we started offering that as well. Here's the schedule for Chip Ignite and MPW for Google. So these are two Chip Ignite data points. One of them is April 8th, the Google shuttle that's upcoming is March 21st. And the next Chip Ignite or second Chip Ignite in 2022 will be in June. Go, you know, can go to eFeders to come to see the details. The users of Chip Ignite, not the Google program, basically started with the universities. Here at Stanford University used it for a course. There was basically the whole course is designed and end up with a go to fabrication and then you come back and test it. Also the IEEE, they created a competition. So they actually got 10 Chip Ignites and then it was a great competition. You can view it and see how the, we had like 56 proposals in it, great designs. Startups also said, okay, I can use Chip Ignite as it is. Basically I can put my own designer like the blue in the middle here design. And then I have a product basically for low volume. I don't have to optimize the area because it makes sense economically and I, but I can get the market very quickly to my customer. This is back to the IEEE. It also shows that these were 10 projects from all over the world. The last six projects, you can see how people utilize one slot to multiple designs instead just having one slot for one project. This is the part where I showed the university. There's multiple aspects of the universities have started talking to us to actually adopt that either in the courses or in parallel sessions like the capstone projects and graduate research. And that's it. So I close here and then when you get the slides, you'll find I'm gonna flash through this very quickly. Fun from the community that I borrowed and just shared different people have posted different pictures and you'll be able to flash through them. And these are all contributors from different places. And they know their names, but you can find them also on Twitter. And it shows how passionate and competent the community and to actually get something done. This is a RAM test chip that Andrew Zonenberg created a board for testing it. This is a met then obviously people know met then they used one slot to create a course that has 16 slots. This is the parallel. This is us. Actually, this is me on my desk. And then other people like TNT or Sylvain Mone. This show you see the quality of the sharing, how people share things and incredible. Never happened before. And get the chance just to take a look at this. And that's my last slide. Thank you. And then open for questions. Ryan. So I look actually or okay now I can hear. Thank you Mohammed for a great talk and if you want to read any questions from the chat you'll be welcome. For instance let's see how much will that normally cost if not using cheap ignite say another shuttle. Well the most important thing I would like to say here is that the word shuttle is kind of a, the word shuttle is actually kind of tricky. As I mentioned a shuttle typically is it gives you an area on silicon so if you want to compare it would be wouldn't compare that's the area because you're getting an area with as I mentioned with the older resources around it to make work like logic analyzer an actual chip around your design. So definitely if you compare it so this would be that 10 millimeters for 10,000 and if you compare at this level even if the cost is the same but you wouldn't get the same resources around it and packaged devices and boards. Okay we have a question about when this lack will be bridged to IRC maybe. It is actually kind of to bridge 100% so if you go to the IRC servers you're going to find the space sky water dash PDK and I should actually I should have maybe I'll send the link later. And what else is Idra a reference design? It is a reference design the design but in the it's open as well but the the blocks in it are not however you can replace them now with a lot of the NPWs coming from blocks are coming from Google N chip Ignite open source. All right I think I'll ask a question myself. Go ahead. Okay what kind of interfaces the the kit has it is high speed can you put a USB maybe. Right now on the the board has USB you can connect it to the the the computer and then it comes with an open source just flashing software and and then you can go from there. Now the chip doesn't have USB yet at least it is right now it's either a UART or a spy interface out there and on top of the GP the general purpose IOS. The general purpose IOS maybe they are high speed what speed could they reach? For this process as they are they they're not high speed they're actually 60 megahertz maximum as they specified by the original design that's Cypress. However we have a flavor where you can designers on on the shuttles actually created their own like LBDS designs so you there will be a variety of highest higher speed IOS that are coming from the community shown you'll see it because people everybody is actually it feels limited by the 60 megahertz. Great so I think we'll wrap up and then anybody which wants to continue the link will be available soon to these two to the room where you could you can continue the chat thank you. Great thank you so much have a good day everyone.
Mohammed Kalsim. I am the co-founder and CTO of of the inaccessibility and the restrictions to which in general restricts innovation. This is justifies the development cost around these Google would fund six manufacturing runs and that for Google. So these are two Chip Ignite data For instance let's see how much will that