throughout the following description , specific details are set forth in order to provide a more thorough understanding of the invention . however , the invention may be practiced without these particulars . in other instances , well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention . accordingly , the specification and drawings are to be regarded in an illustrative , rather than a restrictive , sense . [ 0030 ] fig1 is a block diagram of the band - pass amplifying circuit 2 according to an embodiment of the invention . circuit 2 has input terminals 10 connected to receive a signal . the signal is typically a bioelectrical signal such as a signal picked up by a nerve cuff electrode or other implantable nerve electrode . the signal is coupled from input terminals 10 through protection circuitry 11 , which in turn passes the signal to inputs 12 of preamplifier stage 13 . the preamplified signal at the output 14 of preamplifier 13 is fed into a band - pass amplifier 15 , whose output 16 is fed into a dc restoration stage 17 . circuit 2 provides an output signal at point 18 . the output signal may be provided to follow - on circuitry or devices . in an implantable application , it is imperative to minimize any dc current flow through the electrodes to avoid electrolysis , or in the case of a semiconductor failure , to protect a subject &# 39 ; s nerves from irreversible damage . protection circuitry 11 has the function of blocking or at least minimizing any dc current flow through input terminal 10 ( and any implanted electrode connected to input terminal 10 ). if a malfunction , such as a semiconductor failure , in preamplifier 13 permits current to flow at the input of preamplifier 13 then protection circuitry 11 prevents the flow of current in an amount which would harm the subject &# 39 ; s nerves . current regulations and good design practice suggests that a subject have at least two stages of protection to prevent excessive currents at input terminals 10 . preamplifier 13 could be designed with a bipolar input stage . protection circuit 11 could then be designed to provide two or more protection stages . bipolar transistors require large input bias currents for their operation . the bias current may be hundreds of na . good design , and applicable regulations both require that no single component failure should be able to cause significant currents to flow in input terminals 10 . the protection stages of protection circuit 11 typically are implemented using discrete components , due to the time constants involved . such discrete components occupy a large area . the circuits according to the preferred embodiments of this invention use a cmos input stage in preamplifier 13 . since the input bias current of a cmos transistor is in the order of fa , only one additional protection stage is needed . the input stage of preamplifier 13 itself acts as a protection stage . this permits protection circuitry 11 to be reduced to a single high - value resistor in parallel with a capacitor which is preferably implemented as a series of two capacitors as shown for example in fig2 b . this , in turn , reduces the overall size of circuit 2 . as mentioned above , the noise of the band - pass amplifying circuit 2 is dictated primarily by the input stage of preamplifier 13 . preamplifier 13 is preferably implemented as a differential difference amplifier ( dda ). a dda by g . nicollini and c . guardiani , “ a 3 . 3 - v 800 - nv rms noise , gain - programmable cmos microphone preamplifier design using yield modeling technique ”, ieee journal of solid - state circuits , vol . 28 , no . 8 , pp . 915 - 921 , august 1993 . the basic dda architecture was introduced by e . säckinger and w . guggenbühl , “ a versatile building block : the cmos differential difference amplifier ”, ieee journal of solid - state circuits , vol . 22 , no . 2 , pp . 287 - 294 , april 1987 . several circuits custom - designed for different applications , based on this structure , have been patented . see , for example , u . s . pat . no . 5 , 861 , 778 to louagie et al . for a “ low noise amplifier structure ” and u . s . pat . no . 5 , 339 , 285 to straw for a “ monolithic low noise preamplifier for piezoelectric sensors ”. band - pass amplifier 15 may be implemented by cascading two high - psrr , first - order band - pass amplifiers , each one composed of a g m - c high - pass filter and a low - pass amplifying circuit . dc restoration stage 17 can also be implemented using a g mo - c o high - pass filter , but with a input - linear - range higher than the input linear ranges of the high - pass filters of band - pass amplifier 15 . two alternative architectures for the circuit presented in this invention are shown in fig2 a and 2 b . in fig2 a , protection circuitry 11 comprises a discrete r p - c p high - pass filter that blocks completely any dc current flow caused by a semiconductor failure in preamplifier 13 . resistor r cm causes protection circuitry 11 to act in the same way on both input terminals 10 . this avoids degradation of the cmrr due to the presence of protection circuitry 11 . alternatively , in fig2 b , protection circuitry 11 ′ comprises a high - value resistor r b in parallel with a series of capacitors c b . protection circuitry 11 ′ minimizes any dc current flow caused by a semiconductor failure in preamplifier 13 . capacitors c b are selected to minimize power - line noise . in terms of noise performance and number of external components needed , the protection circuit 11 ′ in fig2 b is preferable to the protection circuit 11 of fig2 a . however , in case of a semiconductor failure , protection circuit 11 completely blocks any dc flow to the electrodes and tissues as opposed to reducing the dc flow below an acceptable threshold . in preferred embodiments , band - pass amplifier 2 has a single - ended output architecture . while a differential output can be used in the context of the invention and may provide enhanced performance , significant area and power penalties must be paid to achieve those benefits . gain programmability may be achieved , as shown in fig2 a and 2 b , by using switches that select different combinations of resistors to vary the ratios of r 3 to r 4 . the gain of preamplifier 13 , in the recording band , may be fixed and given by the ratio ( 1 + r 1 / r 2 ). in preferred embodiments , the high - pass filtering stages are implemented with g m - c filters since precision in the poles is not crucial . the closed - loop transfer function of the low - pass amplifier amp 1 may be set to have its dominant pole at 9 khz ( for 5 μv peak input neural signals ), while providing the necessary further gain . such dc gain is given by the ratio ( 1 + r 3 / r 4 ). the dc restoration stage 17 may comprise a g mo - c o high - pass filter , preferably with an input linear range higher than 0 . 2 v . precision again is not crucial since this stage is only needed for compensation of the band - pass amplifying circuit offset . finally , in fig2 a and 2 b it can be observed that a reference voltage 22 is supplied as an input to the preamplifier 13 and the two low - pass amplifiers amp 1 . this contributes to improving the psrr of the band - pass amplifying circuit in the recording band , as explained below . [ 0041 ] fig3 shows a possible circuit for preamplifier 13 . the m 1 differential pairs realize the transconductance elements of a two - stage dda . the current sources m 3 are implemented using a cascode design as described in r . gregorian and g . c . temes , “ analog mos integrated circuits for signal processing ”, pp . 131 - 133 , john wiley & amp ; sons , 1986 . this provides good matching of the two input stages , which is important in optimizing the performance of a dda . on the other hand , the use of cascode current sources adds a pmos threshold voltage v t to the minimum supply voltage v dd needed for operation ; however , in this case the supply voltage v dd is typically not a limiting factor . the differential current generated by transistors m 1 is converted into a single - ended current by a cascode configuration , comprising transistors q 5 and cascode mirror m 2 . with this configuration , better frequency response can be achieved than in the case of an amplifier based on a cascade of two common - source stages . this is particularly true in the case of preamplifier 13 , since the parasitic capacitance given by the large input transistors m 1 ( needed to achieve low - noise ) is considerable . transistor m 10 provides further gain and accommodates the biasing of the output stage composed by m 11 , m 12 , q 13 and r d . the second stage of preamplifier 13 could comprise a single transistor but , in the preferred embodiment , comprises a transistor m 10 with capacitors c m1 and r m providing frequency compensation . see p . r . gray and r . g . meyer , “ mos operational amplifiers design — a tutorial overview ”, ieee journal of solid - state circuits , vol . sc - 17 , no . 6 , pp . 969 - 982 , december 1982 . finally , the equivalent darlington pnp transistor m 12 - q 13 provides very low output impedance while drawing no current from the second stage . see a . r . alvarez , “ bicmos technology and applications ”, pp . 317 - 318 , second edition , kluwer academics publishers , 1993 . in this way , preamplifier 13 provides negligible systematic offset independent of variations in the electrical characteristics of the fabrication process . this is important for the successful performance of a dda . the transistors may be sized according to the methods presented by f . silveira , d . flandre and p . jespers , “ a gm / i d based methodology for the design of cmos analog circuits and its application to the synthesis of a silicon - on - insulator micropower ota ”, ieee jounal of solid - state circuits , vol . 31 , no . 9 , pp . 1314 - 1319 , september 1996 . these methods are based on the relation of the transconductance over drain current ratio ( g m / i d ), to the normalized current ( i d /( w / l )) and allow a unified treatment of all regions of operation of the mosfet transistors . sizing of the transistors can be achieved for example by using this method and the ekv model , with a set of parameters and measurements from the process . see e . a . vittoz , “ micropower techniques , design of analog - digital vlsi circuits for telecommunications and signal processing ”, pp . 53 - 67 , eds . j . e . franca and y . p . tsividis , prentice hall , 1993 ; and c . c . enz et al ., “ an analytical mos transistor model valid in all regions of operation and dedicated to low - voltage and low - power applications ”, analog integrated circuits and signal processing , no . 8 , pp . 83 - 114 , 1995 . a main specification that applies to the preamplifier 13 is its noise level . the equivalent total input noise spectral density s i has the following expression : s i =  4  s m1 + s r2 + 4  ( g m2 g m1 ) 2  s m2 + 2  ( 1 g m1  r a ) 2  s ra + s 1 / gm a cdda 2  ( f / f hpf ) 2 ( 1 ) s m1 represents the noise contribution of an m 1 input transistor . there are four of these transistors contributing directly to the input noise . the noise of preamplifier 13 is dominated by this factor . s r2 represents the noise contribution of resistance r 2 that passes directly to the inputs 12 . s m2 represents the noise contribution of a m 2 current mirror transistor . the contribution of these loads is reduced by the square of the ratio of their transconductance to that of the input transistors m 1 . s ra represents the noise contribution of a r a resistor . the contribution of these resistors is also reduced by the square of the product of their value and the transconductance of the input transistors m 1 . s 1 / gm is the noise of the equivalent resistor of the g m - c high - pass filter . s 1 / gm is reduced by two factors . first of all , it is reduced by the gain of the preamplifier 13 ( a cdda ), since this stage precedes the filter , and second it decreases with frequency as stated in equation ( 1 ). this decrease is logical since , after the high - pass filter pole ( f hpf ), the capacitor c can be seen as a short circuit . this places the equivalent resistor 1 / g m in parallel with resistor r 1 . a rough calculation shows that , in order to maintain a noise level from thermal sources which does not exceed approximately 0 . 6 μv rms in a 10 khz bandwidth , the total equivalent input noise should be { square root }{ square root over ( s 1 )}= 6nv /{ square root }{ square root over ( hz )}. since in a well - designed amplifier the input transistors dominate the noise , the required level of mosfet transconductance can be achieved only near weak inversion . the selection of the mosfet type for the input transistors m 1 was studied in detail . it is well known that in strong inversion the flicker noise of a pmos transistor is lower than that of nmos transistors . however , it has been reported that flicker noise in pmos transistors may significantly increase when such transistors move from strong inversion toward weak inversion . see d . m . binkley et al ., “ a micropower cmos , direct - conversion , vlf receiver chip for magnetic - field wireless applications ”, ieee journal of solid - state circuits , vol . 33 , no . 3 , pp . 344 - 358 , march 1998 . still others have reported the flicker noise going down , indicating that it arises from a mechanism that is strongly affected by details of device fabrication . the very severe increase in flicker noise has not been observed in prototype circuits according to this invention . therefore transistors m 1 may be pmos in some embodiments of the invention . in embodiments in which the band - pass amplifying circuit 2 is fabricated using an n - well technology , this selection improves the psrr of the circuit as well . by implementing the transfer function of the band - pass amplifying circuit 2 and the noise equation given by equation ( 1 ) in the matlab ® design environment , thermal noise levels for each factor were assigned . this approach led to a value of ( g m / i d )= 16 . 81v − 1 for the input transistors m 1 , that corresponds to a ( w / l )= 4480 . common - centroid crossed - coupling layouts may be used for transistors m 1 . r . p . jindal , “ noise associated with distributed resistance of mosfet gate structures in integrated circuits ”, ieee transactions on electron devices , vol . ed - 31 , no . 10 , pp . 1505 - 1509 , october 1984 describes some common - centroid crossed - coupling layouts . the load m 2 in a prototype circuit according to the invention resulted deep in strong inversion because its transconductance was chosen almost five times lower than that of the input transistors to minimize noise . this resulted in a ( w / l )= 74 . 5 . resistors r a were dimensioned based on biasing requirements , noise minimization , and the folded cascode requirement that g m5 r a & gt ;& gt ; 1 . this integrated resistor is made of a p + diffusion , with a typical value in the range of 64 to 96 to ω /□ ( ohms per square ). in the currently preferred embodiment , r a has a value of 2245 ω . the cmrr of the embodiment of preamplifier 13 shown in fig3 may be expressed by : cmrr = 1 1 2  g m1  r om3  δ   g m1 g m1 + δ   μ 1 μ 1 ( 2 ) where r om3 is the output impedance of the cascode current source formed by transistors m 3 , δg m1 , is the mismatch between the transconductances of transistors m 1 , μ 1 is the voltage gain of transistors m 1 , and δμ 1 , is the mismatch between the voltage gains of such transistors . based on mismatch measurements previously performed for the present technology , the size of transistor m 4 may be chosen to be ( w / l )= 20 . 3 . transistor m 3 is composed of a few transistors m 4 in order to provide the necessary bias current level for the input transistors m 1 . in this way , the cmrr given by equation ( 2 ) is mainly determined by the mismatch in the voltage gain μ 1 . cmrrs in the order of 95 db can be achieved . the output stage formed by m 11 , m 12 , q 13 and r d , may be designed based on the excursion expected at output 14 . amplified emg signals caused by mismatches in nerve cuffs as well as random offset of the preamplifier 13 should be taken into account . the design of the second stage composed by m 9 , m 10 , c m1 , and r m was based on the minimization of systematic offset and the phase margin desired for the preamplifier 13 . in a prototype circuit according to the invention , transistors q 5 - q 13 have an emitter area of 6 . 4 × 9 . 6 μm 2 . the connection of capacitor c m1 between reference voltage 22 and the gate of one of the m 2 transistors , as shown in fig3 improves the psrr of preamplifier 13 . as analyzed by e . säckinger et al ., “ a general relationship between amplifier parameters , and its application to psrr improvement ”, ieee transactions on circuits and systems , vol . 38 , no . 10 , pp . 1173 - 1181 , october 1991 , there is a constraint for the simultaneous improvement of the cmrr and the psrr in any kind of amplifier . the psrr of single - ended amplifiers can be improved and rejection in the mid - frequency range can be improved by connecting a capacitor between the amplifier input and a noise - free reference , in this case , reference voltage 22 . this is the role capacitor c m1 plays in the preamplifier 13 . as mentioned above , band - pass amplifier 15 may be implemented by cascading two high - psrr , first - order band - pass amplifiers , each composed of a g m - c high - pass filter and a low - pass amplifying circuit . in fig4 the g m - c high - pass filter is shown . the transconductance g m is provided by a basic differential pair with active load . all the transistors shown are placed in the moderate inversion region . this provides enough linear range for the present application . [ 0061 ] fig5 shows a preferred embodiment of the amplifier amp 1 . this is a miller - type amplifier with a darlington output stage that provides low - output impedance . darlington transistors q 23 obtain their bias currents from transistors m 21 and m 22 , which also carry signal current , making the amplifier a class ab . this reduces power consumption since it avoids the need of extra transistors to bias transistors q 23 . resistors r 3 and r 4 provide feedback for closed - loop operation . since the two amplifiers amp 1 give the low - pass filter characteristic of the band - pass amplifying circuit 2 , its cutoff frequency is set by the gain of this stage and by the high - pole specification of the band - pass amplifying circuit 2 . capacitor c m2 connected between reference voltage 22 and the gates of transistors m 17 increases the psrr in the passed band , as explained above for the preamplifier 13 . [ 0062 ] fig6 shows the gain programmability obtained by using an n - well resistor string and four switches sw 1 to sw 4 to select different combinations of resistors to vary the ratios of r 3 to r 4 . switches sw 1 to sw 4 may be electronic switches controlled by control logic ( now shown ). in this example , switches sw 1 to sw 4 are selected one at a time according to the desired gain for amp 1 . the switches sw 1 to sw 4 are placed in series with the feedback inputs 21 and 25 , and therefore their finite “ on ” resistance does not affect the gain . of course , the number of switches and resistors can be varied depending on the number of externally controlled gain levels desired . finally , fig7 shows the dc restoration stage . it is implemented using a g mo - c o high - pass filter since precision in the pole is not critical . the cutoff frequency is preferably in the range of 400 hz to 600 hz and is most preferably about 480 hz . this further helps to reduce noise of biological origin while allowing band - pass amplifying circuit 2 to recover within a few milliseconds from overload such as could be caused by stimulation currents or while being cycled on / off . as will be apparent to those skilled in the art in the light of the foregoing disclosure , many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof . accordingly , the scope of the invention is to be construed in accordance with the substance defined by the following claims .
an implantable microvolt - level signal amplifying circuit may be used for resolving electrical signals generated by nerves in the presence of larger amplitude signals generated by muscles , the heart , or external noise sources . the circuit has a low - noise , high common mode rejection ratio preamplifier , followed by a cascade of stages , which provide filtering and further amplification of the neural signal . the band - pass amplifying circuit can also present high power supply rejection ratio . the output is offset - compensated by a dc restoration stage . nerve protection circuitry minimizes or blocks dc current flow through the input terminals in the event of semiconductor failure in the preamplifier . the circuit may be incorporated onto a common monolithic circuit with follow - up circuitry for controlling functional electrical stimulation devices .