in a preferred embodiment , the current generator comprises a pulse generator for generating the calibrated testing pulse . according to the type of test , i . e . the test of a nerve or of a muscle , a respective resistive path allows to maintain an adapted voltage at the output of the pulse generator . a determination device preferably in the form of a power transistor is base - connected to the output of the pulse generator . a measure of the voltage resulting at the emitter point of the power transistor is made to determine if the testing current is provided by the collector path of the transistor or by the base path . if the tested channel is connected , the testing current flows from the high voltage of the muscle or nerve to the current generator , thereby charging the stimulation capacitor . in case the tested channel is disconnected , the current sunk by the current generator must be provided by one of the resistive path , thereby generating a characteristic voltage drop at the output of the pulse generator . the chosen voltage drops are such that no stimulation may be applied to the muscle or nerve . referring to fig1 an exemplary implantable device 100 to be implanted in a paraplegic patient is described . to the extent that certain components of device 100 are conventional for stimulation application in their design and operation , such components ( a conventional programmer for example ) will not be described here and only the circuits operating in conjunction with the present invention are now described . the implantable device 100 comprises an application specific integrated circuit ( generally asic ) 102 powered at a vdd voltage . the asic to be detailed later receives input data on a “ data ” line from external circuitry to be operated either for stimulation or for measurements . the measured data are outputted on a “ measure ” line . a controllable switch component having a command line 104 allows to discharge a stimulation capacitor 106 after each stimulation operation . the stimulation capacitor 106 is connected between an electrode 108 and a power transistor 110 in which flows a stimulation current i . the electrode 108 is connected to a muscle 112 . it is to be understood that the electrode could be connected to a nerve for neural stimulation . as already explained , muscle and neural stimulation for paraplegia require a high power voltage vpp due to the intrinsic impedance of the muscle or the nerve . the details of the relevant circuits which make up the testing device of the present invention are shown in block circuit form in fig2 with reference numerals being the same for circuits identical to fig1 . for sake of clarity , only two electrodes are shown on the figure but one of ordinary skill could easily extend the concept of the invention to a plurality of electrodes either connected to muscle or nerve . a first digital to analog current converter 200 provides a first programmable calibrated stimulation current “ i ” to feed epymisial channels , depending on the value of intensity weights on the d / a converter input . a second digital to analog current converter ( not shown for clarity reason ) provides a second programmable calibrated stimulation current to feed neural channels . each dac may be conventional n - bits converter . both dacs may be respectively activated by a command signal “ co ” which enables the stimulation current “ i ” to be sunk only when the input data ( the binary intensity weights ) have reached stable values . in the preferred embodiment , the first dac 200 is a 8 - bits converter for muscle stimulation while the second dac is a 6 - bits converter for neural stimulation , and the stimulation current i 1 is in the range of 0 to 25 ma for the epymisial case while the stimulation current i 2 is in the range of 0 to 3 ma for the neural case . a control circuit 202 inputting epymisial and neural selection signals “ epy ” and “ neu ” is coupled to power transistor 110 . preferably , one control circuit is associated to each electrode 108 and one circuit is active at a time . the selection of the active control circuit may be realized by common address decoding circuits ( illustrated as address bits a 0 - an on fig2 ). in response to a pulsed input signal “ pw ”, control circuit 202 generates a calibrated command stimulation signal “ sti ” on base of power transistor 110 . one preferred implementation of control circuit 202 is shown on fig3 with circuit 300 being composed of five transistors of fet type . however , the person skilled in the art will easily devise other circuit design required by other technology such as bipolar transistors for example . transistor t 1 receives on its gate the “ epy ” signal and having its drain connected to power voltage vdd . similarly transistor t 3 receives on its gate the “ neu ” signal and having its drain connected to power voltage vdd . the source of t 1 is connected to the drain of transistor t 2 . the source of t 3 is connected to the drain of transistor t 4 . transistors t 2 and t 4 are gate connected to receive the pulsed command signal “ pw ”. the sources of t 2 and t 4 are connected to the drain of transistor t 5 which also inputs on its gate pulsed command signal “ pw ”. the source of t 5 is connected to low voltage ( ground voltage vg ). the output “ sti ” of control circuit 300 is available on the output line 302 . during testing operation , a pulse signal “ pw ” is applied to the gate of transistors ( t 2 , t 4 ) to turn them on and to the gate of transistor t 5 to turn off . according to the active selection signal “ epy ” or “ neu ”, one of the transistor t 1 or t 3 is on , which means testing of a nerve channel or a muscle channel . the initial high voltage ( vdd ) on output line 302 is lowered by the voltage drop due to the resistive path made by either t 1 and t 2 or by t 3 and t 4 . if there is no electrical discontinuity in the tested channel , the voltage on output line 302 ( i . e . the base voltage of power transistor 110 ) remains high , and the current sunk in the emitter of power transistor 110 is provided by the collector of this latter . if there is an electrical discontinuity in the tested channel , the voltage on output line 302 decreases significantly as the current sunk in the emitter of transistor 110 is provided by the resistive path of control circuit 300 through the base of power transistor 110 . the value of each resistive path is chosen such that the current for epymisial testing or neural testing allows a significant voltage drop while avoiding a stimulation effect of the nerve or muscle . in the preferred implementation , for a power voltage vdd of 5v , the voltage drop is around 2v with a current of 2 ma for epymisial testing and a current of 200 ua for neural testing . coming back to fig2 the circuits to measure the voltage on the emitter of power transistor 110 will now be described . a voltage analog to digital converter 204 is connected to the emitter of power transistor 110 . a sampling clock signal “ sc ” is applied to the input of the converter 204 to sample the voltage of the emitter . the voltage is converted in a well - known manner into parallel bits . the parallel bits are stored in a register circuit 206 . register 206 is a common shift register which swaps the parallel bits into serial bits . the serial bits are outputted at a predetermined cycle time defined by a register clock “ rc ”. in an alternate embodiment , a selector circuit may be connected between the emitter of transistor 110 and a / d converter 204 in order to sample other analog data such as battery voltage level , power supplies measurement . a selector signal can be easily designed by a person skilled in the art to determine the selected type of data to be measured . on top of fig2 an electrical representation of the muscle or the nerve is shown . the muscle or nerve is generally represented as a resistor 112 . the electrode plus the lead is schematically illustrated by connection point 108 . stimulation capacitor 106 is in series between the lead connection point 108 and the collector of power transistor 110 . a switch circuit is connected between the collector of power transistor 110 and the high power voltage vpp . the switch is closed in inactive mode ( no stimulation , no test ) to allow the stimulation capacitor 106 to be discharged through the impedance path ( 108 , 112 ). the switch is open in stimulation or testing mode , and a controlled current is sunk through the power transistor 110 during a calibrated time window “ sti ” as previously explained . the capacitor is thus charged at a constant current i . in a preferred embodiment , the high power voltage is 40v in order to get a sufficient current (& gt ; 20 ma ) to the muscle , which offers a resistive value in the range of 1500 ohms . to restate , the principle of impedance testing is to detect if a current is flowing from the muscle or nerve through the stimulation capacitor cs . if the electrode is connected to the muscle ( or the nerve ) there is a current flowing in the muscle ( or the nerve ), but if no current is flowing it means that the electrode is disconnected from the muscle ( or the nerve ) or broken . reference is now made to the timing diagram of fig4 . to operate in test mode the circuit of the invention , a dc current is first determined by the settings of the intensity weights on the d / a converter inputs , which are validated by the “ co ” command . then the type of stimulation is selected by activation of one of the selection signals “ epy ” or “ neu ”. the stimulation signal “ sti ” is generated on the output of the control circuit and one power transistor 110 becomes active as already explained . during the duration of the stimulation signal “ sti ”, the sampling clock “ sc ” is running in order to convert the emitter voltage of the active power transistor 110 into p - binary data . finally , the p - binary data are stored into a p - bits register 206 . the stored data are then serially outputted as shown on last line “ measure ” of fig4 during p clock cycles “ rc ”. the output pattern is thus representative of the voltage emitter status . one advantage the solution is that the test is completely performed internally to the implantable device . other advantages include that only a few devices are required , no extra i / os are required for the asic , and no extra feed through wires for the implant are required . still other advantages include no extra external components are required for the implant , implant is simpler ( no extra wiring ), the power consumption is optimized ( the asic is low powered ), there is no limitation of the number of lead connections , and the solution offers flexibility on the timings as the impedance test can be performed either during a normal stimulation or during a test mode without any stimulation of the muscle or the nerve . it is to be understood that the provided illustrative examples are by no means exhaustive of the many possible uses for my invention . from the foregoing description , one skilled in the art can easily ascertain the essential characteristics of this invention and , without departing from the spirit and scope thereof , can make various changes and modifications of the invention to adapt it to various usages and conditions . it is to be understood that the present invention is not limited to the sole embodiment described above , but encompasses any and all embodiments within the scope of the following claims :
an apparatus for testing the impedance of a medical lead connecting an implantable stimulation device to a nerve or a muscle . the implantable device is of the type comprising a capacitor for stimulating the nerve or the muscle . the system of the invention comprises a current generator for generating a testing current “ i ” during a calibrated testing pulse and a power circuit coupled to the capacitor and to the current generator for determining if the capacitor is charged by the testing current during the calibrated testing pulse .