both of the above unwanted effects are avoided in the present invention . in fig4 reference number 10 again designates a heart , having an atrial lead 11 with an electrode 12 therein , and a ventricular lead 14 with electrode 15 positioned therein . lead 11 connects to terminal 13 and lead 14 connects to ventricular terminal 16 . inside the pacemaker , atrial terminal 13 connects to the input of atrial sensing amplifier and detector 20 which functions to detect p - waves indicative of atrial contractions . atrial sense amplifier 20 sends signals over conductor 21 to the start input of the a - v delay timer 22 . unless reset by a signal applied to its reset input from conductor 41 , timer 22 provides a triggering pulse at its trigger output at the a - v delay interval following receipt of a start signal from conductor 21 . this trigger signal is applied over conductor 23 to the upper rate limit control circuitry which is described in detail below . the ventricular terminal 16 connects via conductor 31 to the output of a output pulse generating circuit 30 which functions , as is known in the prior art , to generate the ventricular stimulating pulses . generator 30 generates its pulses in response to ventricular pace or atrial trigger signals applied to its input over conductor 32 . a branch of conductor 31 connects to the ventricular sensing amplifier and detector 40 , which functions to produce signals at its output on conductor 41 indicative of ventricular events , i . e ., either a ventricular contraction or a ventricular stimulation pulse . both atrial sensing amplifier 20 and ventricular sensing amplifier 40 have circuit means for providing refractory periods for the sensing amplifier following detection of sensed atrial or ventricular events , respectively . in the preferred embodiment the atrial amplifier is rendered inoperative upon occurrence of an atrial or ventricular event , and it remains refractory during the refractory period of the ventricular amplifier and for an overlap period thereafter . the preferred embodiment uses the atrial refractory control as disclosed in my copending patent application entitled &# 34 ; pacemaker atrial refractory control for r - wave rejection .&# 34 ; a branch of conductor 41 connects to the reset input of lower rate timer 42 . timer 42 functions to produce a signal at its output on conductor 43 at the end of its time - out interval corresponding to the lower , ventricular backup rate escape interval . a program control circuit 50 is provided which operates in the manner known in the art to receive control signals in the form of rf energy transmitted from outside the body and received by antenna 51 . controller 50 decodes and processes the received rf signals to send program signals to timer 22 via data bus 52 ; to the lower rate timer 42 via data bus 53 ; and to the upper rate limit control via data bus 54 . although single lines are shown in the drawing for purposes of clarity , it will be appreciated that the program signals to the three timing circuits preferably take the form of digital control words , and thus data buses 52 , 53 , and 54 may comprise several parallel data lines to convey the digital control signals for programming the intervals . by means of the program control circuitry , one of several possible time delays can be selected for timer 22 , as may be appropriate for the patient . similarly , the upper and lower beat per minute rate values can be selected as appropriate for a given individual . within the upper rate limit control or triggering coupling circuit is an upper rate limit timer 60 which receives start signals over conductor 61 from or gate 62 . timer 60 provides a time - out signal at its output at lead 63 , at the end of the upper rate interval , for example 343 milliseconds in the case of an upper rate limit of 175 beats per minute . conductor 63 connects to one input of an and gate 64 , the other input of which is connected to conductor 23 . the output of and gate 64 connects via conductor 65 to one input of an or gate 70 , and to the reset input of a flip flop 71 . a branch of conductor 41 connects to one input of or gate 62 , and a branch of conductor 43 connects to its other input . a branch of conductor 43 also connects to an input of or gate 70 , and to the set input of flip - flop 71 . data bus 54 connects to a plurality of and gates 72a through 72n . the exact number of gates corresponds to the number of parallel bits of the program information , but for purposes of clarity only the least and most significant bits are shown in the drawing . the other inputs to gates 72a through 72n connect via conductor 73 to the q output of flip flop 71 . the outputs from and gates 72a through 72n connect over leads 74a through 74n to inputs of or gates 75a through 75n . again the number of or gates corresponds to the number of bits in the digital control for the timer program value . the output of these or gates connect through conductors 76a through 76n to the program inputs for upper rate timer 60 . a circuit 80 is provided to generate an output digital control word corresponding to a time rate interval of 100 beats per minute , which corresponds to an escape interval of 600 milliseconds . this control word is outputted on conductors 81a through 81n which connect to inputs in and gates 82a through 82n . the outputs of these gates conduct via conductors 83a through 83n to the other inputs of or gates 75a through 75n . the other inputs to and gates 82 connect from the q output of flip flop 71 by conductor 84 . in operation in normal atrial synchronous mode , ( corresponding to the 60 through 175 beat per minute range of fig2 ) p - waves are detected by sense amplifier 20 and start timer 22 . at the end of the a - v delay interval , a triggering pulse is emitted at conductor 23 which will couple through and gate 64 and or gate 70 to pulse generator 30 , causing it to generate and deliver a ventricular stimulation pulse . this sequence assumes that the upper rate timer 60 would have timed out its interval prior to the triggering pulse on conductor 23 , which of course would be the case in the above - mentioned one to one region of the operating curve of fig2 . in the case of atrial synchronous operation at a rate in excess of the upper rate limit , the triggering signal 23 is presented by timer 22 , but it is held at gate 64 until timer 60 completes its time - out interval , after which time the triggering signal is gated to cause generator 30 to deliver its output pulse . in that manner upper rate timer 60 serves to prevent delivery of pacing pulses at a rate in excess of the program value . when the triggering pulse is transmitted through conductor 65 to gate 70 and generator 30 , it also resets flip flop 71 . this enables gates 72 and disables gates 82 , so that the upper rate limit interval applicable for timer 60 is the program value from program control 50 . occurrence of either a ventricular stimulation pulse or a natural ventricular contraction is detected by circuit 40 , which transmits a signal on conductor 41 to reset timers 22 and 42 , and restart timer 60 . operation of the circuit of fig4 in the lower rate ventricular backup mode is as follows . if a ventricular event does not occur prior to the time - out of the lower rate timer 42 , an output pulse will be generated . for example , assuming that the programmed value for timer 42 is 1 , 000 milliseconds , corresponding to a pacing rate of 60 beats per minute , timer 42 will send a signal over lead 43 through gate 70 to generator 30 , causing it to deliver an output stimulating pulse when timer 42 times out . another pulse will be caused by timer 42 1 , 000 milliseconds later , unless prior to that time , either a spontaneous ventricular contraction takes place , or a ventricular stimulus is emitted caused by the control path including atrial amplifier 20 , delay timer 22 , and gate 64 . at the same time that lower rate timer 42 causes generator 30 to deliver an output pulse , the signal on conductor 43 sets flip flop 71 . this in turn provides a signal on conductor 84 from the q output to enable gates 82a - 82n , and a signal on conductor 73 to disable gates 72a - 72n . this switching of flipflop 71 gates the code for a 100 beat per minute rate from device 80 into the program inputs of timer 60 . upper rate timer 60 will remain programmed for the 100 bpm - 600 ms escape interval timing as long as pacing of the heart is under control of the lower rate timer 42 . when atrial synchrony is regained and a pacing signal is transmitted through conductor 65 to the output circuit , flip flop 71 is reset and the 100 bpm - 600 ms timing is removed and the program upper rate limit from data bus 54 is gated into upper rate timer 60 . the operation of the pacemaker of fig4 in overcoming the problem of closely coupled ventricular pulses that exists in the prior art will be seen with the aid of fig5 . in fig5 the horizontal axis again represents time and the six heart and pacemaker parameters that were labeled in fig3 are also shown in fig5 but for the operation of the circuit of fig4 . for illustrative purposes , the first p - wave and ventricular stimulation pulse show atrial synchronous mode of pacing . however , the next several pulses show pacing at the lower ventricular backup rate . this is because the p - waves are occurring with escape intervals of approximately 1 , 075 ms , which is roughly 56 bpm , a slower rate than the programmed 60 bpm - 1 , 000 ms escape interval for the lower rate timer . accordingly , the second , third , fourth , and fifth ventricular stimulation pulses are delivered at 1 , 000 ms intervals , and the p - waves and ventricular stimulation pulses become dissociated , with the p - wave drifting through the ventricular stimulation pulse time . on the fifth p - wave of fig5 the p - wave occurs just after the end of the refractory period of the atrial sensing amplifier following the ventricular stimulation pulse . it will be recalled that in the case of the prior art of fig3 this situation resulted in the delivery of the closely coupled second ventricular pulse , separated from the preceding pulse by only the upper rate limit escape interval of 343 ms . however , the invention of fig4 solves this problem because the upper rate limit timer has been switched to a lower upper rate of 100 bpm - 600 ms escape interval . this is seen in fig5 wherein the upper rate timer times out a short 343 ms interval on the first cycle which was triggered through the atrial sensing path . the second heartbeat cycle shown was triggered by the lower rate timer and the flip flop 71 was set to switch the program value for timer 60 . therefore on the second , third , fourth and fifth cycles shown in fig5 the ventricular time - out rate is switched to the 100 bpm - 600 ms interval . therefore , on the fifth cycle where the p - wave occurs immediately after the refractory period of the atrial amplifier , the a - v delay timer is triggered and times out , but gate 64 delays the delivery of a pace pulse to the output circuit until the end of the time - out period of timer 60 which is at the 600 millisecond level . at 600 milliseconds following the last ventricular stimulation pulse , the trigger signal is passed through to the output and a further ventricular pulse is delivered . it will be seen that the sixth ventricular pulse in fig5 although more closely coupled to the fifth than the preceding pulses , is still separated by sufficient time to avoid having the pulse fall in the vulnerable period of the heart . thus the problem of closely coupled pulses falling in the vulnerable period is eliminated . since the sixth ventricular stimulation pulse shown in fig5 was the result of triggering through the atrial path , flip flop 71 is reset and the normal upper rate limit of 175 bpm - 343 ms is restored . in the final heartbeat cycle shown in fig5 atrail synchrony is regained and the ventricular stimulation pulse is delivered in synchrony following detection of the p - wave , and the shorter upper rate timer time - out period is applicable . with the upper rate timer in its normal program mode , the pacemaker is ready to track p - waves of the heart at a high rate up to the programmed limit , while still being capable of switching to the lower upper rate limit in the event of ventricular backup pacing , in order to prevent closely coupled ventricular pulses from falling in the vulnerable period of the heart .
an improved atrial synchronous pacemaker and control circuit therefor having a minimum ventricular rate backup mode includes circuitry for preventing occurrence of a closely coupled ventricular pulse which might otherwise occur during the vulnerable repolarization period of the ventricles . a triggering coupling circuit includes a variable or programmable upper rate limit / minimum escape interval timer and switching means therefor for switching to a relatively low maximum rate / minimum escape interval condition while pacing in the ventricular backup mode , and for switching to a higher programmed maximum rate / minimum escape interval limit value while pacing in atrial synchronous mode .