The acronym RISC -LRB- pronounced as risk -RRB- , for reduced instruction set computer , represents a CPU design strategy emphasizing the insight that simplified instructions that `` do less '' may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly .

A reduced instruction set computing -LRB- acronym RISC pronounced risk -RRB- , represents a CPU design method to simplify instructions which `` do less '' but provide higher performance by making instructions execute very fast .
