For this reason , a read miss in a write-back cache -LRB- which requires a block to be replaced by another -RRB- will often require two memory accesses to service : one to retrieve the needed datum , and one to write replaced data from the cache to the store .

A miss in a write-back cache -LRB- which requires a block to be replaced by another -RRB- will often need two memory accesses : one to get the needed datum , and another to write replaced data from the cache to the store .
