Limitations Available performance improvement from superscalar techniques is limited by two key areas : The degree of intrinsic parallelism in the instruction stream , i.e. limited amount of instruction-level parallelism , and The complexity and time cost of the dispatcher and associated dependency checking logic .

Limitations Available performance improvement in MISC@1 design is limited by two key areas : The degree of intrinsic parallelism in the instruction stream , i.e. limited amount of instruction-level parallelism . The complexity and time cost of the dispatcher and associated dependency checking logic .
