While pipelining can in theory increase performance over an unpipelined core by a factor of the number of stages -LRB- assuming the clock frequency also scales with the number of stages -RRB- , in reality , most code does not allow for ideal execution .

Pipelining in theory increases performance over an un-pipelined core by a factor of the number of stages -LRB- assuming the clock frequency also increases by the same factor -RRB- and the code is ideal for pipeline execution .
