# Applying negative voltage to CMOS chips

I have a situation where it's possible a negative voltage may appear on the power supply rails driving CMOS chips. The negative voltage will be very limited in current, fed through a resistor.

The datasheets of course specify that Vdd should not go below ground by more than 0.3V.

Now of course, if you take the supply negative then the parasitic transistors and diodes begin to conduct - clamping the supply to 0.3-0.7V anyway.

My question is: how much negative current on the supply rails can a CMOS IC be expected to handle without failing or degrading? Would it be in the same sort of order as the clamping diode current for I/O pins (20mA)?

If it can't handle any significant negative current at all, then I'll have to install a schottky diode reverse across the power supply to clamp it below 0.3V.

I have seen numerous designs where there are ordinary silicon diodes across the power supply to protect against reverse bias. This seems to be pointless, since the datasheet says not to exceed 0.3V - not 0.65V. Surely the parasitic structures will conduct before the external silicon diode.

• You will have a short of the body diodes. To avoid any trace in the chip to be damaged, you had to limit the current to that of the weakest output. Maybe possible for CMOS chips with a few gates, impractical for any higher integrated chip. – Janka Feb 23 '18 at 21:22
• The datasheet's Absolute Maximum Ratings should specify this damage limit, but maybe it's implied by a power limit rather than stated as a current. Can you edit to add link to the datasheet? – MarkU Feb 23 '18 at 21:40
• @Foxie: Just to be clear: are you saying that the chip positive supply sometimes dips below the negative supply? – Transistor Feb 23 '18 at 23:30
• Yes, that's right. There's a split supply and some resistance between the positive rail and the negative rail. The negative rail could have power without the positive rail being powered, hence dragging the positive rail below ground weakly. – Foxie Feb 23 '18 at 23:42
• Regarding the datasheet, it doesn't say anything at all about taking the supply negative - only that the supply cannot go below -0.3V. It does specify the clamp current at 20mA maximum, but this is for I/O pins - not necessarily the supply. The datasheet for one of the ICs is here: ww1.microchip.com/downloads/en/DeviceDoc/40001844D.pdf – Foxie Feb 23 '18 at 23:44

In order to have EOS protection diodes faster than the FET they are protecting they must be small and ESR , Imax, Pd are all related and inverse to speed.

These designed to protect against shoot-thru parasitic SCR effects in CMOS.

simulate this circuit – Schematic created using CircuitLab

Thus they use 2 diodes for each rail with 10k between them to make a better clamp and often specify not to exceed 5mA. If you cannot guarantee this then you must add more Schottky or TVS diode protection.

Faster logic may have even lower DC current limits. TI says 2mA www.ti.com/lit/an/slaa689/slaa689.pdf

• "EOS pro..." => ESD protection diodes I think ? – Bimpelrekkie Feb 23 '18 at 21:43
• rs-online.com/designspark/the-difference-between-eos-and-esd I've been using EOS for 40 yrs but often say ESD like everyone still says PCB – Sunnyskyguy EE75 Feb 23 '18 at 21:47
• Your bottom diodes are upside-down. 'Internal' can't go above $V_f$. – Transistor Feb 23 '18 at 21:49
• of course, touch pad editor is such a PITA – Sunnyskyguy EE75 Feb 23 '18 at 21:51
• Are these ESD diodes the only structures which will conduct in reverse? I was under the impression there were many more structures, some of which will conduct with only one diode drop rather than two. If it's two diode drops then a single silicon diode across the supply will provide protection - but if it's one drop (hinted at by the datasheet's -0.3V minimum supply) a schottky will need to be used. – Foxie Feb 23 '18 at 23:45