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single electron tunneling ( set ) devices@xcite are promising candidates for a wide variety of nanoelectronics applications , such as sensitive electrometers@xcite , thermometers@xcite , electron pumps and turnstiles for current standards@xcite , and quantum bits for quantum information processing@xcite . in recent years , silicon has drawn a lot of attention as a candidate for practical set devices for several reasons . these advantages include compatibility with complementary metal  oxide  semiconductor ( cmos ) processing , good electrostatic control of the tunnel barriers@xcite , greater device stability as demonstrated by a lack of charge offset drift@xcite , and a relative lack of nuclear spins , an important source of decoherence in spin - based quantum information applications@xcite . however , to become truly viable in any of these applications , devices must be fabricated which overcome the device to device variations and low yield associated with the single device processing typical of small  scale research programs . although , at the single device level , the gate voltage variation from one device to another may not be an important parameter , uniform device operation becomes crucial when trying to operate several set devices simultaneously , e.g. , in the large scale integration of set devices . the choice of device architecture can also impact the integrability of devices . for example , gate to gate variations in an architecture where more than one gate@xcite controls a single tunnel barrier can make finding the desired operating point a laborious iterative process .    in this paper we demonstrate robust behavior and good unformity of easily - tuned , fully cmos single electron devices , which contain only silicon , thermally  grown silicon dioxide ( sio@xmath3 ) and phorphorous  doped polycrystalline silicon ( poly  si ) in the active device region . the motivation for a fully cmos approach to fabrication is twofold : 1 ) to minimize the number of impurities and defects near the active device region and 2 ) to avoid the instabilities associated with metallic oxides and , in particular , aluminum oxide . in this way , we avail ourselves of the best opportunity to fabricate uniform , robust devices . below , we will discuss and demonstrate the robustness of our devices with respect to basic metal  oxide  semiconductor field effect transistor ( mosfet ) characteristics and set device operation . in particular , we show that these devices exhibit only small variations of the threshold voltage from device to device , dielectrics which are robust against breakdown , and charge offset stability of the order of 0.01 e over a period of several days . ( color online ) ( a ) a schematic view of a sample . device operation is described in the text . ( b ) left : an optical micrograph of a sample . right : an sem micrograph ( before upper gate deposition ) of the active device area , and schematics of an electrical measurement circuit ( does not show v@xmath4 ) . lower gates lgs , lgc and lgd are poly si and the conducting channel ( s / d ) is single crystal si . channel and lower gates sit on top of the buried silicon oxide ( box ) . the white arrow next to the finger gate indicates the dimension we call gate length . ( c ) a cross  sectional sem image of a device along the dashed white line in ( b ) . the darker areas are si , the gray areas are sio@xmath5 and the bright layer on top is a protective layer of pt deposited prior to the fib cut . ] flow chart of the condensed fabrication process described in the text . ] our devices each contain a lightly boron  doped ( p  type ) mesa  etched single crystal si nanowire , n@xmath6type source and drain , and two layers of gates ; see fig . [ sample ] ( a ) . the topmost gate layer , which we call the upper gate ( ug ) , covers the entire device between the heavily doped source and drain . applying a positive voltage to the upper gate inverts the underlying si nanowire and provides conduction . the second gate layer , which we call the lower gates ( lg ) , consists of three finger gates which wrap around the si nanowire . these are denoted as lgs ( closest to the source ) , lgc ( center gate ) and lgd ( closest to the drain ) ; see fig . [ sample ] ( b ) . the lower gate fingers are primarily used to locally deplete the electron gas and therefore to create electrostatically controlled tunnel barriers ( lgs and lgd ) , or to modulate the electrostatic potential of a quantum dot ( lgc ) . the devices are fabricated on a 6 inch silicon  on  insulator ( soi ) wafer , with doping density of about 10@xmath7 @xmath8 , an initial soi thickness of 100 nm , and a buried oxide ( box ) thickness of 200 nm . to minimize the interface trap density at the gate oxide interface of the nanowire@xcite , we fabricate the soi nanowires at a 45@xmath9 angle with respect to the flat ( @xmath10110@xmath11 ) of the wafer in order to obtain a @xmath10100@xmath11 crystallographic equivalent orientation on each facet of the nanowire . as previously mentioned , we fabricate these devices with a fully cmos process flow developed at the center for nanoscale science and technology ( cnst ) nanofabrication user facility at nist . the fabrication process is presented in fig . [ fabflowchart ] . the nanowire , lower gate and upper gate lithography and etching are performed with negative tone electron beam lithography ( ebl ) using hydrogen silsesquioxane ( hsq ) as a resist and dry etching in cl@xmath3 chemistry . source and drain areas located about 10 @xmath12 m away from the active device area are implanted with phosphorous at 30 kev with a dose of 10@xmath7 @xmath13 . we grow sacrificial oxide on both the nanowire and the lower gate layer in order to remove possible etch damage produced during the dry etch . both sacrificial oxide and the gate oxide on the nanowire are grown in a tube furnace at 850 @xmath9c and 950 @xmath9c , respectively . the sacrificial oxide is removed with a short 100:1 hf dip . the lower and upper gate layers are 75 nm thick _ in situ _ phosphorous  doped poly si deposited by low pressure chemical vapor deposition ( lpcvd ) at 625 @xmath9c . both gate layers are degenerately doped to ensure electrical conduction at low temperatures with a typical resistivity of 1030 m@xmath14 cm ( determined from two terminal measurement at 2.2 k ) . the sacrificial oxide on the lower gate and the isolation oxide between the lower gate and the upper gate are grown with rapid thermal oxidation ( rto ) at 1000 @xmath9c . the final steps of the process are metallization of ohmic contacts with sputter deposited al1%si and a forming gas anneal at 425 @xmath9c for 30 min .    to date , we have fabricated devices on two 6 inch wafers which we call a and b@xcite ; see fig . [ fabflowchart ] . the main differences between the wafers are the nominal gate oxide thickness and the finger gate lengths . the soi nanowire width and length are 70 nm and 800 nm respectively for both wafers . each wafer contained 48 dies : 36 with two devices as in fig . [ sample ] on each and 12 diagnostics dies located on the diagonals of the wafer . the diagnostics dies contained conventional field effect transistors ( fet ) with a 70 nm wide soi nanowire as a channel , and test structures to measure the resistance of ohmic contacts and the resistivity of the poly si .    a cross - sectional sem image produced by a focused ion beam ( fib ) cut along the lgc finger ( white dashed line in fig . [ sample](b ) ) of a finished device is shown in fig [ sample](c ) . the darker areas in the micrograph are si and the gray areas are sio@xmath5 . the cross  sectional image shows that both poly  si films of upper gate and lower gate layers conformally coat the layers underneath as is expected from lpcvd growth , and that the oxides are continuous , as needed for electrical isolation . we characterized many devices and fets from randomly chosen dies across both wafers at room temperature and at 2.2 k. in addition , one of the devices was cooled down and measured in a dilution refrigerator to 30 mk . the summary of the electrical characterization is presented in table [ samplesummary ] . figure [ 3gchar ] ( a ) shows turn  on characteristics of different devices ( as in fig . [ sample ] ) on wafer a ( 40 nm gate oxide ) . the solid lines and dashed lines correspond to data taken at 300 k and 2.2 k , respectively . at room temperature the threshold voltages , as obtained by linearly extrapolating the current to zero@xcite , were @xmath15 v with the standard deviation of 0.1 v and there was a threshold shift of about 0.6 v when devices were cooled down . a simple estimate of the threshold voltage@xcite which ignores the presence of any fixed oxide charge and which treats the devices as planar fets yields @xmath16 v at room temperature and @xmath17 v at 2.2 k , which is in reasonable agreement with our measured values . wafer b ( 25 nm gate oxide ) showed uniform turn  on characteristics with @xmath18 v at room temperature and a nearly equal shift in the threshold when cooled down . the diagnostic transistors on each wafer also showed similar turn  on behavior . a typical subthreshold slope for these devices was 80 mv / decade at room temperature ( the ideal subthreshold slope is 60 mv / decade@xcite ) with an on  off ratio of 10@xmath19 , see inset in fig . [ 3gchar ] ( a ) . typical turn  off characteristics for each of the finger gates ( lgs , lgc and lgd ) measured at both room temperature and 2.2 k for wafer b are shown in fig . [ 3gchar ] ( b ) . the room temperature data was taken with an upper gate voltage @xmath20 v , while the low temperature data was taken with @xmath21 v. the range for turn  off voltages , i.e. the lower gate voltage @xmath22 at 100 pa of drain current @xmath23 , was from -1.5 v to -1 v at room temperature and -1 v to -0.5 v at 2.2 k for all measured lower gates for all devices . ( color online ) turn  on characteristics , i.e. drain current as a function of gate voltage of a mosfet transistor with 25 nm gate oxide thickness . data was taken with the drain voltage @xmath24 of 1 mv . solid ( black ) line is initial turn  on curve , dashed ( red , gray ) line is turn  on curve after @xmath2510 v ( 4 mv / cm ) excursion in the gate voltage . the indentical curves indicate immunity to dielectric breakdown up to @xmath254 mv / cm . ] we also tested the robustness of the gate oxide and the isolation oxide on wafer b. in these tests , the gate voltage was swept in steps up to @xmath2510 v while the source - drain and leakage currents were simultaneously measured to the other gates and to the channel . all leakage resistances between the channel and either layer of gates or between gates were @xmath1110 g@xmath1 up to gate voltages of @xmath2510 v. after each gate voltage excursion , the turn  on characteristics were remeasured in order to determine if there was a change in the threshold voltage or slope . diagnostic fets were immune to electric fields up to 4 mv / cm ( @xmath26 v ) , showing no change in @xmath27 nor generation of a leakage path ( fig . [ transistor ] ) . similar robustness measurements for set devices showed no threshold shift up to 2.8 mv / cm ( @xmath257 v ) and only a small ( 0.05 v and 0.2 v ) threshold shift after a gate excursion of 4 mv / cm ( @xmath2510 v ) in two out of four devices . no observable leakage path developed during the sweep . a typical literature value of the breakdown field of metal  oxide  semiconductor capacitor ( moscap ) is about 10 mv / cm , before generating a leakage path@xcite . we also performed robustness measurements of the isolation oxide between lg and ug on about 50 different lower gate fingers on different devices across the wafer . only three fingers developed a breakdown path during the @xmath2510 v sweep .    [ cols="^,^,^,^,^",options="header " , ]     ( color online ) set oscillations of a device at 2.2 k , vertical dashed lines ( red , gray ) are separated by a period of 12.9 mv . the data show good uniformity of the gate capacitance over 90 periods . ] ( color online ) coulomb diamonds measured at 30 mk for an set device , n is the electron number . charging energy @xmath281.2 mev , drain capacitance @xmath29=7 af and total capacitance of the island @xmath30=70 af , extracted from the diamond data . ] above , we have discussed the robustness and uniformity of devices in terms of mosfet performance , and in the following we present device characteristics when operated in a single electron device mode . first , we discuss ease of tuning . the right hand side of fig . [ sample ] ( b ) shows a schematic of a typical measurement circuit for a device . tuning the device to display set oscillations took very little time , on the order of minutes , because there was very little cross capacitance between gates and each barrier was controlled by a single gate voltage . to tune a device into set mode , we first applied a small bias voltage to the drain ( of order 1 mv ) and set the upper gate to a voltage ( obtained from a short upper gate sweep , typically about 2 v ) which gave about 1 na of current . next , a two dimensional sweep of @xmath31 and @xmath32 ( with @xmath33 well above the turn  off voltage ) was performed to find the voltages where each of these gates began to turn off conduction . typically , the barrier voltages were about -0.6 v. we note that barrier resistances responded symmetrically to @xmath31 and @xmath32 . after fine tuning @xmath31 and @xmath32 , we measured set oscillations by sweeping @xmath33 with the other gate voltages fixed . coulomb oscillations of a device taken at 2.2 k are presented in fig . [ setosc ] . the oscillations were very regular with period of 12.9 mv over an lgc gate voltage range of 1.2 v , corresponding to about 90 periods . the capacitance of lgc to the dot , extracted from the set oscillation period , was about 12 af . coulomb diamond data recorded at 30 mk for the same device is shown in fig . [ diamonds ] . the charging energy and lever arm @xmath34 , which converts the gate voltage to the electrostatic potential of the island @xmath35 , extracted from the diamond data were 1.2 mev and 0.09 , respectively . the capacitance between the dot and each of the other two lower gates ( lgs and lgd ) was measured relative to the lgc capacitance by following the position of a current peak when sweeping lgs ( or lgd ) and lgc ( data not shown ) . the capacitance values for both lgs and lgd were about 5 af , indicating the dot was located in the center of the device . this , together with the agreement between the measured capacitance to lgc ( 12 af ) and that calculated from the geometry ( 14 af ) gives us confidence that the dot being modulated was an intentional dot formed through electrostatic control of lgs and lgd rather than through barriers formed by defects .    as a more strict test of the quality of our fabrication we performed charge offset drift measurements on several devices . this measurement consisted of repeatedly measured coulomb blockade oscillations at a fixed time interval over several days . figure [ cbdata ] ( a ) shows a typical collection of set oscillations taken at 2.2 k and spanning the total duration of the charge offset drift measurement . to obtain charge offset drift values for each curve , a sinusoidal function of the form @xmath36 $ ] was fit to the measured data . here @xmath37 is the amplitude of the oscillations , @xmath38 is the gate voltage and @xmath39 the oscillation period . the phase of the sinusoidal fit function , @xmath40 , is a charge offset value for each curve . the result of this procedure is shown in fig . [ cbdata ] ( b ) . the devices exhibited very stable behavior with a drift in @xmath41 e over 8 days of measurement . moreover , these results rival those of similar si devices fabricated in other foundries@xcite . in addition , after eight days of measurement , we thermally cycled the device to room temperature . figure [ cbdata ] shows this data as well . while the thermal cycle resulted in a shift in the charge offset value of about ( 0.1@xmath42 ) e , the level of drift observed was identical both before and after the thermal cycle . finally , a measurement of @xmath43 vs. @xmath33 voltage with the same lgs , lgd , and ug voltages after the thermal cycle not only reproduced the set oscillations at the same value @xmath33 with charge offset of 0.1 e , but also reproduced the aperiodic features which become prominent when the gate begins to turn off conduction ( inset of fig . [ cbdata ] ) .    while the previous results indicate that the cleanliness of our cmos fabrication is quite good , many devices in this first device run failed electrically by either not turning on or through an inability to turn off conduction with the lower gate fingers . this drove our yield of fully functioning ( in which we were able to measure intentional coulomb blockade ) devices down to 4/34 devices measured . we have been able to identify the gross fabrication failures , by cross - sectioning devices with fib in conjunction with the electrical results . in brief , the failure modes are the result of over  oxidation of the soi nanowire and the lg fingers , as well as the overall amount of oxide removed in the processing . we believe further development of our process flow will ameliorate these failures . ( color online ) ( a ) an example of single electron oscillations taken at different times with interval of about 3 hours ; curves are offset vertically for clarity . ( b ) charge offset drift derived from coulomb oscillations , red and blue ( gray ) dashed horizontal lines are a guide for the eye . the gray area indicates the time interval of the thermal cycle . after the thermal cycle the charge offset value @xmath40 changed by 0.1 e , but remained as stable as before . inset : drain current as a function of lgc voltage @xmath44 before ( black line ) and after ( red , gray line ) the thermal cycle . the data in the inset before and after the thermal cycle are taken with the same gate voltages . all features in the data are reproduced after the thermal cycle . ] in summary , we have demonstrated devices which show good uniformity in electrical characteristics from device to device within a wafer and between wafers . moreover , the devices are quite robust against dielectric breakdown up to electric fields of 4 mv / cm . finally , and most importantly , when operated as a single electron device , these devices show very stable behavior . taken together , these characteristics indicate a relatively clean and stable electrostatic environment throughout the fabrication process . we attribute these successes to the minimization of impurities and defects which result from our cmos processing and material restrictions . to further improve the usefulness of these devices as current standards and quantum information devices , our next tasks include i ) substantially increasing the yield , and ii ) making shorter finger gates so that we can use those gates to both generate barriers and as plunger gates . while these results indicate that a fully cmos process pays dividends in device performance , it also complicates the fabrication . we believe that our results in terms of reliability , ease of tuning , and clean set behavior all justify the cost of the increased complexity of fabrication . we thank ted thorbeck , john bonevich , jerry bowser , and vincent luciani for fruitful discussions . we also thank jerry bowser and vincent luciani for guidance with the fabrication . research was performed in part at the nist center for nanoscale science and technology ( cnst ) . 20ifxundefined [ 1 ] ifx#1 ifnum [ 1 ] # 1firstoftwo secondoftwo ifx [ 1 ] # 1firstoftwo secondoftwo `` `` # 1''''@noop [ 0]secondoftwosanitize@url [ 0 ]  + 12$12  & 12#1212_12%12@startlink[1]@endlink[0]@bib@innerbibempty @noop _ _ , ( ,  ,  ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop * * ,   ( ) @noop _ _  ( ,  ,  ) @noop _ _  ( ,  ,  ) @noop * * ,   ( )
we present electrical data of silicon single electron devices fabricated with cmos techniques and protocols . 
 the easily tuned devices show clean coulomb diamonds at @xmath0 mk and charge offset drift of 0.01 e over eight days . 
 in addition , the devices exhibit robust transistor characteristics including uniformity within about 0.5 v in the threshold voltage , gate resistances greater than 10 g@xmath1 , and immunity to dielectric breakdown in electric fields as high as @xmath2 mv / cm . these results highlight the benefits in device performance of a fully cmos process for single electron device fabrication .