static void nec_interrupt(int int_num, int md_flag) {
        int dest_seg, dest_off;
        if (neclog != null) {
            fprintf(neclog, "nec_interrupt_b :PC:%d,I.ip:%d,AW:%d,CW:%d,DW:%d,BW:%d,SP:%d,BP:%d,IX:%d,IY:%d,b1:%d,b2:%d,b3:%d,b4:%d,s1:%d,s2:%d,s3:%d,s4:%d,A:%d,O:%d,S:%d,Z:%d,C:%d,P:%d,T:%d,I:%d,D:%d,M:%d,v:%d,irq:%d,ns:%d,is:%d,pb:%d,pre:%d,EA:%d\n", cpu_get_pc(), I.ip, I.regs.w[AW], I.regs.w[CW], I.regs.w[DW], I.regs.w[BW], I.regs.w[SP], I.regs.w[BP], I.regs.w[IX], I.regs.w[IY], I.base[0], I.base[1], I.base[2], I.base[3], I.sregs[0], I.sregs[1], I.sregs[2], I.sregs[3], I.AuxVal, I.OverVal, I.SignVal, I.ZeroVal, I.CarryVal, I.ParityVal, I.TF, I.IF, I.DF, I.MF, I.int_vector, I.pending_irq, I.nmi_state, I.irq_state, I.prefix_base, I.seg_prefix, EA);
        }
        i_pushf.handler();
        I.TF = I.IF = 0;
        if (md_flag != 0) {
            SetMD(0);	/* clear Mode-flag = start 8080 emulation mode */

        }

        if (int_num == -1) {
            int_num = (I.irq_callback).handler(0);
            //		if (errorlog) fprintf(errorlog," (indirect ->%02d) ",int_num);
        }

        dest_off = ReadWord(int_num * 4);
        dest_seg = ReadWord(int_num * 4 + 2);

        PUSH(I.sregs[CS]);
        PUSH(I.ip);
        I.ip = dest_off & 0xFFFF;
        I.sregs[CS] = dest_seg & 0xFFFF;
        I.base[CS] = SegBase(CS);
        change_pc20((I.base[CS] + I.ip));
        //	if (errorlog)
        //		fprintf(errorlog,"=%06x\n",cpu_get_pc());
        if (neclog != null) {
            fprintf(neclog, "nec_interrupt :PC:%d,I.ip:%d,AW:%d,CW:%d,DW:%d,BW:%d,SP:%d,BP:%d,IX:%d,IY:%d,b1:%d,b2:%d,b3:%d,b4:%d,s1:%d,s2:%d,s3:%d,s4:%d,A:%d,O:%d,S:%d,Z:%d,C:%d,P:%d,T:%d,I:%d,D:%d,M:%d,v:%d,irq:%d,ns:%d,is:%d,pb:%d,pre:%d,EA:%d\n", cpu_get_pc(), I.ip, I.regs.w[AW], I.regs.w[CW], I.regs.w[DW], I.regs.w[BW], I.regs.w[SP], I.regs.w[BP], I.regs.w[IX], I.regs.w[IY], I.base[0], I.base[1], I.base[2], I.base[3], I.sregs[0], I.sregs[1], I.sregs[2], I.sregs[3], I.AuxVal, I.OverVal, I.SignVal, I.ZeroVal, I.CarryVal, I.ParityVal, I.TF, I.IF, I.DF, I.MF, I.int_vector, I.pending_irq, I.nmi_state, I.irq_state, I.prefix_base, I.seg_prefix, EA);
        }
    }