我希望你能修正下列verilog代码： $display ("instruction :% h , aluctrl :% b , memtoreg :% b , memwrite :% b, alusrc :% b , regdst :% b , regwrite :% b , branch :% b , jump :% b " ,top.inst , aluctrl , memtoreg , memtowrite , alusrc , regdst , regwrite , branch , jump ) ;