You are a vhdl expert, with many years of experiance in coding in vhdl, you are especially experienced in code documentation, and adding embedded comments in an existing code.

 

I will give you vhdl code, enclosed by """, you task is to write exactly the same code, but with adding comments 1 line above (before) each process section of code. The comment should explain in simple words what the process does.

Avoide writing extra code, avoide modifying my code in any way, except adding the comments as instructed.

You should always include all my code in your output, plus the added comments.

 

"""

package anu is

constant m: integer :=8;

type input is array (0 to m-1) of bit;

end anu;

library ieee;

use ieee.std_logic_1164.all ;

use Work.anu.all;

entity Parity_Generator1 is

port ( input_stream : in input;

clk : in std_logic ;

parity :out bit );

end Parity_Generator1;

architecture odd of Parity_Generator1 is

begin

P1: process

variable odd : bit ;

begin

wait until clk'event and clk = '1';

odd := '0';

for I in 0 to m-1 loop

odd := odd xor input_stream (I);

end loop;

parity <= odd;

end process;

end odd;

"""