Now can you explain to me the code given below?

module DFF (
  input wire D,  // Data input
  input wire clk,  // Clock input
  input wire reset,  // Reset input
  output reg Q  // Output
);

  always @(posedge clk or posedge reset) begin
    if (reset)
      Q <= 1'b0;  // Reset to 0
    else
      Q <= D;  // Update output with the input value
  end

endmodule