module Transition_Calculator (CLK, Load, Clear, Data, Count)
input CLK,Load,Clear;
input [9:0] Data;
output reg [4:0] Count;
reg prevBit;

always @(posedge CLK or negedge Clear)
begin
if(!Clear)
Count <=0;
else if (Load&&(prevBit!=Data))
Count<=Count+1;
prevBit<=Data[0];
end
end module

for this verilog code i want a testbench code that will try all 1024 data odds A testbench file to simulate and test your design:
a. You have to give a test case for the Asynchronous Clear,
b. You have to cover all the possible cases for the input Data (1024 different cases)
i. For each case you have to:
1. Select a different value for the input Data
2. Set the Load signal to ‘1’
3. Wait for two clock cycles
c. You have to give a test case to show that no change will occur when the Load
signal is ‘0’.