3447
Exploiting inter-processor data sharing for improving behavior of multi-processor SoCs
Software-managed memories are important in realtime embedded environments where execution time predictability is an important requirement. With the proliferation of embedded multi-processor systems, software support for their memories is becoming an attractive research area in real-time embedded computing. One of the critical problems in embedded real-time multi-processor SoCs (system-on-a-chip) is to reduce the number of off-chip references. This is because frequent off-chip references can be very costly from both performance and power perspectives. In this paper, we propose a novel compiler-driven strategy for reducing the number of off-chip references, which is based on cooperation between the processors in the multi-processor architecture. Specifically, in the proposed strategy, the processors cache data in their local memories, under compiler control, on behalf of each other if doing so reduces the number of off-chip references.
17981801
Studying storage-recomputation tradeoffs in memory-constrained embedded processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we witness an unprecedented proliferation of embedded/mobile applications. Most of the environments that execute these applications have severe power, performance, and memory space constraints that need to be accounted for. In particular, memory limitations can present serious challenges to embedded software designers. The current solutions to this problem include sophisticated packaging techniques and code optimizations for effective memory utilization. While the first solution is not scalable, the second one is restricted by intrinsic data dependences in the code that prevent code restructuring. In this paper, we explore an alternate approach for reducing memory space requirements of embedded applications. The idea is to re-compute the result of a code block (potentially multiple times) instead of storing it in memory and performing a memory operation whenever needed. The main benefit of this approach is that it reduces memory space requirements, that is, no memory space is reserved for storing the result of the code block in question.
17088807
Reducing NoC energy consumption through compiler-directed channel voltage scaling
While scalable NoC (Network-on-Chip) based communication architectures have clear advantages over long point-to-point communication channels, their power consumption can be very high. In contrast to most of the existing hardware-based efforts on NoC power optimization, this paper proposes a compiler-directed approach where the compiler decides the appropriate voltage/frequency levels to be used for each communication channel in the NoC. Our approach builds and operates on a novel graph based representation of a parallel program and has been implemented within an optimizing compiler and tested using 12 embedded benchmarks. Our experiments indicate that the proposed approach behaves better - from both performance and power perspectives - than a hardwarebased scheme and the energy savings it achieves are very close to the savings that could be obtained from an optimal, but hypothetical voltage/frequency scaling scheme.
13530819
Exploiting last idle periods of links for network power management
Network power optimization is becoming increasingly important as the sizes of the data manipulated by parallel applications and the complexity of inter-processor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows that these schemes can be effective in certain cases, they share the common drawback of not being able to predict the link active and idle times very accurately. This paper, instead, proposes a compiler-based scheme that determines the last use of communication links at each loop nest and inserts explicit link turn-off calls in the application source. Specifically, for each loop nest, the compiler inserts a turn-off call per communication link. Each turned-off link is reactivated upon the next access to it. We automated this approach within a parallelizing compiler and applied it to eight array-intensive embedded applications.
7347899
Data compression for improving SPM behavior
Scratch-pad memories (SPMs) enable fast access to time-critical data. While prior research studied both static and dynamic SPM management strategies, not being able to keep all hot data (i.e., data with high reuse) in the SPM remains the biggest problem. This paper proposes data compression to increase the number of data blocks that can be kept in the SPM. Our experiments with several embedded applications show that our compression-based SPM management heuristic is very effective and outperforms prior static and dynamic SPM management approaches. We also present an ILP formulation of the problem, and show that the proposed heuristic generates competitive results with those obtained through ILP, while spending much less time in compilation.
2552667
An evaluation of code and data optimizations in the context of disk power reduction
Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute data-intensive applications. While hardware-only approaches (e.g., low-power modes supported by current disks) are successful to a certain extent, one also needs to consider the software side to achieve further energy savings. This paper first demonstrates that conventional data locality oriented code transformations are not sufficient for minimizing disk power consumption. The reason is that these optimizations do not take into account how disk-resident array data are laid out on the disk system, and consequently, fail to increase idle periods of disks, which is the primary metric using which disk power can be reduced. Instead, we propose a disk layout aware application optimization strategy that uses both code restructuring and data layout optimization. Our experimental evaluation with several benchmark codes reveal that the proposed strategy is very successful in reducing disk energy consumption without performing much worse than a pure data locality oriented scheme, as far as execution cycles are concerned. The experiments also show that the benefits coming from our approach increase with the increased number of disks; i.e., it scales very well.
33560656
Clique covering the edges of a locally cobipartite graph
Abstract We prove that a locally cobipartite graph on n vertices contains a family of at most n cliques that cover its edges. This is related to Opsut's conjecture that states the competition number of a locally cobipartite graph is at most two.
13046770
Local leader election, signal strength aware flooding, and routeless routing
We have identified a fundamental operator in wireless networks that we named the local leader election in which the goal is to select a node in a spatially close neighborhood. We present a simple and efficient solution to the local leader election problem by making use of both: (i) implicit synchronization points, commonly observable by all nodes in the same neighborhood, and (ii) the prioritized backoff delay, dependent on the desired probability of each node becoming a leader. We then show that both flooding and routing are instances of the local leader election problem, so our general solution naturally applies. By relating the backoff delay to the signal strength of the received packet, we have designed a variant of flooding named signal strength aware flooding (SSAF) that can improve its efficiency. By using a different metric to derive the backoff delay, we have designed a new generation wireless routing protocol, that we named the routeless routing protocol that possesses several interesting properties.
26340659
Combinatorial properties of mesh of trees
A mesh of trees, which has two favorable properties: small diameter and large bisection, is known as the fastest network when considered in terms of speed. We show that the wide diameter, fault diameter, and Rabin number, which are three generalizations of diameter, of a two dimensional 2/sup n//spl times/2/sup n/ mesh of trees are equal to 5n+1.
40869256
Parallel algorithms for permutation graphs
In this paper, parallel algorithms are presented for solving some problems on permutation graphs. The coloring problem is solved inO(log2n) time usingO(n3/logn) processors on the CREW PRAM, orO(logn) time usingO(n3) processors on the CRCW PRAM. The weighted clique problem, the weighted independent set problem, the cliques cover problem, and the maximal layers problem are all solved with the same complexities. We can also show that the longest common subsequence problem belongs to the class NC.
10538824
Parallel Decomposition of Generalized Series-Parallel Graphs
Generalized series-parallel (GSP) graphs belong to the class of decomposable graphs which can be represented by their decomposition trees. Given a decomposition tree of a GSP graph, there are many graph-theoretic problems which can be solved efficiently. An efficient parallel algorithm for constructing a decomposition tree of a given GSP graph is presented. It takes O(log n) time with C(m, n) processors on a CRCW PRAM, where C(m, n) is the number of processors required to find connected components of a graph with in edges and n vertices in logarithmic time. Based on our algorithmic results, we also derive some properties for GSP graphs, which may be of interest in and of themselves.