2699297
The Interactive Track at INEX 2004
An interactive track was included in INEX for the first time in 2004. The main aim of the track was to study the behaviour of searchers when interacting with components of XML documents. In this paper, we describe the motivation and aims of the track in detail, we outline the methodology and we present some initial findings from the analysis of the results.
188423
Report on the INEX 2004 interactive track
As scientific data repositories, digital libraries and publishers increasingly use the eXtensible Markup Language (XML) for publication and storage interest has arisen in exploiting this formatting for retrieval purposes. XML is attractive because it defines the logical structure of the documents and has the potential to assist IR systems in providing more appropriate results to users, i.e., to return relevant document components (i.e. XML elements) rather than whole documents. In addition, the XML tags often have specific semantics that may be exploited purposefully in IR.
41842092
The Interactive Track at INEX 2005
In its second year, the Interactive Track at INEX focused on addressing some fundamental issues of interactive XML retrieval: is element retrieval useful for searchers, what granularity of elements do searchers find more useful, what applications for element retrieval can be viable in interactive environments, etc.. In addition, the track also expanded by offering an alternative document collection, by including two additional tasks, and by attracting more participating groups: A total of 11 research groups and 119 test persons participated in the three different tasks that were included in the track. In this paper, we describe the main issues that the Interactive Track at INEX 2005 attempts to address and the methodology and tasks that were used in the track.
10349365
Instruction level power analysis and optimization of software
Software constitutes a major component of today's systems, and its role is projected to continue to grow. This motivates the need for analyzing power consumption from the point of view of software-something that circuit and gate level power analysis tools are inadequate for. This paper describes an alternative, measurement based instruction level power analysis approach that provides ran accurate and practical way of quantifying this cost. This technique has been applied to three commercial, architecturally different microprocessors. This paper presents an overview of the salient results of these analyses. The ability to evaluate software in terms of power consumption makes it feasible to develop tools and techniques for low power software. Several ideas in this regard as suggested by the power analysis of the subject microprocessors are also summarized.
45768571
Challenges in code generation for embedded processors
The emergence of integrated circuits in which both the program-ROM and the processor are integrated on a single die initiates a new era of problems for programming language compilers. In such a micro-architecture, code performance, and particularly code density, gain an unprecedented level of importance and new code-optimization algorithms will be required to supply the required code quality. This paper presents the first wave of a variety of new code-optimization approaches aimed at supplying the highest code quality possible.
70202123
The Quest for Efficient Boolean Satisfiability Solvers
The classical NP-complete problem of Boolean Satisfiability (SAT) has seen much interest in not just the theoretical computer science community, but also in areas where practical solutions to this problem enable significant practical applications. Since the first development of the basic search based algorithm proposed by Davis, Putnam, Logemann and Loveland (DPLL) about forty years ago, this area has seen active research effort with many interesting contributions that have culminated in state-of-the-art SAT solvers today being able to handle problem instances with thousands, and in same cases even millions, of variables. In this paper we examine some of the main ideas along this passage that have led to our current capabilities. Given the depth of the literature in this field, it is impossible to do this in any comprehensive way; rather we focus on techniques with consistent demonstrated efficiency in available solvers. For the most part, we focus on techniques within the basic DPLL search framework, but also briefly describe other approaches and look at some possible future research directions.
18122829
Verification of asynchronous interface circuits with bounded wire delays
We address the problem of verifying that the gatelevel implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table, under the fundamental mode of operation. We ive a procedure to extract the complete set of possi % le flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence.