15447025
A Speculative Coherence Scheme using Decoupling Synchronization for Multiprocessor Systems
This paper proposes a new speculative coherencescheme, SCDS, for hardware distributed shared memory systemsto reduce the overhead of coherence action in directory-basedcache-coherence protocol. SCDS has two main features,predicting accurate timing of speculative coherence withsynchronization information and detecting write pattern(migratory and non-migratory) for exclusive blocks' speculativecoherence action. In our simulation, SCDS outperforms existingschemes (DSI and LTP) for well-synchronized applications.
14450756
How to Design Optimistic Operations for Peer-to-Peer Replication
As collaboration over the Internet becomes an everyday affair, it is increasingly important to provide high quality of interactivity. Distributed applications can replicate collaborative objects at every site for the purpose of achieving high interactivity. Replication, however, has a fatal weakness that it is difficult to maintain consistency among replicas. This paper introduces operation commutativity as a key principle in designing operations in order to manage distributed replicas consistent. In addition, we suggest effective schemes that make operations commutative using the relations of objects and operations. Finally, we apply our approaches to some simple replicated abstract data types, and achieve their consistency without serialization and locking.
43495365
A scalable cache coherent architecture for large-scale mesh-connected multiprocessors
Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data, however, most protocols suffer from extraneous cache invalidates or updates due to insufficient pointers. We focus on large-scale mesh-connected multiprocessors built on top of wormhole and dimension ordered routing networks. In such networks, worms are major bricks for communications, which transit all the intermediate nodes on their way to a destination. From such an observation, we propose a new directory-based protocol DirQ with limited pointers, which can represent either one node or a set of nodes when being widely shared. For /spl radic/N/spl times//spl radic/N processors system, our protocol needs /spl Theta/(N/sup 3/2/ log N) bits for directory memory which is much more scalable compared to the full-map protocol. In terms of latency and traffic volume for cache coherence, our analytic models show that DirQ outperforms other limited protocols, and further comparable to the full-map one.
346657
A Virtual-Physical On-Chip Cache for Shared Memory Multiprocessors
5993695
Correlation Prefetching with a User-Level Memory Thread
This paper proposes using a user-level memory thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: The correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide applicability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
17186964
A Ubiquitous Fashionable Computer with an i-Throw Device on a Location-Based Service Environment
The ubiquitous fashionable computer (UFC), introduced in this paper, is a wearable computer that allows people to exploit ubiquitous computing environment in a user-friendly manner. We present the design approach and philosophy of the UFC that is wearable, aesthetic, and intuitive. The UFC supports the interoperability of various communication interfaces among WLAN, Bluetooth and ZigBee devices. We developed a wireless gesture recognition device, called i -Throw, which is small enough to be worn on one's finger like a ring. The UFC, with the help of i -Throw, can control ubiquitous environment using an intuitive hand motion. To explain the practical use of the UFC platform and the user-friendly interaction with ubiquitous environment, we implemented a ubiquitous testbed where multiple UFC users interact with various ubiquitous devices or other UFC users. In addition, we implemented a practical application which makes it possible to exchange the various objects and control ubiquitous devices very easily.
7307952
Optimal variable-density k-space sampling in MRI
Magnetic resonance imaging (MRI) is often times limited by scan time. To reduce scan time, there have been various efforts to reduce the number of sampling points. In most cases, this is done by utilizing a priori knowledge of the signal of interest. In this paper, we propose an algorithm that will guide the determination of an optimal sampling pattern based on prior knowledge of the signal. Applications of this method include optimal variable-density k-space trajectory design or reduced phase encoding in 3DFT and spectroscopy. Preliminary results are shown as a proof of concept.
275005
Using a user-level memory thread for correlation prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide usability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
623251
Isomorphism classes of bipartite cycle permutation graphs