384064
Proximity based access control in smart-emergency departments
In this paper, we propose a proximity based automated access control (PBAC) model for smart-ED environments which improves the existing ED work-flow by automating mundane administrative procedure for secure information access, allowing caregivers to focus on the treatment of patients. The proposed access model builds on the traditional role-based access control model and extends it by including multiple authentication levels for preventing unauthorized access. We also provide a semi-formal specification for the PBAC model. We further validate it using ultra-wide-band (UWB) based prototype which was tested in ED
2580676
Adaptive Distributed Dynamic Channel Allocation for Wireless Networks
Channel allocation schemes in a mobile computing (wireless) environment can be either static or dynamic. Static allocation offers negligible channel acquisition time and zero message complexity and works well at a low system load; the performance steadily decreases as system load increases since many calls are dropped. In the case of even temporary hot spots many calls may be dropped by a heavily loaded switching station even when there are enough idle channels in the interference region of that station. On the other hand, dynamic schemes provide better utilization of the channels at higher loads albeit at the cost of higher channel acquisition time and some additional control messages. Our purpose in the present paper is to propose a combined channel allocation scheme so that each switching station can tune to its own load independent of other stations in its interference region; the objective is to minimize the call drop rate and at the same time maintain a minimum average channel acquisition time and minimum control message complexity.
12873659
TARA: Thermal-Aware Routing Algorithm for Implanted Sensor Networks
Implanted biological sensors are a special class of wireless sensor networks that are used in-vivo for various medical applications. One of the major challenges of continuous in-vivo sensing is the heat generated by the implanted sensors due to communication radiation and circuitry power consumption. This paper addresses the issues of routing in implanted sensor networks. We propose a thermal-aware routing protocol that routes the data away from high temperature areas (hot spots). With this protocol each node estimates temperature change of its neighbors and routes packets around the hot spot area by a withdraw strategy. The proposed protocol can achieve a better balance of temperature rise and only experience a modest increased delay compared with shortest hop, but thermal-awareness also indicates the capability of load balance, which leads to less packet loss in high load situations.
1274772
Supporting persistent social groups in ubiquitous computing environments using context-aware ephemeral group service
We analyze the role of the social group in a ubiquitous computing (Ubicomp) environment as a source of contextual information. A model is presented to address the social group member's perceptions of how devices in a ubicomp environment should aid them in collaboration. Based on the model a distributed context-aware group membership management scheme is developed. We then present a prototype implementation for a context-aware ephemeral group membership management scheme, along with a sample application, and experimental results that demonstrate the feasibility of our system.
12878004
Criticality aware access control model for pervasive applications
Access control policies define the rules for accessing system resources. Traditionally, these are designed to take a reactive view for providing access, based on explicit user request. This methodology may not be sufficient in the case of critical events (emergencies) where automatic and timely access to resources may be required to facilitate corrective actions. This paper introduces the novel concept of criticality which measures the level of responsiveness for taking such actions. The paper further incorporates criticality in an access control framework for facilitating the management of critical situations. Specific properties and requirements for such criticality aware access control are identified and a sample model is provided along with its verification
14536242
On maximizing lifetime of multicast trees in wireless ad hoc networks
We present a distributed algorithm called L-REMiTfor extending the lifetime of a source-based multicast tree in wireless ad hoc networks (WANET). The lifetime of a multicast tree is the duration from the formation of the tree to the time when the first node fails due to battery energy exhaustion. L-REMiT assumes that the energy consumed to forward a packet is proportional to the forwarding distance and that WANET nodes can dynamically adjust their transmission power. The task of extending the lifetime of a multicast tree is formulated as the task of extending the lifetime of bottleneck nodes in the tree. The number of multicast packets which a bottleneck node can forward, as determined by its residual battery energy and the distance of its farthest child node, is minimum over all the nodes in the multicast tree. Lifetime of a bottleneck node is improved by reassigning its farthest children to other nodes in the tree with the goal of improving the lifetime of the multicast tree. Nodes only require information from their neighbors for refining the tree in a distributed manner. Simulation results show that L-REMiT has low overhead and performs better than BIP/MIP and EWMA algorithms
1246119
Interface synthesis using memory mapping for an FPGA platform
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.
2619259
A new gate delay model for simultaneous switching and its applications
<par.We present a new model to capture the delay phenomena associ-ated with simultaneous to-controlling transitions. The proposed delay model accurately captures the effect of the targeted delay phe-nomena over a wide range of transition times and skews. It also cap-tures the effects of more variables than table lookup methods can handle. The model helps improve the accuracy of static timing anal-ysis, incremental timing refinement, and timing-based ATPG.
40067645
A BIST methodology for comprehensive testing of RAM with reduced heat dissipation
The severity of excessive heat dissipation during concurrent BIST of memory modules has been documented previously (1993). In this paper, the authors present new versions of several memory tests that reduce heat dissipation during testing. Each proposed test has the same fault coverage and time complexity as the original version but it reduces heat dissipation by a factor of two or more. For three of the tests, the heat dissipation is reduced by factors of four to sixteen. The design of BIST circuitry required to implement the proposed tests are presented and it is shown that additional area overhead incurred is very small.
62707609
BIST TPG for faults in system backplanes
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems change frequently, at the system level, the proposed methodology employs a simple test schedule which can be easily changed whenever the system configuration is changed. Since the boards used in such systems are designed for use in a wide variety of systems, the proposed methodology defines the test objectives to be achieved by a board's BIST circuit in terms of the board's edge pin connections, independent of the configurations of the systems in which the board may be used. It is shown that the combination of the proposed test schedule and the availability, on each board in the system, of any BIST circuit that satisfies the proposed test objectives, guarantees safe testing of faults in backplanes. A programmable test architecture and an algorithm to program the architecture to obtain BIST that satisfies the test objectives is also presented. Finally, the applicability and effectiveness of the methodology is demonstrated via its application to multiple configurations of an example system that uses a VME backplane.
39657490
Aliasing Probability for Multiple Input Signature Analyzer
Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q-ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q-ary codes (q=2/sup m/, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given. >