35656281
A generalization of Fan's condition for Hamiltonicity, pancyclicity, and Hamiltonian connectedness
Abstract A weakened version of Fan's condition for Hamiltonicity is shown to be sufficient for a 2-connected graph to be pancyclic (with a few exceptions). Also, a similar condition is shown to be sufficient for a 3-connected graph to be Hamiltonian-connected. These results generalize the earlier work of Benhocine and Wodja (1987).
3811952
Degree Sequences with Repeated Values
A given nonincreasing sequence D = (d1, d2, · · · , dn) is said to contain a (nonincreasing) repetition sequence D∗ = (di1 , di2 , · · · , dik ) for some k ≤ n − 2 if all values of D −D∗ are distinct and for any dil ∈ D ∗ there exists some dt ∈ D −D∗ such that dil = dt. For any pair of integers n and k with n ≥ k + 2, we investigate the existence of a graphic sequence which contains a given repetition sequence. Our main theorem contains the known results for the special case di1 = dik if k = 1 or k = 2 (see [1, 5, 2]). 1supported in part by a foundation of Academia Sinica.
9764979
Tough enough chordal graphs are Hamiltonian
3744350
Hamiltonian graphs involving neighborhood unions
Dirac proved that a graph G is hamiltonian if the minimum degree δ(G) ≥ n/2, where n is the order of G. Let G be a graph and A ⊆ V(G). The neighborhood of A is N(A) = {b : ab ∈ E(G) for some a ∈ A}. For any positive integer k, we show that every (2k − 1)-connected graph of order n ≥ 16k is hamiltonian if |N(A)| ≥ n/2 for every independent vertex set A of k vertices. The result contains a few known results as special cases. The case of k = 1 is the classic result of Dirac when n is large and the case of k = 2 is a result of Broersma, Van den Heuvel, and Veldman when n is large. For general k, this result improves a result of Chen and Liu. The lower bound 2k − 1 on connectivity is best possible in general while the lower bound 16k for n is conjectured to be unnecessary. © 2006 Wiley Periodicals, Inc. J Graph Theory 53: 83–100, 2006
43538481
Vertex-disjoint cycles containing specified vertices in a bipartite graph
A minimum degree condition is given for a bipartite graph to contain a 2-factor each component of which contains a previously specified vertex. 2004 Wiley Periodicals, Inc. J Graph Theory 46: 145–166, 2004
39660968
A special k-coloring for a connected k-chromatic graph
For each positive integer k we consider the smallest positive integer f(k) (dependent only on k) such that the following holds: Each connected graph G with chromatic number ?(G) = k can be properly vertex colored by k colors so that for each pair of vertices xo and xp in any color class there exist vertices x1, x2, ?, xp-1 of the same class with dist(xi, xi+1) ? f(k) for each i, 0 ? i ? p ? 1. Thus, the graph is k-colorable with the vertices of each color class placed throughout the graph so that no subset of the class is at a distance > f(k) from the remainder of the class.We prove that f(k) < 12k when the order of the graph is ? k(k ? 2) + 1.
25434953
A data-centric approach to checksum reuse for array-intensive applications
Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive components. While many systems implement hardware-based protection techniques like ECC and other approaches to ensure an acceptable level of robustness against these errors, such solutions are generally very rigid and costly. Recent research discussed checksum-based software solutions that can be used in the context of array-intensive computations. While a checksum-based scheme can be more flexible than a hardware-based approach to reliability, it can also bring significant runtime overheads. Focusing on array-intensive applications, this paper proposes a compiler-directed data-centric strategy that maximizes reuse of checksums. A unique characteristic of the proposed scheme is that it can work with a given checksum assignment, and automatically - under compiler guidance - restructures the entire application code to maximize checksum reuse. This scheme can reduce checksum recomputing even further by inter-procedural checksum reuse. Our experiments clearly show that the proposed approach reduces the number of checksum calculations required by the previous work.
205000421
A Simple Approach to Implementing Multiplication with Small Tables
Abstract A new approach for implementing multiplication with a small table is presented. This approach is much simpler and thus easier to be implemented.
12152152
Interprocedural optimizations for improving data cache performance of array-intensive embedded applications
As datasets processed by embedded processors increase in size and complexity, the management of higher levels of memory hierarchy (e.g., caches) is becoming an important issue. A major limitation of most of the cache locality optimization techniques proposed by previous research is that they handle a single procedure at a time. This prevents compilers from capturing the data access interactions between procedures and may result in poor performance. In this paper, we look at loop and data transformations from a different angle and use them in an interprocedural optimization framework. Employing the call graph representation of a given application, the proposed technique visits each node of this graph twice and uses loop and data transformations in a systematic way for optimizing array layouts whole program wide. Our experimental results show that this interprocedural locality optimization strategy is much more effective than the previous locality-based techniques that handle each procedure in isolation.
44780895
A Component Model for Discrete Event Simulation
The paper describes the ideas behind a technique for hierarchical linking of simulations as a way of building large-scale simulations from components that interact with each other via communication ports. The resulting component simulation view is compared with the presently used simulation world views. The classification of simulation components, which groups components into timeless, time-dependent, and time-independent categories, implies that components must be linked by type-specific simulation engines. The discovery of the properties of lookback, the ability of a component to change its past without affecting other components, enables another classification which categorizes communication ports into regular, virtual, and lookback ports. These two classifications enable a hierarchical simulation modeling methodology that addresses two important issues in large-scale simulation: composability and efficiency.
1780811
Reducing code size through address register assignment
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.