2598525
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicron CMOS technology. Often coupling delay is strongly dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for minimizing circuit delay through timing window modulation in dual $V_t$ technology. Experimental results on the ISCAS85 benchmark circuits indicate that the critical delay will be reduced significantly when low $V_t$ is applied properly.
14376041
Feasible region approximation using convex polytopes
A new technique for polytope approximation of the feasible region for a design is presented. This method is computationally less expensive than the simplicial approximation method. Results on several circuits are presented. It is shown that the quality of the polytope approximation is substantially better than an ellipsoidal approximation.<<ETX>>
44275614
Cell-level placement for improving substrate thermal distribution
The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.
13548202
Noise constrained power optimization for dual V/sub T/ domino logic
In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
13489029
An integrated approach to realistic worst-case design optimization of MOS analog circuits
The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>
9325323
A Parallel Feature Tracker for Extended Image Sequences
This paper presents a feature tracker for long image sequences based on simultaneously estimating the motions and deformations of a collection of adjacent image patches. By sharing common corner nodes, the patches achieve greater stability than independent patch trackers. Modeling full bilinear deformations enables tracking in sequences which have large nontranslational motions and/or foreshortening effects. We demonstrate the advantages of our technique with respect to previous algorithms using experimental results.
19368669
Location Tracking in Location-Aware Computing: An Energy Perspective
5718915
Determination of motion breakpoints in a task sequence from human hand motion
This paper describes the authors' work on the temporal segmentation of grasping task sequences based on human hand motion. The segmentation process results in the identification of motion breakpoints separating the different constituent phases of the grasping task. A grasping task is composed of three basic phases: pregrasp phase, static grasp phase, and manipulation phase. The authors show that by analyzing the fingertip polygon (preshape) area and the speed of hand movement, they can divide a task into meaningful action segments such as approach object, grasp object, manipulate object, place object, and depart. The authors introduce a measure called the volume sweep rate, which is the product of the fingertip polygon area and the hand speed. The profile of this measure is also used in the determination of the task breakpoints. The temporal task segmentation process is important as it serves as a preprocessing step to the characterization of the task phases. Once the breakpoints have been identified, further analyses such as grasp recognition and object motion extraction can then be carried out.<<ETX>>
18755002
Color image decomposition and restoration
Meyer has recently introduced an image decomposition model to split an image into two components: a geometrical component and a texture (oscillatory) component. Inspired by his work, numerical models have been developed to carry out the decomposition of gray scale images. In this paper, we propose a decomposition algorithm for color images. We introduce a generalization of Meyer’s G norm to RGB vectorial color images, and use Chromaticity and Brightness color model with total variation minimization. We illustrate our approach with numerical examples.
30593608
Skyeye: An Instruction Simulator with Energy Awareness
This paper presents a novel strategy aimed at modeling the instruction energy consumption of ARM microprocessors with dynamic voltage scaling (DVS) support. A novel energy estimation algorithm is designed, which can record the function calls, and generate a detailed energy profile for each function in a specific program. Some of the optimization policies for implementation are also discussed. These optimization policies reduce the workload of the energy estimators for the individual SOC systems. The prototype system, SKYEYE, can automatically detect the voltage/frequency variation activated by DVS system, and adjust the energy estimation model accordingly. The experiment results further prove the effectiveness of the algorithm.