726883
Implementing optimizations at decode time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations, forcing the scheduler to allocate functional units and other execution resources several cycles before they are actually used. Unfortunately, several proposed microarchitectural optimizations become less desirable or even impossible in such an environment, since they require instantaneous or near-instantaneous changes in execution behavior and resource usage in response to dynamic events that occur during instruction execution. Since they are detected several cycles after scheduling decisions have already been made, such dynamic responses are infeasible. To overcome this limitation, we propose to implement optimizations by performing what we call speculative decode. Speculative decode alters the mapping between user-visible instructions and the implemented core instructions based on observed runtime characteristics and generates speculative instruction sequences. In these sequences, optimizations are pre-scheduled in a manner compatible with realistic pipelines with multicycle scheduling latency. We present case studies on memory reference combining and silent store squashing, and demonstrate that speculative decode performs comparably or even better than impractical in-core implementations that require zero-cycle scheduling latency.
9221775
Half-price architecture
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for each instruction in structures--such as the register file and wakeup logic--which are often in the processor's critical timing paths. We argue that these structures are overdesigned since only a small fraction of instructions require two source operands to be processed simultaneously. In this paper, we propose the half-price architecture that judiciously removes this overdesign by restricting the processor's capability to handle two source operands in certain timing-critical cases. Two techniques are proposed and evaluated: one for the wakeup logic is sequential wakeup, which decouples half of the tag matching logic from the wakeup bus to reduce the load capacitance of the bus. The other technique for the register file is sequential register access, which halves the register read ports by sequentially accessing two values using a single port when needed. We show that a pipeline that optimizes scheduling and register access for a single operand achieves nearly the same performance as an ideal base machine that fully handles two operands, with 2.2% (worst case 4.8%) IPC degradation.
13391634
Macro-op Scheduling: Relaxing Scheduling Loop Constraints
Ensuring back-to-back execution of dependent instructionsin a conventional out-of-order processor requiresscheduling logic that wakes up and selects instructions atthe same rate as they are executed. To sustain high performance,integer ALU instructions typically have single-cyclelatency, consequently requiring scheduling logic withthe same single-cycle latency. Prior proposals have advocatedthe use of speculation in either the wakeup or selectphases to enable pipelining of scheduling logic to achievehigher clock frequency. In contrast, this paper proposesmacro-op scheduling, which systematically removesinstructions with single-cycle latency from the machine bycombining them into macro-ops, and performs nonspeculativepipelined scheduling of multi-cycle operations. Macro-opscheduling also increases the effective size of the schedulingwindow by enabling multiple instructions to occupy asingle issue queue entry. We demonstrate that pipelined 2-cyclemacro-op scheduling performs comparably or evenbetter than atomic scheduling or prior proposals for select-freescheduling.
40266494
IP Multiplexing by Transparent Port-Address Translator
There are certain occasions when we want to have more than one computers using a single IP address. One notable case is when we use firewalls for security reasons or when we use private IP addresses and still want to provide global IP connection. Since the computers behind the firewall or using private IP addresses do not have unique IP addresses, they can not participate in global IP network. However, we still want to provide them some means so that they can be used as if they have real IP addresses. 
 
Another example is when we have more than one server and want to make them appear to be just one server. With the proliferation of WWW, popular WWW servers tend to be overloaded and we need a mechanism to balance the load to several servers when needed. One solution being adopted is address translation by DNS (Domain Name Service). IP reuse using network address translator (NAT) is proposed in [TE93] and standardized by RFC1631. For load balancing of the WWW servers, a round robin distribution scheme using DNS is proposed and is used at NCSA [KBM94]. However, as pointed out from the literature, these schemes are based on DNS and there are several shortcomings. We propose a novel technique to perform address translation without a DNS. Our technique is based on the idea that any internet connection is uniquely identified by the socket pair . By using a address translating bridge, we can provide computers with phony IP addresses real IP connection. The performance of our scheme is investigated using a prototype and the test results show that there is very little overhead in using our scheme.
5951770
MetaCore: an application specific DSP development system
This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.
MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.
586183
A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering
In this paper, a consistency-free memory architecture for sort-last parallel rendering processors with a single frame buffer is proposed to resolve the consistency problem which may occur when more than one rasterizer try to access the data at the same address. Also, the proposed architecture reduces the latency due to pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. For these goals, a consistency-free pixel cache architecture and three effective memory systems with consistency-test units are presented. The experimental results show that the proposed architecture can achieve almost linear speedup up to four rasterizers with a single frame buffer.
14854411
Correlation between Correlations: Process and Time in Quantum Networks
We study a special inhomogeneous quantum network consisting of a ring of M pseudo-spins (here M = 4) sequentially coupled to one and the same central spin under the influence of given pulse sequences (quantum gate operations). This architecture could be visualized as a quantum Turing machine with a cyclic "tape". Rather than input-output-relations we investigate the resulting process, i.e. the correlation between one-and two-point expectation values ("correlations") over various time-steps. The resulting spatiotemporal pattern exhibits many non-classical features including Zeno-effects, violation of temporal Bell-inequalities and quantum parallelism. Due to the strange web of correlations being built-up, specific measurement outcomes for the tape may refer to one or several preparation histories of the head. Specific families of correlation functions are more stable with respect to dissipation than the total wave-function.
42316288
Mixing Heterogeneous Address Spaces in a Single Edge Network
The growth of IPv4 Internet has been facing the infamous IP address depletion barrier. In practice, typical IPv4 Internet edge networks can be expanded by incorporating private addresses and NAT devices. 
 
In this paper, major limitations of NAT-expanded private networks are presented. Furthermore, a solution is proposed to encourage the mixed usage of private and public IP addresses in a single edge network domain. The solution comprises of two key ideas : super-subnet mask and shared NAT. Super-subnet mask removes the routing boundary between private and public hosts. Shared NAT saves public IP address resources by sharing them among several private networks. These ideas not only encourage the coexistence of heterogeneous address classes, but also lead to efficient sharing of global IP addresses.