36636082
An accurate analytical delay model for BiCMOS driver circuits
An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration. >
14376041
Feasible region approximation using convex polytopes
A new technique for polytope approximation of the feasible region for a design is presented. This method is computationally less expensive than the simplicial approximation method. Results on several circuits are presented. It is shown that the quality of the polytope approximation is substantially better than an ellipsoidal approximation.<<ETX>>
44275614
Cell-level placement for improving substrate thermal distribution
The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.
13548202
Noise constrained power optimization for dual V/sub T/ domino logic
In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
13489029
An integrated approach to realistic worst-case design optimization of MOS analog circuits
The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
205396452
Video dejittering by bake and shake
Video jittering occurs when the horizontal lines of video image frames are randomly displaced due to the corruption of synchronization signals or electromagnetic interference during video transmission. Inspired by the recent Bayesian/variational dejittering model of Shen (SIAM J. Appl. Math., vol. 64, pp. 1691-1708, 2004), in the current paper we propose a novel dejittering approach nicknamed 'bake-and-shake.' The bake step is to apply Perona-Malik type nonlinear diffusions to 'melt away' or heat up the jittered video frames, based upon which the shake step is able to optimally estimate the individual line jitters and renormalize the jittered images. Numerical implementation of the bake-and-shake algorithm as well as several computational results are presented.
16190492
Noise Estimation from a Single Image
In order to work well, many computer vision algorithms require that their parameters be adjusted according to the image noise level, making it an important quantity to estimate. We show how to estimate an upper bound on the noise level from a single image based on a piecewise smooth image prior model and measured CCD camera response functions. We also learn the space of noise level functions how noise level changes with respect to brightness and use Bayesian MAP inference to infer the noise level function from a single image. We illustrate the utility of this noise estimation for two algorithms: edge detection and featurepreserving smoothing through bilateral filtering. For a variety of different noise levels, we obtain good results for both these algorithms with no user-specified inputs.
19368669
Location Tracking in Location-Aware Computing: An Energy Perspective
32568915
Event Sentence Extraction in Korean Newspapers
Information extraction is to extract information about the main events in the text. This paper presents an event sentence extraction method in Korean newspapers for information extraction. Event sentences contain meaningful information such as the agent, the time and the place of an event. To extract these sentences, we acquire various features such as verbs, nouns, noun phrases, 3Ws, and their weights. And then, the system computes weights of sentences and extracts event sentences by our extraction algorithm. The experimental result shows the average precision of 86.1%.
26233543
Appearance-Based Structure from Motion Using Linear Classes of 3-D Models
In this paper, we address the problem of recovering 3-D models from sequences of partly calibrated images with unknown correspondence. To that end, we integrate tracking, structure from motion with geometric constraints (specifically in the form of linear class models) in a single framework. The key to making the proposed approach work is the use of appearance-based model matching and refinement which updates the estimated correspondences on each iteration of the algorithm. Another key feature is the matching of a 3-D model directly with the input images without the conventional 2-step approach of stereo data recovery and 3-D model fitting. Initialization of the linear class model to one of the input images (the reference image) is currently partly manual.This synthesis and refine approach, or appearance-based constrained structure from motion (AbCSfm), is especially useful in recovering shapes of objects whose general structureis known but which may have little discernable texture in significant parts of their surfaces. We applied the proposed approach to 3-D face modeling from multiple images to create new 3-D faces for DECface, a synthetic talking head developed at Cambridge Research Laboratory, Digital Equipment Corporation. The DECface model comprises a collection of 3-D triangular and rectangular facets, with nodes as vertices. In recovering the DECface model, we assume that the sequence of images is taken with a camera with unknown focal length and pose. The geometric constraints used are of the form of linear combination of prototypes of 3-D faces of real people. Results of this approach show its good convergence properties and its robustness against cluttered backgrounds.