30765152
On the Quickest Path Problem
Abstract Let N be an input network and σ be the amount of data to be transmitted. We present an O( mn 2 ) time algorithm that finds all-pairs quickest paths, for a given value of σ, and show that the quickest path between any two nodes for any value of σ can be found in O(log m ) time, provided O( mn 2 ) preprocessing time is spent.
35779178
On the Quickest Path Problem
In this paper, we propose an O(mn2) time algorithm that finds all-pairs quickest paths in a given network N, where n and m are the numbers of nodes and arcs, respectively, in N. Besides, the quickest path between any two nodes can be determined in O(log m) time, provided O(mn2) time preprocessing is made.
12008114
Weak Clique-Covering Cycles and Paths
In this paper, we investigate the sufficient conditions for a graph to contain a cycle (path) C such that G − V (C) is a disjoint union of cliques. In particular, sufficient conditions involving degree sum and neighborhood union are obtained.
1160338
Graph Connectivity After Path
Removal
Let G be a graph and
u, v be two distinct vertices of
G. A u—v path P is called nonseparating if
G—V(P) is connected. The purpose of this
paper is to study the number of nonseparating
u—v path for two arbitrary
vertices u and
v of a given graph. For a
positive integer k, we will
show that there is a minimum integer α(k) so that if G is an α(k)-connected graph and
u and v are two arbitrary vertices in
G, then there exist
k vertex disjoint paths
P1[u,v], P2[u,v], . . ., Pk[u,v], such that G—V (Pi[u,v]) is connected for every
i (i = 1, 2, ..., k). In fact, we will prove that
α(k) ≤ 22k+2. It is known that α(1) = 3.. A
result of Tutte showed that α(2) = 3. We show that α(3) = 6. In
addition, we prove that if G
is a 5-connected graph, then for every pair of vertices
u and v there exists a path
P[u, v] such that G—V(P[u,
v]) is 2-connected.
14435216
Optimizing instruction TLB energy using software and hardware techniques
Power consumption and power density for the Translation Look-aside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. After pointing out the importance of instruction TLB (iTLB) power optimization, this article embarks on a new philosophy for reducing the number of accesses to this structure. The overall idea is to keep a translation currently being used in a register and avoid going to the iTLB as far as possible---until there is a page change. We propose four different approaches for achieving this, and experimentally demonstrate that one of these schemes that uses a combination of compiler and hardware enhancements can reduce iTLB dynamic power by over 85&percent; in most cases.The proposed approaches can work with different instruction-cache (iL1) lookup mechanisms and achieve significant iTLB power savings without compromising on performance. Their importance grows with higher iL1 miss rates and larger page sizes. They can work very well with large iTLB structures that can possibly consume more power and take longer to lookup, without the iTLB getting into the common case. Further, we also experimentally demonstrate that they can provide performance savings for virtually indexed, virtually tagged iL1 caches, and can even make physically indexed, physically tagged iL1 caches a possible choice for implementation.
40869256
Parallel algorithms for permutation graphs
In this paper, parallel algorithms are presented for solving some problems on permutation graphs. The coloring problem is solved inO(log2n) time usingO(n3/logn) processors on the CREW PRAM, orO(logn) time usingO(n3) processors on the CRCW PRAM. The weighted clique problem, the weighted independent set problem, the cliques cover problem, and the maximal layers problem are all solved with the same complexities. We can also show that the longest common subsequence problem belongs to the class NC.
18317069
Verifiable annotations for embedded java environments
Many implementations of Java Virtual Machine (JVM) use optimizing dynamic compilation for improving performance of Java applications. However, optimizing compilation is expensive in terms of both time and memory space complexity. Annotations are frequently used to reduce the dynamic compilation overhead in embedded Java environments where the memory budget and CPU speed are limited. However, some annotations can cause the dynamic compiler to generate code that violates the security policy of the JVM. These annotations present a safety problem if they are not verified before being used by the compiler. In this work, we present annotation schemes for three frequently used optimizations: null pointer check removal, value liveness analysis, and array bound check removal. All our annotations can be verified at low cost during dynamic compilation time to guarantee that they do not cause the compiler to generate code that violates the security policy of the JVM.