52848704
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction
Interconnect area and energy dissipation are critical factors in any system designed today. In this work, we present techniques to help reduce area/cost and energy dissipation of address buses with significant temporal redundancy. We describe two encoding techniques for such buses, called pattern adjuster (PA) encoding and dynamic charge/discharge encoding (DCDE), that use simple hardware and no extra bus lines for control signals. Results show that, using PA encoding, self energy reduces by 18-38%, coupling toggle energy by 19-96%, and coupling charge/discharge energy by 14-40%. In addition, with DCDE applied on top of PA, coupling charge/discharge energy reduces by up to 48%. Overall, up to 25% address bus energy savings can be obtained using our techniques compared to the energy dissipation of the original bus, with 26-79% reduction in the number of bus lines. Our techniques use very simple hardware and will have negligible encoding/decoding latencies that are much lower than those of low-power bus encoding schemes.
14115714
Energy-efficient compressed address transmission
To realize energy-efficient buses in current nanometer-scale technologies, techniques like compression or encoding that exploit information redundancy have been explored. However, available compression techniques for buses do not always ensure energy-efficient transmission of compressed information. In this work, we present various techniques that can be used with compression schemes for buses to ensure high energy efficiency. Our best scheme, applied to a stream of 38-bit addresses issued in a typical microprocessor, yields about 14.7% energy reduction on the average across a wide range of compressed bus widths ranging and over many SPEC CPU2000 benchmarks. Our proposed techniques especially perform better - up to 28.8% energy reduction is obtained - for narrower bus widths in the range 8-16 bits.
43415133
The performance advantage of applying compression to the memory system
The memory system stores information comprising primarily instructions and data and secondarily address information, such as cache tag fields. It interacts with the processor by supporting related traffic (again comprising addresses, instructions, and data). Continuing exponential growth in processor performance, combined with technology, architecture, and application trends, place enormous demands on the memory system to permit this information storage and exchange at a high-enough performance (i.e., to provide low latency and high bandwidth access to large amounts of information). This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the memory system and evaluates the potential of compression in improving performance of the memory system. Analysis of traces obtained with Sun Microsystems' Shade simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite yield impressive results. Well-designed compression schemes may provide benefits in performance that far outweigh the extra time and logic for compression and decompression. This will be more so in the future since the speed and size of logic (which will be used to perform compression/decompression) are improving and are projected to improve at a much higher rate compared to those of interconnect (which will be used to communicate the information), both on-chip and off-chip.
14714835
A Method of Spatial Reasoning Based on Qualitative Trigonometry
Abstract Due to the lack of exact quantitative information or the difficulty associated with obtaining or processing such information, qualitative spatial knowledge representation and reasoning often become an essential means for solving spatial constraint problems as found in science and engineering. This paper presents a computational approach to representing and reasoning about spatial constraints in two-dimensional Euclidean space, where the a priori spatial information is not precisely expressed in quantitative terms. The spatial quantities considered in this work are qualitative distances and qualitative orientation angles. Here, we explicitly define the semantics of these quantities and thereafter formulate a representation of qualitative trigonometry (QTRIG). The resulting QTRIG formalism provides the necessary inference rules for qualitative spatial reasoning. In the paper, we illustrate how the QTRIG relationships can be employed in generating qualitative spatial descriptions in two-dimensional Euclidean geometric problems, and furthermore, how the derived qualitative spatial descriptions can be used to guide a simulated-annealing-based exact quantitative value assignment. Finally, we discuss an application of the proposed spatial reasoning method to the kinematic constraint analysis in computer-aided pre-parametric mechanism design.
16580627
Handling Safety-Related Feature Interaction in Safety-Critical Product Lines
The variation management of software product lines is currently handled without adequately taking safety or other system-level properties into account. This is largely due to (1) the fact that the available product-line variation-management techniques lack sufficient support for representing the combined effect of different features, and (2) the existing feature interaction techniques do not suffice for handling one-to-many feature interactions typical of many safety-critical product lines. The challenge is that we need to track the safety-related feature interactions while still promoting reuse. The expected contribution of this work is to demonstrate how safety-related feature interactions can be better investigated and managed by the safety-analysis guided, model-based approach described in this paper.
1037858
Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources
In this paper we propose a novel scheduling framework for a dynamic real-time environment that experiences power consumption constraints. This framework is capable of dynamically adjusting the voltage/ speed of the system, such that no task in the system misses its deadline and the total energy savings of the system are maximized. 
 
Each task in the system consumes a certain amount of energy, which depends on a speed chosen for execution. The process of selecting speeds for execution while maximizing the energy savings of the system requires the exploration of a large number of combinations, which is too time consuming to be computed on-line. Thus, we propose an integrated heuristic methodology which executes an optimization procedure and an approximate greedy algorithm in a low computation time. This scheme allows the scheduler to handle power-aware real-time tasks with low cost while maximizing the use of the available resources and without jeopardizing the temporal constraints of the system. Simulation results show that our heuristic methodology achieves a performance with near-optimal results.
14860014
Self-scheduling on distributed-memory machines
The authors present a general approach of self-scheduling a non-uniform parallel loop on a distributed-memory machine. The approach has two phases: a static scheduling phase and a dynamic scheduling phase. In addition to reduce scheduling overhead, using the static scheduling phase allows the data needed by the statically scheduled iterations to be prefetched. The dynamic scheduling phase balances the workload. Data distribution methods for self-scheduling are also the focus of this paper. The authors classify the data distribution methods into four categories and present partial duplication, a method that allows the problem size to grow linearly in the number of processors. The experiments conducted on a 64-node NCUBE show that as much as 79% improvement is achieved over static scheduling on the generation of a false-color image.
9603853
COPACC: A Cooperative Proxy-Client Caching System for On-Demand Media Streaming
Proxy caching is a key technique to reduce transmission cost for on-demand multimedia streaming. However, its effectiveness is limited by the insufficient storage space and weak cooperations among proxies and their clients. In this paper, we propose COPACC, a novel cooperative proxy-and-client caching system that combines the advantages of both proxy caching and peer-to-peer (P2P) client communications. We propose a comprehensive suite of protocols to facilitate the interactions among different network entities in COPACC. We also develop an efficient cache allocation algorithm to minimize the aggregated transmission cost of the whole system. Simulation results demonstrate that COPACC achieves remarkably lower transmission cost. Moreover, it is much more robust than a pure P2P system in the presence of node failures.