15594355
Replacing Failed Sensor Nodes by Mobile Robots
Sensor replacement is important for sensor networks to provide continuous sensing services. Existing approaches relocate redundant nodes to fill the holes created by failed sensors and require all or most sensor nodes to have mobility. However, mobility equipment is expensive while technology trends are scaling sensors to be smaller and cheaper. In this paper, we propose to use a small number of mobile robots to replace failed sensors in a large-scale static sensor network. We study algorithms for detecting and reporting sensor failures and coordinating the movement of robots that minimize the motion energy of mobile robots and the messaging overhead incurred to the sensor network. A manager receives failure reports and determines which robot to handle a failure. We study three algorithms: a centralized manager algorithm, a fixed distributed manager algorithm, and a dynamic distributed manager algorithm. Our simulations show that: (a) The centralized and the dynamic distributed algorithms have lower motion overhead than the fixed distributed algorithm. (b) The centralized algorithm is less scalable than the two distributed manager algorithms. (c) The two distributed algorithms have higher messaging cost than the centralized algorithm. Hence, the optimal choice of the coordination algorithm depends on the specific scenarios and objectives being optimized.
2733921
Joint power management of memory and disk
The paper presents a scheme to combine memory and power management for achieving better energy reduction. Our method periodically adjusts the size of physical memory and the timeout value to shut down a hard disk for reducing the average power consumption. We use Pareto distributions to model the distributions of idle time. The parameters of the distributions are adjusted at run-time for calculating the corresponding timeout value of the disk power management. The memory size is changed based on the inclusion property to predict the number of disk accesses at different memory sizes. Experimental results show more than 50% energy savings compared to a 2-competitive fixed-timeout method.
14287933
Statistically optimal dynamic power management for streaming data
This paper presents a method that uses data buffers to create long periods of idleness to exploit power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes without subjective or heuristic decisions. We simulate four different hardware configurations with MPEG-1, MPEG-2, and MPEG-4 formats as a case study. Our results indicate that the optimal buffer size varies significantly for different data formats on different hardware. Simulation results indicate that 16 MB buffers are sufficient for MPEG-1, MPEG-2, and MPEG-4 video streams from a microdrive or a network card, but transfers from an IDE disk require buffer sizes ranging from 16 MB to 176 MB, depending on each video's statistical properties.
11944586
Comparing System-Level Power Management Policies
Reducing power consumption is a challenge to system designers. Portable systems, such as laptop computers and personal digital assistants (PDAs), draw power from batteries, so reducing power consumption extends their operating times. For desktop computers or servers, high power consumption raises temperature and deteriorates performance and reliability. Soaring energy prices and rising concern about the environmental impact of electronics systems further highlight the importance of low power consumption. Power reduction techniques can be classified as static and dynamic. Static techniques, such as synthesis and compilation for low power, are applied at design time. In contrast, dynamic techniques use runtime behavior to reduce power when systems are serving light workloads or are idle. These techniques are known as dynamic power management (DPM). DPM can be achieved in different ways; for example, dynamic voltage scaling (DVS) changes supply voltage at runtime as a method of power management. Here, we use DPM specifically for shutting down unused I/O devices. We built an experimental environment on a laptop computer running Microsoft Windows. We implemented existing power management policies and quantitatively compared their effects on power saving and performance degradation.
161273
Dynamic power management for streaming data
This paper presents a method that uses data buffers to smoothen request variations and to create long idleness for power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes and the amount of data to store in the buffers. We use video prefetching as a case study and obtain power savings of more than 74% for MPEG-1 and 34% for MPEG-2 videos.
7685891
Quantitative comparison of power management algorithms
Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated to be effective in certain applications. We quantitatively compare the power saving and performance impact of these algorithms on hard disks of a desktop and notebook computers. This paper has three contributions. First, we build a framework in Windows NT to implement power managers running realistic workloads and directly interacting with users. Second, we define performance degradation that reflects user perception. Finally, we compare power saving and performance of existing algorithms and analyze the difference.
7907707
Fast search in DNA sequence databases using punctuation and indexing
Exact pattern searching in DNA sequence databases has applications in identification of highly conserved regulatory sequences, the design of hybridization probes, and improving performance of approximate homology searching tools such as BLAST and BLAT. We propose a new pattern searching algorithm, Compressed-Punctuated-Boyer-Moore (cp-BM), to enhance exact pattern match searches of DNA sequences. cp-BM encodes two bits to represent each A, T, C, G character (4-character 8 bit (4C8B) compression), plus punctuator characters to indicate unambiguously the encoding frame of the compressed target sequence, thereby solving the misalignment problem in searching patterns with ordinary 4C8B compression. cp-BM searches DNA patterns at least 6 times faster than AGREP for pattern lengths ≥ 128 and between 2-fold and 5-fold faster than d-BM for all pattern lengths. cp-BM's performance is enhanced by punctuator indexing and multiple punctuators, especially for short sequences, yielding greater than 10-fold enhancements compared to d-BM and AGREP. In addition, cp-BM outperformed BLAT for sequences 64 or more bases in length, and was more than three-fold faster for 256 base sequences.
7818893
Performance Benefits of Monolithically Stacked 3-D FPGA
The performance benefits of a monolithically stacked three-dimensional (3-D) field-programmable gate array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing logic blocks (LBs) and interconnects, are investigated. A Virtex-II-style two-dimensional (2-D) FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3-D FPGA. It is assumed that only the switch transistor and configuration memory cells can be moved to the top layers and that the 3-D FPGA employs the same LB and programmable interconnect architecture as the baseline 2-D FPGA. Assuming they are les 0.7, the area of a static random-access memory cell and switch transistors having the same characteristics as n-channel metal-oxide-semiconductor devices in the CMOS layer are used. It is shown that a monolithically stacked 3-D FPGA can achieve 3.2 times higher logic density, 1.7 times lower critical path delay, and 1.7 times lower total dynamic power consumption than the baseline 2-D FPGA fabricated in the same 65-nm technology node
158009
Threshold optimization algorithm for weak signal in distributed-sensor fusion system
Distributed order statistics constant false alarm rate (OS-CFAR) detection techniques are important for nonstationary observation with varying weak narrowband random signals. However, it is very difficult to choose system parameters to obtain optimal threshold values at the fusion center because of the nonlinear property of distributed OS-CFAR detection system. This paper provides a novel solution based on an effective and flexible genetic algorithm. Using this approach, all system parameters are directly coded in decimal chromosomes and they can be optimized simultaneously. Furthermore, we also derive the more general model by implementing the K fusion rules. The simulation results show that applying the proposed approach one can achieve comparable performances with the reported methods and results.
11276211
PDC: Pattern discovery with confidence in DNA sequences
Pattern discovery in DNA sequences is one of the most challenging tasks in molecular biology and computer science. The main goal of pattern discovery in DNA sequences is to identify sequences of important biological function hidden in the huge amounts of genomic sequences. Several methods and techniques have been proposed and implemented in this field. However, in order to reduce computational time and complexity, most of them either focus on finding short DNA patterns or require explicit specification of pattern lengths in advance. Scientists need to find longer patterns without specifying pattern lengths in advance and still have good performance.In this paper, we propose a pattern discovery algorithm called Pattern Discovery with Confidence (PDC). Based on biological studies, we propose a new measurement system that can identify overrepresented patterns inside DNA sequences. Using this measurement, PDC algorithm can narrow the search space by checking dependency along the pattern, thus extending the pattern as long as possible without the need to restrict or specify the length of a pattern in advance. Experimental tests demonstrate that this approach can find long, interesting patterns within a reasonable computation time.
1552056
Pama: a Fast String Matching Algorithm
String matching is a fundamental operation in computer science, and its performance has great impact on many applications including database query, text processing, DNA and protein sequence analysis. In this paper, we propose a fast string matching algorithm, PAMA (PAttern MAtching). The shift rule used by PAMA not only subsumes both the bad character rule and the good suffix rule employed by the well-known Boyer-Moore algorithm, but also employs an additional key observation to enable faster shifting during the string matching process. Theoretically, we prove that from the same alignment, the next shift of PAMA will be at least as much as that of the Boyer-Moore algorithm. Experimentally, we show that PAMA indeed significantly outperforms the original Boyer-Moore algorithm in almost all cases, and outperforms other Boyer-Moore variants such as Tuned-BM, Turbo-BM and Horspool for long patterns (length ≥ 128) or for small alphabets (size < 8).