12117022
Distributed data collection through remote probing in windows environments
Distributed data collector (DDC) is a framework to ease and automate repetitive executions of console applications (probes) over a set of LAN networked Windows personal computers. The framework allows for the remote execution of probes, providing support for collecting the execution output of probes (standard output and standard error). Additionally, right after a probe execution, the output can be parsed and processed by user-defined code (post collecting code) that can act accordingly to user's needs. The framework can be useful to perform repetitive large-scale monitoring and administrative tasks over machines with transient availability, that is, machines that present no guarantees of being available at a given time. A major strength of DDC lies in the fact that it does not require installation of software in remote nodes, avoiding administrative burdens that remote daemons and alike normally provoke. Besides presenting the data collection framework, the paper discusses the results of a 30-day monitoring experiment conducted with DDC. The experiment collected resource usage metrics over 169 Windows machines from classroom laboratories of an academic institution.
17056117
Integrating SNMP into a Mobile Agent Infrastructure
Mobile Code is an emerging paradigm that is gaining momentum in several fields of application. Network Management is a potential area for the use of this technology, provided it will be able to interoperate with well established solutions for Network Management. This paper presents the integration a classic NM protocol, like SNMP, into a platform of Mobile Agents. Our platform, called JAMES, has been developed in the context of an Eureka Project (Σ!1921) where the project partners are University of Coimbra, Siemens SA and Siemens AG. Since the main target of the platform is network management, it includes a set of SNMP services allowing mobile agents to easily interface with SNMP agents, as well as with legacy SNMP-based management applications. In the paper we present a brief overview of the general architecture of the platform and we describe in some detail the framework we used to provide for integration between mobile agent applications and SNMP.
33293331
Portable transparent checkpointing for distributed shared memory
We present a checkpointing mechanism for a DSM system that, in spite of being invisible to the programmer, is quite efficient and portable. It is efficient because it is nonblocking, coordinated and thus domino-effect free. It offers some portability because it is built on top of MPI and uses only the services offered by MPI and a POSIX compliant local file system. As far as we know, this is the first real implementation of such a scheme for DSM. Along with the description of the algorithms used, we present experimental results obtained in a cluster of workstations, and discuss many insights that came out of the implementation effort. We hope that our research shows that efficient, transparent and portable checkpointing is viable for DSM systems.
32609589
Avoiding checkpoint contamination in parallel systems
Checkpointing and rollback recovery is a very effective technique to tolerate faults, provided the application is able to recover from a previous checkpoint and proceed with a failure-free computation. However, this technique may fall short if the checkpoint files are somehow contaminated by errors. This paper presents two mechanisms that may be used to determine if a committed checkpoint is error-free or not. These techniques can be used simultaneously for error detection and failure recovery. Both of them are based on checkpoint duplication: one makes use of spatial redundancy while the other is based on temporal redundancy. We discuss the main problems and trade-offs that have to be dealt with to implement these techniques. We then present a performance study that clearly shows the pros and cons of each one. As far as we know, this paper presents the first implementation of these mechanisms in a standard parallel computing system.
9058735
Supporting Disconnected Computing in Mobile Agent Systems
Mobile agents are typically referred as a very adequate paradigm for using in mobile and disconnected computing environments. They are autonomous, have a strong sense of location and are able to operate independently of a central server. Nevertheless, although this is true, for developing a mobile agent system that is capable of operating in a disconnected computing environment, much more is needed: persistence stores where the agents can be safely stored; agent reactivation mechanisms, which allow agents to migrate when a network connection is detected; policies and notification mechanisms for dealing with changing locations; among other things. In this paper, we present the mechanisms developed for the M&M mobile agent framework in order to address mobile and disconnected computing environments. These mechanisms can be readily adapted to any other platform that needs to deal with disconnected computing. Keyworks: Distributed agents, mobile agents, mobile computing, disconnected computing
30244538
Fault-tolerance on regular decomposition grid applications
Writing parallel applications is considerably more complex due to additional problems not found in the sequential environment. The main problems include communication, synchronization data partitioning and distribution, mapping of processes, heterogeneity and fault tolerance. Fault tolerance is a very important feature in parallel/distributed systems since the mean time between failures of the system decreases with the number of processors, and the failure of just one process(or) can lead to the crash of the entire application. This paper presents an example of a parallel library (PUL-RD) that solves most of the problems pointed out before and provides support for fault tolerance. The original version of the library offers high-level support for parallelism in a portable way and can be used to write grid-based parallel applications which have a regular decomposition. In this paper, we will describe the fault-tolerance issues that were incorporated into the PUL-RD, giving special attention to the functionality of the checkpointing scheme.<<ETX>>
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
15163719
Solving satisfiability in combinational circuits
As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.
16534842
Formal Verification of Component-Based Software Systems
In this work we present a methodology for formal modeling and verification of component based software systems. The methodology is based on software architecture, components, and reuse of Petri Nets models. With this process, we are contributing for the visual composition, verification, and formal validation of software. We also show an example of the application of this methodology into two different domains.