29505226
Discriminant neighborhood embedding for classification
In this paper a novel subspace learning method called discriminant neighborhood embedding (DNE) is proposed for pattern classification. We suppose that multi-class data points in high-dimensional space tend to move due to local intra-class attraction or inter-class repulsion and the optimal embedding from the point of view of classification is discovered consequently. After being embedded into a low-dimensional subspace, data points in the same class form compact submanifod whereas the gaps between submanifolds corresponding to different classes become wider than before. Experiments on the UMIST and MNIST databases demonstrate the effectiveness of our method.
43025995
Processing Probabilistic Range Query over Imprecise Data Based on Quality of Result
Sensors are employed in many applications to monitor entities such as environment temperature or illumination. Because of limited resources (e.g., battery power and wireless bandwidth), it is impractical for the database to track continuous changing readings from sensors at all times. Consequently, database may produce incorrect query results based on recorded data. However, if the error between the recorded value and the actual value is bounded, probabilistic approach can be applied to process queries over the imprecise data in database. The paper proposes a quality of result based probabilistic range query processing method. Two measures are defined to evaluate the quality of result. A probability model is proposed to estimate the quality of returned results. Based on the model, an algorithm is developed to choose the probability threshold according to user’s requirement on the quality of result.
14422830
Compiler-guided register reliability improvement against soft errors
With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely used in reliability-sensitive environments, it becomes increasingly important to develop cost-effective techniques to improve the processor reliability against soft errors. This paper focuses on studying the register file immunity against soft errors since modern processors typically employ a large number of registers, which are accessed very frequently. As a result, soft errors occurred in registers can easily propagate to functional units or the memory system, leading to silent data error (SDC) or system crash.To develop cost-effective techniques to fight soft errors for embedded processors, the first step is to understand the register file susceptibility to soft errors and its impact on the system reliability accurately. Toward this goal, this paper proposes the concept of register vulnerability factor (RVF) to characterize the probability that register transient errors can escape the register file and thus potentially impact the system reliability. Built upon the RVF concept, we then propose two cost-effective compiler-guided techniques to improve the register file reliability by lowering the RVF value. Our experiments indicate that on average, the RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly while protecting register files against transient errors.
17633305
The Impact of Cache Organization in Optimizing Microprocessor Power Consumption
In the recent years, power consumption has become increasingly an important design concern as silicon area and performance in modern computer systems design. Several factors have contributed to this trend. Perhaps the most visible have been the remarkable success and growth of Personal Digital Assistants (PDA’s), Cellular phones and pagers, etc .This work is an attempt to explore the impact of feature size shrinkage and cache configuration on optimizing power consumption in modern processors. The work studies two commercially known RISC microprocessors. The StrongARM and the Alpha-21064 microprocessors. The latter is the ancestor of the former and is therefore used here as the baseline in our analysis. Our analysis has illustrated quantitatively great power saving when technology is downsized and cache is well organized
12895493
Improvement of HITS-based algorithms on web documents
In this paper, we present two ways to improve the precision of HITS-based algorithms on Web documents. First, by analyzing the limitations of current HITS-based algorithms, we propose a new weighted HITS-based method that assigns appropriate weights to in-links of root documents. Then, we combine content analysis with HITS-based algorithms and study the effects of four representative relevance scoring methods, VSM, Okapi, TLS, and CDR, using a set of broad topic queries. Our experimental results show that our weighted HITS-based method performs significantly better than Bharat's improved HITS algorithm. When we combine our weighted HITS-based method or Bharat's HITS algorithm with any of the four relevance scoring methods, the combined methods are only marginally better than our weighted HITS-based method. Between the four relevance-scoring methods, there is no significant quality difference when they are combined with a HITS-based algorithm.
9354212
High-Performance Job-Shop Scheduling With A Time-Delay TD-lambda Network
Job-shop scheduling is an important task for manufacturing industries. We are interested in the particular task of scheduling payload processing for NASA's space shuttle program. This paper summarizes our previous work on formulating this task for solution by the reinforcement learning algorithm T D(). A shortcoming of this previous work was its reliance on hand-engineered input features. This paper shows how to extend the time-delay neural network (TDNN) architecture to apply it to irregular-length schedules. Experimental tests show that this TDNN-TD() network can match the performance of our previous hand-engineered system. The tests also show that both neural network approaches signiicantly out-perform the best previous (non-learning) solution to this problem in terms of the quality of the resulting schedules and the number of search steps required to construct them.
2749219
A Method for Speeding Up Value Iteration in Partially Observable Markov Decision Processes
We present a technique for speeding up the convergence of value iteration for partially observable Markov decisions processes (POMDPs). The underlying idea is similar to that behind modified policy iteration for fully observable Markov decision processes (MDPs). The technique can be easily incorporated into any existing POMDP value iteration algorithms. Experiments have been conducted on several test problems with one POMDP value iteration algorithm called incremental pruning. We find that the technique can make incremental pruning run several orders of magnitude faster.
207099457
Improved sparse least-squares support vector machine classifiers
The least-squares support vector machines (LS-SVM) can be obtained by solving a simpler optimization problem than that in standard support vector machines (SVM). Its shortcoming is the loss of sparseness and this usually results in slow testing speed. Several pruning methods have been proposed. It is found that these methods can be further improved for classification problems. In this paper a different reduced training set is selected to re-train LS-SVM. Then a new procedure is proposed to obtain the sparseness. The performance of the proposed method is compared with other typical ones and the results indicate that it is more effective.
30318957
Replication cache: a small fully associative cache to improve data cache reliability
Soft error conscious cache design has become increasingly crucial for reliable computing. The widely used ECC or parity-based integrity checking techniques have only limited capability in error detection and correction, while incurring nontrivial penalty in area or performance. The N modular redundancy (NMR) scheme is too costly for processors with stringent cost constraints. This paper proposes a cost-effective solution to enhance data reliability significantly with minimum impact on performance. The idea is to add a small fully associative cache to store the replica of every write to the L1 data cache. Due to data locality and its full associativity, the replication cache can be kept small while providing replicas for a significant fraction of read hits in L1, which can be used to enhance data integrity against soft errors. Our experiments show that a replication cache with eight blocks can provide replicas for 97.3 percent of read hits in L1 on average. Moreover, compared with the recently proposed in-cache replication schemes, the replication cache is more energy efficient, while improving the data integrity against soft errors significantly.
9748208
CAGER: classification analysis of gene expression regulation using multiple information sources
BackgroundMany classification approaches have been applied to analyzing transcriptional regulation of gene expressions. These methods build models that can explain a gene's expression level from the regulatory elements (features) on its promoter sequence. Different types of features, such as experimentally verified binding motifs, motifs discovered by computer programs, or transcription factor binding data measured with Chromatin Immunoprecipitation (ChIP) assays, have been used towards this goal. Each type of features has been shown successful in modeling gene transcriptional regulation under certain conditions. However, no comparison has been made to evaluate the relative merit of these features. Furthermore, most publicly available classification tools were not designed specifically for modeling transcriptional regulation, and do not allow the user to combine different types of features.ResultsIn this study, we use a specific classification method, decision trees, to model transcriptional regulation in yeast with features based on predefined motifs, automatically identified motifs, ChlP-chip data, or their combinations. We compare the accuracies and stability of these models, and analyze their capabilities in identifying functionally related genes. Furthermore, we design and implement a user-friendly web server called CAGER (Classification Analysis of Gene Expression Regulation) that integrates several software components for automated analysis of transcriptional regulation using decision trees. Finally, we use CAGER to study the transcriptional regulation of Arabidopsis genes in response to abscisic acid, and report some interesting new results.ConclusionModels built with ChlP-chip data suffer from low accuracies when the condition under which gene expressions are measured is significantly different from the condition under which the ChIP experiment is conducted. Models built with automatically identified motifs can sometimes discover new features, but their modeling accuracies may have been over-estimated in previous studies. Furthermore, models built with automatically identified motifs are not stable with respect to noises. A combination of ChlP-chip data and predefined motifs can substantially improve modeling accuracies, and is effective in identifying true regulons. The CAGER web server, which is freely available at http://cic.cs.wustl.edu/CAGER/, allows the user to select combinations of different feature types for building decision trees, and interact with the models graphically. We believe that it will be a useful tool to facilitate the discovery of gene transcriptional regulatory networks.
2426741
An analysis and application of distributed constraint satisfaction and optimization algorithms in sensor networks
This research is motivated by a distributed scheduling problem in distributed sensor networks, in which computational resources are scarce. To cope with limited computational resources and restricted real-time requirement, it is imperative to apply distributed algorithms that have low overhead on resource requirement and high anytime performance. In this paper, We study distributed stochastic algorithm (DSA) and distributed breakout algorithm (DBA), two distributed algorithms developed earlier for distributed constraint satisfaction problems. We experimentally investigate their properties and compare their performance using our distributed scheduling problem as a benchmark. We first formulate the scheduling problem as a distributed multi-coloring problem. We then experimentally show that the solution quality and communication cost of DSA exhibit phase-transition or threshold behavior, in that the performance degenerates abruptly and dramatically when the degree of parallel executions of distributed agents increases beyond some critical value. The results show that when controlled properly, DSA is superior to DBA, having better or competitive solution quality and significantly smaller communication cost than DBA. Therefore, DSA is the algorithm of choice for our distributed scan scheduling problem.