45927986
Full chip ESD design rule checking
Electrostatic discharge (ESD) protection is essential for reliability and high yield. ESD design rule checking, however, is beyond the scope of commercial DRC tools. We have presented previously an ESD design rule checker for individual I/O cells. Full chip ESD design rules come in a myriad number of ways and are heavily process dependent. To check them one by one requires rewriting the design rule checker program for each process generation. This paper presents a framework for full chip ESD design rule checking adaptive to how full chip ESD design rules are derived.
44275614
Cell-level placement for improving substrate thermal distribution
The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.
14376041
Feasible region approximation using convex polytopes
A new technique for polytope approximation of the feasible region for a design is presented. This method is computationally less expensive than the simplicial approximation method. Results on several circuits are presented. It is shown that the quality of the polytope approximation is substantially better than an ellipsoidal approximation.<<ETX>>
13489029
An integrated approach to realistic worst-case design optimization of MOS analog circuits
The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
13548202
Noise constrained power optimization for dual V/sub T/ domino logic
In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
14238528
Is appearance-based structure from motion viable?
Most structure from motion work assumes that tracking is a separate issue from recovery of structure and motion. This paper argues that in certain cases, it helps to use the original images to refine the tracking in the course of estimating structure and motion. We illustrate this by presenting two algorithms: one for appearance-based structure from complete rotation and another for 3-D face modeling from three images. We come to the following conclusion: use appearance prediction only if the gross shape or type of shape deformation is known. Otherwise, one is very likely better off just using the currently known tracks.
9325323
A Parallel Feature Tracker for Extended Image Sequences
This paper presents a feature tracker for long image sequences based on simultaneously estimating the motions and deformations of a collection of adjacent image patches. By sharing common corner nodes, the patches achieve greater stability than independent patch trackers. Modeling full bilinear deformations enables tracking in sequences which have large nontranslational motions and/or foreshortening effects. We demonstrate the advantages of our technique with respect to previous algorithms using experimental results.
39878736
Unsupervised Learning of Pattern Templates from Unannotated Corpora for Proper Noun Extraction
This paper describes an approach to extracting proper nouns in the very large text corpora without using the lexicon or cue word dictionary. At first, we train the pattern for extracting the proper nouns by applying the initial proper names into the unannotated corpora that does not have any tags yet. And then we continuously apply the pattern templates into the corpora in order to extract new proper nouns until certain period.
2096181
Video editing using figure tracking and image-based rendering
We describe a new approach to video editing based on the semi-automatic segmentation of video into multiple layers and the composition of layers using image-based rendering. Using figure tracking and background motion estimation, we can segment a moving figure and reconstruct the background. Using geometrically-correct pixel reprojection, layers can be composited on the basis of the geometry of the underlying scene and the position of a virtual camera. We have implemented a prototype editing system called SpliceWorld.
956323
Estimating Intrinsic Images from Image Sequences with Biased Illumination
We present a method for estimating intrinsic images from a fixed-viewpoint image sequence captured under changing illumination directions. Previous work on this problem reduces the influence of shadows on reflectance images, but does not address shading effects which can significantly degrade reflectance image estimation under the typically biased sampling of illumination directions. In this paper, we describe how biased illumination sampling leads to biased estimates of reflectance image derivatives. To avoid the effects of illumination bias, we propose a solution that explicitly models spatial and temporal constraints over the image sequence. With this constraint network, our technique minimizes a regularization function that takes advantage of the biased image derivatives to yield reflectance images less influenced by shading.