41129235
Determining the Global Progress of Parallel Simulation with FIFO Communication Property
Abstract In an optimistic parallel simulation, the global progress (i.e., the global virtual time or GVT) must be computed from time to time. We present a simple and efficient algorithm for computing the GVT in a distributed environment with FIFO communication delays. The accuracy and the complexity of the algorithm are discussed.
16848330
A flexible graphical user interface for performance modeling
We identify three goals for the graphical user interface (GUI) of a network simulation environment: user friendliness, model re-usability, and application extensibility. We address the user friendliness issue by proposing a simple yet efficient approach to setup parameters for the simulation models. We address the application extensibility issue by a two-layer GUI architecture. The two layers are loosely-coupled, and the first layer can be easily replaced (without affecting the other components of the simulation environment). We address the model re-usability issue by subnetworks. Unlike most existing simulation packages where subnetwork is simply a method to group the nodes, the subnetwork construct in our approach is an integral part of the simulation environment (i.e., all operations for a basic node also apply to a subnetwork). The port concept is used to explicitly define the I/O relationship between a subnetwork and the outside world. Parameter dialog boxes are used to set up the parameters for a subnetwork conveniently. Finally, a simple stack mechanism is proposed to measure subnetwork-wide output statistics.<<ETX>>
15619003
A Graphical User Interface Design for Network Simulation
Abstract This article describes a prototyping effort of a flexible graphical user interface (GUI) for a simulation tool called COPS. The GUI is designed to allow parameter setup for all modules in simulation model, and can be easily replaced by new GUIs implemented in different languages/graphical tools. This article provides design guidelines and implementation details of the flexible GUI.
2805042
A new random walk model for PCS networks
This paper proposes a new approach to simplify the two-dimensional random walk models capturing the movement of mobile users in personal communications services (PCS) networks. Analytical models are proposed for the new random walks. For a PCS network with hexagonal configuration, our approach reduces the states of the two-dimensional random walk from (3n/sup 2/+3n-5) to n(n+1)/2, where n is the layers of a cluster. For a mesh configuration, our approach reduces the states from (2n2-2n+1) to (n/sup 2/+2n+4)/4 if n is even and to (n/sup 2/+2n+5)/4 if n is odd. Simulation experiments are conducted to validate the analytical models. The results indicate that the errors between the analytical and simulation models are within 1%. Three applications (i.e., microcell/macrocell configuration, distance-based location update, and GPRS mobility management for data routing) are used to show how our new model can be used to investigate the performance of PCS networks.
16744149
Performance Analysis for Dual Band PCS Networks
In a dual band personal communications services (PCS) network, heavy traffic areas are covered by microcells which overlay macrocells. In such a network, microcells and macrocells utilize different frequency bands. We propose an analytic model to study the performance of a dual band PCS architecture. Our model assumes that a PCS subscriber has a general residence time distribution in a microcell and the macrocell residence time distribution is derived from the microcell residence time distribution. An iterative algorithm is used to compute the overflow traffic from a microcell to its overlaid macrocell. Then, the call incompletion probability is computed by a macrocell model based on the overflow traffic. Our study indicates that the variance of the microcell residence time distribution and the number of microcells covered by a macrocell have significant effects on the call incompletion probability.
5110930
A comparison study of the two-tier and the single-tier personal communications services systems
A two-tier PCS system integrates the high tier PCS system and the low tier PCS systems into a single system to provide the advantages of both tiers. Such a system is expected to provide better service (more available and more cost effective to the users) at the expense of the extra tier switching management. We compare the performance of the two-tier PCS system and the single low tier system in two aspects: the registration traffic and the service availability. Because of the tier management, the two-tier system generates more registration traffic than the single low tier system. Under the range of the input parameters in our study, we show that the two-tier system generates less than 10% extra registration traffic than the single low tier system in most cases and generates less than 20% registration traffic in the worst cases. It is clear that for the service availability, the two-tier system is better than the single one tier system. We also study the probability that a call is forced terminated in the single low tier system because the low tier becomes unavailable during the call (such a call can be continued in the two-tier system).
16475094
A mixture model for estimating the local false discovery rate in DNA microarray analysis
MOTIVATION
Statistical methods based on controlling the false discovery rate (FDR) or positive false discovery rate (pFDR) are now well established in identifying differentially expressed genes in DNA microarray. Several authors have recently raised the important issue that FDR or pFDR may give misleading inference when specific genes are of interest because they average the genes under consideration with genes that show stronger evidence for differential expression. The paper proposes a flexible and robust mixture model for estimating the local FDR which quantifies how plausible each specific gene expresses differentially.


RESULTS
We develop a special mixture model tailored to multiple testing by requiring the P-value distribution for the differentially expressed genes to be stochastically smaller than the P-value distribution for the non-differentially expressed genes. A smoothing mechanism is built in. The proposed model gives robust estimation of local FDR for any reasonable underlying P-value distributions. It also provides a single framework for estimating the proportion of differentially expressed genes, pFDR, negative predictive values, sensitivity and specificity. A cervical cancer study shows that the local FDR gives more specific and relevant quantification of the evidence for differential expression that can be substantially different from pFDR.


AVAILABILITY
An R function implementing the proposed model is available at http://www.geocities.com/jg_liao/software
15077607
A transformation-based method for loop folding
We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported. >
5689495
A hardware accelerator IP for EBCOT tier-1 coding in JPEG2000 standard
We propose a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standard. EBCOT Tier-1 accounts for more than 70% of encoding time due to extensive bit-level processing. Our architecture consists of a 16-way parallel context formation module and a 3-stage pipelined arithmetic encoder. We reduce power consumption by properly shutting down parts of the circuit. Compared with the known best design, we reduce 17% of the cycle count and reach a level within 5% of the theoretical lower bound. We have implemented the design in synthesizable Verilog RTL with an AMBA-AHB interface for SOC design. FPGA prototyping has been successfully demonstrated and substantial speedup achieved.
19539329
Induction and Deduction for Autonomous Networks
The key issues in network management are the representation and sharing of management information and the automatic management mechanisms based on the underlying information infrastructure. The authors propose a framework, which operates on the standard management information base (MIB) and common management information protocol (CMIP), for a network management system with learning and inference as its management engines. In addition to the general domain knowledge, patterns related to the managed network are learned to enhance the understanding of the network and refine the knowledge base. Facts in object-oriented databases or queries from management applications trigger the inference process on logical rules which are either prespecified knowledge or learned network patterns. Forward inference drives prediction and control, while backward inference directs diagnosis and supports view abstraction. A case study on ATM network topology tuning is presented. >
123088
A phase assignment method for virtual-wire-based hardware emulation
In a hardware emulator consisting of multiple field-programmable gate arrays (FPGAs), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time division multiplexing (TDM). TDM allows one physical wire to be shared by multiple logical wires. For TDM to be effective, each transportation of an inter-FPGA signal must be carefully assigned to a slot of the time division. In this note, we show that the phase assignment problem is exactly same as the resource-constrained operation scheduling problem. We adopt the static-list scheduling heuristic for the task, and present some experimental results on a set of benchmark circuits from the MCNC. The experiments show that the proposed method can increase the number of effective I/O pins as many as ten times.