111114972
Commissioning Experience with the ATLAS Level-1 Calorimeter Trigger System
The ATLAS Level-1 Calorimeter Trigger is one of the main elements of the first stage of event selection for the ATLAS experiment at the LHC. The input stage consists of a mixed analogue/digital component taking trigger sums from the ATLAS calorimeters. The trigger logic is performed in a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of physics objects and energy sums. The production of final modules started in 2006, and installation of these modules and the necessary infrastructure at ATLAS has been underway for some time, with the intention of having a full system in situ during 2007, before first collisions at the LHC. The first experiences of commissioning and running the full scale system will be presented, along with results from integration tests performed with the upstream calorimeters, and the downstream trigger and data flow systems.
27359669
The ATLAS level-1 calorimeter trigger architecture
The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em//spl tau/ cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC timing, trigger and control system (TTC). A common data merger module (CMM) uses field-programmable gate arrays (FPGAs) with multiple configurations for summing electron/photon and /spl tau//hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquisition (DAQ) system, and region-of-interest (RoI) data to the level-2 triggers. Extensive use of FPGAs throughout the system makes the trigger flexible and upgradable, and several architectural choices have been made to reduce the number of intercrate links and make the hardware more robust.
122279281
The triumf low energy pion spectrometer and channel
Abstract A low energy pion spectrometer has been developed for use with the TRIUMF M13 pion channel. The combined channel and spectrometer resolution is presently 1.1. MeV at T = 50 MeV. This is limited by the amount of gas and detector material in the spectrometer in addition to the inherent resolution of the channel. Improvements to both the spectrometer and channel are discussed.
15246775
Prototype Readout Module for the ATLAS Level-1 Calorimeter Trigger Processors
The level-1 calorimeter trigger consists of three subsystems, namely the Preprocessor, electron/photon and tau/hadron Cluster Processor (CP), and Jet/Energy-sum Processor (JEP). The CP and JEP will receive digitised calorimeter trigger-tower data from the Preprocessor and will provide trigger multiplicity information to the Central Trigger Processor and region-of-interest (RoI) information for the level-2 trigger. It will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes. This paper will outline a readout system based on FPGA technology, providing a common solution for both DAQ readout and RoI readout for the CP and the JEP. Results of building a prototype readout driver (ROD) module will be presented, together with results of tests on its integration with level-2 and DAQ modules.
122765043
A silicon strip vertex detector for the Mark II experiment at the SLAC linear collider
The design and status of a silicon strip vertex detector for the Mark II experiment at the SLAC Linear Collider are described.
110416746
The Mark II silicon strip vertex detector and performance of a silicon detector telescope in the Mark II detector at the SLC
A silicon strip vertex detector (SSVD) consisting of 36 independent silicon detector modules has been built for use in the Mark II detector at the SLAC Linear Collider (SLC). The performance of the individual modules and the stability and accuracy of their placement in the mechanical support are discussed. Top gain operational experience at the SLC, a telescope made of three silicon detector modules has been assembled and placed inside the Mark II. Results from the first data run of the SLC on the overall performance of the telescope, including backgrounds, charged particle tracking, and spatial resolution, are presented. >
119906527
MEASUREMENT OF THE POLARIZATION PARAMETER IN BACKWARD $pi$$sup +$p ELASTIC SCATTERING AT 1.60, 1.80, 2.11, AND 2.31 GeV/c.
122601142
SVX', the new CDF silicon vertex detector
Abstract The Collider Detector at Fermilab (CDF) radiation hardened silicon vertex detector (SVX') is described. The new detector has several improvements over its predecessor such as better signal to noise and higher efficiency. It is expected to have a radiation tolerance in excess of 1 Mrad. It has been taking data for several months and some preliminary results are shown.
121154652
Spatial resolution of wedge shaped silicon microstrip detectors
Abstract Several wedge-shaped silicon microstrip detectors with pitches from 30 to 100 μm have been designed by our group and beam tested at the CERN SPS. We find the spatial resolution σ becomes larger at the rate of 0.21 μm per 1 μm increase in pitch, but the number of strips per cluster remains about the same as the pitch varies from 30 to 100 μm.