18425238
A compiler for multiple memory models
The design of consistency models for both hardware and software is a difficult task. For a programming language, it is particularly difficult because the target audience for a high-level programming language is much wider than the target audience for a machine language, making usability a more important criterion. Exacerbating this problem is the reality that the programming language community has little experience designing programming language consistency models, and therefore each new attempt is very much a voyage into uncharted territory. A concrete example of the difficulties of the task is the current Java Memory Model. Although designed to be easy to use by Java programmers, it is poorly understood and at least one common idiom (the ‘double check idiom’) to exploit the model is unsafe. In this paper, we describe the design of an optimizing Java compiler that will accept either as input or as an interface implementation a consistency model for the code to be compiled. The compiler will use Shasha and Snir's delay set analysis, and our CSSA program representation to provide a canonical representation for the effects of different consistency models on optimizations and analysis. The compiler will serve as a testbed to prototype new memory models, and to measure the effects of different memory models on program performance. Copyright © 2004 John Wiley & Sons, Ltd.
43332794
Hiding Relaxed Memory Consistency with a Compiler
45872187
Parallel Programming with Polaris
Parallel programming tools are limited, making effective parallel programming difficult and cumbersome. Compilers that translate conventional sequential programs into parallel form would liberate programmers from the complexities of explicit, machine oriented parallel programming. The paper discusses parallel programming with Polaris, an experimental translator of conventional Fortran programs that target machines such as the Cray T3D.
14452578
Automatically mapping code on an intelligent memory architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, the two processors should overlap their execution as much as possible. With our algorithm, applications are mapped fully automatically using both static and dynamic information. Using a set of standard applications and a simulated architecture, we show average speedups of 1.7 for numerical applications and 1.3 for nonnumerical applications over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited and represents one step toward effectively mapping code on intelligent memory systems.
7460855
Automatic Code Mapping on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a high-end host processor and a simpler memory processor. To achieve high performance with this type of architecture, the code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, the two processors should overlap their execution as much as possible. With our algorithm, applications are mapped fully automatically using both static and dynamic information. Using a set of standard applications and a simulated architecture, we obtain average speedups of 1.7 for numerical applications and 1.2 for nonnumerical applications over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited and represents one step toward effectively mapping code on heterogeneous intelligent memory systems.
6606959
Adaptively Mapping Code in an Intelligent Memory Architecture
This paper presents an algorithm to authomatically map code to a generic Processor-In-Memory (PIM) system that consists of a host processor and a much simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, processors should overlap their execution as much as possible. 
 
Our algorithm is embeded in a compiler and run-time system and maps applications fully automatically using both static and dynamic information. Using a set of applications and a simulated architecture, we show average speedups of 1.7 over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited, and represents one step toward effectively mapping code to more advanced PIM systems.
16002222
Isomorphism classes of cycle permutation graphs
Abstract In this paper, we construct a cycle permutation graph as a covering graph over the dumbbell graph, and give a new characterization of when two given cycle permutation graphs are isomorphic by a positive or a negative natural isomorphism. Also, we count the isomorphism classes of cycle permutation graphs up to positive natural isomorphism, and find the number of distinct cycle permutation graphs isomorphic to a given cycle permutation graph by a positive/negative natural isomorphism. As a consequence, we obtain a formula for finding the number of double cosets of the dihedral group in the symmetric group.
12138219
Emergency response after 9/11: the potential of real-time 3D GIS for quick emergency response in micro-spatial environments
Terrorist attacks at the World Trade Center (WTC) in New York City and the Pentagon on September 11, 2001, not only affected multi-level structures in urban areas but also impacted upon their immediate environment at the street level in ways that considerably reduced the speed of emergency response. In this paper, we examine the potential of using real-time 3D GIS for the development and implementation of GIS-based intelligent emergency response systems (GIERS) that aim at facilitating quick emergency response to terrorist attacks on multi-level structures (e.g. multi-story office buildings). We outline a system architecture and a network data model that integrates the ground transportation system with the internal conduits within multi-level structures into a navigable 3D GIS. We examine important implementation issues of GIERS, especially the need for wireless and mobile deployment. Important decision support functionalities of GIERS are also explored with particular reference to the application of network-based shortest path algorithms. Finally, we present the results of an experimental implementation of an integrated 3D network data model using a GIS database of Franklin County, Ohio (USA). Our study shows that response delay within multi-level structures can be much longer than delays incurred on the ground transportation system, and GIERS have the potential for considerably reducing these delays.
16343799
Synchronization with multiprocessor caches
Introducing private caches in bus-based shared memory multiprocessors leads to the cache consistency problem since there may be multiple copies of shared data. However, the ability to snoop on the bus coupled with the fast broadcast capability allows the design of special hardware support for synchronization. We present a new lock-based cache scheme which incorporates synchronization into the cache coherency mechanism. With this scheme high-level synchronization primitives as well as low-level ones can be implemented without excessive overhead. Cost functions for well-known synchronization methods are derived for invalidation schemes, write update schemes, and our lock-based scheme. To accurately predict the performance implications of the new scheme, a new simulation model is developed embodying a widely accepted paradigm of parallel programming. It is shown that our lock-based protocol outperforms existing cache protocols.
6995681
Quasi-optimal case-selective neural network model for software effort estimation
Abstract A number of software effort estimations have attempted using statistical models, case based reasoning, and neural networks. The research results showed that the neural network models perform at least as well as the other approaches, so we selected the neural network model as the estimator. However, since the computing environment changes so rapidly in terms of programming languages, development tools, and methodologies, it is very difficult to maintain the performance of estimation models for the new breed of projects. Therefore, we propose a search method that finds the right level of relevant cases for the neural network model. For the selected case set, the scale of the neural network model can be reduced by eliminating the qualitative input factors with the same values. Since there exist a multitude of combinations of case sets, we need to search for the optimal reduced neural network model and corresponding case set. To find the quasi-optimal model from the hierarchy of reduced neural network models, we adopted the beam search technique and devised the case-set selection algorithm. We have shown that the resulting model significantly outperforms the original full model for the software effort estimation. This approach can be also used for building any case-selective neural network.
17462310
Bipartite covering graphs
Abstract In this paper we study when a bipartite graph is a covering of a non-bipartite graph. We give a characterization of all bipartite coverings in terms of factoring the covering map through the canonical double covering. We also consider regular bipartite coverings described in terms of voltage assignments. We give an algebraic characterization of such coverings involving the subgroup generated by voltages on closed walks of even length. This allows us to count the number of regular bipartite coverings for orders which are twice a prime.