29667666
Building a distributed asynchronous control unit through automatic derivation of hierarchically decomposed AFSMs from a CDFG
Although there are several successful asynchronous logic synthesis tools, it is still unwieldy for designers to conceive and describe behaviors for a number of controllers constituting an asynchronous control unit of a target system manually. In this paper, building a distributed asynchronous control unit automatically through automatic derivation of hierarchically decomposed AFSMs from a CDFG is suggested. A resulting control unit consists of small asynchronous controllers and has complete separation of 'execution controllers' and 'execution order controllers'. This distributive feature leads to significant improvements in the aspects of area, performance and synthesis time of derived control circuits.
28781309
Automatic process-oriented control circuit generation for asynchronous high-level synthesis
As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method, so called process-oriented method, which generates distributed asynchronous control circuits automatically in a hierarchical and systematic manner is suggested as part of an AHLS tool. Experimental results show that the suggested method is efficient in the aspects of area and performance of derived control circuits.
7800252
Imprecise data computation for high performance asynchronous processors
Instruction level parallelism(ILP) is strictly limited by various dependencies. In particular , data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show the performance benefits of the suggested computing model, simulation results are presented. The imprecise computation can be used effectively in data intensive processing with a microprocessor, a Digital Signal Processor or a multimedia processor.
1336097
Distributed synchronous control units for dataflow graphs under allocation of telescopic arithmetic units
In order to enjoy the performance improvement effects of variable computation time arithmetic units at a system level, we propose a new synchronous control unit design methodology for dataflow graphs under allocation of a telescopic arithmetic unit, which is one of the well-known synchronous variable computation time arithmetic units. The proposed method generates an independent synchronous controller for each component arithmetic unit, and builds a distributed synchronous control unit through integrating the derived controllers. The distributed structure of the final synchronous control unit maximizes the performance improvement effect of telescopic arithmetic units through a complete preservation of original concurrency among operations.
9094168
Microscopic examination of TCP flows over transatlantic links
Much of the recent research and development in the area of high-speed TCP is focused on the steady state behavior of TCP flows. However, our experience with the first research only transatlantic 2.5 Gbps Lambda link clearly demonstrates the need to focus on the initial stages of TCP. The work we present here examines the behavior of TCP flows at microscopic level over high-bandwidth long delay networks. This examination has led us to study the influence of the minute properties of the underlying network on bursty protocols such as TCP at these very high speeds combined with high latency. In this paper we briefly describe the requirements for such an extreme network environment to support high-speed TCP flows. We also present results collected using transatlantic links at iGrid2002 where we tuned various host parameters and used modified TCP stacks.
7796564
CFLRU: a replacement algorithm for flash memory
In most operating systems which are customized for disk-based storage system, the replacement algorithm concerns only the number of memory hits. However, flash memory has different read and write cost in the aspects of time and energy so the replacement algorithm with flash memory should consider not only the hit count but also the replacement cost caused by selecting dirty victims. The replacement cost of dirty page is higher than that of clean page with regard to both access time and energy consumption. In this paper, we propose the Clean-First LRU (CFLRU) replacement algorithm that exploits the characteristics of flash memory. CFLRU splits the LRU list into the working region and the clean-first region and adopts a policy that evicts clean pages preferentially in the clean-first region until the number of page hits in the working region is preserved in a suitable level. Using the trace-driven simulation, the proposed algorithm reduces the average replacement cost by 28.4% in swap system and by 26.2% in buffer cache, compared with LRU algorithm. We also implement the CFLRU algorithm in the Linux kernel and present some optimization issues.
7491965
Modeling and analyzing the impact of location inconsistencies on geographic routing in wireless networks
Recently, geographic routing in wireless networks has gained attention due to several advantages of location information. Location information eliminates the necessity to set up and maintain explicit routes, which reduces communication overhead and routing table size. These advantages allow scalability especially in dynamic and unstable wireless networks. However, no matter which technologies or techniques a location system uses, its measurements will have some amount of quantifiable inaccuracy depending on environment and system. These inaccuracies may affect the performance and even correctness of geographic routing. However, thus far, these impacts have not been studied in-depth. In this paper, we analyze the impact of location inaccuracy on geographic routing. First, we model location inaccuracy metrics - absolute location inaccuracy, relative distance inaccuracy, absolute location inconsistency and relative distance inconsistency. Then, we analyze how location inaccuracy metrics affect the building blocks of geographic routing including greedy forwarding and local maximum resolution. We use extensive NS-2 simulations to evaluate the performance of geographic routing using a wide array of parameter settings including inaccuracy level, node degree and network diameter. In our simulation results, reasonable location inaccuracy (of 20 percent or less of radio range) caused packet drop reaching up to 54 percent, non-optimal path up to 53 percent and packet looping. These observations indicate the importance of re-visiting geographic routing protocols, and the significance of considering location inaccuracy in their design and evaluation.
1519617
Distributed parallel data storage systems: a scalable approach to high speed image servers
We have designed, built, and analyzed a distributed parallel storage system that will supply image streams fast enough to permit multi-user, “real-time”, video-like applications in a wide-area ATM network-based Internet environment. We have based the implementation on user-level code in order to secure portability; we have characterized the performance bottlenecks arising from operating system and hardware issues, and based on this have optimized our design to make the best use of the available performance. Although at this time we have only operated with a few classes of data, the approach appears to be capable of providing a scalable, high-performance, and economical mechanism to provide a data storage system for several classes of data (including mixed multimedia streams), and for applications (clients) that operate in a high-speed network environment.
17910425
TMO-structured distributed location information system prototype
To realize location-based services, it is essential to handle the extreme situation that must cope with a very large volume, at least millions, of moving items. In this paper, we describe a location information system prototype of GALIS, which is a cluster-based scalable distributed computing system architecture which consists of multiple data processors, each dedicated to keeping records relevant to a different geographical zone and a different time zone. The proposed system contains all of the major computing nodes of GALIS architecture and is developed as a middleware on top of commercial main-memory database engines and spatial database engines, for short-term data and long-term data processing, respectively. To show the usefulness of our system, some experimental results showing clear advantages of distributed computing are also explained.