16061427
A wide-field direction-selective aVLSI spiking neuron
We describe an analog Very-Large-Scale Integrated (aVLSI) wide-field direction-selective spiking neuron that responds robustly to both natural and artificial images. The circuitry is based on a model of the wide-field direction-selective neurons in the fly visual system. The architecture of the chip closely follows the anatomical layout of the fly visual system. The circuit has a one-dimensional array of 37 elementary motion detectors (EMDs); each of which provides local motion information to the wide-field spiking neuron. Normalisation and adaptation are employed in the circuits at each processing stage. The inputs to the EMDs saturate with high contrasts so that the motion output is not confounded with the signal contrast. The outputs of the EMDs are aggregated in a nonlinear way to produce a motion output that is independent of the stimulus size. The global aggregated signal is then used to drive an integrate-and-fire neuron. All the computation is analog except for the output of the spiking neuron. We show results from the fabricated circuit.
34951314
Spike synchronization in a network of silicon integrate-and-fire neurons
Spike-event based computational processing by neuronal networks depends on a variety of spatio-temporal mechanisms that are distributed across neuronal synapses, dendrites, and somata. The overall processing of spatio-temporal patterns of spike requires global temporal coherence between all these processes both within a neuron, and across all neurons of the network. We are evaluating the use of networks of hybrid analog-digital integrate-and-fire neurons, fabricated using VLSI, for studying real-time event-based processing. These hardware networks have the advantages of real-time operation, and inherent global synchronization by their analog implementation. However, one of the technical challenges in the operation of such networks is the unavoidable fabrication related variance between the different neurons of the network. Here we show that despite this variance, an important behavior of neuronal networks, spike synchronization, can be obtained from a simple network of VLSI neurons interconnected by lateral excitation and global inhibition.
1845062
Adaptive Retina with Center-Surround Receptive Field
Both vertebrate and invertebrate retinas are highly efficient in extracting contrast independent of the background intensity over five or more decades. This efficiency has been rendered possible by the adaptation of the DC operating point to the background intensity while maintaining high gain transient responses. The center-surround properties of the retina allows the system to extract information at the edges in the image. This silicon retina models the adaptation properties of the receptors and the antagonistic center-surround properties of the laminar cells of the invertebrate retina and the outer-plexiform layer of the vertebrate retina. We also illustrate the spatio-temporal responses of the silicon retina on moving bars. The chip has 59×64 pixels on a 6.9×6.8mm2 die and it is fabricated in 2 µm n-well technology.
6979172
Encoding the Temporal Statistics of Markovian Sequences of Stimuli in Recurrent Neuronal Networks
Encoding, storing, and recalling a temporal sequence of stimuli in a neuronal network can be achieved by creating associations between pairs of stimuli that are contiguous in time. This idea is illustrated by studying the behavior of a neural network model with binary neurons and binary stochastic synapses. The network extracts in an unsupervised manner the temporal statistics of the sequence of input stimuli. When a stimulus triggers the recalling process, the statistics of the output patterns reflects those of the input. If the sequence of stimuli is generated through a Markov process, then the network dynamics faithfully reproduces all the transition probabilities.
18592302
A Winner-Take-All Circuit with Controllable Soft Max Property
I describe a silicon network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths. This output models the normalization property of the wide-field direction-selective cells in the fly visual system. This normalizing property is also useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit with one additional transistor and a voltage reference. Just as in Lazzaro's circuit, the outputs of the excitatory neurons code the neuron with the largest input. The difference here is that multiple winners can be chosen. By varying the voltage reference of the neuron, the network can transition between a soft-max behavior and a hard WTA behavior. I show results from a fabricated chip of 20 neurons in a 1.2 µm CMOS technology.
12793172
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 /spl mu/m CMOS technology are in agreement with the analysis.<<ETX>>
15677254
Inference Queues for Communicating and Monitoring Declarative Information between Web Services
We introduce the inference queue as a mechanism for communicating and transforming data in Web services choreography. The insert operation provides definite clauses to the inference queue, and the remove operation generates output that is sound, complete, fair, and irredundant. Both operations are thread safe and responsive. The inference queue can form part of a highly configurable data transformation system. Rules can also monitor for events of interest based on the occurrence of certain conditions. Our suggestion of system wide monitoring of communication is complementary to existing Web services proposals.
16252718
QoSPL: A QoS-Driven Software Product Line Engineering Framework for Distributed Real-time and Embedded Systems
The current synergy of Component-Based Software Engineering (CBSE) and Software Product Line Engineering (SPLE) requires evolution to facilitate Distributed Realtime and Embedded (DRE) system construction. Such evolution is driven by inherent Quality of Service (QoS) characteristics in DRE systems. This paper introduces a QoSdriven SPLE framework (QoSPL) as an analysis and design paradigm for constructing a set of DRE systems as a product line. Leveraging separation of concerns, DRE systems are analyzed and designed by a collection of QoS systemic paths, each of which individually determines how well the service performs along the path and as a whole represents a behavioral view of software architecture. The paradigm reduces construction workload from the problems of tangled functional and QoS requirements and abundant infeasible design alternatives, and offers a less subjective QoS evaluation. The adopted formalisms also facilitate high-confidence DRE product line construction.
14652555
Adding multi-class routing into the DiffServ architecture
To alleviate the problem of high priority traffic hogging of all the available network capacity and to optimize the network traffic in the DiffServ network, we introduce the multi-class routing (MCR) scheme into the DiffServ architecture. The MCR scheme that builds multiple routing tables in the DiffServ routers forms the MCR DiffServ architecture. In this paper, the MCR DiffServ architecture focuses on the intra-DS domain. Different MCR approaches that include a static approach and dynamic approaches can be used for the MCR DiffServ system. We extend the OSPF protocol in order to build up more than one routing table in each MCR DiffServ system. According to the extensions to OSPF, we have implemented the static MCR approach for the MCR DiffServ system on the basis of the open source Zebra software.
1399991
Validation of Distributed Real-Time and Embedded System composition in UniFrame
Distributed Real-Time and Embedded (DRE) Systems are widely applied to large scale and mission critical application domains such as avionics systems and medical imaging. Due to the rapid lifecycle and the complexity of design of the systems, there is an urgent demand to manage the development of robust, COTS, and effective software for vendors. The UniFrame project is a unified framework for seamless integration of distributed heterogeneous software components. This paper describes how the UniFrame approach is applicable to DRE software components. Leveraging the Two-Level Grammar (TLG) specification language and the Vienna Development Method (VDM), a formal methodology for developing DRE components and system code generation is developed for UniFrame.
18693305
Verifying Consistency and Validity of Formal Specifications by Testing
Detecting faults in specifications can help reduce the cost and risk of software development because incorrect implementation can be prevented early. This goal can be achieved by verifying the consistency and validity of specifications. In this paper we put forward specification testing as a practical technique for verification and validation of formal specifications. Our approach is to derive proof obligations from a specification and then test them, in order to detect faults leading to the violation of consistency or validity of the specification. We describe proof obligations for various consistency properties of a specification, and suggest the use of five strategies for testing them. We provide a method for testing implicit specifications by evaluation rather than by prototyping, and criteria for interpreting the meaning of test results.