8549309
Wire length prediction in constraint driven placement
Experiments show that lengths of individual wires are different for different placement algorithms. To achieve accurate wire length prediction, some knowledge of a placer's details is necessary. We postulate that wire length prediction should be coupled with placement flow to obtain accurate results. In this paper, we embed wire length prediction into our constraint-driven placer, developed in Fast Placer Implementation (FPI) framework [15]. We predict individual wire lengths during the clustering step. The predicted wire lengths act as constraints for the simulated annealing refinement stage, which guides the placement towards a solution fulfilling the predictions. Experimental results show that our wire length prediction process yields accurate results without quality loss at a small cost of placement effort. This is the first time that constraints have been used to guide placement and thus increase the accuracy of wire length prediction.
17618621
Semi-individual wire-length prediction with application to logic synthesis
A new concept for wire-length prediction, the semi-individual wire-length prediction, is introduced. Structural metrics, such as mutual contraction and net range, are used to predict which interconnects have a tendency to be long or short in the final layout. The very good correlation of the prelayout measures with the postlayout interconnect lengths is demonstrated. The prelayout wire-length-prediction techniques are applied in logic synthesis, targeting wiring cost, and congestion minimization. This paper focuses on technology mapping and fan-out optimization. Experiments on LGSyn93 and ITC'99 benchmark suites show that the wire-length-prediction-based technology mapping and fan-out-optimization algorithms produce layout-friendly netlists. After placement and global routing, the netlists yield smaller total wire length, are more routable, and achieve better timing than the netlists obtained using traditional logic-synthesis flow in SIS.
86206
Wire length prediction-based technology mapping and fanout optimization
In modern VLSI systems early wire optimization is essential in achieving required performance, routability, and power. The cost functions optimized during traditional logic synthesis do not capture interconnect effects, which may lead to sub-optimal designs. In this paper, we propose a method for applying pre-layout wire-length prediction techniques in logic synthesis, targeting wiring cost and ways to minimize congestion. Specifically, we focus on technology mapping and fanout optimization. Experimental results show that our wire-length-prediction-based technology mapping (WP-Map) and fanout optimization (WP-Fanout) result in 8.7% improvement in average congestion, 17.2% improvement in peak congestion, and 3.3% improvement in timing performance.
15497881
A congestion-driven placement framework with local congestion prediction
In this paper, we present a novel congestion-driven placement methodology. We analyze netlist structure and perform local congestion prediction to determine the amount of white space which will be attached to each cell. We place the modified netlist using a total-wire-length-driven placer and obtain an initial legal placement. We extract the congestion information and determine the target white space distribution. Finally, we apply placement migration, an incremental placement technique, to transform the initial placement into a placement which satisfies the target white space distribution. We provide experimental data to demonstrate the effectiveness of our congestion driven placement framework. Compared with the recent academic routability-driven placer Dragon [12], we achieve significant routability improvements in much shorter cpu run time.
8945696
Synthesis and placement flow for gain-based programmable regular fabrics
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gain-based Logic Blocks (GLBs). The GLB is a semi-universal logic block designed based on logical effort theory[12]. Customization of the GLBs is provided by programmable vias. To achieve the best performance, appropriate fabric has to be selected from a family of GLAs with different performance-area trade-offs. We describe a synthesis and placement flow which, for a given design to be implemented, allows us to select the best GLA from the candidate family.
10460404
Pre-layout wire length and congestion estimation
In this paper, we study the pre-layout wire length and congestion estimation. We find that two structural metrics, mutual contraction and net range, can be used to predict wire lengths. These metrics have different application ranges and complement each other. We also propose a new metric, the structural pin density, to capture the peak routing congestion of designs. Larger maximum pin densities usually lead to larger peak congestions in circuits with similar average congestions. We demonstrate experimentally very good correlation of our pre-layout measures with post layout interconnect lengths. We also isolate the structural netlist properties which cause the peak congestion.
32477053
lambda-Level Rough Equality Relation and the Inference of Rough Paramodulation
In the paper, it defines a λ-level rough equality relation in rough logic and establishes a rough sets on real-valued information systems with it. We obtain some related properties and relative rough paramodulation inference rules. They will be used in the approximate reasoning and deductive resolutions of rough logic. Finally, it proves that λ-level rough paramodulant reasoning is sound.
3992721
Error minimization in approximate range aggregates
Histogram techniques have been used in many commercial database management systems to estimate a query result size. Recently, it has been shown that they are very effective to support approximation of query processing especially aggregates. In this paper, we investigate the problem of minimizing average errors of approximate aggregates using histogram techniques. Firstly, we present a novel linear-spline histogram model that is more accurate than the existing models. Secondly, we propose a novel histogram construction technique for minimizing such average errors, which is shown to generate a near optimal histogram. Our experiment results demonstrate that the new histogram construction techniques lead to a great accuracy improvement on the existing techniques.
15319550
Log-Linear Models for Word Alignment
We present a framework for word alignment based on log-linear models. All knowledge sources are treated as feature functions, which depend on the source language sentence, the target language sentence and possible additional variables. Log-linear models allow statistical alignment models to be easily extended by incorporating syntactic information. In this paper, we use IBM Model 3 alignment probabilities, POS correspondence, and bilingual dictionary coverage as features. Our experiments show that log-linear models significantly outperform IBM translation models.
2285434
Towards multidimensional subspace skyline analysis
The skyline operator is important for multicriteria decision-making applications. Although many recent studies developed efficient methods to compute skyline objects in a given space, none of them considers skylines in multiple subspaces simultaneously. More importantly, the fundamental problem on the semantics of skylines remains open: Why and in which subspaces is (or is not) an object in the skyline? Practically, users may also be interested in the skylines in any subspaces. Then, what is the relationship between the skylines in the subspaces and those in the super-spaces? How can we effectively analyze the subspace skylines? Can we efficiently compute skylines in various subspaces and answer various analytical queries?In this article, we tackle the problem of multidimensional subspace skyline computation and analysis. We explore skylines in subspaces. First, we propose the concept of Skycube, which consists of skylines of all possible nonempty subspaces of a given full space. Once a Skycube is materialized, any subspace skyline queries can be answered online. However, Skycube cannot fully address the semantic concerns and may contain redundant information. To tackle the problem, we introduce a novel notion of skyline group which essentially is a group of objects that coincide in the skylines of some subspaces. We identify the decisive subspaces that qualify skyline groups in the subspace skylines. The new notions concisely capture the semantics and the structures of skylines in various subspaces. Multidimensional roll-up and drill-down analysis is introduced. We also develop efficient algorithms to compute Skycube, skyline groups and their decisive subspaces. A systematic performance study using both real data sets and synthetic data sets is reported to evaluate our approach.
45863395
First Order Rough Logic-Revisited
Based on axiomatic rough set theory, first order rough logic was developed earlier. In this paper, a new model theory for that logic is introduced. With this new semantic, first order rough logic is shown to be equivalent to first order S5, and hence consistent and complete.