6606959
Adaptively Mapping Code in an Intelligent Memory Architecture
This paper presents an algorithm to authomatically map code to a generic Processor-In-Memory (PIM) system that consists of a host processor and a much simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, processors should overlap their execution as much as possible. 
 
Our algorithm is embeded in a compiler and run-time system and maps applications fully automatically using both static and dynamic information. Using a set of applications and a simulated architecture, we show average speedups of 1.7 over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited, and represents one step toward effectively mapping code to more advanced PIM systems.
5993695
Correlation Prefetching with a User-Level Memory Thread
This paper proposes using a user-level memory thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: The correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide applicability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
45872187
Parallel Programming with Polaris
Parallel programming tools are limited, making effective parallel programming difficult and cumbersome. Compilers that translate conventional sequential programs into parallel form would liberate programmers from the complexities of explicit, machine oriented parallel programming. The paper discusses parallel programming with Polaris, an experimental translator of conventional Fortran programs that target machines such as the Cray T3D.
7460855
Automatic Code Mapping on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a high-end host processor and a simpler memory processor. To achieve high performance with this type of architecture, the code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, the two processors should overlap their execution as much as possible. With our algorithm, applications are mapped fully automatically using both static and dynamic information. Using a set of standard applications and a simulated architecture, we obtain average speedups of 1.7 for numerical applications and 1.2 for nonnumerical applications over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited and represents one step toward effectively mapping code on heterogeneous intelligent memory systems.
43332794
Hiding Relaxed Memory Consistency with a Compiler
46430091
Design of VDSL Networks for the High Speed Internet Services
VDSL is recently getting more attention as the efficient xDSL technology. VDSL can be used for next generation Grid computing. Because VDSL is last mile network, they designed multimedia supplying VDSL networks through combining it with core network or access network properly. Core network was designed with IP network and ATM network and simulated through COMNET. In the measure result (Bit rate, Delay) of the simulation, we knew that IP network is superior to ATM network in terms of measure result.
7800252
Imprecise data computation for high performance asynchronous processors
Instruction level parallelism(ILP) is strictly limited by various dependencies. In particular , data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show the performance benefits of the suggested computing model, simulation results are presented. The imprecise computation can be used effectively in data intensive processing with a microprocessor, a Digital Signal Processor or a multimedia processor.
9196724
STRG-Index: spatio-temporal region graph indexing for large video databases
In this paper, we propose new graph-based data structure and indexing to organize and retrieve video data. Several researches have shown that a graph can be a better candidate for modeling semantically rich and complicated multimedia data. However, there are few methods that consider the temporal feature of video data, which is a distinguishable and representative characteristic when compared with other multimedia (i.e., images). In order to consider the temporal feature effectively and efficiently, we propose a new graph-based data structure called Spatio-Temporal Region Graph (STRG). Unlike existing graph-based data structures which provide only spatial features, the proposed STRG further provides temporal features, which represent temporal relationships among spatial objects. The STRG is decomposed into its subgraphs in which redundant subgraphs are eliminated to reduce the index size and search time, because the computational complexity of graph matching (subgraph isomorphism) is NP-complete. In addition, a new distance measure, called Extended Graph Edit Distance (EGED), is introduced in both non-metric and metric spaces for matching and indexing respectively. Based on STRG and EGED, we propose a new indexing method STRG-Index, which is faster and more accurate since it uses tree structure and clustering algorithm. We compare the STRG-Index with the M-tree, which is a popular tree-based indexing method for multimedia data. The STRG-Index outperforms the M-tree for various query loads in terms of cost and speed.
316350
Dynamic Repartitioning of Real-Time Schedule on a Multicore Processor for Energy Efficiency
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as the performance requirements are increasing. Though DVS may reduce power consumption for hard real time applications on single core processors, it introduces a new implication for multicore systems since all the cores in a chip should run at the same performance. Blind adoption of existing DVS algorithms may result in waste of energy since a core which requires low performance should run at the same high frequency with other cores. Based on the existing partitioning algorithms for the multiprocessor hard real-time scheduling, this article presents dynamic task repartitioning algorithm that balances task loads among cores to avoid the phenomena dynamically during execution. Simulation results show that in general cases our scheme makes additional energy saving more than 10% than that without our scheme even when the schedules are generated by WFD partitioning algorithm which is known as the best energy efficient partitioning algorithm.
6969387
Case- and Constraint-Based Project Planning for Apartment Construction
To effectively generate a fast and consistent apartment construction project network, Hyundai Engineering and Construction and Korea Advanced Institute of Science and Technology developed a case- and constraint-based project-planning expert system for an apartment domain. The system, FAS-TRAK- APT, is inspired by the use of previous cases by a human expert project planner for planning a new project and the modification of these cases by the project planner using his/her knowledge of domain constraints. This large-scale, case-based, and mixed-initiative planning system, integrated with intensive constraint-based adaptation, utilizes semantic-level metaconstraints and human decisions for compensating incomplete cases imbedding specific planning knowledge. The case- and constraint-based architecture inherently supports cross-checking cases with constraints during system development and maintenance. This system has drastically reduced the time and effort required for initial project planning, improved the quality and completeness of the generated plans, and is expected to give the company the competitive advantage in contract bids for new contracts.
34616590
On the dynamic model and kinematic analysis of a class of Stewart platforms
Abstract In this paper, a dynamic model for a class of Stewart platform (six degrees of freedom parallel link robotic manipulators) is derived by using tensor representation. A set of six Lagrange's equations are obtained. The kinematics analysis for a class of Stewart platform is conducted and a sixteenth order polynomial equation corresponding to the forward kinematic solution of the Stewart platform is obtained, which gives all possible global solutions of a manipulator configuration for a given set of six leg lengths.