188423
Report on the INEX 2004 interactive track
As scientific data repositories, digital libraries and publishers increasingly use the eXtensible Markup Language (XML) for publication and storage interest has arisen in exploiting this formatting for retrieval purposes. XML is attractive because it defines the logical structure of the documents and has the potential to assist IR systems in providing more appropriate results to users, i.e., to return relevant document components (i.e. XML elements) rather than whole documents. In addition, the XML tags often have specific semantics that may be exploited purposefully in IR.
41842092
The Interactive Track at INEX 2005
In its second year, the Interactive Track at INEX focused on addressing some fundamental issues of interactive XML retrieval: is element retrieval useful for searchers, what granularity of elements do searchers find more useful, what applications for element retrieval can be viable in interactive environments, etc.. In addition, the track also expanded by offering an alternative document collection, by including two additional tasks, and by attracting more participating groups: A total of 11 research groups and 119 test persons participated in the three different tasks that were included in the track. In this paper, we describe the main issues that the Interactive Track at INEX 2005 attempts to address and the methodology and tasks that were used in the track.
2473916
A Case for Runtime Validation of Hardware
Increasing hardware design complexity has resulted in significant challenges for hardware design verification. The growing “verification gap” between the complexity of what we can verify and what we can fabricate/design is indicative of a crisis that is likely to get only worse with increasing complexity. A variety of methodology and tool solutions have been proposed to deal with this crisis, but there is little optimism that a single solution or even a set of cooperative solutions will be scalable to enable future design verification to be cost effective. It is time we reconcile ourselves to the fact that hardware, like software, will be shipped with bugs in it. One possible solution to deal with this inevitable scenario is to provide support for runtime validation that detects functional failures at runtime and then recovers from such failures. Such runtime validation hardware will increasingly be used to handle dynamic operational failures caused by reduced reliability of devices due to large process variations as well as increasing soft errors. Expanding the use of such hardware to deal with functional design failures provides for an on-chip insurance policy when design errors inevitably slip through the verification process. This paper will discuss the strengths and weaknesses of this form of design validation, some possible forms this may take, and implications on design methodology.
14915367
Processor evaluation in an embedded systems design environment
In this paper we present a novel methodology for processor evaluation in an embedded systems design environment. This evaluation can help in either selecting a suitable processor core or in evaluating changes to an ASIP. The processor evaluation is carried out in two stages. First, an architecture independent stage in which processors are rejected based on key application parameters and secondary architecture dependent stage in which performance is estimated on selected processors. The contribution of our work includes identification of application parameters which can influence processor selection, a mechanism to capture widely varying processor architectures and an instruction constrained scheduler. Initial experimental results suggest the potential of this approach.
53240163
Optimal code generation for embedded memory non-homogeneous register architectures
This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,/spl infin/] model. Optimality is guaranteed by sufficient conditions derived from the register transfer graph (RTG), a structural representation of the architecture which depends exclusively on the processor instruction set architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.
195863977
Using reconfigurable computing techniques to accelerate problems in the CAD domain: a case study with Boolean satisfiability
The Boolean satisfiability problem lies at the core of several CAD applications, including automatic test pattern generation and logic synthesis. This paper describes and evaluates an approach for accelerating Boolean satisfiability using configurable hardware. Our approach harnesses the increasing speed and capacity of field-programmable gate arrays by tailoring the SAT-solver circuit to the particular formula being solved. This input-specific technique gets high performance due both to (i) a direct mapping of Boolean operations to logic gates, and (ii) large amounts of fine grain parallelism in the implication processing. Overall, these strategies yields impressive speedups (>200/spl times/ in many cases) compared to current software approaches, and they require only modest amounts of hardware. In a broader sense, this paper alerts the hardware design community to the increasing importance of input-specific designs, and documents their promise via a quantitative study of input-specific SAT solving.