2713872
A BIST scheme for on-chip ADC and DAC testing
In this paper we present a BIST scheme for testing on-chip A/D and D/A converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation-5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.
11615380
A sigma-delta modulation based BIST scheme for mixed-signal circuits
In this work, we present the analysis of a built-in self-test (BIST) scheme for mixed-signal circuits that is intended to provide on-chip stimulus generation and response analysis. Based on the sigma-delta modulation principle, the proposed scheme can produce high-quality stimuli and obtain accurate measurements without the need of precise analog circuitry. Numerical simulations are conducted to validate our idea and the results show that the scheme is a promising BIST approach for mixed-signal circuits.
14811510
Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits
In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing fault simulation only locally for the fault block. Simulation results on an industrial design show a speedup factor of 7.2 with 98% correct classification of detected and undetected faults as compared with full-chip DC fault simulation.
9736317
Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test
In this paper, we characterize and evaluate the effectiveness of a pseudo-random-based implicit functional testing technique for analog and mixed-signal circuits. The analog test problem is transformed into the digital domain by embedding the device-under-test (DUT) between a digital-to-analog-converter and an analog-to-digital converter. The pseudo-random testing technique uses band-limited digital white noise (pseudo-random-patterns) as input stimulus. The signature is constructed by computing the cross-correlation between the digitized output response and the pseudo-random input sequence. We have implemented a DSP-based hardware testbed to evaluate the effectiveness of the pseudo-random testing technique. Our results show that we can achieve close to 100% yield and fault coverages by carefully selecting only two cross-correlation samples. Noise level and total harmonic distortion below 0.1% and 0.5%, respectively, do not affect the classification accuracy.
12035723
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis
Delta-sigma modulation has become popular in modern analog-to-digital modulator design due to its relatively high immunity from process variations. We propose efficient characterization techniques to obtain the key performance parameters of the 1-bit first-order delta-sigma modulator which is intended to be used as an on-chip analog signal digitizer for BIST applications. Numerical simulations have been performed to validate the techniques and the results indicate that accurate estimation of the parameters can be obtained at the presence of noise.
15852893
The swisshouse: an inhabitable interface for connecting nations
We present the Swisshouse, a novel type of "inhabitable interface" that supports direct and indirect communication and cultural awareness of habitants in different nations. The Swisshouse allows unsophisticated users to collaborate and be aware of each other over distance. By carefully sculpting the space and choreographing interactive elements in the space, the Swisshouse allows users to instantly separate, combine, and customize environments for specific collaborative activities. By providing visual representations of remote users and places, the Swisshouse provides awareness of the culture, presence and identities of virtual participants. And by tagging physical users with RFID tags, the Swisshouse makes participants aware of the social interaction occurring in the physical space. The combination of these primitives provides a single consistent inhabitable interface that integrates architectural and user interface design thinking, hardware and software design. To illustrate the power of this convergent approach, we describe several examples of real-life applications including a remote lecture, a brainstorming session, a business meeting, and an exhibition.
36043890
Remote Visualization by Browsing Image Based Databases with Logistical Networking
8925570
Auction-Based Spectrum Sharing
We study auction mechanisms for sharing spectrum among a group of users, subject to a constraint on the interference temperature at a measurement point. The users access the channel using spread spectrum signaling and so interfere with each other. Each user receives a utility that is a function of the received signal-to-interference plus noise ratio. We propose two auction mechanisms for allocating the received power. The first is an auction in which users are charged for received SINR, which, when combined with logarithmic utilities, leads to a weighted max-min fair SINR allocation. The second is an auction in which users are charged for power, which maximizes the total utility when the bandwidth is large enough and the receivers are co-located. Both auction mechanisms are shown to be socially optimal for a limiting “large system” with co-located receivers, where bandwidth, power and the number of users are increased in fixed proportion. We also formulate an iterative and distributed bid updating algorithm, and specify conditions under which this algorithm converges globally to the Nash equilibrium of the auction.
37411387
Automatic generation of memory built-in self-test cores for system-on-chip
Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
7193109
An object-oriented architecture supporting Web application testing
The flexibility and rich application frameworks of the Web model make Web applications more prevalent in both Internet and intranet environments. Programmers enjoy various Web application frameworks with support ranging from simple user interactions based on the plain client-server model, to complicated distributed-object computations based on CORBA. The variety gives users the flexibility to decide a proper framework, and leads to demands for new support tools and a testing framework to test and maintain Web applications. This paper presents an architecture containing several supporting tools which enhance traditional software testing architecture to fit common Web application frameworks. The architecture suits current Web models and reuses several software patterns and architectures from traditional testing environments. In addition, a prototype Web application testing environment is constructed for demonstration.