11078936
Software architecture supporting integrated real-time systems
To achieve reliability, reusability, and cost reduction, a significant trend in building large complex real-time systems is to integrate separate application modules of different criticalities in a common hardware platform. An essential requirement of integrated real-time systems is to guarantee spatial and temporal partitioning among applications in order te ensure an exclusive access of physical and temporal resources to the applications. In this paper we propose software architecture, implemented as SPIRIT-µKernel, for strongly partitioned integrated real-time systems. The SPIRIT-µKernel has been designed and implemented based on a two-level hierarchical scheduling methodology such that the real-time constraints of each application can be guaranteed. To demonstrate the feasibility of the SPIRIT-µKernel, we have ported two real-time operating systems (RTOS), WindRiver's VxWorks and Cygnus's eCos, on the top of the microkernel. Thus, different RTOS can be applied in various partitions to provide required features for each application. Based on the measured performance results, the SPIRIT-µKernel architecture is practical and appealing due to its low overheads of kernel services and the support for dependable integration of real-time applications via scheduling algorithm.
920212
Resource scheduling in dependable integrated modular avionics
In the recent development of avionics systems, integrated modular avionics (IMA) is advocated for next generation architecture that needs integration of mixed criticality real-time applications. These integrated applications meet their own timing constraints while sharing avionics computer resources. To guarantee timing constraints and dependability of each application, an IMA-based system is equipped with the schemes for spatial and temporal partitioning. We refer the model as SP-RTS (strongly partitioned real-time system), which deals with processor partitions and communication channels as its basic scheduling entities. This paper presents a partition and channel-scheduling algorithm for the SP-RTS. The basic idea of the algorithm is to use a two-level hierarchical schedule that activates partitions (or channels) following a distance-constraints guaranteed cyclic schedule and then dispatches tasks (or messages) according to a fixed priority schedule. To enhance schedulability, we devised heuristic algorithms for deadline decomposition and channel combining. The simulation results show the schedulability analysis of the two-level scheduling algorithm and the beneficial characteristics of the proposed deadline decomposition and channel combining algorithms.
12406392
Measurement and Application of Fault Latency
The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate effects impossible. To remedy this deficiency, we 1) present a new methodology for indirectly measuring fault latency, 2) derive the distribution of fault latency from the methodology, and 3) apply the knowledge of fault latency to the analysis of two important examples.
30590203
Efficient State-Saving Architectures for Power-Mode Switching
Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce switching speed and energy. We present a heuristic to save the most relevant cache contents so that power and delay overheads are minimized. To measure the area overhead a synthesizable VHDL model was designed.
206579905
Improving multistage network performance under uniform and hot-spot traffics
The major performance drawbacks of multistage interconnection networks are due to link contention and message blockage. To remedy this problem, the authors propose a switch design which uses two independent routes between each input port and each output port within a switch. With proper routing control mechanisms, the adverse effect on link conflicts can be greatly reduced. Various simulations are used to illustrate the performance improvement of this new design under both uniform and hot-spot traffic patterns.<<ETX>>
10753893
Evaluation of Error Recovery Blocks Used for Cooperating Processes
Three alternatives for implementing recovery blocks (RB's) are conceivable for backward error recovery in concurrent processing. These are the asynchronous, synchronous, and the pseudorecovery point implementations. Asynchronous RB's are based on the concept of maximum autonomy in each of concurrent processes. Consequently, establishment of RB's in a process is made independently of others and unbounded rollback propagations become a serious problem. In order to completely avoid unbounded rollback propagations, it is necessary to synchronize the establishment of recovery blocks in all cooperating processes. Process autonomy is sacrificed and processes are forced to wait for commitments from others to establish a recovery line, leading to inefficiency in time utilization. As a compromise between asynchronous and synchronous RB's we propose to insert pseudorecovery points (PRP's) so that unbounded rollback propagations may be avoided while maintaining process autonomy. We developed probabilistic models for analyzing these three methods under standard assumptions in computer performance analysis, i.e., exponential distributions for related random variables. With these models we have estimated 1) the interval between two successive recovery lines for asynchronous RB's, 2) mean loss in computation power for the synchronized method, and 3) additional overhead and rollback distance in case PRP's are used.
850911
Usability-based caching of query results in OLAP systems
In this paper we propose a new cache management scheme for online analytical processing (OLAP) systems based on the usability of query results in rewriting and processing other queries. For effective admission and replacement of OLAP query results, we consider the benefit of query results not only for recently issued queries but for the expected future queries of a current query. We exploit semantic relationships between successive queries in an OLAP session, which are derived from the interactive and navigational nature of OLAP query workloads, in order to classify and predict subsequent future queries. We present a method for estimating the usability of query results for the representative future queries using a probability model for them. Experimental evaluation shows that our caching scheme using the past and future usability of query results can reduce the cost of processing OLAP query workloads effectively only with a small cache size and outperforms the previous caching strategies for OLAP systems.
12254873
Process Knowledge and Data Quality Outcomes
What modes and domains of knowledge about data production processes are most critical for producing high-quality data? This study provides an answer to this question. Data are collected via questionnaire and analyzed using linear regression. The results show some similarities and differences in which knowledge variables are significant for various data quality dimensions. Three results are of particular interest to data quality managers and researchers. The first is the complexity and mix of knowledge associated with producing accurate data. The second is the significant results overall for knowledge about the data collection process as compared to data storage and utilization processes. The third is the negative associations of the knowing-why mode of knowledge as compared to the positive associations for knowing-what and knowing-how. Each of these results has managerial implications and generates avenues for further research.
13163414
Process-Embedded Data Integrity
Despite the established theory and the history of the practical use of integrity rules, data quality problems, which should be solvable using data integrity rules, persist in organizations. One effective mechanism to solve this problem is to embed data integrity in a continuous data quality improvement process. The result is an iterative data quality improvement process as data integrity rules are defined, violations of these rules are measured and analyzed, and then the rules are redefined to reflect the dynamic and global context of business process changes. Using action research, we study a global manufacturing company that applied these ideas for improving data quality as it built a global data warehouse. This research merges data integrity theory with management theories about quality improvement using a data quality lens, and it demonstrates the usefulness of the combined theory for data quality improvement.
2576924
Integration of 802.11 and third-generation wireless data networks
The third-generation (3G) wide area wireless networks and 802.11 local area wireless networks possess complementary characteristics. 3G networks promise to offer always-on, ubiquitous connectivity with relatively low data rates. 802.11 offers much higher data rates, comparable to wired networks, but can cover only smaller areas, suitable for hot-spot applications in hotels and airports. The performance and flexibility of wireless data services would be dramatically improved if users could seamlessly roam across the two networks. In this paper, we address the problem of integration of these two classes of networks to offer such seamless connectivity. Specifically, we describe two possible integration approaches - namely tight integration and loose integration and advocate the latter as the preferred approach. Our realization of the loose integration approach consists of two components: a new network element called IOTA gateway deployed in 802.11 networks, and a new client software. The IOTA gateway is composed of several software modules, and with cooperation from the client software offers integrated 802.11/3G wireless data services that support seamless intertechnology mobility, Quality of Service (QoS) guarantees and multiprovider roaming agreements. We describe the design and implementation of the IOTA gateway and the client software in detail and present experimental performance results that validate our architectural approach.
10552627
An efficient parallel join algorithm based on hypercube-partitioning
Many parallel join algorithms have been proposed so far but most of which are developed focused on minimizing the disk I/O and CPU costs. The communication cost, however, is also an important factor that can significantly affect the join processing performance in multiprocessor systems. We propose an efficient parallel join algorithm, called Cube-Robust, for hypercube multicomputers. The proposed algorithm is developed based on the observation that the size ratio of two relations to be joined is the dominant factor in the communication cost. We develop the analytic cost model for the proposed join algorithm. The performance comparisons show that the Cube-Robust join algorithm works better than others proposed earlier in a wide range of size ratios.<<ETX>>