19842410
Automated design approaches for multi-domain dynamic systems using bond graphs and genetic programming
14747412
Adaptive Hierarchical Fair Competition (AHFC) Model For Parallel Evolutionary Algorithms
The HFC model for parallel evolutionary computation is inspired by the stratified competition often seen in society and biology. Subpopulations are stratified by fitness. Individuals move from low-fitness to higher-fitness subpopulations if and only if they exceed the fitness-based admission threshold of the receiving subpopulation, but not of a higher one. The HFC model implements several critical features of a competent parallel evolutionary computation model, simultaneously and naturally, allowing rapid exploitation while impeding premature convergence. The AHFC model is an adaptive version of HFC, extending it by allowing the admission thresholds of fitness levels to be determined dynamically by the evolution process itself. The effectiveness of the Adaptive HFC model is compared with the HFC model on a genetic programming-based evolutionary synthesis example.
872013
Integrative Array Analyzer: a software package for analysis of cross-platform and cross-species microarray data
The rapid accumulation of microarray data translates into an urgent need for tools to perform integrative microarray analysis. Integrative Array Analyzer is a comprehensive analysis and visualization software toolkit, which aims to facilitate the reuse of the large amount of cross-platform and cross-species microarray data. It is composed of the data preprocess module, the co-expression analysis module, the differential expression analysis module, the functional and transcriptional annotation module and the graph visualization module.
5276231
Open-ended robust design of analog filters using genetic programming
Most existing research on robust design using evolutionary algorithms (EA) follows the paradigm of traditional robust design, in which parameters of a design solution are tuned to improve the robustness of the system. However, the topological structure of a system may set a limit on the possible robustness achievable through parameter tuning. This paper proposes a new robust design paradigm that exploits the open-ended topological synthesis capability of genetic programming to evolve more robust systems. As a case study, a methodology for automated synthesis of dynamic systems, based on genetic programming and bond graph modeling (GPBG), is applied to evolve robust low-pass and high-pass analog filters. Compared with a traditional robust design approach based on a state-of-the-art real-parameter genetic algorithm (GA), it is shown that open-ended topology search by genetic programming with a fitness criterion rewarding robustness can evolve more robust systems with respect to parameter perturbations than what was achieved through parameter tuning alone, for our test problems.
15595451
HEMO: A Sustainable Multi-objective Evolutionary Optimization Framework
The capability of multi-objective evolutionary algorithms (MOEAs) to handle premature convergence is critically important when applied to real-world problems. Their highly multi-modal and discrete search space often makes the required performance out of reach to current MOEAs. Examining the fundamental cause of premature convergence in evolutionary search has led to proposing of a generic framework, named Hierarchical Fair Competition (HFC)[9], for robust and sustainable evolutionary search. Here an HFC-based Hierarchical Evolutionary Multi-objective Optimization framework (HEMO) is proposed, which is characterized by its simultaneous maintenance of individuals of all degrees of evolution in hierarchically organized repositories, by its continuous inflow of random individuals at the base repository, by its intrinsic hierarchical elitism and hyper-grid-based density estimation. Two experiments demonstrate its search robustness and its capability to provide sustainable evolutionary search for difficult multi-modal problems. HEMO makes it possible to do reliable multi-objective search without risk of premature convergence. The paradigmatic transition of HEMO to handle premature convergence is that instead of trying to escape local optima from converged high fitness populations, it tries to maintain the opportunity for new optima to emerge from the bottom up as enabled by its hierarchical organization of individuals of different fitnesses.
18592986
Simulation Study of TCP Performance Over Mobile IPV4 and Mobile IPV6
Mobile IPv6 (MIPv6) is a protocol to deal with mobility for the next generation Internet (IPv6). However, the performance of MIPv6 has not yet been extensively investigated. Knowledge of how MIPv6 affects TCP performance, especially in comparison with MIPv4, can provide directions for further improvement. In this report, an intensive simulation study of TCP performance over MIPv4 and MIPv6 has been conducted. Simulation using the famous network simulator NS-2 will be used to highlight differences when TCP is used in hybrid wireless environment, over these two Mobile IP protocols. Initial simulation has shown a solid improvement in performance for MIPv6 when IPv6 Route Optimisation features are used. During the course of simulation, a consistent event causing dropped TCP throughput was identified. Out of order arrival of packets would occur when the mobile node initiated a handover. This out of order arrival invokes TCP congestion control falsely which reduces throughput. The difference in overall throughput of MIPv4 compared to MIPv6 is roughly proportional to the difference in packet size attributed to IPv6’s increased header size. Another contribution of this work is to provide modifications and new functions such as node processing time, to the NS-2 simulator to make such investigation possible. To the best of our knowledge, no similar publication has been reported.
13437077
Scheduling reusable instructions for power reduction
In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.
6089015
Virtual machine management for Tele-Lab "IT-security" server
Tele-Lab "IT-security" Server is a new concept for practical security education. The Tele-lab server builds a virtual security laboratory using lightweight virtual machines and features a pure Web user interface. Thus, students can easily exercise security over the Internet. Running such a security laboratory on the Internet is difficult. Its infrastructure is subject to misuse and crash due to the nature of security tasks. The management of virtual machines is a crucial component which enables running the Tele-Lab server on the Internet. It effectively saves resources and improves security and reliability of the virtual laboratory. This paper briefly reviews the architecture of the Tele-Lab "IT-security" server, describes its virtual machine management in detail, and presents some experiential and experimental results.
56583323
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are mostly based on edge triggered flip-flops. In this paper, we demonstrate the advantages of using level sensitive latches in terms of both latency and area cost. The input-output timing coupling and the strict short path constraint for latches demand additional design elaborations compared with flip-flops. New approaches are proposed in this work to solve these difficulties so that the advantages of latches can be fully utilized. In particular, a deferred delay padding technique is developed to correct short path violations with the minimal extra cost. These techniques are integrated with a dynamic programming based concurrent synchronous element and repeater insertion framework. Experimental results confirm the advantages of using latches as well as effectiveness of our algorithms.
28075982
Clock buffer polarity assignment for power noise reduction