1780811
Reducing code size through address register assignment
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.
25434953
A data-centric approach to checksum reuse for array-intensive applications
Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive components. While many systems implement hardware-based protection techniques like ECC and other approaches to ensure an acceptable level of robustness against these errors, such solutions are generally very rigid and costly. Recent research discussed checksum-based software solutions that can be used in the context of array-intensive computations. While a checksum-based scheme can be more flexible than a hardware-based approach to reliability, it can also bring significant runtime overheads. Focusing on array-intensive applications, this paper proposes a compiler-directed data-centric strategy that maximizes reuse of checksums. A unique characteristic of the proposed scheme is that it can work with a given checksum assignment, and automatically - under compiler guidance - restructures the entire application code to maximize checksum reuse. This scheme can reduce checksum recomputing even further by inter-procedural checksum reuse. Our experiments clearly show that the proposed approach reduces the number of checksum calculations required by the previous work.
15399936
Compiler-guided leakage optimization for banked scratch-pad memories
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
2974807
Address Register Assignment for Reducing Code Size
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55&percnt). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).
316842
Cycles in 4-connected planar graphs
Let G be a 4-connected planar graph on n vertices. Previous results show that G contains a cycle of length k for each k ∈ {n, n - 1,n - 2, n - 3} with k ≥ 3. These results are proved using the "Tutte path" technique, and this technique alone cannot be used to obtain further results in this direction. One approach to obtain further results is to combine Tutte paths and contractible edges. In this paper, we demonstrate this approach by showing that G also has a cycle of length k for each k ∈ {n - 4, n - 5, n - 6} with k ≥ 3. This work was partially motivated by an old conjecture of Malkevitch.
11486473
Circumference of Graphs with Bounded Degree
Karger, Motwani, and Ramkumar Algorithmica, 18 (1997), pp. 82--98] have shown that there is no constant approximation algorithm to find a longest cycle in a Hamiltonian graph, and they conjectured that this is the case even for graphs with bounded degree. On the other hand, Feder, Motwani, and Subi [SIAM J. Comput., 31 (2002), pp. 1596--1607] have shown that there is a polynomial time algorithm for finding a cycle of length $n^{\log_32}$ in a 3-connected cubic n-vertex graph. In this paper, we show that if G is a 3-connected n-vertex graph with maximum degree at most d, then one can find, in O(n3) time, a cycle in G of length at least $\Omega(n^{\log_b2})$, where $b=2(d-1)^2+1$.
206570229
Graphs with Linearly Bounded Ramsey Numbers
Abstract A graph G of order n is p -arrangeable if its vertices can be ordered as v 1 , v 2 , ..., v n such that | N L i ( N Ri ( v i ))| ≤ p for each 1 ≤ i ≤ n − 1, where L i = { v 1 , v 2 , ..., v i }, R i = { v i +1 , v i +2 , ..., v n }, and N A ( B ) denotes the neighbors of B which lie in A . We prove that for each p ≥ 1, there is a constant c (depending only on p ) such that the Ramsey number r ( G , G ) ≤ cn for each p -arrangeable graph G of order n . Further we prove that there exists a fixed positive integer p such that all planar graphs are p -arrangeable.
2501005
Coordinating Multiple Agents via Reinforcement Learning
In this paper, we attempt to use reinforcement learning techniques to solve agent coordination problems in task-oriented environments. The Fuzzy Subjective Task Structure model (FSTS) is presented to model the general agent coordination. We show that an agent coordination problem modeled in FSTS is a Decision-Theoretic Planning (DTP) problem, to which reinforcement learning can be applied. Two learning algorithms, ‘‘coarse-grained’’ and ‘‘fine-grained’’, are proposed to address agents coordination behavior at two different levels. The ‘‘coarse-grained’’ algorithm operates at one level and tackle hard system constraints, and the ‘‘fine-grained’’ at another level and for soft constraints. We argue that it is important to explicitly model and explore coordination-specific (particularly system constraints) information, which underpins the two algorithms and attributes to the effectiveness of the algorithms. The algorithms are formally proved to converge and experimentally shown to be effective.
13201367
Generalized Diameters of the Mesh of Trees
Abstract
The mesh of trees, which owns two favorable properties, small diameter and large bisection,
is known as the fastest network when considered in terms of speed. In this paper we show that
the wide diameter, fault diameter and Rabin number, which are three generalizations of diameter,
of a two-dimensional 2n×2n mesh of trees are equal to 5n + 1.

