12391996
A Framework for Multi-Agent Belief Revision
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23049563
A Framework for Multi-Agent Belief Revision, Part I: The Role of Ontology
In this paper, we identify that failure to cater for the various forms of heterogeneity is one of the major drawbacks of the previous research on multi-agent belief revision (MABR). Three major categories of heterogeneity, namely social, semantic and syntactic heterogeneity are clarified. Several issues posed by such heterogeneities are addressed in the context of BR. The use of ontology is proposed as a powerful tool to tackle the heterogeneity issues so as to achieve the necessary reliable communication find system interoperability required by MABR. The question of what kind of ontology would be suitable to support MABR in a heterogenous setting is answered in Part I. In its sequel, Part II, a general framework for MABR is presented based on a shared knowledge structure which serves as the theoretical basis for ontology design.
5841147
Trustworthiness of Information Sources and Information Pedigrees
To survive, and indeed thrive, in an open heterogenous information sharing environment, an agent's ability to evaluate the trustworthiness of other agents becomes crucial. In this paper, we investigate a procedure for evaluating an agent's trustworthiness as an information source. By separating the procedure into competency analysis and sincerity analysis, we are able to deal with complicated cases involving the passing-on of information, where the same information may reach a receiver agent via different routes. In order to keep information about the source agent we use an information pedigree as a means to maintain the history of communicated information. Our evaluation of trustworthiness can be employed to drive data fusion, weighted knowledge base merging, and multiple source conflict resolution.
11837218
Using Web Based Answer Hunting System to Promote Collaborative Learning
In this paper, we share our pedagogical experience to motivate and facilitate an interactive and collaborative learning atmosphere by using an answer hunting system. In the software engineering practice course we are teaching, a problem that may deteriorate the learning quality is that, the students lack the opportunities of communication and discussion with the instructor both in class and out of class since they do not have many common time slots. Therefore, a web based answer hunting system is carefully designed and built to facilitate the communications between the students and instructor, and among the students. This system is designed based on the Q&A competition metaphor. The students are encouraged to participate in the competition to learn more knowledge, share more knowledge, and earn more participation marks.
1862113
iWatcher: efficient architectural support for software debugging
Recent impressive performance improvements in computer architecture have not led to significant gains in ease of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root cause of a bug. Moreover, program execution typically slows down significantly, often by 10-100 times. To address this problem, this paper introduces the Intelligent Watcher (iWatcher), novel architectural support to monitor dynamic execution with minimal overhead, automatically, and flexibly. iWatcher associates program-specified monitoring functions with memory locations. When any such location is accessed, the monitoring function is automatically triggered with low overhead. To further reduce overhead and support rollback, iWatcher can leverage Thread-Level Speculation (TLS). To test iWatcher, we use applications with various bugs. Our results show that iWatcher detects many more software bugs than Valgrind, a well-known open-source bug detector. Moreover, iWatcher only induces a 4-80% execution overhead, which is orders of magnitude less than Valgrind. Even with 20% of the dynamic loads monitored in a program, iWatcher adds only 66-174% overhead. Finally, TLS is effective at reducing overheads for programs with substantial monitoring.
10470214
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must exploit multiple sources of speculative task-level parallelism, including any nesting levels of both subroutines and loop iterations. Unfortunately, these environments are hard to support in decentralized CMP hardware: since tasks are spawned out-of-order and unpredictably, maintaining key TLS basics such as task ordering and efficient resource allocation is challenging.While the concept of out-of-order spawning is not new, this paper is the first to propose a set of microarchitectural mechanisms that, altogether, fundamentally enable fast TLS with out-of-order spawn in a CMP. Moreover, we develop a fully-automated TLS compiler for aggressive out-of-order spawn. With our mechanisms, a TLS CMP with four 4-issue cores achieves an average speedup of 1.30 for full SPECint 2000 applications; the corresponding speedup for in-order only spawn is 1.04. Overall, our mechanisms unlock the potential of TLS for the toughest applications.
14227266
Thread-Level Speculation on a CMP can be energy efficient
Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research. However, TLS is suspected of being too energy inefficient to compete against conventional processors. In this paper, we refute this claim. To do so, we first identify the main sources of dynamic energy consumption in TLS. Then, we present simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact. The resulting TLS CMP, populated with four 3-issue cores, speeds-up full SPECint 2000 codes by 1.27 on average, while keeping the fraction of the chip's energy consumption due to TLS to only 20%. Compared to a 6-issue superscalar at the same frequency, the TLS CMP is on average faster, while consuming only 85% of its total on-chip power.
11385703
Hardware Enhanced Mining for Association Rules
In this paper, we propose a hardware-enhanced mining framework to cope with many challenging data mining tasks in a data stream environment. In this framework, hardware enhancements are implemented in commercial Field Programmable Gate Array (FPGA) devices, which have been growing rapidly in terms of density and speed. By exploiting the parallelism in hardware, many data mining primitive subtasks can be executed with high throughput, thus increasing the performance of the overall data mining tasks. Simple operations like counting, which take a major portion of conventional mining execution time, can in fact be executed on the hardware enhancements very efficiently. Subtask modules that are used repetitively can also be replaced with the equivalent hardware enhancements. Specifically, we realize an Apriori-like algorithm with our proposed hardware-enhanced mining framework to mine frequent temporal patterns from data streams. The frequent counts of 1-itemsets and 2-itemsets are obtained after one pass of scanning the datasets with our hardware implementation. It is empirically shown that the hardware enhancements provide the scalability by mapping the high complexity operations such as subset itemsets counting to the hardware. Our approach achieve considerably higher throughput than traditional database architectures with pure software implementation. With fast increase in applications of mobile devices where power consumption is a concern and complicated software executions are prohibited, it is envisioned that hardware enhanced mining is an important direction to explore.