2207402
Bias properties of infinitesimal perturbation analysis for systems with parallel servers
Abstract Infinitesimal pertubation analysis (IPA) is a technique for estimating derivatives of performance measures from a single simulation of a stochastic discrete-event system, which might, for example, be modeling a computer/communication network or a manufacturing system. Such derivative estimates are useful in sensitivity analysis of the system and in optimizing—or at least improving—the performance of the system through gradient algorithms. However, it is well-known that IPA gives biased estimates for systems with multiple servers (channels or machines) in parallel when the server characteristics are not identical. In this paper, we investigate the seriousness of the bias both theoretically and experimentally. From our study, we believe the IPA estimator is relatively insensitive to small differences in the service time distributions of the servers. Specifially, we conjecture that for nearly-identical servers, the bias is proportional to the square of the difference between the means of the service time distributions. To support this conjecture, we present a tractable analytical example and investigate, via simulation experiments, more general systems.
206976454
Formulation of the traffic engineering problems in MPLS based IP networks
The growth of the Internet has fuelled the development of new technologies that enable IP backbone networks to be engineered efficiently. One such prominent technology, multiprotocol label switching (MPLS) enables IP networks with quality of service to be traffic engineered well. We mathematically formulate the traffic engineering problem's in MPLS based IP networks including constraint based routing, connection admission control, rerouting and capacity planning problems. Unfortunately, obtaining the optimal solution of the traffic engineering problems has undesirable computational complexity since they can be shown to be NP-complete. It is intended that this work will articulate the details and provide insights into the inherent structure of the problems as well as motivate the development of efficient solution techniques.
11856531
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures
Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.
15946403
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor is implemented on the Xilinx XC2V6000-5 FPGA chip. To test the performance, the W-matrix sparse solver for linear equations is realized. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less than 1.1ms on the FPGA. A comparison with a commercial PC indicates that the vector processor is competitive for such computation-intensive problems
52800042
Library cell layout with Alt-PSM compliance and composability
6735188
Efficient model update for general link-insertion networks
Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network
5276231
Open-ended robust design of analog filters using genetic programming
Most existing research on robust design using evolutionary algorithms (EA) follows the paradigm of traditional robust design, in which parameters of a design solution are tuned to improve the robustness of the system. However, the topological structure of a system may set a limit on the possible robustness achievable through parameter tuning. This paper proposes a new robust design paradigm that exploits the open-ended topological synthesis capability of genetic programming to evolve more robust systems. As a case study, a methodology for automated synthesis of dynamic systems, based on genetic programming and bond graph modeling (GPBG), is applied to evolve robust low-pass and high-pass analog filters. Compared with a traditional robust design approach based on a state-of-the-art real-parameter genetic algorithm (GA), it is shown that open-ended topology search by genetic programming with a fitness criterion rewarding robustness can evolve more robust systems with respect to parameter perturbations than what was achieved through parameter tuning alone, for our test problems.