30693379
The Implementation of One-Sided Communications for WMPI II
This paper describes the implementation of MPI-2 one-sided communications (OSC) for the forthcoming WMPI II product, aimed at clusters of workstations (Windows workstations, for now). This implementation is layered directly on top of the WMPI Management Layer (WML), rather than being on top of the MPI layer and as such can draw more performance from the new features of the WMPI's WML. The major features of this implementation are presented, including the synchronization operations, the remote memory operations and the datatype handling mechanism. Performance benchmarks were taken, comparing the message passing and the one-sided communication models, as well as to compare this implementation with one layered on top of MPI.
35292815
WPVM: parallel computing for the people
This paper presents WPVM, a PVM implementation for the “MS Windows” — Microsoft Windows Operating System. WPVM stands for “Windows Parallel Virtual Machine” and intends to exploit the potential computational power of the small and medium PC LANs that proliferate in corporations and universities. As the original PVM [1–2], WPVM creates the abstraction of a parallel machine from a cluster of computers connected by a network. This virtual machine appears as a single and manageable resource to the programmer. The difference is that the target machines for WPVM are personal computers with MS Windows instead of UNIX machines. However, this system is compatible with the original PVM, meaning that we can use virtual machines composed simultaneously of UNIX and MS Windows machines.
11033391
System-level versus user-defined checkpointing
Checkpointing and rollback recovery is a very effective technique to tolerate transient faults and preventive shutdowns. In the past, most of the checkpointing schemes published in the literature were supposed to be transparent to the application programmer and implemented at the operating-system level. In recent years, there has been some work on higher-level forms of checkpointing. In this second approach, the user is responsible for the checkpoint placement and is required to specify the checkpoint contents. We compare the two approaches: system-level and user-defined checkpointing. We discuss the pros and cons of both approaches and we present an experimental study that was conducted on a commercial parallel machine.
11507520
Web-based Metacomputing with JET
22782109
A Fault-Tolerant Mechanism for Simple Controllers
There are many industrial controllers where no systematic fault-tolerant mechanisms are included because of cost constraints. This paper addresses that problem by making a proposal for a simple and low-cost fault-tolerant technique, yet very effective, that can be used even in the simplest controllers. The mechanism is able of tolerating both hardware and software faults. It uses behaviour-based error detection, with checkpointing and rollback, to give resiliency to the application. The programs are made of possibly non-deterministic processes that communicate solely by messages. The technique, called RP-Actions, also guarantees that the recovery is domino-effect free. Software bugs are caught by acceptance tests as in recovery blocks. Forward error recovery is used for time, since time cannot be rolled back. Several implementations of the proposed mechanisms were made — we present in this paper some important results.
35428904
Portable checkpointing and recovery
This paper presents a checkpointing scheme that was implemented in a parallel library that runs on top of CHIMP/MPI. The main goals of the checkpointing mechanism are portability and efficiency. It runs on every platform supported by MPI in a machine-independent way. The scheme allows the migration of checkpoints and offers a flexible recovery mechanism based on data-reconfiguration. Some performance results will be presented at the end of the paper together with some techniques that can be used to increase the efficiency of the checkpointing mechanism.
14688474
A processor for testing mixed-signal cores in system-on-chip
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.
9584994
A Traffic Differentiation Method for IPv6 over ATM Networks
At present, the number of Internet users continues to increase dramatically, accompanied by the large-scale introduction of new applications with multimedia capabilities. New users and applications are constantly demanding better performance from the Internet, if possible with some forms of quality of service (QoS) guarantees. Knowing that no single technology is able to provide such guarantees in the Internet environment — which, by definition is a multi-technology environment — the exploration of promising technologies capable of traffic differentiation that are applicable to parts of the Internet appears as a possible way forward. This paper addresses and explores the benefits of the Internet Protocol version 6 (IPv6) and Asynchronous Transfer Mode (ATM) integration in multimedia environments. A method for traffic differentiation in IPv6-over-ATM networks is proposed, based on the mapping of different IPv6 flows into the address resolution functions of ATM. The proposal is evaluated in terms of introduced overhead, by means of simulation studies, supported by an experimental platform and an IPv6-over-ATM simulator developed for this purpose.
62642642
GRASP—a new search algorithm for satisfiability
This paper introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), an integrated algorithmic framework for SAT that unifies several previously proposed search-pruning techniques and facilitates identification of additional ones. GRASP is premised on the inevitability of conflicts during search and its most distinguishing feature is the augmentation of basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by "recording" the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Finally, straightforward bookkeeping of the causality chains leading up to conflicts allows GRASP to identify assignments that are necessary for a solution to be found. Experimental results obtained from a large number of benchmarks, including many from the field of test pattern generation, indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for a large number of representative classes of SAT instances.
10924515
Run-Time Profiling of Functional Logic Programs
In this work, we introduce a profiling scheme for modern functional logic languages covering notions like laziness, sharing, and non-determinism. Firstly, we instrument a natural (big-step) semantics in order to associate a symbolic cost to each basic operation (e.g., variable updates, function unfoldings, case evaluations). While this cost semantics provides a formal basis to analyze the cost of a computation, the implementation of a cost-augmented interpreter based on it would introduce a huge overhead. Therefore, we also introduce a sound transformation that instruments a program such that its execution—under the standard semantics—yields not only the corresponding results but also the associated costs. Finally, we describe a prototype implementation of a profiler based on the developments in this paper.
33382273
Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure
The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture of the proposed analog boundary module to implement alternative testing methods. These include a method for parametric testing of passive components based on the monitoring of the power supply current, and a mixed current/voltage technique allowing the implementation of correlation for testing analog and mixed-signal macros.