5958118
Delayed stability and performance of distributed congestion control
Recent research efforts to design better Internet transport protocols combined with scalable Active Queue Management (AQM) have led to significant advances in congestion control. One of the hottest topics in this area is the design of discrete congestion control algorithms that are asymptotically stable under heterogeneous feedback delay and whose control equations do not explicitly depend on the RTTs of end-flows. In this paper, we show that max-min fair congestion control methods with a stable symmetric Jacobian remain stable under arbitrary feedback delay (including heterogeneous directional delays) and that the stability condition of such methods does not involve any of the delays. To demonstrate the practicality of the obtained result, we change the original controller in Kelly's work [14] to become robust under random feedback delay and fixed constants of the control equation. We call the resulting framework Max-min Kelly Control (MKC) and show that it offers smooth sending rate, exponential convergence to efficiency, and fast convergence to fairness, all of which make it appealing for future high-speed networks.
353647
On Estimating Tight-Link Bandwidth Characteristics over Multi-Hop Paths
In this paper, we explore multi-hop bandwidth estimation assuming arbitrary cross-traffic at each node and develop a new probing method called Envelope that can asymptotically estimate not only the available bandwidth but also the raw capacity of the tight link. Envelope is based on a multi-link recursive extension of unbiased single-hop estimators proposed in the past (e.g., [14]) and a variation of the packet-cartouche technique [6]. Through extensive simulations, we evaluate Envelope in various network settings and cross-traffic conditions and find that it can measure tight-link bandwidth characteristics with accuracy that significantly surpasses that of the existing methods. We also find that Envelope can measure non-tight links in certain path and cross-traffic configurations.
5454614
Impact of FEC overhead on scalable video streaming
Forward-error correction (FEC) is used in many streaming applications for protecting multimedia data over lossy network paths. However, studies in the literature [1, 3, 4] report conflicting results on the benefits of FEC. To address this uncertainty, we study the performance of FEC-based streaming and provide additional insight into how FEC overhead rate affects the performance of scalable video streaming under dynamically changing network packet loss. Through analytical investigation, we derive the relationship between packet loss, FEC overhead, and utility of received video, and propose a simple control mechanism that adjusts the amount of FEC based on packet loss information. We find that our FEC control allows the application to maintain high end-user utility and achieve better quality of video at the receiver.
9687304
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the cycle-averaged power model for interconnects accounting for switching statistics and dynamic behaviors. For the sake of signal integrity, cross-coupling effects are also characterized which reflect logical correlation between adjacent wires. Based on the new models for interconnect power and capacitive crosstalk, we optimize the coupling power consumed by interconnects with crosstalk constraints. Experimental results show that optimized designs save the power consumption significantly.
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
41028764
Large environment rendering using plenoptic primitives
One of the most difficult tasks in computer graphics is to enable virtual walkthroughs in very large and complicated environments that are photorealistic, seamless, and in real time. Current image-based rendering techniques, while capable of photorealism and interactive speeds, have failed in practice to extend to visualizations of such environments. We demonstrate an approach that defines a virtual walkthrough experience using plenoptic primitives (PPs). A PP can be any type of local visual experience: 360/spl deg/ static panorama, panoramic video (PV), lumigraph/light field representation, or concentric mosaics (CMs). By combining them judiciously, user experience can be authored with significantly reduced effort while maintaining high-quality user experience. We illustrate our technique on synthetic and real environments using PVs and CMs and show how the problem of achieving smooth transitions among PVs and CMs can be solved by using position-dependent local geometries.
36636082
An accurate analytical delay model for BiCMOS driver circuits
An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration. >
45749208
A low-power reduced swing single clock flip-flop
A reduced swing single clock flip-flop (RS/sup 2/CFF) is developed to reduce power consumption significantly compared to conventional FFs. RS/sup 2/CFF avoids unnecessary internal node transition and reduce fighting currents. The overall power saving in flip-flop operation is estimated to be 33% with additional 64% power savings in clock network.