30244538
Fault-tolerance on regular decomposition grid applications
Writing parallel applications is considerably more complex due to additional problems not found in the sequential environment. The main problems include communication, synchronization data partitioning and distribution, mapping of processes, heterogeneity and fault tolerance. Fault tolerance is a very important feature in parallel/distributed systems since the mean time between failures of the system decreases with the number of processors, and the failure of just one process(or) can lead to the crash of the entire application. This paper presents an example of a parallel library (PUL-RD) that solves most of the problems pointed out before and provides support for fault tolerance. The original version of the library offers high-level support for parallelism in a portable way and can be used to write grid-based parallel applications which have a regular decomposition. In this paper, we will describe the fault-tolerance issues that were incorporated into the PUL-RD, giving special attention to the functionality of the checkpointing scheme.<<ETX>>
29620691
Heterogeneous parallel computing using Java and WMPI
In this paper, we present briefly the implementation of a Java interface forWMPI , a Windows-based implementation of MPI. Then, we describe a system that is oriented for Web-based computing and present a solution to integrate WMPIwith this tool by making use of a Java bridge component and the Java bindings for WMPI . This solution allows the execution of meta-applications over a mixed configuration of platforms, execution models and programming languages. The resulting system provides a way to solve the problem of heterogeneity and to unleash the potential of diverse computational resources and programming tools. Copyright  2000 John Wiley & Sons, Ltd.
12469936
JAMES: A Platform of Mobile Agents for the Management of Telecommunication Networks
This paper presents an overview of JAMES, a Java-based platform of mobile agents that is mainly oriented for the management of data and telecommunication networks. This platform has been developed on behalf of a Eureka Project (Σ!1921) and the project partners are Siemens SA, University of Coimbra and Siemens AG. We describe the main architecture of the platform giving more emphasis to the most important features. To show the effectiveness of some of the techniques that have been implemented we will present some performance results that compare the JAMES platform with the Aglets Workbench. 
 
The main target of our platform is network management and telecommunication applications. In this line, we have done a Java-based implementation of SNMP that has been integrated within the platform. The industrial partners of our project (i.e. Siemens S.A.) have developed a prototype application for TMN performance management. Although it is still a prototype it is being used to validate the technological advantages of using mobile agents in the management of telecommunication networks.
33293331
Portable transparent checkpointing for distributed shared memory
We present a checkpointing mechanism for a DSM system that, in spite of being invisible to the programmer, is quite efficient and portable. It is efficient because it is nonblocking, coordinated and thus domino-effect free. It offers some portability because it is built on top of MPI and uses only the services offered by MPI and a POSIX compliant local file system. As far as we know, this is the first real implementation of such a scheme for DSM. Along with the description of the algorithms used, we present experimental results obtained in a cluster of workstations, and discuss many insights that came out of the implementation effort. We hope that our research shows that efficient, transparent and portable checkpointing is viable for DSM systems.
18538603
Sharing checkpoints to improve turnaround time in desktop grid computing
In this paper, we present a checkpoint sharing methodology to improve turnaround time of applications run over desktop grid environments. In fact, volatility of desktop grid nodes reduces the efficiency of such environments when a fast turnaround time is sought, since a task might get stalled if its assigned machine remains unavailable for a somewhat long period of time (long at the scale of the computation). The rationale behind our approach is to permit checkpoint reuse, so that when a computation is forced to move from one node to another, it can be restarted from an intermediary point provided by the last saved checkpoint. We study the effects of sharing checkpoints in application turnaround time simulating three scheduling algorithms based on first come first served: FCFS, FCFS-AT and FCFS-TR. The targeted environment consists of institutional desktop grids. Our results show that sharing checkpoints is particularly effective in volatile environments, yielding performance improvement up to three times relatively to schemes based on private checkpoints. Furthermore, for non-volatile environments, a simple timeout strategy produces good results.
35428904
Portable checkpointing and recovery
This paper presents a checkpointing scheme that was implemented in a parallel library that runs on top of CHIMP/MPI. The main goals of the checkpointing mechanism are portability and efficiency. It runs on every platform supported by MPI in a machine-independent way. The scheme allows the migration of checkpoints and offers a flexible recovery mechanism based on data-reconfiguration. Some performance results will be presented at the end of the paper together with some techniques that can be used to increase the efficiency of the checkpointing mechanism.
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
16534842
Formal Verification of Component-Based Software Systems
In this work we present a methodology for formal modeling and verification of component based software systems. The methodology is based on software architecture, components, and reuse of Petri Nets models. With this process, we are contributing for the visual composition, verification, and formal validation of software. We also show an example of the application of this methodology into two different domains.
15163719
Solving satisfiability in combinational circuits
As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.
1299949
Sociable Interfaces
Interface formalisms are able to model both the input requirements and the output behavior of system components; they support both bottom-up component-based design, and top-down design refinement. In this paper, we propose “sociable” interface formalisms, endowed with a rich compositional semantics that facilitates their use in design and modeling. Specifically, we introduce interface models that can communicate via both actions and shared variables, and where communication and synchronization covers the full spectrum, from one-to-one, to one-to-many, many-to-one, and many-to-many. Thanks to the expressive power of interface formalisms, this rich compositional semantics can be realized in an economical way, on the basis of a few basic principles. We show how the algorithms for composing, checking the compatibility, and refining the resulting sociable interfaces can be implemented symbolically, leading to efficient implementations.
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.