37411387
Automatic generation of memory built-in self-test cores for system-on-chip
Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
28276441
A Programmable BIST Core for Embedded DRAM
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy.
14986573
Sharing ontology schema information for Web service integration
In spite of many standards efforts, Web services with similar or compatible functionalities often have heterogeneous semantics. One reason is the disparate ontologies used for service descriptions. In order to compare and compose Web services, the ability to merge different ontologies is essential. This paper describes an approach to align numerous, independently designed ontologies. Our approach is a completely automated one, without the need for prior agreement on semantics. It incorporates WordNet and heuristic reasoning and infers new knowledge by self-learning. Our system provides a solid base for the seamless integration of Web services.
10675163
Maximal and Minimal Vertex-Critical Graphs of Diameter Two
A graph is vertex-critical if deleting any vertex increases its diameter. We construct, for each??5 except?=6, a vertex-critical graph of diameter two on?vertices with at least 12?2?2?3/2+c1?edges, wherec1is some constant. We show that such a graph contains at most 12?2?(2/2)?3/2+c2?edges, wherec2is some constant. We also construct, for each??5 except?=6, a vertex-critical graph of diameter two on?vertices with at most 12 (5??12) edges. We show that such a graph must contain at least 12 (5??29) edges.
4803217
Pushing the cycles out of multipartite tournaments
Abstract Let D be a digraph and X ⊆ V ( D ). By pushing X we mean reversing each arc of D with exactly one end in X. Klostermeyer proved that it is NP-complete to decide if a given digraph can be made acyclic using the push operation. Here we characterize, in terms of forbidden subdigraphs, the multipartite tournaments which can be made acyclic (resp. ordinary, unidirectional) using the push operation. This implies that the problem of deciding if a given multipartite tournament can be made acyclic (resp. ordinary, unidirectional) using the push operation and, if so, finding a suitable subset of vertices to push, is solvable in polynomial time.
8122062
High quality splatting and volume synthesis
Our recent improvements to volume rendering using splatting allow for an accurate functional reconstruction and volume integration, occlusion-based acceleration, post-rendering classification and shading, 3D texture mapping, bump mapping, anti-aliasing and gaseous animation. A pure software implementation requiring low storage and using simple operations has been implemented to easily support these operations. This paper presents a unified framework and discussion of these enhancements, as well as extensions to support hypertextures efficiently. Discussions on appropriate volume models for effective usage of these techniques is also presented.
7193109
An object-oriented architecture supporting Web application testing
The flexibility and rich application frameworks of the Web model make Web applications more prevalent in both Internet and intranet environments. Programmers enjoy various Web application frameworks with support ranging from simple user interactions based on the plain client-server model, to complicated distributed-object computations based on CORBA. The variety gives users the flexibility to decide a proper framework, and leads to demands for new support tools and a testing framework to test and maintain Web applications. This paper presents an architecture containing several supporting tools which enhance traditional software testing architecture to fit common Web application frameworks. The architecture suits current Web models and reuses several software patterns and architectures from traditional testing environments. In addition, a prototype Web application testing environment is constructed for demonstration.