9436195
Satisfiability models and algorithms for circuit delay computation
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
29620691
Heterogeneous parallel computing using Java and WMPI
In this paper, we present briefly the implementation of a Java interface forWMPI , a Windows-based implementation of MPI. Then, we describe a system that is oriented for Web-based computing and present a solution to integrate WMPIwith this tool by making use of a Java bridge component and the Java bindings for WMPI . This solution allows the execution of meta-applications over a mixed configuration of platforms, execution models and programming languages. The resulting system provides a way to solve the problem of heterogeneity and to unleash the potential of diverse computational resources and programming tools. Copyright  2000 John Wiley & Sons, Ltd.
6164806
Deterministic Models of Software Aging and Optimal Rejuvenation Schedules
Automated modeling of software aging processes is a prerequisite for cost-effective usage of adaptive software rejuvenation as a self-healing technique. We consider the problem of such automated modeling in server-type applications whose performance degrades depending on the "work" done since last rejuvenation, for example the number of served requests. This type of performance degradation - caused mostly by resource depletion - is common, as we illustrate in a study of the popular Axis Soap server 1.3. In particular, we propose deterministic models for approximating the leading indicators of aging and an automated procedure for statistical testing of their correctness. We further demonstrate how to use these models for finding optimal rejuvenation schedules under utility functions. Our focus is on the important case that the utility function is the average of a performance metric (such as maximum service rate). We also consider optional SLA constraints under which the performance should never drop below a specified level. Our approach is verified by a study of the aging processes in the Axis Soap 1.3 server. The experiments show that the deterministic modeling technique is appropriate in this case, and that the optimization of rejuvenation schedules can greatly improve the average maximum service rate of an aging application.
540709
The performance of coordinated and independent checkpointing
Checkpointing is a very effective technique to tolerate the occurrence of failures in distributed and parallel applications. The existing algorithms in the literature are basically divided into two main classes: coordinated and independent checkpointing. This paper presents an experimental study that compares the performance of these two classes of algorithms. The main conclusion of our study is that coordinated checkpointing is more efficient than independent checkpointing and all the arguments against the performance of coordinated algorithms were not verified in practice.
17928832
Software Aging and Rejuvenation in a SOAP-based Server
Web-services and service-oriented architectures are gaining momentum in the area of distributed systems and Internet applications. However, as we increase the abstraction level of the applications we are also increasing the complexity of the underlying middleware. In this paper, we present a dependability benchmarking study to evaluate and compare the robustness of some of the most popular SOAP-RPC implementations that are intensively used in the industry. The study was focused on Apache Axis where we have observed a high susceptibility of software aging. Building on these results we propose a new SLA-oriented software rejuvenation technique that proved to be a simple way to increase the dependability of the SOAP-server, the degree of self-healing and to maintain a sustained level of performance in the applications
12117022
Distributed data collection through remote probing in windows environments
Distributed data collector (DDC) is a framework to ease and automate repetitive executions of console applications (probes) over a set of LAN networked Windows personal computers. The framework allows for the remote execution of probes, providing support for collecting the execution output of probes (standard output and standard error). Additionally, right after a probe execution, the output can be parsed and processed by user-defined code (post collecting code) that can act accordingly to user's needs. The framework can be useful to perform repetitive large-scale monitoring and administrative tasks over machines with transient availability, that is, machines that present no guarantees of being available at a given time. A major strength of DDC lies in the fact that it does not require installation of software in remote nodes, avoiding administrative burdens that remote daemons and alike normally provoke. Besides presenting the data collection framework, the paper discusses the results of a 30-day monitoring experiment conducted with DDC. The experiment collected resource usage metrics over 169 Windows machines from classroom laboratories of an academic institution.