14059927
Test scheduling of BISTed memory cores for SoC
The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.
37411387
Automatic generation of memory built-in self-test cores for system-on-chip
Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
28276441
A Programmable BIST Core for Embedded DRAM
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy.
832921
Hardware-assisted feature analysis and visualization of procedurally encoded multifield volumetric data
We take a new approach to interactive visualization and feature detection of large scalar, vector, and multifield computational fluid dynamics data sets that is also well suited for meshless CFD methods. Radial basis functions (RBFs) are used to procedurally encode both scattered and irregular gridded scalar data sets. The RBF encoding creates a complete, unified, functional representation of the scalar field throughout 3D space, independent of the underlying data topology, and eliminates the need for the original data grid during visualization. The capability of commodity PC graphics hardware to accelerate the reconstruction and rendering and to perform feature detection from this functional representation is a powerful tool for visualizing procedurally encoded volumes. Our RBF encoding and GPU-accelerated reconstruction, feature detection, and visualization tool provides a flexible system for visually exploring and analyzing large, structured, scattered, and unstructured scalar, vector, and multifield data sets at interactive rates on desktop PCs.
1414584
Broadcast program generation for unordered queries with data replication
We study in this paper the problem of broadcasting dependent data for unordered queries. However, most prior studies on dependent data broadcasting are limited to the premise of no data replication. Different from other prior studies, we investigate the effect of data replication in this paper. Specifically, we first derive several theoretical properties for the average access time by analyzing the model of dependent data broadcasting. On the basis of the theoretical results, we develop a genetic algorithm to generate broadcast programs with replication. In order to compare the performance of the proposed algorithm and the prior studies, several experiments are conducted. Our experimental results show that with the analytical results derived, the theoretical results derived are able to guide the search of the genetic algorithm very effectively, and lead to solution broadcast programs of higher quality than those of the prior studies.
10392277
Visibility Culling Using Plenoptic Opacity Functions for Large Data Visualization
6334357
An energy-conserved on-demand data broadcasting system
We propose in this paper an energy-conserved on-demand data broadcasting system by employing the data indexing technique. We also propose algorithm AIDOA to adjust the degree of buckets according to system workload. Experimental results show that algorithm AIDOA is able to greatly reduce power consumption at the cost of slight increment in average access time and adjust the index and data organization dynamically to adapt to change of system workload.
6321071
The Myth of the Boundaryless Organization
Technology does not make cultural and business boundaries disappear simply because it exists.