16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
8520040
The embedded software consortium of taiwan
The advancement of semiconductor manufacturing technology makes it practical to place a traditional board-level embedded system on a single chip. The evolvement of system-on-chip (SoC) techniques presents new challenges for integrated circuit designs as well as embedded software and systems. To address these challenges, the Ministry of Education (MOE) of Taiwan has been running the VLSI Circuits and Systems Education Program since 1996. This program adopts a top-down approach by forming six domain-specific, intercollegiate consortia. The Embedded Software (ESW) consortium addresses the challenges of embedded software for SoC systems. This paper first introduces the six-consortium architecture and the organization and programs of ESW. We next describe the embedded software curriculum developed by ESW. This curriculum will later be implemented in most universities and colleges in Taiwan to promote the capabilities of embedded software design and implementations. Finally, we present an execution summary of ESW 2004.
12521322
Repacking on Demand for Hierarchical Cellular Networks
In mobile telecommunications operation, radio channels are scarce resources and should be carefully assigned. One possibility is to deploy the hierarchical cellular network (HCN). This paper studies a HCN channel assignment scheme called repacking on demand (RoD). RoD was originally proposed for wireless local loop networks. We expend this work to accommodate mobile HCN. A simulation model is proposed to study the performance of HCN with RoD and some previously proposed schemes. Our study quantitatively indicates that RoD may significantly outperform the previous proposed schemes.
26216894
Equal resource sharing scheduling for PCS data services
For high speed mobile communication applications, the data rate can be increased by using multiple channels (or time slots) instead of one channel. To reduce the high blocking rate of multiple channels assignment, flexible resource allocation strategies have been proposed. This paper proposes the Equal Resource Sharing Allocation scheme (ERSA scheme) for flexible resource allocation. The ERSA scheme dynamically averages the allocated resource to the call requests based on the number of calls in a base station. The scheme accommodates the maximum number of requests while providing acceptable quality to the admitted requests. We developed an analytic model to investigate the performance of ERSA, and conducted simulation experiments to validate the analytic model. We define satisfaction indication SI as the performance measurement of the resource allocation algorithm. The experiment results indicate that the ERSA scheme outperforms other resource allocation algorithms proposed in our previous study.
3227227
Dynamic Resource Assignment Strategies for PCS Data Services
For high speed mobile communication applications, the data rate can be increased by using multiple channels (or time slots) instead of a single channel (or time slot). To reduce the high blocking rate of multiple channels assignment, flexible resource allocation strategies are exercised. This paper proposes a generic Mobile Switching Center (MSC) resource allocation algorithm called MRA algorithm for Personal Communications Services (PCS) data services. The algorithm may combine with any base station resource allocation algorithms proposed in our previous study. A simulation model is proposed to investigate the performance of these algorithms. We define satisfaction indication SI to measure the performance of the resource allocation. SI indicates the customer's satisfaction about the call connection, it can also be used by the service provider as a charge indication.
14212252
Mobility management: from GPRS to UMTS
This paper describes mobility management for the third-generation mobile networks. We focus on the evolution from General Packet Radio Service (GPRS) to Universal Mobile Telecommunication System (UMTS). In this evolution, the radio access network UTRAN has been introduced, and radio-related management is moved from the core network to UTRAN. We elaborate on how this architecture change affects the mobility management functionality, including the attach and detach procedures, location update, serving radio network controller relocation and intersystem change between GPRS and UMTS. Copyright © 2001 John Wiley & Sons, Ltd.
206549585
vGPRS: a mechanism for voice over GPRS
This paper proposes vGPRS, a voice over IP (VoIP) mechanism for a general packet radio service (GPRS) network. In this approach, a new network element called VoIP mobile switching center (VMSC) is introduced to replace standard GSM MSC. The vGPRS approach is implemented using standard H.323, GPRS, and GSM protocols. Thus, existing GPRS and H.323 network elements are not modified. Furthermore, both standard GSM and GPRS mobile stations can be used to receive vGPRS service, which need not be equipped with the VoIP (i.e., H.323) terminal capabilities.