1051446
Integrated scheduling with garbage collection for real-time embedded applications in CLI
We present a schedulable garbage collection for realtime applications in virtual machine environments. The design objective is to make the pause time caused by garbage collection operations controllable, and the invocation of garbage collection predictable. Thus, real-time applications can be schedulable along with garbage collection. We develop a prototype for a schedulable garbage collection in MONO CLI execution environment. A cost model of garbage collection is established based on measured WCET to predict the execution time and overhead of garbage collection operations. A scheduling algorithm of garbage collection and application tasks is presented to illustrate how the time and memory constraints of real-time systems can be met. The experiment result of the scheduling algorithm for a periodic task set on the prototype is included in the paper
40618061
Transaction Recovery in Distributed DB/DC Systems: A Progressive Approach
30590203
Efficient State-Saving Architectures for Power-Mode Switching
Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce switching speed and energy. We present a heuristic to save the most relevant cache contents so that power and delay overheads are minimized. To measure the area overhead a synthesizable VHDL model was designed.
10753893
Evaluation of Error Recovery Blocks Used for Cooperating Processes
Three alternatives for implementing recovery blocks (RB's) are conceivable for backward error recovery in concurrent processing. These are the asynchronous, synchronous, and the pseudorecovery point implementations. Asynchronous RB's are based on the concept of maximum autonomy in each of concurrent processes. Consequently, establishment of RB's in a process is made independently of others and unbounded rollback propagations become a serious problem. In order to completely avoid unbounded rollback propagations, it is necessary to synchronize the establishment of recovery blocks in all cooperating processes. Process autonomy is sacrificed and processes are forced to wait for commitments from others to establish a recovery line, leading to inefficiency in time utilization. As a compromise between asynchronous and synchronous RB's we propose to insert pseudorecovery points (PRP's) so that unbounded rollback propagations may be avoided while maintaining process autonomy. We developed probabilistic models for analyzing these three methods under standard assumptions in computer performance analysis, i.e., exponential distributions for related random variables. With these models we have estimated 1) the interval between two successive recovery lines for asynchronous RB's, 2) mean loss in computation power for the synchronized method, and 3) additional overhead and rollback distance in case PRP's are used.
31591898
Scanning the issue - special issue on real-time systems
920212
Resource scheduling in dependable integrated modular avionics
In the recent development of avionics systems, integrated modular avionics (IMA) is advocated for next generation architecture that needs integration of mixed criticality real-time applications. These integrated applications meet their own timing constraints while sharing avionics computer resources. To guarantee timing constraints and dependability of each application, an IMA-based system is equipped with the schemes for spatial and temporal partitioning. We refer the model as SP-RTS (strongly partitioned real-time system), which deals with processor partitions and communication channels as its basic scheduling entities. This paper presents a partition and channel-scheduling algorithm for the SP-RTS. The basic idea of the algorithm is to use a two-level hierarchical schedule that activates partitions (or channels) following a distance-constraints guaranteed cyclic schedule and then dispatches tasks (or messages) according to a fixed priority schedule. To enhance schedulability, we devised heuristic algorithms for deadline decomposition and channel combining. The simulation results show the schedulability analysis of the two-level scheduling algorithm and the beneficial characteristics of the proposed deadline decomposition and channel combining algorithms.
6621245
Application of Machine Shop Data Model in Manufacturing Simulation
Simulation technology holds tremendous promise for the manufacturing industry. A machine shop data model has been developed at the National Institute of Standards and Technology (NIST) to represent neutral machine shop data for supporting machine shop manufacturing simulation [1]. This paper discusses the data model and its application in manufacturing simulation. The paper also proposes an application framework that integrates the simulation model, machine shop database, and machine shop XML (Extensible Markup Language) data document. A prototype system is developed to present the application of machine shop data model using the proposed framework.
207563187
Data quality assessment
How good is a company's data quality? Answering this question requires usable data quality metrics. Currently, most data quality measures are developed on an ad hoc basis to solve specific problems [6, 8], and fundamental principles necessary for developing usable metrics in practice are lacking. In this article, we describe principles that can help organizations develop usable data quality metrics.
14475818
Data exchange for machine shop simulation
Manufacturing simulation systems normally provide interfaces for data import and export using proprietary formats. Dependent data interfaces limit simulation applications in the manufacturing industry. This paper describes a mechanism for transferring data between a traditional database and XML files, which represent a machine shop data model developed at the National Institute of Standards and Technology (NIST). The data model is described by XML (eXtensible Markup Language) and UML (Unified Modeling Language). The data transfer mechanism is based on document object model (DOM), XML path language (XPath), and open database connectivity (ODBC) database engines. A prototype implementation is also described in this paper
13163414
Process-Embedded Data Integrity
Despite the established theory and the history of the practical use of integrity rules, data quality problems, which should be solvable using data integrity rules, persist in organizations. One effective mechanism to solve this problem is to embed data integrity in a continuous data quality improvement process. The result is an iterative data quality improvement process as data integrity rules are defined, violations of these rules are measured and analyzed, and then the rules are redefined to reflect the dynamic and global context of business process changes. Using action research, we study a global manufacturing company that applied these ideas for improving data quality as it built a global data warehouse. This research merges data integrity theory with management theories about quality improvement using a data quality lens, and it demonstrates the usefulness of the combined theory for data quality improvement.
9352277
An ATM Switch Capacity Allocation Problem
In this paper, we consider a capacity allocation problem arising in the context of deploying asynchronous transfer mode (ATM) networks. Given types of ATM switches, the problem is to find an optimal allocation of capacity such that the total cost of installed switch modules is minimized, while satisfying all traffic demands. We formulate the problem as an integer programming model, which can be conceptualized as a generalized bin packing problem with capacity constraints. We then develop a surrogate constraint technique of the formulation for enhancing the representation of the model. Guided by the tight lower bound of the surrogate relaxation, we devise an effective tabu search heuristic that provides good quality solutions with guaranteed optimality. We present promising computational results that show the viability of the proposed heuristic and lower bounding methods, and that provide insights into implementation for configuring ATM switch in practice.