16849942
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler phases include instruction scheduling, which maximizes instruction level parallelism (ILP), and register allocation, which minimizes data spills to external memory. If ILP is maximized without considering register constraints, high register pressure may result, leading to increased spill code and reduced run-time performance. In this paper, a new register pressure reduction technique for embedded VLIW processors is presented to control register pressure prior to instruction scheduling and register allocation. By modifying the relative ordering of operations, this technique restructures code to better reduce spills. Our technique has been implemented in Trimaran, an academic VLIW compiler, and evaluated using a series of VLIW benchmarks. Experimental results show that, on average, our algorithm reduces dynamic spills and improves overall cycle counts by 6% for a VLIW architecture with 8 functional units and 32 registers versus previous spill code reduction techniques.
18802067
Adaptive fault recovery for networked reconfigurable systems
The device-level size and complexity of reconfigurable architectures makes fault tolerance an important concern in system design. In this paper, we introduce a fully automated fault recovery system for networked systems, which contain FPGAs (field programmable gate arrays). If a fault is detected hat cannot be addressed locally, fault information is transferred to a reconfiguration server. Following design recompilation to avoid the fault, a new FPGA configuration is returned to the remote system and computation is reinitiated. To illustrate the benefit of this approach, we have implemented a complete fault recovery system, which requires no manual intervention. An important part of the system is a timing-driven incremental router for Xilinx Virtex devices. This router is directly interfaced to Xilinx JBits and uses no CAD tools from the standard Xilinx Alliance tool flow. Our completed system has been applied to three benchmark designs and exhibits complete fault recovery in up to 12x less time than the standard incremental Xilinx PAR flow.
13976369
Design of a nanosensor array architecture
This paper describes a nanowire sensor array architecture for high-speed, high-accuracy sensor systems. The chip has very simple processing elements (PEs) in a massively parallel architecture, in which each PE is directly connected to seven sensors. A sampling rate of 100 ns is enough to realized high-speed sensing feedback for electronic nose. We aim to create a very simple architecture, because a compact design is required ton integrate as many PEs as possible on a single chip. A widely used, easy to implement estimator-minimum distance classifier is introduced to realize the pattern recognition. A sample design is implemented in VHDL and has been simulated and synthesized using TSMC 0.25 standard cell library and a commercial 0.16 standard cell library.
2062974
A Conditional Random Field Model for Video Super-resolution
In this paper, we propose a learning-based method for video super-resolution. There are two main contributions of the proposed method. First, information from cameras with different spatial-temporal resolutions is combined in our framework. This is achieved by constructing training dictionary using the high resolution images captured by still camera and the low resolution video is enhanced via searching in this customized database. Second, we enforce the spatio-temporal constraints using the conditional random field (CRF) and the problem of video super-resolution is posed as finding the high resolution video that maximizes the conditional probability. We apply the algorithm to video sequences taken from different scenes using cameras with different qualities and promising results are presented
14934278
Optimal 2-D interleaving with latin rectangles
One of the key problems in the study of optimal interleaving schemes for correcting two-dimensional (2-D) cluster errors is how to place, say, n distinct symbols, each appearing m times, in an m/spl times/n array such that the resulting array has the maximum possible burst error-correcting power. In a previous paper, the authors have proved that for any given m, n, the maximum possible interleaving distance, and hence, the largest possible value t such that an arbitrary error burst of size t can be corrected in an m/spl times/n interleaved array, is given by t=/spl lfloor//spl radic/2n/spl rfloor/ for n = /spl les/ /spl lceil/m/sup 2//2/spl rceil/, and t=m+/spl lfloor/(n-/spl lceil/m/sup 2//2/spl rceil/)/m/spl rfloor/ for n /spl ges/ /spl lceil/m/sup 2//2/spl rceil/. In this work, we extend these results and show that for all m, n with n /spl ges/ m, an optimal m/spl times/n interleaving array can always be obtained by a Latin rectangle in which each row and each column contains each symbol at most once. This provides additional error-correcting power to the array in that all linear error bursts occupying a whole row or column can also be corrected.
14445257
Background Segmentation Using Spatial-Temporal Multi-Resolution MRF
Robust and accurate background segmentation is crucial for surveillance applications and is a key element in visual tracking, layer-based compression, and silhouette-based 3D reconstruction. In this paper, we present a novel spatial-temporal model that describes the appearance and dynamics of background scenes at multiple resolutions. We propose a time-dependent Markov Random Field (MRF) to represent the state of foreground and background at each pixel in the spatial-temporal pyramid. Pixels are linked spatially and temporally across frames. The probability of adding/deleting a foreground object is calculated by online learning algorithm and is used as prior information in computing foreground label. We use Gibbs Sampling to solve the MRF in a Maximum A Posterior (MAP) framework. Experimental results show that this real-time algorithm is able to segment the foreground object accurately from videos and more resilient to distractions such as imaging noise, illumination changes, camera shakes, and random motion in the scene.
57229289
An algorithm for multiple object trajectory tracking
Most tracking algorithms are based on the maximum a posteriori (MAP) solution of a probabilistic framework called Hidden Markov Model, where the distribution of the object state at current time instance is estimated based on current and previous observations. However this approach is prone to errors caused by temporal distractions such as occlusion, background clutter and multi-object confusion. In this paper we propose a multiple object tracking algorithm that seeks the optimal state sequence which maximizes the joint state-observation probability. We name this algorithm trajectory tracking since it estimates the state sequence or "trajectory" instead of the current state. The algorithm is capable of tracking multiple objects whose number is unknown and varies during tracking. We introduce an observation model which is composed of the original image, the foreground mask given by background subtraction and the object detection map generated by an object detector The image provides the object appearance information. The foreground mask enables the likelihood computation to consider the multi-object configuration in its entirety. The detection map consists of pixel-wise object detection scores, which drives the tracking algorithm to perform joint inference on both the number of objects and their configurations efficiently.