28815316
Stability analysis of buffer priority scheduling policies using Petri nets
A Petri net approach to determining the conditions for stability of a re-entrant system with buffer priority scheduling policy is described in this paper. The concept of buffer boundedness based on the dynamic behavior of the marking in the system model is emphasized. The method is used to demonstrate the stability of the first buffer first served (FBFS) and the last buffer first served (LBFS) scheduling policies. finally a sufficient condition for instability of systems with a positive feedback loop (PFL) is established, and an example is given.
30562053
Design a robust controller for active queue management in large delay networks
AQM (active queue management) can maintain the smaller queuing delay and higher throughput by the purposefully dropping the packets at the intermediate nodes. Almost all the existed schemes for AQM neglect the impact of large delay on performance. In this study, we firstly verify a fact through simulation experiments, which is the queues controlled by the several popular AQM schemes, including RED, PI controller and REM, appear the dramatic oscillations in large delay networks, which decreases the utilization of the bottleneck link and introduces the avoidable delay jitter. After some appropriate model approximation, we design a robust AQM controller to compensate the delay using the principle of internal mode compensation in control theory. The novel algorithm restrains the negative effect on queue stability caused by large delay. The simulation results show that the integrated performance of the proposed algorithm is obviously superior to that of several well-known schemes when the connections have large delay, at the same time, the buffers keep at small queue length.
14723095
Optimal Priority Packetization with Multi-layer UEP for Video Streaming over Wireless Network
Most of current packetization schemes consider only bit error or packet erasure, both of which are common in wireless networks. This paper addresses these two problems together, and proposes an optimal packetization scheme for video streaming over wireless network, which is independent of video coding method. To combat the packet erasure, priority packetization combined with multi-layer unequal error protection (UEP) is applied on video frames. Multi-layer UEP contains low-complexity duplication of high-priority packet in application layer and different retransmission limit in media access control layer. Content-aware rate-distortion optimization is also introduced in order to countermine the distortion caused by bit errors. Simulations show that our scheme gains 2.17 dB or more compared with the conventional scheme.
16307564
Architecture of Trustworthy Networks
Existing isolated and add-on secure systems are rarely robust under attack, misoperation and internal faults. Secure communication only offers little protection if one ore more components are compromised, and are not sufficient for holistic and systemic security. This paper proposes the concept of trustworthy networks, which makes advances along these traditional researches on network security in combination. We outline the key challenges in constructing trustworthy networks, and define three properties, namely security, survivability and controllability. Consulting human interactions, the abstract architecture for trustworthy networks is proposed, depicting protocols layers, topology structure, entities and components, and protocol steps
5812336
A Key Embedded Video Codec for Secure Video Multicast
The problem of controlling access to multimedia multicasts requires the distribution and maintenance of keying information. This paper proposes a new key embedded video codec for the media-dependent approach that involves the use of a data-dependent channel, and can be achieved for multimedia by using data embedding techniques. Using data embedding to convey keying information can provide an additional security and reduce the demand of bandwidth. In this paper, we develop a new statistical data embedding algorithm on compression-domain, then, by combining FEC (Forward Error Correction) algorithm and our proposed key information frame format. After a series of simulation experiments, we find that the new codec can satisfy the special demand of media-dependent approach. At the same time, the codec provides good performance.
16309496
Scaling to the end of silicon with EDGE architectures
Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, called explicit data graph execution (EDGE), that will match the characteristics of semiconductor technology over the next decade. The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
1207322
Dynamic integrated scheduling of hard real-time, soft real-time, and non-real-time processes
Real-time systems are growing in complexity and real-time and soft real-time applications are becoming common in general-purpose computing environments. Thus, there is a growing need for scheduling solutions that simultaneously support processes with a variety of different timeliness constraints. Toward this goal we have developed the resource allocation/dispatching (RAD) integrated scheduling model and the rate-based earliest deadline (RBED) integrated multi-class real-time scheduler based on this model. We present RAD and the RBED scheduler and formally prove the correctness of the operations that RBED employs. We then describe our implementation of RBED and present results demonstrating how RBED simultaneously and seamlessly supports hard real-time, soft real-time, and best-effort processes.
626075
Neural methods for dynamic branch prediction
This article presents a new and highly accurate method for branch prediction. The key idea is to use one of the simplest possible neural methods, the perceptron, as an alternative to the commonly used two-bit counters. The source of our predictor's accuracy is its ability to use long history lengths, because the hardware resources for our method scale linearly, rather than exponentially, with the history length. We describe two versions of perceptron predictors, and we evaluate these predictors with respect to five well-known predictors. We show that for a 4 KB hardware budget, a simple version of our method that uses a global history achieves a misprediction rate of 4.6% on the SPEC 2000 integer benchmarks, an improvement of 26% over gshare. We also introduce a global/local version of our predictor that is 14% more accurate than the McFarling-style hybrid predictor of the Alpha 21264. We show that for hardware budgets of up to 256 KB, this global/local perceptron predictor is more accurate than Evers' multicomponent predictor, so we conclude that ours is the most accurate dynamic predictor currently available. To explore the feasibility of our ideas, we provide a circuit-level design of the perceptron predictor and describe techniques that allow our complex predictor to operate quickly. Finally, we show how the relatively complex perceptron predictor can be used in modern CPUs by having it override a simpler, quicker Smith predictor, providing IPC improvements of 15.8% over gshare and 5.7% over the McFarling hybrid predictor.
5057977
ZPL: A Machine Independent Programming Language for Parallel Computers
The goal of producing architecture-independent parallel programs is complicated by the competing need for high performance. The ZPL programming language achieves both goals by building upon an abstract parallel machine and by providing programming constructs that allow the programmer to "see" this underlying machine. This paper describes ZPL and provides a comprehensive evaluation of the language with respect to its goals of performance, portability, and programming convenience. In particular, we describe ZPt's machine-independent performance model, describe the programming benefits of ZPL's region-based constructs, summarize the compilation benefits of the language's high-level semantics, and summarize empirical evidence that ZPL has achieved both high performance and portability on diverse machines such as the IBM SP-2, Cray T3E, and SGI Power Challenge.
11225382
Asymptotic Behaviors of Support Vector Machines with Gaussian Kernel
Support vector machines (SVMs) with the gaussian (RBF) kernel have been popular for practical use. Model selection in this class of SVMs involves two hyper parameters: the penalty parameter C and the kernel width . This letter analyzes the behavior of the SVM classifier when these hyper parameters take very small or very large values. Our results help in understanding the hyperparameter space that leads to an efficient heuristic method of searching for hyperparameter values with small generalization errors. The analysis also indicates that if complete model selection using the gaussian kernel has been conducted, there is no need to consider linear SVM.