35348578
The Complex EGI: A New Representation for 3-D Pose Determination
The complex extended Gaussian image (CEGI), a 3D object representation that can be used to determine the pose of an object, is described. In this representation, the weight associated with each outward surface normal is a complex weight. The normal distance of the surface from the predefined origin is encoded as the phase of the weight, whereas the magnitude of the weight is the visible area of the surface. This approach decouples the orientation and translation determination into two distinct least-squares problems. The justification for using such a scheme is twofold: it not only allows the pose of the object to be extracted, but it also distinguishes a convex object from a nonconvex object having the same EGI representation. The CEGI scheme has the advantage of not requiring explicit spatial object-model surface correspondence in determining object orientation and translation. Experiments involving synthetic data of two polyhedral and two smooth objects are presented to illustrate the feasibility of this method. >
47117010
Stylizing 2.5-D video
In recent years considerable interest has been given to non-photorealistic rendering of photographs, video, and 3D models for illustrative or artistic purposes. Conventional 2D inputs such as photographs and video are easy to create and capture, while 3D models allow for a wider variety of stylization techniques, such as cross-hatching. In this paper, we propose using video with depth information (2.5-D video) to combine the advantages of 2D and 3D input. 2.5-D video is becoming increasingly easy to capture, and with the additional depth information, stylization techniques that require shape information can be applied. However, because 2.5-D video contains only limited shape information and 3D correspondence over time is unknown, it is difficult to create temporally coherent stylized animations directly from raw 2.5-D video. In this paper, we present techniques for processing 2.5-D video to overcome these drawbacks, and demonstrate several styles that can be created using these techniques.
44673585
Characterization of Errors in Compositing Panoramic Images
A panoramic image has a 360° horizontal field of view, and it can provide the viewer the impression of being immersed in the scene. A panorama is created by first taking a sequence of images while rotating the camera about a vertical axis. These images are then projected onto a cylindrical surface before being seamlessly composited. The cross-sectional circumference of the cylindrical panorama is called thecompositing length. This work characterizes the error in compositing panoramic images due to errors in some of the intrinsic parameters. The intrinsic camera parameters that are considered are the camera focal length and the radial distortion coefficient. We show that the error in the compositing length is more sensitive to the error in the camera focal length. Especially important is the discovery that the relative error in compositing length is always smaller than the relative error in the focal length. This means that the error in focal length can be corrected by iteratively using the composited length to compute a new and more correct focal length. Thiscompositing approach to camera calibrationhas the advantages of not requiring both feature detection and separate prior calibration.
2096181
Video editing using figure tracking and image-based rendering
We describe a new approach to video editing based on the semi-automatic segmentation of video into multiple layers and the composition of layers using image-based rendering. Using figure tracking and background motion estimation, we can segment a moving figure and reconstruct the background. Using geometrically-correct pixel reprojection, layers can be composited on the basis of the geometry of the underlying scene and the position of a virtual camera. We have implemented a prototype editing system called SpliceWorld.
40596005
Survey of image-based representations and compression techniques
We survey the techniques for image-based rendering (IBR) and for compressing image-based representations. Unlike traditional three-dimensional (3-D) computer graphics, in which 3-D geometry of the scene is known, IBR techniques render novel views directly from input images. IBR techniques can be classified into three categories according to how much geometric information is used: rendering without geometry, rendering with implicit geometry (i.e., correspondence), and rendering with explicit geometry (either with approximate or accurate geometry). We discuss the characteristics of these categories and their representative techniques. IBR techniques demonstrate a surprising diverse range in their extent of use of images and geometry in representing 3-D scenes. We explore the issues in trading off the use of images and geometry by revisiting plenoptic-sampling analysis and the notions of view dependency and geometric proxies. Finally, we highlight compression techniques specifically designed for image-based representations. Such compression techniques are important in making IBR techniques practical.
16190492
Noise Estimation from a Single Image
In order to work well, many computer vision algorithms require that their parameters be adjusted according to the image noise level, making it an important quantity to estimate. We show how to estimate an upper bound on the noise level from a single image based on a piecewise smooth image prior model and measured CCD camera response functions. We also learn the space of noise level functions how noise level changes with respect to brightness and use Bayesian MAP inference to infer the noise level function from a single image. We illustrate the utility of this noise estimation for two algorithms: edge detection and featurepreserving smoothing through bilateral filtering. For a variety of different noise levels, we obtain good results for both these algorithms with no user-specified inputs.
36636082
An accurate analytical delay model for BiCMOS driver circuits
An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration. >
32568915
Event Sentence Extraction in Korean Newspapers
Information extraction is to extract information about the main events in the text. This paper presents an event sentence extraction method in Korean newspapers for information extraction. Event sentences contain meaningful information such as the agent, the time and the place of an event. To extract these sentences, we acquire various features such as verbs, nouns, noun phrases, 3Ws, and their weights. And then, the system computes weights of sentences and extracts event sentences by our extraction algorithm. The experimental result shows the average precision of 86.1%.
1671645
Domino logic synthesis minimizing crosstalk
Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive cross-coupling effects are developed for domino logic circuit. The nets in a crosstalk immunity set are free from crosstalk effects for any combination of input vectors. New algorithms for CIS identification and minimization are proposed to maximize the chance of crosstalk minimization in routing step. Our routing algorithm augmented with CIS information searches for optimal solution to minimize maximum crosstalk the circuit would experience. Experimental results show that the reduction of maximum crosstalk is up to 30% with CIS-augmented routing.
9872720
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
High-speed domino logic is now prevailing in performance critical block of a chip. Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost up the transition speed in proposed circuitry, a well-established dual threshold voltage technique is exploited. Dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in clock tree and logic gates effectively. Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.
29231099
A new circuit optimization technique for high performance CMOS circuits
A novel transistor sizing technique with a concise problem formulation and rigorous optimization scheme is described. A circuit optimization technique for high-performance CMOS circuits is presented for proper balance of chip speed and area. The timing specification is accommodated as a design constraint, and reliability issues in the charge sharing and noise margin, which have been neglected in previous optimization tools, are also embedded into the design constraints. The optimization scheme used in this approach does not require derivatives, and therefore, can be used for a broad class of continuous cost functions. Special attention is given to the most effective use of silicon area based on the sensitivity of the delay time with respect to the transistor size. Excessively large transistor sizes are avoided by using the resource redistribution scheme. This timing allocation scheme allows the computation time to be linearly proportional to the number of gates. >