38190971
Modeling and Analysis of Performance Aspects for Software Architecture: a Uml-based Approach
Much attention has been focused on the problem of effectively designing software architecture to meet non-functional requirements (NFRs). The significant benefits of such work include detecting and removing defects earlier, which reduces development time and cost while improving the quality of the design; in turn the improved quality of the design makes it easier to maintain as the system evolves. The Formal Design Analysis Framework (FDAF) is an aspect-oriented approach proposed to support the design and analysis of multiple NFRs for distributed, concurrent, and real-time systems. In FDAF, non-functional requirements are realized and represented as reusable aspects in the repository; designs are captured in an extended version of the Unified Modeling Language (UML). FDAF supports the automated translation of extended UML designs into existing formal notations. Subsequently, the analysis of an aspect design is achieved using existing formal analysis tools, which leverages a large body of work in the research community. This paper focuses on the modeling and analysis of the response time performance aspect. The algorithms for translating extended UML diagrams into Rapide, the proofs of correctness for the algorithms, and an illustration of the FDAF approach using the Domain Name System are presented.
206572113
Measuring distance between program features
We present a metric to determine the distance between the features of a software system. Such a measurement can elucidate how features of the system being examined are close to each other. We first use an execution slice-based technique to identify a set of code (basic blocks in our case) that is used to implement each feature. Then, depending on whether the execution frequency of each block is considered during the construction of such sets of code, a static as well as a dynamic distance is computed for each pair of features. These two types of distance differ in that the former computes the distance between two features only by how these features are implemented in the system, while the latter also takes into account how each feature is executed based on a user's operational profile. In other words, the static distance quantitatively gives the closeness of two features from the system implementation point of view, whereas the dynamic distance presents such closeness from the users' execution point of view. To illustrate the use of our metric, we report a case study on a Symbolic Hierarchical Automated Reliability and Performance Evaluator (SHARPE). The results of our study suggest that the distance metric discussed in this paper can provide a good measurement, in a quantitative way, of how close two program features are. Such information can also serve as a good start to understanding how a modification made to one feature is likely to affect other features.
30609851
An integrated solution for creating dependable software
Software testing and maintenance are the two most expensive phases of the software life cycle. Why, in general, are customers not satisfied with the quality of software? Studies have shown that approximately 20% of a software system is responsible for 80% of the faults and over the lifetime of an average software system as much as 70% of the cost is estimated to be dedicated to testing and maintenance. Clearly an appropriate methodology ought to be employed to address these high-leverage concerns. With the increased emphasis on software quality and the pressure to deliver software faster and cheaper such a methodology should encompass software design, architecture, development, testing, and maintenance as a whole and provide an integrated solution that leads to the creation of more dependable software. In addition, it is also crucial to have a set of effective tools with user-friendly interfaces available to software practitioners to apply this methodology in real-life contexts. We explain how to take advantage of sophisticated analysis of the dynamic behavior of the software being developed to help programmers, as well as testers, accomplish their assignments more effectively and efficiently.
39945640
Smart debugging software architectural design in SDL
Statistical data show that it is much less expensive to correct software bugs at the early design stage rather than the late stage of the development process when the final system has already been implemented and integrated together. The use of slicing and execution histories as an aid in software debugging is well established for programming languages like C and C++; however, it is rarely applied in the field of software design specification. We propose a solution by applying the source code level technologies to debugging software designs represented in a high-level specification and description language such as SDL. More specifically, we extend execution slice-based heuristics from source code-based debugging to the software design specification level. Suspicious locations in an SDL specification are prioritized by their likelihood of containing faults. Locations with a higher priority should be examined first rather than those with a lower priority as the former are more likely to contain the faults. A debugging tool, SmartD/sub DSL/, with user-friendly interfaces was developed to support our method. An illustration is provided to demonstrate the feasibility of using our method to effectively debug an architectural design.
31350744
Redesigning legacy systems into the object-oriented paradigm
Object-oriented/sup 1/ languages support many modern programming paradigms such as information hiding, inheritance, polymorphism, and dynamic binding. As a result, software systems implemented in OO languages are more reusable and reliable than those in non-OO. Many legacy software systems were created before OO programming became popular and needed to be redesigned and updated to OO programs. The process of abstracting OO designs from the procedural source code was often done manually or with limited assistance from program structural diagrams. Most reengineering focuses on the functionality of the original program, and the OO redesign often results in a completely new design based on the designers' understanding of the original program. Such an approach is not sufficient, for it not only takes time and effort for designers to become familiar with the original program, but the approach itself is also mistake-prone due to the human involvement. This paper presents a computer-aided semi-automatic method that abstracts OO designs from the original procedural source code. More specifically, it is a method for OO redesign based on program structural diagrams, visualization, and execution slice. We conducted a case study by applying this method to an inventory management software system. Results indicate that our method can effectively and efficiently abstract an appropriate OO design out of the original C code as well as re-generate part of the system in C++ code based on this new OO design.
13223545
Quantifying the closeness between program components and features
Abstract One of the most important steps towards effective software maintenance of a large complicated system is to understand how program features are spread over the entire system and their interactions with the program components. However, we must first be able to represent an abstract feature in terms of some concrete program components. In this paper, we use an execution slice-based technique to identify the basic blocks which are used to implement a program feature. Three metrics are then defined, based on this identification, to determine quantitatively , the disparity between a program component and a feature, the concentration of a feature in a program component, and the dedication of a program component to a feature. The computations of these metrics are automated by incorporating them in a tool ( χ Suds), which makes the use of our metrics immediately applicable in real-life contexts. We demonstrate the effectiveness of our technique by experimenting with a reliability and performance evaluator. Results of our study suggest that these metrics can provide an indication of the closeness between a feature and a program component which is very useful for software programmers and maintainers to better understand the system at hand.
9691799
Targeted Data Prefetching
Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data. The success of any data prefetching scheme depends on three factors: timeliness, accuracy and overhead. In most hardware prefetching mechanism, the focus has been on accuracy – ensuring that the predicted address do turn out to be demanded in a later part of the code. In this paper, we introduce a simple hardware prefetching mechanism that targets delinquent loads, i.e. loads that account for a large proportion of the load misses in an application. Our results show that our prefetch strategy can reduce up to 45% of stall cycles of benchmarks running on a simulated out-of-order superscalar processor with an overhead of 0.0005 prefetch per CPU cycle.
8187290
Model-driven SoC design via executable UML to SystemC
We present a system level description mechanism based on UML-notations from which one can automatically extract SystemC code. Our modelling framework is based on a restricted set of UML diagram types and some standard extensions influenced by the communication infrastructure of SystemC. The system specifications are developed using the UML-compatible tool, Rhapsody (2004). We then translate the internal representation of the design generated by Rhapsody into SystemC code. The extensions we have implemented using the stereotype feature of the Rhapsody tool pull up the communication infrastructure and timing features of SystemC to the UML-level. Consequently, we can describe executable platforms at the UML-level as well as translate UML-based application descriptions to SystemC level.
6734680
Compiler Optimizations for Adaptive EPIC Processors
Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.
12405719
Playing with Heritage: Semiotics and cultural analysis of the online Mahjong game in the global environment
13948106
Design of clocked circuits using UML
Clocking is an essential component of any embedded system design. However, traditional design techniques are either short of clocking support or too complex for users. The Unified Modeling Language (UML) has been proposed as design tool in real time system design, but the clocking semantics has not been properly dealt with. In this paper, we will present our experience of using UML to design a clocked system. In particular, UML is used to model the digital down converter, an essential component of software radios. Our tool chain automatically generates the simulation as well as synthesizes the final implementation.