42975476
An Integrated Performance Analysis Tool for SPMD Data-Parallel Programs
Abstract A new generation of data parallel languages have been proposed whereby a user specifies how data structures are to be distributed amongst the processor nodes of a distributed-memory machine. Based on this information, the compiler then generates code for the parallel application. Although this approach significantly simplifies the development of the initial version of a parallel application, selection of good data distributions leading to efficient computations is often quite difficult. Therefore, performance debuggers are needed to yield insights into the data distribution effects. On the other hand, most of the existing approaches to performance debugging are very general and thus do not provide the user feedback in terms of the high level programming model or the source code of the parallel application. In this paper, we describe a novel approach to performance debugging of data parallel programs. The design and implementation of a visual performance debugger is described that is specifically targeted to meet the performance debugging requirements of a data-parallel programming model based on user-specified data distributions. The performance debugger is part of an integrated programming environment, called EPPP, which also supports a data parallel compiler and a parallel architecture simulator. Thus development and performance debugging of an application may be done either on the real hardware or by using the simulator. The code for EPPP can be obtained free of cost (contact web address, http://www.crim.ca/apar).
46228924
Communication Using a Reconfigurable and Reliable Transport Layer Protocol
Although TCP is known to be inefficient over networks such as wireless, satellite, and log-fat-pipes, it is still the most widely used transport layer protocol even on these networks. In this paper, we explore an alternative strategy for designing a reliable transport layer protocol that is much more suitable for today's mobile and other types of non-conventional networks. The objective here is to have a single protocol that is compatible with today's communication software and can be easily made to perform better over all types of network. The outcome of the research is a reconfigurable, user-level, reliable transport layer protocol, called RRTP (Reliable and Reconfigurable Transport Protocol) that is TCP-friendly, i.e. it asymptotically converges to fairness as in the case of LIMD (Linear Increase Multiplicative Decrease) algorithms. The protocol is implemented on top of UDP, but it can also easily be incorporated into OS kernels. The paper presents the RRTP algorithm and the key parameters that are necessary for its reconfiguration. We evaluate our protocol using the standard network simulation tool (ns2). Several representative network configurations are used to benchmark the performance of our protocol against TCP in terms of network throughput and congestion loss rate. It is observed that under normal operating conditions, our protocol has a performance advantage of 30% to 700% over TCP in lossy, wireless environments as well as high bandwidth, high latency networks.
28610861
A User Level, Reliable, and Reconfigurable Transport Layer Protocol
It is well known that TCP is not suitable for a number of environments such as wireless, satellite, and long-fat-pipe networks. At the same time, there is no other single transport protocol that would outperform TCP in all situations. In this paper, we explore an alternative transport layer protocol that is more suitable for today’s mobile as well as other non-conventional network environments. The result is a user-level, reconfigurable, TCP-friendly (asymptotically converges to fairness as in the case of LIMD (Linear Increase Multiplicative Decrease) algorithms) transport layer protocol, called RRTP (Reliable and Reconfigurable Transport Protocol), which runs atop of UDP. We evaluate our protocol using the standard network simulation tool (ns2). Several representative network configurations are used to benchmark the performance of our protocol against TCP in terms of network throughput and congestion loss rate. It is observed that under normal operating conditions, our protocol has a performance advantage of 30% to 700% over TCP in lossy, wireless environments as well as high bandwidth, high latency networks.
5517060
Structuring Distributed Algorithms in a Workstation Environment: The FrameWorks Approach
11606897
Malicious ICMP Tunneling: Defense against the Vulnerability
This paper presents a systematic solution to the problem of using ICMP tunneling for covert channel. ICMP is not multiplexed via port numbers and the data part of the ICMP packet provides considerable bandwidth for malicious covert channels. These factors make it an integral part of many malicious software like remote access and denial of service attack tools. These tools use ICMP to establish covert communication channels. In this paper a stateless model is proposed to prevent ICMP tunneling. A Linux kernel module was implemented to demonstrate the proposed stateless solution. The module enforces a fixed payload policy for ICMP packets and virtually eliminates ICMP tunneling which arises due to the data carrying capability of ICMP. The performance impact on end hosts and routers due to the stateless monitoring model is described.
9094346
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.
15601419
A Peer-to-Peer Reference Architecture
Peer-to-peer (P2P) applications are extremely popular on the Internet because they allow users to share information in a decentralized manner. Internet users use file-sharing applications (e.g., BitTorrent, KaZaA) to share and exchange files and collaboration applications (e.g., Jabber, Groove) to exchange chat messages and work on shared documents. A reference architecture for a domain provides an architecture template which can be used as a starting point for designing the software architecture of a system in that domain. Despite the popularity of P2P applications there is no reference architecture for the P2P domain. This paper presents a reference architecture for the P2P domain. The reference architecture has been designed to satisfy the concerns that a P2P application needs to address. The reference architecture takes a service-centric view of the P2P domain. The reference architecture can be used to describe the structure of existing P2P applications and middlewares. The paper validates the reference architecture by describing the structure of some of the existing P2P applications and middlewares using the reference architecture
29012055
Variable Order Verification Use of Logic Representation
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. In the last 15 years, a number of applications based on efficient manipulation of Boolean functions gained industrial significance, notably in automated design and verification of logic circuits. The efficient representation and manipulation of Boolean functions is important for many algorithms in a wide variety of applications in particular, many problems in computer-aided design for digital circuits (CAD). The efficiency of the Boolean manipulation depends on the form of representation of the Boolean function. It is unavoidable and important problem to find a variable ordering which minimize the size of a BDD, since variable ordering has a great influence on the computation time and storage requirements for Boolean function manipulation number of times each variable takes part in the Logic operation to obtain the best possible the variable order. This paper describes a technique for finding the best variable ordering by analyzing the logic gate representation in the given Boolean function. Algorithm starts with initial variable ordering. The system will check each sub expression to find out the number times each variable takes part in each type of logic operations. The number of occurrences for each variable will be stored and then all the totals are arranged in descending order to identify the variable ordering for that Boolean function. If more than one input variables have the same total then a special criteria will be used to break the tie: We present graph-based evidence of the improvement obtained by using highly effective logical verification based variable ordering technique for BDDs. It is shown that the effectiveness of the Decision Diagram is mainly depending on the variable ordering selected. It is not practical to have any unique ordering for a given Boolean function and it can be selected among the number of best results, what will be more appropriate with the design. This new technique, easy to implement and automate, consistently creates high quality variable ordering for Boolean function.
9328622
Dynamic Query-Based Debugging
Program errors are hard to find because of the cause-effect gap between the time when an error occurs and the time when the error becomes apparent to the programmer. Although debugging techniques such as conditional and data breakpoints help to find error causes in simple cases, they fail to effectively bridge the cause-effect gap in many situations. Dynamic query-based debuggers offer programmers an effective tool that provides instant error alert by continuously checking inter-object relationships while the debugged program is running. To speed up dynamic query evaluation, our debugger (implemented in portable Java) uses a combination of program instrumentation, load-time code generation, query optimization, and incremental reevaluation. Experiments and a query cost model show that selection queries are efficient in most cases, while more costly join queries are practical when query evaluations are infrequent or query domains are small.