15654186
The Architecture and Performance of WMPI II
WMPI II is the only commercial implementation of MPI 2.0 that runs on both Windows and Linux clusters. It evolved from the first ever Windows version of MPI, then a port of MPICH, but is now fully built from its own code base. It supports both 32 and 64 bit versions and mixed clusters of Windows and Linux nodes. This paper describes the main design decisions and the multithreaded, non-polling architecture of WMPI II. Experimental results show that, although WMPI II has figures comparable to MPICH and LAM for latency and bandwidth, most application benchmarks perform significantly better when running on top of WMPI II.
1492279
Experimental assessment of parallel systems
In the research reported in this paper, transient faults were injected in the nodes and in the communication subsystem (by using software fault injection) of a commercial parallel machine running several real applications. The results showed that a significant percentage of faults caused the system to produce wrong results while the application seemed to terminate normally, thus demonstrating that fault tolerance techniques are required in parallel systems, not only to assure that long-running applications can terminate but also (and more important) that the results produced are correct. Of the techniques tested to reduce the percentage of undetected wrong results only ABFT proved to be effective. For other simple error detection methods to be effective, they have to be designed in, and not added as an after thought. Faults injected in the communication subsystem proved the effectiveness of end-to-end CRCs on the data movements between processors.
11507520
Web-based Metacomputing with JET
42069370
An Experimental Evaluation of Coordinated Checkpointing in a Parallel Machine
Coordinated checkpointing represents a very effective solution to assure the continuity of distributed and parallel applications in the occurrence of failures. In previous studies it has been proved that this approach achieved better results than independent checkpointing and message logging. However, we need to know more about the real overhead of coordinated checkpointing and get sustained insights about the best way to implement this technique of fault-tolerance. This paper presents an experimental evaluation of coordinated checkpointing in a parallel machine. It describes some optimization techniques and presents some performance results.
35292815
WPVM: parallel computing for the people
This paper presents WPVM, a PVM implementation for the “MS Windows” — Microsoft Windows Operating System. WPVM stands for “Windows Parallel Virtual Machine” and intends to exploit the potential computational power of the small and medium PC LANs that proliferate in corporations and universities. As the original PVM [1–2], WPVM creates the abstraction of a parallel machine from a cluster of computers connected by a network. This virtual machine appears as a single and manageable resource to the programmer. The difference is that the target machines for WPVM are personal computers with MS Windows instead of UNIX machines. However, this system is compatible with the original PVM, meaning that we can use virtual machines composed simultaneously of UNIX and MS Windows machines.
35428904
Portable checkpointing and recovery
This paper presents a checkpointing scheme that was implemented in a parallel library that runs on top of CHIMP/MPI. The main goals of the checkpointing mechanism are portability and efficiency. It runs on every platform supported by MPI in a machine-independent way. The scheme allows the migration of checkpoints and offers a flexible recovery mechanism based on data-reconfiguration. Some performance results will be presented at the end of the paper together with some techniques that can be used to increase the efficiency of the checkpointing mechanism.
1093169
An Embedded Language Approach to Router Specification in Curry
The development of modern routers require a significant effort to be designed, built, and verified. While hardware routers are faster, they are difficult to configure and maintain. Software routers, on the other hand, are slower but much more flexible, easier to configure and maintain, less expensive, etc. Recently, a modular architecture and toolkit for building software routers and other packet processors has been introduced: the Click system. It includes a specification language with features for declaring and connecting router elements and for designing abstractions.
37612228
An approach to testability improvement of mixed-signal boards
The increasing complexity of mixed-signal boards makes an integrated analogue/digital testability approach an attractive proposition. This paper investigates one such approach based on the use of mixed-signal test support ICs together with standard board level test infrastructures. The architecture of a test support IC and preliminary experimental results are also presented.<<ETX>>
34103836
Lexical Categorical Disambiguation using a Multi-Agent Systems Architecture
We present a distributed architecture model for lexical categorical disambiguation based on multi agent systems. This proposal aims to minimize some shortcomings from sequential approaches to natural language processing systems, through cooperation among intelligent and distributed modules. We have proposed a model for a linguistic society of agents which includes linguistic knowledge as well as a set of procedures to manipulate it, and mechanisms for social reasoning. The disambiguation is solved by a subsociety of acquaintance agents that use a communication protocol based on cooperative learning in order to reach a common goal.
14688474
A processor for testing mixed-signal cores in system-on-chip
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.
37459114
Cluster Analysis of Named Entities
This paper presents a statistics-based and language independent unsupervised approach for clustering possible named entities. We describe and motivate the features and statistical filters used by our clustering process. Using the Model-Based Clustering Analysis software we obtained different clusters of named entities. The method was applied to Bulgarian and English. For some clusters, precision is close to 100%; this helps human validation and saves time. Other clusters still need further refinement.