37382391
Horizons of Parallel Computation
This paper considers the ultimate impact of fundamental physical limitations---notably, speed of light and device size---on parallel computing machines. Although we fully expect an innovative and very gradual evolution to the limiting situation, here we take the provocative view of exploring the consequences of the accomplished attainment of the physical bounds. The main result is that scalability holds only for neighborly interconnections, such as the square mesh, of bounded-size synchronous modules, presumably of the area-universal type. We also discuss the ultimate infeasibility of latency-hiding, the violation of intuitive maximal speedups, and the emerging novel processor-time tradeoffs.
930169
Sequencing-by-hybridization at the information-theory bound: an optimal algorithm
In a recent paper [PFU99) we have introduced a novel probing scheme for DNA sequencing by hybridization (SBH). The new gapped-probe scheme combines natural and universal bases in a well defined periodic pattern. It was shown in [PFU99] that the performance of the gapped-probe scheme (in terms of the length of a sequence that can be uniquely reconstructed using a given library size of probes) is significantly better than the standard scheme based on oligomer probes.
In this paper we present and analyze a new, more powerful, sequencing algorithm for the gapped-probe scheme. We prove that the new algorithm exploits the full potential of the SBH technology with high-confidence performance, that comes within a small constant factor (about 2) of the information-theory bound. Moreover, this performance is achieved while maintaining running time linear in the target sequence length.
62245037
Processor—Time Tradeoffs under Bounded-Speed Message Propagation: Part I, Upper Bounds
Upper bounds are derived for the processor—time tradeoffs of machines such as linear arrays and two-dimensional meshes, which are compatible with the physical limitation expressed by bounded-speed propagation of messages (due to the finiteness of the speed of light). It is shown that parallelism and locality combined may yield speedups superlinear in the number of processors. The speedups are inherent, due to the optimality of the obtained tradeoffs as established in a companion paper.Simulations of multiprocessor machines are developed by analogous machines with fewer processors. A crucial role is played by the hierarchical nature of the memory system. A divide-and-conquer technique for hierarchical memories is developed, based on the graph-theoretic notion of a topological separator. For multiprocessors, this technique also requires a careful balance of memory access and interprocessor communication costs, which leads to nonintuitive orchestrations of the simulation process.
1952504
Data structures and algorithms for the string statistics problem
Given a textstringx of lengthn, theMinimal Augmented Suffix Tree T (x) ofx is a digital-search index that returns, for anyquery stringw and in a number of comparisons bounded by the length ofw, the maximum number of nonoverlapping occurrences ofw inx. It is shown that, denoting the length ofx byn, T(x) can be built in timeO(n log2n) and spaceO(n logn), off-line on a RAM.
18686062
Sequencing-by-hybridization revisited: the analog-spectrum proposal
All published approaches to DNA sequencing by hybridization (SBH) consist of the biochemical acquisition of the spectrum of a target sequence (the set of its subsequences conforming to a given probing pattern) followed by the algorithmic reconstruction of the sequence from its spectrum. In the "standard" or "uniform" approach, the probing pattern is a string of length L and the length of reliably reconstructible sequences is known to be m/sub len/ = O(2/sup L/). For a fixed microarray area, higher sequencing performance can be achieved by inserting nonprobing gaps ("wild-cards") in the probing pattern. The reconstruction, however, must cope with the emergence of fooling probes due to the gaps and algorithmic failure occurs when the spectrum becomes too densely populated, although we can achieve m/sub comp/ = O(4/sup L/). Despite the combinatorial success of gapped probing, all current approaches are based on a biochemically unrealistic spectrum-acquisition model (digital-spectrum). The reality of hybridization is much more complex. Departing from the conventional model, in this paper, we propose an alternative, called the analog-spectrum model, which more closely reflects the biochemical process. This novel modeling reestablishes probe length as the performance-governing factor, adopting "semidegenerate bases" as suitable emulators of currently inadequate universal bases. One important conclusion is that accurate biochemical measurements are pivotal to the success of SBH. The theoretical proposal presented in this paper should be a convincing stimulus for the needed biotechnological work.
45504051
Horizons of Parallel Computation
This paper considers the ultimate impact of fundamental physical limitations—notably, speed of light and device size—on parallel computing machines. Although we fully expect an innovative and very gradual evolution to the limiting situation, we take here the provocative view of exploring the consequences of the accomplished attainment of the physical bounds. The main result is that scalability holds only for neighborly interconnections, such as the square mesh, of bounded-size synchronous modules, presumably of the area-universal type. We also discuss the ultimate infeasibility of latency-hiding, the violation of intuitive maximal speedups, and the emerging novel processor-time tradeoffs.
9517013
Beware of the Model: Reflections on Algorithmic Research
Over the past four decades the design and analysis of algorithms has been a vibrant area of computer science research, since it was early realized that adoption of a superior algorithm could achieve accelerations unattainable by conceivable technological improvements.
17687657
Work-Preserving Speed-Up of Parallel Matrix Computations
Brent's scheduling principle provides a general simulation scheme when fewer processors are available than specified by the fastest parallel algorithm. Such a scheme preserves, under slow-down, the actual number of executed operations, also called work. In this paper we take the complementary viewpoint, and rather than consider the work-preserving slow-down of some fast parallel algorithm, we investigate the problem of the achievable speed-ups of computation while preserving the work of the best-known sequential algorithm for the same problem. The proposed technique, eminently applicable to problems of matrix-computational flavor, achieves its result through the interplay of two algorithms with significantly different features. Analogous but structurally different "interplays" have been used previously to improve the algorithmic efficiency of graph computations, selection, and list ranking. We demonstrate the efficacy of our technique for the computation of path algebras in graphs and digraphs and various fundamental computations in linear algebra. Some of the fundamental new algorithms may have practical value; for instance, we substantially improve the algorithmic performance of the parallel solution of triangular and Toeplitz linear systems of equations and the computation of the transitive closure of digraphs.
7946687
Practical constructive schemes for deterministic shared-memory access
We present three explicit schemes for distributingM variables amongN memory modules, whereM=Θ(N1.5),M = Θ(N2), andM=Θ(N3), respectively. Each variable is replicated into a constant number of copies stored in distinct modules. We show thatN processors, directly accessing the memories through a complete interconnection, can read/write any set ofN variables in worst-case timeO (N1/3),O(N1/2), andO(N2/3), respectively for the three schemes. The access times for the last two schemes are optimal with respect to the particular redundancy values used by such schemes. The address computation can be carried out efficiently by each processor without recourse to a complete memory map and requiring onlyO(1) internal storage.
15570871
Restructuring of Arithmetic Expressions For Parallel Evaluation
Let <italic>E</italic> be an arithmetic expression involving <italic>n</italic> variables, each of which appears just once, and the possible operations of addition, multiplication, and division. Although other cases are considered, when these three operations take unit time the restructuring algorithms presented in this paper yield evaluation times no greater than 2.88 log<subscrpt>2</subscrpt><italic>n</italic> + 1 and 2.08 log<subscrpt>2</subscrpt><italic>n</italic> for general expressions and division-free expressions, respectively. The coefficients are precisely given by 2/log<subscrpt>2</subscrpt>α ≈ 2.88 and 1/log<subscrpt>2</subscrpt><italic>β</italic> ≈ 2.08, where <italic>α</italic> and <italic>β</italic> are the positive real roots of the equations <italic>z</italic><supscrpt>2</supscrpt> = <italic>z</italic> + 1 and <italic>z</italic><supscrpt>4</supscrpt> = 2<italic>z</italic> + 1, respectively. While these times were known to be of order log<subscrpt>2</subscrpt><italic>n</italic>, the best previously known coefficients were 4 and 2.15 for the two cases.
The authors conjecture that the present coefficients are the best possible, since they have exhibited expressions which seem to require these times within an additive constant.
The paper also gives upper bounds to the restructuring time of a given expression <italic>E</italic> and to the number of processors required for its parallel evaluation. It is shown that at most <italic>O</italic><italic>(n</italic><supscrpt>1.44</supscrpt><italic>)</italic> and <italic>O</italic>(n<supscrpt>1.82</supscrpt><italic>)</italic> operations are needed for restructuring general expressions and division-free expression, respectively.
  It is pointed out that, since the order of the compiling time is greater than <italic>n</italic> log <italic>n</italic>, the numbers of required processors exhibit the same rate of growth in <italic>n</italic> as the corresponding compiling times.
38486057
VLSI Algorithms and Architectures
In this paper we consider the relationship between algorithms and parallel VLSI architectures. Starting from the premise that VLSI is the natural habitat for parallel algorithmics, we outline the desirable features of VLSI architectures. Next we discuss the notion of algorithmic paradigm, as the data transfer pattern of a class of specific algorithms. The recursive combination paradigm (applicable to merging, sorting, FFT, permutation, etc.), is naturally mapped to the awkward binary cube architecture. Thus we analyze four viable architectures — the shuffle-exchange, the linear array, the mesh, and the cube-connected-cycles — which emulate the binary cube. Finally, we illustrate the mechanisms of pipelining, pleating, and mixing, which play a significant role in matching algorithms and architectures.