9006063
Performance evaluation model for buyer-carts in B2B EC
Even though B2B EC is becoming popular, there have been not so much studies about performance evaluation methodology for B2B systems. In this paper, after analyzing buyer carts systematically focusing on the buyer's interactional efforts on the typical buying processes of each buyer cart, we propose a quantitative performance evaluation model. For this, we categorize buyer carts in B2B EC as s-cart, i-cart, and b-cart depending upon its residing sites: seller, intermediary, and buyer sites. And after proposing the desired features of buyer carts in B2B EC as identification, collection, trashing, ordering, payment, tracking, recording, purchasing decision support, and transmission of records to e-procurement systems, we derive a performance evaluation model by calculating detail subprocesses from the desired features' viewpoints. By setting variables from interviews of business buyers in 30 listed companies in Korea, we try to evaluate the performance of buyer-carts in B2B EC. In this paper, we suggest a new methodology of performance evaluation for B2B systems, and show that the b-cart platform is more efficient than other buyer carts especially in B2B EC.
9935268
Case and Constraint-Based Apartment Construction Project Planning System: FASTrak-APT
To effectively generate a fast and consistent apartment construction project network, Hyundai and KAIST have developed a case and constraint based project planning expert system for apartment domain, FASTrak-APT, inspired by the fact that human expert project planner uses previous cases for planning a new project and modifies them using her/his knowledge on domain constraints. This largescale, case based and mixed-initiative planning system integrated with intensive constraint-based adaptation utilizes semantic level meta-constraints and human decisions for compensating incomplete cases imbedding specific planning knowledge. The case and constraint based architecture inherently supports cross-checking cases with constraints during the system development and maintenance. This system has drastically reduced the time and effort required for initial project planning, improved the quality and completeness of the generated plans, and is expected to give the company the competitive advantage in contract bids for new contracts.
393666
DAS: Intelligent Scheduling Systems for Shipbuilding
Daewoo Shipbuilding Company, one of the largest shipbuilders in the world, has experienced great deal of trouble with the planning and scheduling of its production process. To solve the problems, from 1991 to 1993, Korea Advanced Institute of Science and Technology (KAIST) and Daewoo jointly conducted the Daewoo Shipbuilding Scheduling (das) Project. To integrate the scheduling expert systems for shipbuilding, we used a hierarchical scheduling architecture. To automate the dynamic spatial layout of objects in various areas of the shipyard, we developed spatial scheduling expert systems. For reliable estimation of person-hour requirements, we implemented the neural network-based person-hour estimator. In addition, we developed the paneled-block assembly shop scheduler and the long-range production planner. For this large-scale project, we devised a phased development strategy consisting of three phases: (1) vision revelation, (2) data-dependent realization, and (3) prospective enhancement. The DAS systems were successfully launched in January 1994 and are actively being used as indispensable systems in the shipyard, resulting in significant improvement in productivity and visible and positive effects in many areas.
9952889
Extraction of Structured Rules from Web Pages and Maintenance of Mutual Consistency: XRML Approach
Web pages provide valuable knowledge for human comprehension in text, tables, and mathematical notations. However, the extraction and maintenance of structured rules from the Web pages are not easy tasks. To tackle these problems, we adopt the eXtensible Rule Markup Language framework. The RIML (Rule Identification Markup Language) and RSML (Rule Structure Markup Language) are two compliant representations in XRML for this purpose. RIML identifies the implicit rules in the Web pages possibly using multiple pages to make a rule or rule group. RSML specifies the complete rule structure to be processed by software agents or expert systems. 
 
In this study, we cover the natural text, tables, and implicit numeric functions in the texts. In order to fulfill the research goal, we define the necessary tags for the rule extraction and maintenance in XRML. Typical ones include tags for rule grouping, tabular rules, numeric operators, and functions. The rule acquisition process consists of rule base design, rule identification with RIML, and rule structuring with RSML. The maintenance process for the revisions that may occur either in Web pages and structured rules is also described. The approach is demonstrated with the shipping cost comparison on the electronic book stores.
19081367
Robust technique for estimating the bearings of cyclostationary signals
This paper deals with the problem of direction finding using cyclostationary signals in the presence of cycle frequency error (CFE). By exploiting the signal cyclostationarity, cyclic MUSIC and conjugate cyclic MUSIC presented in Gardner (Cyclostationarity in Communications and Signal Processing, New York, 1994; Proc. IEEE 76 (1988) 845) have been shown to be effective for signal-selective direction finding. However, they suffer from severe performance degradation even if there is a small error in the cycle frequency of the signals of interest. In this paper, we first evaluate the performance of conjugate cyclic MUSIC when CFE exists. An analytical formula is derived to show the behavior of the performance degradation due to CFE. By exploiting the eigenstructure of the conjugate cyclic correlation matrix of the received array data, we develop a technique including a method for estimating the cycle frequency of the SOI and an efficient method in conjunction with a subspace-fitting algorithm to achieve robust direction finding against CFE. Several simulation examples confirming the theoretical analysis and showing the effectiveness of the proposed technique are also presented.
17186964
A Ubiquitous Fashionable Computer with an i-Throw Device on a Location-Based Service Environment
The ubiquitous fashionable computer (UFC), introduced in this paper, is a wearable computer that allows people to exploit ubiquitous computing environment in a user-friendly manner. We present the design approach and philosophy of the UFC that is wearable, aesthetic, and intuitive. The UFC supports the interoperability of various communication interfaces among WLAN, Bluetooth and ZigBee devices. We developed a wireless gesture recognition device, called i -Throw, which is small enough to be worn on one's finger like a ring. The UFC, with the help of i -Throw, can control ubiquitous environment using an intuitive hand motion. To explain the practical use of the UFC platform and the user-friendly interaction with ubiquitous environment, we implemented a ubiquitous testbed where multiple UFC users interact with various ubiquitous devices or other UFC users. In addition, we implemented a practical application which makes it possible to exchange the various objects and control ubiquitous devices very easily.
32342128
Performance Analysis of an Input Queueing ATM Switch with Two Priority Classes
Abstract In this paper, we study an input queueing asynchronous transfer mode (ATM) switch with the preemptive priority scheme. Up to now, many researchers have studied this switch, but their models do not yield accurate results. Therefore, we propose another model and analyze the performance of the switch for two different arrival processes, that is, the independent priority arrival process (IPAP) and the dependent priority arrival process (DPAP). In this paper, we model a virtual head of line (HOL) queue like the previous works, and analyze it using a three-dimensional Markov chain. As for each input queue, we model it as a two-class Geomx/Geom/1 queue with preemptive priority. By using this model, we obtain the mean queueing delay of the low priority class and the maximum throughput of the switch. In case of the IPAP, we compare our result with simulation and those of the previous works to show that our model yields more accurate results. In addition, we compare the performances of those two arrival processes to illustrate their difference.
54356023
A monitoring sensor management system for grid environments
Large distributed systems, such as computational grids, require a large amount of monitoring data be collected for a variety of tasks, such as fault detection, performance analysis, performance tuning, performance prediction and scheduling. Ensuring that all necessary monitoring is turned on and that the data is being collected can be a very tedious and error-prone task. We have developed an agent-based system to automate the execution of monitoring sensors and the collection of event data.
14452578
Automatically mapping code on an intelligent memory architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, the two processors should overlap their execution as much as possible. With our algorithm, applications are mapped fully automatically using both static and dynamic information. Using a set of standard applications and a simulated architecture, we show average speedups of 1.7 for numerical applications and 1.3 for nonnumerical applications over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be cost-effectively exploited and represents one step toward effectively mapping code on intelligent memory systems.