39878736
Unsupervised Learning of Pattern Templates from Unannotated Corpora for Proper Noun Extraction
This paper describes an approach to extracting proper nouns in the very large text corpora without using the lexicon or cue word dictionary. At first, we train the pattern for extracting the proper nouns by applying the initial proper names into the unannotated corpora that does not have any tags yet. And then we continuously apply the pattern templates into the corpora in order to extract new proper nouns until certain period.
11955356
Automatic Segmentation of Words using Syllable Bigram Statistics
We present a syllable bigram model for segmenting a Korean sentence into words and correcting word-spacing errors in the spelling checker. We evaluated the system’s performance for automatic word segmentation, word-spacing error detection, and the word-splitting problem of the character recognition system at the end of a line.
7236201
Catadioptric self-calibration
We have assembled a standalone, movable system that can capture long sequences of omnidirectional images (up to 1,500 images at 6.7 Hz and a resolution of 1140/spl times/090). The goal of this system is to reconstruct complex large environments, such as an entire floor of a building, from the captured images only. In this paper, we address the important issue of how to calibrate such a system. Our method uses images of the environment to calibrate the camera, without the use of any special calibration pattern, knowledge of camera motion, or knowledge of scene geometry. It uses the consistency of pairwise tracked point features across a sequence based on the characteristics of catadioptric imaging. We also show how the projection equation for this catadioptric camera can be formulated to be equivalent to that of a typical rectilinear perspective camera with just a simple transformation.
17348246
Lighting interpolation by shadow morphing using intrinsic lumigraphs
Densely-sampled image representations such as the light field or lumigraph have been effective in enabling photorealistic image synthesis. Unfortunately, lighting interpolation with such representations has not been shown to be possible without the use of accurate 3D geometry and surface reflectance properties. In this paper we propose an approach to image-based lighting interpolation that is based on estimates of geometry and shading from relatively few images. We decompose captured light fields at different lighting conditions into intrinsic images (reflectance and illumination images), and estimate view-dependent scene geometries using multi-view stereo. We call the resulting representation an intrinsic lumigraph. In the same way that the lumigraph uses geometry to permit more accurate view interpolation, the intrinsic lumigraph uses both geometry and intrinsic images to allow high-quality interpolation at different views and lighting conditions. Joint use of geometry and intrinsic images is effective in the computation of shadow masks for shadow prediction at new lighting conditions. We illustrate our approach with images of real scenes.
29231099
A new circuit optimization technique for high performance CMOS circuits
A novel transistor sizing technique with a concise problem formulation and rigorous optimization scheme is described. A circuit optimization technique for high-performance CMOS circuits is presented for proper balance of chip speed and area. The timing specification is accommodated as a design constraint, and reliability issues in the charge sharing and noise margin, which have been neglected in previous optimization tools, are also embedded into the design constraints. The optimization scheme used in this approach does not require derivatives, and therefore, can be used for a broad class of continuous cost functions. Special attention is given to the most effective use of silicon area based on the sensitivity of the delay time with respect to the transistor size. Excessively large transistor sizes are avoided by using the resource redistribution scheme. This timing allocation scheme allows the computation time to be linearly proportional to the number of gates. >
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
8573619
NMOS energy recovery logic
In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-clock. We have designed an 8-bit CLA and inverter chain using 0.6 /spl mu/m CMOS technology and verified that NERL saves energy over ECRL by 2 to 3 times.