42768359
Hardware-Accelerated Real-Time Rendering for 3D Sumi-e Painting
This paper presents a method for real-time 3D Sumi-e rendering using normal graphics hardware. Sumi-e is one of the traditional oriental painting styles. Most research on Sumi-e paintings has focused on 2D or 2.5D Sumi-e brushwork simulation. On these systems, complicated user's hand drawing is required to generate the image of Sumi-e effects, and it can render the 2D or 2.5D Sumi-e images only. We present an automated rendering system for 3D image of Sumi-e painting. It uses 3D common object as an input data and does not need any additional input of user brushwork. Especially for the real-time rendering, hardware-accelerated algorithm for Sumi-e rendering is newly suggested in our system. It is designed with efficiency for customer level graphics hardware. The results of this paper show that the features of traditional Sumi-e painting are successfully modeled and that 3D Sumi-e painting is rendered in real-time effectively.
6889249
Discrete differential error metric for surface simplification
In this paper we propose a new discrete differential error metric for surface simplification. Many surface simplification algorithms have been developed in order to produce rapidly high quality approximations of polygonal models, and the quadric error metric based on the distance error is the most popular and successful error metric so far Even though such distance based error metrics give visually pleasing results with a reasonably fast speed, it is hard to measure an accurate geometric error on a highly curved and thin region since the error measured by the distance metric on such a region is usually small and causes a loss of visually important features. To overcome such a drawback, we define a new error metric based on the theory of local differential geometry in such a way that the first and the second order discrete differentials approximated locally on a discrete polygonal surface are integrated into the usual distance error metric. The benefits of our error metric are preservation of sharp feature regions after a drastic simplification, small geometric errors, and fast computation comparable to the existing methods.
9179095
fmp and fmp2rsm: eclipse plug-ins for modeling features using model templates
Feature-based model templates have been proposed as a technique for modeling software product lines. We describe a set of tools supporting the technique, namely a feature model editor and feature configurator, and a model-template editor, processor, and verifier.
44446781
One-dimensional simplex search
Abstract We present a one-dimensional simplex search algorithm. We show that it converges to an optimum of any unimodal function and can be made to perform like the well known Golden Section search. We point out why our search would be preferable over other search algorithms when used as a subroutine in multidimensional search.
12552933
TTS without Revocation Capability Secure Against CCA2
A traitor tracing scheme (TTS) deters traitors from giving away their secret keys to decrypt the transmitted data by enabling the system manager to trace at least one of the traitors who participated in the construction of a pirate decoder after confiscating it. In an asymmetric scheme, the system manager is also under suspicion, so the system manager must convince a judge of the implication of the traitors. Recently, Kiayias and Yung proposed an asymmetric public key traitor tracing scheme [13]. However, their scheme does not provide CCA2 security even if a single user is a traitor. That is, their scheme is secure against adaptive chosen ciphertext (CCA2) attack only when there is no traitor. In this paper, we first introduce the security notion against CCA2 attack in a traitor tracing scheme with no revocation capability. This notion is somewhat different from the traditional security notion against CCA2 attack in a two-party encryption scheme [5]. To the best of our knowledge, no security notion against CCA2 attack in a traitor tracing scheme with no revocation capability has been presented. In addition, we modify the Kiayias and Yung’s scheme to achieve security against CCA2 attack under the decision Diffie-Hellman assumption and the collision-resistant hash function assumption.
12329362
Fault Attacks for CRT Based RSA: New Attacks, New Results, and New Countermeasures
Nowadays RSA using Chinese Remainder Theorem (CRT) is widely used in practical applications. However there is a very powerful attack against it with a fault injection during one of its exponentiations. Many countermeasures were proposed but almost all of them are proven to be insecure. In 2005, two new countermeasures were proposed. However they still have a weakness. The final signature is stored in a memory after CRT combination and there is an error-check routine just after CRT combination. Therefore, if an attacker can do a double-fault attack that gives the first fault during one of the exponentiation and the other to skip the error-checking routine, then he can succeed in breaking RSA. In this paper, we show this can be done with the concrete result employing a glitch attack and propose a simple and almost cost-free method to defeat it.
36481442
An Efficient Revocation Scheme for Stateless Receivers
A revocation scheme for stateless receivers enables the center to deliver information securely to the legitimate users over a public channel, where the receivers do not update their state from session to session. In this paper, we propose an efficient revocation scheme for stateless receivers. Our scheme uses a logical hierarchical key tree. Among previously proposed revocation schemes for stateless receivers, the SD scheme [10] is very efficient with respect to message length and Asano’s schemes [1] are very efficient with respect to key storage. Using a binary key tree, our scheme has the same message length as the SD scheme and requires the storage of log n keys, whereas the SD scheme requires the storage of \(\frac{1}{2}\log ^{2} n + \frac{1}{2}\log n + 1\) keys. Using an a-ary key tree, our scheme has the same key storage as Asano’s method 2 and requires a message length of at most 2r–1, whereas Asano’s schemes require a message length of at most \(r(\frac{\log\frac{n}{r}}{\log a} +1)\). Therefore, our scheme is more efficient than the SD scheme and Asano’s schemes.