39505715
Iterative Abstraction using SAT-based BMC with Proof Analysis
8665183
Dynamic detection and removal of inactive clauses in SAT with application in image computation
In this paper, we present a new technique for the efficient dynamic detection and removal of inactive clauses, i.e. clauses that do not affect the solutions of interest of a Boolean satisfiability (SAT) problem. The algorithm is based on the extraction of gate connectivity information during generation of the Boolean formula from the circuit, and its use in the inner loop of a branch-and-bound SAT algorithm. The motivation for this optimization is to exploit the circuit structure information, which can be used to find unobservable gates at circuit outputs under dynamic conditions. It has the potential to speed up all applications of SAT in which the SAT formula is derived from a logic circuit. In particular, we find that it has considerable impact on an image computation algorithm based on SAT. We present practical results for benchmark circuits which show that the use of this optimization consistently improves the performance for reachability analysis, in some cases enabling the prototype tool to reach more states than otherwise possible.
6311626
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-of-the-art SAT solvers like Chaff on important problem domains in VLSI CAD. We observe that in circuit oriented applications like ATPG and verification, different software engineering techniques are required for the portions of the formula corresponding to learnt clauses compared to the original formula. We demonstrate that by employing the same innovations as in advanced CNF-based SAT solvers, but in a hybrid approach where these two portions of the formula are represented differently and processed separately, it is possible to obtain the consistently highest performing SAT solver for circuit oriented problem domains. We also present controlled experiments to highlight where these gains come from. Once it is established that the hybrid approach is faster, it becomes possible to apply low overhead circuit-based heuristics that would be unavailable in the CNF domain for greater speedup.
46604085
Assertion-based verification turns the corner
The "formal verification method: Getting around the Brick Wall" panel at the 2002Design Automation Conference highlighted the industrial emergence of assertion-based verification and the need to go beyond current methods. Moderator David Dill initiated a discussion on the three brick walls to formal verifcation methods: handling high computational complexity, formulating properties to check, and characterizing the set of legal inputs to the design underverification. The panelists addressed moving to higher abstraction levels and assertion-based.verification as two strategies to solve these problems.
11387042
Predicate learning and selective theory deduction for a difference logic solver
Design and verification of systems at the register-transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an arbitrary Boolean combination of propositional variables and difference predicates and therefore provides an appropriate abstraction. In this paper, we present several new optimization techniques for efficiently deciding difference logic formulas. We use the lazy approach by combining a DPLL Boolean SAT procedure with a dedicated graph-based theory solver, which adds transitivity constraints among difference predicates on a "need-to" basis. Our new optimization techniques include flexible theory constraint propagation, selective theory deduction, and dynamic predicate learning. We have implemented these techniques in our lazy solver. We demonstrate the effectiveness of the proposed techniques on public benchmarks through a set of controlled experiments
15353920
Beyond safety: customized SAT-based model checking
Model checking of safety properties has taken a significant lead over nonsafety properties in recent years. To bridge the gap, we propose dedicated SAT-based model checking algorithms for properties beyond safety. Previous bounded model checking (BMC) approaches have relied on either converting such properties to safety checking, or finding proofs by deriving termination criteria using loop-free path analysis. Instead, our approach uses a customized SAT-based formulation for bounded model checking of nonsafety properties, and determines the completeness bounds for liveness using unbounded SAT-based analysis. Our main contributions are: 1) Customized property translations for LTL formulas for BMC, with novel features that utilize partitioning, learning, and incremental formulation. Customized translations not only improve the BMC performance significantly in comparison to standard monolithic LTL translations, but also allow efficient derivation and use of completeness bounds. Though we discuss the translation schemas for liveness, they can be easily extended to handle other LTL properties as well. 2) Customized formulations for determining completeness bounds for liveness using SAT-based unbounded model checking (UMC) rather than using loop-free path analysis. These formulations comprise greatest fixed-point and least fixed-point computations to efficiently handle nested properties using SAT-based quantification approaches. We show the effectiveness of our overall approach for checking liveness on public benchmarks and several industry designs.
5098045
XML-based information mediation with MIX
The MIX mediator system, MIX<italic>m</italic>, is developed as part of the MIX Project at the San Diego Supercomputer Center, and the University of California, San Diego.<supscrpt>1</supscrpt> MIX<italic>m</italic> uses XML as the common model for data exchange. Mediator views are expressed in XMAS (<italic>XML Matching And Structuring Language</italic>), a declarative XML query language. To facilitate user-friendly query formulation and for optimization purposes, MIX<italic>m</italic> employs XML DTDs as a structural description (in effect, a “schema”) of the exchanged data. The novel features of the system include:<list><item>Data exchange and integration solely relies on XML, i.e., instance and schema information is represented by XML documents and XML DTDs, respectively. XML queries are denoted in XMAS, which builds upon ideas of languages like XML-QL, MSL, Yat, and UnQL. Additionally, XMAS features powerful grouping and order constructs for generating new integrated XML “objects” from existing ones.
</item><item>The graphical user interface BBQ (<italic>Blended Browsing and Querying</italic>) is driven by the mediator view DTD and integrates browsing and querying of XML data. Complex queries can be constructed in an intuitive way, resembling QBE. Due to the nested nature of XML data and DTDs, BBQ provides graphical means to specify the nesting and grouping of query results.
</item><item>Query evaluation can be demand-driven, i.e., by the user's navigation into the mediated view.
</item></list>
155165
Multivariate Integration on Hypercubic and Mesh Networks
Abstract We analyze a class of adaptive algorithms for integration over N-dimensional hyper-rectangular or simplical regions, on distributed systems. An adaptive algorithm attempts to achieve the requested accuracy by refining the subdivision of the integration region, thus allowing for a concentration of subdivisions near singularities. At the subdivision of a region, the error behaves according to a prescribed model, relating the error of the parent region to that of its children. The analysis can also be applied to problems in other areas, as long as the task selection is based on a priority function which behaves according to a suitable model. Using an efficient management of the subregions, we show that an O (p/ log p) speedup can be achieved on a p-processor hypercubic network, such as shuffle exchange, butterfly and hypercube. Furthermore, a speedup of O ( p ) can be achieved on a p × p mesh network. We also show that our algorithms compare favorably with well-known dynamic load balancing strategies.
12034549
On embedding ternary trees into Boolean hypercubes
It is pointed out that the problem of efficiently embedding a k-ary tree into hypercube with k>or=3 has largely remained unsolved, even though optimal embeddings (i.e. embeddings achieving minimum delta , lambda , and in ) of complete and incomplete binary trees into hypercubes have been known for some time. Thus, in their quest for designing efficient embeddings of k-ary trees into hypercube for arbitrary k, the authors present some preliminary results that give efficient embeddings for the situations when k=3, 2/sup p/, 3/sup p/, 2/sup p/*3/sup q/ and p, q>0. The embedding of complete ternary trees and the embedding of complete k-ary trees are considered.<<ETX>>
28954888
Modeling shape and topology of 3D images of biological specimens
This paper presents an efficient way of representing the geometry and topology of 3D images of biological specimens derived from electron microscopy. A vector quantization algorithm is used in order to select a reduced set of interior points that best approximates the probability density function of the original volumetric data. Object's geometry and topology are obtained from the point set by the use of the alpha shapes theory.
195611449
Scheduling tasks in multiprocessor systems using evolutionary strategies
Scheduling tasks in multiprocessor systems is a difficult problem. The paper describes a method based upon evolutionary strategies (using genetic algorithms) to aid in finding good task assignments. The technique is illustrated by scheduling a digital signal processing algorithm on a two processor distributed system.<<ETX>>