11125013
A self-stabilizing algorithm for coloring planar graphs
SummaryThis paper describes an algorithm for coloring the nodes of a planar graph with no more than six colors using a self-stabilizing approach. The first part illustrates the coloring algorithm on a directed acyclic version of the given planar graph. The second part describes a selfstabilizing algorithm for generating the directed acyclic version of the planar graph, and combines the two algorithms into one.
34174199
Selfish Stabilization
11369250
Self-optimizing Peer-to-Peer Networks with Selfish Processes
Request patterns in peer-to-peer networks are not uniform, and the cost of communication depends on the traffic flows among peers. This paper illustrates how processes in an overlay network can use the information about traffic flow pattern and spontaneously adjust the topology to minimize their communication costs. Four different self-optimization protocols are presented. The selfish protocols allow peers to modify their routing tables to suit their individual needs, and are easy to implement, but the improvements are limited. Compared to this, the altruistic protocols that allow peers to adjust the routing tables based on the needs of other processes, promise a better performance. Since selfish peers may not comply, a penalty mechanism is proposed to discourage selfishness.
62100403
Scalable self-stabilization
The paper presents a method by which an asynchronous non-reactive distributed system can stabilize from a k-faulty configuration in a time that is a monotonically increasing function of k and independent of the size of the system. In the proposed methodology processes first measure the size of the faulty regions, and then use this information to schedule actions in such a way that the faulty regions progressively shrink, until they completely disappear. When k contiguous processes fail, the stabilization time is O(k/sup 3/). Otherwise, for small values of k, the stabilization time can be exponential in k, but it has an upper bound of O(n/sup 3/). The added space complexity per process is O(/spl delta/ log/sub 2/n), where /spl delta/ is the maximum degree of a node.
435881
Self-Adaptation in Sensor Networks via Code Mutation
22054365
Study of a Simulated Stream Machine for Dataflow Computation
Abstract In this paper, a stream-based dataflow architecture is proposed, and its simulation model, which has helped to evaluate the effectiveness of the proposed architectural concept, is discussed. The machine integrates the conventional Von Neumann type of control flow subsystem with a dataflow processing element of token storage type. The control flow unit tackles the dynamic nature of the stream structure including input/output whereas the dataflow unit does the computation part in an applicative style. A pipelined version of the stream machine is also discussed. The effectiveness of the machine is studied by running a few example programs in the simulated machine. The machine is expected to be useful in real time signal processing applications.
1283500
GaMa: an evolutionary algorithmic approach for the design of mesh-based radio access networks
Wireless mesh based access networks are destined to play a pivotal role in next generation broadband systems. With the proliferation of mesh networks, a key issue for network designers is the design of an optimal mesh topology which minimizes cost while maintaining carrier-class features. In this paper, we formulate the design of an optimal mesh, taking network deployment cost, topological properties and carrier-grade reliability into account. Next, we present a genetic algorithm based algorithm (GaMa) for mesh topology design. We show that GaMa is capable of determining a generic mesh topology with carrier-class network features. The performance of the algorithm is compared with existing mesh topologies and gives improved results without the constraints of maintaining a regular topology
748684
Detection probabilities of interconnect breaks: an analysis
An interconnect break is a break that occurs in the interconnect wiring, resulting in logic gate inputs being disconnected from the drivers and causing the wire to float. Interconnect breaks are the most common types of breaks in modern CMOS integrated circuits, so testing and detecting these breaks has become very important. This paper proposes a model by which standard tests for stuck-at-faults can be used to detect interconnect breaks in a circuit. This paper presents a worst-case analysis of the detection of these breaks and calculate the minimum number of test vectors required to detect breaks with a specified confidence level, using n-detection principles. To enhance the understanding of the breaks in the circuit, we present a statistical model based on the length distribution of the wires surrounding the floating wire where the break occurs. From the model we compute the detection probabilities of such breaks and show that the worst case of detection is when the bias voltage is the same as the logic threshold voltage.
15460911
Polyhedral sampling for multiattribute preference elicitation
A basic requirement for running multiattribute auctions is knowledge of the utility function of the buyer that trades off nonprice attributes against price. We present and study an approach that elicits this preference structure based on a markovian polyhedral sampling scheme called the "Hit-and-Run" algorithm. An advantage of this technique is its relative simplicity - it relies only on matrix algebra as opposed to the use of nonlinear optimization techniques by other methods in the literature. Computational results suggest that this method is fast and accurate.
6555367
Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits
The approach proposed in this paper reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory ECC. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting code. The non-linear power optimization problem is solved using two methods, genetic algorithms and simulated annealing. Both the methods are applied to two SEC-DED codes: standard Hamming codes and odd-column-weight Hsiao codes. Experiments on actual memory traces of Spec and MediaBench benchmarks indicate that considering power along with area and delay when selecting the parity check matrix can result in power reductions of up to 27% for Hsiao codes and up to 41% for Hamming codes. Experiments are also performed to motivate the choice of parameters of the non-linear optimization algorithms, using sensitivity analysis of the low-power solutions to the choice of the different parameters of each algorithm.
1136530
A graph-theoretic approach for studying the convergence of fractal encoding algorithm
In this paper, we present a graph-theoretic interpretation of convergence of fractal encoding based on partial iterated function system (PIFS). First we have considered a special circumstance, where no spatial contraction has been allowed in the encoding process. The concept leads to the development of a linear time fast decoding algorithm from the compressed image. This concept is extended for the general scheme of fractal compression allowing spatial contraction (on averaging) from larger domains to smaller ranges. A linear time fast decoding algorithm is also proposed in this situation, which produces a decoded image very close to the result obtained by an ordinary iterative decompression algorithm.