11417595
Distributed embedded systems for low power: a case study
Summary form only given. A multiple-processor system can potentially achieve higher energy savings than a single processor, because the reduced workload on each processor creates new opportunities for dynamic voltage scaling (DVS). However, as the cost of communication starts to match or surpass that of computation, many new challenges arise in making DVS effective in a distributed system under communication-intensive workload. We discuss implementation issues for supporting DVS on distributed embedded processors. We implemented and evaluated four distributed schemes: (1) DVS during I/O, (2) partitioning, (3) power-failure recovery, and (4) node rotation. We validated the results on a distributed embedded system with the Itsy pocket computers connected by serial links. Our experiments confirmed that a distributed system can create new DVS opportunities and achieve further energy savings. However, a surprising result was that aggregate energy savings do not translate directly into a longer battery life. In fact, the best partitioning scheme, which distributed the workload onto two nodes and enabled the most power-efficient CPU speeds at 30-50%, resulted in only 15% improvement in battery lifetime. Of the four techniques evaluated, node rotation showed the most measurable improvement to battery lifetime at 45% by balancing the discharge rates among the nodes.
1037858
Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources
In this paper we propose a novel scheduling framework for a dynamic real-time environment that experiences power consumption constraints. This framework is capable of dynamically adjusting the voltage/ speed of the system, such that no task in the system misses its deadline and the total energy savings of the system are maximized. 
 
Each task in the system consumes a certain amount of energy, which depends on a speed chosen for execution. The process of selecting speeds for execution while maximizing the energy savings of the system requires the exploration of a large number of combinations, which is too time consuming to be computed on-line. Thus, we propose an integrated heuristic methodology which executes an optimization procedure and an approximate greedy algorithm in a low computation time. This scheme allows the scheduler to handle power-aware real-time tasks with low cost while maximizing the use of the available resources and without jeopardizing the temporal constraints of the system. Simulation results show that our heuristic methodology achieves a performance with near-optimal results.
29539267
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning
7025134
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We formulate a multi-dimensional optimization problem by modeling communication dependencies between processors and their timing budgets. This enables engineers to systematically solve the problem of optimal speed selection for global energy reduction. We demonstrate the effectiveness of our speed selection approach with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.
6396851
Multiagent diffusion and distributed optimization
Distributed problem solving by a multiagent system represents a promising approach to solving complex computational problems. However, many multiagent systems require certain degree of planning, coordination and negotiation to achieve the given goal. This paper presents a multiagent framework for tackling global optimization tasks inspired by diffusion in nature. The framework is designed for situations where agent communication must be kept to a minimal. Hence, complicated coordination and negotiation is not possible. Distributed agents in this framework share the common goal of finding the global optimal solution. They cooperate to achieve this common goal by sharing and updating a common belief that captures their estimation of the whereabouts of the optimal solution. To facilitate this, agents are naturally organized in families with a parent and its offsprings as members. This paper also presents an algorithm called Evolutionary Diffusion Optimization, which is implemented base on the proposed agent framework. Experimental results on some benchmark problems are presented together with performance comparison with a simulated annealing algorithm.
15418886
Progressive Principal Component Analysis
Principal Component Analysis (PCA) is a feature extraction approach directly based on a whole vector pattern and acquires a set of projections that can realize the best reconstruction for an original data in the mean squared error sense. In this paper, the progressive PCA (PrPCA) is proposed, which could progressively extract features from a set of given data with large dimensionality and the extracted features are subsequently applied to pattern recognition. Experiments on the FERET database show its face recognition performance is better than those based on both E(PC)2A and FLDA.
14714835
A Method of Spatial Reasoning Based on Qualitative Trigonometry
Abstract Due to the lack of exact quantitative information or the difficulty associated with obtaining or processing such information, qualitative spatial knowledge representation and reasoning often become an essential means for solving spatial constraint problems as found in science and engineering. This paper presents a computational approach to representing and reasoning about spatial constraints in two-dimensional Euclidean space, where the a priori spatial information is not precisely expressed in quantitative terms. The spatial quantities considered in this work are qualitative distances and qualitative orientation angles. Here, we explicitly define the semantics of these quantities and thereafter formulate a representation of qualitative trigonometry (QTRIG). The resulting QTRIG formalism provides the necessary inference rules for qualitative spatial reasoning. In the paper, we illustrate how the QTRIG relationships can be employed in generating qualitative spatial descriptions in two-dimensional Euclidean geometric problems, and furthermore, how the derived qualitative spatial descriptions can be used to guide a simulated-annealing-based exact quantitative value assignment. Finally, we discuss an application of the proposed spatial reasoning method to the kinematic constraint analysis in computer-aided pre-parametric mechanism design.
17015441
Dynamic address compression schemes: a performance, energy, and cost study
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this work, we investigate two such schemes and determine their optimal parameters that result in the highest area/cost reductions and least performance penalty for various address buses (both on- and off-chip) in current systems. For addresses compressed with these schemes, we study energy reduction of buses in current and future nanometer technology nodes. Our study uses the cycle-accurate simulator for the Alpha 21264 processor called sim-alpha for performance estimation and accurate interconnect models considering inter-wire capacitances for bus energy estimation. Results show that using address compression results in only small performance overheads (less than 1% for compressing a 38-bit bus to 14 bits) and reduce bus energy dissipation by as much as 13% when applied to on-chip buses in current technologies.
1755728
An evolutionary autonomous agents approach to image feature extraction
This paper presents a new approach to image feature extraction which utilizes evolutionary autonomous agents. Image features are often mathematically defined in terms of the gray-level intensity at image pixels. The optimality of image feature extraction is to find all the feature pixels from the image. In the proposed approach, the autonomous agents, being distributed computational entities, operate directly in the 2-D lattice of a digital image and exhibit a number of reactive behaviors. To effectively locate the feature pixels, individual agents sense the local stimuli from their image environment by means of evaluating the gray-level intensity of locally connected pixels, and accordingly activate their behaviors. The behavioral repository of the agents consists of: 1) feature-marking at local pixels and self-reproduction of offspring agents in the neighboring regions if the local stimuli are found to satisfy feature conditions, 2) diffusion to adjacent image regions if the feature conditions are not held, or 3) death if the agents exceed their life span. As part of the behavior evolution, the directions in which the agents self-reproduce and/or diffuse are inherited from the directions of their selected high-fitness parents. Here the fitness of a parent agent is defined according to the steps that the agent takes to locate an image feature pixel.