2974807
Address Register Assignment for Reducing Code Size
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55&percnt). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).
525351
Memory Space Conscious Loop Iteration Duplication for Reliable Execution
Soft errors, a form of transient errors that cause bit flips in memory and other hardware components, are a growing concern for embedded systems as technology scales down. While hardware-based approaches to detect/correct soft errors are important, software-based techniques can be much more flexible. One simple software-based strategy would be full duplication of computations and data, and comparing the results of the corresponding original and duplicate computations. However, while the performance overhead of this strategy can be hidden during execution if there are idle hardware resources, the memory demand increase due to data duplication can be dramatic, particularly for array-based applications that process large amounts of data. 
 
Focusing on array-based embedded computing, this paper presents a memory space conscious loop iteration duplication approach that can reduce memory requirements of full duplication (of array data), without decreasing the level of reliability the latter provides. Our “in-place duplication” approach reuses the memory locations from the same array to store the duplicates of the elements of a given array. Consequently, the memory overhead brought by the duplicates can be reduced. Further, we extend this approach to incorporate “global duplication”, which reuses memory locations from other arrays to store duplicates of the elements of a given array. This paper also discusses how our approach operates under a memory size constraint. The experimental results from our implementation show that the proposed approach is successful in reducing memory requirements of the full duplication scheme for twelve array-based applications.
8725655
Optimizing address code generation for array-intensive DSP applications
The application code size is a critical design factor for many embedded systems. Unfortunately, most available compilers optimize primarily for speed of execution rather than code density. As a result, the compiler-generated code can be much larger than necessary. In particular, in the DSP domain, the past research found that optimizing address code generation can be very important since address code can account for over 50% of all program bits. This paper presents a compiler-directed scheme to minimize the number of instructions to be generated to manipulate address registers found in DSP architectures. As opposed to most of the prior techniques that attempt to reduce the number of such instructions through careful address register assignment, this paper proposes modifying loop access patterns in array-intensive signal processing applications. In addition, it demonstrates how the proposed scheme can cooperate with a data layout optimizer for increasing its benefits further. We also discuss how optimizations that target effective address code generation can conflict with data locality-enhancing transformations. We evaluate the proposed approach using twelve array-intensive embedded applications. Our experimental results indicate that the proposed approach not only leads to significant reductions in code size but also outperforms prior efforts on reducing code size of array-intensive DSP applications.
37185470
An ILP-Based Approach to Locality Optimization
One of the most important factors that determine performance of data-intensive applications is data locality. A program with high data locality makes better use of fast, on-chip memories and can avoid large main memory latencies. Although previous compiler research investigated numerous techniques for enhancing locality, we lack of formal techniques, against which the existing heuristics can be compared. Motivated by this observation, this paper presents a fresh look at locality optimization based on integer linear programming (ILP). We formulate the conditions for data locality, and present a system of constraints whose solution gives optimal computation re-ordering and data-to-memory assignment under our objective function and cost model. Our experimental results using three data-intensive applications clearly indicate that the ILP-based approach generates very good results and outperforms a previously proposed heuristic solution to locality.
17483991
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors
Compilers designed for current embedded systems must be capable of addressing multiple constraints such as low power, high performance, small memory footprint and form factor, and high reliability at the same time. In particular, optimizing for one constraint should be performed carefully, considering its impact on other constraints. Recent trends indicate that transient errors are becoming increasingly important in embedded systems. Focusing on an embedded chip multiprocessor and array-intensive applications, this paper demonstrates how reliability against transient errors can be improved without impacting execution time by utilizing idle processors for duplicating some of the computations of the active processors. It also shows how a balance between power savings and reliability improvement can be struck using a metric called the energy-delay-fallibility product. Our experimental results indicate that the "percentage of duplicated computations" is a useful high-level metric for studying the tradeoffs among performance, power, and reliability
2166475
Temperature-sensitive loop parallelization for chip multiprocessors
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9/spl deg/C (4.3/spl deg/C) when averaged over all the applications tested, incurring small performance/power penalties.
16806816
Dependency management in distributed settings
Applications in a computation and communication saturated pervasive-computing environment have to adapt their behaviors according the context of the user and the physical space. These "context-aware" applications typically obtain high-level situational understanding by aggregating one or more outputs of distributed sensors. To reduce the complexity of developing and deploying these adaptive applications, we designed and implemented a flexible software infrastructure, Solar, for large-scale context fusion (Chen et al., 2004). Solar consists of a set of functionally equivalent nodes, named Planets, which peer together to form a service overlay. A sensor connects to a Planet to register a name with Solar's naming service and publish a stream of events, while an application connects to a Planet to subscribe to one or more sensor outputs by querying Solar's name space. In addition, applications may inject data-fusion operators into the Solar to reduce the computation and communication costs on the mobile devices. In this paper we present our approach to address the dependency management issues in Solar.
5559036
Dynamic compilation for energy adaptation
While previous compiler research indicates that significant improvements in energy efficiency may be possible if properly optimized code is used, the energy constraints under which a given application code should be optimized may not always be available at compile-time. More importantly, these constraints may change dynamically during the course of execution. In this work, we present a dynamic recompilation/linking framework using which the energy behavior of a given application can be optimized while the application is being executed. Our preliminary experiments indicate that large energy gains are possible through dynamic code recompilation/linking at the expense of a relatively small increase in execution time.
39660968
A special k-coloring for a connected k-chromatic graph
For each positive integer k we consider the smallest positive integer f(k) (dependent only on k) such that the following holds: Each connected graph G with chromatic number ?(G) = k can be properly vertex colored by k colors so that for each pair of vertices xo and xp in any color class there exist vertices x1, x2, ?, xp-1 of the same class with dist(xi, xi+1) ? f(k) for each i, 0 ? i ? p ? 1. Thus, the graph is k-colorable with the vertices of each color class placed throughout the graph so that no subset of the class is at a distance > f(k) from the remainder of the class.We prove that f(k) < 12k when the order of the graph is ? k(k ? 2) + 1.
41567017
Gender Differences in Vancouver Secondary Students
This paper presents results from a survey of Vancouver secondary school students on their interests and perceived abilities in a range of subjects, the factors they felt would influence their career choices, and a number of issues related to computer use and perceptions of computer professionals. Females indicated substantially lower interest and perceived ability than males in three subjects, namely computer science, engineering and physics. Females also reported spending less time on most forms of computer activities at school and at home, and gave lower estimates of their computer skills. The survey also revealed that both male and female students have little knowledge of the skills and personality characteristics needed for success in information technology careers. These findings may help explain the low participation of women in information technology areas in university and the work force.
316842
Cycles in 4-connected planar graphs
Let G be a 4-connected planar graph on n vertices. Previous results show that G contains a cycle of length k for each k ∈ {n, n - 1,n - 2, n - 3} with k ≥ 3. These results are proved using the "Tutte path" technique, and this technique alone cannot be used to obtain further results in this direction. One approach to obtain further results is to combine Tutte paths and contractible edges. In this paper, we demonstrate this approach by showing that G also has a cycle of length k for each k ∈ {n - 4, n - 5, n - 6} with k ≥ 3. This work was partially motivated by an old conjecture of Malkevitch.