2580676
Adaptive Distributed Dynamic Channel Allocation for Wireless Networks
Channel allocation schemes in a mobile computing (wireless) environment can be either static or dynamic. Static allocation offers negligible channel acquisition time and zero message complexity and works well at a low system load; the performance steadily decreases as system load increases since many calls are dropped. In the case of even temporary hot spots many calls may be dropped by a heavily loaded switching station even when there are enough idle channels in the interference region of that station. On the other hand, dynamic schemes provide better utilization of the channels at higher loads albeit at the cost of higher channel acquisition time and some additional control messages. Our purpose in the present paper is to propose a combined channel allocation scheme so that each switching station can tune to its own load independent of other stations in its interference region; the objective is to minimize the call drop rate and at the same time maintain a minimum average channel acquisition time and minimum control message complexity.
794427
UpdateSearch: A New Dynamic Channel Allocation Scheme for Mobile Networks That Can Adjust to System Loads
Distributed dynamic channel allocation techniques are an integral part of distributed mobile computing systems where nodes communicate among themselves via wireless radio channels. The channel allocation schemes can be broadly categorized as search based or update based. Search based techniques have low messaging complexity and are suited for high system load and low request rates. On the other hand update based schemes have higher messaging complexity but are more suitable for low system load and high request rates. This paper presents a combined scheme, called UpdateSearch, which provides the advantages of both types of schemes. UpdateSearch is parameterized by the number of channel classes k, 1≤k≤n, where n is the total number of channels in the system. The parameter k can be adjusted to control the number of concurrent searches and degree of contention between cells competing for channels in the system. For k=1 and k=n the scheme respectively behaves as basic search and basic update scheme [2]. A simple analytical model is used to compare the performance of UpdateSearch for various values of k with the basic update and search techniques in terms of channel allocation time and number of simultaneous channel selections allowed in the system under different system loading conditions.
15929474
Optimal offline and online registration techniques for location management with overlapping registration areas
Personal communication services (PCS) standards such as the IS-41 and the GSM use a location management scheme, which is based on registration areas (RA). Overlapping of registration areas has been proposed to reduce the overhead of location updates in such systems. Overlapping provides multiple choices for the selection of a registration area, a feature that does not appear in environments of nonoverlapping RAs. In this paper, we demonstrate how the choice of a registration area affects the number of subsequent registrations and define the problem of optimal choice based on minimization of subsequent registrations. We study two versions of the problem: 1) the deterministic (or offline) version, in which the entire trajectory of the mobile unit is known a priori, and 2) the stochastic (or online) version, in which the trajectory of the mobile unit is not known a priori, but the system has the knowledge of the mobility pattern of the mobile. The mobility pattern is modeled as a random walk across coverage area. In the deterministic case, the method presented computes an optimal solution to the registration problem. In the stochastic case, we present a method that determines the registration that minimizes the expected number of registrations by looking ahead in the probable future paths of the mobile unit. The algorithm's time complexity has exponential dependence on the length of the look-ahead. The cost of search is independent of the choice, therefore the algorithm does not increase the search cost. We also consider an alternative cost model for the stochastic case and propose a preemptive and a nonpreemptive approach each of which incurs different numbers of hard and soft registration operations. Simulation results show a reduction of 25-30 percent in number of registrations over a random-choice scheme. This can be translated to 5-20 percent effective location management load reduction for most cases, subject to the call-to-mobility ratio (CMR) of a mobile unit and search-cost-to-update-cost ratio (CCR) in the network.
13275430
Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions
In this paper, we present a framework for synthesizing I/O efficient out-of-core programs for block recursive algorithms, such as the fast Fourier transform (FFT) and block matrix transposition algorithms. Our framework uses an algebraic representation which is based on tensor products and other matrix operations. The programs are optimized for the striped Vitter and Shriver's two-level memory model in which data can be distributed using various cyclic(B) distributions in contrast to the normally used physical track distribution cyclic(B/sub d/), where B/sub d/ is the physical disk block size. We first introduce tensor bases to capture the semantics of block-cyclic data distributions of out-of-core data and also data access patterns to out-of-core data. We then present program generation techniques for tensor products and matrix transposition. We accurately represent the number of parallel I/O operations required for the synthesized programs for tensor products and matrix transposition as a function of tensor bases and data distributions. We introduce an algorithm to determine the data distribution which optimizes the performance of the synthesized programs. Further, we formalize the procedure of synthesizing efficient out-of-core programs for tensor product formulas with various block-cyclic distributions as a dynamic programming problem. We demonstrate the effectiveness of our approach through several examples. We show that the choice of an appropriate data distribution can reduce the number of passes to access out-of-core data by as large as eight times for a tensor product and the dynamic programming approach can largely reduce the number of passes to access out-of-core data for the overall tensor product formulas.
16361691
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection.
6948566
Process variations and their impact on circuit operation
The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using data obtained from a 0.8 /spl mu/m CMOS process. The impact of these variations and correlations on circuit operation is illustrated. Examples show that circuit delay can increase from the mean by about 100% due to crosstalk effects aggravated by process variations. Case studies emphasize the need for a tighter coupling between fabrication and circuit design and the need for new design corners based on process information.
13972401
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing
Pseudo-exhaustive testing involves applying all possible input patterns to individual output cones of a circuit. Circuits with output cones driven by a large number of inputs often need to be partitioned to reduce the test application time. In this paper, we present an efficient heuristic partitioning procedure of polynomial complexity. Experiments on combinational benchmark circuits validate the efficiency and quality of our approach.
12025861
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault coverage for circuits by exercising greater control over flip-flop clocks in the test mode. In the test mode, the flip-flops are partitioned into different clock-groups. The flip-flops in each clock group can be either clocked or not clocked, independent of the flip-flops in the other groups. This exibility is used to enhance the number of different (v/sub 1/, v/sub 2/) test pairs that can be applied to the state inputs of the circuit thereby increasing coverage of delay faults. Experimental data on benchmark circuits shows that high fault coverage can be obtained by using only two clock groups in most circuits. The proposed clock grouping methodology can be applied to non-scan circuits as well. In fact, it can provide a DFT solution for high speed data path circuits where the performance penalties of conventional DFT techniques are unacceptable.
14782550
Algorithms for selecting cutters in multi-part milling problems
This paper describes geometric algorithms for automatically selecting an optimal sequence of cutters for machining a set of 2.5-D parts. In milling operations, cutter size affects the machining time significantly. Meanwhile, if the batch size is small, it is also important to shorten the time spent on loading tools into the tool magazine and establishing z-length compensation values. Therefore, in small-batch manufacturing, if we can select a set of milling tools that will produce good machining time on more than one type of parts, then several unnecessary machine-tool reconfiguration operations can be eliminated. In selecting milling cutters we consider both the tool loading time and the machining time and generate solutions that allow us to minimize the total machining time. In this paper we first present algorithms for finding the area that can be cut by a given cutter. Then we describe a graph search formulation for the tool selection problem. Finally, the optimal sequence of cutters is selected by using Dijkstra's shortest path planning algorithm.