15489348
A Gradient Based Weighted Averaging Method for Estimation of Fingerprint Orientation Fields
Estimation of orientation fields is an essential module in a fingerprint recognition system. Conventional gradient based approaches are popular but very sensitive to noise. In this paper, we propose a new implementation that is more resistant to noise. Our basic idea is to conduct redundant estimation over four overlapping neighborhoods for each target block. Following this idea, we devise a weighted averaging scheme operated on the base blocks directly. Thus, each block (including the target one) in the overlapping neighborhoods has different impact on estimation of the dominant orientation fields. Our preliminary experiment results suggest that the proposed weighted averaging algorithm is more robust against noise in comparison with other gradient based methods.
6719974
Intrusion Detection Based on Data Mining
56583323
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are mostly based on edge triggered flip-flops. In this paper, we demonstrate the advantages of using level sensitive latches in terms of both latency and area cost. The input-output timing coupling and the strict short path constraint for latches demand additional design elaborations compared with flip-flops. New approaches are proposed in this work to solve these difficulties so that the advantages of latches can be fully utilized. In particular, a deferred delay padding technique is developed to correct short path violations with the minimal extra cost. These techniques are integrated with a dynamic programming based concurrent synchronous element and repeater insertion framework. Experimental results confirm the advantages of using latches as well as effectiveness of our algorithms.
11856531
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures
Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement.
14468769
Exploring Wakeup-Free Instruction Scheduling
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free issue queue designs is critically based on their success in predicting the issue latency of an instruction accurately. Consequently, the goal of this paper is to explore the predictability of instruction issue latency under different design constraints and to identify the impediments to performance in such wakeup-free architectures. Our results indicate that structural problems in promoting instructions to the head of the instruction queue from where they are issued in wakeup-free architectures, the limited number of candidate instructions that can be considered for instruction issue, and the resource conflicts due to non-availability of issue ports all have a significant impact in degrading the performance of broadcast free architectures. Based on these observation, we explore an architecture that attempts to overcome the structural limitations by employing traditional selection logic and by using pre-check logic to reduce the impact of resource conflicts while still employing a wakeup-free strategy based on predicted instruction issue latencies. Finally, we improve this technique by limiting the selection logic to a small segment of the issue queue.
41764873
Supporting provision and access of educational visual resources on the web
4069319
Attribute Reduction Based on Granular Computing
Attribute reduction is a very important issue in data mining and machine learning. Granular computing is a new kind of soft computing theory. A novel method for encoding granules using bitmap technique is proposed in this paper. A new attribute reduction method based on granular computing is also developed with this encoding method. It is proved to be efficient.