12850641
Fault-oriented Test Generation for Multicast Routing Protocol Design
We present a new algorithm for automatic test generation for multicast routing. Our algorithm processes a finite state machine (FSM) model of the protocol and uses a mix of forward and backward search techniques to generate the tests. The output tests include a set of topologies, protocol events and network failures, that lead to violation of protocol correctness and behavioral requirements. We target protocol robustness in specific, and do not attempt to verify other properties in this paper. We apply our method to a multicast routing protocol; PIM-DM, and investigate its behavior in the presence of selective packet loss on LANs and router crashes. Our study unveils several robustness violations in PIM-DM, for which we suggest fixes with the aid of the presented algorithm.
16013811
A comprehensive fault macromodel for opamps
In this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. With the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. Test generation and fault classification are addressed for stand-alone opamps. A high fault coverage is achieved by a proposed testing strategy. Transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. Based on the macromodels for parametric faults, faults simulation is performed for an active filter. We found many parametric faults in the active filter cannot be detected by traditional functional testing. A DFT scheme alone with a current testing strategy to improve fault coverage is proposed.
19051554
BIST test pattern generators for stuck-open and delay testing
Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs.<<ETX>>
30665466
ATPG for Heat Dissipation Minimization During Test Application
A automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds, Three new cost functions, namely transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.
206766191
Accurate and efficient static timing analysis with crosstalk
We have developed an accurate and efficient methodology to perform static timing analysis (STA) in combinational logic blocks in the presence of multiple crosstalk-induced noise effects. The crosstalk model used is more accurate because it considers skew, input transition times, and driver strengths. This crosstalk model is enhanced to handle timing ranges for performing STA. The methodology also uses more accurate delay models for gates. The presence of one or more coupling capacitances can create cyclic timing dependencies, even in an otherwise acyclic circuit. We have developed an approach to partition the circuit into minimal timing-iterative subcircuits (TISs) that encapsulate the cyclic timing dependencies. When used in conjunction with our levelization procedure, iterative timing analysis is confined within individual TISs. We have demonstrated that the maximum arrival time values computed by the proposed STA using integrated delay models are much closer to detailed circuit simulation results than an STA that uses the 3C/sub c/ delay model.
2431223
Switch-level delay test
Gate-level models are usually used to generate tests for circuits containing non-primitive CMOS gates. It is shown that tests generated using these models and classical conditions for robust path delay testing can fail to detect delay faults in such circuits. A new delay-independent, switch-level delay test methodology, called /spl tau/-robust testing, is proposed that defines new entities called targets and proposes conditions to generate tests for each target. It is proven that, under the assumed delay model, a circuit that passes a test set containing a /spl tau/-robust test for every target is guaranteed to operate correctly at the desired speed. The effectiveness of the proposed methodology is demonstrated by (a) illustrating the difference between the delays excited by classical robust and /spl tau/-robust tests via circuit simulation, and (b) generation of /spl tau/-robust tests for benchmark circuits and comparison of /spl tau/-robust coverage of classical robust and /spl tau/-robust test sets.
7271224
Speculation techniques for high level synthesis of control intensive designs
The quality of synthesis results for most high level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. In this paper, we explore the effectiveness of various types of code motions, such as moving operations across conditionals, out of conditionals (speculation) and into conditionals (reverse speculation), and how they can be effectively directed by heuristics so as to lead to improved synthesis results in terms of fewer execution cycles and fewer number of states in the finite state machine controller. We also study the effects of the code motions on the area and latency of the final synthesized netlist. Based on speculative code motions, we present a novel way to perform early condition execution that leads to significant improvements in highly control-intensive designs. Overall, reductions of up to 38 \% in execution cycles are obtained with all the code motions enabled.
12219775
Geometric algorithms for containment analysis of rotational parts
Abstract This paper describes a system and underlying algorithms to perform geometric containment analysis to determine if a newly designed rotational part can be manufactured from a part in an existing database of rotational parts. Only material removal of the database part is considered in order to obtain the newly designed part from the database part. The system uses a three-step algorithm to test for containment. The first step analyzes feasibility of containment using bounding cylinders. If the bounding cylinder of the query part is bigger than the part in the database, then the database part cannot contain the query part and it is eliminated from consideration. The second step analyzes feasibility of containment by ignoring off-axis features. Any part that fails to satisfy containment at this stage is eliminated from consideration. The third step analyzes the remaining parts from the database for feasibility of containment by including the off-axis features. Finally, the system rank-orders all the database parts that can contain the query part based on their volume differences with the query part. The system described in this paper can be used by designers and process planners to find an existing part that can be used as a stock to manufacture a newly designed part. This capability is expected to significantly reduce proliferation of parts, to improve manufacturing responsiveness, and to reduce the cost of new products.
16692732
Versioned Hypermedia can improve software document management
This research was supported by the U. S. Department of Defense and by NSF CAREER award CCR-9734102. The Software Concordance project is addressing the software document management problem by providing a fine-grained version control model for software documents and their relationships using hypermedia versioning. A set of tools needed to maintain, visualize and analyze software documents is being constructed. This short paper presents research issues, initial results and a scheme for using hypermedia versioning and time stamps to automate detection of possible semantic non-conformance among software artifacts.
794427
UpdateSearch: A New Dynamic Channel Allocation Scheme for Mobile Networks That Can Adjust to System Loads
Distributed dynamic channel allocation techniques are an integral part of distributed mobile computing systems where nodes communicate among themselves via wireless radio channels. The channel allocation schemes can be broadly categorized as search based or update based. Search based techniques have low messaging complexity and are suited for high system load and low request rates. On the other hand update based schemes have higher messaging complexity but are more suitable for low system load and high request rates. This paper presents a combined scheme, called UpdateSearch, which provides the advantages of both types of schemes. UpdateSearch is parameterized by the number of channel classes k, 1≤k≤n, where n is the total number of channels in the system. The parameter k can be adjusted to control the number of concurrent searches and degree of contention between cells competing for channels in the system. For k=1 and k=n the scheme respectively behaves as basic search and basic update scheme [2]. A simple analytical model is used to compare the performance of UpdateSearch for various values of k with the basic update and search techniques in terms of channel allocation time and number of simultaneous channel selections allowed in the system under different system loading conditions.
8368503
Synthesis of testable RTL designs
With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to "learn" to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.