299633
Power reduction in pipelines
The reduction of power consumption for a system level pipeline is addressed in this paper. The pipeline is composed of several stages. Each stage has several behaviours. Different behaviours have differing execution times. The speed of the pipeline is only affected by the behaviours on the critical path of the slowest stages. Other behaviours can be slowed down to decrease the power consumed in the system. We propose a multi-voltage supply scheme, in which differing behaviours are supplied with differing voltages. The formulas for computing the supply voltage of each behaviour and minimal power consumption are derived in this paper. The results of computer experiment show that up to 80% hardware power can be saved with this scheme.
2705722
Unrolling loops with indeterminate loop counts in system level pipelines
This paper describes the unrolling of loops with indeterminate loop counts in system level pipelines. Two methods are discussed in this paper. The first method is the varied latency method, where the input is blocked until the pipeline is clear. This variation in the input arrival time gives rise to the name. In this method the output will be in the same order as the input. The second method, called the fixed latency method, allows for the input arrival time to remain unchanged. The loops with loop count in excess of the number of unrolled loops will have to be stored, until a suitable gap in the system becomes available. Analysis of the both methods is given, which shows that the fixed latency method is significantly faster but needs reordering of tasks and memory to store tasks.
1856693
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instruction encoding schemes for multi-pipe Application Specific Instruction-Set Processors (ASIPs). Forwarding is a popular technique to reduce data hazards in the pipeline to improve performance and is applied in almost all modern processor designs; but it is very area expensive. Instruction encoding schemes have a direct impact on code size; an efficient encoding method can lead to a small instruction width, and hence reducing the code size. We propose application specific techniques to reduce forwarding networks and instruction widths for ASIPs with multiple pipelines. By these design techniques, it is possible to reduce area, code size, and even power consumption (due to reduced area), without costing any performance. Our experiments, on a set of benchmarks using the proposed customization approaches show that, on average, there are 27% savings on area, 30% on leakage power, 16.7% on code size, and at the same time, performance even improves by 4% because of the reduced clock period.
7995704
Dual-pipeline heterogeneous ASIP design
We demonstrate the feasibility of a dual pipeline application specific instruction set processor. We take a C program and create a target instruction set by compiling to a basic instruction set from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL descriptions to construct a dual pipeline processor. Our results show that in comparison to the single pipeline application specific instruction set processor, the performance improves by 27.6% and switching activity reduces by 6.1% for a number of benchmarks. These improvements come at the cost of increased area which for benchmarks considered is 16.7% on average.
29819645
Support for relaxed currency and consistency constraints in MTCache
1460421
A New Data-driven Approach for Multimedia Presentation Planning
A number of Multimedia Presentation Systems have been built for technical documentation, traffic management systems, educational software and other applications. However, these systems use handwritten presentation planning operators, which limits their flexibility. In this paper we describe a new data-driven approach for multimedia presentation planning. We present algorithms for acquiring presentation plan operators from Web pages, and for using these operators to generate multimedia presentations. We also show how to use machine learning to adapt multimedia presentation planning to human presentation preferences.
40185955
Improving Multimedia Delivery Performance for Digital Library Applications
Nowadays an educational digital library usually contains instructional materials such as class lectures, seminar presentations, and various training materials. These materials accompany video and audio media. In this case, multimedia streaming and delivery techniques are concerned in the construction of a novel multimedia digital library. In this paper, we focus on multimedia streaming techniques in digital library applications. To achieve scalability and deliver high quality streams, we present the multimedia proxy caching scheme between the server and client path, and a prototype design and implementation of a proxy caching system is proposed. By validate our implementation, the experimental results show that our proxy system can contribute to improve streaming media quality, reduce network transferring latency and decrease streaming service response time.
6968558
Relaxed currency and consistency: how to say "good enough" in SQL
Despite the widespread and growing use of asynchronous copies to improve scalability, performance and availability, this practice still lacks a firm semantic foundation. Applications are written with some understanding of which queries can use data that is not entirely current and which copies are "good enough"; however, there are neither explicit requirements nor guarantees. We propose to make this knowledge available to the DBMS through explicit currency and consistency (C&C) constraints in queries and develop techniques so the DBMS can guarantee that the constraints are satisfied. In this paper we describe our model for expressing C&C constraints, define their semantics, and propose SQL syntax. We explain how C&C constraints are enforced in MTCache, our prototype mid-tier database cache, including how constraints and replica update policies are elegantly integrated into the cost-based query optimizer. Consistency constraints are enforced at compile time while currency constraints are enforced at run time by dynamic plans that check the currency of each local replica before use and select sub-plans accordingly. This approach makes optimal use of the cache DBMS while at the same time guaranteeing that applications always get data that is "good enough" for their purpose.