37317818
Practice and Experience of an Embedded Processor Core Modeling
This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations).
404376
Power-aware deterministic block allocation for low-power way-selective cache structure
This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of a conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss.
52850595
LOD Canny Edge Based Boundary Edge Selection for Human Body Tracking
We propose a simple method for tracking a nonparameterized subject contour in a single video stream with a moving camera and changing background. Our method is based on level-of-detail (LOD) Canny edge maps and graph-based routing operations on the LOD maps. LOD Canny edge maps are generated by changing scale parameters for a given image. Simple (strong) Canny edge map has the smallest number of edge pixels while the most detailed Canny edge map, Wcanny N , has the biggest number of edge pixels. We start our basic tracking using strong Canny edges generated from large image intensity gradients of an input image, called Scanny edges to reduce side-effects because of irrelevant edges. Starting from Scanny edges, we get more edge pixels ranging from simple Canny edge maps until the most detailed Canny edge maps. LOD Canny edge pixels become nodes in routing, and LOD values of adjacent edge pixels determine routing costs between the nodes. We find a best route to follow Canny edge pixels favoring stronger Canny edge pixels. Our accurate tracking is based on reducing effects from irrelevant edges by selecting the stronger edge pixels, thereby relying on the current frame edge pixel as much as possible contrary to other approaches of always combining the previous contour. Our experimental results show that this tracking approach is robust enough to handle a complex-textured scene.
14990532
Weaving Aspects into Real-Time Operating System Design Using Object-Oriented Model Transformation
Despite of the proliferation of object-oriented and component technology, their application to real-time operating systems (RTOS) has been limited since most design concerns in RTOSes crosscut software components and these are critical to deliver required performance and functionality. Aspect-Oriented Programming (AOP) is a very effective means to solve the crosscutting problem. However, we have observed the following limitations of the current AOP framework: (1) the current text-based AOP languages cannot clearly show how aspects are weaved together, (2) their granularity is too coarse to capture all aspects in an RTOS, (3) it is difficult to control the weaving process, since aspect weavers are usually hard-coded. In this paper, we propose a new AOP framework that provides (1) a graphical aspect programming environment that visualizes aspects, crosscutting classes, and method structures, (2) a new aspect model that supports a sub-method level granularity where an aspect is defined as a set of classes, and (3) an aspect weaving process specified by an object-oriented meta-model transformation. Since our aspect-oriented programming framework improves the expressiveness of the crosscutting concerns of RTOSes and automates aspect weaver generation, it can enhance RTOS customization.
16813459
Scenario-based multitasking for real-time object-oriented models
Abstract Contemporary embedded systems quite often employ extremely complicated software consisting of a number of interrelated components, and this has made object-oriented design methodologies widely used in practice. To implement an object-oriented model in given target hardware, it is imperative to derive a set of tasks from the designed objects. This process of determining tasks and the events they handle greatly influences the real-time performance of the resultant system including response times and real-time guarantees. However, the innate discrepancies between objects and tasks make this exceedingly difficult, and many developers are forced to find their task sets through trial and error. In this paper, we propose Scenario-based Implementation Synthesis Architecture (SISA), an architecture consisting of a method for deriving a task set from a given object-oriented model and the development tools and run-time system architecture to support the method. A system developed with SISA guarantees the optimal response time for each event while deriving the smallest possible number of tasks. We have fully implemented SISA by extending the RoseRT development tool and applied it to an existing industrial PBX (private branch exchange) system. The experimental results show that SISA outperforms the best known conventional techniques by reducing maximum response times an average of 30.3%.
15933972
A logical specification for usage control
Recently presented usage control (UCON) has been considered as the next generation access control model with distinguishing properties of decision continuity and attribute mutability. Ausage control decision is determined by combining authorizations, obligations, and conditions, presented as UCONABC core models by Park and Sandhu. Based on these core aspects, we develop afirst-order logic specification of UCON with Lamport's temporallogic of actions (TLA). The building blocks of this model include:(1) a sequence of states expressed by attributes of subjects, objects, and the system, (2) state predicates on subject andobject attributes, (3) pre-defined authorization actions performed by the security system and subjects, (4) obligation actions, and(5) condition predicates on system attributes. For a UCON model we define a set of temporal logic formulas that hold as usage control policies. We show the flexibility and expressive capability of this logic model by specifying the new features and core models of UCON.
11119047
Component-abnormality detection and immunization for survivable systems in large distributed environments