1879174
LEAPS: A Location Estimation and Action Prediction System in a Wireless LAN Environment
Location estimation and user behavior recognition are research issues that go hand in hand. In the past, these two issues have been investigated separately. In this paper, we present an integrated framework called LEAPS (location estimation and action prediction), jointly developed by Hong Kong University of Science and Technology, and the Institute of Computing, Shanghai, of the Chinese Academy of Sciences that combines two areas of interest, namely, location estimation and plan recognition, in a coherent whole. Under this framework, we have been carrying out several investigations, including action and plan recognition from low-level signals and location estimation by intelligently selecting access points (AP). Our two-layered model, including a sensor-level model and an action and goal prediction model, allows for future extensions in more advanced features and services.
9645876
Handling feature interactions in process-planning
Abstract The development of a successful approach to the integration of computer-aided design and computer-aided process-planning will require solutions to several fundamental problems in planning and geometric reasoning. In this article, we consider two such problems, both of which arise from interactions among machinable features. The first problem is that interactions can lead to several alternative interpretations of what the machinable features are. We address this problem by developing an algebra of features. The second problem is that interactions among features can cause problems in optimizing the process plans. For this problem, we have developed a branch-and-bound optimization algorithm with good heuristics to guide the search. This article presents the theory and mathematical framework for both problems and also the details of the implementation and experimental results.
13595177
Multiple-Goal Recognition from Low-Level Signals
Researchers and practitioners from both the artificial intelligence and pervasive computing communities have been paying increasing attention to the task of inferring users' high-level goals from low-level sensor readings. A common assumption made by most approaches is that a user either has a single goal in mind, or achieves several goals sequentially. However, in real-world environments, a user often has multiple goals that are concurrently carried out, and a single action can serve as a common step towards multiple goals. In this paper, we formulate the multiple-goal recognition problem and exemplify it in an indoor environment where an RF-based wireless network is available. We propose a goal-recognition algorithm based on a dynamic model set and show how goal models evolve over time based on pre-defined states. Experiments with real data demonstrate that our method can accurately and efficiently recognize multiple interleaving goals in a user's trace.
11767978
Real-Time Scheduling for Multi-agent Call Center Automation
In a call center, service agents with different capabilities are available for solving incoming customer problems at any time. To supply quick response and better problem solution to customers, it is necessary to schedule customer problems to appropriate service agents efficiently. We developed SANet, a service agent network for call center, which integrates multiple service agents including both software agents and human agents, and employs a broker to schedule customer problems to service agents for better solutions according to their changing capabilities and availability. This paper describes the real-time scheduling method in SANet as well as its architecture. There are two phases in our scheduling method. One is problem-type learning. The broker is trained to learn the problem types and hence can decide the type of incoming problems automatically. The other is the scheduling algorithm based on problem types, capabilities and availability of service agents. We highlight an application in which we apply SANet to a call center problem for a cable-TV company. Finally, we support our claims via experimental results and discuss related works.
5296157
A Novel Scalable Algorithm for Supervised Subspace Learning
Subspace learning approaches aim to discover important statistical distribution on lower dimensions for high dimensional data. Methods such as principal component analysis (PCA) do not make use of the class information, and linear discriminant analysis (LDA) could not be performed efficiently in a scalable way. In this paper, we propose a novel highly scalable supervised subspace learning algorithm called as supervised Kampong measure (SKM). It assigns data points as close as possible to their corresponding class mean, simultaneously assigns data points to be as far as possible from the other class means in the transformed lower dimensional subspace. Theoretical derivation shows that our algorithm is not limited by the number of classes or the singularity problem faced by LDA. Furthermore, our algorithm can be executed in an incremental manner in which learning is done in an online fashion as data streams are received. Experimental results on several datasets, including a very large text data set RCV1, show the outstanding performance of our proposed algorithm on classification problems as compared to PCA, LDA and a popular feature selection approach, information gain (IG).
15099164
A scalable supervised algorithm for dimensionality reduction on streaming data
Algorithms on streaming data have attracted increasing attention in the past decade. Among them, dimensionality reduction algorithms are greatly interesting due to the desirability of real tasks. Principal Component Analysis (PCA) and Linear Discriminant Analysis (LDA) are two of the most widely used dimensionality reduction approaches. However, PCA is not optimal for general classification problems because it is unsupervised and ignores valuable label information for classification. On the other hand, the performance of LDA is degraded when encountering limited available low-dimensional spaces and singularity problem. Recently, Maximum Margin Criterion (MMC) was proposed to overcome the shortcomings of PCA and LDA. Nevertheless, the original MMC algorithm could not satisfy the streaming data model to handle large-scale high-dimensional data set. Thus an effective, efficient and scalable approach is needed. In this paper, we propose a supervised incremental dimensionality reduction algorithm and its extension to infer adaptive low-dimensional spaces by optimizing the maximum margin criterion. Experimental results on a synthetic dataset and real datasets demonstrate the superior performance of our proposed algorithm on streaming data.
13194241
BUCS - a bottom-up cache structure for networked storage servers
This paper introduces a new caching structure to improve server performance by minimizing data traffic over the system bus. The idea is to form a bottom-up caching hierarchy in a networked storage server. The bottom level cache is located on an embedded controller that is a combination of a network interface card (NIC) and a storage host bus adapter (HBA). Storage data coming from or going to a network are cached at this bottom level cache and meta-data related to these data are passed to the host for processing. When cached data exceed the capacity of the bottom level cache, some data are moved to the host RAM that is usually larger than the bottom level cache. This new cache hierarchy is referred to as bottom-up cache structure (BUGS) in contrast to a traditional CPU-centric top-down cache where the top-level cache is the smallest and fastest, and the lower in the hierarchy the larger and slower the cache. Such data caching at the controller level dramatically reduces bus traffic and leads to great performance improvement for networked storages. We have implemented a proof-of-concept prototype using Intel's IQ80310 reference board and Linux network block device. Through performance measurements on the prototype implementation, we observed up to 3 times performance improvement of BUCS over traditional systems in terms of response time and system throughput.
2308836
RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage Systems
Modern high performance disk systems make extensive use of nonvolatile RAM (NVRAM) write caches. A single-copy NVRAM cache creates a single point of failure while a dual-copy NVRAM cache is very expensive because of the high cost of NVRAM. This paper presents a new cache architecture called RAPID-Cache for Redundant, Asymmetrically Parallel, and Inexpensive Disk Cache. A typical RAPID-Cache consists of two redundant write buffers on top of a disk system. One of the buffers is a primary cache made of RAM or NVRAM and the other is a backup cache containing a two-level hierarchy: a small NVRAM buffer on top of a log disk. The small NVRAM buffer combines small write data and writes them into the log disk in large sizes. By exploiting the locality property of I/O accesses and taking advantage of well-known Log-structured File Systems, the backup cache has nearly equivalent write performance as the primary RAM cache. The read performance of the backup cache is not as critical because normal read operations are performed through the primary RAM cache and reads from the backup cache happen only during error recovery periods. The RAPID-Cache presents an asymmetric architecture with a fast-write-fast-read RAM being a primary cache and a fast-write-slow-read NVRAM-disk hierarchy being a backup cache. The asymmetrically parallel architecture and an algorithm that separates actively accessed data from inactive data in the cache virtually eliminate the garbage collection overhead, which are the major problems associated with previous solutions such as Log-structured File Systems and Disk Caching Disk. The asymmetric cache allows cost-effective designs for very large write caches for high-end parallel disk systems that would otherwise have to use dual-copy, costly NVRAM caches. It also makes it possible to implement reliable write caching for low-end disk I/O systems since the RAPID-Cache makes use of inexpensive disks to perform reliable caching. Our analysis and trace-driven simulation results show that the RAPID-Cache has significant reliability/cost advantages over conventional single NVRAM write caches and has great cost advantages over dual-copy NVRAM caches. The RAPID-Cache architecture opens a new dimension for disk system designers to exercise trade-offs among performance, reliability, and cost.
6054148
Hamiltonian cycles in circulant digraphs with two stripes
Abstract The circulant traveling salesman problem ( CTSP ) is the problem of finding a minimum weight Hamiltonian cycle in a weighted graph with circulant distance matrix. The computational complexity of this problem is not known. In fact, even the complexity of deciding Hamiltonicity of the underlying graph is unknown. This paper provides a characterization of Hamiltonian digraphs with circulant distance matrix containing only two nonzero stripes . The corresponding conditions can be checked in polynomial time. Secondly, we show that all Hamiltonian cycles of a circulant 2-digraph are periodic. Based on these two results, a method for enumerating all Hamiltonian cycles in such digraphs is described. Moreover, two simple algorithms are derived for solving the sum and bottleneck versions of CTSP for circulant distance matrices with two nonzero stripes.
8600912
Performance Evaluation of Distributed Web Server Architectures under E-Commerce Workloads
One of the central and key components to make the ECommerce a success is high performance and highly reliable web server architectures. Extensive research has been sparked aiming at improving web server performance. Fundamental to the goal of improving web server performance is a solid understanding of behavior and performance of web servers. However, very little research is found on evaluating web server performance based on realistic workload representing E-Commerce applications which are usually exemplified by a large amount of CGI (Common Gateway Interface), ASP (Active Server Page), or Servlet (Java Server-side interface) calls. This paper presents a performance study under the workload with a mixture of static web page requests, CGI requests, Servlet requests, and database queries. System throughputs and user response times are measured for five different server architectures consisting of PCs that run both a web server program and a database. We observed that performance behaviors of the web server architectures considered under this mixed workload are quite different from that under static page workload and sometimes counter-intuitive. Our performance results suggest that there is a large room for potential performance improvement for web servers.
20437986
Design and analysis of multiple-bus arbiters with different priority schemes
The authors present four multiple-user and multiple-server arbiter designs of multiple-bus multiprocessors. All designs are based on decentralized control, which has the advantage of good reliability and potentially high throughput. The priority protocols considered are fixed priority, rotating priority, round-robin priority, and equal priority. For the first two priority protocols, lookahead techniques are used to speed up the arbitration process. The round-robin protocol is based on the decentralized daisy-chain idea and is operated in an asynchronous fashion. Analytical models are developed for the four different priority protocols to evaluate the performance of the different designs. The analyses are based on a probabilistic model for the synchronous case and simple queuing analysis for the asynchronous system. Numerical results obtained from the proposed model show that the equal priority protocol performs better than the others in the system with a few buses. The performance difference is not significant when the number of buses is relatively large.<<ETX>>