15399936
Compiler-guided leakage optimization for banked scratch-pad memories
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
14081
Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors
Code and data duplication has been identified as one of the important mechanisms for improving reliability. In a chip multiprocessor-based execution environment, while it is possible to hide the overhead of code duplication through parallelism, hiding the memory space overhead incurred by data duplication is more difficult. This paper presents a compiler-directed memory-conscious data duplication scheme that tries to minimize the extra memory space required by duplicate execution. The proposed approach achieves this goal by using the memory locations that hold dead data to store the duplicates of the actively-used data. In this way, instead of using extra memory storage for duplicate elements, we use the existing memory locations to the extent allowed by usage patterns of data. The results collected from our experiments clearly show that the proposed approach saves significant memory space, as compared to a straightforward approach that implements full duplication
525351
Memory Space Conscious Loop Iteration Duplication for Reliable Execution
Soft errors, a form of transient errors that cause bit flips in memory and other hardware components, are a growing concern for embedded systems as technology scales down. While hardware-based approaches to detect/correct soft errors are important, software-based techniques can be much more flexible. One simple software-based strategy would be full duplication of computations and data, and comparing the results of the corresponding original and duplicate computations. However, while the performance overhead of this strategy can be hidden during execution if there are idle hardware resources, the memory demand increase due to data duplication can be dramatic, particularly for array-based applications that process large amounts of data. 
 
Focusing on array-based embedded computing, this paper presents a memory space conscious loop iteration duplication approach that can reduce memory requirements of full duplication (of array data), without decreasing the level of reliability the latter provides. Our “in-place duplication” approach reuses the memory locations from the same array to store the duplicates of the elements of a given array. Consequently, the memory overhead brought by the duplicates can be reduced. Further, we extend this approach to incorporate “global duplication”, which reuses memory locations from other arrays to store duplicates of the elements of a given array. This paper also discusses how our approach operates under a memory size constraint. The experimental results from our implementation show that the proposed approach is successful in reducing memory requirements of the full duplication scheme for twelve array-based applications.
8725655
Optimizing address code generation for array-intensive DSP applications
The application code size is a critical design factor for many embedded systems. Unfortunately, most available compilers optimize primarily for speed of execution rather than code density. As a result, the compiler-generated code can be much larger than necessary. In particular, in the DSP domain, the past research found that optimizing address code generation can be very important since address code can account for over 50% of all program bits. This paper presents a compiler-directed scheme to minimize the number of instructions to be generated to manipulate address registers found in DSP architectures. As opposed to most of the prior techniques that attempt to reduce the number of such instructions through careful address register assignment, this paper proposes modifying loop access patterns in array-intensive signal processing applications. In addition, it demonstrates how the proposed scheme can cooperate with a data layout optimizer for increasing its benefits further. We also discuss how optimizations that target effective address code generation can conflict with data locality-enhancing transformations. We evaluate the proposed approach using twelve array-intensive embedded applications. Our experimental results indicate that the proposed approach not only leads to significant reductions in code size but also outperforms prior efforts on reducing code size of array-intensive DSP applications.
17483991
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors
Compilers designed for current embedded systems must be capable of addressing multiple constraints such as low power, high performance, small memory footprint and form factor, and high reliability at the same time. In particular, optimizing for one constraint should be performed carefully, considering its impact on other constraints. Recent trends indicate that transient errors are becoming increasingly important in embedded systems. Focusing on an embedded chip multiprocessor and array-intensive applications, this paper demonstrates how reliability against transient errors can be improved without impacting execution time by utilizing idle processors for duplicating some of the computations of the active processors. It also shows how a balance between power savings and reliability improvement can be struck using a metric called the energy-delay-fallibility product. Our experimental results indicate that the "percentage of duplicated computations" is a useful high-level metric for studying the tradeoffs among performance, power, and reliability
2974807
Address Register Assignment for Reducing Code Size
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55&percnt). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).
15396672
Maintaining System State Information in a Multiagent Environment for Effective Learning
One fundamental issue in multiagent reinforcement learning is how to deal with the limited local knowledge of an agent in order to achieve effective learning. In this paper, we argue that this issue can be more effectively solved if agents are equipped with a consistent global view. We achieve this by requiring agents to follow an interacting protocol. The properties of the protocol are derived and theoretically analyzed. A distributed protocol that satisfies these properties is presented. The experimental evaluations are conducted for a well-known test-case (i.e., pursuit game) in the context of two learning algorithms. The results show that the protocol is effective and the reinforcement learning algorithms using it perform much better. key words: multiagent system, system state, distributed protocol, token ring
41643555
A Fuzzy Dead Reckoning Algorithm for Distributed Interactive Applications
A fuzzy Dead Reckoning (DR) algorithm for distributed interactive applications is proposed in this paper. Since fixed threshold cannot adequately handle the dynamic relationships between moving entities, some multi-level threshold DR algorithms were proposed in the past few years. In these algorithms the level of threshold is adaptively adjusted based on the distance between entities. The proposed fuzzy DR algorithm is based on multi-level threshold DR algorithm and takes all properties of entity (e.g. position, size and view angle etc.) into consideration when adjusting the level of threshold. This algorithm employs fuzzy correlation degree to measure the relationships between entities and determine the level of threshold for DR algorithm. Fuzzy consistent relation is used to distribute weight for each property. Simulation results indicate that fuzzy DR algorithm can achieve a considerable reduction in the number of state update messages while maintaining adequate accuracy in extrapolation.
30765152
On the Quickest Path Problem
Abstract Let N be an input network and σ be the amount of data to be transmitted. We present an O( mn 2 ) time algorithm that finds all-pairs quickest paths, for a given value of σ, and show that the quickest path between any two nodes for any value of σ can be found in O(log m ) time, provided O( mn 2 ) preprocessing time is spent.
21143930
An I/O Optimal and Scalable Skyline Query Algorithm
Given a set of d-dimensional points, skyline query returns the points that are not dominated by any other point on all dimensions. Currently, BBS (branch-and-bound skyline) is the most efficient skyline processing method over static data in a centralized setting. Although BBS has some desirable features (e.g., I/O optimal and flexibility), it requires large main-memory consumption. In this paper, we present an improved skyline computation algorithm based on best-first nearest neighbor search, called IBBS, which captures the optimal I/O and less memory space (i.e., IBBS visits and stores only those entries that contribute to the final skyline). Its core enables several effective pruning strategies to discard non-qualifying entries. Extensive experimental evaluations show that IBBS outperforms BBS in both scalability and efficiency for most cases, especially in low dimensions.
44397360
Reducing Time Complexities of Semigroup Computations on Mesh-Connected Computers with Multiple Broadcasting