8187290
Model-driven SoC design via executable UML to SystemC
We present a system level description mechanism based on UML-notations from which one can automatically extract SystemC code. Our modelling framework is based on a restricted set of UML diagram types and some standard extensions influenced by the communication infrastructure of SystemC. The system specifications are developed using the UML-compatible tool, Rhapsody (2004). We then translate the internal representation of the design generated by Rhapsody into SystemC code. The extensions we have implemented using the stereotype feature of the Rhapsody tool pull up the communication infrastructure and timing features of SystemC to the UML-level. Consequently, we can describe executable platforms at the UML-level as well as translate UML-based application descriptions to SystemC level.
15634785
The performance model of SilkRoad - a multithreaded DSM system for clusters
Distributed Shared Memory (DSM) is a highly desirable programming model for cluster based computing. Even though a number of software DSMs have been developed with their performance evaluated, few of them have a theoretical performance model. In this paper, we propose and analyze the performance model of the software DSM of SilkRoad,, a multithreaded runtime system for cluster computing. SilkRoad is built on the Cilk system with an extended memory consistency model which we call RC/sub dag/ consistency: Extending Cilk's theoretical performance model, we show that with the RC/sub dag/ consistent DSM, the expected execution.time T/sub P/ of a partially strict multithreaded computation on P processors is O((T/sub 1/(Z, L) + N)/P + /spl mu/HT/sub /spl infin//), where T/sub 1/(Z, L) is the total work of computation, T/sub /spl infin// is the critical path, N is the number of lock acquisitions, /spl mu/ is the service time of a cache miss, and H is the height of memory: Finally, we present experimental evidence that verify the performance model.
18143878
Compiling Parallel Lisp for a Shared Memory Multiprocessor
There is a commonly held idea that although Lisp is a good language for prototyping and software development, it is often too inefcient to be useful in actual implementation. Advances in compiling Lisp have begun to change this notion. However, the situation is less clear in the case of parallel Lisp dialects. In this paper, we report on our experience in implementing a compiler for a parallel Lisp dialect we called BaLinda Lisp for a shared memory multiprocessor. For a class of problems, our compiler was able to achieve performances on Lisp programs that are near, if not equal to, their imperative (C) equivalents. However, on other problems, the situation is less than ideal. We investigate this phenomenum and outline the future challenges in realizing a production strength parallel Lisp compiler.
3457072
Using UML 2.0 for system level design of real time SoC platforms for stream processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing stream modeling languages. To address them we describe a design approach in which specifications are captured in UML 2.0, and automatically translated into SystemC models consisting of simulators and synthesizable code under proper style constraints. As an application case, we explain real time stream processor specifications using new UML 2.0 notations. Then we expound how our translator generates SystemC models and includes additional hardware details. Verifications are made during UML execution as well as assertions in SystemC. The case study demonstrates the feasibility of fast specifications, modifications and generation of real time stream processor designs.
9691799
Targeted Data Prefetching
Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data. The success of any data prefetching scheme depends on three factors: timeliness, accuracy and overhead. In most hardware prefetching mechanism, the focus has been on accuracy – ensuring that the predicted address do turn out to be demanded in a later part of the code. In this paper, we introduce a simple hardware prefetching mechanism that targets delinquent loads, i.e. loads that account for a large proportion of the load misses in an application. Our results show that our prefetch strategy can reduce up to 45% of stall cycles of benchmarks running on a simulated out-of-order superscalar processor with an overhead of 0.0005 prefetch per CPU cycle.
1841047
Design and Implementation of Abstract Machine for Parallel Lisp Compilation
1188802
Smart debugging software architectural design in SDL
Statistical data show that it is much cheaper to fix software bugs at the early design stage than the late stage of the development process where the final system has already been implemented and integrated together. The use of slicing and execution histories as an aid in software debugging is well established for programming languages like C and C++; however, it is rarely applied in the field of software specification for designs. We propose a solution by applying the technology at source code level to debugging software designs represented in a high-level specification and description language such as SDL. More specifically, we extend execution slice-based heuristics from source code-based debugging to the software design specification level. Suspicious locations in an SDL specification are prioritized based on their likelihood of containing faults. Locations with a higher priority should be examined first rather than those with a lower priority as the former are more suspicious than the latter, i.e., more likely to contain the faults. A debugging tool, SmartDSDL, with user-friendly interfaces was developed to support our method. An experiment is reported to demonstrate the feasibility of using our method to effectively debug an architectural design.
1096223
Vascular segmentation in three-dimensional rotational angiography based on maximum intensity projections
Three-dimensional rotational angiography (3D-RA) is a relatively new and promising technique for imaging blood vessels. In this paper, we propose a novel 3D-RA vascular segmentation algorithm, which is fully automatic and very computationally efficient, based on the maximum intensity projections (MIP) of 3D-RA images. Validation results on 13 clinical 3D-RA datasets reveal that, according to the agreement between the segmentation results and the ground truth, our method (a) outperforms both the maximum a posteriori-expectation maximization (MAP-EM)-based method and the MAP-Markov random field (MAP-MRF)-based segmentation method, and (b) works comparably to the optimal global thresholding method. Experimental results also show that our method can successfully segment major vascular structures in 3D-RA and produce a lower false positive rate than that of the MAP-EM-based and MAP-MRF-based methods.
16317533
Multi Criteria Selection of Components Using the Analytic Hierarchy Process
The Analytic Hierarchy Process (AHP) has been successfully used in the past for the selection of components, as presented in case studies in the literature. In this paper, an empirical study using AHP to rank components is presented. The components used in the study are for data compression; each implements one of the Arithmetic Encoding (AREC), Huffman coding (HUFF), Burrows-Wheeler Transform (BWT), Fractal Image Encoding (FRAC), and Embedded Zero-Tree Wavelet Encoder (EZW) algorithms. The ranking is a semi-automated approach that is based on using rigorously collected data for the components' behavior; selection criteria include maximum memory usage, total response time, and security properties (e.g., data integrity). The results provide a clear indication that AHP is appropriate for the task of selecting components when several criteria must be considered. Though the study is limited to select components based on multiple non-functional criteria, the approach can be expanded to include multiple functional criteria.
26802541
Test set size minimization and fault detection effectiveness: A case study in a space application
Abstract An important question in software testing is whether it is reasonable to apply coverage-based criteria as a filter to reduce the size of a test set. An empirical study was conducted using a test set minimization technique to explore the effect of reducing the size of a test set, while keeping block coverage constant, on the fault detection strength of the resulting minimized test set. Two types of test sets were examined. For those with respect to a fixed size, no test case screening was conducted during the generation, whereas for those with respect to a fixed coverage, each subsequent test case had to improve the overall coverage in order to be included. The study reveals that regardless of how a test set is generated, with or without any test case screening, block minimized test sets have a size/effectiveness advantage, in terms of a significant reduction in test set size and with almost the same fault detection effectiveness, over the original non-minimized test sets.
16024151
An adaptable architecture for secure delivery of converged services
We present an approach for secure delivery of multimodal services to end users over heterogeneous converged networks. Our approach leads to an easily adaptable and extensible system architecture, in which system components interact with each other through loosely coupled interfaces based on asynchronous exchange of messages. It also effectively separates service logic from service delivery, through the introduction of a secure broker between the end user devices and the enterprise level application that contains the service logic. This separation also provides additional levels of security at the application level. This paper describes how our approach provides the features mentioned above. We have also validated our approach through the implementation of a prototype system, a description of which is also provided.