5934964
Fuzzy control for guaranteeing absolute delays in Web servers
This paper presents a fuzzy control approach that guarantees absolute delays in Web servers. Previous work has proposed the use of classical PI controllers for delay guarantees. However, a disadvantage of the classical PI controller is that the system model, which is obtained by system identification, mismatches the real system and inevitably degrades the performance of the Web system. In contrast with classical PI controllers, fuzzy controllers are nonlinear and therefore independent of the accurate model of the plant, i.e. the controlled system. Hence, fuzzy controllers seem to be very suitable for Web servers. Our experiments show that fuzzy controllers indeed perform better than PI controllers presented in earlier papers
15949067
Security authentication of 3G-WLAN interworking
With the development of wireless Internet, the interworking of the third generation (3G) wide area wireless networks and wireless local area networks (WLAN) has become a focus of research. 3G systems have their advantages in charging management, roaming, and security facilities, and WLAN systems have the advantages of high bandwidth and low investment cost. Interworking of 3G-WLAN offers characteristics that complement each other perfectly. Several authentication protocols have been proposed to improve security. In this paper, we firstly introduce the architectures of 3G-WLAN interworking and discuss existing problems related to authentication and key agreement procedures. Then, we present two schemes by applying authentication based on EAP-TLS (extensible authentication protocol-transport layer security) and EAP-TTLS (tunneled TLS) into integrated 3G and WLAN to achieve high end-to-end security and authentication for the users. Finally, we conduct a series of performance evaluation on the energy consumption and latency of standard authentication protocols.
3052468
Performance Modeling and Analysis for Resource Scheduling in Data Grids
Data Grids normally deal with large data-intensive problems on geographically distributed resources; yet, most current research on performance evaluation of resource scheduling in Data Grids is based on simulation techniques, which can only consider a limited range of scenarios. In this paper, we propose a formal framework via Stochastic Petri Nets to deal with this problem. Within this framework, we model and analyze the performance of resource scheduling in Data Grids, allowing for a wide variety of job and data scheduling algorithms. As a result of our research, we can investigate more scenarios with multiple input parameters. Moreover, we can evaluate the combined effectiveness of job and data scheduling algorithms, rather than study them separately.
18052662
Probabilistic analysis on mesh network fault tolerance
Mesh networks are among the most important interconnection network topologies for large multicomputer systems. Mesh networks perform poorly in tolerating faults in the view of worst-case analysis. On the other hand, such worst cases occur very rarely in realistic situations. In this paper, we study the fault tolerance of 2-D and 3-D mesh networks under a more realistic model in which each network node has an independent failure probability. We first observe that if the node failure probability is fixed, then the connectivity probability of these mesh networks can be arbitrarily small when the network size is sufficiently large. Thus, it is practically important for multicomputer system manufacture to determine the upper bound for node failure probability when the probability of network connectivity and the network size are given. We develop a novel technique to formally derive lower bounds on the connectivity probability for 2-D and 3-D mesh networks. Our study shows that these mesh networks of practical size can tolerate a large number of faulty nodes thus are reliable enough for multicomputer systems. For example, it is formally proved that as long as the node failure probability is bounded by 0.5%, a 3-D mesh network of up to a million nodes remains connected with a probability larger than 99%.
28815316
Stability analysis of buffer priority scheduling policies using Petri nets
A Petri net approach to determining the conditions for stability of a re-entrant system with buffer priority scheduling policy is described in this paper. The concept of buffer boundedness based on the dynamic behavior of the marking in the system model is emphasized. The method is used to demonstrate the stability of the first buffer first served (FBFS) and the last buffer first served (LBFS) scheduling policies. finally a sufficient condition for instability of systems with a positive feedback loop (PFL) is established, and an example is given.
36427579
Dynamic handoff scheme in differentiated QoS wireless multimedia networks
Handoff is one of the key elements in ensuring quality of service (QoS) in mobile wireless networks. Handoff connections generally have higher priority than new connections. Traditional reservation policies that reserve some channels for handoff connections are not adaptive to traffic load changes. This paper proposes a new Dynamic Guard Channel (DGC) scheme, which (1) combines differentiated QoS service model and priority handoff mechanism; (2) provides fairness for differentiated QoS services; (3) adapts to various traffic loads because it adopts passive feedback mechanism if we assume a stationary distribution for the mean arrival times; (4) does not need to exchange state information among different cells, so it is easy to implement and is simple enough to be used in real world scenarios; (5) utilizes network resource efficiently and puts a bound on each service blocking probability. The simulation results show that the ratios among different QoS service probabilities are guaranteed to predefined values and system utilization is improved.
27000155
Towards a Machine-Independent Solution of Sparse Cholesky Factorization
15658650
A reinforcement neuro-fuzzy combiner for multiobjective control
This paper proposes a neuro-fuzzy combiner (NFC) with reinforcement learning capability for solving multiobjective control problems. The proposed NFC can combine n existing low-level controllers in a hierarchical way to form a multiobjective fuzzy controller. It is assumed that each low-level (fuzzy or nonfuzzy) controller has been well designed to serve a particular objective. The role of the NFC is to fuse the n actions decided by the n low-level controllers and determine a proper action acting on the environment (plant) at each time step. Hence, the NFC can combine low-level controllers and achieve multiple objectives (goals) at once. The NFC acts like a switch that chooses a proper action from the actions of low-level controllers according to the feedback information from the environment. In fact, the NFC is a soft switch; it allows more than one low-level actions to be active with different degrees through fuzzy combination at each time step. An NFC can be designed by the trial-and-error approach if enough a priori knowledge is available, or it can be obtained by supervised learning if precise input/output training data are available. In the more practical cases when there is no instructive teaching information available, the NFC can learn by itself using the proposed reinforcement learning scheme. Adopted with reinforcement learning capability, the NFC can learn to achieve desired multiobjectives simultaneously through the rough reinforcement feedback from the environment, which contains only critic information such as "success (good)" or "failure (bad)" for each desired objective. Computer simulations have been conducted to illustrate the performance and applicability of the proposed architecture and learning scheme.
18172401
SIMPLE Performance Results in ZPL
This paper presents performance results for ZPL programs running on the Kendall Square Research KSR-2 and the Intel Paragon. Because ZPL is a data parallel language based on the Phase Abstractions programming model, these results complement earlier claims that the Phase Abstractions model can lead to portability across MIMD computers. The ZPL language and selected aspects of the compilation strategy are briefly described, and performance results are compared against hand-coded programs.
9269937
A general framework for certifying garbage collectors and their mutators
Garbage-collected languages such as Java and C# are becoming more and more widely used in both high-end software and real-time embedded applications. The correctness of the GC implementation is essential to the reliability and security of a large portion of the world's mission-critical software. Unfortunately, garbage collectors--especially incremental and concurrent ones--are extremely hard to implement correctly. In this paper, we present a new uniform approach to verifying the safety of both a mutator and its garbage collector in Hoare-style logic. We define a formal garbage collector interface general enough to reason about a variety of algorithms while allowing the mutator to ignore implementation-specific details of the collector. Our approach supports collectors that require read and write barriers. We have used our approach to mechanically verify assembly implementations of mark-sweep, copying and incremental copying GCs in Coq, as well as sample mutator programs that can be linked with any of the GCs to produce a fully-verified garbage-collected program. Our work provides a foundation for reasoning about complex mutator-collector interaction and makes an important advance toward building fully certified production-quality GCs.
6353139
Static placement, dynamic issue (SPDI) scheduling for EDGE architectures
Technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density increases the number of execution units on a single chip, and decreasing wire transmission speeds causes long and variable on-chip latencies. These trends severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler instead work cooperatively, called static placement dynamic issue (SPDI). This paper focuses on the static instruction scheduler for SPDI. We identify and explore three issues SPDI schedulers must consider - locality, contention, and depth of speculation. We evaluate a range of SPDI scheduling algorithms executing on an explicit data graph execution (EDGE) architecture. We find that a surprisingly simple one achieves an average of 5.6 instructions-per-cycle (IPC) for SPEC2000 64-wide issue machine, and is within 80% of the performance without on-chip latencies. These results suggest that the compiler is effective at balancing on-chip latency and parallelism, and that the division of responsibilities between the compiler and the architecture is well suited to future systems.