17015441
Dynamic address compression schemes: a performance, energy, and cost study
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this work, we investigate two such schemes and determine their optimal parameters that result in the highest area/cost reductions and least performance penalty for various address buses (both on- and off-chip) in current systems. For addresses compressed with these schemes, we study energy reduction of buses in current and future nanometer technology nodes. Our study uses the cycle-accurate simulator for the Alpha 21264 processor called sim-alpha for performance estimation and accurate interconnect models considering inter-wire capacitances for bus energy estimation. Results show that using address compression results in only small performance overheads (less than 1% for compressing a 38-bit bus to 14 bits) and reduce bus energy dissipation by as much as 13% when applied to on-chip buses in current technologies.
14115714
Energy-efficient compressed address transmission
To realize energy-efficient buses in current nanometer-scale technologies, techniques like compression or encoding that exploit information redundancy have been explored. However, available compression techniques for buses do not always ensure energy-efficient transmission of compressed information. In this work, we present various techniques that can be used with compression schemes for buses to ensure high energy efficiency. Our best scheme, applied to a stream of 38-bit addresses issued in a typical microprocessor, yields about 14.7% energy reduction on the average across a wide range of compressed bus widths ranging and over many SPEC CPU2000 benchmarks. Our proposed techniques especially perform better - up to 28.8% energy reduction is obtained - for narrower bus widths in the range 8-16 bits.
43415133
The performance advantage of applying compression to the memory system
The memory system stores information comprising primarily instructions and data and secondarily address information, such as cache tag fields. It interacts with the processor by supporting related traffic (again comprising addresses, instructions, and data). Continuing exponential growth in processor performance, combined with technology, architecture, and application trends, place enormous demands on the memory system to permit this information storage and exchange at a high-enough performance (i.e., to provide low latency and high bandwidth access to large amounts of information). This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the memory system and evaluates the potential of compression in improving performance of the memory system. Analysis of traces obtained with Sun Microsystems' Shade simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite yield impressive results. Well-designed compression schemes may provide benefits in performance that far outweigh the extra time and logic for compression and decompression. This will be more so in the future since the speed and size of logic (which will be used to perform compression/decompression) are improving and are projected to improve at a much higher rate compared to those of interconnect (which will be used to communicate the information), both on-chip and off-chip.
52848704
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction
Interconnect area and energy dissipation are critical factors in any system designed today. In this work, we present techniques to help reduce area/cost and energy dissipation of address buses with significant temporal redundancy. We describe two encoding techniques for such buses, called pattern adjuster (PA) encoding and dynamic charge/discharge encoding (DCDE), that use simple hardware and no extra bus lines for control signals. Results show that, using PA encoding, self energy reduces by 18-38%, coupling toggle energy by 19-96%, and coupling charge/discharge energy by 14-40%. In addition, with DCDE applied on top of PA, coupling charge/discharge energy reduces by up to 48%. Overall, up to 25% address bus energy savings can be obtained using our techniques compared to the energy dissipation of the original bus, with 26-79% reduction in the number of bus lines. Our techniques use very simple hardware and will have negligible encoding/decoding latencies that are much lower than those of low-power bus encoding schemes.
6152126
QoS-aware dynamic service composition in ambient intelligence environments
Due to the large success of wireless networks and handheld devices, the ambient intelligence (AmI) paradigm is becoming a reality. One of the most challenging objectives to achieve in AmI environments is to enable a user to perform a task by composing on the fly networked services available at a specific time and place. Towards this goal, we propose a solution based on semantic Web services, and we show how service capabilities described as conversations can be integrated to perform a user task that is also described as a conversation, further meeting the QoS requirements of the user task. Experimental results show that the runtime overhead of our algorithm is reasonable, and further, that QoS-awareness improves its performance.
5750170
Bounds on the Gain of Network Coding and Broadcasting in Wireless Networks
Gupta and Kumar established that the per node throughput of ad hoc networks with multi-pair unicast traffic scales (poorly) as lambda(n) = Theta (1 / radic(n log n)) with an increasing number of nodes n. However, Gupta and Kumar did not consider the possibility of network coding and broadcasting in their model, and recent work has suggested that such techniques have the potential to greatly improve network throughput. In [1], we have shown that for the protocol communication model of Gupta and Kumar [2], the multi-unicast throughput of schemes using arbitrary network coding and broadcasting in a two-dimensional random topology also scales as lambda(n) = Theta (1 / radic(n log n))1, thus showing that network coding provides no order difference improvement on throughput. Of course, in practice the constant factor of improvement is important; thus, here we derive bounds for the throughput benefit ratio -the ratio of the throughput of the optimal network coding scheme to the throughput of the optimal non-coding flow scheme. We show that the improvement factor is 1+ Delta / 1+Delta /2for 1D random networks, where Delta > 0 is a parameter of the wireless medium that characterizes the intensity of the interference. We obtain this by giving tight bounds (both upper and lower) on the throughput of the coding and flow schemes. For 2D networks, we obtain an upper bound for the throughput benefit ratio as alpha (n) les 2cDelta radic(pi = 1+Delta/Delta) for large n, wnere cDelta = max {2, radic(Delta2 + 2Delta)}. This is obtained by finding an upper bound for the coding throughput and a lower bound for the flow throughput. We then consider the more general physical communication model as in Gupta and Kumar. We show that the coding scheme throughput in this case is upper bounded by Theta (1/n) for the 1D random network and by Theta(1/radic(n)) for the 2D case. We also show the flow scheme throughput for the ID case can achieve the same order throughput as the coding scheme. Combined with previous work on a 2D lower bound [3], we conclude that the throughput benefit ratio under the physical model is also bounded by a constant; thus, we have shown for both the protocol and physical model that the coding benefit in terms of throughput is a constant factor. Finally, we evaluate the potential coding gain from another important perspective - total energy efficiency - and show that the factor by which the total energy is decreased is upper bounded by 3.
1037858
Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources
In this paper we propose a novel scheduling framework for a dynamic real-time environment that experiences power consumption constraints. This framework is capable of dynamically adjusting the voltage/ speed of the system, such that no task in the system misses its deadline and the total energy savings of the system are maximized. 
 
Each task in the system consumes a certain amount of energy, which depends on a speed chosen for execution. The process of selecting speeds for execution while maximizing the energy savings of the system requires the exploration of a large number of combinations, which is too time consuming to be computed on-line. Thus, we propose an integrated heuristic methodology which executes an optimization procedure and an approximate greedy algorithm in a low computation time. This scheme allows the scheduler to handle power-aware real-time tasks with low cost while maximizing the use of the available resources and without jeopardizing the temporal constraints of the system. Simulation results show that our heuristic methodology achieves a performance with near-optimal results.
15698160
Performance prediction of a parallel simulator
There are at least three major obstacles thwarting widespread adoption of parallel discrete-event simulation: lack of need; lack of tools; and lack of predictability in behavior and performance. The plain truth is that most simulation studies can be adequately done on ordinary serial computers. Parallel simulation tools are products of research efforts, and simply do not stand up to the demands of modern software engineering. The results of 20 years of research in parallel simulation reveal it to be a highly complex endeavour, with performance results very much dependent on implementation details and model characteristics. The Scalable Simulation Framework (SSF) is an effort to address some these concerns. It addresses lack of need in two ways; it provides a modeling API that is attractive both for serial and parallel simulation, with parallel execution requiring no change to the model, and it targets large-scale telecommunication system modeling, an application area that requires the computational capabilities of parallelism. We address the concern over unpredictable behavior. We show how we measured the internal overheads of the Dartmouth implementation of the SSF API (DaSSF), and how those measurements can be used to predict the performance of a given model, using given features of the simulator, without having to run, or even build, the model.
7025134
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We formulate a multi-dimensional optimization problem by modeling communication dependencies between processors and their timing budgets. This enables engineers to systematically solve the problem of optimal speed selection for global energy reduction. We demonstrate the effectiveness of our speed selection approach with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.