43442956
Representation characterizations of chordal bipartite graphs
A bipartite graph is chordal bipartite if it does not contain an induced cycle of length at least six. We give three representation characterizations of chordal bipartite graphs. More precisely, we show that a bipartite graph is chordal bipartite if and only if the complement is the intersection graph of a family of pairwise compatible claws in a weighted hypercircle. (A hypercircle is a graph which consists of internally vertex disjoint paths between two distinguished vertices, and a claw in a hypercircle is a connected subgraph containing exactly one of the two distinguished vertices.) We also introduce two classes of bipartite graphs, both containing interval bigraphs and interval containment bigraphs. They are compatible subtree intersection bigraphs and compatible subtree containment bigraphs. We show that these two classes are identical to the class of chordal bipartite graphs.
31025959
A Note on Spanning Local Tournaments in Locally Semicomplete Digraphs
We prove a result which implies that every k-connected locally semicomplete digraph which is not a semicomplete digraph must contain a k-connected spanning local tournament. This improves an earlier result of Guo and partially answers a question of Jackson and Thomassen.
10675163
Maximal and Minimal Vertex-Critical Graphs of Diameter Two
A graph is vertex-critical if deleting any vertex increases its diameter. We construct, for each??5 except?=6, a vertex-critical graph of diameter two on?vertices with at least 12?2?2?3/2+c1?edges, wherec1is some constant. We show that such a graph contains at most 12?2?(2/2)?3/2+c2?edges, wherec2is some constant. We also construct, for each??5 except?=6, a vertex-critical graph of diameter two on?vertices with at most 12 (5??12) edges. We show that such a graph must contain at least 12 (5??29) edges.
4803217
Pushing the cycles out of multipartite tournaments
Abstract Let D be a digraph and X ⊆ V ( D ). By pushing X we mean reversing each arc of D with exactly one end in X. Klostermeyer proved that it is NP-complete to decide if a given digraph can be made acyclic using the push operation. Here we characterize, in terms of forbidden subdigraphs, the multipartite tournaments which can be made acyclic (resp. ordinary, unidirectional) using the push operation. This implies that the problem of deciding if a given multipartite tournament can be made acyclic (resp. ordinary, unidirectional) using the push operation and, if so, finding a suitable subset of vertices to push, is solvable in polynomial time.
4778324
Pushing vertices in digraphs without long induced cycles
Given a digraph D and a subset X of vertices of D, pushing X in D means reversing the orientation of all arcs with exactly one end in X. We continue the study of deciding whether a digraph can be made acyclic using the push operation, focussing on special classes of well-structured digraphs. It is proved that the problem remains NP-complete even when restricted to the class of bipartite digraphs (i.e., oriented bipartite graphs). We characterize, in terms of two forbidden subdigraphs, the chordal digraphs which can be made acyclic using the push operation, and show that there is no similar characterization for the family of chordal bipartite digraphs. A polynomial algorithm, based on 2-SAT, for solving the problem for a subclass of the chordal bipartite digraphs is given. Finally, a characterization in terms of a finite number of forbidden subdigraphs, of the acyclically pushable bipartite permutation digraphs is given.
14351696
A sufficient condition for a semicomplete multipartite digraph to be Hamiltonian
Abstract A multipartite tournament is an orientation of a complete k -partite graph for some k ⩾ 2. A factor of a digraph D is a collection of vertex disjoint cycles covering all the vertices of D . We show that there is no degree of strong connectivity which together with the existence of a factor will guarantee that a multipartite tournament is Hamiltonian. Our main result is a sufficient condition for a multipartite tournament to be Hamiltonian. We show that this condition is general enough to provide easy proofs of many existing results on paths and cycles in multipartite tournaments. Using this condition, we obtain a best possible lower bound on the length of a longest cycle in any strongly connected multipartite tournament.
28276441
A Programmable BIST Core for Embedded DRAM
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy.
2023739
Joint video scene segmentation and classification based on hidden Markov model
Video classification and segmentation are fundamental steps for efficient accessing, retrieval and browsing of large amounts of video data. We have developed a scene classification scheme using a hidden Markov model (HMM) based classifier. By utilizing the temporal behaviors of different scene classes, the HMM classifier can effectively classify video segments into one of the pre-defined scene classes. In this paper, we describe two approaches for joint video classification and segmentation based on a HMM, which works by searching for the most likely class transition path utilizing the dynamic programming technique.
16721854
Learning from labeled and unlabeled data on a directed graph
We propose a general framework for learning from labeled and unlabeled data on a directed graph in which the structure of the graph including the directionality of the edges is considered. The time complexity of the algorithm derived from this framework is nearly linear due to recently developed numerical techniques. In the absence of labeled instances, this framework can be utilized as a spectral clustering method for directed graphs, which generalizes the spectral clustering approach for undirected graphs. We have applied our framework to real-world web classification problems and obtained encouraging results.
6920930
Data Broadcast on a Multi-System Heterogeneous Overlayed Wireless Network
We propose in this paper a two-phase algorithm, named algorithm layered-cutting, to address the problem of broadcast program generation in a multisystem heterogeneous overlayed wireless network. The experimental results show that algorithm layered-cutting is able to efficiently generate broadcast programs of high quality for a multisystem heterogeneous overlayed wireless network
14811510
Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits
In this paper we present the specification backpropagation technique which enables one to derive the constraint of an internal functional block with respect to a given DC specification for an analog/mixed-signal system. Based on this technique, we implement an efficient fault simulator which reduces the required efforts by (1) removing undetectable faults from the fault list, and (2) performing fault simulation only locally for the fault block. Simulation results on an industrial design show a speedup factor of 7.2 with 98% correct classification of detected and undetected faults as compared with full-chip DC fault simulation.