1744079
Object-based analog VLSI vision circuits
Describes two analog VLSI chips that perform object-based computations. The first chip computes length of various contours in an image and the second chip performs figure-ground separation of a scene.<<ETX>>
34951314
Spike synchronization in a network of silicon integrate-and-fire neurons
Spike-event based computational processing by neuronal networks depends on a variety of spatio-temporal mechanisms that are distributed across neuronal synapses, dendrites, and somata. The overall processing of spatio-temporal patterns of spike requires global temporal coherence between all these processes both within a neuron, and across all neurons of the network. We are evaluating the use of networks of hybrid analog-digital integrate-and-fire neurons, fabricated using VLSI, for studying real-time event-based processing. These hardware networks have the advantages of real-time operation, and inherent global synchronization by their analog implementation. However, one of the technical challenges in the operation of such networks is the unavoidable fabrication related variance between the different neurons of the network. Here we show that despite this variance, an important behavior of neuronal networks, spike synchronization, can be obtained from a simple network of VLSI neurons interconnected by lateral excitation and global inhibition.
6979172
Encoding the Temporal Statistics of Markovian Sequences of Stimuli in Recurrent Neuronal Networks
Encoding, storing, and recalling a temporal sequence of stimuli in a neuronal network can be achieved by creating associations between pairs of stimuli that are contiguous in time. This idea is illustrated by studying the behavior of a neural network model with binary neurons and binary stochastic synapses. The network extracts in an unsupervised manner the temporal statistics of the sequence of input stimuli. When a stimulus triggers the recalling process, the statistics of the output patterns reflects those of the input. If the sequence of stimuli is generated through a Markov process, then the network dynamics faithfully reproduces all the transition probabilities.
1845062
Adaptive Retina with Center-Surround Receptive Field
Both vertebrate and invertebrate retinas are highly efficient in extracting contrast independent of the background intensity over five or more decades. This efficiency has been rendered possible by the adaptation of the DC operating point to the background intensity while maintaining high gain transient responses. The center-surround properties of the retina allows the system to extract information at the edges in the image. This silicon retina models the adaptation properties of the receptors and the antagonistic center-surround properties of the laminar cells of the invertebrate retina and the outer-plexiform layer of the vertebrate retina. We also illustrate the spatio-temporal responses of the silicon retina on moving bars. The chip has 59×64 pixels on a 6.9×6.8mm2 die and it is fabricated in 2 µm n-well technology.
12793172
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 /spl mu/m CMOS technology are in agreement with the analysis.<<ETX>>
18592302
A Winner-Take-All Circuit with Controllable Soft Max Property
I describe a silicon network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths. This output models the normalization property of the wide-field direction-selective cells in the fly visual system. This normalizing property is also useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit with one additional transistor and a voltage reference. Just as in Lazzaro's circuit, the outputs of the excitatory neurons code the neuron with the largest input. The difference here is that multiple winners can be chosen. By varying the voltage reference of the neuron, the network can transition between a soft-max behavior and a hard WTA behavior. I show results from a fabricated chip of 20 neurons in a 1.2 µm CMOS technology.
1399991
Validation of Distributed Real-Time and Embedded System composition in UniFrame
Distributed Real-Time and Embedded (DRE) Systems are widely applied to large scale and mission critical application domains such as avionics systems and medical imaging. Due to the rapid lifecycle and the complexity of design of the systems, there is an urgent demand to manage the development of robust, COTS, and effective software for vendors. The UniFrame project is a unified framework for seamless integration of distributed heterogeneous software components. This paper describes how the UniFrame approach is applicable to DRE software components. Leveraging the Two-Level Grammar (TLG) specification language and the Vienna Development Method (VDM), a formal methodology for developing DRE components and system code generation is developed for UniFrame.
14652555
Adding multi-class routing into the DiffServ architecture
To alleviate the problem of high priority traffic hogging of all the available network capacity and to optimize the network traffic in the DiffServ network, we introduce the multi-class routing (MCR) scheme into the DiffServ architecture. The MCR scheme that builds multiple routing tables in the DiffServ routers forms the MCR DiffServ architecture. In this paper, the MCR DiffServ architecture focuses on the intra-DS domain. Different MCR approaches that include a static approach and dynamic approaches can be used for the MCR DiffServ system. We extend the OSPF protocol in order to build up more than one routing table in each MCR DiffServ system. According to the extensions to OSPF, we have implemented the static MCR approach for the MCR DiffServ system on the basis of the open source Zebra software.
13893049
Pitfalls in the fluid modeling of RTT variations in window-based congestion control
Deterministic delay differential equation models, where the packet traffic is modeled as a fluid, are widely used to study congestion control algorithms in the Internet. In this paper, we point out some pitfalls in such fluid modeling of window flow control algorithms. Specifically, we argue that the modeling assumptions used to capture the variability in the RTT (due to queue length fluctuations) may play a critical role in our ability to design stable algorithms. We study two scenarios to illustrate the dramatic impact of RTT modeling. We first consider TCP-Reno with RED, and show that assuming that the RTT is a constant (when it is actually time-varying) leads to conservative parameter choices, i.e., the system continues to be stable even with variable RTT. On the other hand, for the recently proposed stabilized Vegas, we show the following result: while the network can be stabilized under the constant RTT assumption, there is no choice of parameters that would stabilize the system when the RTT variations are taken into account. Interestingly, such problems do not arise if the congestion-control mechanisms at the end-users are rate-based.
2425320
Scalable data aggregation for dynamic events in sensor networks
Computing and maintaining network structures for efficient data aggregation incurs high overhead for dynamic events where the set of nodes sensing an event changes with time. Moreover, structured approaches are sensitive to the waiting-time which is used by nodes to wait for packets from their children before forwarding the packet to the sink. Although structureless approaches can address these issues, the performance does not scale well with the network size. We propose a semi-structured approach that uses a structureless technique locally followed by Dynamic Forwarding on an implicitly constructed packet forwarding structure to support network scalability. The structure, ToD, is composed of multiple shortest path trees. After performing local aggregation, nodes dynamically decide the forwarding tree based on the location of the sources. The key principle behind ToD is that adjacent nodes in a graph will have low stretch in one of these trees in ToD, thus resulting in early aggregation of packets. Based on simulations on a 2000 nodes network and real experiments on a 105 nodes Mica2-based network, we conclude that efficient aggregation in large scale networks can be achieved by our semi-structured approach.
11824549
An approach to detecting domain errors using formal specification-based testing
Domain testing, a technique for testing software or portions of software dominated by numerical processing, is intended to detect domain errors that usually arise from incorrect implementations of desired domains. This paper describes our recent work aiming to provide support for revealing domain errors using formal specifications. In our approach, formal specifications serve as a means for domain modeling. We describe a strong domain testing strategy that guide testers to select a set of test points so that the potential domain errors can be effectively detected, and apply our approach in two case studies for test cases generation.