36521667
Storage management for persistent complex objects
Abstract The emerging generation of database systems and persistent programming languages presents a new set of requirements for object management systems. In this paper, we first describe these requirements and provide a survey of prior efforts to address these issues. We then present an object model with the descriptive power to satisfy these requirements. Finally, we propose a modular architecture for an object manager which will provide efficient support for the storage, retrieval and modification of persistent complex objects. The object manager hides the internal structural details of objects from its clients. It provides direct support for indexing and does not impose any size restrictions on objects.
2815522
Efficient Filtering of XML Documents for Selective Dissemination of Information
Information Dissemination applications are gaining increasing popularity due to dramatic improvements in communications bandwidth and ubiquity. The sheer volume of data available necessitates the use of selective approaches to dissemination in order to avoid overwhelming users with unnecessaryinformation. Existing mechanisms for selective dissemination typically rely on simple keyword matching or “bag of words” information retrieval techniques. The advent of XML as a standard for information exchangeand the development of query languages for XML data enables the development of more sophisticated filtering mechanisms that take structure information into account. We have developed several index organizations and search algorithms for performing efficient filtering of XML documents for large-scale information dissemination systems. In this paper we describe these techniques and examine their performance across a range of document, workload, and scale scenarios.
1006062
The design of an acquisitional query processor for sensor networks
We discuss the design of an acquisitional query processor for data collection in sensor networks. Acquisitional issues are those that pertain to where, when, and how often data is physically acquired (sampled) and delivered to query processing operators. By focusing on the locations and costs of acquiring data, we are able to significantly reduce power consumption over traditional passive systems that assume the a priori existence of data. We discuss simple extensions to SQL for controlling data acquisition, and show how acquisitional issues influence query optimization, dissemination, and execution. We evaluate these issues in the context of TinyDB, a distributed query processor for smart sensor devices, and show how acquisitional techniques can provide significant reductions in power consumption on our sensor devices.
2567437
Dynamic Query Operator Scheduling for Wide-Area Remote Access
Distributed databases operating over wide-area networks such as the Internet, must deal with the unpredictable nature of the performance of communication. The response times of accessing remote sources can vary widely due to network congestion, link failure, and other problems. In such an unpredictable environment, the traditional iterator-based query execution model performs poorly. We have developed a class of methods, called query scrambling, for dealing explicitly with the problem of unpredictable response times. Query scrambling dynamically modifies query execution plans on-the-fly in reaction to unexpected delays in data access. In this paper we focus on the dynamic scheduling of query operators in the context of query scrambling. We explore various choices for dynamic scheduling and examine, through a detailed simulation, the effects of these choices. Our experimental environment considers pipelined and non-pipelined join processing in a client with multiple remote data sources and delayed or possibly bursty arrivals of data. Our performance results show that scrambling rescheduling is effective in hiding the impact of delays on query response time for a number of different delay scenarios.
7889988
Crash recovery in client-server EXODUS
In this paper, we address the correctness and performance issues that arise when implementing logging and crash recovery in a page-server environment. The issues result from two characteristics of page-server systems: 1) the fact that data is modified and cached in client database buffers that are not accessible by the server, and 2) the performance and cost trade-offs that are inherent in a client-server environment. We describe a recovery system that we have implemented for the client-server version of the EXODUS storage manager. The implementation supports efficient buffer management policies, allows flexibility in the interaction between clients and the server, and reduces the server load by generating log records at clients. We also present a preliminary performance analysis of the implementation.
2033914
Data Staging for On-Demand Broadcast
:A>@<b_DCGAdPBEG>R<:c\A8:Q@L]J.A8<0H(L[MOz:CTL0PBc:zbP[<bc4EGADCG ? >@_DA8EHGbP[HP[CTA>@<::ADCTAD<.HTQRJz:CTL0PBcb_DPBEwHw_DPBbP[zbQRA bP0EqPBc\A>Uc\ADPBCGAdP$c:P]HFP z:CGL.PBc:_8PBEwHP[<P]HGHGCFPB_ HG>@?BA4c:P]HFP c\A8QR>@?BA8CGJ P[QRHGA8CG<kP]HG>@?BA2MSLBCQ@PBCG0A&_Q@>RA8<.H  LB:a:QUP]HT>RL0<bE8`v:ADCTAbP0Evz ADAD<Ew>@B<:>Rk_8P[<.HvyL0CGZ HGL]P[CFc:EOc\A8?BA8QRL0:>R<b$LB<\QR>@<:Az:CTL0P0c:_DP0EKHET_F:Adc\a:QR >@<:P[Q@BLBCT>RHG:E MSLBCEGJ\EKHTADE :ADCTA!P[Q@Q c:P]HFP >RHGADEOPBCGAyCGAdPBc\>@QRJPY?]PB>RQUP[z:Q@A>@<¡HG:AEGADCT?BADCd¢ E6P[>@< ADLBCTJB` :A8EGA£EwHGabc:>RAdE(>@B<bLBCTA HG:Ac:P]HFP2P[<: P[0ADAD<.H>UETEwa:AdEOHTbP]HP[CT>@EGA:A8<HG:A c:P[HTP HTL£z A z:CTL0P0c:_DP0EKH£akEKH&z A L0z\HTPB>R<bA8c MSCGL0¤EGA8_DLB<bcbP[CTJ EwHGLBCFP[0A LBC,CTADL[HTA Q@L\_DP]HT>RL0<bE8`¥<¦HT:>@E4bPBkA8C8V  A§:CTLB L0EGA HG:CTADA_LB:Q@ADA8<0HFP[CTJ ̈EGLBQ@a\HG>@LB<kE HGL EGab_F ̈©Ba[«a ¬­«aD®B ̄±°.®_L0<b_A8CG<kED2§L0: LBCGHGa:<:>UEw HG>U_ ET_F:A8c:a:QR>@<:kVEGADCT?BA8C2_DP0_F:>R<bbVP[<bc bCGADMSAHT_F: >@<:b`&bA8EGAHGA8_Fb<:>@3.a:AdE$A ́\:Q@LB>RH:>@<.HTE$:CTL]? >@c:A8c z J,HG:AET_F:A8c\abQR>@<:,P[Q@BLBCT>RHG:,`$μ¶c:AHTPB>RQ@A8c kA8Cw MSLBCTP[<b_DA AD?]P[Q@abP]HT>RL0< akEw>@<:P[<·¥K ̧o1 a:QRHG>U_DPBEwHw zbP0EwAdc HGAdEKHTzkAdc EG:L]vE$HTbP]HHG:AdEwA4c:P]HFP EwHTPBB>@<: HGAd_F:<:>U3.a:A8Ev_8P[< c\CFP[P]HT>@_8P[Q@QRJA8<:bPB<b_A HT:A$kA8Cw MSLBCTP[<b_DA L[M£P Q@PBCG0AEG_8P[Q@A,LB<\c\ADPB<bcz:CTL0P0c  _DP0EKHvEGJ\EKHTAD,`
15978640
Speculative Computation: Overcoming Communication Delays
Communication latencies and delays are a major source of performance degradation in parallel computing systems. It is important to "mask" these communication delays by overlapping them with useful computation in order to obtain good parallel performance. This article proposes speculative computation as a technique to mask communication latencies in synchronous iterative algorithms. Processors speculate the contents of messages that are not yet received and perform computation based on the speculated values. When the messages are received, they are compared with the speculated values and, if the error is unacceptable, the resulting computation is corrected or recomputed. If the error is small, the speculated value is accepted and the processor has masked the communication delay. The technique, applied to N-body simulations yielded a performance improvement of up to 34%.
61655346
Statistics on Logic Simulation
The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speedups over standard software based logic simulators. Several commercial simulation engines have been produced to satisfy needs in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity by first examining possible sources of speedup in the logic simulation task, examining the sort of data needed in the design of simulation engines, and then presenting such data. The data contained in the paper includes information on subtask times found in standard discrete event simulation algorithms, event intensities, queue length distributions and simultaneous event distributions.
4770738
Parallel Simulated Annealing using Speculative Computation
A parallel simulated annealing algorithm that is problem-independent, maintains the serial decision sequence, and obtains speedup which can exceed log/sub 2/P on P processors is discussed. The algorithm achieves parallelism by using the concurrency technique of speculative computation. Implementation of the parallel algorithm on a hypercube multiprocessor and application to a task assignment problem are described. The simulated annealing solutions are shown to be, on average, 28% better than the solutions produced by a random task assignment algorithm and 2% better than the solutions produced by a heuristic. >
34325813
Timing Control of VLSI Based NlogN and Crossbar Networks
Two basic data flow control methods for circuit switched, pipelined networks of the general nlogn and crossbar (cb) topologies are modelled and their effects on overall data rates achievable are determined. The synchronous method uses a global clock and as network modules grow, clock skew and clock tree charge/discharge times grow resulting in lower data rates. The asynchronous method relies on local request/acknowledge signals to control data movement and hence its performance is less affected by system growth. 12 references.
583321
Performance models for network processor design
To provide a variety of new and advanced communications services, computer networks are required to perform increasingly complex packet processing. This processing typically takes place on network routers and their associated components. An increasingly central component in router design is a chip-multiprocessor (CMP) referred to as "network processor" or NP. In addition to multiple processors, NPs have multiple forms of on-chip memory, various network and off-chip memory interfaces, and other specialized logic components such as CAMs (content addressable memories). The design space for NPs (e.g., number of processors, caches, cache sizes, etc.) is large due to the diverse workload, application requirements, and system characteristics. System design constraints relate to the maximum chip area and the power consumption that are permissible while achieving defined line rates and executing required packet functions. In this paper, an analytic performance model that captures the processing performance, chip area, and power consumption for a prototypical NP is developed and used to provide quantitative insights into system design trade offs. The model, parameterized with a networking application benchmark, provides the basis for the design of a scalable, high-performance network processor and presents insights into how best to configure the numerous design elements associated with NPs