8545280
EnviroStore: A Cooperative Storage System for Disconnected Operation in Sensor Networks
This paper presents a new cooperative storage system for sensor networks geared for disconnected operation (where sensor nodes do not have a connected path to a basestation). The goal of the system is to maximize its data storage capacity by appropriately distributing storage utilization and opportunistically offloading data to external devices when possible. The system is motivated by the observation that a large category of sensor network applications, such as environmental data logging, does not require real-time data access. Such networks generally operate in a disconnected mode. Rather than focusing on multihop routing to a basestation, an important concern becomes (i) to maximize the effective storage capacity of the disconnected sensor network such that it accommodates the most data, and (ii) to take the best advantage of data upload opportunities when they become available to relieve network storage. The storage system described in this paper achieves the above goals, leading to significant improvements in the amount of data collected compared to non-cooperative storage. It is implemented in nesC for TinyOS and evaluated in TOSSIM through various application scenarios.
8295901
Bounded-latency content distribution feasibility and evaluation
This paper investigates the performance of a content distribution network designed to provide bounded content access latency. Content can be divided into multiple classes with different configurable per-class delay bounds. The network uses a simple distributed algorithm to dynamically select subsets of its proxy servers for different classes such that a global per-class delay bound is achieved on content access. The content distribution algorithm is implemented and tested on PlanetLab, a world-wide distributed Internet testbed. Evaluation results demonstrate that, despite Internet delay variability, subsecond delay bounds (of 200-500 ms) can be guaranteed with a very high probability at only a moderate content replication cost. The distribution algorithm achieves a four to fivefold reduction in the number of response-time violations compared to prior content distribution approaches that attempt to minimize average latency. To the authors' knowledge, this paper presents the first wide-area performance evaluation of an algorithm designed to bound maximum content access latency, as opposed to optimizing an average performance metric.
1650647
Load balancing in bounded-latency content distribution
In this paper we present a balanced data replication scheme that provides real-time latency bounds on content retrieval in content distribution networks. Many network applications have ever-increasing requirements on latency sensitive data services. Data replication services have been widely used as an important performance enhancement mechanism to reduce data access latency and throughput. We investigate the problem of provisioning an underlying balanced data replication service to provide a global latency bound on data retrieval in content distribution networks. The solution involves constructing an overlay network based on the given latency bound, and a mechanism to assign content objects to the network nodes so that the workload of all the network nodes is balanced. Our evaluation results drawn from detailed simulations show the efficacy of our load-balancing scheme in meeting the latency bound requirements with high confidence under heavy load
16039010
Design, Implementation and Evaluation of a Real-Time Active Content Distribution Service
The phenomenal growth of the world-wide web has made it the most popular Internet application today. Web caching and content distribution services have been recognized as valuable techniques to mitigate the explosion of web traffic. An increasing fraction of web traffic today is dynamically generated and therefore intrinsically difficult to replicate or cache using present static approaches. Scalable delivery of such active content poses a myriad of challenges, including content replication, update propagation, and consistency management. This paper makes two contributions: it (1) describes a scalable architecture for transparent demand-driven distribution of active content; and (2) presents a system that can provide real-time delay guarantees on content access. Our approach involves migrating the scripts which generate dynamic web traffic, and their data, from the origin servers to active content distribution proxies nearest to the clients. We also present mechanisms on these proxies to enforce real-time delay guarantees for client requests. Our system is implemented and deployed on Planetlab (2004), a real-world distributed Internet testbed. Experimental data show that significant improvements are observed in effective throughput and client response time, and that delay bounds on content access can be guaranteed with a very high probability.
14725341
Towards content distribution networks with latency guarantees
This paper investigates the performance of a content distribution network designed to provide bounded content access latency. Content can be divided into multiple classes with different configurable per-class delay bounds. The network uses a simple distributed algorithm to dynamically select a subset of its proxy servers for different classes such that a global per-class delay bound is achieved on content access. The content distribution algorithm is implemented and tested on PlanetLab, a world-wide distributed Internet testbed. Evaluation results demonstrate that despite Internet delay variability, subsecond delay bounds (of 200-500ms) can be guaranteed with a very high probability at only a moderate content replication cost. The distribution algorithm achieves a 4 to 5 fold reduction in the number of response-time violations compared to prior content distribution approaches that attempt to minimize average latency. This paper presents the first wide-area performance evaluation of an algorithm designed to bound maximum content access latency, as opposed to optimizing an average performance metric.
1236122
Range-free localization and its impact on large scale sensor networks
With the proliferation of location dependent applications in sensor networks, location awareness becomes an essential capability of sensor nodes. Because coarse accuracy is sufficient for most sensor network applications, solutions in range-free localization are being pursued as a cost-effective alternative to more expensive range-based approaches. In this paper, we present APIT, a novel localization algorithm that is range-free. We show that our APIT scheme performs best when an irregular radio pattern and random node placement are considered, and low communication overhead is desired. We compare our work, via extensive simulation, with three state-of-the-art range-free localization schemes to identify the preferable system configurations of each. In addition, we provide insight into the impact of localization accuracy on various location dependent applications and suggestions on improving their performance in the presence of such inaccuracy.
1034949
Character-based Collocation for Mandarin Chinese
This paper describes a characters-based Chinese collocation system and discusses the advantages of it over a traditiolml word-based systcm. Since wordbreaks are not conventionally marked in Chinese text corpora, a character-based collocation system has the dual advantages of avoiding pre-proccssing distortion and directly accessing sub-lexical information. Furthermore, word-based collocational properties can be obtained through an auxiliary modttle of automatic segmentation. corpora as they are, we ",viii be able to access sub-lexical information without additional cost. To take the full advantage of the nature of texts, reliable tools can also be devised to obtain [exical collocation. In this paper, we ,,viii describe the design and implementation e r a Chinese collocational system that does not require the preprocessing of automatic segmentation but is awe to allow both lexical and sub-lexical information be automatically extracted.
1476959
High-level synthesis of distributed logic-memory architectures
With the increasing cost of global communication on-chip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout a chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This work provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the trade-offs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps.We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (upto, 5.31X average of 3.45X) performance improvements over well-optimized conventional designs with small area overheads (upto 19.3%, 15.1% on average).
14432070
Monitoring cycles for fault detection in meshed all-optical networks
Fault detection is critical for all-optical networks (AONs). This paper introduces the concept of monitoring cycle and proposes a fault detection mechanism based on decomposing AONs into a set of cycles (a cycle cover), in which each one is defined as a monitoring cycle. Two cycle-finding algorithms are developed and compared for the proposed fault detection mechanism: heuristic depth first searching (HDFS) and shortest path Eulerian matching (SPEM). The degradation of wavelength utilization and the cardinality of cycle covers are analyzed for evaluating the proposed mechanism. The proposed mechanism is applied to four network examples: NSFNET, ARPA2, SmallNet and Bellcore. The evaluation results show that the proposed fault detection mechanism is effective and cost efficient.
6505998
Failure factor based yield enhancement for SRAM designs
With increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-for-yield (DFY) methodologies have an increasing impact on the yield learning of modem silicon chips. However, a major part of a system chip is typically occupied by memories, which dominate the yield of the chip. During chip integration, it is important that we pick the right design of memory cores that will maximize the yield under the specific process technology chosen. Traditionally, yield prediction is only based on layout and defect statistics. In this paper, we propose to estimate the yield with a failure factor. We thus develop a memory failure factor analyzer (FFA), based on that, we can select the memory design that is more suitable for the given process technology. Experimental results show that we can efficiently evaluate the yields of different memory designs for the same specification, so that the most robust one, that results in the highest yield, can be selected.
41188840
Finding Double Euler Trails of Planar Graphs in Linear Time
This paper answers an open question in the design of complimentary metal-oxide semiconductor VLSI circuits. The question asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding ${\cal E}$ such that ${\cal E}$ has an Euler trail P = e1 e2 ... em and its dual graph has an Euler trail $P^*=e^*_1 e^*_2 \ldots e^*_m$, where $e^*_i$ is the dual edge of ei for i=1,2,...,m. This paper answers this question in the affirmative by presenting a linear-time algorithm.