41662557
Soft Errors: Technology Trends, System Effects, and Protection Techniques
Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level modeling of soft errors, architectural impact of soft errors, challenges associated with evaluation of run-time behaviors of systems in the presence of soft errors, actual data on system behaviors in the presence of soft errors, metrics for quantifying soft error vulnerabilities, design of architectures with Built-in-Soft-Error-Resilience techniques, and actual case studies.
42903241
Test vector compression using EDA-ATE synergies
This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.
2397835
Speed clustering of integrated circuits
Experimental data on 0.18 /spl mu/ test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.
2734062
A design diversity metric and reliability analysis for redundant systems
Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs. Based on this metric, we derive analytical reliability models that show a simple relationship between design diversity, system failure rate, and mission time. In addition, we present simulation results to demonstrate the effectiveness of design diversity in Duplex and Triple Modular Redundant (TMR) systems. For independent multiple-module failures, we show that, mere use of different implementations does not always guarantee higher reliability compared to redundant systems with identical implementations-it is important to analyze the reliability of redundant systems using our metric. For common-mode failures and design faults, there is a significant gain in using different implementations-however, as our analysis shows, the gain diminishes as the mission time increases. Our simulation results also demonstrate the usefulness of diversity for enhancing the self-testing properties of redundant systems.
18607273
X-tolerant test response compaction
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.
900289
Techniques and algorithms for fault grading of FPGA interconnect test configurations
Conventional fault simulation techniques for field programmable gate arrays (FPGAs) are very complicated and time consuming. The alternative, FPGA fault emulation technique, is incomplete and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. The presented technique is able to report all detectable and undetectable faults and, compared with conventional methods, is orders of magnitude faster.
10906898
The Role of Statistical Models in Biometric Authentication
The current paper demonstrates the role of statistical models in authentication tasks – both in system development and in performance evaluation. We first introduce a model-based face authentication system based on the Fourier domain phase using Gaussian Mixture Models (GMM) which yields verification error rates as low as 0.3% on a face database of 65 individuals with extreme illumination variations. We then present a statistical framework for predicting authentication error rates for future populations in a rigorous way. This is in contrast to most evaluation protocols used today that are based on observational studies and valid only for the databases at hand. Applications establish that our model-based approach has better predictive performance than an existing state-of-the-art authentication technique.
1899140
Learning Cycle-Linear Hybrid Automata for Excitable Cells
We show how to automatically learn the class of Hybrid Automata called Cycle-Linear Hybrid Automata (CLHA) in order to model the behavior of excitable cells. Such cells, whose main purpose is to amplify and propagate an electrical signal known as the action potential (AP), serve as the "biologic transistors" of living organisms. The learning algorithm we propose comprises the following three phases: (1) Geometric analysis of the APs in the training set is used to identify, for each AP, the modes and switching logic of the corresponding Linear Hybrid Automata. (2) For each mode, the modified Prony's method is used to learn the coefficients of the associated linear flows. (3) The modified Prony's method is used again to learn the functions that adjust, on a per-cycle basis, the mode dynamics and switching logic of the Linear Hybrid Automata obtained in the first two phases. Our results show that the learned CLHA is able to successfully capture AP morphology and other important excitable-cell properties, such as refractoriness and restitution, up to a prescribed approximation error. Our approach is fully implemented in MATLAB and, to the best of our knowledge, provides the most accurate approximation model for ECs to date.
29308229
Safety Verification of Model Helicopter Controller Using Hybrid Input/Output Automata
This paper presents an application of the Hybrid I/O Automaton (HIOA) framework [12] in verifying a realistic hybrid system. A supervisory pitch controller for a model helicopter system is designed and then verified. The design of the supervisor is limited by the actuator bandwidth, the sensor inaccuracies, and the sampling rates. Verification is carried out by induction over the length of an execution of the composed system automaton. The HIOA model makes the inductive proofs tractable by decomposing them into independent discrete and continuous parts. The paper also presents a set of language constructs for specifying hybrid I/O automata.
6745026
Translating Timed I/O Automata Specifications for Theorem Proving in PVS
Timed Input/Output Automaton (TIOA) is a mathematical framework for specification and analysis of systems that involve discrete and continuous evolution. In order to employ an interactive theorem prover in deducing properties of a TIOA, its state-transition based description has to be translated to the language of the theorem prover. In this paper, we describe a tool for translating TIOA to the language of the Prototype Verification System (PVS)—a specification system with an integrated interactive theorem prover. We describe the translation scheme, discuss the design decisions, and briefly present three case studies to illustrate the application of the translator in the verification process.
45280262
Leveraging information in multi-echelon inventory systems
Abstract Decision-making in multi-echelon inventory systems is often facilitated by the availability of information. In this paper, we examine the effect of utilising demand information in a one-warehouse two-retailer system operating under periodic-review. A common and fixed replenishment interval is assumed for all stages. The lead times are deterministic, and are small compared to the replenishment interval. The warehouse does not maintain any cycle stock, i.e., as soon as replenishment arrives at the warehouse, retailers’ demands are fulfilled from the available stock. In the event of a shortage at the warehouse, two cases have been considered––emergency shipment and allocation. For both the cases, expected total cost (ETC) models have been developed, and it has been shown through numerical examples that the optimal ETC in the presence of demand information is always lower than that in the absence of demand information. It is also noted that the order-up-to level at the warehouse has to be dynamic to reap the benefits of availability of demand information.