7462465
Power Analysis and Optimization Techniques for Energy Efficient Computer Systems
Reducing power consumption has become a major challenge in the design and operation of today's computer systems. This chapter describes different techniques addressing this challenge at different levels of system hardware, such as CPU, memory, and internal interconnection network, as well as at different levels of software components, such as compiler, operating system and user applications. These techniques can be broadly categorized into two types: Design time power analysis versus run-time dynamic power management. Mechanisms in the first category use analytical energy models that are integrated into existing simulators to measure the system's power consumption and thus help engineers to test power-conscious hardware and software during design time. On the other hand, dynamic power management techniques are applied during run-time, and are used to monitor system workload and adapt the system's behavior dynamically to save energy.
12012567
Energy efficient routing protocols for mobile ad hoc networks
Summary Although establishing correct and efficient routes is an important design issue in mobile ad hoc networks (MANETs), a more challenging goal is to provide energy efficient routes because mobile nodes’ operation time is the most critical limiting factor. This article surveys and classifies the energy-aware routing protocols proposed for MANETs. They minimize either the active communication energy required to transmit or receive packets or the inactive energy consumed when a mobile node stays idle but listens to the wireless medium for any possible communication requests from other nodes. Transmission power control approach and load distribution approach belong to the former category, and sleep/power-down mode approach belongs to the latter category. While it is not clear whether any particular algorithm or a class of algorithms is the best for all scenarios, each protocol has definite advantages/disadvantages and is well suited for certain situations. The purpose of this paper is to facilitate the research efforts in combining the existing solutions to offer a more energy efficient routing mechanism. Copyright # 2003 John Wiley & Sons, Ltd.
1642899
Isomorphic Strategy for Processor Allocation in k-Ary n-Cube Systems
Due to its topological generality and flexibility, the k-ary n-cube architecture has been actively researched for various applications. However, the processor allocation problem has not been adequately addressed for the k-ary n-cube architecture, even though it has been studied extensively for hypercubes and meshes. The earlier k-ary n-cube allocation schemes based on conventional slice partitioning suffer from internal fragmentation of processors. In contrast, algorithms based on job-based partitioning alleviate the fragmentation problem but require higher time complexity. This paper proposes a new allocation scheme based on isomorphic partitioning, where the processor space is partitioned into higher dimensional isomorphic subcubes. The proposed scheme minimizes the fragmentation problem and is general in the sense that any size request can be supported and the host architecture need not be isomorphic. Extensive simulation study reveals that the proposed scheme significantly outperforms earlier schemes in terms of mean response time for practical size k-ary and n-cube architectures. The simulation results also show that reduction of external fragmentation is more substantial than internal fragmentation with the proposed scheme.
18416128
Dynamic Simultaneous Multithreaded Architecture
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomplish this, threads are generated dynamically from a predictable flow of control and then executed speculatively. Data obtained during the single context nonspeculative execution phase of DSMT is used as a hint to speculate the posterior behavior of multiple threads. DSMT employs simple mechanisms based on state bits that keep track of inter-thread dependencies in registers and memory, synchronize thread execution, and control recovery from misspeculation. Moreover, DSMT utilizes a novel greedy policy for choosing those sections of code which provide the highest performance based on their past execution history. The DSMT architecture was simulated with a new cycle-accurate, execution-driven simulator. Our simulation results show that DSMT has very good potential to improve SMT performance, even when only a single program is available. However, we found that dynamic thread behavior together with frequent misspeculation may also produce diminishing returns in performance. Therefore, the challenge is to maximize the amount of thread-level parallelism that DSMT is capable of exploiting and at the same time reduce the frequency of misspeculations.
6217758
Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card
This paper describes the implementation and performance of M-VIA on the AceNIC Gigabit Ethernet card. The AceNIC adapter has several notable hardware features for high-speed communication, such as jumbo frames and interrupt coalescing. The M-VIA performance charac- teristics were measured and evaluated based on these hardware features. Our results show that latency and bandwidth improvement can be ob- tained when the M-VIA data segmentation size is properly adjusted to utilize the AceNIC's jumbo frame feature. The M-VIA data segmenta- tion size of 4,096 bytes with MTU size of 4,138 bytes showed the best performance. However, larger MTU sizes did not necessarily result in better performance due to extra segmentation and DMA setup over- head. In addition, the cost of M-VIA interrupt handling can be reduced with AceNIC's hardware interrupt coalescing. When the parameters for the hardware interrupt coalescing were properly adjusted, the latency of interrupt handling was reduced by up to 170 µs.
11122198
Shared memory and distributed shared memory systems: A survey
Publisher Summary This chapter illustrates distributed shared memory (DSM) systems that are intended to combine the ease of programming of the shared-memory model with the scalability of the distributed-memory system. DSM systems aim to unify parallel processing systems that rely on message passing with the shared-memory systems. The chapter explores the design space for such systems and includes descriptions of both hardware- and software-supported DSM systems. The implementation prototypes of some of the systems are based on older technology and older software designs, making them appear to perform poorly.
10692830
Accurate and efficient regression modeling for microarchitectural performance and power prediction
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a large microarchitectural design space. This paper addresses fundamental challenges in microarchitectural simulation cost by reducing the number of required simulations and using simulated results more effectively via statistical modeling and inference.Specifically, we derive and validate regression models for performance and power. Such models enable computationally efficient statistical inference, requiring the simulation of only 1 in 5 million points of a joint microarchitecture-application design space while achieving median error rates as low as 4.1 percent for performance and 4.3 percent for power. Although both models achieve similar accuracy, the sources of accuracy are strikingly different. We present optimizations for a baseline regression model to obtain (1) application-specific models to maximize accuracy in performance prediction and (2) regional power models leveraging only the most relevant samples from the microarchitectural design space to maximize accuracy in power prediction. Assessing sensitivity to the number of samples simulated for model formulation, we find fewer than 4,000 samples from a design space of approximately 22 billion points are sufficient. Collectively, our results suggest significant potential in accurate and efficient statistical inference for microarchitectural design space exploration via regression models.
6809024
TreePlus: Interactive Exploration of Networks with Enhanced Tree Layouts
Despite extensive research, it is still difficult to produce effective interactive layouts for large graphs. Dense layout and occlusion make food Webs, ontologies and social networks difficult to understand and interact with. We propose a new interactive visual analytics component called TreePlus that is based on a tree-style layout. TreePlus reveals the missing graph structure with visualization and interaction while maintaining good readability. To support exploration of the local structure of the graph and gathering of information from the extensive reading of labels, we use a guiding metaphor of "plant a seed and watch it grow." It allows users to start with a node and expand the graph as needed, which complements the classic overview techniques that can be effective at (but often limited to) revealing clusters. We describe our design goals, describe the interface and report on a controlled user study with 28 participants comparing TreePlus with a traditional graph interface for six tasks. In general, the advantage of TreePlus over the traditional interface increased as the density of the displayed data increased. Participants also reported higher levels of confidence in their answers with TreePlus and most of them preferred TreePlus
16215166
Visual Media Retrieval Framework Using Web Service
The need for content-based image retrieval from image databases is ever increasing rapidly in many applications, such as electronic art museums, internet shopping malls, internet search engines, and medical information systems. Many such image resources have been previously developed and widely spread over the internet. In this paper, we propose a Web Service-driven architecture, named the HERMES(tHE Retrieval framework for visual MEdia Service), to support effective retrieval on large volumes of visual media resources. We explain how semantic metadata and ontology can be utilized to realize more intelligent content-based retrieval on visual media data.
355618
Reducing pattern delay variations for screening frequency dependent defects
The delay variations of a pattern set can come from two sources: (1) Different patterns sensitize different parts of the circuit and result in different delays. (2) The same pattern, applied on different chips, results in different delays because of process variations. For structural delay testing, these pattern variations may result in difficulty for finding an optimal test clock setting, which may significantly impact the defect screening effectiveness. This paper investigates the possibility of applying statistical timing analysis techniques to reduce pattern variations for structural delay testing. We develop an efficient statistical pattern-based timing simulator and devise pattern selection algorithms for reducing such variations. By constructing pattern sets with smaller variations, we show that higher screening effectiveness can be achieved. We present experimental results to demonstrate the advantages of our techniques based on benchmark circuits.
33958226
Performance evaluation of a communication optimization model in network-based parallel computing
Network based distributed computing has been gaining popularity over the past decade. Many parallel programming languages and related parallel programming modes are becoming widely accepted. However, the execution of parallel applications on distributed systems has been hampered by the high communication overhead. To reduce the communication overhead and the completion time of a parallel application, we propose a key message model for parallel computing on network of workstations (NOWs). In the key message model, all messages generated in a key message path are prioritized. A key message path in a task graph is defined as the path that is optimized by the key message algorithm. All messages generated in a key message path are prioritized. Besides, the key message algorithm automatically finds the key message paths. In this paper, we first describe the algorithm that identifies the key messages to be prioritized in a parallel application, then analyze the cost of the algorithm, and finally evaluate the performance of the algorithm in a simulation. Our preliminary analysis of the algorithm shows improvement over the system which does not use prioritization scheme.