1176441
Secure Audit Logging with Tamper-Resistant Hardware
Secure perimeter schemes (e.g. DRM) and tracing traitor schemes (e.g. watermarking, audit logging) strive to mitigate the problems of content escaping the control of the rights holder. Secure audit logging records the user's actions on content and enables detection of some forms of tampering with the logs. We implement Schneier and Kelsey's secure audit logging protocol, strengthening the protocol by using tamper-resistant hardware (an iButton) in two ways: Firstly our implementation of the protocol works offline as well as online. Secondly, we use unforgeable time stamps to increase the possibilities of fraud detection. We provide a performance assessment of our implementation to show under which circumstances the protocol is practical to use.
8351252
Using object deputy model to prepare data for data warehousing
Providing integrated access to multiple, distributed, heterogeneous databases and other information sources has become one of the leading issues in database research and the industry. One of the most effective approaches is to extract and integrate information of interest from each source in advance and store them in a centralized repository (known as a data warehouse). When a query is posed, it is evaluated directly at the warehouse without accessing the original information sources. One of the techniques that this approach uses to improve the efficiency of query processing is materialized view(s). Essentially, materialized views are used for data warehouses, and various methods for relational databases have been developed. In this paper, we first discuss an object deputy approach to realize materialized object views for data warehouses which can also incorporate object-oriented databases. A framework has been developed using Smalltalk to prepare data for data warehousing, in which an object deputy model and database connecting tools have been implemented. The object deputy model can provide an easy-to-use way to resolve inconsistency and conflicts while preparing data for data warehousing, as evidenced by our empirical study.
27568459
Automated transformation of algorithms into register-transfer level implementations
This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled. >
7886387
An Efficient Reduction from Constrained to Unconstrained Maximum Agreement Subtree
We propose and study the Maximum Constrained Agreement Subtree (MCAST) problem, which is a variant of the classical Maximum Agreement Subtree (MAST) problem. Our problem allows users to apply their domain knowledge to control the construction of the agreement subtrees in order to get better results. We show that the MCAST problem can be reduced to the MAST problem efficiently and thus we have algorithms for MCAST with running times matching the fastest known algorithms for MAST.
10777322
Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problem is formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.
40452783
A Buffering/Caching Mechanism for Continous Media Players
In order to reduce the playback discontinuity of a stream of data (audio for example) sent through a packet-switched network, we proposed a buffering/caching mechanism for continuous media players. The stream playback is usually implemented by two parallel processes: receiving and playing. The former receives stream chips from the network while the latter plays the received stream chips and then empties their occupied buffers for the former. Our buffering/caching mechanism makes the receiving process completely independent of the playing process. Thus, the receiving process does not need to wait for the playing process to empty buffers so that the network bandwidth can be used as much as possible. Because the cached stream chips can be played from the local disk, the response latency of the playback control operations such as REPLAY and REWIND can be reduced as well. The mechanism was developed for our hyper audio web system.
7761822
An integrated system-on-chip test framework
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.