6818133
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
A 5-layer neuromorphic vision processor whose components communicate spike events asychronously using the address-event-representation (AER) is demonstrated. The system includes a retina chip, two convolution chips, a 2D winner-take-all chip, a delay line chip, a learning classifier chip, and a set of PCBs for computer interfacing and address space remappings. The components use a mixture of analog and digital computation and will learn to classify trajectories of a moving object. A complete experimental setup and measurements results are shown.
6979172
Encoding the Temporal Statistics of Markovian Sequences of Stimuli in Recurrent Neuronal Networks
Encoding, storing, and recalling a temporal sequence of stimuli in a neuronal network can be achieved by creating associations between pairs of stimuli that are contiguous in time. This idea is illustrated by studying the behavior of a neural network model with binary neurons and binary stochastic synapses. The network extracts in an unsupervised manner the temporal statistics of the sequence of input stimuli. When a stimulus triggers the recalling process, the statistics of the output patterns reflects those of the input. If the sequence of stimuli is generated through a Markov process, then the network dynamics faithfully reproduces all the transition probabilities.
18592302
A Winner-Take-All Circuit with Controllable Soft Max Property
I describe a silicon network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths. This output models the normalization property of the wide-field direction-selective cells in the fly visual system. This normalizing property is also useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit with one additional transistor and a voltage reference. Just as in Lazzaro's circuit, the outputs of the excitatory neurons code the neuron with the largest input. The difference here is that multiple winners can be chosen. By varying the voltage reference of the neuron, the network can transition between a soft-max behavior and a hard WTA behavior. I show results from a fabricated chip of 20 neurons in a 1.2 µm CMOS technology.
34951314
Spike synchronization in a network of silicon integrate-and-fire neurons
Spike-event based computational processing by neuronal networks depends on a variety of spatio-temporal mechanisms that are distributed across neuronal synapses, dendrites, and somata. The overall processing of spatio-temporal patterns of spike requires global temporal coherence between all these processes both within a neuron, and across all neurons of the network. We are evaluating the use of networks of hybrid analog-digital integrate-and-fire neurons, fabricated using VLSI, for studying real-time event-based processing. These hardware networks have the advantages of real-time operation, and inherent global synchronization by their analog implementation. However, one of the technical challenges in the operation of such networks is the unavoidable fabrication related variance between the different neurons of the network. Here we show that despite this variance, an important behavior of neuronal networks, spike synchronization, can be obtained from a simple network of VLSI neurons interconnected by lateral excitation and global inhibition.
1845062
Adaptive Retina with Center-Surround Receptive Field
Both vertebrate and invertebrate retinas are highly efficient in extracting contrast independent of the background intensity over five or more decades. This efficiency has been rendered possible by the adaptation of the DC operating point to the background intensity while maintaining high gain transient responses. The center-surround properties of the retina allows the system to extract information at the edges in the image. This silicon retina models the adaptation properties of the receptors and the antagonistic center-surround properties of the laminar cells of the invertebrate retina and the outer-plexiform layer of the vertebrate retina. We also illustrate the spatio-temporal responses of the silicon retina on moving bars. The chip has 59×64 pixels on a 6.9×6.8mm2 die and it is fabricated in 2 µm n-well technology.
12793172
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 /spl mu/m CMOS technology are in agreement with the analysis.<<ETX>>
5842197
Configurable indexing and ranking for XML information retrieval
Indexing and ranking are two key factors for efficient and effective XML information retrieval. Inappropriate indexing may result in false negatives and false positives, and improper ranking may lead to low precisions. In this paper, we propose a configurable XML information retrieval system, in which users can configure appropriate index types for XML tags and text contents. Based on users' index configurations, the system transforms XML structures into a compact tree representation, Ctree, and indexes XML text contents. To support XML ranking, we propose the concepts of "weighted term frequency" and "inverted element frequency," where the weight of a term depends on its frequency and location within an XML element as well as its popularity among similar elements in an XML dataset. We evaluate the effectiveness of our system through extensive experiments on the INEX 03 dataset and 30 content and structure (CAS) topics. The experimental results reveal that our system has significantly high precision at low recall regions and achieves the highest average precision (0.3309) as compared with 38 official INEX 03 submissions using the strict evaluation metric.
11127695
The semantics of extended SOFL
SOFL (structured-object-based-formal language) has been extended to a formal object-oriented language and method while keeping its structured features. This extension allows powerful object-oriented reuse mechanisms, such as class inheritance and object composition, to be utilized in the early design phases. This paper presents the semantics for this extended SOFL, and further demonstrates the extendibility and reusability of the object-oriented semantic models of SOFL.
7160160
QoS-UniFrame: a Petri net-based modeling approach to assure QoS requirements of distributed real-time and embedded systems
Assuring quality of service (QoS) requirements is critical when assembling a distributed real-time and embedded (DRE) system from a repository of existing components. This paper presents a two-level approach for assuring satisfaction of QoS requirements in the context of a reduced design space for DRE systems. A dynamic and parallel approach is introduced to prune off the infeasible design spaces at the first level. Evolutionary algorithms cooperating with a domain-specific scripting language then discard less probable design spaces using statistics. These techniques fulfill the collective objectives of pruning and assuring the design space at system assembly time.
18693305
Verifying Consistency and Validity of Formal Specifications by Testing
Detecting faults in specifications can help reduce the cost and risk of software development because incorrect implementation can be prevented early. This goal can be achieved by verifying the consistency and validity of specifications. In this paper we put forward specification testing as a practical technique for verification and validation of formal specifications. Our approach is to derive proof obligations from a specification and then test them, in order to detect faults leading to the violation of consistency or validity of the specification. We describe proof obligations for various consistency properties of a specification, and suggest the use of five strategies for testing them. We provide a method for testing implicit specifications by evaluation rather than by prototyping, and criteria for interpreting the meaning of test results.
227525
Integrated RFID data modeling: an approach for querying physical objects in pervasive computing
Radio frequency identiﬂcation(RFID) technology uses radio-frequency waves to transfer data between readers and mov-able tagged objects without line of sight. RFID holds thepromise of real-time identifying, locating, tracking and mon-itoring physical objects, and can be used for a wide range ofpervasive computing applications. To achieve these goals,RFID data have to be collected, transformed and expres-sively modeled as their virtual counterparts in the virtualworld. RFID data, however, have their own unique char-acteristics { including aggregation, location, temporal andhistory-oriented { which have to be fully considered and inte-grated into the data model. The diversity of RFID applica-tions pose further challenges to a generalized framework forRFID data modeling. In this paper, we explore the funda-mental characteristics of RFID data and classify RFID ap-plications into a set of typical scenarios. We then propose ageneralized RFID data modeling framework with constructsfor each typical scenario. These constructs can be combinedto model most RFID applications in real world.