26839737
A BIST scheme for FPGA interconnect delay faults
In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.
29576760
A configurable AES processor for enhanced security
904578
Simulation-based test algorithm generation for random access memories
Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.
10023746
Test and diagnosis of word-oriented multiport memories
Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observability and controllability that effectively reduces the test time. Our key idea is that a sequence of March operations for any memory cell can be folded and executed within a single access cycle. We have also developed an efficient test algorithm for port-specific faults as well as traditional cell faults. The port-specific faults include the stuck-open, address decoder, and inter-port faults, for both bit-oriented and word-oriented RAMs. Experimental results for our folding scheme show that the test time reduction is about 28% for a commercial 8 KB embedded SRAM. An efficient diagnostic algorithm is also proposed for the port-specific faults and traditional cell faults.
28276441
A Programmable BIST Core for Embedded DRAM
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy.
14027625
On test and diagnostics of flash memories
Embedded flash memory has been widely used in applications that require non-volatile on-chip storage elements. However, test and diagnostics of flash memories needs further investigation so that the overall cost of the products can be reduced. This paper presents the challenges and issues for test and diagnostics of flash memories, based on our recent experiences. We also suggest improvement of the test and diagnosis flow, including design-for-testability (DFT) using built-in self-test (BIST), built-in self-repair (BISR), and failure analysis. In addition, we present a configurable flash memory tester using FPGA for low-cost testing and diagnostics. Experimental results on industrial flash chips justify the effectiveness of our test and diagnostics system.
2224019
Using an Immune System Model to Explore Mate Selection in Genetic Algorithms
When Genetic Algorithms (GAs) are employed in multimodal function optimization, engineering and machine learning, identifying multiple peaks and maintaining subpopulations of the search space are two central themes. In this paper, an immune system model is adopted to develop a framework for exploring the role of mate selection in GAs with respect to these two issues. The experimental results reported in the paper will shed more light into how mate selection schemes compare to traditional selection schemes. In particular, we show that dissimilar mating is beneficial in identifying multiple peaks, yet harmful in maintaining subpopulations of the search space.
54735
An architecture for real-time active content distribution
The phenomenal growth of the World Wide Web has made it the most popular Internet application today. Web caching and content distribution services have been recognized as valuable techniques to mitigate the explosion of Web traffic. An increasing fraction of Web traffic today is dynamically generated and therefore intrinsically difficult for replication using present static approaches. Scalable delivery of such active content poses a myriad of challenges, including content replication, update propagation, and consistency management. This paper makes two contributions: (1) it describes a scalable architecture for transparent demand-driven distribution of active content; (2) the system can provide real-time delay guarantee on content access. Our approach involves migrating the scripts which generate the dynamic Web traffic, and their data, from the server to active content distribution proxies nearest to the clients and mechanisms on these proxies to enforce real-time delay guarantees for client requests. Our system is implemented and deployed on PlanetLab, a real-world distributed Internet testbed. Experimental data show that significant improvements are observed in effective throughput and client response time, and delay bounds on content access can be guaranteed with a very high probability.
5351237
Game traffic analysis: an MMORPG perspective
Online gaming is one of the most profitable businesses over the Internet. Among all genres of the online games, the popularity of the MMORPG (Massive Multiplayer Online Role Playing Games) is especially prominent in Asia. Opting for a better understanding of the game traffic and the economic well being of the Internet, we analyze a 1,356-million-packet trace from a sizeable MMORPG, ShenZhou Online. This work is, as far as we know, the first formal analysis on the MMORPG server traces.We find that the MMORPG and FPS (First-Person Shooting) games are similar in that they both generate small packets and require low bandwidths. In particular, the bandwidth requirement of MMORPG is even lower due to the less real-time game play. More distinctive are the strong periodicity, temporal locality, and irregularity observed in the MMORPG traffic. The periodicity is due to a common practice in game implementation, where the game state updates are accumulated within a fixed time window before transmission. The temporal locality in the game traffic is largely due to the game nature where one action leads to another. The irregularity, particular unique in MMORPG traffic, is due to the diversity of game design where the user behavior can be drastically different depending on the quest at hand.
1236122
Range-free localization and its impact on large scale sensor networks
With the proliferation of location dependent applications in sensor networks, location awareness becomes an essential capability of sensor nodes. Because coarse accuracy is sufficient for most sensor network applications, solutions in range-free localization are being pursued as a cost-effective alternative to more expensive range-based approaches. In this paper, we present APIT, a novel localization algorithm that is range-free. We show that our APIT scheme performs best when an irregular radio pattern and random node placement are considered, and low communication overhead is desired. We compare our work, via extensive simulation, with three state-of-the-art range-free localization schemes to identify the preferable system configurations of each. In addition, we provide insight into the impact of localization accuracy on various location dependent applications and suggestions on improving their performance in the presence of such inaccuracy.
7537228
Achieving strong scaling with NAMD on Blue Gene/L
NAMD is a scalable molecular dynamics application, which has demonstrated its performance on several parallel computer architectures. Strong scaling is necessary for molecular dynamics as problem size is fixed, and a large number of iterations need to be executed to understand interesting biological phenomenon. The Blue Gene/L machine is a massive source of compute power. It consists of tens of thousands of embedded Power PC 440 processors. In this paper, we present several techniques to scale NAMD to 8192 processors of Blue Gene/L. These include topology specific optimizations, new messaging protocols, load-balancing, and overlap of computation and communication. We were able to achieve 1.2 TF of peak performance for cutoff simulations and 0.99 TF with PME.