17722126
Architectural primitives for a scalable shared memory multiprocessor
Since large memory latencies are not uncommon for a large scale multiprocessor, researchers have investigated memory models to relax memory access ordering. This paper presents a new memory model, and discusses implementation issues in a cache-based environment. These issues mot ivate a set of architectural primitives with which software can implement desired memory consistency. For efficient cache management, we propose a cache protocol that allows read-initiated actions for coherence maintenance. For efficient synchronization, we present a cache-based locking scheme that implements queued busy-wait ing using cache lines. The scalability of the proposed schemes is explored through analytical modeling and simulation studies.
7999511
A proportional-share scheduler for multimedia applications
This paper presents a proportional-share CPU scheduler which can support multimedia applications in a general-purpose workstation environment. For this purpose, we have extended the stride scheduler which is designed originally for conventional tasks. New scheduling parameters are introduced to specify timing requirements of multimedia applications. Through the, use of the rate regulator, the accuracy error of the scheduling is reduced to O(1). Separate task groups are proposed to represent both relative shares and absolute shares. The proposed scheduler is evaluated using a simulation study. The results show that the proposed scheduler achieves improved accuracy and adaptability as well as fairness.
43495365
A scalable cache coherent architecture for large-scale mesh-connected multiprocessors
Until now, various limited directory-based cache coherence protocols were proposed for medium- or large-scale multiprocessors while employing scalable directory memories. For widely shared data, however, most protocols suffer from extraneous cache invalidates or updates due to insufficient pointers. We focus on large-scale mesh-connected multiprocessors built on top of wormhole and dimension ordered routing networks. In such networks, worms are major bricks for communications, which transit all the intermediate nodes on their way to a destination. From such an observation, we propose a new directory-based protocol DirQ with limited pointers, which can represent either one node or a set of nodes when being widely shared. For /spl radic/N/spl times//spl radic/N processors system, our protocol needs /spl Theta/(N/sup 3/2/ log N) bits for directory memory which is much more scalable compared to the full-map protocol. In terms of latency and traffic volume for cache coherence, our analytic models show that DirQ outperforms other limited protocols, and further comparable to the full-map one.
207160824
A superblock-based flash translation layer for NAND flash memory
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL)is usually employed to hide the erase-before-write characteristics of NAND flash memory. This paper proposes a novel superblockbased FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed FTL scheme, superblocks are mapped at coarse granularity,while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid mapping technique has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme decreases the garbage collection overhead up to 40% compared to previous FTL schemes.
7796564
CFLRU: a replacement algorithm for flash memory
In most operating systems which are customized for disk-based storage system, the replacement algorithm concerns only the number of memory hits. However, flash memory has different read and write cost in the aspects of time and energy so the replacement algorithm with flash memory should consider not only the hit count but also the replacement cost caused by selecting dirty victims. The replacement cost of dirty page is higher than that of clean page with regard to both access time and energy consumption. In this paper, we propose the Clean-First LRU (CFLRU) replacement algorithm that exploits the characteristics of flash memory. CFLRU splits the LRU list into the working region and the clean-first region and adopts a policy that evicts clean pages preferentially in the clean-first region until the number of page hits in the working region is preserved in a suitable level. Using the trace-driven simulation, the proposed algorithm reduces the average replacement cost by 28.4% in swap system and by 26.2% in buffer cache, compared with LRU algorithm. We also implement the CFLRU algorithm in the Linux kernel and present some optimization issues.
15447025
A Speculative Coherence Scheme using Decoupling Synchronization for Multiprocessor Systems
This paper proposes a new speculative coherencescheme, SCDS, for hardware distributed shared memory systemsto reduce the overhead of coherence action in directory-basedcache-coherence protocol. SCDS has two main features,predicting accurate timing of speculative coherence withsynchronization information and detecting write pattern(migratory and non-migratory) for exclusive blocks' speculativecoherence action. In our simulation, SCDS outperforms existingschemes (DSI and LTP) for well-synchronized applications.
52853952
Adaptive acknowledgment scheme for efficient error control in ATM clustering system
An ATM clustering system is a kind of workstation clusters over an ATM network. Such a system can be used as a distributed database server which requires reliable data delivery. This paper proposes an error recovery scheme at the transport layer for reliable data transfers with high throughput in the ATM clustering system. For such data transfers, acknowledgments are sent periodically as well as at the detection of packet losses. To be efficient the periods of acknowledgments for the scheme are adaptively varied depending on,whether current transfer is either in error-free phase or in an error recovery phase. The design and performance evaluation of the error recovery scheme is presented with a set of parameter values to achieve the best performance. The results show that the proposed scheme operates correctly and efficiently for the ATM clustering system. The throughput performance of the proposed scheme is superior to the SSCOP (service specific connection oriented protocol) regardless of packet loss rates.
16229648
Enhancement of a WLAN-based internet service in Korea
A wireless LAN (WLAN)-based Internet service, called NESPOT, of Korea Telecom (KT), the biggest telecommunication and Internet service company in Korea, has been operational since early 2002. As the numbers of subscribers and deployed access points (APs) increase, KT has been endeavoring to improve its service quality as well as the network management. In this paper, we introduce a joint effort between Seoul National University (SNU) and KT to achieve it. We have been addressing two major issues as part of the joint project thus far: (1) a unified WLAN management tool; and (2) real-time traffic support enhancement. We present our on-going efforts as well as some preliminary results. Some issues, which need further attention for the future NESPOT service enhancement, are also introduced.
3175252
Predicate-based caching in mobile clients for con tinuous partial match queries
This paper proposes a cache management scheme for continuous partial match queries in mobile computing systems. Conventional cache management methods for mobile clients are record ID-based ones. However, since the partial match query is a content-based retrieval, the conventional record ID-based approach cannot properly manage the cache consistency. We show the pr edicate- based approach is an effective cache management in mobile environments.
5993695
Correlation Prefetching with a User-Level Memory Thread
This paper proposes using a user-level memory thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: The correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide applicability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
7307952
Optimal variable-density k-space sampling in MRI
Magnetic resonance imaging (MRI) is often times limited by scan time. To reduce scan time, there have been various efforts to reduce the number of sampling points. In most cases, this is done by utilizing a priori knowledge of the signal of interest. In this paper, we propose an algorithm that will guide the determination of an optimal sampling pattern based on prior knowledge of the signal. Applications of this method include optimal variable-density k-space trajectory design or reduced phase encoding in 3DFT and spectroscopy. Preliminary results are shown as a proof of concept.