1305
Design Considerations for the Virtual Source/Virtual Destination (VS/VD) Feature in the ABR Service of ATM Networks
Abstract The Available Bit Rate (ABR) service in ATM networks uses end-to-end rate-based flow control to allow fair and efficient support of data applications over ATM networks. One of the architectural features in the ABR specification [ATM Forum, ATM Traffic Management Specification Version 4.0, April 1996] is the Virtual Source/Virtual Destination (VS/VD) option. This option allows a switch to divide an end-to-end ABR connection into separately controlled ABR segments by acting like a (virtual) destination on one segment, and like a (virtual) source on the other. The translation and propagation of feedback in the VS/VD switch between the two ABR control segments (called “coupling”) is implementation specific. In this paper, we model a VS/VD ATM switch and study the issues in designing the coupling between ABR segments. We identify a number of implementation options for the coupling and show that the choice of the implementation option significantly affects the system performance in terms of (a) the system stability in the steady state, (b) the time to respond to transient changes and converge to the steady state, and (c) the buffer requirements at the switches.
5318665
Providing rate guarantees to TCP over the ATM GFR service
The ATM guaranteed frame rate (GFR) service is intended for best effort traffic that can benefit from minimum throughput guarantees. Edge devices connecting LANs to an ATM network can use GFR to transport multiple TCP/IP connections over a single GFR VC. These devices would typically multiplex VCs into a single FIFO queue. It has been shown that in general, FIFO queuing is not sufficient to provide rate guarantees, and per-VC queuing with scheduling is needed. We show that under conditions of low buffer allocation, it is possible to control TCP rates with FIFO queuing and buffer management. We present analysis and simulation results on controlling TCP rates by buffer management. We present a buffer management policy that provides loose rate guarantees to SACK TCP sources when the total buffer allocation is low. We study the performance of this buffer management scheme by simulation.
3204907
Performance of Bursty World Wide Web (WWW) Sources over ABR
Bobby Vandalore, Shivkumar Kalyanaraman, Raj Jain, Rohit Goyal, Sonia Fahmy The Ohio State University, Department of CIS Columbus, OH 43210-1277 Phone: 614-688-4482, Fax: 614-292-2911 Email: fvandalor, shivkuma, jain, goyal, fahmyg@cis.ohio-state.edu Seong-Cheol Kim Principal Engineer, Network Research Group, Communication Systems R&D Center Samsung Electronics Co. Ltd., Chung-Ang Newspaper Bldg. 8-2, Karak-Dong, Songpa-Ku, Seoul, Korea 138-160 Email: kimsc@metro.telecom.samsung.co.kr Abstract
5623657
Satellite ATM Network Architectural Considerations and TCP/IP Performance
In this paper, we have provided a summary of the design options in Satellite-ATM technology. A satellite ATM network consists of a space segment of satellites connected by inter-satellite crosslinks, and a ground segment of the various ATM networks. A satellite-ATM interface module connects the satellite network to the ATM networks and performs various call and control functions. A network control center performs various network management and resource allocation functions. Several issues such as the ATM service model, media access protocols, and traffic management issues must be considered when designing a satellite ATM network to effectively transport Internet traffic. We have presented the buffer requirements for TCP/IP traffic over ATM-UBR for satellite latencies. Our results are based on TCP with selective acknowledgments and a per-VC buffer management policy at the switches. A buffer size of about 0.5 * RTT to 1 * RTT is sufficient to provide over 98% throughput to infinite TCP traffic for long latency networks and a large number of sources. This buffer requirement is independent of the number of sources. The fairness is high for a large numbers of sources because of the per-VC buffer management performed at the switches and the nature of TCP traffic.
16677800
AQuaFWiN: adaptive QoS framework for multimedia in wireless networks and its comparison with other QoS frameworks
In a wireless environment, due to topology changes and characteristics of media (interference in radio signals) the bandwidth of a link is unpredictable and possibly very low, the error rates are variable and extremely high. Provisioning and guaranteeing quality of service (QoS) in such an environment is a very challenging problem. In this paper we propose an adaptive and QoS framework to support multimedia applications in a wireless networking environment. The proposed framework is hierarchical in nature with cluster of mobile end hosts connected to a base station, base stations are connected to a supervisory node, which in turn is connected to the wired infrastructure. The changing conditions in wireless due to interference and possibly mobility, entitle that the real-time applications needing stringent QoS should be adaptable. The framework uses a generic feedback mechanism to support adaptability at all layers of the wireless network. An overview of existing wireless architectures which support QoS is given. The architectures discussed are WAMIS (wireless adaptive multimedia information system), SWAN (seamless wireless ATM network), MMWN (multimedia support for mobile wireless networks), and QGMC (QoS guarantees in mobile computing). The proposed approach is compared with these existing methods.
609563
A definition of general weighted fairness and its support in explicit rate switch algorithms
We give a general definition of weighted fairness and discuss how a pricing policy can be mapped to general weighted (GW) fairness. The GW fairness can be achieved by calculating the excess fairshare (weighted fairshare of the left over bandwidth) for each VC. We show how a switch algorithm can be modified to support the GW fairness by using the excess fairshare term. We use ERICA+ as an example switch algorithm and show how it can be modified to achieve the general fairness. Simulations results are presented to demonstrate that, the modified switch algorithm achieves GW fairness. An analytical proof for convergence of the modified ERICA+ algorithm is given in the appendix.
40775308
Vector Field Analysis for Oriented Patterns
Presents a method, based on the properties of vector fields, for the estimation of a set of symbolic descriptors (node, saddle, star-node, improper-node, center, and spiral) from linear orientation fields. Planar first-order phase portraits are used to model the linear orientation fields. A weighted linear estimator is developed to estimate linear phase portraits, using only the flow orientation. A classification scheme for planar first-order phase portraits, based on their local properties: curl, divergence, and deformation is developed. The authors present results of experiments on noise-added synthetic flow patterns and real oriented textures. >
13629855
An integrated CAD system for algorithm-specific IC design
LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described. >
47572575
The Art of Computer Systems Performance Analysis
the art of computer systems performance analysis by is one of the most effective vendor publications worldwide? Have you had it? Not at all? Ridiculous of you. Currently, you can get this impressive book simply here. Locate them is layout of ppt, kindle, pdf, word, txt, rar, as well as zip. Just how? Merely download and even read online in this site. Now, never ever late to read this the art of computer systems performance analysis. Whatever our proffesion, the art of computer systems performance analysis can be good source for reading. Find the existing reports of word, txt, kindle, ppt, zip, pdf, and also rar in this website. You can absolutely read online or download this book by right here. Currently, never miss it. Our goal is always to offer you an assortment of cost-free ebooks too as aid resolve your troubles. We have got a considerable collection of totally free of expense Book for people from every single stroll of life. We have got tried our finest to gather a sizable library of preferred cost-free as well as paid files. GO TO THE TECHNICAL WRITING FOR AN EXPANDED TYPE OF THIS THE ART OF COMPUTER SYSTEMS PERFORMANCE ANALYSIS, ALONG WITH A CORRECTLY FORMATTED VERSION OF THE INSTANCE MANUAL PAGE ABOVE.
39032710
Refining decision tree classifiers using rough set tools
The proposed hybridized rough set framework is composed of traditional Rough Set (RS) approach and classical Decision Tree (DT) induction algorithm. RS helps to identify dominant attributes and DT algorithm results in simpler and generalized classifier. The implementation of the Hybridized Rough Set Framework is presented as the RDT algorithm. GA heuristics are used to generalize the RDT algorithm further. Experimental results obtained on applying the hybridized rough set framework and the related base algorithms on datasets belonging to the three categories are presented in this paper. Accuracy, complexity, number of rules and number of attributes in the induced classifier assess the performance of the candidate algorithms. The results indicate that the proposed framework is an effective model for classification.
13296348
Variability in the execution of multimedia applications and implications for architecture
Multimedia applications are an increasingly important workload for general-purpose processors. This paper analyzes frame-level execution time variability for several multimedia applications on general-purpose architectures. There are two reasons for such an analysis. First, it has been conjectured that complex features of such architectures (e.g., out-of-order issue) result in unpredictable execution times, making them unsuitable for meeting real-time requirements of multimedia applications. Our analysis tests this conjecture. Second, such an analysis can be used to effectively employ recently proposed adaptive architectures.
We find that while execution time varies from frame to frame for many multimedia applications, the variability is mostly caused by the application algorithm and the media input. Aggressive architectural features induce little additional variability (and unpredictability) in execution time, in contrast to conventional wisdom.
The presence of frame-level execution time variability motivates frame-level architectural adaptation (e.g., to save energy). Additionally, our results show that execution time generally varies slowly, implying it is possible to dynamically predict the behavior of future frames on a variety of hardware configurations for effective adaptation.