5517060
Structuring Distributed Algorithms in a Workstation Environment: The FrameWorks Approach
46228924
Communication Using a Reconfigurable and Reliable Transport Layer Protocol
Although TCP is known to be inefficient over networks such as wireless, satellite, and log-fat-pipes, it is still the most widely used transport layer protocol even on these networks. In this paper, we explore an alternative strategy for designing a reliable transport layer protocol that is much more suitable for today's mobile and other types of non-conventional networks. The objective here is to have a single protocol that is compatible with today's communication software and can be easily made to perform better over all types of network. The outcome of the research is a reconfigurable, user-level, reliable transport layer protocol, called RRTP (Reliable and Reconfigurable Transport Protocol) that is TCP-friendly, i.e. it asymptotically converges to fairness as in the case of LIMD (Linear Increase Multiplicative Decrease) algorithms. The protocol is implemented on top of UDP, but it can also easily be incorporated into OS kernels. The paper presents the RRTP algorithm and the key parameters that are necessary for its reconfiguration. We evaluate our protocol using the standard network simulation tool (ns2). Several representative network configurations are used to benchmark the performance of our protocol against TCP in terms of network throughput and congestion loss rate. It is observed that under normal operating conditions, our protocol has a performance advantage of 30% to 700% over TCP in lossy, wireless environments as well as high bandwidth, high latency networks.
13609251
Creating an adaptive network of hubs using Schelling's model
Adjusting the overlay network topology in a peer-to-peer network to satisfy performance criteria.
9094346
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.
2485299
Sizing CMOS circuits for increased transient error tolerance
The continuous shrinking of microelectronic device sizes with every technology generation, along with the reduction in supply voltages, is causing a significant decrease in circuit noise margins. This leads to increased susceptibility of circuits to transient errors. In this paper, we propose a methodology to increase the robustness of combinational circuits to transient errors by sizing the gates of the circuit in such a way that the number of errors propagated to the primary output is minimized while the timing requirement is met. Using SPICE simulation, we validate that combinational circuits propagate fewer numbers of transient errors to the circuit output after application of our sizing algorithm.
6105186
Query-based debugging of object-oriented programs
Object relationships in modem software systems are becoming increasingly numerous and complex. Programmers who try to find violations of such relationships need new tools that allow them to explore objects in a large system more efficiently. Many existing debuggers present only a low-level, one-object-at-a-time view of objects and their relationships. We propose a new solution to overcome these problems: query-based debugging. The implementation of the query-based debugger described here offers programmers an effective query tool that allows efficient searching of large object spaces and quick verification of complex relationships. Even for programs that have large numbers of objects, the debugger achieves interactive response times for common queries by using a combination of fast searching primitives, query optimization, and incremental result delivery.
29012055
Variable Order Verification Use of Logic Representation
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. In the last 15 years, a number of applications based on efficient manipulation of Boolean functions gained industrial significance, notably in automated design and verification of logic circuits. The efficient representation and manipulation of Boolean functions is important for many algorithms in a wide variety of applications in particular, many problems in computer-aided design for digital circuits (CAD). The efficiency of the Boolean manipulation depends on the form of representation of the Boolean function. It is unavoidable and important problem to find a variable ordering which minimize the size of a BDD, since variable ordering has a great influence on the computation time and storage requirements for Boolean function manipulation number of times each variable takes part in the Logic operation to obtain the best possible the variable order. This paper describes a technique for finding the best variable ordering by analyzing the logic gate representation in the given Boolean function. Algorithm starts with initial variable ordering. The system will check each sub expression to find out the number times each variable takes part in each type of logic operations. The number of occurrences for each variable will be stored and then all the totals are arranged in descending order to identify the variable ordering for that Boolean function. If more than one input variables have the same total then a special criteria will be used to break the tie: We present graph-based evidence of the improvement obtained by using highly effective logical verification based variable ordering technique for BDDs. It is shown that the effectiveness of the Decision Diagram is mainly depending on the variable ordering selected. It is not practical to have any unique ordering for a given Boolean function and it can be selected among the number of best results, what will be more appropriate with the design. This new technique, easy to implement and automate, consistently creates high quality variable ordering for Boolean function.