1650647
Load balancing in bounded-latency content distribution
In this paper we present a balanced data replication scheme that provides real-time latency bounds on content retrieval in content distribution networks. Many network applications have ever-increasing requirements on latency sensitive data services. Data replication services have been widely used as an important performance enhancement mechanism to reduce data access latency and throughput. We investigate the problem of provisioning an underlying balanced data replication service to provide a global latency bound on data retrieval in content distribution networks. The solution involves constructing an overlay network based on the given latency bound, and a mechanism to assign content objects to the network nodes so that the workload of all the network nodes is balanced. Our evaluation results drawn from detailed simulations show the efficacy of our load-balancing scheme in meeting the latency bound requirements with high confidence under heavy load
1236122
Range-free localization and its impact on large scale sensor networks
With the proliferation of location dependent applications in sensor networks, location awareness becomes an essential capability of sensor nodes. Because coarse accuracy is sufficient for most sensor network applications, solutions in range-free localization are being pursued as a cost-effective alternative to more expensive range-based approaches. In this paper, we present APIT, a novel localization algorithm that is range-free. We show that our APIT scheme performs best when an irregular radio pattern and random node placement are considered, and low communication overhead is desired. We compare our work, via extensive simulation, with three state-of-the-art range-free localization schemes to identify the preferable system configurations of each. In addition, we provide insight into the impact of localization accuracy on various location dependent applications and suggestions on improving their performance in the presence of such inaccuracy.
16039010
Design, Implementation and Evaluation of a Real-Time Active Content Distribution Service
The phenomenal growth of the world-wide web has made it the most popular Internet application today. Web caching and content distribution services have been recognized as valuable techniques to mitigate the explosion of web traffic. An increasing fraction of web traffic today is dynamically generated and therefore intrinsically difficult to replicate or cache using present static approaches. Scalable delivery of such active content poses a myriad of challenges, including content replication, update propagation, and consistency management. This paper makes two contributions: it (1) describes a scalable architecture for transparent demand-driven distribution of active content; and (2) presents a system that can provide real-time delay guarantees on content access. Our approach involves migrating the scripts which generate dynamic web traffic, and their data, from the origin servers to active content distribution proxies nearest to the clients. We also present mechanisms on these proxies to enforce real-time delay guarantees for client requests. Our system is implemented and deployed on Planetlab (2004), a real-world distributed Internet testbed. Experimental data show that significant improvements are observed in effective throughput and client response time, and that delay bounds on content access can be guaranteed with a very high probability.
14142232
Confessible Threshold Ring Signatures
We present two threshold ring signature schemes with different properties. One focuses on the confessibility (or signer verifiability) and the denouncibility properties. The other focuses on the threshold-confessibility. Our schemes are built on generic ring signature schemes and can be easily adapted to most existing ring signature schemes. Based on the former works, we also construct a realization of our schemes as an example. We prove that our schemes are secure in the random oracle model.
15052014
Optimization of Regular Expression Pattern Matching Circuits on FPGA
Regular expressions are widely used in network intrusion detection system (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to the speed advance of networks, many previous works propose hardware architectures on FPGA to accelerate attack detection. The challenge of hardware implementation is to accommodate the regular expressions to FPGAs of the large number of attacks. Although the minimization of logic equations has been studied intensively in the CAD area, the minimization of multiple regular expressions has been largely neglected. This paper presents an architecture allowing our algorithm to extract and share common sub-regular expressions. Experimental results show that our sharing scheme significantly reduces the area of regular expression circuits
2224019
Using an Immune System Model to Explore Mate Selection in Genetic Algorithms
When Genetic Algorithms (GAs) are employed in multimodal function optimization, engineering and machine learning, identifying multiple peaks and maintaining subpopulations of the search space are two central themes. In this paper, an immune system model is adopted to develop a framework for exploring the role of mate selection in GAs with respect to these two issues. The experimental results reported in the paper will shed more light into how mate selection schemes compare to traditional selection schemes. In particular, we show that dissimilar mating is beneficial in identifying multiple peaks, yet harmful in maintaining subpopulations of the search space.
14432070
Monitoring cycles for fault detection in meshed all-optical networks
Fault detection is critical for all-optical networks (AONs). This paper introduces the concept of monitoring cycle and proposes a fault detection mechanism based on decomposing AONs into a set of cycles (a cycle cover), in which each one is defined as a monitoring cycle. Two cycle-finding algorithms are developed and compared for the proposed fault detection mechanism: heuristic depth first searching (HDFS) and shortest path Eulerian matching (SPEM). The degradation of wavelength utilization and the cardinality of cycle covers are analyzed for evaluating the proposed mechanism. The proposed mechanism is applied to four network examples: NSFNET, ARPA2, SmallNet and Bellcore. The evaluation results show that the proposed fault detection mechanism is effective and cost efficient.
1368534
Use of Computation-Unit Integrated Memories in High-Level Synthesis
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller datapath associated with a memory subsystem (monolithic, partitioned, etc.). An architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated is proposed. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This paper addresses the challenge of providing a systematic synthesis framework for a CIM-based architecture. This framework can analyze the various tradeoffs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance low-overhead implementation. Efficient data reuse of register files have also been fully exploited to further improve system performance. Experiments with several behaviors indicate that an average performance improvement of 2.02times(a maximum of 2.70times) is possible with very low area overheads. The energy-delay product improves by an average of 2.5times(maximum of 3.8times)