32785610
Customizing Software Libraries for Performance Portability
15307682
Accommodating polymorphic data decompositions in explicitly parallel programs
Explicitly parallel programs have the potential for greater performance than their implicitly parallel counterparts. However, this benefit can be accompanied by additional programming difficulties. We address one particular problem that has implications for both scalability and portability: the need for programs do accommodate diverse data decompositions. We explain why programs with explicit communication have difficulties in handling changes in data decomposition, and we present a solution to this problem which involves the notions of derivative functions and configuration parameters. We illustrate the technique by using three different data decompositions to solve the Modified Gram-Schmidt method on four parallel machines.<<ETX>>
5795237
The portable parallel implementation of two novel mathematical biology algorithms in ZPL
This paper shows that mathematical models of biological pattern formation are ideally suited to data parallelism. We present two new algorithms, one for simulating the dynamic structure of fibroblasts, and the other for studying the self-organization of motile bacteria. We describe implementations of these algorithms using a high level data parallel language called ZPL, and we give performance results for the Kendall Square Research KSR-2 and the Intel Paragon that include comparisons against sequential Fortran.
1057171
ZPL's WYSIWYG performance model
ZPL is a parallel array language designed for high performance scientific and engineering computations. Unlike other parallel languages, ZPL is founded on a machine model (the CTA) that accurately abstracts contemporary MIMD parallel computers. This makes it possible to correlate ZPL programs with machine behavior. As a result, programmers can reason about how code will perform on a typical parallel machine and thereby make informed decisions between alternative programming solutions. The paper describes ZPL's performance model and its syntactic cues for conveying operation cost. The what you see is what you get (WYSIWYG) nature of ZPL operations is demonstrated on the IBM SP-2, Intel Paragon, SGI Power Challenge, and Cray T3E. Additionally, the model is used to evaluate two algorithms for matrix multiplication. Experiments show that the performance model correctly predicts the faster solution on all four platforms for a range of problem sizes.
7870525
Adaptive History-Based Memory Schedulers
As memory performance becomes increasingly important to overall system performance, the need to carefully schedule memory operations also increases. This paper presents a new approach to memory scheduling that considers the history of recently scheduled operations. This history-based approach provides two conceptual advantages: (1) it allows the scheduler to better reason about the delays associated with its scheduling decisions, and (2) it allows the scheduler to select operations so that they match the program's mixture of Reads and Writes, thereby avoiding certain bottlenecks within the memory controller. We evaluate our solution using a cycle-accurate simulator for the recently announced IBM Power5. When compared with an in-order scheduler, our solution achieves IPC improvements of 10.9% on the NAS benchmarks and 63% on the data-intensive Stream benchmarks. Using microbenchmarks, we illustrate the growing importance of memory scheduling in the context of CMP's, hardware controlled prefetching, and faster CPU speeds.
27000155
Towards a Machine-Independent Solution of Sparse Cholesky Factorization
52872372
Modeling and Performance Analysis of a Multiserver Multiqueue System on the Grid
Grid computing has emerged as an important new field, distinguished from conventional distributed computing by its focus on large-scale resource sharing, innovative applications, and high-performance orientation. A Grid integrates and coordinates resources and users that live within different control domains with the goal of delivering nontrivial quality of service (QoS). Consequently, task management and scheduling is of central importance for the Grid-based systems. In this paper, we model the task dispatching and selecting on the distributed Grid computing system by a multiserver multiqueue (MSMQ) model, and propose a modeling and analysis technique based on Stochastic Petri Net (SPN) methods. An approximate analysis technique is also proposed to reduce the complexity of the model.
26305379
A parallel decoding algorithm for IFS codes without transient behavior
Iterated function systems (IFSs) have received great attention in encoding and decoding fractal images. Barnsley (1988) has shown that IFSs for image compression can achieve a very high compression ratio for a single image. However, the major drawback of such a technique is the large computation load required to both encode and decode a fractal image. We provide a novel algorithm to decode IFS codes. The main features of this algorithm are that it is very suitable for parallel implementation and has no transient behavior. Also, from the decoding process of this method we can understand the encoding procedure explicitly. One example is illustrated to demonstrate the quality of its performance.
43707062
A Dependable Task Scheduling Strategy for a Fault Tolerant Grid Model
Grid provides an integrated computer platform composed of differentiated and distributed systems. In this paper, aiming at the heterogeneity and dynamism of a grid system, a novel fault-tolerant grid-scheduling model is presented based on Stochastic Petri Net. On the other hand, a new grid-scheduling strategy, the united strategy for the availability factor and expected accomplishing time (USAT), is put forward, In the end, the performance of the scheduling strategy based on the fault-tolerant grid-scheduling model is analyzed by SPNP software package. The numerical results show that USAT strategy can reduce these bad effects of dynamic and autonomic resources to some extent so as to guarantee quality of service (QoS).
16309496
Scaling to the end of silicon with EDGE architectures
Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, called explicit data graph execution (EDGE), that will match the characteristics of semiconductor technology over the next decade. The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
11960535
Performance Modeling of Grid Resource Management and Scheduling Systems
Performance evaluation of grid resource management and scheduling system is of key importance to the success of the grid. In this paper, we introduce a generalized stochastic Petri net (GSPN) model for such purpose. The model is simple with clarity and can be applied to other research issues on grid to provide them with performance evaluation capabilities.