18593367
Biosec: a biometric based approach for securing communication in wireless networks of biosensors implanted in the human body
Advances in microelectronics, material science and wireless technology have led to the development of sensors that can be used for accurate monitoring of inaccessible environments. Health monitoring, telemedicine, military and environmental monitoring are some of the applications where sensors can be used. The sensors implanted inside the human body to monitor parts of the body are called biosensors. These biosensors form a network and collectively monitor the health condition of their carrier or host. Health monitoring involves collection of data about vital body parameters from different parts of the body and making decisions based on it. This information is of personal nature and is required to be secured. Insecurity may also lead to dangerous consequences. Due to the extreme constraints of energy, memory and computation securing the communication among the biosensors is not a trivial problem. Key distribution is central to any security mechanism. In this paper we propose an approach wherein, biometrics derived from the body are used for securing the keying material. This method obviates the need for expensive computation and avoids unnecessary communication making our approach novel compared to existing approaches.
15600368
Dynamically adapting registration areas to user mobility and call patterns for efficient location management in PCS networks
In this paper, we propose an extension to the personal communication services (PCS) location management protocol which uses dynamically overlapped registration areas. The scheme is based on monitoring the aggregate mobility and call pattern of the users during each reconfiguration period and adapting to the mobility and call patterns by either expanding or shrinking registration areas at the end of each reconfiguration period. We analytically characterize the trade-off resulting from the inclusion or exclusion of a cell in a registration area in terms of expected change in aggregate database access cost and signaling overhead. This characterization is used to guide the registration area adaption in a manner in which the signaling and database access load on any given location register (LR) does not exceed a specified limit. Our simulation results show that it is useful to dynamically adapt the registration areas to the aggregate mobility and call patterns of the mobile units when the mobility pattern exhibits locality. For such mobility and call patterns, the proposed scheme can greatly reduce the average signaling and database access load on LRs. Further, the cost of adapting the registration areas is shown to be low in terms of memory and communication requirements.
2580676
Adaptive Distributed Dynamic Channel Allocation for Wireless Networks
Channel allocation schemes in a mobile computing (wireless) environment can be either static or dynamic. Static allocation offers negligible channel acquisition time and zero message complexity and works well at a low system load; the performance steadily decreases as system load increases since many calls are dropped. In the case of even temporary hot spots many calls may be dropped by a heavily loaded switching station even when there are enough idle channels in the interference region of that station. On the other hand, dynamic schemes provide better utilization of the channels at higher loads albeit at the cost of higher channel acquisition time and some additional control messages. Our purpose in the present paper is to propose a combined channel allocation scheme so that each switching station can tune to its own load independent of other stations in its interference region; the objective is to minimize the call drop rate and at the same time maintain a minimum average channel acquisition time and minimum control message complexity.
3266186
e3D: an energy-efficient routing algorithm for wireless sensor networks
One of the limitations of wireless sensor nodes is their inherent limited energy resource. Besides maximizing the lifetime of the sensor node, it is preferable to distribute the energy dissipated throughout the wireless sensor network in order to minimize maintenance and maximize overall system performance. Any communication protocol that involves synchronization of peer nodes incurs some overhead for setting up the communication. We introduce a new algorithm, e3D (energy-efficient distributed dynamic diffusion routing algorithm), and compare it to two other algorithms, namely directed, and random clustering communication. We take into account the setup costs and analyze the energy-efficiency and the useful lifetime of the system. We compare the algorithms in terms of system lifetime, power dissipation distribution, cost of synchronization, and simplicity of the algorithm. Our simulation results show that e3D performs comparable to its optimal counterpart while having significantly less overhead.
6130612
Cored-Based Tree with Forwarding Regions (CBT-FR); A Protocol for Reliable Multicasting in Mobile Ad Hoc Networks
In this paper we propose a new protocol for reliable multicast in a multihop mobile radio network. The protocol is reliable, i.e., it guarantees message delivery to all multicast nodes even when the topology of the network changes during multicasting. The proposed protocol uses a core-based shared tree. The multicast tree may get fragmented due to node movements. The notion of a forwarding region is introduced which is used to glue together fragments of multicast trees. The gluing process involves flooding the forwarding region of only those nodes that witness topology change due to node mobility. Delivery of multicast messages to mobile nodes is expedited through (i) pushing the message by witness nodes in their forwarding regions and (ii) pulling messages by a mobile node during (re)joining process. Hence, the protocol conserves network bandwidth by using a combination of the push?pull approach and by restricting flooding only to the essential parts of the network that are affected by topology change. We develop a theoretical model to compute the probability of packet loss (as a function of the mobility rate) for our proposed scheme compared to the the core-based tree protocol (CBT); we also evaluate the effectiveness of forwarding regions as compared to traditional flooding. Our analysis shows that the proposed scheme significantly outperforms CBT.
384064
Proximity based access control in smart-emergency departments
In this paper, we propose a proximity based automated access control (PBAC) model for smart-ED environments which improves the existing ED work-flow by automating mundane administrative procedure for secure information access, allowing caregivers to focus on the treatment of patients. The proposed access model builds on the traditional role-based access control model and extends it by including multiple authentication levels for preventing unauthorized access. We also provide a semi-formal specification for the PBAC model. We further validate it using ultra-wide-band (UWB) based prototype which was tested in ED
8584813
Generation of alternative feature-based models and precedence orderings for machining applications
Incre=ing global competition is challenging the U.S. manufacturing industry to bring competitively-priced, well-designed and well-manufactured products to market in a timely fashion. Since decisions made during the design stage can have significant effects on product cost, quality, and lead time, increasing research attention is being given to integrating engineering design and manufacturing, with a focus on design for manufacturability. Consider the task of designing and manufacturing machined parts. Often there can be several different ways to machine a part. Which way is best depends on several factors, including dimensions, tolerances, surface finishes, availability of machine tools and cutting tools, fixturability, and optimization criteria. Thus, to evaluate the manufacturability of the proposed design, we may need to consider more than one way to machine it. This paper outlines our approach for generating and evaluating alternative ways to machine a part. For additional details, see [1]; for other related work, see [2, 3].
15811522
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS-LFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is 1/dth that of the normal clock, which drives the normal-speed LFSR. The use of DS-LFSR reduces the frequency of transitions at the circuit inputs driven by the slow LFSR, leading to a reduction in switching activity during test application. A procedure is presented to design a DS-LFSR so as to achieve high fault coverage by ensuring that patterns generated by it are unique and uniformly distributed. A new gain function and a method to compute its value for each circuit input are proposed to select inputs to be driven by the slow LFSR. Also, a procedure to increase the number of inputs driven by the slow LFSR by combining compatible inputs is presented to further decrease the switching activity. Finally, DS-LFSRs are designed for the ISCAS85 and ISCAS89 benchmark circuits and shown to provide a 13% to 70% reduction in the numbers of load-capacitance weighted transitions with no loss of fault coverage (for stuck-at as well as transition delay faults) and at very slight area overheads.
1533259
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with little or no resource constraints but tight bounds on the cycle time. Extreme parallelization, conditional and speculative execution of operations is essential to meet the processor performance goals. However, this is a tedious task for which classical high-level synthesis (HLS) formulations are inadequate and thus rarely used. In this paper, we present a new methodology for application of HLS targeted to such microprocessor functional blocks that can potentially speed up the design space exploration for microprocessor designs. Our methodology consists of a coordinated set of source-level and fine-grain parallelizing compiler transformations that targets these behavioral descriptions, specifically loop constructs in them and enables efficient chaining of operations and high-level synthesis of the functional blocks. As a case study in understanding the complexity and challenges in the use of HLS, we walk the reader through the detailed design of an instruction length decoder drawn from the Pentium®-family of processors. The chief contribution of this paper is formulation of a domain-specific methodology for application of high-level synthesis techniques to a domain that rarely, if ever, finds use for it.
19051554
BIST test pattern generators for stuck-open and delay testing
Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs.<<ETX>>
1661451
Generating redesign suggestions to reduce setup cost: a step towards automated redesign
Abstract All mechanical designs pass through a series of formal and informal redesign steps, involving the analysis of functionality, manufacturability, cost and other life-cycle factors. The speed and efficacy of these steps has a major influence on the lead time of the product from conceptualization to launching. In this paper we propose a methodology for automatically generating redesign suggestions for reducing setup costs for machined parts. Given an interpretation of the design as a collection of machinable features, our approach is to generate alternate machining features by making geometric changes to the original features, and add them to the feature set of the original part to create an extended feature set. The designer may provide restrictions on the design indicating the type and extent of modifications allowed on certain faces and volumes, in which case all redesign suggestions generated by our approach honour those restrictions. By taking combinations of features from the extended feature set generated above, we can generate modified versions of the original design that still satisfy the designer's intent. By considering precedence constraints, we can estimate the setup time that will be required for each design. Any modified design whose setup time is less than that of the original design can be presented to the designer as a possible way to modify the original design.