10548039
Typed memory management via static capabilities
Region-based memory management is an alternative to standard tracing garbage collection that makes operation such as memory deallocation explicit but verifiably safe. In this article, we present a new compiler intermediate language, called the Capability Language (CL), that supports region-based memory management and enjoys a provably safe type systems. Unlike previous region-based type system, region lifetimes need not be lexically scoped, and yet the language may be checked for safety without complex analyses. Therefore, our type system may be deployed in settings such as extensible operating systems where both the performance and safety of untrusted code is important. The central novelty of the language is the use of static capabilities to specify the permissibility of various operations, such as memory access and deallocation. In order to ensure capabilities are relinquished properly, the type system tracks aliasing information using a form of bounded quantification. Moreover, unlike previous work on region-based type systems, the proof of soundness of our type system is relatively simple, employing only standard syntactic techniques. In order to show how our language may be used in practice, we show how to translate a variant of Tofte and Talpin's high-level type-and-effects system for region-based memory management into our language. When combined with known region inference algorithms, this translation provides a way to compile source-level languages to CL.
215896794
From system F to typed assembly language
We motivate the design of typed assembly language (TAL) and present a type-preserving ttranslation from Systemn F to TAL. The typed assembly language we pressent is based on a conventional RISC ass...
21446187
Is IDDQ Test of Microprocessors Feasible?
Quiescent leakage current (Iddq) test has proven very effective for detecting defects that escape other test methods, such as small delay faults or reliability hazards. However, leakage currents in microprocessors, digital signal processors, and graphics processors have risen to the point that these products no longer use Iddq test. Quality must be achieved through other test methods, often at higher development and application cost. We propose to bring Iddq  test back to high performance chips by using a practical built-in current sensor (BICS). 180 nm test chip results show that a small sensor can achieve a resolution of 54 muA, which is adequate to detect most small delay defects and reliability hazards
326056
A circuit level fault model for resistive bridges
Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.
1233075
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this work we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by injecting bridging faults into samples of a Streaming audio controller chip and comparing the predicted defect locations and layers with the actual values. The correct defect location and layer was predicted in all 9 samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.
1745513
Test generation for global delay faults
This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks.
17178263
Accurate fault modeling and fault simulation of resistive bridges
This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults.