15163719
Solving satisfiability in combinational circuits
As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
9436195
Satisfiability models and algorithms for circuit delay computation
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.
1798861
RAIL: code instrumentation for .NET
Code instrumentation is a mechanism that allows modules of programs to be completely rewritten at runtime. With the advent of virtual machines, this type of functionality is becoming more and more interesting because it allows the introduction of new functionality after an application has been deployed, easy implementation of aspect-oriented programming, performing security verifications, dynamic software upgrading, among others.
 The Runtime Assembly Instrumentation Library (RAIL) is one of the first frameworks to implement code instrumentation in the.NET platform. It specifically addresses the limitations that exist between the reflection capabilities of.NET and its code emission functionalities. RAIL gives the programmer an object-oriented vision of the code of an application, allowing assemblies, modules, classes, references and even intermediate code to be easily manipulated.
 This paper addresses the design of an implementation of RAIL along with the difficulties and lessons learnt in building a framework for code instrumentation in.NET.
21703134
Frequency-based Watermarking with Spatial Masking for DRM of MMS Content
Copyright enforcement is the major constraint to the development of mobile content distribution business. In this paper a low computational complexity watermarking scheme is presented. The algorithm exhibits resilience to the major expected attacks in the MMS context using a canonical insertion procedure in the Fourier domain. Watermark transparency is provided based on spatial texture masking through a constrained frequency perturbation maximization procedure. This watermarking scheme is the core protection mechanism of a Proxy-based DRM solution for MMS, currently under trial with a mobile operator.
16534842
Formal Verification of Component-Based Software Systems
In this work we present a methodology for formal modeling and verification of component based software systems. The methodology is based on software architecture, components, and reuse of Petri Nets models. With this process, we are contributing for the visual composition, verification, and formal validation of software. We also show an example of the application of this methodology into two different domains.
18641869
Checkpointing Distributed Shared Memory
Distributed shared memory (DSM) is a very promising programming model for exploiting the parallelism of distributed memory systems, because it provides a higher level of abstraction than simple message passing. Although the nodes of standard distributed systems exhibit high crash rates only very few DSM environments have some kind of support for fault-tolerance.In this article, we present a checkpointing mechanism for a DSM system that is efficient and portable. It offers some portability because it is built on top of MPI and uses only the services offered by MPI and a POSIX compliant local file system.As far as we know, this is the first real implementation of such a scheme for DSM. Along with the description of the algorithm we present experimental results obtained in a cluster of workstations. We hope that our research shows that efficient, transparent and portable checkpointing is viable for DSM systems.
14564941
PetroGrapher: managing petrographic data and knowledge using an intelligent database application
This paper describes the PetroGrapher system, an intelligent database application to support petrographic analysis, interpretation of oil reservoir rocks, and management of relevant data using resources from both knowledge-based system technology and database technology. In this project, the visual tacit knowledge applied in petrographic analysis was rendered explicit through the collection of cases (rock descriptions), which were then used in the development of a domain ontology organized in a partonomy. Expert-level basic features, which we call ‘visual chunks’, were identified. The cases were further compared against the ontology to elucidate the relations between features in descriptions of rocks, visual chunks and expert interpretations. The domain knowledge was represented through a set of frames and knowledge graphs. The knowledge graphs are applied to recognize the visual chunks in the user data and retrieved the related interpretation. The system was developed as a structure tightly coupled with a relational database system, which acts as a repository for the knowledge base and the user data, and an object-oriented component, which preserves the semantics of data and develops inferences. The system was validated by three groups of users with different levels of expertise. q 2003 Elsevier Ltd. All rights reserved.