1145290
Hamilton cycles in regular 3-connected graphs
Abstract We show in this paper that for k ⩾63, every 3-connected, k -regular simple graph on at most 22 7 k vertices is hamiltonian.
38249565
An extreme problem concerning k-arc-cyclic property for a class of tournaments
B. Alspach has proved that a regular tournament is arc-pancyclic. Zhu and Tian proved that if a tournament T = (V, A) with vertex set V, arc set A and order p satisfies that for any arc (vi, vj) of T, if d+(vj)+d-(vi)⩾p−2, then T is arc-pancyclic, where p⩾7. In this paper we study an extreme problem concerning the k-arc-cyclic property for a class of tournaments. 
 
We say that a tournament T=(V, A) satisfies the condition O(p, q) if d+(v)+d-(u)⩾p−q for any arc (u, v) of T, where q is a positive integer and |V|=p. Zhu, Tian, Chen and Zhang proved that if a tournament T satisfies the condition O(p, q) and p⩾3q+3, then T is arc-pancyclic. Let S(p, q) be the set{T=(V, A): T is a tournament with p vertices and T satisfies the condition O(p, q)}; let Ck(u, v) be the set {cycles of T with length k using the arc (u, v)}. The aim of this paper is that for a given integer q, we can find an integer m(q, k) such that if p⩾m(q, k), then for any T ϵ S(p, q), T is k-arc-cyclic; if p⩽m(q, k)−1, then there exists T ϵ S(p, q) such that T is not k-arc-cyclic. We have found that m(q, 4)=5q−7, and m(q, 5)=⌊p∗(q)⌋+1 or ⌈p∗(q)⌉+1, where p∗(q)=(1+312)q−(1+43·3 12).
43360105
Factorizations of regular graphs
Let G be a k-regular graph of order 2n such that k≥n. Hilton (J. Graph Theory, 9 (1985), 193–196) proved that G contains at least ⌊k3⌋ edge-disjoint 1-factors. Hilton's theorem is improved in this paper that G contains at least ⌊k2⌋ edge-disjoint 1-factors. The following result is also proved in this paper: Let G be a 2-connected, k-regular, non-bipartite graph of order at most 3k − 3 and x, y be a pair of distinct vertices. If Gβ {x, y} is connected, then G contains an (x, y)-Hamilton path.
8902892
Dynamic Load Balancing for I/O- and Memory-Intensive Workload in clusters Using a Feedback Control Mechanism
One common assumption of the existing models of load balancing is that the weights of resources and I/O buffer size are statically configured. Though the static configuration of these parameters performs well in a cluster where the workload can be predicted, its performance is poor in dynamic systems where the workload is unknown. In this paper, a new feedback control mechanism is proposed to improve the overall performance of a cluster with I/O-intensive and memory-intensive workload. The mechanism dynamically adjusts the resource weights as well as the I/O buffer size. Results from a trace-driven simulation show that this mechanism is effective in enhancing the performance of a number of existing load-balancing schemes.
27779170
Study of Dempster-Shafer theory for image segmentation applications
Abstract This paper addresses a new knowledge model using the Dempster–Shafer's theory of evidence for image segmentation and fusion. The salient aspects of the proposed method are at two levels. Firstly, mass distributions in Dempster–Shafer theory are directly derived from image histograms. Secondly, the fusion process does not start from one single frame of discernment, as it was done in most of the previously reported works, but does start from first defining two independent frames of discernment associated with the two images to be fused, and then combining them for forming a new frame of discernment. The strategy used to define mass distributions in the combined framework is discussed in detail. The proposed fusion method is illustrated in the context of image segmentation. The obtained results show the robustness of the method.
35564489
Accelerated 2D Image Processing on GPUs
Graphics processing units (GPUs) in recent years have evolved to become powerful, programmable vector processing units. Furthermore, the maximum processing power of current generation GPUs is roughly four times that of current generation CPUs (central processing units), and that power is doubling approximately every nine months, about twice the rate of Moore's law. This research examines the GPU's advantage at performing convolutionbased image processing tasks compared to the CPU. Straight-forward 2D convolutions show up to a 130:1 speedup on the GPU over the CPU, with an average speedup in our tests of 59:1. Over convolutions performed with the highly optimized FFTW routines on the CPU, the GPU showed an average speedup of 18:1 for filter kernel sizes from 3x3 to 29x29.
179733
Exploiting redundancy to boost performance in a RAID-10 style cluster-based file system
While aggregating the throughput of existing disks on cluster nodes is a cost-effective approach to alleviate the I/O bottleneck in cluster computing, this approach suffers from potential performance degradations due to contentions for shared resources on the same node between storage data processing and user task computation. This paper proposes to judiciously utilize the storage redundancy in the form of mirroring existed in a RAID-10 style file system to alleviate this performance degradation. More specifically, a heuristic scheduling algorithm is developed, motivated from the observations of a simple cluster configuration, to spatially schedule write operations on the nodes with less load among each mirroring pair. The duplication of modified data to the mirroring nodes is performed asynchronously in the background. The read performance is improved by two techniques: doubling the degree of parallelism and hot-spot skipping. A synthetic benchmark is used to evaluate these algorithms in a real cluster environment and the proposed algorithms are shown to be very effective in performance enhancement.
1253650
A reconfigurable, multi-gigahertz pulse shaping circuit based on distributed transversal filters
A distributed transversal filter (DTF) is a good candidate for ultrafast pulse shaping in wideband systems like UWB. This paper presents the circuit analysis of DTFs based on transmission line theory. We also show the detailed design procedure of DTFs. A 5-tap prototype DTF is designed and fabricated using microwave PCB substrate and pHEMT discrete transistors. Simulation and initial measurement results demonstrate its pulse shaping capability