44855762
Optimizing floating point operations in Scheme
It is well known that dynamic typing in languages like Lisp is costly in terms of performance. Besides the cost of tag checking, the other major source of inefficiency comes from the need to place and retrieve data from dynamically allocated objects, i.e. boxing and unboxing. This makes it unacceptable in general to write numerical code in Lisp. Such programs involve ''tight'' loops in which boxing, unboxing and tag checking will dominate the computation time. With advances in the compilation of Lisp programs, it has been suggested that type checking and inference can be used to alleviate the problem. In this paper we shall examine a sub-problem, namely using type inference to aid compilation of numerical intensive Lisp code. A type inference algorithm for floating point operations will be described. This has been implemented in a Scheme compiler. Implementation issues and performance results on fairly large numerical code will also be reported. The results suggest that significant performance gains can be obtained. It is our hope that as an augmentation to other general type inferencing scheme, it will contribute towards the realization of highly optimizing Scheme compilers.
15634785
The performance model of SilkRoad - a multithreaded DSM system for clusters
Distributed Shared Memory (DSM) is a highly desirable programming model for cluster based computing. Even though a number of software DSMs have been developed with their performance evaluated, few of them have a theoretical performance model. In this paper, we propose and analyze the performance model of the software DSM of SilkRoad,, a multithreaded runtime system for cluster computing. SilkRoad is built on the Cilk system with an extended memory consistency model which we call RC/sub dag/ consistency: Extending Cilk's theoretical performance model, we show that with the RC/sub dag/ consistent DSM, the expected execution.time T/sub P/ of a partially strict multithreaded computation on P processors is O((T/sub 1/(Z, L) + N)/P + /spl mu/HT/sub /spl infin//), where T/sub 1/(Z, L) is the total work of computation, T/sub /spl infin// is the critical path, N is the number of lock acquisitions, /spl mu/ is the service time of a cache miss, and H is the height of memory: Finally, we present experimental evidence that verify the performance model.
18143878
Compiling Parallel Lisp for a Shared Memory Multiprocessor
There is a commonly held idea that although Lisp is a good language for prototyping and software development, it is often too inefcient to be useful in actual implementation. Advances in compiling Lisp have begun to change this notion. However, the situation is less clear in the case of parallel Lisp dialects. In this paper, we report on our experience in implementing a compiler for a parallel Lisp dialect we called BaLinda Lisp for a shared memory multiprocessor. For a class of problems, our compiler was able to achieve performances on Lisp programs that are near, if not equal to, their imperative (C) equivalents. However, on other problems, the situation is less than ideal. We investigate this phenomenum and outline the future challenges in realizing a production strength parallel Lisp compiler.
9691799
Targeted Data Prefetching
Given the increasing gap between processors and memory, prefetching data into cache becomes an important strategy for preventing the processor from being starved of data. The success of any data prefetching scheme depends on three factors: timeliness, accuracy and overhead. In most hardware prefetching mechanism, the focus has been on accuracy – ensuring that the predicted address do turn out to be demanded in a later part of the code. In this paper, we introduce a simple hardware prefetching mechanism that targets delinquent loads, i.e. loads that account for a large proportion of the load misses in an application. Our results show that our prefetch strategy can reduce up to 45% of stall cycles of benchmarks running on a simulated out-of-order superscalar processor with an overhead of 0.0005 prefetch per CPU cycle.
3457072
Using UML 2.0 for system level design of real time SoC platforms for stream processing
While enabling fast implementation and reconfiguration of stream applications, programmable stream processors expose issues of incompatibility and lack of adoption in existing stream modeling languages. To address them we describe a design approach in which specifications are captured in UML 2.0, and automatically translated into SystemC models consisting of simulators and synthesizable code under proper style constraints. As an application case, we explain real time stream processor specifications using new UML 2.0 notations. Then we expound how our translator generates SystemC models and includes additional hardware details. Verifications are made during UML execution as well as assertions in SystemC. The case study demonstrates the feasibility of fast specifications, modifications and generation of real time stream processor designs.
1841047
Design and Implementation of Abstract Machine for Parallel Lisp Compilation
8251892
Optimal Reinsertion: A New Search Operator for Accelerated and More Accurate Bayesian Network Structure Learning
We show how a conceptually simple search operator called Optimal Reinsertion can be applied to learning Bayesian Network structure from data. On each step we pick a node called the target. We delete all arcs entering or exiting the target. We then find, subject to some constraints, the globally optimal combination of in-arcs and out-arcs with which to reinsert it. The heart of the paper is a new algorithm called ORSearch which allows each optimal reinsertion step to be computed efficiently on large datasets. Our empirical results compare Optimal Reinsertion against a highly tuned implementation of multirestart hill climbing. The results typically show one to two orders of magnitude speed-up on a variety of datasets. They usually show better final results, both in terms of BDEU score and in modeling of future data drawn from the same distribution.
42032352
Static and dynamic distance metrics for feature-based code analysis
In this paper we present metrics to determine the distance between the features of a software system. Such a measurement can elucidate how features of the system being examined are close to each other. We first use an execution slice-based technique to identify a set of code (basic blocks in our case) that is used to implement each feature. Then, depending on whether the execution frequency of each block is considered during the construction of such sets of code, a static as well as a dynamic distance is computed for each pair of features. These two types of distance differ in that the former computes the distance between two features only by how these features are implemented in the system, while the latter also takes into account how each feature is executed based on a user's operational profile. In other words, the static distance quantitatively gives the closeness of two features from the system implementation point of view, whereas the dynamic distance presents such closeness from the users' execution point of view. To illustrate the use of our metrics, we report a case study on a Symbolic Hierarchical Automated Reliability and Performance Evaluator (SHARPE). The results of our study suggest that the distance metrics discussed in this paper can provide a good measurement, in a quantitative way, of how close two program features are. Such information can also serve as a good start to understanding how a modification made to one feature is likely to affect other features.
1444557
Conditional entropy coding of VQ indexes for image compression
Block sizes of practical vector quantization (VQ) image coders are not large enough to exploit all high-order statistical dependencies among pixels. Therefore, adaptive entropy coding of VQ indexes via statistical context modeling can significantly reduce the bit rate of VQ coders for given distortion. Address VQ was a pioneer work in this direction. In this paper we develop a framework of conditional entropy coding of VQ indexes (CECOVI) based on a simple Bayesian-type method of estimating probabilities conditioned on causal contexts, CECOVI is conceptually cleaner and algorithmically more efficient than address VQ, with address-VQ technique being its special case. It reduces the bit rate of address VQ by more than 20% for the same distortion, and does so at only a tiny fraction of address VQ's computational cost.
7323513
Coverage Testing Embedded Software on Symbian/OMAP
5666480
An integrated solution for testing and analyzing Java applications in an industrial setting
Testing a large-scale, real-life commercial software application is a very challenging task due to the constant changes in the software, the involvement of multiple programmers and testers, and a large amount of code. Integrating testing with development can help find program bugs at an earlier stage and hence reduce the overall cost. In this paper, we report our experience on how to apply eXVantage (a tool suite for code coverage testing, debugging, performance profiling, etc.) to a large, complex Java application at the implementation and unit testing phases in Avaya. Our results suggest that programmers and testers can benefit from using eXVantage to monitor the testing process, gain confidence on the quality of their software, detect bugs which are otherwise difficult to reveal, and identify performance bottlenecks in terms of which part of code is most frequently executed.