467375
Profile-guided microarchitectural floor planning for deep submicron processor design
As very large scale integration (VLSI) process technology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a single cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic communication patterns of applications. This article, using the profile information acquired at the microarchitecture level, proposes a "profile-guided microarchitectural floor planner" that considers both the impact of wire delay and the architectural behavior, namely, the intermodule communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on the simulation results here, the proposed profile-guided method shows a 5%-40% average instructions per cycle (IPC) improvement when the clock frequency is fixed. From the perspective of instruction throughput in billion instructions per second (BIPS), the floor planner is much more scalable than the conventional wirelength-based floor planner
19776539
Stack value file: custom microarchitecture for the stack
As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack regions. Each of these designs can improve performance by constructing two separate structures which can be probed in parallel while reducing contention. In this paper, we propose a new memory organization that partitions data references into stack and nonstack regions. Non-stack references are routed to a conventional cache. Stack references, on the other hand, are shown to have several characteristics that can be leveraged to improve performance using a less conventional storage organization. This paper enumerates those characteristics and proposes a new microarchitectural feature, the stack value file (SVF), which exploits them to improve instruction-level parallelism, reduce stack access latencies, reduce demand on the first-level cache, and reduce data bus traffic. Our results show that the SVF can improve execution performance by 29 to 65% while reducing overhead traffic for the stack region by many orders of magnitude over cache structures of the same size.
19026342
Eager writeback - a technique for improving bandwidth utilization
Modern high-performance processors utilize multi-level cache structures to help tolerate the increasing latency of main memory. Most of these caches employ either a writeback or a write-through strategy to deal with store operations. Write-through caches propagate data to more distant memory levels at the time each store occurs, which requires a very large bandwidth between the memory hierarchy levels. Writeback caches can significantly reduce the bandwidth requirements between caches and memory by marking cache lines as dirty when stores are processed and writing those lines to the memory system only when that dirty line is evicted. Unfortunately, for applications that experience significant numbers of cache misses due to streaming data, writeback cache designs can degrade overall system performance by clustering bus activity when dirty lines contend with data being fetched into the cache. In this paper we present a new technique called Eager Writeback, which re-distributes and balances memory traffic by writing and "cleaning" dirty cache lines prior to their eviction. Eager Writeback can be viewed as a compromise between write-through and writeback policies, in which dirty lines are written later than write-through, but prior to writeback. We will show that this approach can reduce the large number of writes seen in a write-through design, while avoiding the performance degradation caused by clustering bus traffic in a writeback approach.
15007668
Wakeup scheduling in wireless sensor networks
A large number of ractical sensing and actuating applications require immediate notification of rare but urgent events and also fast delivery of time sensitive actuation commands. In this a er,we consider the design of efficient wakeup scheduling schemes for energy constrained sensor nodes that adhere to the bidirectional end-to-end delay constraints posed by such applications. We evaluate several existing scheduling schemes and propose novel scheduling methods that outperform existing ones.We also resent a new family of wakeu methods,called multi-parent schemes, which take a cross-layer a roach where multiple routes for transfer of messages and wakeup schedules for various nodes are crafted in synergy to increase longevity while reducing message delivery latencies. We analyze the power-delay and lifetime-latency tradeoffs for several wakeup methods and show that our proposed techniques significantly improve the performance and allow for much longer network lifetime while satisfying the latency constraints.
17910425
TMO-structured distributed location information system prototype
To realize location-based services, it is essential to handle the extreme situation that must cope with a very large volume, at least millions, of moving items. In this paper, we describe a location information system prototype of GALIS, which is a cluster-based scalable distributed computing system architecture which consists of multiple data processors, each dedicated to keeping records relevant to a different geographical zone and a different time zone. The proposed system contains all of the major computing nodes of GALIS architecture and is developed as a middleware on top of commercial main-memory database engines and spatial database engines, for short-term data and long-term data processing, respectively. To show the usefulness of our system, some experimental results showing clear advantages of distributed computing are also explained.
671835
Algorithm for Reducing the Complexity of Switching Time in Real-Time Multitask Environments
16122349
Feature-Based Image Watermarking Method Using Scale-Invariant Keypoints
This paper addresses feature-based image watermarking methods for digital contents. Most previous watermarking algorithms suffer from geometric distortion attacks that desynchronize the location of the inserted watermark. In order to synchronize the watermark location, watermark synchronization should be performed. One solution for watermark synchronization is to use image features. This paper describes a feature-based watermarking method based on scale-invariant keypoints. We extract feature points from the scale-invariant keypoint extractor and then decompose feature points into a set of disjoint triangles. These triangles are watermarked by an additive spread-spectrum method on the spatial domain. We perform an intensive simulation in comparison with other feature-based watermarking methods using 100 test images. Results show that the proposed method is considerably robust against both geometric distortion attacks and signal processing attacks listed in Stirmark 3.1.
7431488
An HMM-Based Threshold Model Approach for Gesture Recognition
A new method is developed using the hidden Markov model (HMM) based technique. To handle nongesture patterns, we introduce the concept of a threshold model that calculates the likelihood threshold of an input pattern and provides a confirmation mechanism for the provisionally matched gesture patterns. The threshold model is a weak model for all trained gestures in the sense that its likelihood is smaller than that of the dedicated gesture model for a given gesture. Consequently, the likelihood can be used as an adaptive threshold for selecting proper gesture model. It has, however, a large number of states and needs to be reduced because the threshold model is constructed by collecting the states of all gesture models in the system. To overcome this problem, the states with similar probability distributions are merged, utilizing the relative entropy measure. Experimental results show that the proposed method can successfully extract trained gestures from continuous hand motion with 93.14% reliability.