43480564
PLS: a scheduler for pipeline synthesis
The authors point out that pipelining is an effective method for optimizing the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. Although throughput and turnaround time are two important optimization criteria, previous work emphasized mainly the throughput. It is shown that the delay time for executing an iteration of a loop has a strong relationship to the cost of the registers and the controller. By minimizing the delay, there is more silicon area to allocate to additional resources, which in turn increases throughput. Forward scheduling and a backward scheduling are iteratively used to achieve this purpose. The algorithm, called PipeLining Scheduler or PLS, can be used to pipeline a loop with or without loop-carried dependencies. Real examples are used to illustrate the method. Experiments on benchmark examples show that considerable improvement over previous approaches is attained. >
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
18483873
Modeling Frequently Accessed Wireless Data With Weak Consistency
To reduce the response times of wireless data access in a mobile network, caches are utilized in wireless handheld devices. If the original data entry has been updated, the cached data in the handheld device becomes stale. Thus, a mechanism is required to predict when the cached copy will expire. This paper studies a weakly consistent data access mechanism that computes the time-to-live (TTL) interval to predict the expiration time. We propose an analytic model to investigate this TTL-based algorithm for frequently accessed data. The analytic model is validated against simulation experiments. Our study quantitatively indicates how the TTL-based algorithm reduces the wireless communication cost by increasing the probability of stale accesses. Depending on the requirements of the application, appropriate parameter values can be selected based on the guidelines provided in this paper.
1571256
Parallelism analyzers for parallel discrete event simulation
Discrete event simulation is usually time consuming. Recently, there has been a great deal of interest in using parallel computers to speed up the simulation process. Before the parallel simulation approach is applied, it is important to understand the inherent parallelism of simulation applications. A simple technique called critical path analysis was proposed to study paralllelism of simulation applications. This paper describes three critical path analysis algorithms based on different event-scheduling (process scheduling) policies. These algorithms are much simpler than a previous approach, where the events must be recorded in a trace and an extra pass is required to process the event trace. In our approach, the critical path analysis algorithms are integrated with the sequential simulation. At the end of the sequential simulation, the optimal parallel execution time is also computed. Livny proposed an algorithm similar to our approach (His, however, was designed for a specific language). Our algorithms can be integrated with sequential simulation programs written by users or be integrated with simulation languages. Another advantage of our algorithms over previous approaches is that ours can be used to study load balancing under different event-scheduling policies. Since our algorithms can be easily inserted in sequential simulation programs, critical path analysis can be applied to existing sequential programs without difficulty. The results can then be used to predict the performance of parallel simulation on similar applications. An example is given to show how useful information can be obtained from our algorithms.
9314572
Demand re‐registration for PCS database restoration
In a Personal Communications Services (PCS) network, mobility databases such as Home Location Register (HLR) and Visitor Location Register (VLR) are utilized to support mobility management for Mobile Stations (MSs). If the location databases fail, the location information loss or corruption will seriously degrade the service offered to the subscribers. In this paper, we propose a new VLR failure recovery scheme called demand re‐registration. In this scheme, the VLR broadcasts a re‐registration request to all MSs after the VLR failure. When an MS receives the re‐registration request, it sends a registration message to the VLR to recover the location record. Since all MSs will re‐register after receiving the broadcasting request, traffic jam (and thus collisions) may occur. If a collision occurs, then the involved MSs must re‐send the registration messages. This paper studies the performance of demand re‐registration by investigating how effectively the re‐registration can recover the location record for an MS before the first MS call termination occurs. Our results indicate that demand re‐registration can effectively recover VLR failure.
31678954
Exposing Phylogenetic Relationships by Genome Rearrangement
Abstract Evolutionary studies based on large-scale rearrangement operations, as opposed to the traditional approaches on point mutations, have been considered as a promising alternative for inferring the evolutionary history of species. Genome rearrangement problems lead to combinatorial puzzles of finding parsimonious scenarios towards measuring what difference species have and explaining how a species evolves from another. Throughout this chapter, we will focus on the introduction of computing the genomic distance, arising from the effects of a set of rearrangement events, between a pair of genomes. In the end, two experiments on Campanulaceae and Proteobacteria are used to simply show how to exploit the genome rearrangement approach for exposing phylogenetic relationships.
18189663
Reducing location update cost in a PCS network
Location tracking operations in a personal communications services (PCSs) network are expensive. Several strategies have been proposed to reduce the location update cost. This paper studies a special case of a location tracking algorithm called the alternative location algorithm. This special case is referred to as the two location algorithm (TLA). An analytical model is proposed to compare the performance of the TLA and the IS-41 protocol. Our study indicates that the performance of the TLA is significantly affected by the user moving patterns and the call traffic. If the user mobility is higher than the call frequency or the user tends to move back to the previously visited registration areas, then the TLA may significantly outperform IS-41. We also observe that the variance of the portable residence times in registration areas has an impact on the performance of the TLA (i.e., better performance is expected for larger variance).