26391037
Adaptive Checkpointing and Rollback in Multiprocessor Systems
16106791
A microprocessor-controlled asynchronous circuit switching network
This paper describes an asynchronous circuit switching network for multiple-processor systems. Several circuit switching networks for various applications have been proposed and constructed. However, there are problems associated with these networks. The asynchronous circuit switching network possesses several features that can solve these problems. A three-stage fully connected topology is utilized to construct the network. Each switching element is functionally and physically identical and this facilitates a cost-effective LSI implementation and software development. The control structure of the switching element and the routing algorithm are re-organized to fit the asynchronous operation. The network takes advantage of low-cost microcomputers to do the distributed routing control and to implement the communication protocols. The graceful degradation characteristic in the network is provided by independent multiple paths existing between any pair of the source and the destination. A network monitor is incorporated to facilitate an adaptive routing strategy and to have the fault diagnostic capability. Three alternatives for the switching element implementation are described to demonstrate the hardware and software tradeoffs.
15881866
Performance analysis of circuit switching, baseline interconnection networks
Performance evaluation, using both analytical and simulation models, of circuit switching baseline networks is presented. Two configurations of the baseline networks, single and dual, are evaluated. In each configuration, two different conflict resolution strategies, drop and hold, are tried to see the performance difference. Our analytical models are based on a more realistic assumption. New analyses are given and are verified by simulation results. In single network configuration, it is shown that the drop strategy is better than the hold strategy in the case that the data transfer time is longer than 10 cycles under a high request rate. In the dual network configuration, five different communication strategies are investigated and the optimum performance level is shown to be dependent on the length of the data transfer time.
19123449
Operating System Kernel for a Reconfigurable Multiprocessor System
27793990
Fail Safe Distributed Fault Diagnosis of Multiprocessor Systems
19852972
Distributed Instruction Set Computer Architecture
The Distributed Instruction Set Computer Architecture (DISC) is proposed as a fine-grained multiprocessing computer architecture. DISC uses a parallel instruction set and a distributed control mechanism to explore fine-grained, parallel processing in a multiple-functional-unit system. Multiple instructions are executed in parallel and/or out of order at the highest speed of n instructions/cycle, where n is the number of functional units. Based on this architecture, a hardware system is developed. Extensive studies were conducted on a behavioral DISC system model to investigate the performance level, the effect of program sizes, and the hardware utilization. Simulation showed that a DISC system incorporating 16 functional units can run 7.7 times faster than a single-functional-unit DISC system. >
38476421
Design Trade-offs for Process Scheduling in Tightly Coupled Multiprocessor Systems
7629632
Speech content authentication integrated with CELP speech decoders
A speech content authentication scheme, which is integrated with CELP speech coders to minimize the total computational cost is proposed in this research. Speech features relevant to semantic meaning are extracted, encrypted and attached as the header information. A low cost synchronization algorithm is used to resolve mis-synchronization caused by content preserving operations. Silent and tonal regions in the speech are identified with algorithms of low complexity to enhance the precision of integrity verification. This scheme is not only much faster than traditional cryptographic bitstream integrity algorithms, but also more compatible for a variety of applications. Experimental results are collected by using the GSM-AMR speech coder, and statistical analysis is performed to calculate the false positive rate of tamper detection.
206015400
Genetic-algorithm-based real-time task scheduling with multiple goals
This paper presents and evaluates a new method for real-time task scheduling in multiprocessor systems. Its objectives are to minimize the number of processors required and the total tardiness of tasks. The minimization is carried out through a multiobjective genetic algorithm (GA), because the problem has non-commensurable and competing objectives to be optimized. The experimental results showed that when compared to five methods used previously, such as list-scheduling algorithms and a specific GA, the performance of our algorithm was comparable or better for 178 out of 180 randomly generated task graphs. Also shown is the impact of the sparsity of a task graph on the performance of our algorithm.
7582647
On self-similarity and hamiltonicity of dual-cubes
The dual-cube is a newly proposed topology for interconnection networks, which uses low dimensional hypercubes as building blocks. The primary advantages of the dual-cube over the hypercube are that, with the same node degree n, the dual-cube contains 2/sup n-1/ times more nodes than the hypercube and, with the same amount of nodes, the dual-cube has approximately 50% less links than the hypercube. This paper was focused on the investigations of the structural self-similarity and the Hamiltonian property of the dual-cube. It was shown that a dual-cube can be recursively constructed from lower dimensional dual-cubes and, conversely, a dual-cube can be recursively decomposed into lower dimensional dual-cubes. It was also proved that all dual-cubes are Hamiltonian. There exist multiple Hamiltonian cycles on a dual-cube, among which, [(n-1)/2] cycles are edge-disjoint. It was illustrated that rings and linear arrays can be effectively emulated on dual-cubes. Some strategies for track sharing in efficient VLSI layout design were also discussed.
3236118
Human performance modeling in temporary segmentation Chinese character handwriting recognizers
Human performance in Chinese character handwriting recognizers is critical to the satisfaction and acceptance of their users. Based on Teal's [CHI'92 (1992) p. 295] interactive model, a static model describing the independent factors in determining the task completion time was set up with a simple mathematical inference; in addition, a dynamic model describing these factors' direct and indirect causal relationship was established by the path analytic method. Results in Experiment 1 indicated that both the static model and the dynamic model could fit observed task completion time satisfactorily with minor modifications. In addition, with users' average writing time around 1500 ms for each frequently used character, it was found that the user's performance was impaired significantly when segmentation time was longer than 1040 ms. An integrated model was devised after combining the static and dynamic models. Experiment 2 testified the integrated model in another handwriting recognizer and found that it could still fit human performance data with users in three different training conditions. Implications of the integrated model are that: (1) when recognition accuracy and number of inputting characters are constant, the weights of average writing time for each character, segmentation time, recognition time in determining task completion time are equal but bigger than the weight of the repairing time; (2) when the repairing time, average writing time for each character, segmentation time and recognition time are constant, there is an inverse model between task completion time and recognition accuracy; when recognition accuracy is from 50% to 93%, every 1% increase of recognition accuracy will reduce task completion time from 1989 to 1915 ms; when recognition accuracy increases from 94% to 100%, every 1% increase of recognition accuracy will reduce task completion time from 1895 to 1392 ms. Guidelines in designing these recognizers were given based on these implications.