16360248
Exploiting software pipelining for network-on-chip architectures
Recent developments in process technology have made it possible to produce chips consisting of a large number of processing elements. For factors such as scalability, performance, power-efficiency, the interconnection structure supporting such a chip needs to be an on-chip network architecture rather than a conventional bus-based system. Recent research has studied such network-on-chip (NoC) based systems from the performance and throughput, power/energy, reliability, predictability, synchronization, and concurrency perspectives. However, most of these studies are hardware based and it is not clear what type of compiler support would be best suited for these NoC based systems. Focusing on a mesh based NoC architecture that connects multiple processor cores, this paper explores the effectiveness of voltage/frequency scaling for processors and communication links with and without software pipelining, a compiler optimization for increasing parallelism. To our knowledge, this is the first paper that explores the influence of software pipelining in the context of the embedded NoC architectures
11193384
Compiler-directed voltage scaling on communication links for reducing power consumption
Reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. Most of the prior efforts on network power optimization are hardware-based schemes. These schemes are predictive by definition as they control communication link status based on the observations made In the past. Since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. This paper proposes a compiler driven approach to communication link voltage management. In this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. This information along with network topology is used for identifying the link access patterns. These patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. Our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. We exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which In turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.
6208153
Maximizing data reuse for minimizing memory space requirements and execution cycles
Embedded systems in the form of vehicles and mobile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints. Therefore, their performance demands must be balanced very well against their memory space requirements and power consumption. Automatic tools that can optimize for memory space utilization and performance are expected to be increasingly important in the future as increasingly larger portions of embedded designs are being implemented in software. In this paper, we describe a novel optimization framework that can be used in two different ways: (i) deciding a suitable on-chip memory capacity for a given code, and (ii) restructuring the application code to make better use of the available on-chip memory space. While prior proposals have addressed these two questions, the solutions proposed in this paper are very aggressive in extracting and exploiting all data reuse in the application code, restricted only by inherent data dependences
2691860
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this paper is to study the challenges for L2 design and management in 3D chip multiprocessors. Our first contribution is to propose a router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory. Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections. In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration. This also helps reduce power consumption in L2 due to a reduced number of data movements
11226444
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over complex single core based systems, compilation issues for these architectures have relatively received less attention. Programming MPSOCs can be challenging as several potentially conflicting issues such as data locality, parallelism and load balance across processors should be considered simultaneously. Most of the compilation techniques discussed in the literature for parallel architectures (not necessarily for MPSOCs) are loop based, i.e., they consider each loop nest in isolation. However, one key problem associated with such loop based techniques is that they fail to capture the interactions between the different loop nests in the application. This paper takes a more global approach to the problem and proposes a compiler-driven data locality optimization strategy in the context of embedded MPSOCs. An important characteristic of the proposed approach is that, in deciding the workloads of the processors (i.e., in parallelizing the application) it considers all the loop nests in the application simultaneously. The authors' experimental evaluation with eight embedded applications showed that the global scheme brings significant power/performance benefits over the conventional loop based scheme.
13941129
Compiler-directed thermal management for VLIW functional units
As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.
8583268
Proportional degradation services in wireless/mobile adaptive multimedia networks
Adaptive multimedia services are very attractive since resources in wireless/mobile networks are relatively scarce and widely variable, and more importantly the resource fluctuation caused by mobility and channel fading can be mitigated using adaptive services. Therefore, there are extensive research activities on Quality of Service (QoS), call admission control, as well as bandwidth degradation and adaptation for adaptive multimedia services in wireless/mobile networks in recent years. However, fairness of bandwidth degradation has largely been ignored in previous work and remains an important issue in adaptive multimedia service provisioning. In this paper, we propose and study proportional degradation service provisioning in wireless/mobile networks that offer multiple classes of adaptive multimedia services. The proposed proportional degradation fairness model guarantees the proportional bandwidth degradation among different classes of services. Two proportional degradation scenarios are studied in this paper. In the first scenario, we study the proportional degradation provisioning with two QoS parameters for adaptive multimedia: the degradation ratio (DR) and the degradation degree (DD). In the second scenario, we study the proportional degradation provisioning with a new QoS parameter for adaptive multimedia: the degradation area (DA). For each scenario, based on the QoS parameters, proportional degradation adaptation algorithms are proposed to approximate the proportional degradation model, to fairly adapt calls' degradations, to utilize the system resource efficiently, as well as to optimize QoS parameters. Performance studies show that in the first scenario, proportional DR has been achieved very well, whereas proportional DD has not been well achieved. In other words, DR outperforms DD in terms of proportional degradation. In the second scenario, proportional DA has been well achieved. Furthermore, bandwidth resources have been efficiently utilized and DA has been minimized. Copyright © 2004 John Wiley & Sons, Ltd.
10555290
From Lasso regression to Feature vector machine
Lasso regression tends to assign zero weights to most irrelevant or redundant features, and hence is a promising technique for feature selection. Its limitation, however, is that it only offers solutions to linear models. Kernel machines with feature scaling techniques have been studied for feature selection with non-linear models. However, such approaches require to solve hard non-convex optimization problems. This paper proposes a new approach named the Feature Vector Machine (FVM). It reformulates the standard Lasso regression into a form isomorphic to SVM, and this form can be easily extended for feature selection with non-linear models by introducing kernels defined on feature vectors. FVM generates sparse solutions in the nonlinear feature space and it is much more tractable compared to feature scaling kernel machines. Our experiments with FVM on simulated data show encouraging results in identifying the small number of dominating features that are non-linearly correlated to the response, a task the standard Lasso fails to complete.
11851203
Locally Divergence-Free Discontinuous Galerkin Methods for MHD Equations
In this paper, we continue our investigation of the locally divergence-free discontinuous Galerkin method, originally developed for the linear Maxwell equations (J. Comput. Phys. 194 588–610 (2004)), to solve the nonlinear ideal magnetohydrodynamics (MHD) equations. The distinctive feature of such method is the use of approximate solutions that are exactly divergence-free inside each element for the magnetic field. As a consequence, this method has a smaller computational cost than the traditional discontinuous Galerkin method with standard piecewise polynomial spaces. We formulate the locally divergence-free discontinuous Galerkin method for the MHD equations and perform extensive one and two-dimensional numerical experiments for both smooth solutions and solutions with discontinuities. Our computational results demonstrate that the locally divergence-free discontinuous Galerkin method, with a reduced cost comparing to the traditional discontinuous Galerkin method, can maintain the same accuracy for smooth solutions and can enhance the numerical stability of the scheme and reduce certain nonphysical features in some of the test cases.
8615414
Collaborative distributed virtual sculpting
A lot of effort is now being put into developing collaborative distributed virtual environments. However very few projects address collaborative virtual sculpting in which the shapes of the target objects are likely changing continuously. Some major issues including user interaction, data transmission, concurrent object editing by multiple clients and rendering of deforming objects must be addressed in a real-time context. We propose a framework for collaborative virtual sculpting in a distributed virtual environment. The system is based on a hybrid model which merges the client-server and the peer-to-peer architectures to allow fast data replication. To support real-time deformation and rendering of deformable objects, we model each of these objects using NURBS surfaces and render them using the real-time deformable NURBS rendering method that we have developed. We present a data structure for the transmission of these deformable objects. We also introduce the idea of editing region and the corresponding locking mechanism for simultaneous editing of the same object by multiple clients. Toward the end of the paper we show some performance results of the prototype system.
17558341
Adaptive partitioning for multi-server distributed virtual environments
A distributed virtual environment (DVE) allows users at different geographical locations to share information and interact within a common virtual environment (VE) via a local network or through the Internet. However, when the number of users exploring the VE increases, the server will quickly become the bottleneck. To enable good performance, we are currently developing a multi-server DVE prototype. In this paper, we describe an adaptive data partitioning technique to dynamically partition the whole VE into regions. All objects within each region will be managed by a single server. As the loading of the servers changes, we show how it can be redistributed while minimizing the communication cost. Our initial results show that the proposed adaptive partitioning technique significantly improves the performance of the overall system.