7886387
An Efficient Reduction from Constrained to Unconstrained Maximum Agreement Subtree
We propose and study the Maximum Constrained Agreement Subtree (MCAST) problem, which is a variant of the classical Maximum Agreement Subtree (MAST) problem. Our problem allows users to apply their domain knowledge to control the construction of the agreement subtrees in order to get better results. We show that the MCAST problem can be reduced to the MAST problem efficiently and thus we have algorithms for MCAST with running times matching the fastest known algorithms for MAST.
36553676
Time and Space Efficient Algorithms for Constrained Sequence Alignment
In this paper, we study the constrained sequence alignment problem, which is a generalization of the classical sequence alignment problem with the additional constraint that some characters in the alignment must be positioned at the same columns. The problem finds important applications in Bioinformatics. Our major result is an O(ln2)-time and O(ln)-space algorithm for constructing an optimal constrained alignment of two sequences where n is the length of the longer sequence and l is the length of the constraint. Our algorithm matches the best known time complexity and reduces the best known space complexity by a factor of n for solving the problem. We also apply our technique to design time and space efficient heuristic and approximation algorithm for aligning multiple sequences.
43458709
Algorithms for Local Forest Similarity
An ordered labeled tree is a rooted tree, where the left-to-right order among siblings is significant and each node associates a label. A forest is a sequence of ordered labeled trees. Suppose F is a forest. A substructure is a connected subgraph of F. Define a subforest as a sequence of substructures of F such that their roots are siblings. The local forest similarity problem for forests F and G is to find two most similar subforests of F and G. We answer an open problem in Paper [3], and provide efficient algorithms on it. Comparing with previous results, our algorithms achieve better performance.
43554221
Online and Dynamic Recognition of Squarefree Strings
The online squarefree recognition problem is to detect the first occurrence of a square in a string whose characters are provided as input one at a time. We present an efficient algorithm to solve this problem for strings over arbitrarily ordered alphabets. Its running time is O(n log n), where n is the ending position of the first square, which matches the running times of the fastest known algorithms for the analogous offline problem. We also present a very simple algorithm for a dynamic version of the problem over general alphabets in which we are initially given a squarefree string, followed by a series of updates, and the objective is to determine after each update if the resulting string contains a square and if so, report it and stop.
46430059
An O(n log n)-Time Algorithm for the Maximum Constrained Agreement Subtree Problem for Binary Trees
This paper introduces the maximum constrained agreement subtree problem, which is a generalization of the classical maximum agreement subtree problem This new problem is motivated by the understood constraint when we compare the evolutionary trees We give an O(n log n)-time algorithm for solving the problem when the input trees are binary The time complexity of our algorithm matches the fastest known algorithm for the maximum agreement subtree problem for binary trees.
10777322
Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problem is formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.
27568459
Automated transformation of algorithms into register-transfer level implementations
This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled. >
7975456
Schedulability-driven frame packing for multi-cluster distributed embedded systems
We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.
9707498
Efficient test solutions for core-based designs
A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.
40452783
A Buffering/Caching Mechanism for Continous Media Players
In order to reduce the playback discontinuity of a stream of data (audio for example) sent through a packet-switched network, we proposed a buffering/caching mechanism for continuous media players. The stream playback is usually implemented by two parallel processes: receiving and playing. The former receives stream chips from the network while the latter plays the received stream chips and then empties their occupied buffers for the former. Our buffering/caching mechanism makes the receiving process completely independent of the playing process. Thus, the receiving process does not need to wait for the playing process to empty buffers so that the network bandwidth can be used as much as possible. Because the cached stream chips can be played from the local disk, the response latency of the playback control operations such as REPLAY and REWIND can be reduced as well. The mechanism was developed for our hyper audio web system.