1945498
An AMBA-compliant deblocking filter IP for H.264/AVC
We propose an efficient hardware architecture for the deblocking filter function in H.264/AVC. We use a novel memory organization that results in significant saving in filtering time. Our design includes two 4/spl times/4 register sets and one 160/spl times/32 two-port SRAM such that filtering and transpose are carried out simultaneously. Synthesis results show that our design is small (19k gates) and high performance (100 MHz @ 0.25 /spl mu/m). An AMBA-compliant interface is added to our design for SOC integration and FPGA prototyping. Experimental results show that our design works well with the reference software JM 7.3 and achieves significant speed up, even with a huge communication overhead between the CPU and the hardware accelerator.
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
53235373
Performance-optimal clustering with retiming for sequential circuits
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
16848330
A flexible graphical user interface for performance modeling
We identify three goals for the graphical user interface (GUI) of a network simulation environment: user friendliness, model re-usability, and application extensibility. We address the user friendliness issue by proposing a simple yet efficient approach to setup parameters for the simulation models. We address the application extensibility issue by a two-layer GUI architecture. The two layers are loosely-coupled, and the first layer can be easily replaced (without affecting the other components of the simulation environment). We address the model re-usability issue by subnetworks. Unlike most existing simulation packages where subnetwork is simply a method to group the nodes, the subnetwork construct in our approach is an integral part of the simulation environment (i.e., all operations for a basic node also apply to a subnetwork). The port concept is used to explicitly define the I/O relationship between a subnetwork and the outside world. Parameter dialog boxes are used to set up the parameters for a subnetwork conveniently. Finally, a simple stack mechanism is proposed to measure subnetwork-wide output statistics.<<ETX>>
9700596
Implicit Deregistration with Forced Registration for PCS Mobility Management
Registration/deregistration with a mobility database called Visitor Location Registers (VLRs) is required in a PCS network when a mobile phone moves between registration areas. Several schemes were proposed to deregister a mobile phone after it moves out of a registration area. A simple scheme, called implicit deregistration, is studied in this paper, which does not specifically deregister any obsolete record in the VLR. If the VLR is full when a mobile phone arrives, a record in the VLR is deleted and the reclaimed storage is reassigned to the incoming mobile phone. It is possible that a valid record will be deleted. If so, the VLR record of a mobile phone may be deleted before a call to the mobile phone arrives. Our previous work assumed that the incoming call setup would be lost. In this paper, we propose forced registration to restore the VLR record before the call setup operation can proceed. With this modification, implicit deregistration totally eliminates the deregistration traffic at the cost of creating some forced registration traffic.We derive the record-missing probability and the portion of the network traffic saved by implicit deregistration. Our study indicates that implicit deregistration with forced registration may significantly reduce the deregistration traffic if the user mobility is high and the number of mobile phones in a registration area is not very large.
13768633
Software Defined Radio - A High Performance Embedded Challenge
Wireless communication is one of the most computationally demanding workloads. It is performed by mobile terminals (“cell phones”) and must be accomplished by a small battery powered system. An important goal of the wireless industry is to develop hardware platforms that can support multiple protocols implemented in software (software defined radio) to support seamless end-user service over a variety of wireless networks. An equally important goal is to provide higher and higher data rates. This paper focuses on a study of the wideband code division multiple access protocol, which is one of the dominant third generation wireless standards. We have chosen it as a representative protocol. We provide a detailed analysis of computation and processing requirements of the core algorithms along with the interactions between the components. The goal of this paper is to describe the computational characteristics of this protocol to the computer architecture community, and to provide a high-level analysis of the architectural implications to illustrate one of the protocols that would need to be accommodated in a programmable platform for software defined radio. The computation demands and power limitations of approximately 60 Gops and 100~300 mW, place extremely challenging goals on such a system. Several of the key features of wideband code division multiple access protocol that can be exploited in the architecture include high degrees of vector and task parallelism, small memory footprints for both data and instructions, limited need for complex arithmetic functions such as multiplication, and a highly variable processing load that provides the opportunity to dynamically scale voltage and frequency.
16053955
Design Issues for Optimistic Distributed Discrete Event Simulation
Simulation is a powerful tool for studying the dynamics of a system. However, simulation is time-consuming. Thus, it is natural to attempt to use multiple processors to speed up the simulation process. Many protocols have been proposed to perform discrete event simulation in multi-processor environments. Most of these distributed discrete event simulation protocols are either conservative or optimistic. The most common optimistic distributed simulation protocol is called Time Warp. Several issues must be considered when designing a Time Warp simulation; examples are reducing the state saving overhead and designing the global control mechanism (i. e., global virtual time computation, memory management, distributed termination, and fault tolerance). This paper addresses these issues. We propose a heuristic to select the checkpoint interval to reduce the state saving overhead, generalize a previously proposed global virtual time computation algorithm, and present new algorithms for memory management, distributed termination, and fault tolerance. The main contribution of this paper is to provide guidelines for designing an efficient Time Warp simulation.
5110930
A comparison study of the two-tier and the single-tier personal communications services systems
A two-tier PCS system integrates the high tier PCS system and the low tier PCS systems into a single system to provide the advantages of both tiers. Such a system is expected to provide better service (more available and more cost effective to the users) at the expense of the extra tier switching management. We compare the performance of the two-tier PCS system and the single low tier system in two aspects: the registration traffic and the service availability. Because of the tier management, the two-tier system generates more registration traffic than the single low tier system. Under the range of the input parameters in our study, we show that the two-tier system generates less than 10% extra registration traffic than the single low tier system in most cases and generates less than 20% registration traffic in the worst cases. It is clear that for the service availability, the two-tier system is better than the single one tier system. We also study the probability that a call is forced terminated in the single low tier system because the low tier becomes unavailable during the call (such a call can be continued in the two-tier system).