31833569
The kth Lower Multiexponent of Tournament Matrices
10079260
The sum number and integral sum number of complete bipartite graphs
Let N denote the set of positive integers. The sum graph G + (S) of a 1nite subset S of N is the graph (S; E) with vertex set S and edge set E such that for u; v ∈ S; uv ∈ E if and only if u + v ∈ S. A graph G is called a sum graph if it is isomorphic to the sum graph G + (S) of some 1nite subset S of N . The sum number � (G) of a graph G is de1ned as the smallest nonnegative integer m for which G ∪ mK1 is a sum graph. Let Z be the set of all integers. By extending the set N to Z in the above de1nitions of sum graphs and sum numbers, Harary [3] introduced the corresponding notions of integral sum graphs and integral sum number of a graph. In this paper, we evaluate the value of the sum number and integral sum number of the complete bipartite graph Kr; s. While the former one corrects the result given in [4], the latter settles completely a problem proposed in [3]. c � 2001 Elsevier Science B.V. All rights reserved.
62878
Single-hop probing asymptotics in available bandwidth estimation: sample-path analysis
In this paper, we take the sample-path approach in analyzing the asymptotic behavior of single-hop bandwidth estimation under bursty cross-traffic and show that these results are provably different from those observed under fluid models of prior work. This difference, which we call the probing bias, is one of the previously unknown factors that can cause measurement inaccuracies in available bandwidth estimation. We present an analytical formulation of "packet probing," based on which we derive several major properties of the probing bias. We then experimentally observe the <i>probing bias</i> and investigate its quantitative relationship to several deciding factors such as probing packet size, probing train length, and cross-traffic burstiness. Both our analytical and experimental results show that the probing bias vanishes as the packet-train length or packet size increases. The vanishing rate is decided by the burstiness of cross-traffic.
6291223
Interconnect implications of growth-based structural models for VLSI circuits
Power-law scaling phenomena that govern VLSI circuits have for several decades formed the foundation of VLSI interconnect estimation.   This research investigates possible alternative power-law phenomena in VLSI circuits.   In particular, we develop new<italic>random growth</italic>models and assess their implications for VLSI interconnect structure.   We assess our models' predictions for<italic>fanout</italic>,<italic>crossing edge</italic>, and<italic>terminal</italic>scaling using test data from 21 industry standard-cell designs with up to 283K cells.   Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.
863906
Per-Flow Queueing by Dynamic Queue Sharing
Per-flow queuing is believed to be able to guarantee advanced Quality of Service (QoS) for each flow. With the dramatic increase of link speed and number of traffic flows, per-flow queuing faces a great challenge since millions of queues need to be maintained for implementation in a traditional sense. In this paper, by setting only a small number of physical queues, we propose a Dynamic Queue Sharing (DQS) mechanism to achieve an equal performance to the pure per-flow queuing with a lower cost. The proposed mechanism is based on an interesting fact that the number of simultaneous active flows in the router buffer is far less than that of in-progress flows. In DQS, a physical queue is dynamically created on-demand when a new flow comes and then dynamically released when the flow temporarily pauses. Hashing and binary sorting tree (or linked list) are combined to manage the mapping between flows and queues, so as to isolate flows in different queues. Theoretical analysis and traces experiments are conducted to evaluate DQS. The results demonstrate that when the parameters are well set, the operation delay is less than two time cycles in average with an extra memory of 16k bits.
21236644
Parallel Switch System with QoS Guarantee for Real-Time Traffic
This paper studies the load-balancing algorithm and quality of service (QoS) control mechanism in a 320Gb/s switch system, which incorporates four packet-level parallel switch planes. Eight priorities for both unicast and multicast traffic are implemented, and the highest priority with strict QoS guarantee is designed for real-time traffic. Through performance analysis under multi-priority burst traffic, we demonstrate that the load-balancing algorithm is efficient, and the switch system not only provides excellent performance to real-time traffic, but also efficiently allocates bandwidth among other traffic of lower priorities. As a result, this parallel switch system is more scalable towards next generation core routers with QoS guarantee, as well as ensures in-order delivery of IP packets.
5712150
Preemptive Packet-Mode Scheduling to Improve TCP Performance
Recent Internet traffic measurements show that 60% of the total packets are short packets, which include TCP acknowledgment and control segments. These short packets make a great impact on the performance of TCP. Unfortunately, short packets suffer from large delay due to serving long data packets in switches running in the packet mode, i.e. a packet is switched in its entirety. To optimize TCP performance, we apply a cross-layer approach to the design of switching architectures and scheduling algorithms. Specifically, we propose a preemptive packet-mode scheduling architecture and an algorithm called preemptive short packets first (P-SPF). Analysis and simulation results demonstrate that compared to existing packet-mode schedulers, P-SPF significantly reduces the waiting time for short packets while achieving a high overall throughput when the traffic load is heavy. Moreover, with a relatively low speedup, P-SPF performs better than existing packet-mode schedulers under any traffic load.