1870907
Macro-modeling concepts for the chip electrical interface
The power delivery network is made up of passive elements in the distribution network, as well as the active transistor loads. A chip typically has three types of power supplies that require attention: core, I/O, and analog. Core circuits consist of digital circuits and have the largest current demand. In addition to all of the system issues/models for the core, modeling the I/O subsystem has the additional requirement of modeling return paths and discontinuities. The analog circuits present yet a different challenge to the macro-modeling of the supply network because they place a tight demand on supply variations. This paper presents a design methodology on how to generate macro-models of the entire chip electrical interface. This methodology can be used by the chip, package, and system designers and is being used to design high-reliability servers.
12123652
Analysis of blocking dynamic circuits
In order for dynamic circuits to operate correctly, their inputs must be monotonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is negative. With blocking dynamic circuits, cascading low-skew dynamic gates allows each dynamic gate to tolerate a degraded input level. The larger noise margin provides greater flexibility with the delay vs. noise margin trade-off (i.e. the circuit robustness vs. speed tradeoff). This paper generalizes blocking dynamic circuits and provides a systematic approach for assigning clock phases, given delay and noise margin constraints. Using this framework, one can analyze any logic network consisting of blocking dynamic circuits.
6282895
Timing analysis including clock skew
Clock skew is an increasing concern for high-speed circuit designers. Circuit designers use transparent latches and skew-tolerant domino circuits to hide clock skew from the critical path and take advantage of shared portions of the clock network to budget less skew between nearby elements than across the entire die, but current timing analysis algorithms do not handle correlated clock skews. This paper extends the Sakallah-Mudge-Olukotun (SMO) latch-based timing analysis to include different amounts of clock skew between different elements. The key change is that departure times from each latch must be defined with respect to launching clocks so that the skew between the launching and receiving clocks can be determined at each receiver. The exact analysis leads to an explosion in the number of timing constraints, but most constraints are not tight in practical situations and a modified version of the Szymanski-Shenoy relaxation algorithm gives exact results with only a small increase in runtime. The timing analysis formulation also captures the effects of skew on edge-triggered flip-flops, domino circuits, and min-delay constraints. Our exact algorithm, applied to a supercomputer node controller with over 12000 clocked elements, finds the system can run 50-90 ps faster than a single skew analysis would predict and requires searching fewer than 4% more latch departures than conventional algorithms. With the less conservative skew budgets enabled by better timing analysis, we expect clocked systems will remain viable to multi-GHz frequencies.
53748903
A Framework for Designing Reusable Analog Circuits
38675279
On-Line Learning Control for Discrete Nonlinear Systems Via an Improved ADDHP Method
This paper mainly discusses a generic scheme for on-line adaptive critic design for nonlinear system based on neural dynamic programming (NDP), more exactly, an improved action-depended dual heuristic dynamic programming (ADDHP) method. The principal merit of the proposed method is to avoid the model neural network which predicts the state of next time step, and only use current and previous states in the method, as makes the algorithm more suitable for real-time or on-line application for process control. In this paper, convergence proof of the method will also be given to guarantee the control to reach the optimal. At last, simulation result verifies the performance.
12953069
Efficient Security Mechanisms for Overlay Multicast-Based Content Distribution
This paper studies the security issues that arise in an overlay multicast architecture where service providers distribute content such as web pages, static and streaming multimedia data, realtime stock quotes, or security updates to a large number of users. In particular, two major security problems of overlay multicast, network access control and group key management, are addressed. We first present a bandwidth-efficient scheme, called CRBR, that seamlessly integrates network access control and group key management. Next we propose a DoS-resilient key distribution scheme, called k-RIP, that delivers updated keys to a large fraction of nodes with high probability even if an attacker can selectively compromise nodes in the multicast data delivery hierarchy and command these compromised nodes to drop keying packets. The proposed schemes do not rely on knowledge of overlay topology, and can scale up to very large overlay networks.
14999533
Efficient target search with relevance feedback for large CBIR systems
Recent content-based image retrieval (CBIR) techniques were designed around query refinement based on relevance feedback. They suffer from slow convergence, high disk I/O, and do not even guarantee to find intended targets. In this paper, we identify the cause of these problems and propose several efficient target search methods to address these drawbacks. Our complexity analysis shows that our approach is able to reach any given target image with fewer iterations in the worst and average cases. We evaluated our techniques on large datasets in simulated and realistic environments. The results show that our approach significantly reduces the number of iterations and improves overall retrieval performance. The experiments also confirm that our approach can always retrieve intended targets even with poor selection of initial query points and can be used to improve the effectiveness of existing CBIR systems with relevance feedback.
24184742
On Distance Two Labellings of Graphs
15233730
Circulant Distant Two Labeling and Circular Chromatic Number
Let G be a graph and d,d 0 be positive integers, d 0 d. An m-(d,d 0 )-circular distance two labeling is a function f : V (G) ! {0,1,2,···,m 1} such that |f(u) f(v)|m d if u and v are adjacent; and |f(u) f(v)|m d 0 if u and v are distance two apart, where |x|m := min{|x|,m| x|}. The minimum m such that there exists an m-(d,d 0 )-circular labeling for G is called the d,d0-number of G and denoted by d,d 0(G). The d,d 0-numbers for trees can be obtained by a first-fit algorithm. In this article, we completely determine the d,1-numbers for cycles. In addition, we show connections between generalized circular distance labeling and circular chromatic number.