9179095
fmp and fmp2rsm: eclipse plug-ins for modeling features using model templates
Feature-based model templates have been proposed as a technique for modeling software product lines. We describe a set of tools supporting the technique, namely a feature model editor and feature configurator, and a model-template editor, processor, and verifier.
8872211
Synchronizing Cardinality-Based Feature Models and Their Specializations
A software product line comprises a set of products implementing different configurations of features. The set of valid feature configurations within a product line can be described by a feature model. In some practical situations, a feature configuration needs to be derived in stages by creating a series of successive specializations of the initial feature model. In this paper, we consider the scenario where changes to the feature model due to, for example, the evolution of the product line, need to be propagated to its existing specializations and configurations. After discussing general dimensions of model synchronization, a solution to synchronizing cardinality-based feature models and their specializations and configurations is presented.
16925677
Multi-level customization in application engineering
Developing mechanisms for mapping features to analysis models.
7848399
Model-driven software product lines
Model-driven software product lines combine the abstraction capability of Model Driven Software Development (MDSD) and the variability management capability of Software Product Line Engineering (SPLE). This short contribution motivates the idea of model-driven software product lines and briefly explains the concepts underlying feature-based model templates, which is a particular technique for modeling software product lines.
12329362
Fault Attacks for CRT Based RSA: New Attacks, New Results, and New Countermeasures
Nowadays RSA using Chinese Remainder Theorem (CRT) is widely used in practical applications. However there is a very powerful attack against it with a fault injection during one of its exponentiations. Many countermeasures were proposed but almost all of them are proven to be insecure. In 2005, two new countermeasures were proposed. However they still have a weakness. The final signature is stored in a memory after CRT combination and there is an error-check routine just after CRT combination. Therefore, if an attacker can do a double-fault attack that gives the first fault during one of the exponentiation and the other to skip the error-checking routine, then he can succeed in breaking RSA. In this paper, we show this can be done with the concrete result employing a glitch attack and propose a simple and almost cost-free method to defeat it.
4382018
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
This paper describes the polymorphous TRIPS architecture that can be configured for different granularities and types of parallelism. The TRIPS architecture is the first in a class of post-RISC, dataflow-like instruction sets called explicit data-graph execution (EDGE). This EDGE ISA is coupled with hardware mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrency, the TRIPS architecture prototype contains two out-of-order, 16-wide-issue grid processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes---ILP, TLP, and DLP---demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.
6889249
Discrete differential error metric for surface simplification
In this paper we propose a new discrete differential error metric for surface simplification. Many surface simplification algorithms have been developed in order to produce rapidly high quality approximations of polygonal models, and the quadric error metric based on the distance error is the most popular and successful error metric so far Even though such distance based error metrics give visually pleasing results with a reasonably fast speed, it is hard to measure an accurate geometric error on a highly curved and thin region since the error measured by the distance metric on such a region is usually small and causes a loss of visually important features. To overcome such a drawback, we define a new error metric based on the theory of local differential geometry in such a way that the first and the second order discrete differentials approximated locally on a discrete polygonal surface are integrated into the usual distance error metric. The benefits of our error metric are preservation of sharp feature regions after a drastic simplification, small geometric errors, and fast computation comparable to the existing methods.
9249416
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB non-uniform (NUCA) on-chip memory system
12552933
TTS without Revocation Capability Secure Against CCA2
A traitor tracing scheme (TTS) deters traitors from giving away their secret keys to decrypt the transmitted data by enabling the system manager to trace at least one of the traitors who participated in the construction of a pirate decoder after confiscating it. In an asymmetric scheme, the system manager is also under suspicion, so the system manager must convince a judge of the implication of the traitors. Recently, Kiayias and Yung proposed an asymmetric public key traitor tracing scheme [13]. However, their scheme does not provide CCA2 security even if a single user is a traitor. That is, their scheme is secure against adaptive chosen ciphertext (CCA2) attack only when there is no traitor. In this paper, we first introduce the security notion against CCA2 attack in a traitor tracing scheme with no revocation capability. This notion is somewhat different from the traditional security notion against CCA2 attack in a two-party encryption scheme [5]. To the best of our knowledge, no security notion against CCA2 attack in a traitor tracing scheme with no revocation capability has been presented. In addition, we modify the Kiayias and Yung’s scheme to achieve security against CCA2 attack under the decision Diffie-Hellman assumption and the collision-resistant hash function assumption.