12521322
Repacking on Demand for Hierarchical Cellular Networks
In mobile telecommunications operation, radio channels are scarce resources and should be carefully assigned. One possibility is to deploy the hierarchical cellular network (HCN). This paper studies a HCN channel assignment scheme called repacking on demand (RoD). RoD was originally proposed for wireless local loop networks. We expend this work to accommodate mobile HCN. A simulation model is proposed to study the performance of HCN with RoD and some previously proposed schemes. Our study quantitatively indicates that RoD may significantly outperform the previous proposed schemes.
2805042
A new random walk model for PCS networks
This paper proposes a new approach to simplify the two-dimensional random walk models capturing the movement of mobile users in personal communications services (PCS) networks. Analytical models are proposed for the new random walks. For a PCS network with hexagonal configuration, our approach reduces the states of the two-dimensional random walk from (3n/sup 2/+3n-5) to n(n+1)/2, where n is the layers of a cluster. For a mesh configuration, our approach reduces the states from (2n2-2n+1) to (n/sup 2/+2n+4)/4 if n is even and to (n/sup 2/+2n+5)/4 if n is odd. Simulation experiments are conducted to validate the analytical models. The results indicate that the errors between the analytical and simulation models are within 1%. Three applications (i.e., microcell/macrocell configuration, distance-based location update, and GPRS mobility management for data routing) are used to show how our new model can be used to investigate the performance of PCS networks.
5110930
A comparison study of the two-tier and the single-tier personal communications services systems
A two-tier PCS system integrates the high tier PCS system and the low tier PCS systems into a single system to provide the advantages of both tiers. Such a system is expected to provide better service (more available and more cost effective to the users) at the expense of the extra tier switching management. We compare the performance of the two-tier PCS system and the single low tier system in two aspects: the registration traffic and the service availability. Because of the tier management, the two-tier system generates more registration traffic than the single low tier system. Under the range of the input parameters in our study, we show that the two-tier system generates less than 10% extra registration traffic than the single low tier system in most cases and generates less than 20% registration traffic in the worst cases. It is clear that for the service availability, the two-tier system is better than the single one tier system. We also study the probability that a call is forced terminated in the single low tier system because the low tier becomes unavailable during the call (such a call can be continued in the two-tier system).
16848330
A flexible graphical user interface for performance modeling
We identify three goals for the graphical user interface (GUI) of a network simulation environment: user friendliness, model re-usability, and application extensibility. We address the user friendliness issue by proposing a simple yet efficient approach to setup parameters for the simulation models. We address the application extensibility issue by a two-layer GUI architecture. The two layers are loosely-coupled, and the first layer can be easily replaced (without affecting the other components of the simulation environment). We address the model re-usability issue by subnetworks. Unlike most existing simulation packages where subnetwork is simply a method to group the nodes, the subnetwork construct in our approach is an integral part of the simulation environment (i.e., all operations for a basic node also apply to a subnetwork). The port concept is used to explicitly define the I/O relationship between a subnetwork and the outside world. Parameter dialog boxes are used to set up the parameters for a subnetwork conveniently. Finally, a simple stack mechanism is proposed to measure subnetwork-wide output statistics.<<ETX>>
16744149
Performance Analysis for Dual Band PCS Networks
In a dual band personal communications services (PCS) network, heavy traffic areas are covered by microcells which overlay macrocells. In such a network, microcells and macrocells utilize different frequency bands. We propose an analytic model to study the performance of a dual band PCS architecture. Our model assumes that a PCS subscriber has a general residence time distribution in a microcell and the macrocell residence time distribution is derived from the microcell residence time distribution. An iterative algorithm is used to compute the overflow traffic from a microcell to its overlaid macrocell. Then, the call incompletion probability is computed by a macrocell model based on the overflow traffic. Our study indicates that the variance of the microcell residence time distribution and the number of microcells covered by a macrocell have significant effects on the call incompletion probability.
15619003
A Graphical User Interface Design for Network Simulation
Abstract This article describes a prototyping effort of a flexible graphical user interface (GUI) for a simulation tool called COPS. The GUI is designed to allow parameter setup for all modules in simulation model, and can be easily replaced by new GUIs implemented in different languages/graphical tools. This article provides design guidelines and implementation details of the flexible GUI.
32261160
Channel assignment for GSM half-rate and full-rate traffic
Global System for Mobile Communications (GSM) supports full-rate and half-rate calls. In this paper, we propose analytical and simulation models to study the performance of four channel assignment schemes for GSM half-rate and full-rate traffic. Our study indicates that among the four schemes, the repacking scheme has the best performance for mixing half-rate and full-rate traffic. We also observe that good performance is expected if the standard derivation of the cell residence time for a mobile station is large.
53235726
Integrating logic retiming and register placement
16940967
A fast transistor-chaining algorithm for CMOS cell layout
A fast algorithm is proposed for the transistor-chaining problem in CMOS functional cell layout based on the layout style of T. Uehara and W.M. van Cleemput (1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of transistor chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the set of branches that needs to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is also derived. This bound enables one to prune the search tree efficiently. The algorithm has been implemented and tested and is able to find optimal solutions almost instantly for all the cases from the literature that were examined. >
28386887
New Systolic Arrays for the Longest Common Subsequence Problem
Abstract New systolic arrays are presented to solve the longest common subsequence (LCS) problem. The first array is based on a previous work to compute the length of an LCS. The second array improves on the first one. The second array is about 1 4 faster than the first array, and each processing element (PE) of the second array requires one less port for both input and output to transfer one less value. Either of the two arrays can be equipped with a content-addressable memory in each PE to recover an LCS. The resulting array requires fewer steps than the previously proposed one.
195838526
LiB: a cell layout generator
An automatic layout generation system, called LiB, for the library cells used in CMOS ASIC design is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a symbolic layout. In LiB, the intra-cell routing runs not only between PMOS and NMOS but also on diffusion islands as well as the two side regions (one between the PMOS diffusion and the power line, and the other between the NMOS diffusion and the ground line). Several heuristic algorithms are proposed to solve the transistor-clustering, -pairing, -chaining, -folding, the chain placement, the routing, and the net assignment problems. Experimental results are presented to show the capability of LiB.<<ETX>>