41639900
An Evolutionary Fuzzy Multi-objective Approach to Cell Formation
Fuzzy mathematical programming (FMP) has been shown not only providing a better and more flexible way of representing the cell formation (CF) problem of cellular manufacturing, but also improving solution quality and computational efficiency. However, FMP cannot meet the demand of real-world applications because it can only be used to solve small-size problems. In this paper, we propose a heuristic genetic algorithm (HGA) as a viable solution for solving large-scale fuzzy multi-objective CF problems. Heuristic crossover and mutation operators are developed to improve computational efficiency. Our results show that the HGA outperforms the FMP and goal programming (GP) models in terms of clustering results, computational time, and user friendliness.
27561759
Splice site prediction using support vector machines with a Bayes kernel
One of the most important tasks in correctly annotating genes in higher organisms is to accurately locate the DNA splice sites. Although relatively high accuracy has been achieved by existing methods, most of these prediction methods are computationally extensive. Due to the enormous amount of DNA sequences to be processed, the computational speed is an important issue to consider. In this paper, we present a new machine learning method for predicting DNA splice sites, which first applies a Bayes feature mapping (kernel) to project the data into a new feature space and then uses a linear Support Vector Machine (SVM) as a classifier to recognize the true splice sites. The computation time is linear to the number of sequences tested, while the performance is notably improved compared with the Naive Bayes classifier in terms of classification accuracy, precision, and recall. Our classification results are also comparable to the solution quality obtained by the SVMs with polynomial kernels, while the speed of our proposed method is significantly faster. This is a notable improvement in computational modeling considering the huge amount of DNA sequences to be processed.
17686405
A time-series biclustering algorithm for revealing co-regulated genes
Although existing bicluster algorithms claimed to be able to discover co-regulated genes under a subset of given experiment conditions, they ignore the inherent sequential relationship between crucial time points and thus are not applicable to analyze time-series gene expression data. A simple and effective deletion-based algorithm, using the mean squared residue score as a measure, was developed to bicluster time-series gene expression data. While enforcing a threshold value for the score, the algorithm alternately eliminates genes and time points according to their correlation to the bicluster. To ensure the time locality, only the starting and ending points in the time interval are eligible for deletion. As a result, the number of genes and the length of time interval are simultaneously maximized. Our experimental results shown that the proposed method is capable of identifying co-regulated genes characterized by partial time-course data that previous methods failed to discover.
1288514
Generation of universal series-parallel Boolean functions
The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique in FTGA design, it is desirable to design FPGA logic modules based on Boolan functions which can be represented by a tree of gates (i.e., series-parallel or SP functions). Thakur and Wong [1996a; 1996b] studied this issue and they demonstrated the advantages of designing logic modules as universal SP functions, that is, SP functions which can implement all SP functions with a certain number of inputs. The number of variables in the universal function corresponds to the number of inputs to the FPGA module, so it is desirable to have as few variables as possible in the constructed functions. The universal SP functions presented in  Thakur and Wong [1996a; 1966b] were designed manually. Recently, there is an algorithm that can generate these functions automatically [Young and Wong 1997], but the number of variables in the generated functions grows exponentially. In this paper, we present an algorithm to generate, for each <italic>n</italic> > 0, a universal SP function <italic>f<subscrpt>n</subscrpt></italic> for implementing all SP functions with <italic>n</italic> inputs or less. The number of variables in <italic>f<subscrpt>n</subscrpt></italic> is less than <italic>n</italic><supscrpt>2.376</supscrpt> and the constructions are the smallest possible when <italic>n</italic> is small (<italic>n</italic> ≤ 7). We also derived a nontrival lower bound on the sizes of the optimal universal SP functions  (&OHgr;(<italic>n</italic> log <italic>n</italic>)).
52810492
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solving this flipping problem optimally. However, solving such a problem optimally is non-trivial given the gigantic sizes of modern circuits. We are able to identify a large portion of cells (about 75%) of which the orientation (flipped or not flipped) can be determined independent of the orientations of all the other cells. We have derived three non-trivial conditions to identify those so called independent cells, strictly solvable cells and conditionally solvable cells. In this way, we can greatly reduce the number of cells whose orientations are dependent on each other. Finally, the cell flipping problem of the remaining dependent cells can be formulated as a mixed integer linear programming (MILP) problem and solved optimally. However, this may still be too slow for extremely large circuits and we have applied two other methods, linear programming (LP) and linear programming followed by mixed integer linear programming (LP+MILP) to solve the problem. Experimental results show that by identifying those independent and solvable cells first and applying the LP+MILP technique, we can solve this flipping problem effectively and obtain results just 0.01% more than the optimal. In addition, we can improve the wirelength and number of overflow tiles by 5% and 9% respectively on the floorplanning benchmarks
18525423
An efficient and optimal algorithm for simultaneous buffer and wire sizing
In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10000 segments and buffers, the CPU time is only 0.255 s. We then extend our result to handle interconnect trees. We present an algorithm SBWS-T which always gives the optimal solution. Experimental results show that SBWS-T is faster than the greedy wire sizing algorithm in practice.
41181041
A matrix synthesis approach to thermal placement
In this paper, we consider the thermal placement problem for gate arrays. We introduce a new combinatorial optimization problem, matrix synthesis problem (MSP), to model the thermal placement problem. Given a list of mn nonnegative real numbers and an integer t, MSP constructs a m/spl times/n matrix out of the given numbers such that the maximum sum among all t/spl times/t submatrices is minimized. We show that MSP is NP-complete and present several provably good approximation algorithms for the problem. We also demonstrate that our thermal placement strategy is flexible enough to allow simultaneous consideration of other objectives such as wiring.
6347443
IPR: An Integrated Placement and Routing Algorithm
In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all previous placement approaches optimize some very primitive interconnect models during placement. These models are far from the actual interconnect implementation in the routing stage. As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. In addition, the placement may not even be routable and timing closure may not be achievable. In this paper, we propose to address the inconsistency between the placement and routing objectives by fully integrating global routing into placement. As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (integrated placement and routing). To ensure the algorithm to be computationally efficient, efficient placement and routing algorithms FastPlace, FastDP and FastRoute are integrated, and well-designed methods are proposed to integrate them efficiently and effectively. Experimental results show that IPR reduces overflow by 36%, global routing wirelength by 3.6%, and runtime by 36% comparing to ROOSTER, which is the previous best academic routability- driven placer.