1745513
Test generation for global delay faults
This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks.
17178263
Accurate fault modeling and fault simulation of resistive bridges
This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults.
15554842
Resistive bridge fault modeling, simulation and test generation
In this work/sup 1/ we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the first resistive bridging fault ATPG, which attempts to detect the maximum possible bridging resistance at each fault site. We compare the results of the ATPG to the coverage obtained from other test sets, and coverage obtained by using the ATPG in a clean-up mode. Results on ISCAS85 circuits show that stuck-at test sets do quite well, but that the ATPG can still improve the coverage. We have also found that the loss of fault coverage is predominantly due to undetected faults, rather than faults in which only a small resistance is detected. This suggests that lower-cost fault models can be used to obtain high resistive bridge fault coverage.
11931234
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus an two fault types: resistive bridges between gate outputs that cause pattern sensitive functional faults and opens in transmission gates that cause delay faults. In both cases, the traditional stuck at model is inadequate. The test vector to sensitize and propagate a resistive bridging fault is not unique. The traditional greedy test vector selection is optimistic, with some choices having poor real coverage. We realistically model the fault and fault coverage, and describe an optimal selection strategy. In a transmission gate with an open NMOS or PMOS device, the output voltage is degraded, increasing delay and reducing noise margin. We model this fault and show how low-voltage testing can be used to detect it. Our goal in applying these techniques to all important fault types is to maximize the real coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.
8781947
A fast algorithm for critical path tracing in VLSI digital circuits
An exact, linear-time critical path tracing algorithm is presented. The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets.
980425
Stack-Based Typed Assembly Language
In previous work, we presented a Typed Assembly Language (TAL). TAL is sufficiently expressive to serve as a target language for compilers of high-level languages such as ML. This work assumed such a compiler would perform a continuation-passing style transform and eliminate the control stack by heap-allocating activation records. However, most compilers are based on stack allocation. This paper presents STAL, an extension of TAL with stack constructs and stack types to support the stack allocation style. We show that STAL is sufficiently expressive to support languages such as Java, Pascal, and ML; constructs such as exceptions and displays; and optimizations such as tail call elimination and callee-saves registers. This paper also formalizes the typing connection between CPS-based compilation and stack-based compilation and illustrates how STAL can formally model calling conventions by specifying them as formal translations of source function types to STAL types.
827988
On Synchronous and Asynchronous Mobile Processes
This paper studies the relationship between synchronous and asynchronous mobile processes, in the setting of the π-calculus. A type system for processes of the asynchronous monadic subcalculus is introduced and used to obtain a full-abstraction result: two processes of the polyadic π-calculus are typed barbed congruent iff their translations into the subcalculus are asynchronous-monadic-typed barbed congruent.
209401601
On Regions and Linear Types.
10826914
Thermal modeling of single event burnout failure in semiconductor power devices
Abstract Experimental investigations of single event burnout (SEB) of power devices due to heavy ion impacts have identified the conditions required to produce device failure. A key feature observed in the data is an anomalistic secondary rise in current occurring shortly after the ion strike. To verify these findings including the thermally induced secondary plateau, simulations have been performed on the model single event burnout. The new models include additional thermally dependent electrical components to capture thermally induced physical effects. Through the inclusion of analytic temperature models coupled with the electrical model, the electrical response is predicted with reasonable accuracy. The simulations provide order-of-magnitude estimates as well as prediction of phenomenological features such as the secondary rise in current. This work represents a first attempt to characterize thermal failure of power devices due to heavy ion impacts by including temperature dependent components that until now have not been modeled. The thermal model in the present work produces qualitative agreement with experiments on SEB that have been previously unexplained.