6577464
An HMAC processor with integrated SHA-1 and MD5 algorithms
Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost---12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.
37411387
Automatic generation of memory built-in self-test cores for system-on-chip
Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
26839737
A BIST scheme for FPGA interconnect delay faults
In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.
53223861
Design and test of a scalable security processor
39753705
A programmable built-in self-test core for embedded memories
15052014
Optimization of Regular Expression Pattern Matching Circuits on FPGA
Regular expressions are widely used in network intrusion detection system (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to the speed advance of networks, many previous works propose hardware architectures on FPGA to accelerate attack detection. The challenge of hardware implementation is to accommodate the regular expressions to FPGAs of the large number of attacks. Although the minimization of logic equations has been studied intensively in the CAD area, the minimization of multiple regular expressions has been largely neglected. This paper presents an architecture allowing our algorithm to extract and share common sub-regular expressions. Experimental results show that our sharing scheme significantly reduces the area of regular expression circuits
9249972
Measures of wireless data performance
There is considerable interest within the industry in specifying the performance of wireless data. In this letter, we review and contrast various performance metrics such as peak rates, average throughput, and user experience. We discuss the relevance of these measures to varying applications such as marketing, planning, and technology comparisons.
2158099
Keyphrase Extraction Using Semantic Networks Structure Analysis
Keyphrases play a key role in text indexing, summarization and categorization. However, most of the existing keyphrase extraction approaches require human-labeled training sets. In this paper, we propose an automatic keyphrase extraction algorithm, which can be used in both supervised and unsupervised tasks. This algorithm treats each document as a semantic network. Structural dynamics of the network are used to extract keyphrases (key nodes) unsupervised. Experiments demonstrate the proposed algorithm averagely improves 50% in effectiveness and 30% in efficiency in unsupervised tasks and performs comparatively with supervised extractors. Moreover, by applying this algorithm to supervised tasks, we develop a classifier with an overall accuracy up to 80%.
5119687
Adaptive MPI
Processor virtualization is a powerful technique that enables the runtime system to carry out intelligent adaptive optimizations like dynamic resource management. Charm++ is an early language/system that supports processor virtualization. This paper describes Adaptive MPI or AMPI, an MPI implementation and extension, that supports processor virtualization. AMPI implements virtual MPI processes (VPs), several of which may be mapped to a single physical processor. AMPI includes a powerful runtime support system that takes advantage of the degree of freedom afforded by allowing it to assign VPs onto processors. With this runtime system, AMPI supports such features as automatic adaptive overlap of communication and computation and automatic load balancing. It can also support other features such as checkpointing without additional user code, and the ability to shrink and expand the set of processors used by a job at runtime. This paper describes AMPI, its features, benchmarks that illustrate performance advantages and tradeoffs offered by AMPI, and application experiences.
195352079
The impact of network variabilities on TCP clocking schemes
41188840
Finding Double Euler Trails of Planar Graphs in Linear Time
This paper answers an open question in the design of complimentary metal-oxide semiconductor VLSI circuits. The question asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding ${\cal E}$ such that ${\cal E}$ has an Euler trail P = e1 e2 ... em and its dual graph has an Euler trail $P^*=e^*_1 e^*_2 \ldots e^*_m$, where $e^*_i$ is the dual edge of ei for i=1,2,...,m. This paper answers this question in the affirmative by presenting a linear-time algorithm.