529060
Issues in Dataflow Computing
Publisher Summary This chapter discusses the basic principles of the dataflow model, along with its major attributes and the language support for dataflow. It provides a general description of the dataflow model of execution based on the pioneering works of research groups at Massachusetts Institute of Technology (MIT) and the University of Manchester namely, the static dataflow machine, tagged-token dataflow architecture, and Manchester machine. Major problems encountered in the design of these machines are outlined. The chapter surveys current dataflow projects and provides a comparison of the architectural characteristics and evolutionary improvements in dataflow computing. It discusses the difficulties in handling data structures in a dataflow environment. An overview of the methods for representing data structures is provided. This is supplemented by various issues required to handle data structures in a dataflow environment. The chapter addresses the issue of program allocation. Several proposed methodologies are presented and the various issues involved in program allocation are discussed. The resource requirements for dataflow computations are examined.
11122198
Shared memory and distributed shared memory systems: A survey
Publisher Summary This chapter illustrates distributed shared memory (DSM) systems that are intended to combine the ease of programming of the shared-memory model with the scalability of the distributed-memory system. DSM systems aim to unify parallel processing systems that rely on message passing with the shared-memory systems. The chapter explores the design space for such systems and includes descriptions of both hardware- and software-supported DSM systems. The implementation prototypes of some of the systems are based on older technology and older software designs, making them appear to perform poorly.
18416128
Dynamic Simultaneous Multithreaded Architecture
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomplish this, threads are generated dynamically from a predictable flow of control and then executed speculatively. Data obtained during the single context nonspeculative execution phase of DSMT is used as a hint to speculate the posterior behavior of multiple threads. DSMT employs simple mechanisms based on state bits that keep track of inter-thread dependencies in registers and memory, synchronize thread execution, and control recovery from misspeculation. Moreover, DSMT utilizes a novel greedy policy for choosing those sections of code which provide the highest performance based on their past execution history. The DSMT architecture was simulated with a new cycle-accurate, execution-driven simulator. Our simulation results show that DSMT has very good potential to improve SMT performance, even when only a single program is available. However, we found that dynamic thread behavior together with frequent misspeculation may also produce diminishing returns in performance. Therefore, the challenge is to maximize the amount of thread-level parallelism that DSMT is capable of exploiting and at the same time reduce the frequency of misspeculations.
6217758
Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card
This paper describes the implementation and performance of M-VIA on the AceNIC Gigabit Ethernet card. The AceNIC adapter has several notable hardware features for high-speed communication, such as jumbo frames and interrupt coalescing. The M-VIA performance charac- teristics were measured and evaluated based on these hardware features. Our results show that latency and bandwidth improvement can be ob- tained when the M-VIA data segmentation size is properly adjusted to utilize the AceNIC's jumbo frame feature. The M-VIA data segmenta- tion size of 4,096 bytes with MTU size of 4,138 bytes showed the best performance. However, larger MTU sizes did not necessarily result in better performance due to extra segmentation and DMA setup over- head. In addition, the cost of M-VIA interrupt handling can be reduced with AceNIC's hardware interrupt coalescing. When the parameters for the hardware interrupt coalescing were properly adjusted, the latency of interrupt handling was reduced by up to 170 µs.
8533475
Parallelization of DOALL and DOACROSS Loops - A Survey
Abstract Since loops in programs are the major source of parallelism, considerable research has been focused on strategies for parallelizing loops. For DOALL loops, loops can be allocated to processors either statically or dynamically. When the execution times of individual iterations vary, dynamic schemes can achieve better load balance, albeit at a higher runtime scheduling cost. The inter-iteration dependencies of DOACROSS loops can be constant (regular DOACROSS loops) or variable (irregular DOACROSS loops). In our research, we have proposed and tested two loop allocation techniques for regular DOACROSS loops, known as Staggered distribution (SD) and Cyclic Staggered (CSD) distribution. This article analyzes several classes of loop allocation algorithms for parallelizing DOALL, regular, and irregular DOACROSS loops.
1642899
Isomorphic Strategy for Processor Allocation in k-Ary n-Cube Systems
Due to its topological generality and flexibility, the k-ary n-cube architecture has been actively researched for various applications. However, the processor allocation problem has not been adequately addressed for the k-ary n-cube architecture, even though it has been studied extensively for hypercubes and meshes. The earlier k-ary n-cube allocation schemes based on conventional slice partitioning suffer from internal fragmentation of processors. In contrast, algorithms based on job-based partitioning alleviate the fragmentation problem but require higher time complexity. This paper proposes a new allocation scheme based on isomorphic partitioning, where the processor space is partitioned into higher dimensional isomorphic subcubes. The proposed scheme minimizes the fragmentation problem and is general in the sense that any size request can be supported and the host architecture need not be isomorphic. Extensive simulation study reveals that the proposed scheme significantly outperforms earlier schemes in terms of mean response time for practical size k-ary and n-cube architectures. The simulation results also show that reduction of external fragmentation is more substantial than internal fragmentation with the proposed scheme.
25406406
Architectural support for accelerating congestion control applications in network processors
Complex network protocols and various network services require significant processing capability for modern intelligent network applications. One of the significant features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications - scheduling and queue management algorithms, and we propose application-specific acceleration technique using ILP (instruction level parallelism) and PLP (packet level parallelism). From the ILP perspective, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10-12% improvement in performance for instruction set enhancements. For PLP, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, large number of processing elements and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. As the performance of general purpose processors rapidly increases, defining architectural extensions (e.g., MMX as in multimedia applications) for general purpose processors could be an alternative solution for wide range of network applications.
2438079
Visualizations for taxonomic and phylogenetic trees
MOTIVATION
Despite substantial efforts to develop and populate the back-ends of biological databases, front-ends to these systems often rely on taxonomic expertise. This research applies techniques from human-computer interaction research to the biodiversity domain.


RESULTS
We developed an interactive node-link tool, TaxonTree, illustrating the value of a carefully designed interaction model, animation, and integrated searching and browsing towards retrieval of biological names and other information. Users tested the tool using a new, large integrated dataset of animal names with phylogenetic-based and classification-based tree structures. These techniques also translated well for a tool, DoubleTree, to allow comparison of trees using coupled interaction. Our approaches will be useful not only for biological data but as general portal interfaces.
22808943
Exploring content-actor paired network data using iterative query refinement with NetLens
Networks have remained a challenge for information retrieval and visualization because of the rich set of tasks that users want to accomplish. This paper demonstrates a tool, NetLens, to explore a content-actor paired network data model. The NetLens interface was designed to allow users to pose a series of elementary queries and iteratively refine visual overviews and sorted lists. This enables the support of complex queries that are traditionally hard to specify in node-link visualizations. NetLens is general and scalable in that it applies to any dataset that can be represented with our abstract content-actor data model
1712871
Quasi-interpolants Based Multilevel B-Spline Surface Reconstruction from Scattered Data
This paper presents a new fast and local method of 3D surface reconstruction for scattered data. The algorithm makes use of quasi-interpolants to compute the control points from a coarse to fine hierarchy to generate a sequence of bicubic B-spline functions whose sum approaches to the desired interpolation function. Quasi-interpolants gives a procedure for deriving local spline approximation methods where a B-spline coefficient only depends on data points taken from the neighborhood of the support corresponding B-spline. Experimental results demonstrate that high-fidelity reconstruction is possible from a selected set of irregular samples.
29035719
Extracting User Profiles from E-mails Using the Set-Oriented Classifier
More and more people rely on e-mails rather than postal letters to communicate to each other. Although e-mails are more convenient, letters still have many positive features. The ability to handle "anonymous recipient" is one of them. This paper proposes a software agent that performs the routing task as human beings for the anonymous recipient e-mails. The software agent named "TWIMC (To Whom It May Concern)" receives anonymous recipient e-mails, analyze it, and then routes the e-mail to the mostly qualified person (i.e., email account) inside the organization. The agent employs the Set-oriented Classifier System (SCS) that is a genetic algorithm classifier that uses set representation internally. The comparison of SCS with the Support Vector Machine (SVM) shows that the SCS outperforms SVM under noisy environment.