33293331
Portable transparent checkpointing for distributed shared memory
We present a checkpointing mechanism for a DSM system that, in spite of being invisible to the programmer, is quite efficient and portable. It is efficient because it is nonblocking, coordinated and thus domino-effect free. It offers some portability because it is built on top of MPI and uses only the services offered by MPI and a POSIX compliant local file system. As far as we know, this is the first real implementation of such a scheme for DSM. Along with the description of the algorithms used, we present experimental results obtained in a cluster of workstations, and discuss many insights that came out of the implementation effort. We hope that our research shows that efficient, transparent and portable checkpointing is viable for DSM systems.
7711926
A flexible mobile-agent framework for accessing information systems in disconnected computing environments
Over the last few years, the importance of mobile computing has been steadily increasing. While it is important to provide support for accessing databases in disconnected computing environments, many of the information systems being deployed today are using a three-tier architecture. It is becoming vital to find ways of providing reliable access to the business logic present in the middle-tier for mobile applications. The authors present a component based framework that enables client applications to send mobile agents to interact with application servers in disconnected computing environments. This framework allows the applications to benefit from the advantages of using mobile agents in disconnected computing environments, and at the same time provides integration between mobile clients and corporate information systems.
12469936
JAMES: A Platform of Mobile Agents for the Management of Telecommunication Networks
This paper presents an overview of JAMES, a Java-based platform of mobile agents that is mainly oriented for the management of data and telecommunication networks. This platform has been developed on behalf of a Eureka Project (Σ!1921) and the project partners are Siemens SA, University of Coimbra and Siemens AG. We describe the main architecture of the platform giving more emphasis to the most important features. To show the effectiveness of some of the techniques that have been implemented we will present some performance results that compare the JAMES platform with the Aglets Workbench. 
 
The main target of our platform is network management and telecommunication applications. In this line, we have done a Java-based implementation of SNMP that has been integrated within the platform. The industrial partners of our project (i.e. Siemens S.A.) have developed a prototype application for TMN performance management. Although it is still a prototype it is being used to validate the technological advantages of using mobile agents in the management of telecommunication networks.
35428904
Portable checkpointing and recovery
This paper presents a checkpointing scheme that was implemented in a parallel library that runs on top of CHIMP/MPI. The main goals of the checkpointing mechanism are portability and efficiency. It runs on every platform supported by MPI in a machine-independent way. The scheme allows the migration of checkpoints and offers a flexible recovery mechanism based on data-reconfiguration. Some performance results will be presented at the end of the paper together with some techniques that can be used to increase the efficiency of the checkpointing mechanism.
9570610
Towards Manageable Mobile Agent Infrastructures
This paper addresses the problem of managing distributed mobile agent infrastructures. First, the weaknesses of current mobile agent implementations will be discussed and identified from the manageability viewpoint. The solutions devised and experimented in order to alleviate these weaknesses in our own agent platform will then be presented. These solutions are generic and could easily be applied to the majority of existing mobile agent implementations. The paper will finish with the discussion of a new approach we are following in the M&M Project, based on a rather different architecture that significantly reduces the manageability requirements.
18538603
Sharing checkpoints to improve turnaround time in desktop grid computing
In this paper, we present a checkpoint sharing methodology to improve turnaround time of applications run over desktop grid environments. In fact, volatility of desktop grid nodes reduces the efficiency of such environments when a fast turnaround time is sought, since a task might get stalled if its assigned machine remains unavailable for a somewhat long period of time (long at the scale of the computation). The rationale behind our approach is to permit checkpoint reuse, so that when a computation is forced to move from one node to another, it can be restarted from an intermediary point provided by the last saved checkpoint. We study the effects of sharing checkpoints in application turnaround time simulating three scheduling algorithms based on first come first served: FCFS, FCFS-AT and FCFS-TR. The targeted environment consists of institutional desktop grids. Our results show that sharing checkpoints is particularly effective in volatile environments, yielding performance improvement up to three times relatively to schemes based on private checkpoints. Furthermore, for non-volatile environments, a simple timeout strategy produces good results.
14564941
PetroGrapher: managing petrographic data and knowledge using an intelligent database application
This paper describes the PetroGrapher system, an intelligent database application to support petrographic analysis, interpretation of oil reservoir rocks, and management of relevant data using resources from both knowledge-based system technology and database technology. In this project, the visual tacit knowledge applied in petrographic analysis was rendered explicit through the collection of cases (rock descriptions), which were then used in the development of a domain ontology organized in a partonomy. Expert-level basic features, which we call ‘visual chunks’, were identified. The cases were further compared against the ontology to elucidate the relations between features in descriptions of rocks, visual chunks and expert interpretations. The domain knowledge was represented through a set of frames and knowledge graphs. The knowledge graphs are applied to recognize the visual chunks in the user data and retrieved the related interpretation. The system was developed as a structure tightly coupled with a relational database system, which acts as a repository for the knowledge base and the user data, and an object-oriented component, which preserves the semantics of data and develops inferences. The system was validated by three groups of users with different levels of expertise. q 2003 Elsevier Ltd. All rights reserved.
10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
15163719
Solving satisfiability in combinational circuits
As EDA evolves, researchers continue to find modeling tools to solve problems of test generation, design verification, logic, and physical synthesis, among others. One such modeling tool is Boolean satisfiability (SAT), which has very broad applicability in EDA. The authors review modern SAT algorithms, show how these algorithms can account for structural information in combinational circuits, and explain what recursive learning can add to SAT.
9436195
Satisfiability models and algorithms for circuit delay computation
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.