10513438
Orientation-Selective aVLSI Spiking Neurons
We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.
34951314
Spike synchronization in a network of silicon integrate-and-fire neurons
Spike-event based computational processing by neuronal networks depends on a variety of spatio-temporal mechanisms that are distributed across neuronal synapses, dendrites, and somata. The overall processing of spatio-temporal patterns of spike requires global temporal coherence between all these processes both within a neuron, and across all neurons of the network. We are evaluating the use of networks of hybrid analog-digital integrate-and-fire neurons, fabricated using VLSI, for studying real-time event-based processing. These hardware networks have the advantages of real-time operation, and inherent global synchronization by their analog implementation. However, one of the technical challenges in the operation of such networks is the unavoidable fabrication related variance between the different neurons of the network. Here we show that despite this variance, an important behavior of neuronal networks, spike synchronization, can be obtained from a simple network of VLSI neurons interconnected by lateral excitation and global inhibition.
1845062
Adaptive Retina with Center-Surround Receptive Field
Both vertebrate and invertebrate retinas are highly efficient in extracting contrast independent of the background intensity over five or more decades. This efficiency has been rendered possible by the adaptation of the DC operating point to the background intensity while maintaining high gain transient responses. The center-surround properties of the retina allows the system to extract information at the edges in the image. This silicon retina models the adaptation properties of the receptors and the antagonistic center-surround properties of the laminar cells of the invertebrate retina and the outer-plexiform layer of the vertebrate retina. We also illustrate the spatio-temporal responses of the silicon retina on moving bars. The chip has 59×64 pixels on a 6.9×6.8mm2 die and it is fabricated in 2 µm n-well technology.
18592302
A Winner-Take-All Circuit with Controllable Soft Max Property
I describe a silicon network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths. This output models the normalization property of the wide-field direction-selective cells in the fly visual system. This normalizing property is also useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit with one additional transistor and a voltage reference. Just as in Lazzaro's circuit, the outputs of the excitatory neurons code the neuron with the largest input. The difference here is that multiple winners can be chosen. By varying the voltage reference of the neuron, the network can transition between a soft-max behavior and a hard WTA behavior. I show results from a fabricated chip of 20 neurons in a 1.2 µm CMOS technology.
12793172
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 /spl mu/m CMOS technology are in agreement with the analysis.<<ETX>>
6979172
Encoding the Temporal Statistics of Markovian Sequences of Stimuli in Recurrent Neuronal Networks
Encoding, storing, and recalling a temporal sequence of stimuli in a neuronal network can be achieved by creating associations between pairs of stimuli that are contiguous in time. This idea is illustrated by studying the behavior of a neural network model with binary neurons and binary stochastic synapses. The network extracts in an unsupervised manner the temporal statistics of the sequence of input stimuli. When a stimulus triggers the recalling process, the statistics of the output patterns reflects those of the input. If the sequence of stimuli is generated through a Markov process, then the network dynamics faithfully reproduces all the transition probabilities.
5842197
Configurable indexing and ranking for XML information retrieval
Indexing and ranking are two key factors for efficient and effective XML information retrieval. Inappropriate indexing may result in false negatives and false positives, and improper ranking may lead to low precisions. In this paper, we propose a configurable XML information retrieval system, in which users can configure appropriate index types for XML tags and text contents. Based on users' index configurations, the system transforms XML structures into a compact tree representation, Ctree, and indexes XML text contents. To support XML ranking, we propose the concepts of "weighted term frequency" and "inverted element frequency," where the weight of a term depends on its frequency and location within an XML element as well as its popularity among similar elements in an XML dataset. We evaluate the effectiveness of our system through extensive experiments on the INEX 03 dataset and 30 content and structure (CAS) topics. The experimental results reveal that our system has significantly high precision at low recall regions and achieves the highest average precision (0.3309) as compared with 38 official INEX 03 submissions using the strict evaluation metric.
1976770
Self-independent Petri Nets for Distributed Systems
We propose that asynchronous mechanism for communication should be considered as a primitive for semantic models of distributed systems in contrast to the synchronous mechanism (hand-shaking) of CSP (Hoare, 1985) and of CCS (Milner, 1989). By doing so, we present an approach to producing a deadlock-free system, and give a denotational model for CCS in a non-interleaving fashion.
14632854
An Approach to Integration Testing Based on Data Flow Specifications
Integration testing of programs based on formal specifications can benefit considerably from the comprehensibility of specifications. In this paper, we describe an approach to testing programs based on data-flow-oriented specifications by analyzing data flow paths and discussing criteria for test case generation. This approach suggests a specific way to generate test cases directly from formalized data flow diagrams and the associated textual specifications. We apply the approach in a case study of testing part of an ATM system to evaluate its effectiveness in fault detection and to uncover its weakness for further improvement.
14652555
Adding multi-class routing into the DiffServ architecture
To alleviate the problem of high priority traffic hogging of all the available network capacity and to optimize the network traffic in the DiffServ network, we introduce the multi-class routing (MCR) scheme into the DiffServ architecture. The MCR scheme that builds multiple routing tables in the DiffServ routers forms the MCR DiffServ architecture. In this paper, the MCR DiffServ architecture focuses on the intra-DS domain. Different MCR approaches that include a static approach and dynamic approaches can be used for the MCR DiffServ system. We extend the OSPF protocol in order to build up more than one routing table in each MCR DiffServ system. According to the extensions to OSPF, we have implemented the static MCR approach for the MCR DiffServ system on the basis of the open source Zebra software.
1315911
An Object Semantic Model of SOFL
SOFL (Structured-Object-based-Formal Language) is recently proposed to combine the advantages of formal methods, structured methods and object-oriented methodology into one method for software development. SOFL integrates modeling techniques from VDM (for specifying system component state) and data flow diagrams with Petri nets (for specifying system behaviours and interaction). To support the standardisation and the tool support for SOFL, a formal semantics of the language is desirable. As SOFL is under further development, the semantic representation of current SOFL needs to be easily reused and extended. In this paper, an object-oriented approach is taken to specify the semantics of SOFL and this approach is proved to be effective in providing a modular and reusable semantic representation. Object modeling techniques, such as inheritance is used to illustrate the common and the differences between various SOFL graphical constructs; object containment is used to capture the acyclic structure of SOFL hierarchical module decomposition.