9249416
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB non-uniform (NUCA) on-chip memory system
4382018
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
This paper describes the polymorphous TRIPS architecture that can be configured for different granularities and types of parallelism. The TRIPS architecture is the first in a class of post-RISC, dataflow-like instruction sets called explicit data-graph execution (EDGE). This EDGE ISA is coupled with hardware mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrency, the TRIPS architecture prototype contains two out-of-order, 16-wide-issue grid processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes---ILP, TLP, and DLP---demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.
12867787
I Am Fine but You Are Not: Optimistic Bias and Illusion of Control on Information Security
Information security is a critically important issue in current networked business and work environments. While there is extensive publicity on the increasing incidents of numerous information security breaches and their serious consequences, recent surveys and research on information security repeatedly identify the low levels of user and managerial awareness as a key obstacle to achieving a good information security posture. The main motivation of our research emanates from this contradicting phenomenon: increased vulnerability to information security breaches yet the low level of user and managerial awareness on information security threats. In this research, we study this dissonance by addressing a cognitive bias, optimistic bias, that is, the tendency of people to believe that negative events are less likely to happen to them than to others and that positive events are more likely to happen to them than others. Using a survey, we find that users demonstrate optimistic bias in their risk perceptions associated with information security. This self-serving bias is also found to be related to a perception of controllability with information security threats. These results have practical implications for designing security awareness programs by suggesting that risk communication and management efforts are likely to fail unless they consider this bias.
42768359
Hardware-Accelerated Real-Time Rendering for 3D Sumi-e Painting
This paper presents a method for real-time 3D Sumi-e rendering using normal graphics hardware. Sumi-e is one of the traditional oriental painting styles. Most research on Sumi-e paintings has focused on 2D or 2.5D Sumi-e brushwork simulation. On these systems, complicated user's hand drawing is required to generate the image of Sumi-e effects, and it can render the 2D or 2.5D Sumi-e images only. We present an automated rendering system for 3D image of Sumi-e painting. It uses 3D common object as an input data and does not need any additional input of user brushwork. Especially for the real-time rendering, hardware-accelerated algorithm for Sumi-e rendering is newly suggested in our system. It is designed with efficiency for customer level graphics hardware. The results of this paper show that the features of traditional Sumi-e painting are successfully modeled and that 3D Sumi-e painting is rendered in real-time effectively.
12552933
TTS without Revocation Capability Secure Against CCA2
A traitor tracing scheme (TTS) deters traitors from giving away their secret keys to decrypt the transmitted data by enabling the system manager to trace at least one of the traitors who participated in the construction of a pirate decoder after confiscating it. In an asymmetric scheme, the system manager is also under suspicion, so the system manager must convince a judge of the implication of the traitors. Recently, Kiayias and Yung proposed an asymmetric public key traitor tracing scheme [13]. However, their scheme does not provide CCA2 security even if a single user is a traitor. That is, their scheme is secure against adaptive chosen ciphertext (CCA2) attack only when there is no traitor. In this paper, we first introduce the security notion against CCA2 attack in a traitor tracing scheme with no revocation capability. This notion is somewhat different from the traditional security notion against CCA2 attack in a two-party encryption scheme [5]. To the best of our knowledge, no security notion against CCA2 attack in a traitor tracing scheme with no revocation capability has been presented. In addition, we modify the Kiayias and Yung’s scheme to achieve security against CCA2 attack under the decision Diffie-Hellman assumption and the collision-resistant hash function assumption.
11427398
New Key Recovery in WAKE Protocol
Wireless authentication and key establishment (WAKE) protocols are essential in mobile communications. The key recovery mechanism may also be required in mobile communication systems for the investigation of serious crimes and for national security. Recently some protocols that give key recovery in the WAKE protocol have been published. In this paper we propose new key recovery protocols that improve previous protocols in security and efficiency.
7848399
Model-driven software product lines
Model-driven software product lines combine the abstraction capability of Model Driven Software Development (MDSD) and the variability management capability of Software Product Line Engineering (SPLE). This short contribution motivates the idea of model-driven software product lines and briefly explains the concepts underlying feature-based model templates, which is a particular technique for modeling software product lines.