12048501
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Crosstalk aggressor alignment induces significant interconnect delay variation and needs to be taken into account in a statistical timer. In this paper, we approximate crosstalk aggressor alignment induced interconnect delay variation in a piecewise-quadratic function, and present closed form formulas for statistical interconnect delay calculation with crosstalk aggressor alignment variation. Our proposed method can be easily integrated in a statistical timer, where traditional corner-based timing windows are replaced by probabilistic distributions of crosstalk aggressor alignment, which can be refined by similar delay calculation iterations. Runtime is O(N) for initial delay calculation of N sampling crosstalk aggressor alignments, while pdf propagation and delay updating requires constant time. We compare with SPICE Monte Carlo simulations on Berkeley predictive model 70nm global interconnect structures and 130nm industry design instances. Our experimental results show that crosstalk aggressor alignment oblivious statistical delay calculation could lead to up to 114.65% (71.26%) mismatch of interconnect delay means (standard deviations), while our method gives output signal arrival time means (standard deviations) within 2.09% (3.38%) of SPICE Monte Carlo simulation results.
1437746
On the skew-bounded minimum-buffer routing tree problem
Bounding the load capacitance at gate outputs is a standard element in today's electrical correctness methodologies for high-speed digital very large scale integration design. Bounds on load caps improve coupling-noise immunity, reduce degradation of signal transition edges, and reduce delay uncertainty due to coupling noise (Kahng et al. 1998). For clock and test distribution, an additional design requirement is bounding the buffer skew, i.e., the difference between the maximum and the minimum number of buffers over all of the source-to-sink paths in the routing tree, since buffer skew is one of the main factors affecting delay skew (Tellez and Sarrafzadeh 1997). In this paper, we consider algorithms for buffering a given tree with the minimum number of buffers under given load cap and buffer skew constraints. We show that the greedy algorithm proposed by Tellez and Sarrafzadeh is suboptimal for nonzero buffer-skew bounds and give examples showing that no bottom-up greedy algorithm can achieve optimality. The main contribution of the paper is an optimal dynamic programming algorithm for the problem. Experiments on test cases extracted from recent industrial designs show that the dynamic programming algorithm has practical running time and saves up to 37.5% of the buffers inserted by Tellez and Sarrafzadeh's algorithm.
6291223
Interconnect implications of growth-based structural models for VLSI circuits
Power-law scaling phenomena that govern VLSI circuits have for several decades formed the foundation of VLSI interconnect estimation.   This research investigates possible alternative power-law phenomena in VLSI circuits.   In particular, we develop new<italic>random growth</italic>models and assess their implications for VLSI interconnect structure.   We assess our models' predictions for<italic>fanout</italic>,<italic>crossing edge</italic>, and<italic>terminal</italic>scaling using test data from 21 industry standard-cell designs with up to 283K cells.   Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.
53249400
Non-tree routing for reliability and yield improvement
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduced at the cost of increased potential for short faults; overall, manufacturing yield and fault tolerance can be improved. We focus on a post-processing, tree augmentation approach which can be easily integrated in current physical design flows. Experiments on randomly generated and industry testcases show that our greedy augmentation method achieves significant increase in reliability (as measured by the percentage of biconnected tree edges) with very small increase in wirelength. SPICE simulations imply that non-tree routing has smaller delay variation due to process variability.
5760901
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significant as multiple-input switching on gate delay variation [2]. We establish a functional relationship between driver gate delay and crosstalk alignment by deterministic circuit simulation, and derive closed form formulas for statistical distributions of driver gate delay and output signal arrival time.Our proposed method can be smoothly integrated into a static timing analyzer, which runtime is dominated by sampling deterministic delay calculation, while probabilistic computation and updating take constant time. Our experimental results on 70nm technology global interconnect structures and 130nm technology industry designs show respectively 159:4% and 147:4% differences in mean and standard deviation of gate delay without crosstalk aggressor alignment consideration, while our method gives within 2:57% and 3:86% offset in gate output signal arrival time mean and standard deviation, respectively.
1873553
Toward better wireload models in the presence of obstacles
Efficient and accurate interconnect estimation is crucial to design convergence. With System-on-Chip design, IP blocks form routing obstacles that cannot be accounted for by existing a priori wirelength estimations. In this paper, we identify two distinct effects of obstacles on interconnection length: (i) changes due to the redistribution of interconnect terminals and (ii) detours that have to be made around the obstacles. Theoretical expressions of both effects for point-to-point nets with a single obstacle are derived and compared to experimental observations. We also experimentally assess these effects for multi-terminal interconnections and in the presence of multiple obstacles. We single out cases where the effects are additive, which suggests the use of lookup tables and equivalent blockage relations. Our results are applicable in chip planning tools, where they enable improved accounting for obstacles in a priori wirelength estimation schemes.
14440312
Fluid Simulation of Large Scale Networks: Issues and Tradeoffs
Traditional discrete-event packet-level approaches to simulating computer networks become computationally infeasible as the number of network nodes or their complexity increases. An alternative approach, in which packet-level traffic sources are replaced by fluid sources, has been proposed to address this challenge. In this paper we compare the amount of computational effort needed to simulate a network using a packet-level approach versus a fluid-based approach. We quantitatively characterize the amount of computational effort needed by each approach using the notion of a simulation’s event rate, and derive expressions for the event rate of a packet and fluid flow at both the input and output sides of a queue. We show that fluid simulation can require less computational effort for simple networks. However, as the network size and complexity grow, the so-called ”ripple effect” can result in fluid simulations becoming more expensive than their packet-level counterparts. This suggests that time-driven (approximate) fluid simulation techniques may be needed to efficiently simulate large scale networks.
10886416
Prediction and indexing of moving objects with unknown motion patterns
Existing methods for peediction spatio-temporal databases assume that objects move according to linear functions. This severely limits their applicability, since in practice movement is more complex, and individual objects may follow drastically diffferent motion patterns. In order to overcome these problems, we first introduce a general framework for monitoring and indexing moving objects, where (i) each boject computes individually the function that accurately captures its movement and (ii) a server indexes the object locations at a coarse level and processes queries using a filter-refinement mechanism. Our second contribution is a novel recursive motion function that supports a broad class of non-linear motion patterns. The function does not presume any a-priori movement but can postulate the particular motion of each object by examining its locations at recent timestamps. Finally. we propse an efficient indexing scheme that faciliates the processing of predicitive queries without false misses.
5712150
Preemptive Packet-Mode Scheduling to Improve TCP Performance
Recent Internet traffic measurements show that 60% of the total packets are short packets, which include TCP acknowledgment and control segments. These short packets make a great impact on the performance of TCP. Unfortunately, short packets suffer from large delay due to serving long data packets in switches running in the packet mode, i.e. a packet is switched in its entirety. To optimize TCP performance, we apply a cross-layer approach to the design of switching architectures and scheduling algorithms. Specifically, we propose a preemptive packet-mode scheduling architecture and an algorithm called preemptive short packets first (P-SPF). Analysis and simulation results demonstrate that compared to existing packet-mode schedulers, P-SPF significantly reduces the waiting time for short packets while achieving a high overall throughput when the traffic load is heavy. Moreover, with a relatively low speedup, P-SPF performs better than existing packet-mode schedulers under any traffic load.
8584874
Throughput Optimization and Fair Bandwidth Allocation in Multi-Hop Wireless LANs
There is an inherent well-known conflict between fairness and throughput that arises in many networking scenarios. A number of researchers have studied this problem in the context of (single-hop) wireless local area networks (WLANs), where clients directly exchange traffic with access points (APs). More recently, researchers have proposed multi-hop extensions to WLANs where client traffic is forwarded via a series of client-client links. In this paper, we show that the objective of improving throughput without sacrificing fairness can be much better met in multi-hop WLANs. We decouple this objective into two separate but related problems. First, we need an algorithm to organize clients into a multi-hop structure such that fair bandwidth allocation within this structure leads to improved throughput. Second, we need algorithms for performing fair bandwidth allocation within the determined multi-hop structure. In this paper, we first design optimal fair bandwidth allocation algorithms for both max-min throughput fairness and max-min time fairness in multi-hop WLANs. Subsequently, we design an efficient algorithm to find desirable multi-hop structures. With slight modifications, our results in this paper can be generalized to other multi-hop wireless networks as well. Our proposed solutions seamlessly integrate with legacy devices and hence are incrementally deployable. Simulation results demonstrate that our solutions can effectively improve throughput (by up to 114% or more) as well as network coverage while preserving fairness.
3063801
Iteration-Shared Scheduling Algorithms Abolishing the Departure-Time-Compatible Graph in Switch-Memory-Switch Switches
Switch-Memory-Switch (SMS) architecture exhibits an excellent performance due to its emulating the Output Queueing structure. However, in order to achieve the maximal matching, the first stage scheduling operates at a huge computational complexity, which blocks the SMS from practical implementation. In order to put SMS into more effective industrial applications, especially in super-large size switches/routers with multi-services environment, two parallel iterative scheduling algorithms, named IS-RRM and AIS-RRM respectively, are proposed in this paper. The algorithms abolish totally the traditional departure-time-compatible (DTC) graph, and by using iteration-sharing technology, greatly reduce the required iteration number in each time slot. Using a discrete-time Markov chain to model the AIS-RRM algorithm, we obtain its upper bound of cell loss rate. Meanwhile, experimental and theoretical results show that so long as the number of shared memories is twice the switch size, AIS-RRM algorithm can achieve a cell loss rate of 10 when the input buffer size is 15 and the iteration number of each time slot is 6, despite the arrival traffic pattern and the switch size. Furthermore, the iteration number required in each time slot can be further decreased by increasing the input buffer size.