1039631
New Conditions for k-ordered Hamiltonian Graphs
We show that in any graph G on n vertices with d(x) + d(y) ≥ n for any two nonadjacent vertices x and y, we can fix the order of k vertices on a given cycle and find a hamiltonian cycle encountering these vertices in the same order, as long as k < n/12 and G is d(k + 1)/2e-connected. Further we show that every b3k/2cconnected graph on n vertices with d(x) + d(y) ≥ n for any two nonadjacent vertices x and y is k-ordered hamiltonian, i.e. for every ordered set of k vertices we can find a hamiltonian cycle encountering these vertices in the given order. Both connectivity bounds are best possible.
9764979
Tough enough chordal graphs are Hamiltonian
43538481
Vertex-disjoint cycles containing specified vertices in a bipartite graph
A minimum degree condition is given for a bipartite graph to contain a 2-factor each component of which contains a previously specified vertex. 2004 Wiley Periodicals, Inc. J Graph Theory 46: 145–166, 2004
3744350
Hamiltonian graphs involving neighborhood unions
Dirac proved that a graph G is hamiltonian if the minimum degree δ(G) ≥ n/2, where n is the order of G. Let G be a graph and A ⊆ V(G). The neighborhood of A is N(A) = {b : ab ∈ E(G) for some a ∈ A}. For any positive integer k, we show that every (2k − 1)-connected graph of order n ≥ 16k is hamiltonian if |N(A)| ≥ n/2 for every independent vertex set A of k vertices. The result contains a few known results as special cases. The case of k = 1 is the classic result of Dirac when n is large and the case of k = 2 is a result of Broersma, Van den Heuvel, and Veldman when n is large. For general k, this result improves a result of Chen and Liu. The lower bound 2k − 1 on connectivity is best possible in general while the lower bound 16k for n is conjectured to be unnecessary. © 2006 Wiley Periodicals, Inc. J Graph Theory 53: 83–100, 2006
44728169
A New Game Chromatic Number
Consider the following two-person game on a graphG.Players I and II move alternatively to color a yet uncolored vertex ofGproperly using a pre-specified set of colors. Furthermore, Player II can only use the colors that have been used, unless he is forced to use a new color to guarantee that the graph is colored properly. The game ends when some player can no longer move. Player I wins if all vertices ofGare colored. Otherwise Player II wins. What is the minimal number?g*(G)of colors such that Player I has a winning strategy? This problem is motivated by the game chromatic number?g(G)introduced by Bodlaender and by the continued work of Faigle, Kern, Kierstead and Trotter. In this paper, we show that?g*(T) ?3for each treeT.We are also interested in determining the graphsGfor which?(G)= ?g*(G),as well as?g*(G)for thek-inductive graphs wherekis a fixed positive integer.
23991617
Ramsey Problems With Bounded Degree Spread
30765152
On the Quickest Path Problem
Abstract Let N be an input network and σ be the amount of data to be transmitted. We present an O( mn 2 ) time algorithm that finds all-pairs quickest paths, for a given value of σ, and show that the quickest path between any two nodes for any value of σ can be found in O(log m ) time, provided O( mn 2 ) preprocessing time is spent.
5198300
Compiler-directed channel allocation for saving power in on-chip networks
Increasing complexity in the communication patterns of embedded applications parallelized over multiple processing units makes it difficult to continue using the traditional bus-based on-chip communication techniques. The main contribution of this paper is to demonstrate the importance of compiler technology in reducing power consumption of applications designed for emerging multi processor, NoC (Network-on-Chip) based embedded systems. Specifically, we propose and evaluate a compiler-directed approach to NoC power management in the context of array-intensive applications, used frequently in embedded image/video processing. The unique characteristic of the compiler-based approach proposed in this paper is that it increases the idle periods of communication channels by reusing the same set of channels for as many communication messages as possible. The unused channels in this case take better advantage of the underlying power saving mechanism employed by the network architecture. However, this channel reuse optimization should be applied with care as it can hurt performance if two or more simultaneous communications are mapped onto the same set of channels. Therefore, the problem addressed in this paper is one of reducing the number of channels used to implement a set of communications without increasing the communication latency significantly. To test the effectiveness of our approach, we implemented it within an optimizing compiler and performed experiments using twelve application codes and a network simulation environment. Our experiments show that the proposed compiler-based approach is very successful in practice and works well under both hardware based and software based channel turn-off schemes.
40616325
A Color Bar Based Affective Annotation Method for Media Player
Multimedia technology has been developing quickly since the computer was invented. Nowadays, more and more people use media players to watch movies and TV shows on their computer. But it seems that we are too busy sometimes to spare nearly two hours watching a movie from beginning to end. We’d like to find and watch the most exciting episodes that we are interested in as soon as possible. The media players we use often only provide a slider bar for locating, which is rather low in efficiency. Respecting this, an affective annotation method for video clips is proposed in this paper and the method is implemented in an affectively annotated media player. In addition, two experiments were set up to evaluate the proposed method. Experiment results indicate that affective annotation facilitates the subjects in quick locating target events and helps them understand the scenarios better.
15399936
Compiler-guided leakage optimization for banked scratch-pad memories
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
5984361
Improving Java virtual machine reliability for memory-constrained embedded systems
Dual-execution/checkpointing based transient error tolerance-techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very attractive for cost-sensitive embedded systems because they require extra resources (e.g., large memory, special hardware, etc), and thus increase overall cost of the system. In this paper, we propose a transient error tolerant Java virtual machine (JVM) implementation for embedded systems. Our JVM uses dual-execution and checkpointing to detect and recover from transient errors. However, our technique does not require any special hardware support (except for the memory page protection mechanism, which is commonly available in modern embedded processors), and the memory space overhead it incurs is not excessive. Therefore, it is suitable for memory-constrained embedded systems. We implemented our approach and performed experiments with seven embedded Java applications.