9506912
Quantifying Input and Output Spike Statistics of a Winner-Take-All Network in a Vision System
Event-driven spike-based processing systems offer new possibilities for real-time vision. Signals are encoded asynchronously in time thus preserving the time information of the occurrence of an event. The paper examines this form of coding using experimental data from a multi-layered multi-chip system which consists of an artificial retina, a convolution filter bank and a winner-take-all network which detect the position of a moving object. The spike outputs of the convolution stage can be described by an inhomogeneous Poisson distribution of Gaussian profile, although the underlying building blocks are completely deterministic and exhibit only a small amount of variation. The authors discuss a method for measuring the accuracy of the asynchronous spiking representation in both time and value, thereby quantifying the performance of the winner-take-all network in determining the position of a ball rotating in front of the system.
34951314
Spike synchronization in a network of silicon integrate-and-fire neurons
Spike-event based computational processing by neuronal networks depends on a variety of spatio-temporal mechanisms that are distributed across neuronal synapses, dendrites, and somata. The overall processing of spatio-temporal patterns of spike requires global temporal coherence between all these processes both within a neuron, and across all neurons of the network. We are evaluating the use of networks of hybrid analog-digital integrate-and-fire neurons, fabricated using VLSI, for studying real-time event-based processing. These hardware networks have the advantages of real-time operation, and inherent global synchronization by their analog implementation. However, one of the technical challenges in the operation of such networks is the unavoidable fabrication related variance between the different neurons of the network. Here we show that despite this variance, an important behavior of neuronal networks, spike synchronization, can be obtained from a simple network of VLSI neurons interconnected by lateral excitation and global inhibition.
1845062
Adaptive Retina with Center-Surround Receptive Field
Both vertebrate and invertebrate retinas are highly efficient in extracting contrast independent of the background intensity over five or more decades. This efficiency has been rendered possible by the adaptation of the DC operating point to the background intensity while maintaining high gain transient responses. The center-surround properties of the retina allows the system to extract information at the edges in the image. This silicon retina models the adaptation properties of the receptors and the antagonistic center-surround properties of the laminar cells of the invertebrate retina and the outer-plexiform layer of the vertebrate retina. We also illustrate the spatio-temporal responses of the silicon retina on moving bars. The chip has 59×64 pixels on a 6.9×6.8mm2 die and it is fabricated in 2 µm n-well technology.
12793172
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 /spl mu/m CMOS technology are in agreement with the analysis.<<ETX>>
18592302
A Winner-Take-All Circuit with Controllable Soft Max Property
I describe a silicon network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths. This output models the normalization property of the wide-field direction-selective cells in the fly visual system. This normalizing property is also useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit with one additional transistor and a voltage reference. Just as in Lazzaro's circuit, the outputs of the excitatory neurons code the neuron with the largest input. The difference here is that multiple winners can be chosen. By varying the voltage reference of the neuron, the network can transition between a soft-max behavior and a hard WTA behavior. I show results from a fabricated chip of 20 neurons in a 1.2 µm CMOS technology.
6979172
Encoding the Temporal Statistics of Markovian Sequences of Stimuli in Recurrent Neuronal Networks
Encoding, storing, and recalling a temporal sequence of stimuli in a neuronal network can be achieved by creating associations between pairs of stimuli that are contiguous in time. This idea is illustrated by studying the behavior of a neural network model with binary neurons and binary stochastic synapses. The network extracts in an unsupervised manner the temporal statistics of the sequence of input stimuli. When a stimulus triggers the recalling process, the statistics of the output patterns reflects those of the input. If the sequence of stimuli is generated through a Markov process, then the network dynamics faithfully reproduces all the transition probabilities.
15677254
Inference Queues for Communicating and Monitoring Declarative Information between Web Services
We introduce the inference queue as a mechanism for communicating and transforming data in Web services choreography. The insert operation provides definite clauses to the inference queue, and the remove operation generates output that is sound, complete, fair, and irredundant. Both operations are thread safe and responsive. The inference queue can form part of a highly configurable data transformation system. Rules can also monitor for events of interest based on the occurrence of certain conditions. Our suggestion of system wide monitoring of communication is complementary to existing Web services proposals.
7866306
Two-level assurance of QoS requirements for distributed real-time and embedded systems
Assuring quality of service (QoS) requirements is critical when assembling a distributed real-time and embedded (DRE) system from a repository of existing software and hardware components. This paper presents a two-level approach for assuring satisfaction of QoS requirements in the context of a reduced design space for DRE systems. Techniques from artificial intelligence and statistics are used to fulfill these collective objectives at system assembly time. The result not only lessens the overhead of validation of QoS requirements at run-time, but also reduces the development and integration cost of DRE systems.
11705717
Generating test data from state-based specifications
SUMMARY Although the majority of software testing in industry is conducted at the system level, most formal research has focused on the unit level. As a result, most system-level testing techniques are only described informally. This paper presents formal testing criteria for system level testing that are based on formal specifications of the software. Software testing can only be formalized and quantified when a solid basis for test generation can be defined. Formal specifications represent a significant opportunity for testing because they precisely describe what functions the software is supposed to provide in a form that can be automatically manipulated. This paper presents general criteria for generating test inputs from state-based specifications. The criteria include techniques for generating tests at several levels of abstraction for specifications (transition predicates, transitions, pairs of transitions and sequences of transitions). These techniques provide coverage criteria that are based on the specifications and are made up of several parts, including test prefixes that contain inputs necessary to put the software into the appropriate state for the test values. The test generation process includes several steps for transforming specifications to tests. These criteria have been applied to a case study to compare their ability to detect seeded faults. Copyright c � 2003 John Wiley & Sons, Ltd.
14314870
Formalization, Testing and Execution of a Use Case Diagram
Errors in a requirements model have prolonged detrimental effects on reliability, cost, and safety of a software system. It is very costly to fix these errors in later phases of software development if they cannot be corrected during requirements analysis and design. A use case diagram, as a requirements model, plays an important role in giving requirements for a software system. It provides a communication tool between software requirements developers and prospective users to understand what requirements of a software system are. However most descriptions of a use case diagram are written in some informal language, leading to possible misunderstanding between developers and users. In this paper, we propose a new rigorous review technique which can be applied to software requirements models. Using this new technique before a software system is fully designed will help us find some potential errors in a requirements model, resulting in reduced time, labor and expenditure in software development.
11183356
Consequences for exchange energy density functional of exponentially decaying nature of atomic electron densities