8993397
A Novel Hybrid Crypto-Biometric Authentication Scheme for ATM Based Banking Applications
This paper studies the smartcard based fingerprint encrytion/auth-entication scheme for ATM banking systems. In this scheme, the system authenticates each user by both his/her possession (smartcard) and biometrics (fingerprint). A smartcard is used for the first layer of authentication. Based on the successful pass of the first layer authentication, a subsequent process of the biometric fingerprint authentication proceeds. The proposed scheme is fast and secure. Computer simulations and statistical analyze are presented.
38537514
A Biometric Encryption Approach Incorporating Fingerprint Indexing in Key Generation
This paper presents a new biometric encryption protocol in which encryption key is incorporated with fingerprint indexing. Based on the extended chaotic Baker map, the pixel permutation and gray level value substitution are performed to shuffle pixel positions in the original fingerprint images. The encryption key of the pixel permutation is generated by the combination of the random pixel distribution of a fingerprint imprint as well as features used for the fingerprint indexing. In addition to the advantage enjoyed by biometric keys over traditional password/PINs, the proposed biometric encryption approach is very efficient in identity identification within a large database due to the pre-filtering feature of the fingerprint indexing incorporated in the keys. This approach is applicable to the centralized matching scenario where fingerprints need to be encrypted before transmitted. Simulation results have validated the proposed schemes.
15489348
A Gradient Based Weighted Averaging Method for Estimation of Fingerprint Orientation Fields
Estimation of orientation fields is an essential module in a fingerprint recognition system. Conventional gradient based approaches are popular but very sensitive to noise. In this paper, we propose a new implementation that is more resistant to noise. Our basic idea is to conduct redundant estimation over four overlapping neighborhoods for each target block. Following this idea, we devise a weighted averaging scheme operated on the base blocks directly. Thus, each block (including the target one) in the overlapping neighborhoods has different impact on estimation of the dominant orientation fields. Our preliminary experiment results suggest that the proposed weighted averaging algorithm is more robust against noise in comparison with other gradient based methods.
18592986
Simulation Study of TCP Performance Over Mobile IPV4 and Mobile IPV6
Mobile IPv6 (MIPv6) is a protocol to deal with mobility for the next generation Internet (IPv6). However, the performance of MIPv6 has not yet been extensively investigated. Knowledge of how MIPv6 affects TCP performance, especially in comparison with MIPv4, can provide directions for further improvement. In this report, an intensive simulation study of TCP performance over MIPv4 and MIPv6 has been conducted. Simulation using the famous network simulator NS-2 will be used to highlight differences when TCP is used in hybrid wireless environment, over these two Mobile IP protocols. Initial simulation has shown a solid improvement in performance for MIPv6 when IPv6 Route Optimisation features are used. During the course of simulation, a consistent event causing dropped TCP throughput was identified. Out of order arrival of packets would occur when the mobile node initiated a handover. This out of order arrival invokes TCP congestion control falsely which reduces throughput. The difference in overall throughput of MIPv4 compared to MIPv6 is roughly proportional to the difference in packet size attributed to IPv6’s increased header size. Another contribution of this work is to provide modifications and new functions such as node processing time, to the NS-2 simulator to make such investigation possible. To the best of our knowledge, no similar publication has been reported.
18760651
Modelling of SACK TCP and application to the HTTP file transfer environment
It is known that analytic modelling for TCP latency is a non trivial task. Recently, some significant progress has been made, such as the comprehensive result by Sikdar et al. However, models similar to these often rely on trial and error methods such as "data fitting". This can lead to a very limited scope for the resulting model and also large estimation error. In this paper, we propose improvements to Sikdar's SACK TCP model. A new delayed acknowledgement slow start model is developed that is analytically derived from the slow start algorithm which provides a novel mechanism to model the relationship between RTT and the delayed acknowledgement timer. We introduce a simple mechanism to include time taken to send an HTTP get request to broaden the scope of our SACK TCP model to Website file transfer. Simulation and live Internet experimentation has validated our scheme
6719974
Intrusion Detection Based on Data Mining
18212343
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which consider only wire self capacitance become inadequate since the wire delay is affected more by coupling capacitance in ultra-deep submicron designs. Furthermore, the technology scaling dramatically increases the likelihood of the antenna problem in manufacturing and requests corresponding considerations in the routing stage. In this paper, we propose techniques that can be applied to handle the coupling aware timing and the antenna problem simultaneously during layer assignment which is an important step between global routing and detailed routing. An improved probabilistic coupling capacitance model is suggested for coupling aware timing optimization without performing track assignment. The antenna avoidance problem is modeled as a tree partitioning problem with a linear time optimal algorithm solution. This algorithm is customized to guide antenna avoidance in layer assignment. A linear time optimal jumper insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 270ps timing slack improvement validated by track assignment, 76% antenna violation reduction and 99% via violation reduction.
4069319
Attribute Reduction Based on Granular Computing
Attribute reduction is a very important issue in data mining and machine learning. Granular computing is a new kind of soft computing theory. A novel method for encoding granules using bitmap technique is proposed in this paper. A new attribute reduction method based on granular computing is also developed with this encoding method. It is proved to be efficient.
11408697
Path-Based Buffer Insertion
Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.
17009072
Steiner network construction for timing critical nets
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nano-scale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable. We propose Steiner network construction heuristics which can generate either tree or non-tree with different slack-wirelength tradeoff, and handle both long path and short path constraints. Incremental non-tree delay update techniques are developed to facilitate fast Steiner network evaluations. Extensive experiments in different scenarios show that our heuristics usually improve timing slack by hundreds of pico seconds compared to traditional tree approaches
15903312
Using dynamic branch behavior for power-efficient instruction fetch
Power consumption has become an increasing concern in high performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instruction cache contributes a large portion of the total power consumption in the microprocessor The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flows to boost performance, conventional trace caches (CTC) may increase power consumption in the fetch unit due to its simultaneous access to both the trace cache and the instruction cache. By avoiding this simultaneous accesses, sequential trace caches (STC) achieve lower power consumption, but suffer a significant performance loss at the meantime. In this paper we propose dynamic direction prediction based trace cache (DPTC) which avoids simultaneous accesses to the trace cache and the instruction cache with the guide of fetch direction prediction. Experimental results show that dynamic prediction based trace cache can achieve 38.5% power reduction over conventional trace caches and an additional 7.2% reduction over STC, on average, while only trading a 1.8% performance loss compared to CTC.