14018858
Single event burnout in power diodes: Mechanisms and models
Power electronic devices are susceptible to catastrophic failures when they are exposed to energetic particles; the most serious failure mechanism is single event burnout (SEB). SEB is a widely recognized problem for space applications, but it also may affect devices in terrestrial applications. This phenomenon has been studied in detail for power MOSFETs, but much less is known about the mechanisms responsible for SEB in power diodes. This paper reviews the current state-of-knowledge of power-diode vulnerability to SEB, based on both experimental and simulation results. It is shown that present models are limited by the lack of detailed descriptions of thermal processes that lead to physical failure.
10826914
Thermal modeling of single event burnout failure in semiconductor power devices
Abstract Experimental investigations of single event burnout (SEB) of power devices due to heavy ion impacts have identified the conditions required to produce device failure. A key feature observed in the data is an anomalistic secondary rise in current occurring shortly after the ion strike. To verify these findings including the thermally induced secondary plateau, simulations have been performed on the model single event burnout. The new models include additional thermally dependent electrical components to capture thermally induced physical effects. Through the inclusion of analytic temperature models coupled with the electrical model, the electrical response is predicted with reasonable accuracy. The simulations provide order-of-magnitude estimates as well as prediction of phenomenological features such as the secondary rise in current. This work represents a first attempt to characterize thermal failure of power devices due to heavy ion impacts by including temperature dependent components that until now have not been modeled. The thermal model in the present work produces qualitative agreement with experiments on SEB that have been previously unexplained.
1745513
Test generation for global delay faults
This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks.
37536130
On Encoding p-pi in m-pi
This paper is about the encoding of pπ, the polyadic π-calculus, in mπ, the monadic π-calculus. A type system for mπ processes is introduced which captures the interaction regime underlying the encoding of pπ processes respecting a sorting. A full-abstraction result is shown: two pπ processes are typed barbed congruent iff their mπ encodings are monadic-typed barbed congruent.
326056
A circuit level fault model for resistive bridges
Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these models are not efficient to use in delay tests for large circuits. In this article, we propose a physically realistic yet economical resistive bridge fault model to model delay faults as well as logic faults. An accurate yet simple delay calculation method is proposed. We also enumerate all possible fault behaviors and present the relationship between input patterns and output behaviors, which is useful in ATPG. Our fault simulation results show the benefit of at-speed tests.
21446187
Is IDDQ Test of Microprocessors Feasible?
Quiescent leakage current (Iddq) test has proven very effective for detecting defects that escape other test methods, such as small delay faults or reliability hazards. However, leakage currents in microprocessors, digital signal processors, and graphics processors have risen to the point that these products no longer use Iddq test. Quality must be achieved through other test methods, often at higher development and application cost. We propose to bring Iddq  test back to high performance chips by using a practical built-in current sensor (BICS). 180 nm test chip results show that a small sensor can achieve a resolution of 54 muA, which is adequate to detect most small delay defects and reliability hazards
8103128
Alias Types for Recursive Data Structures
Linear type systems permit programmers to deallocate or explicitly recycle memory, but are severely restricted by the fact that they admit no aliasing. This paper describes a pseudo-linear type system that allows a degree of aliasing and memory reuse as well as the ability to define complex recursive data structures. Our type system can encode conventional linear data structures such as linear lists and trees as well as more sophisticated data structures including cyclic and doubly-linked lists and trees. In the latter cases, our type system is expressive enough to represent pointer aliasing and yet safely permit destructive operations such as object deallocation. We demonstrate the flexibility of our type system by encoding two common space-conscious algorithms: destination-passing style and Deutsch-Schorr-Waite or "link-reversal" traversal algoithms.