12116657
A Step Towards Automated Design of Side Actions in Injection Molding of Complex Parts
Side actions contribute to mold cost by resulting in an additional manufacturing and assembly cost as well as by increasing the molding cycle time. Therefore, generating shapes of side actions requires solving a complex geometric optimization problem. Different objective functions may be needed depending upon different molding scenarios (e.g., prototyping versus large production runs). Manually designing side actions is a challenging task and requires considerable expertise. Automated design of side actions will significantly reduce mold design lead times. This paper describes algorithms for generating shapes of side actions to minimize a customizable molding cost function.
7211906
Manufacturing feature instances: which ones to recognize?
Manufacturing features and feature-based representations have become an integral part of research on manufacturing systems, largely due to their ability to model correspondences between design information and manufacturing operations. However, several research challenges still must be addressed in order to place feature technologies into a solid scientific and mathematical framework. One challenge is the issue of alternatives in feature-based planning. Even after one has decided upon an abstract set of features to use for representing manufacturing operations, the set of feature instances used to represent a part is by no means unique. For a complex part, many (sometimes infinitely many) different manufacturing operations can potentially be used to manufacture various portions of the part. Some of these feature instances will appear in useful manufacturing plans, and others will not. In order to reduce the number of alternative manufacturing plans that must be examined, we require a systematic means of specifying which feature instances are of interest. This paper addresses the issue of alternatives by introducing the notion of primary feature instances, which we contend are sufficient to generate all manufacturing plans of interest. To substantiate our argument, we describe how various instances in the primary feature set can be used to produce the desired plans. Furthermore, we discuss how this formulation overcomes computational difficulties faced by previous work, and present some complexity results for this approach in the domain of machined parts. “Also with: Nationaf Institute of Standards and Technology, Manufacturing Systems Integration Division Building 220, Room A-127, Gaithersburg, MD 20899. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advanta$e, the ACM copyright notice and the title of the publication and Its date appear, and notice is given that copying is by permission of the Association of Computing Machinery.To copy otherwise, or to republish, requires a fee and/or specific permission. Solid Modeling ’95, Salt Lake City, Utah USA
6821018
Concurrent evaluation of machinability during product design
An approach to evaluating the machinability of a part during the design stage, which performs systematic generation and evaluation of machining alternatives, is discussed. The results of the analysis provide feedback to the designer about problems that might arise with the machining and information to the manufacturing engineer about which machining processes and process parameters are most desirable.<<ETX>>
12219775
Geometric algorithms for containment analysis of rotational parts
Abstract This paper describes a system and underlying algorithms to perform geometric containment analysis to determine if a newly designed rotational part can be manufactured from a part in an existing database of rotational parts. Only material removal of the database part is considered in order to obtain the newly designed part from the database part. The system uses a three-step algorithm to test for containment. The first step analyzes feasibility of containment using bounding cylinders. If the bounding cylinder of the query part is bigger than the part in the database, then the database part cannot contain the query part and it is eliminated from consideration. The second step analyzes feasibility of containment by ignoring off-axis features. Any part that fails to satisfy containment at this stage is eliminated from consideration. The third step analyzes the remaining parts from the database for feasibility of containment by including the off-axis features. Finally, the system rank-orders all the database parts that can contain the query part based on their volume differences with the query part. The system described in this paper can be used by designers and process planners to find an existing part that can be used as a stock to manufacture a newly designed part. This capability is expected to significantly reduce proliferation of parts, to improve manufacturing responsiveness, and to reduce the cost of new products.
13998462
Geometric algorithms for computing cutter engagement functions in 2.5D milling operations
Cutter engagement is a measure that describes what portion of the cutter is involved in machining at a given instant of time. During profile milling of complex geometries, cutter engagement varies significantly along the cutter path. Cutter engagement information helps in determining the efficiency of the cutter path and also helps in improving it by adjusting the feed rate. This paper describes geometric algorithms for computing piece-wise continuous closed-form cutter engagement functions for 2.5D milling operations. The results produced by our algorithm are compared with the results obtained by discrete simulations of the cutting process and appear to match very well.
532672
IMACS: A Case Study in Real-World Planning
This article discusses the complexities of real-world planning and how to create planning systems to address them. IMACS (Interactive Manufacturability Analysis and Critiquing System), an automated designer's aid, evaluates machined parts and suggests design modifications to improve their manufacturability, offering advantages over the planning techniques used in classical planning systems.
5347587
Process aggravated noise (PAN): new validation and test problems
How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.
45533435
BIST TPG for combinational cluster (glue logic) interconnect testing at board level
Due to the expense and complexity of boundary scan architecture (BSA) circuitry, non-boundary scan ICs (cluster ICs) are still used in modern circuit boards. A novel BIST architecture and a TPG design methodology to program this architecture are presented for testing inter-IC interconnects among combinational cluster ICs via IEEE 1149.1 BSA at board level. The two main issues that are tackled are: (1) safe testing, i.e., avoidance of conflicts at all multi-driver nets; and (2) obtaining complete coverage of all detectable faults in the interconnect. We have proposed a realistic model of interconnects that contain combinational cluster ICs, identified test requirements that must be satisfied by the TPG to achieve the above objectives, and developed a new TPG architecture that satisfies these test requirements. We have theoretically proven that the proposed technique guarantees safe and comprehensive testing of cluster interconnects and also demonstrated this fact via its applications to a few example circuits.
1656626
Coordinated parallelizing compiler optimizations and high-level synthesis
We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the <i>SPARK</i> framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.
2580676
Adaptive Distributed Dynamic Channel Allocation for Wireless Networks
Channel allocation schemes in a mobile computing (wireless) environment can be either static or dynamic. Static allocation offers negligible channel acquisition time and zero message complexity and works well at a low system load; the performance steadily decreases as system load increases since many calls are dropped. In the case of even temporary hot spots many calls may be dropped by a heavily loaded switching station even when there are enough idle channels in the interference region of that station. On the other hand, dynamic schemes provide better utilization of the channels at higher loads albeit at the cost of higher channel acquisition time and some additional control messages. Our purpose in the present paper is to propose a combined channel allocation scheme so that each switching station can tune to its own load independent of other stations in its interference region; the objective is to minimize the call drop rate and at the same time maintain a minimum average channel acquisition time and minimum control message complexity.
29303565
Delay Fault Testing: How Robust are Our Models?
This panel will debate fundamental concepts in delay fault testing. A basic assumption in delay fault testing is that for a given transition propagated along a path, the path delay does not depend on values and transitions at circuit nodes that do not belong to the path. Is this assumption justified? If not, as some panelists will argue, then our current test procedures may miss some of the faults they target, and a lot of the current work in robust delay fault testing and in the synthesis of robust-testable circuits may be unreliable. A related question to be debated by the panel is whether a circuit passing a complete set of robust path delay tests at clock period T is guaranteed to perform its intended function at any clock period >= T. What are the delay models for which the answer is always true? What are the limitations of these models? Do we need to change the way we test circuits for delay faults? Other important questions deal with the hardware generating the tests: Can the response to the test be measured in a meaningful way (from a timing point of view)? Is the generating hardware capable of applying all two-pattern tests ? What delay model should be use to have a reasonable trade-off between accuracy and practicality? 502 O-8186-7304-4/96 $05.00