17171711
Characterization of errors in compositing panoramic images
In this paper we describe the effect of errors in the intrinsic camera parameters on reconstructed panoramic images. A panoramic image is created by first capturing a sequence of images while rotating the camera about a vertical axis a full 360/spl deg/. The subsequent steps are projecting the original rectilinear images onto cylindrical surfaces and compositing them to form the panoramic image. Our analysis has led to a technique that allows simultaneous recovery of the camera focal length and properly composited panoramic images. The correct focal length can be determined by iterating the processes of projecting the original rectilinear images onto cylindrical surfaces given an estimate of the focal length and compositing the resulting images to yield an increasingly better estimate of the focal length. This paper shows that the convergence towards the correct focal length is exponential.
2096181
Video editing using figure tracking and image-based rendering
We describe a new approach to video editing based on the semi-automatic segmentation of video into multiple layers and the composition of layers using image-based rendering. Using figure tracking and background motion estimation, we can segment a moving figure and reconstruct the background. Using geometrically-correct pixel reprojection, layers can be composited on the basis of the geometry of the underlying scene and the position of a virtual camera. We have implemented a prototype editing system called SpliceWorld.
40596005
Survey of image-based representations and compression techniques
We survey the techniques for image-based rendering (IBR) and for compressing image-based representations. Unlike traditional three-dimensional (3-D) computer graphics, in which 3-D geometry of the scene is known, IBR techniques render novel views directly from input images. IBR techniques can be classified into three categories according to how much geometric information is used: rendering without geometry, rendering with implicit geometry (i.e., correspondence), and rendering with explicit geometry (either with approximate or accurate geometry). We discuss the characteristics of these categories and their representative techniques. IBR techniques demonstrate a surprising diverse range in their extent of use of images and geometry in representing 3-D scenes. We explore the issues in trading off the use of images and geometry by revisiting plenoptic-sampling analysis and the notions of view dependency and geometric proxies. Finally, we highlight compression techniques specifically designed for image-based representations. Such compression techniques are important in making IBR techniques practical.
44673585
Characterization of Errors in Compositing Panoramic Images
A panoramic image has a 360° horizontal field of view, and it can provide the viewer the impression of being immersed in the scene. A panorama is created by first taking a sequence of images while rotating the camera about a vertical axis. These images are then projected onto a cylindrical surface before being seamlessly composited. The cross-sectional circumference of the cylindrical panorama is called thecompositing length. This work characterizes the error in compositing panoramic images due to errors in some of the intrinsic parameters. The intrinsic camera parameters that are considered are the camera focal length and the radial distortion coefficient. We show that the error in the compositing length is more sensitive to the error in the camera focal length. Especially important is the discovery that the relative error in compositing length is always smaller than the relative error in the focal length. This means that the error in focal length can be corrected by iteratively using the composited length to compute a new and more correct focal length. Thiscompositing approach to camera calibrationhas the advantages of not requiring both feature detection and separate prior calibration.
16190492
Noise Estimation from a Single Image
In order to work well, many computer vision algorithms require that their parameters be adjusted according to the image noise level, making it an important quantity to estimate. We show how to estimate an upper bound on the noise level from a single image based on a piecewise smooth image prior model and measured CCD camera response functions. We also learn the space of noise level functions how noise level changes with respect to brightness and use Bayesian MAP inference to infer the noise level function from a single image. We illustrate the utility of this noise estimation for two algorithms: edge detection and featurepreserving smoothing through bilateral filtering. For a variety of different noise levels, we obtain good results for both these algorithms with no user-specified inputs.
47117010
Stylizing 2.5-D video
In recent years considerable interest has been given to non-photorealistic rendering of photographs, video, and 3D models for illustrative or artistic purposes. Conventional 2D inputs such as photographs and video are easy to create and capture, while 3D models allow for a wider variety of stylization techniques, such as cross-hatching. In this paper, we propose using video with depth information (2.5-D video) to combine the advantages of 2D and 3D input. 2.5-D video is becoming increasingly easy to capture, and with the additional depth information, stylization techniques that require shape information can be applied. However, because 2.5-D video contains only limited shape information and 3D correspondence over time is unknown, it is difficult to create temporally coherent stylized animations directly from raw 2.5-D video. In this paper, we present techniques for processing 2.5-D video to overcome these drawbacks, and demonstrate several styles that can be created using these techniques.
45927986
Full chip ESD design rule checking
Electrostatic discharge (ESD) protection is essential for reliability and high yield. ESD design rule checking, however, is beyond the scope of commercial DRC tools. We have presented previously an ESD design rule checker for individual I/O cells. Full chip ESD design rules come in a myriad number of ways and are heavily process dependent. To check them one by one requires rewriting the design rule checker program for each process generation. This paper presents a framework for full chip ESD design rule checking adaptive to how full chip ESD design rules are derived.
9872720
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
High-speed domino logic is now prevailing in performance critical block of a chip. Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost up the transition speed in proposed circuitry, a well-established dual threshold voltage technique is exploited. Dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in clock tree and logic gates effectively. Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.
699756
An efficient calibration technique for systematic current-mismatch of D/A converters
This paper presents a current calibration technique for systematic mismatch in current-cell array. The proposed technique is suitable for GHz-range current-steering D/A converters because of an efficient and totally independent calibration operation. Behavioral simulation and measurement results show that static and yield performance of a D/A converter can be enhanced significantly by using the proposed technique. A measured reduction in INL and DNL errors before and after calibration is from +33.2/-60.1 LSB to +1.28/-1.28 LSB and from +10.2/-12.8 LSB to +2.56/-1.28 LSB in 12-bit resolution.
8573619
NMOS energy recovery logic
In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-clock. We have designed an 8-bit CLA and inverter chain using 0.6 /spl mu/m CMOS technology and verified that NERL saves energy over ECRL by 2 to 3 times.
9186181
New simulation methods for MOS VLSI timing and reliability
A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors. The simulator is able to simulate circuits as large as 235000 transistors in 10 min real time. Also presented is a novel approach to fast hot-carrier reliability simulation. These methods make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of MOS transistors in a workstation environment.<<ETX>>