2976234
Spec-based repeater insertion and wire sizing for on-chip interconnect
Recently Lillis, et al. (see Proc. Custom Integrated Conf., p. 259-262, May 1995) presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q/sup 2/) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.
7360354
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-free problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.
61819982
Optimal non-uniform wire-sizing under the Elmore delay model
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: (1) total weighted sink-delays; (2) total area subject to sink-delay bounds; and (3) maximum sink delay. We first present an algorithm NWSA-wd for minimizing total weighted sink-delays based on iteratively applying the wire-sizing formula in [1]. We show that NWSA-wd always converges to an optimal wire-sizing solution. Based on NWSA-wd and the Lagrangian relaxation technique, we obtained two algorithms NWSA-db and NWSA-md which can optimally solve the other two minimization objectives. Experimental results show that our algorithms are efficient both in terms of runtime and storage. For example, NWSA-wd, with linear runtime and storage, can solve a 6201-wire segment routing-tree problem using about 1.5-second runtime and 1.3-MB memory on an IBM RS/6000 workstation.
12098402
Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric a noise-aware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results.
195862034
Error bounded Pade approximation via bilinear conformal transformation
Since asymptotic waveform evaluation (AWE) was introduced, many interconnect model order reduction methods via Pade approximation have been proposed. Although the stability and precision of model reduction methods have been greatly improved, the following important question has not been answered: "What is the error bound in the time domain?". This problem is mainly caused by the "gap" between the frequency domain and the time domain, i.e., a good approximated transfer function in the frequency domain may not be a good approximation in the time domain. All of the existing methods approximate the transfer function directly in the frequency domain and hence can not provide error bounds in the time domain. In this paper, we present new moment matching methods which can provide guaranteed error bounds in the time domain. Our methods are based on the classic work by Teasdale (1953) which performs Pade approximation in a transformed domain by the bilinear conformal transformation s=(1-z)/(1+z).
21349955
A unified optimization framework for microelectronics industry
In this paper, an object-oriented unified optimization framework (UOF) for general problem optimization is proposed. Based on evolutionary algorithms, numerical deterministic methods, and C++ objective design, the UOF possesses real-world applications for various optimization problems. The UOF is with interface between defining a general problem and generic solver; hence the two areas are bridged. The UOF's components are categorized into problem and solver parts, and they work independently. Therefore, the reusable high level code allows the adaptation to new problem and solver quickly. Practical applications in microelectronics industry confirm the functionality of the developed unified optimization framework.
16272778
The Maximum Partition Matching Problem with Applications
Let ${\cal S} = {C1, C2, . . . , Ck}$ be a collection of pairwise disjoint subsets of U = { 1, 2, . . . , n} such that $\bigcup_{i = 1}^k Ci = U. A partition matching of $\cal S$ consists of two subsets {a1, . . . , am} and {b1, . . ., bm} of U together with a sequence of distinct partitions of $\cal S$: $({\cal A}_1, {\cal B}_1), \ldots, ({\cal A}_m, {\cal B}_m)$ such that ai is contained in a subset in the collection ${\cal A}_i$ and bi is contained in a subset in the collection ${\cal B}_i$ for all i = 1, . . . , m. An efficient algorithm is developed that constructs a maximum partition matching for a given collection $\cal S$. The algorithm can be used to construct optimal parallel routing between two nodes in interconnection networks.
260704
An implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation
A new parallel semiconductor device simulation using the dynamic load balancing approach is presented. This semiconductor device simulation based on adaptive finite volume error estimation, and monotone iterative methods has been developed and implemented on a Linux-cluster with MPI library. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first one is a dynamic parallel domain decomposition approach. The second version is a parallel current-voltage characteristic points simulation. The implementation shows that a well-designed load balancing simulation can reduce the execution time up to an order of magnitude. Compared with the measured data, numerical simulations on P-N diode, N-MOSFET, and DTMOS devices are presented to show the accuracy and efficiency of the method.
20325790
Top 10 Unsolved Information Visualization Problems
The top 10 unsolved problems list described in this article is a revised and extended version of information visualization problems. These problems are not necessarily imposed by technical barriers, rather, they are problems that might hinder the growth of information visualization as a field. The first three problems highlight issues from a user-centered perspective. The fifth, sixth, and seventh problems are technical challenges in nature. The last three are the ones that need tackling at the disciplinary level. The author broadly defines information visualization as visual representations of the semantics, or meaning, of information. In contrast to scientific visualization, information visualization typically deals with nonnumeric, nonspatial, and high-dimensional data.
2154628
Distributed web-based simulation experiments for optimization
Abstract The web has grown tremendously over the past decade – with applications in education, marketing, financial services, and supply chain management. Web technology also has a significant impact on computer simulation. Most of the effort in web-based simulation is aimed at modeling, particularly at building simulation languages and at creating model libraries that can be assembled and executed over the web. This paper focuses on efficiency of simulation experimentation for optimization. We introduce a framework for combining the statistical efficiency of simulation optimization techniques with the effectiveness of parallel execution algorithms. In particular, a novel simulation sampling procedure, the Optimal Computing Budget Allocation (OCBA) algorithm, is implemented in a web-based environment for low-cost parallel and distributed simulation experimentation. A prototype implementation with some experimental results is presented to show the viability of web-enabled simulation environments.