6968436
Optimal memory management for time warp parallel simulation
Recently there has been a great deal of interest in performance evalution of parallel simulation. Most work is devoted to the time complexity and assumes that the amount of memory available for parallel simulation is unlimited. This paper studies the space complexity of parallel simulation. Our goal is to design an efficient memory management protocol which guarantees that the memory consumption of parallel simulation is of the same order as sequential simulation. (Such an algorithm is referred to as a optimal.) First, we derive the relationships among the space complexities of sequential simulation, Chandy-Misra simulation [2], and Time Warp simulation [7]. We show that Chandy-Misra may consume more storage than sequential simulation, or vice versa. Then we show that Time Warp never consumes less memory than sequential simulation. Then we describe cancelback, an optimal Time Warp memory management protocol proposed by Jefferson. Although cancelback is considered to be complete solution for the storage management problem in Time Warp, some efficiency issues in implementing this algorithm must be considered. We propose an optimal algorithm called artifical rollback. We show that this algorithm is easy to implement and analyze. An implementation of artificial rollback is given, which is integrated with processor scheduling to adjust the memory consumption rate based on the amount of free storage available in the system.
16848330
A flexible graphical user interface for performance modeling
We identify three goals for the graphical user interface (GUI) of a network simulation environment: user friendliness, model re-usability, and application extensibility. We address the user friendliness issue by proposing a simple yet efficient approach to setup parameters for the simulation models. We address the application extensibility issue by a two-layer GUI architecture. The two layers are loosely-coupled, and the first layer can be easily replaced (without affecting the other components of the simulation environment). We address the model re-usability issue by subnetworks. Unlike most existing simulation packages where subnetwork is simply a method to group the nodes, the subnetwork construct in our approach is an integral part of the simulation environment (i.e., all operations for a basic node also apply to a subnetwork). The port concept is used to explicitly define the I/O relationship between a subnetwork and the outside world. Parameter dialog boxes are used to set up the parameters for a subnetwork conveniently. Finally, a simple stack mechanism is proposed to measure subnetwork-wide output statistics.<<ETX>>
2805042
A new random walk model for PCS networks
This paper proposes a new approach to simplify the two-dimensional random walk models capturing the movement of mobile users in personal communications services (PCS) networks. Analytical models are proposed for the new random walks. For a PCS network with hexagonal configuration, our approach reduces the states of the two-dimensional random walk from (3n/sup 2/+3n-5) to n(n+1)/2, where n is the layers of a cluster. For a mesh configuration, our approach reduces the states from (2n2-2n+1) to (n/sup 2/+2n+4)/4 if n is even and to (n/sup 2/+2n+5)/4 if n is odd. Simulation experiments are conducted to validate the analytical models. The results indicate that the errors between the analytical and simulation models are within 1%. Three applications (i.e., microcell/macrocell configuration, distance-based location update, and GPRS mobility management for data routing) are used to show how our new model can be used to investigate the performance of PCS networks.
5110930
A comparison study of the two-tier and the single-tier personal communications services systems
A two-tier PCS system integrates the high tier PCS system and the low tier PCS systems into a single system to provide the advantages of both tiers. Such a system is expected to provide better service (more available and more cost effective to the users) at the expense of the extra tier switching management. We compare the performance of the two-tier PCS system and the single low tier system in two aspects: the registration traffic and the service availability. Because of the tier management, the two-tier system generates more registration traffic than the single low tier system. Under the range of the input parameters in our study, we show that the two-tier system generates less than 10% extra registration traffic than the single low tier system in most cases and generates less than 20% registration traffic in the worst cases. It is clear that for the service availability, the two-tier system is better than the single one tier system. We also study the probability that a call is forced terminated in the single low tier system because the low tier becomes unavailable during the call (such a call can be continued in the two-tier system).
16744149
Performance Analysis for Dual Band PCS Networks
In a dual band personal communications services (PCS) network, heavy traffic areas are covered by microcells which overlay macrocells. In such a network, microcells and macrocells utilize different frequency bands. We propose an analytic model to study the performance of a dual band PCS architecture. Our model assumes that a PCS subscriber has a general residence time distribution in a microcell and the macrocell residence time distribution is derived from the microcell residence time distribution. An iterative algorithm is used to compute the overflow traffic from a microcell to its overlaid macrocell. Then, the call incompletion probability is computed by a macrocell model based on the overflow traffic. Our study indicates that the variance of the microcell residence time distribution and the number of microcells covered by a macrocell have significant effects on the call incompletion probability.
22500122
Performance of hot billing mobile prepaid service
Abstract Prepaid service has become an important mobile application with rapid growth for subscription rate in the recent years. Implementation of prepaid service may generate large network traffic that significantly affects the performance of a mobile network. This paper studies the hot billing solution for prepaid service. We investigate how the amount of prepaid credit and the frequency of call detail record (CDR) transmissions affect network signaling and potential bad debt that a service provider may bear. Our study suggests that a prepaid service provider should encourage customers to buy large prepaid credits by giving them discounts. Furthermore, based on call traffic, an optimal CDR transmission frequency can be found by using our modeling technique.
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
14489226
A performance-driven standard-cell placer based on a modified force-directed algorithm
We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming these two rows (top/bottom), all movable core cells force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained.
 We have integrated the proposed approach into an industrial APR flow. Experimental results on benchmark circuits up to 191K-cell (500K-gate) show that the critical path delay can be improved by as much as 11.5%. We also study the effect on both layout quality and CPU time consumption due to the amount of pseudo net added. We found that the introduction of pseudo net indeed significantly improves the layout quality.
10713306
Register Minimization beyond Sharing among Variables
Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated circuits, which usually have variables/signals of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, or some unclocked sequential networks. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that Vreg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register minimization also leads to both smaller area and faster designs.
27728163
Hybrid routing
A general-purpose routing algorithm for very-large-scale integrated (VLSI) circuits and printed circuit board (PCB) designs is proposed. Ideas behind the maze-running algorithm and the hierarchical routing algorithm are combined into a powerful algorithm called hybrid routing. The new algorithm demonstrates a speed compatible to a hierarchical router and produces routings with quality equivalent to that obtained by a maze router. Hybrid routing is based on the maze-running method with a third search dimension added. The extra search space is built by recursively constructing a hierarchy of coarser grid meshes. By means of a parameter-controlled expansion into the coarser meshes, the hybrid router is able to find the preferred search region very quickly and will not miss local information as a hierarchical router does. A user-given parameter can turn the algorithm into a pure maze router, a pure hierarchical router, or a wide spectrum of hybrid routers with different speed/quality characteristics between the extremes. The algorithm has been implemented and integrated into a global router that can handle large-scale routing, such as that encountered in the sea-of-gates layout. >
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.