28156768
A VLSI implementation of the blowfish encryption/decryption algorithm
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-rescheduling method, the critical path delay is improved by 21.7%. We have successfully implemented it using Compass cell library targeted at a 0.6 μm TSMC SPTM CMOS process. The die size is 5.7x6.1 mm and the maximum frequency is 50MHz.
53235373
Performance-optimal clustering with retiming for sequential circuits
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
16794704
A data request scheduling policy for PCS networks
This paper proposes a scheduling policy called latest preempted, earliest resumed (LPER) for personal communications services (PCS) systems that support voice services as well as the circuit mode data services. The policy gives priority to the voice services over the data services. The scheduling of voice requests is performed as if no data requests exist. Thus, if no idle channel is available when a voice request arrives, a data channel (if exists) is interrupted and the channel will be used for the voice request. The interrupted data request will be resumed when an idle channel is available. In LPER, the data channel selected for interruption is the one that serves the latest outstanding data request (i.e., other outstanding requests enter the system earlier than this request). When an occupied channel is released, LPER resumes the earliest request that entered the system. An analytic model is proposed to study the performance of LPER and provides guidelines to select the input parameters for the PCS systems.
34826185
Effects of Erlang call holding times on PCS call completion
Previous performance studies of PCS channel allocation assumed that call holding times have an exponential distribution. The exponential call holding time assumption is justified for existing cellular systems, where wireless calls are charged based on the length of the call holding time. Future PCS systems may exercise flat rate billing, and consequently a more general distribution is desirable to model the call holding times. This paper models the call holding times by the Erlang distribution (a generalization of the exponential distribution) to investigate the effect of the variance of the call holding times on the call completion probability. Our analysis indicates that the call completion probability decreases as the variance of the call holding times decreases. This effect becomes more pronounced as the variance of the cell residence times decreases.
26381792
Fault Tolerant Distributed Simulation
41129235
Determining the Global Progress of Parallel Simulation with FIFO Communication Property
Abstract In an optimistic parallel simulation, the global progress (i.e., the global virtual time or GVT) must be computed from time to time. We present a simple and efficient algorithm for computing the GVT in a distributed environment with FIFO communication delays. The accuracy and the complexity of the algorithm are discussed.
8520198
Performance of a weakly consistent wireless web access mechanism
In wireless web information access, long response may be experienced. To reduce the response times of wireless data access in a mobile network, caches are utilized in the wireless handheld devices or wireless proxy server. This paper proposes a wireless web data access algorithm for WAP (wireless application protocol) caching proxy to speed up data access. Our algorithm utilizes the access frequency to tune the data expiration time. The performance of the algorithm is investigated and is compared with existing TTL-based algorithms. Our study indicates that good performance is expected for the new algorithm.