13014348
QoS policies and architecture for cache/memory in CMP platforms
As we enter the era of CMP platforms with multiple threads/cores on the die, the diversity of the simultaneous workloads running on them is expected to increase. The rapid deployment of virtualization as a means to consolidate workloads on to a single platform is a prime example of this trend. In such scenarios, the quality of service (QoS) that each individual workload gets from the platform can widely vary depending on the behavior of the simultaneously running workloads. While the number of cores assigned to each workload can be controlled, there is no hardware or software support in today's platforms to control allocation of platform resources such as cache space and memory bandwidth to individual workloads. In this paper, we propose a QoS-enabled memory architecture for CMP platforms that addresses this problem. The QoS-enabled memory architecture enables more cache resources (i.e. space) and memory resources (i.e. bandwidth) for high priority applications based on guidance from the operating environment. The architecture also allows dynamic resource reassignment during run-time to further optimize the performance of the high priority application with minimal degradation to low priority. To achieve these goals, we will describe the hardware/software support required in the platform as well as the operating environment (O/S and virtual machine monitor). Our evaluation framework consists of detailed platform simulation models and a QoS-enabled version of Linux. Based on evaluation experiments, we show the effectiveness of a QoS-enabled architecture and summarize key findings/trade-offs.
15509008
Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers
As we enter the era of chip multiprocessor (CMP) architectures, it is important that we explore the scaling characteristics of mainstream server workloads on these platforms. In this paper, we analyze the performance of an Enterprise Java workload (SPECjbb2005) on two important classes of CMP architectures. One class of CMP platforms comprise of "small-scale" CMP (SCMP) processors with a few large out-of order cores on the die. Another class of CMP platforms comprise of "large-scale" CMP (LCMP) processors) with several small in-order cores on the die. For these classes of CMP architectures to succeed, it is important that there are sufficient resources (cache, memory and interconnect) to allow for a balanced scalable platform. In this paper, we focus on evaluating the resource scaling characteristics (cores, caches and memory) of SPECjbb2005 on these two architectures and understanding architectural trade-offs that may be required in future CMP offerings. The overall evaluation is uniquely conducted using four different methodologies (measurements on latest platforms, trace-based cache simulation, trace-based platform simulation and execution-driven emulation). Based on our findings, we summarize the architectural recommendations for future CMP server platforms (e.g. the need for large DRAM caches)
19000804
Receive Side Coalescing for Accelerating TCP/IP Processing
With rapid advancements in Ethernet technology, Ethernet speeds have increased by 10 fold, from 1 to 10Gbps, in a period of 2-3 years. This sudden increase in speeds has outpaced the rate at which processor and memory speeds have been increasing, raising concerns that TCP/IP processing will not scale to these levels. As a result, applications running on commercial servers will not be able to take advantage of the increased Ethernet bandwidth. This has led to a flurry of activity in the industry and academia focused on finding ways to scale up TCP/IP processing to 10Gbps and beyond. In this paper, we propose a novel technique called "Receive Side Coalescing" (RSC) that increases TCP/IP processing efficiencies significantly. RSC allows NICs to identify packets that belong to same TCP/IP flow and coalesce them into a single large packet. As a result, TCP/IP stack has to process fewer packets reducing per packet processing costs. NIC can do this coalescing of packets during interrupt moderation time hence packet latency is not affected. We have collected packet traces and analyzed those to find out how much coalescing is possible in different scenarios. Our analysis shows that about 50% reduction in number of packets is possible. We have prototyped RSC on Windows and Linux to understand the benefits, and the results show that 2-7% of savings in CPU utilization is possible at 1Gbps speeds. Projection models developed to estimate processing costs at 10Gbps show that RSC can save up to 20% of the CPU.
31753599
Adaptive Closed-Loop Power Control Using an MMSE Receiver in DS-CDMA Systems
A closed-loop power control algorithm, which includes both power control and power allocation functions for DS-CDMA systems, is proposed. The target power level is updated by an iterative algorithm for a minimum mean square error (MMSE) linear filter receiver. The received power is compared with the target to generate the current power control command (PCC). The transmitted power is adjusted by applying a variable stepsize generator that utilizes the PCC history and the estimated mobile speed. Simulation results are presented to show the improvement of the proposed adaptive power control over the conventional fixed stepsize power control.
3098509
The nature of novelty detection
Sentence level novelty detection aims at spotting sentences with novel information from an ordered sentence list. In the task, sentences appearing later in the list with no new meanings are eliminated. For the task of novelty detection, the contributions of this paper are three-fold. First, conceptually, this paper reveals the computational nature of the task currently overlooked by the Novelty community—Novelty as a combination of partial overlap (PO) and complete overlap (CO) relations between sentences. We define partial overlap between two sentences as a sharing of common facts, while complete overlap is when one sentence covers all of the meanings of the other sentence. Second, technically, a novel approach, the selected pool method is provided which follows naturally from the PO-CO computational structure. We provide formal error analysis for selected pool and methods based on this PO-CO framework. We address the question how accurate must the PO judgments be to outperform the baseline pool method. Third, experimentally, results were presented for all the three novelty datasets currently available. Results show that the selected pool is significantly better or no worse than the current methods, an indication that the term overlap criterion for the PO judgments could be adequately accurate.
5957902
Qualitative and quantitative car tracking from a range image sequence
In this paper, we present a car tracking system which provides quantitative and qualitative motion estimates of the tracked car simultaneously from a moving observer. First, we construct three motion models (constant velocity, constant acceleration, and turning) to describe the qualitative motion of a moving car. Then the models are incorporated into the Extended Kalman Filters to perform quantitative tracking. Finally, we develop, an Extended Interacting Multiple Model (EIMM) algorithm to manage the switching between models and to output both qualitative and quantitative motion estimates of the tracked car. Accurate motion modeling and efficient model management result in a high performance tracking system. The experimental results on simulated and real data demonstrate that our tracking system is reliable and robust, and runs in real-time. The multiple motion representations make the system useful in various autonomous driving tasks.
44859876
A primal-dual approximation algorithm for the survivable network design problem in hypergraphs
Given a hypergraph with nonnegative costs on hyperedges, and a weakly supermodular function r:2V → Z+, where V is the vertex set, we consider the problem of finding a minimum cost subset of hyperedges such that for every set S ⊆ V, there are at least r(S) hyperedges that have at least one but no all endpoints in S. This problem captures a hypergraph generalization of the survivable network design problem (SNDP), and also the element connectivity problem (ECP). We present a primal-dual algorithm with a performance guarantee of dmax+H (rmax), where dmax+ is the maximum degree of hyperedges of positive costs, rmax = maxs r(S), and H(k) = 1 + 1/2 +...+ 1/k. In particular, our result contains a 2H(rmax)-approximation algorithm for ECP, which gives an independent and complete proof for the result first obtained by Jain et al. (Proceedings of the SODA, 1999, p. 484-489).
32435431
Regularized Semi-supervised Classification on Manifold
Semi-supervised learning gets estimated marginal distribution PX with a large number of unlabeled examples and then constrains the conditional probability p(y | x) with a few labeled examples. In this paper, we focus on a regularization approach for semi-supervised classification. The label information graph is first defined to keep the pairwise label relationship and can be incorporated with neighborhood graph which reflects the intrinsic geometry structure of PX. Then we propose a novel regularized semi-supervised classification algorithm, in which the regularization term is based on the modified Graph Laplacian. By redefining the Graph Laplacian, we can adjust and optimize the decision boundary using the labeled examples. The new algorithm combines the benefits of both unsupervised and supervised learning and can use unlabeled and labeled examples effectively. Encouraging experimental results are presented on both synthetic and real world datasets.