206458818
Delay defect characteristics and testing strategies
Several factors influence production delay testing and corresponding DFT techniques: defect sources, design styles. ability to monitor process characteristics, test generation time. available test time, and tester memory. We present an overview of delay defect characteristics and the impact of delay defects on IC quality. We also discuss practical delay-testing strategy in terms of test pattern generation, test application speed, DFT, and test cost.
15807495
Application-independent testing of FPGA interconnects
We present a new automatic test-configuration-generation technique for application-independent manufacturing testing of the interconnection network of static-random-access-memory-based field programmable gate arrays (FPGAs). This technique targets detection of open and bridging faults in the wiring channels and programmable switches in the interconnects. Experimental results on Xilinx Virtex FPGAs show that very few test configurations are required to cover stuck-open, stuck-closed, open, and bridging faults in the interconnects.
42903241
Test vector compression using EDA-ATE synergies
This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.
900289
Techniques and algorithms for fault grading of FPGA interconnect test configurations
Conventional fault simulation techniques for field programmable gate arrays (FPGAs) are very complicated and time consuming. The alternative, FPGA fault emulation technique, is incomplete and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. The presented technique is able to report all detectable and undetectable faults and, compared with conventional methods, is orders of magnitude faster.
2397835
Speed clustering of integrated circuits
Experimental data on 0.18 /spl mu/ test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.
2705949
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
33350706
Evolutionary Modular MLP with Rough Sets and ID3 Algorithm for Staging of Cervical Cancer
This paper describes a way of designing a hybrid system for detecting the different stages of cervical cancer. Hybridisation includes the evolution of knowledge-based subnetwork modules with GAs using rough set theory and the ID3 algorithm. Crude subnetworks for each module are initially obtained via rough set theory and the ID3 algorithm. These subnetworks are then combined, and the final network is evolved using genetic algorithms. The evol-ution uses a restricted mutation operator which utilises the knowledge of the modular structure, already generated, for faster convergence. The GA tunes the network weights and structure simultaneously. The aforesaid integration enhances the performance in terms of classification score, network size and training time, as compared to the conven-tional MLP. This methodology also helps in imposing a structure on the weights, which results in a network more suitable for rule extraction.
1158736
Specifying and proving properties of timed I/O automata in the TIOA toolkit
Timed I/O Automata (TIOA) is a mathematical framework for modeling and verification of distributed systems that involve discrete and continuous dynamics. TIOA can be used for example, to model a real-time software component controlling a physical process. The TIOA model is sufficiently general to subsume other models in use for timed systems. The TIOA toolkit, currently under development, is aimed at supporting system development based on TIOA specifications. The TIOA toolkit is an extension of the IOA toolkit, which provides a specification simulator, a code generator, and both model checking and theorem proving support for analyzing specifications. This paper focuses on modeling of timed systems with TIOA and the TAME-based theorem proving support provided in the toolkit, for proving system properties, including timing properties. Several examples are provided by way of illustration
6745026
Translating Timed I/O Automata Specifications for Theorem Proving in PVS
Timed Input/Output Automaton (TIOA) is a mathematical framework for specification and analysis of systems that involve discrete and continuous evolution. In order to employ an interactive theorem prover in deducing properties of a TIOA, its state-transition based description has to be translated to the language of the theorem prover. In this paper, we describe a tool for translating TIOA to the language of the Prototype Verification System (PVS)—a specification system with an integrated interactive theorem prover. We describe the translation scheme, discuss the design decisions, and briefly present three case studies to illustrate the application of the translator in the verification process.
206590610
Modeling Phase Spectra Using Gaussian Mixture Models for Human Face Identification
It has been established that information distinguishing one human face from another is contained to a large extent in the Fourier domain phase component of the facial image. However, to date, formal statistical models for this component have not been deployed in face recognition tasks. In this paper we introduce a model-based approach using Gaussian mixture models (GMM) for the phase component for performing human identification. Classification and verification are performed using a MAP estimate and we show that we are able to achieve identification error rates as low as 2% and verification error rates as low as 0.3% on a database with 65 individuals with extreme illumination variations. The proposed method is easily able to deal with other distortions such as expressions and poses, and hence this establishes its robustness to intra-personal variations. A potential use of the method in illumination normalization is also discussed.
29308229
Safety Verification of Model Helicopter Controller Using Hybrid Input/Output Automata
This paper presents an application of the Hybrid I/O Automaton (HIOA) framework [12] in verifying a realistic hybrid system. A supervisory pitch controller for a model helicopter system is designed and then verified. The design of the supervisor is limited by the actuator bandwidth, the sensor inaccuracies, and the sampling rates. Verification is carried out by induction over the length of an execution of the composed system automaton. The HIOA model makes the inductive proofs tractable by decomposing them into independent discrete and continuous parts. The paper also presents a set of language constructs for specifying hybrid I/O automata.