30062933
LiB: a CMOS cell compiler
An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. The layout style is a modification of that proposed by T. Uehara, and W. M. van Cleemput (IEEE Trans. Comput., vol.C-30, no.5, p.305-12, 1981). An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two are on the diffusion island and the others are rectilinear-shaped routing channels. A graph-theoretic method for selecting nets (subnets) for routing on the diffusion island is proposed. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing SILK, a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiB's layout using a symbolic editor. >
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
5123114
Bayesian Regularization and Nonnegative Deconvolution for Time Delay Estimation
Bayesian Regularization and Nonnegative Deconvolution (BRAND) is proposed for estimating time delays of acoustic signals in reverberant environments. Sparsity of the nonnegative filter coefficients is enforced using an L1-norm regularization. A probabilistic generative model is used to simultaneously estimate the regularization parameters and filter coefficients from the signal data. Iterative update rules are derived under a Bayesian framework using the Expectation-Maximization procedure. The resulting time delay estimation algorithm is demonstrated on noisy acoustic data.
13768633
Software Defined Radio - A High Performance Embedded Challenge
Wireless communication is one of the most computationally demanding workloads. It is performed by mobile terminals (“cell phones”) and must be accomplished by a small battery powered system. An important goal of the wireless industry is to develop hardware platforms that can support multiple protocols implemented in software (software defined radio) to support seamless end-user service over a variety of wireless networks. An equally important goal is to provide higher and higher data rates. This paper focuses on a study of the wideband code division multiple access protocol, which is one of the dominant third generation wireless standards. We have chosen it as a representative protocol. We provide a detailed analysis of computation and processing requirements of the core algorithms along with the interactions between the components. The goal of this paper is to describe the computational characteristics of this protocol to the computer architecture community, and to provide a high-level analysis of the architectural implications to illustrate one of the protocols that would need to be accommodated in a programmable platform for software defined radio. The computation demands and power limitations of approximately 60 Gops and 100~300 mW, place extremely challenging goals on such a system. Several of the key features of wideband code division multiple access protocol that can be exploited in the architecture include high degrees of vector and task parallelism, small memory footprints for both data and instructions, limited need for complex arithmetic functions such as multiplication, and a highly variable processing load that provides the opportunity to dynamically scale voltage and frequency.
38988284
Perfectly Overlapped Generation of Long Runs for Sorting Large Files
A parallel algorithm is presented for quick generation of long sorted runs as the first phase of sorting a large file. It can generate runs of length about 2(m + 2)p on a linear array of p processors each with a heap of size m. Internal computations can be completely overlapped with I/O, and only n + (m + 2)p steps are required to generate the runs from a file of n items. Experiments with the algorithm show that it can give highly satisfactory results in a real environment. A variant of the algorithm is also presented. It is possible that no merge phase is required for sorting a file occupying a whole disk.
1571256
Parallelism analyzers for parallel discrete event simulation
Discrete event simulation is usually time consuming. Recently, there has been a great deal of interest in using parallel computers to speed up the simulation process. Before the parallel simulation approach is applied, it is important to understand the inherent parallelism of simulation applications. A simple technique called critical path analysis was proposed to study paralllelism of simulation applications. This paper describes three critical path analysis algorithms based on different event-scheduling (process scheduling) policies. These algorithms are much simpler than a previous approach, where the events must be recorded in a trace and an extra pass is required to process the event trace. In our approach, the critical path analysis algorithms are integrated with the sequential simulation. At the end of the sequential simulation, the optimal parallel execution time is also computed. Livny proposed an algorithm similar to our approach (His, however, was designed for a specific language). Our algorithms can be integrated with sequential simulation programs written by users or be integrated with simulation languages. Another advantage of our algorithms over previous approaches is that ours can be used to study load balancing under different event-scheduling policies. Since our algorithms can be easily inserted in sequential simulation programs, critical path analysis can be applied to existing sequential programs without difficulty. The results can then be used to predict the performance of parallel simulation on similar applications. An example is given to show how useful information can be obtained from our algorithms.
30064725
Potential Fraudulent Usage in Mobile Telecommunications Networks
This paper investigates the fraudulent usage of mobile telecommunications services due to cloned subscriber identity modules (SIMs). In GSM or the Universal Mobile Telecommunication System (UMTS), a mobile phone or mobile station uses its SIM to gain network access through authentication. If the SIM of a legal user is cloned, then the cloned SIM can be used for GSM/UMTS authentication and fraudulent usage may occur. Under the existing GSM/UMTS mobility management and call setup procedures, we show how quickly the fraudulent usage can be detected. We also propose a simple solution to speed up the detection of potential fraudulent usage.