6598356
Loop Transformations for Architectures with Partitioned Register Banks
Embedded systems require maximum performance from a processor within significant constraints in power consumption and chip cost. Using software pipelining, processors can often exploit considerable instruction-level parallelism (ILP), and thus significantly improve performance, at the cost of substantially increasing register requirements. These increasing register requirements, however, make it difficult to build a high-performance embedded processor with a single, multi-ported register file while maintaining clock speed and limiting power consumption.
Some digital signal processors, such as the TI C6x, reduce the number of ports required for a register bank by partitioning the register bank into multiple banks. Disjoint subsets of functional units are directly connected to one of the partitioned register banks. Each register bank and its associate functional units is called a cluster. Clustering reduces the number of ports needed on a per-bank basis, allowing an increased clock rate. However, execution speed can be hampered because of the potential need to copy “non-local” operands among register banks in order to make them available to the functional unit performing an operation. The task of the compiler is to both maximize parallelism and minimize the number of remote register accesses needed.
Previous work has concentrated on methods to partition virtual registers amongst the target architecture's clusters. In this paper, we show how high-level loop transformations can enhance the partitioning obtained by low-level schemes. In our experiments, loop transformations improved software pipelining by 27% on a machine with 2 clusters, each having 1 floating-point and 1 integer register bank and 4 functional units. We also observed a 20% improvement on a similar machine with 4 clusters of 2 functional units. In fact, by performing the described loop transformations we were able to show improvements of greater than 10% over schedules (for un-transformed loops) generated with the unrealistic assumption of a single multi-ported register bank.
1106182
A visualization system for multithreaded programming
Almost all modern operating systems, from Windows to Unix, support multithreaded programming. To make sure our students can lead the trend of computer science in the foreseeable future, we need to introduce them to this important technology. However, we have found through experience in teaching multithreaded programming that the paradigm shift from sequential to multithreaded causes students significant problems, such as (1) multithreaded program development requires a new mindset, (2) multithreaded program behavior is dynamic, making debugging very difficult, and (3) proper synchronization is more difficult than anticipated [10, 11]. Moreover, detecting race conditions and deadlocks is more easily said than done.
329318
The garbage collection advantage: improving program locality
As improvements in processor speed continue to outpace improvements in cache and memory speed, poor locality increasingly degrades performance. Because copying garbage collectors move objects, they have an opportunity to improve locality. However, no static copying order is guaranteed to match program traversal orders. This paper introduces <i>online object reordering</i> (OOR) which includes a new dynamic, online class analysis for Java that detects program traversal patterns and exploits them in a copying collector. OOR uses run-time method sampling that drives just-in-time (JIT) compilation. For each <i>hot</i> (frequently executed) method, OOR analysis identifies the hot field accesses. At garbage collection time, the OOR collector then copies referents of hot fields together with their parent. Enhancements include static analysis to exclude accesses in cold basic blocks, heuristics that decay heat to respond to phase changes, and a separate space for hot objects. The overhead of OOR is on average negligible and always less than 2% on Java benchmarks in Jikes RVM with MMTk. We compare program performance of OOR to static class-oblivious copying orders (e.g., breadth and depth first). Performance variation due to static orders is often low, but can be up to 25%. In contrast, OOR matches or improves upon the best static order since its history-based copying tunes memory layout to program traversal.
153966
Compiling for the Impulse memory controller
The Impulse memory controller provides an interface for remapping irregular or sparse memory accesses into dense accesses in the cache memory. This capability significantly increases processor cache and system bus utilization, and previous work shows performance improvements from a factor of 1.2 to 5 with current technology models for hand-coded kernels in a cycle-level simulator. To attain widespread use of any specialized hardware feature requires automating its use in a compiler. We present compiler cost models using dependence and locality analysis that determine when to use Impulse to improve performance based on the reduction in misses, the additional cost for misses in Impulse, and the fixed cost for setting up a remapping. We implement the cost models and generate the appropriate Impulse system calls in the Scale compiler framework. Our results demonstrate that our cost models correctly choose when and when not to use Impulse. We also combine and compare Impulse with our implementation of loop permutation for improving locality. If loop permutation can achieve the same dense access pattern as Impulse, we prefer it, since it has no overheads, but we show that the combination can yield better performance.
10668543
Parameterized Computation of LCS for Two Sequences
The problem of finding the longest common subsequence is a well-known optimization problem because of its applications, especially in bioinformatics. In this paper, by applying the techniques developed in parameterized computation, an efficient approach for the problem of finding the longest common subsequence of two sequences is presented. The parameterized approach is compared with the well-known dynamic programming approach for the problem. The parameterized approach is much more efficient, as is shown by the experimental results.
42418095
An Improved ALOHA Algorithm for RFID Tag Identification
One of problems that we faced for Radio frequency identification (RFID) systems is that the collision between tags which lowers the efficiency of the RFID systems. One of the popular anti-collision algorithms is ALOHA-type algorithms, which are simple and have good performance when the number of tags to be read is reasonable small. In this paper, an enhanced dynamic framed slotted ALOHA algorithm for RFID is extended to a more general close form, hence reference [9] becomes only one special case described in our paper. The improved ALOHA algorithm for RFID tag identifications has much larger capacity to handle the cases when the tag numbers increasing largely while every frame keeping the optimum system efficiency 35.5%. Simulation results show that the proposed algorithm improves the efficiency nicely in comparison with the conventional algorithms keeping >80% as the previous paper shown.
14449557
Evaluation and automatic selection of methods for handling missing data
Real-world data often contain missing values. In this paper, nine different methods for handling missing data are described and compared. Thirty real-world datasets are used as input data in our experiment. Nine different missing levels are implemented in each training data set to investigate the performance of the methods at different missing levels. For evaluation, two different classification techniques, C4.5 and ELEM2, are applied to obtain the classification error rates. The experimental results show that different methods can have different effects on a data set. Based on the experimental results, we also propose a meta-learning approach to selecting a method for handling missing data. The evaluation results show that the meta-learning approach is effective in selecting a suitable method for handling missing data.
26664144
A Novel Framework for Graph Visualization
17691685
WFMS-based Data Integration for e-Learning
As more and more organisations and institutions are moving towards the e-learning strategy, more and more disparate data are distributed by different e-learning systems. How to effectively use this vast amount of distributed data becomes a big challenge. This paper addresses this challenge and works out a new mechanism to implement data integration for e-learning. A workflow management system based (WFMS-based) data integration model is contributed to the e-learning