29576760
A configurable AES processor for enhanced security
14027625
On test and diagnostics of flash memories
Embedded flash memory has been widely used in applications that require non-volatile on-chip storage elements. However, test and diagnostics of flash memories needs further investigation so that the overall cost of the products can be reduced. This paper presents the challenges and issues for test and diagnostics of flash memories, based on our recent experiences. We also suggest improvement of the test and diagnosis flow, including design-for-testability (DFT) using built-in self-test (BIST), built-in self-repair (BISR), and failure analysis. In addition, we present a configurable flash memory tester using FPGA for low-cost testing and diagnostics. Experimental results on industrial flash chips justify the effectiveness of our test and diagnostics system.
6505998
Failure factor based yield enhancement for SRAM designs
With increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-for-yield (DFY) methodologies have an increasing impact on the yield learning of modem silicon chips. However, a major part of a system chip is typically occupied by memories, which dominate the yield of the chip. During chip integration, it is important that we pick the right design of memory cores that will maximize the yield under the specific process technology chosen. Traditionally, yield prediction is only based on layout and defect statistics. In this paper, we propose to estimate the yield with a failure factor. We thus develop a memory failure factor analyzer (FFA), based on that, we can select the memory design that is more suitable for the given process technology. Experimental results show that we can efficiently evaluate the yields of different memory designs for the same specification, so that the most robust one, that results in the highest yield, can be selected.
6577464
An HMAC processor with integrated SHA-1 and MD5 algorithms
Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the standard HMAC function that supports both. Our HMAC design automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost---12.5% by sharing of the SHA-1 and MD5 circuitry and a little performance penalty.
904578
Simulation-based test algorithm generation for random access memories
Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.
9639915
Support for adaptivity in ARMCI using migratable objects
Many new paradigms of parallel programming have emerged that compete with and complement the standard and well-established MPI model. Most notable, and successful, among these are models that support some form of global address space. At the same time, approaches based on migratable objects (also called virtualized processes) have shown that resource management concerns can be separated effectively from the overall parallel programming effort. For example, Charm++ supports dynamic load balancing via an intelligent adaptive run-time system. It is also becoming clear that a multi-paradigm approach that allows modules written in one or more paradigms to coexist and co-operate will be necessary to tame the parallel programming challenge. ARMCI is a remote memory copy library that serves as a foundation of many global address space languages and libraries. This paper presents our preliminary work on integrating and supporting ARMCI with the adaptive run-time system of Charm++ as a part of our overall effort in the multi-paradigm approach
6313307
On the Security and Vulnerability of PING
We present a formal specification of the PING protocol, and use three concepts of convergence theory, namely closure, convergence, and protection, to show that this protocol is secure against weak adversaries (and insecure against strong ones). We then argue that despite the security of PING against weak adversaries, the natural vulnerability of this protocol (or of any other protocol for that matter) can be exploited by a weak adversary to launch a denial of service attack against any computer that hosts the protocol. Finally, we discuss three mechanisms, namely ingress filtering, hop integrity, and soft firewalls that can be used to prevent denial of service attacks in the Internet.
8545280
EnviroStore: A Cooperative Storage System for Disconnected Operation in Sensor Networks
This paper presents a new cooperative storage system for sensor networks geared for disconnected operation (where sensor nodes do not have a connected path to a basestation). The goal of the system is to maximize its data storage capacity by appropriately distributing storage utilization and opportunistically offloading data to external devices when possible. The system is motivated by the observation that a large category of sensor network applications, such as environmental data logging, does not require real-time data access. Such networks generally operate in a disconnected mode. Rather than focusing on multihop routing to a basestation, an important concern becomes (i) to maximize the effective storage capacity of the disconnected sensor network such that it accommodates the most data, and (ii) to take the best advantage of data upload opportunities when they become available to relieve network storage. The storage system described in this paper achieves the above goals, leading to significant improvements in the amount of data collected compared to non-cooperative storage. It is implemented in nesC for TinyOS and evaluated in TOSSIM through various application scenarios.
3172548
Key trees and the security of interval multicast
A key tree is a distributed data structure of security keys that can be used by a group of users. In this paper we describe how any user in the group can use the different keys in the key tree to securely multicast data to different subgroups within the group. The cost of securely multicasting data to a subgroup whose users are "consecutive" is O(log n) encryptions, where n is the total number of users in the group. The cost of securely multicasting data to an arbitrary subgroup is O(n/2) encryptions. However this cost can be reduced to one encryption by introducing an additional key tree to the group.
14645139
Generation of distributed logic-memory architectures through high-level synthesis
With the increasing cost of on-chip global communication, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout the chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This paper provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the tradeoffs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps. We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (up to 5.3/spl times/, average of 3.5/spl times/) performance improvements over well-optimized conventional designs with small area overheads (up to 19.3%, 15.1% on average). At the same time, the reduction in the energy-delay product is by an average of 5.9/spl times/ (up to 11.0/spl times/).