7983927
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in performance optimization. This work proposes a new placement methodology that facilitates low cost and robust clock network. It is based on the observation that bringing tightly constrained flip-flops close to each other can reduce the non-common paths between them in clock network. Such a reduction in-turn improves the tolerance of the clock network towards variations in delay/skew. Monte Carlo experiments (based on spatial correlations) indicate that our methodology can reduce the maximum skew violation due to variations by up to 62% with less than 2.7% increase in total wire length
7189153
Antenna avoidance in layer assignment
The sustained progress of very-large-scale-integration (VLSI) technology has dramatically increased the likelihood of the antenna problem in the manufacturing process and calls for corresponding considerations in the routing stage. In this paper, the authors propose a technique that can handle the antenna problem during the layer-assignment (LA) stage, which is an important step between global routing and detailed routing. The antenna-avoidance problem is modeled as a tree-partitioning problem with a linear-time-optimal-algorithm solution. This algorithm is customized to guide antenna avoidance in the LA stage. A linear-time optimal jumper-insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 76% antenna-violation reduction and 99% via-violation reduction.
1271597
An improved AMG-based method for fast power grid analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve AMG-based power grid analysis: (1) dynamic reduction threshold; (2) weighted interpolation; and (3) a new error smoothing scheme. Experimental results on power grid with up to 1.6 million nodes show that these techniques can improve accuracy by over 10 times compared to a reported industrial method while retaining the same fast speed
11408697
Path-Based Buffer Insertion
Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.
28075982
Clock buffer polarity assignment for power noise reduction
10406726
Associative Skew Clock Routing for Difficult Instances
In clock network synthesis, sometimes skew constraints are required only within certain groups of clock sinks and do not exist between different groups. This is the so-called associative skew clock routing problem. Although the number of constraints is reduced, the problem becomes more difficult to solve due to the enlarged solution space. The perhaps only previous work used a very primitive delay model and cannot handle difficult instances in which sink groups are intermingled. We reuse existing techniques to solve this problem, including the difficult instances, based on a more accurate and popular delay model. Experimental results show that our algorithm can reduce the total clock routing wirelength by 12% on average compared to greedy-DME which is one of the best zero skew routing algorithms
41764873
Supporting provision and access of educational visual resources on the web
15903312
Using dynamic branch behavior for power-efficient instruction fetch
Power consumption has become an increasing concern in high performance microprocessor design in terms of packaging and cooling cost. The fetch unit including instruction cache contributes a large portion of the total power consumption in the microprocessor The instruction cache itself suffers some hidden power consumption due to dynamic control flows. Although capturing the dynamic control flows to boost performance, conventional trace caches (CTC) may increase power consumption in the fetch unit due to its simultaneous access to both the trace cache and the instruction cache. By avoiding this simultaneous accesses, sequential trace caches (STC) achieve lower power consumption, but suffer a significant performance loss at the meantime. In this paper we propose dynamic direction prediction based trace cache (DPTC) which avoids simultaneous accesses to the trace cache and the instruction cache with the guide of fetch direction prediction. Experimental results show that dynamic prediction based trace cache can achieve 38.5% power reduction over conventional trace caches and an additional 7.2% reduction over STC, on average, while only trading a 1.8% performance loss compared to CTC.
52807519
An Adaptive Architecture for Presenting Interactive Media Onto Distributed Interfaces
This paper introduces an adaptive architecture for presenting interactive timed media onto distributed networked devices. The architecture is put into the test in a storytelling application for children. The interactive story is documented in StoryML, an XML-based language, and presented to multiple interface devices organized in an agent-based architecture. This allows the separation of the content from concrete physical devices, the definition of abstract media objects and the automatic adaptation of the same content to different environments of physical devices. Since both the content and the interaction are timed, issues of streaming and synchronization in this architecture are also addressed.
8993397
A Novel Hybrid Crypto-Biometric Authentication Scheme for ATM Based Banking Applications
This paper studies the smartcard based fingerprint encrytion/auth-entication scheme for ATM banking systems. In this scheme, the system authenticates each user by both his/her possession (smartcard) and biometrics (fingerprint). A smartcard is used for the first layer of authentication. Based on the successful pass of the first layer authentication, a subsequent process of the biometric fingerprint authentication proceeds. The proposed scheme is fast and secure. Computer simulations and statistical analyze are presented.
14468769
Exploring Wakeup-Free Instruction Scheduling
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free issue queue designs is critically based on their success in predicting the issue latency of an instruction accurately. Consequently, the goal of this paper is to explore the predictability of instruction issue latency under different design constraints and to identify the impediments to performance in such wakeup-free architectures. Our results indicate that structural problems in promoting instructions to the head of the instruction queue from where they are issued in wakeup-free architectures, the limited number of candidate instructions that can be considered for instruction issue, and the resource conflicts due to non-availability of issue ports all have a significant impact in degrading the performance of broadcast free architectures. Based on these observation, we explore an architecture that attempts to overcome the structural limitations by employing traditional selection logic and by using pre-check logic to reduce the impact of resource conflicts while still employing a wakeup-free strategy based on predicted instruction issue latencies. Finally, we improve this technique by limiting the selection logic to a small segment of the issue queue.