15628775
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
─ MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO systems increases. This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate at 20dB SNR respectively on XUP Virtex-II pro developing board with an xc2vp30 FPGA, which are 19 and 16 times faster than their respective implementations on a DSP. The performance in terms of resource utilization and bit error rate are also compared between these two algorithms.
16276152
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms
This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms in MIMO system. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate respectively on XUP Virtex-II pro developing board, which are 19 and 16 times faster than their respective implementations on a DSP
12254782
A system-on-programmable chip approach for MIMO sphere decoder
This paper presents a system-on-programmable chip approach for a Schnorr-Euchner strategy based sphere decoder. The decoding algorithm is partitioned with the division intensive matrix computation part on embedded microprocessor and the iterative lattice decoding function on programmable logics. Efficient hardware architectures are developed with three levels of parallelism. The system prototype of the decoder shows that it supports 35.75 Mbit/s data rate on an Altera Stratix EP1S10 FPGA located on Nios development board for a four antenna system with 16-QAM signal constellation, and is about 20 times faster than its implementation on a DSP.
7583168
Incremental Design Methodology for Multimillion-gate Fpgas
This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multimillions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. When combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An integrated FPGA design environment is then developed based on the incremental placer and its background refiner. The results show that the incremental design methodology is in orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.
37047287
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications
14449557
Evaluation and automatic selection of methods for handling missing data
Real-world data often contain missing values. In this paper, nine different methods for handling missing data are described and compared. Thirty real-world datasets are used as input data in our experiment. Nine different missing levels are implemented in each training data set to investigate the performance of the methods at different missing levels. For evaluation, two different classification techniques, C4.5 and ELEM2, are applied to obtain the classification error rates. The experimental results show that different methods can have different effects on a data set. Based on the experimental results, we also propose a meta-learning approach to selecting a method for handling missing data. The evaluation results show that the meta-learning approach is effective in selecting a suitable method for handling missing data.
17691685
WFMS-based Data Integration for e-Learning
As more and more organisations and institutions are moving towards the e-learning strategy, more and more disparate data are distributed by different e-learning systems. How to effectively use this vast amount of distributed data becomes a big challenge. This paper addresses this challenge and works out a new mechanism to implement data integration for e-learning. A workflow management system based (WFMS-based) data integration model is contributed to the e-learning
12321641
Locally Balanced Incremental Hierarchical Discriminant Regression
Incremental hierarchical discriminant regression faces several challenging issues: (a) a large input space with a small output space and (b) nonstationary statistics of data sequences. In the first case (a), there maybe few distinct labels in the output space while the input data distribute in a high dimensional space. In the second case (b), a tree has to be grown when only a limited data sequence has been observed. In this paper, we present the Locally Balanced Incremental Hierarchical Discriminant Regression (LBIHDR) algorithm. A novel node self-organization and spawning strategy is proposed to generate a more discriminant subspace by forming multiple clusters for one class. The algorithm was successfully applied to different kinds of data set.
43590220
Lower Bounds and Parameterized Approach for Longest Common Subsequence
In this paper, different parameterized versions of the longest common subsequence (LCS) problem are extensively investigated and computational lower bound results are derived based on current research progress in parameterized computation. For example, with the number of sequences as the parameter k, the problem is unlikely to be solvable in time f(k)no(k), where n is the length of each sequence and f is any recursive function. The lower bound result is asymptotically tight in consideration of the dynamic programming approach of time O(nk). Computational lower bounds for polynomial-time approximation schemes (PTAS) for the LCS problem are also derived. It is shown that the LCS problem has no PTAS of time f(1/ e)no(1/ e) for any recursive function f, unless all SNP problems are solvable in subexponential time. Compared with former results on this problem, this result has its significance. Finally a parameterized approach for the LCS problem is discussed, which is more efficient than the dynamic programming approach, especially when applied to large scale sequences.
27390518
Session Boundary Detection for Association Rule Learning Using n-Gram Language Models
We present a statistical method using n-gram language models to identify session boundaries in a large collection of Livelink log data. The identified sessions are then used for association rule learning. Unlike the traditional ad hoc timeout method, which uses fixed time thresholds for session identification, our method uses an information theoretic approach that provides a natural technique for performing dynamic session identification. The effectiveness of our approach is evaluated with respect to 4 different interestingness measures. We find that we obtain a significant improvement in each interestingness measure, ranging from a 26.6% to 39% improvement on average over the best results obtained with standard timeout methods.