29004467
Coherent Network Interfaces for Fine-Grain Communication
12937575
Application-specific protocols for user-level shared memory
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented some or all of their cache coherence protocols in software. One way to exploit the flexibility of this software is to tailor a coherence protocol to match an application's communication patterns and memory semantics. This paper presents evidence that this approach can lead to large performance improvements. It shows that application-specific protocols substantially improved the performance of three application programs-appbt, em3d, and barnes-over carefully tuned transparent shared memory implementations. The speed-ups were obtained on Blizzard, a fine-grained DSM system running on a 32-node Thinking Machines CM-5.<<ETX>>
7972983
Using speculation to simplify multiprocessor design
Summary form only given. Modern multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that rare corner-case events behave correctly. We propose using "speculation for simplicity " to enable designers to focus on common-case scenarios. Our approach is to speculate that rare events will not occur and rely on an efficient recovery mechanism to undo the effects of misspeculations. We illustrate the potential of speculation to simplify multiprocessor design with three examples. First, we simplify the design of a directory cache coherence protocol by speculatively relying on point-to-point ordering of messages in an adoptively routed interconnection network. Second, we simplify a snooping cache coherence protocol by treating a rare coherence state transition as a misspeculation. Third, we simplify interconnection network design by removing the virtual channels and then recovering from deadlocks when they occur. Experiments with full-system simulation and commercial workloads show that speculation is a viable approach for simplifying system design. Systems can incur as many as ten recoveries per second due to misspeculations without significantly degrading performance, and our speculatively simplified designs incur far fewer recoveries.
3338486
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scalingof transistor and conventional on-chip interconnect performancepresents a major barrier to future high performancesystems. Previous research has focused on wire-centricdesigns that use parallelism, locality, and on-chipwiring bandwidth to compensate for long wire latency.An alternative approach to this problem is to exploitnewly-emerging on-chip transmission line technology toreduce communication latency. Compared to conventionalRC wires, transmission lines can reduce delay by up to afactor of 30 for global wires, while eliminating the needfor repeaters. However, this latency reduction comes at thecost of a comparable reduction in bandwidth.In this paper, we investigate using transmission linesto access large level-2 on-chip caches. We propose a familyof Transmission Line Cache (TLC) designs that representdifferent points in the latency/bandwidth spectrum.Compared to the recently-proposed Dynamic Non-UniformCache Architecture (DNUCA) design, the base TLCdesign reduces the required cache area by 18% andreduces the interconnection network's dynamic powerconsumption by an average of 61%. The optimized TLCdesigns attain similar performance using fewer transmis-sionlines but with some additional complexity. Simulationresults using full-system simulation show that TLC providesmore consistent performance than the DNUCAdesign across a wide variety of workloads. TLC caches arelogically simpler than DNUCA designs, but requiregreater circuit and manufacturing complexity.
970409
Fine-grain access control for distributed shared memory
This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing.
This paper categorizes techniques based on where access control is enforced and where access conflicts are handled. We incorporated three techniques that require no additional hardware into Blizzard, a system that supports distributed shared memory on the CM-5. The first adds a software lookup before each shared-memory reference by modifying the program's executable. The second uses the memory's error correcting code (ECC) as cache-block valid bits. The third is a hybrid. The software technique ranged from slightly faster to two times slower than the ECC approach. Blizzard's performance is roughly comparable to a hardware shared-memory machine. These results argue that clusters of workstations or personal computers with networks comparable to the CM-5's will be able to support the same shared-memory interfaces as supercomputers.
8147536
Active memory: a new abstraction for memory-system simulation
This paper describes the active memory abstraction for memory-system simulation. In this abstraction---designed specifically for on-the-fly simulation, memory references logically invoke a user-specified function depending upon the reference's type and accessed memory block state. Active memory allows simulator writers to specify the appropriate action on each reference, including "no action" for the common case of cache hits. Because the abstraction hides implementation details, implementations can be carefully tuned for particular platforms, permitting much more efficient on-the-fly simulation than the traditional trace-driven abstraction.Our SPARC implementation, Fast-Cache, executes simple data cache simulations two or three times faster than a highly-tuned trace-driven simulator and only 2 to 7 times slower than the original program. Fast-Cache implements active memory by performing a fast table look up of the memory block state, taking as few as 3 cycles on a SuperSPARC for the no-action case. Modeling the effects of Fast-Cache's additional lookup instructions qualitatively shows that Fast-Cache is likely to be the most efficient simulator for miss ratios between 3% and 40%.
52806192
Minimising the Number of Bends and Volume in 3-Dimensional
Orthogonal Graph Drawings with a Diagonal Vertex Layout
Abstract 
A 3-dimensional orthogonal drawing of a graph with maximum
degree at most 6, positions the vertices at grid-points in the 3-dimensional
orthogonal grid, and routes edges along grid-lines such that edge routes only
intersect at common end-vertices. Minimising the number of bends and the volume
of 3-dimensional orthogonal drawings are established criteria for measuring the
aesthetic quality of a given drawing. In this paper we present two algorithms
for producing 3-dimensional orthogonal graph drawings with the vertices
positioned along the main diagonal of a cube, so-called diagonal
drawings. This vertex-layout strategy was introduced in the 3-BENDS
algorithm of Eades et al. [Discrete Applied Math.
103:55–87, 2000]. We show that minimising the number of bends in a
diagonal drawing of a given graph is NP-hard. Our first algorithm minimises the
total number of bends for a fixed ordering of the vertices along the diagonal
in linear time. Using two heuristics for determining this vertex-ordering we
obtain upper bounds on the number of bends. Our second algorithm, which is a
variation of the above-mentioned 3-BENDS algorithm, produces 3-bend
drawings with n3+o(n3) volume, which is the best known upper bound for
the volume of 3-dimensional orthogonal graph drawings with at most three bends per
edge. 


6424947
Queue Layouts, Tree-Width, and Three-Dimensional Graph Drawing
A three-dimensional (straight-line grid) drawing of a graph represents the vertices by points in Z3 and the edges by noncrossing line segments. This research is motivated by the following open problem due to Felsner, Liotta, and Wismath [Graph Drawing '01, Lecture Notes in Comput. Sci., 2002]: does every n-vertex planar graph have a three-dimensional drawing with O(n) volume? We prove that this question is almost equivalent to an existing one-dimensional graph layout problem. A queue layout consists of a linear order ? of the vertices of a graph, and a partition of the edges into queues, such that no two edges in the same queue are nested with respect to ?. The minimum number of queues in a queue layout of a graph is its queue-number. Let G be an n-vertex member of a proper minor-closed family of graphs (such as a planar graph). We prove that G has a O(1) × O(1) × O(n) drawing if and only if G has O(1) queue-number. Thus the above question is almost equivalent to an open problem of Heath, Leighton, and Rosenberg [SIAM J. Discrete Math., 1992], who ask whether every planar graph has O(1) queue-number? We also present partial solutions to an open problem of Ganley and Heath [Discrete Appl. Math., 2001], who ask whether graphs of bounded tree-width have bounded queue-number? We prove that graphs with bounded path-width, or both bounded tree-width and bounded maximum degree, have bounded queue-number. As a corollary we obtain three-dimensional drawings with optimal O(n) volume, for series-parallel graphs, and graphs with both bounded tree-width and bounded maximum degree.
119496125
Vertex partitions of chordal graphs
A k-tree is a chordal graph with no (k + 2)-clique. An 𝓁-tree-partition of a graph G is a vertex partition of G into 'bags,' such that contracting each bag to a single vertex gives an 𝓁-tree (after deleting loops and replacing parallel edges by a single edge). We prove that for all k ≥ 𝓁 ≥0, every k-tree has an 𝓁-tree-partition in which each bag induces a connected ${\lfloor k} /(\ell+1) \rfloor$-tree. An analogous result is proved for oriented k-trees. © 2006 Wiley Periodicals, Inc. J Graph Theory 53: 167172, 2006 
 
Supported by Government of Spain grant MEC SB2003-0270, and by the projects MCYT-FEDER BFM2003-00368 and Gen. Cat 2001SGR00224. Research initiated at the Department of Applied Mathematics and the Institute for Theoretical Computer Science at Charles University, Prague, Czech Republic. Supported by project LN00A056 of the Ministry of Education of the Czech Republic, and by the European Union Research Training Network COMBSTRU (Combinatorial Structure of Intractable Problems).
1926264
L Codes and Number Systems
Abstract The notion of an L code is introduced as a generalization of the customary notion of a code. Attention is focused on unary L codes. where the target alphabet consists of one letter only. Unary L codes can be identified with such number systems where the representation is unique. Surprisingly many unary morphisms are L codes. Furthermore, even for non-L-codes there is only one ‘exceptional length’ We also give a complete classification for the binary case.
1804621
The Maximum Number of Edges in a Three-Dimensional Grid-Drawing
An exact formula is given for the maximum number of edges in a graph that admits a three-dimensional grid-drawing contained in a given bounding box. The first universal lower bound on the volume of threedimensional grid-drawings is obtained as a corollary. Our results generalise to the setting of multi-dimensional polyline grid-drawings.