214800963
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
Encrypting data in unprotected memory has gained much interest lately for digital rights protection and security reasons. Counter Mode is a well-known encryption scheme. It is a symmetric-key encryption scheme based on any block cipher, e.g. AES. The schemeýs encryption algorithm uses a block cipher, a secret key and a counter (or a sequence number) to generate an encryption pad which is XORed with the data stored in memory. Like other memory encryption schemes, this method suffers from the inherent latency of decrypting encrypted data when loading them into the on-chip cache. One solution that parallelizes data fetching and encryption pad generation requires the sequence numbers of evicted cache lines to be cached on-chip. On-chip sequence number caching can be successful in reducing the latency at the cost of a large area overhead. In this paper, we present a novel technique to hide the latency overhead of decrypting counter mode encrypted memory by predicting the sequence number and pre-computing the encryption pad that we call one-time-pad or OTP. In contrast to the prior techniques of sequence number caching, our mechanism solves the latency issue by using idle decryption engine cycles to speculatively predict and pre-compute OTPs before the corresponding sequence number is loaded. This technique incurs very little area overhead. In addition, a novel adaptive OTP prediction technique is also presented to further improve our regular OTP prediction and precomputation mechanism. This adaptive scheme is not only able to predict encryption pads associated with static and infrequently updated cache lines but also those frequently updated ones as well. Experimental results using SPEC2000 benchmark show an 82% prediction rate. Moreover, we also explore several optimization techniques for improving the prediction accuracy. Two specific techniques, Two-level prediction and Context-based prediction are presented and evaluated. For the two-level prediction, the prediction rate was improved from 82% to 96%. With the context-based prediction, the prediction rate approaches 99%. Context-based OTP prediction outperforms a very large 512KB sequence number cache for many memory-bound SPEC programs. IPC results show an overall 15% to 40% performance improvement using our prediction and precomputation, and another 7% improvement when context-based prediction techniques is used.
19026342
Eager writeback - a technique for improving bandwidth utilization
Modern high-performance processors utilize multi-level cache structures to help tolerate the increasing latency of main memory. Most of these caches employ either a writeback or a write-through strategy to deal with store operations. Write-through caches propagate data to more distant memory levels at the time each store occurs, which requires a very large bandwidth between the memory hierarchy levels. Writeback caches can significantly reduce the bandwidth requirements between caches and memory by marking cache lines as dirty when stores are processed and writing those lines to the memory system only when that dirty line is evicted. Unfortunately, for applications that experience significant numbers of cache misses due to streaming data, writeback cache designs can degrade overall system performance by clustering bus activity when dirty lines contend with data being fetched into the cache. In this paper we present a new technique called Eager Writeback, which re-distributes and balances memory traffic by writing and "cleaning" dirty cache lines prior to their eviction. Eager Writeback can be viewed as a compromise between write-through and writeback policies, in which dirty lines are written later than write-through, but prior to writeback. We will show that this approach can reduce the large number of writes seen in a write-through design, while avoiding the performance degradation caused by clustering bus traffic in a writeback approach.
467375
Profile-guided microarchitectural floor planning for deep submicron processor design
As very large scale integration (VLSI) process technology migrates to nanoscale with a feature size of less than 100 nm, global wire delay is becoming a major hindrance in keeping the latency of intrachip communication within a single cycle, thus substantially decaying performance scalability. In addition, an effective microarchitectural floor planning algorithm can no longer ignore the dynamic communication patterns of applications. This article, using the profile information acquired at the microarchitecture level, proposes a "profile-guided microarchitectural floor planner" that considers both the impact of wire delay and the architectural behavior, namely, the intermodule communication, to reduce the latency of frequent routes inside a processor and to maintain performance scalability. Based on the simulation results here, the proposed profile-guided method shows a 5%-40% average instructions per cycle (IPC) improvement when the clock frequency is fixed. From the perspective of instruction throughput in billion instructions per second (BIPS), the floor planner is much more scalable than the conventional wirelength-based floor planner
19776539
Stack value file: custom microarchitecture for the stack
As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack regions. Each of these designs can improve performance by constructing two separate structures which can be probed in parallel while reducing contention. In this paper, we propose a new memory organization that partitions data references into stack and nonstack regions. Non-stack references are routed to a conventional cache. Stack references, on the other hand, are shown to have several characteristics that can be leveraged to improve performance using a less conventional storage organization. This paper enumerates those characteristics and proposes a new microarchitectural feature, the stack value file (SVF), which exploits them to improve instruction-level parallelism, reduce stack access latencies, reduce demand on the first-level cache, and reduce data bus traffic. Our results show that the SVF can improve execution performance by 29 to 65% while reducing overhead traffic for the stack region by many orders of magnitude over cache structures of the same size.
42364168
An Algorithm for Incremental Nearest Neighbor Search in High-Dimensional Data Spaces
The SPY-TEC (Spherical Pyramid-Technique) [8] was proposed as a new indexing method for high-dimensional data spaces using a special partitioning strategy that divides a d-dimensional data space into 2d spherical pyramids. Although the authors of [8] proposed an efficient algorithm for processing hyperspherical range queries, they did not propose an algorithm for processing k-nearest neighbor queries that are frequently used in similarity search. In this paper, we propose an efficient algorithm for processing exact nearest neighbor queries on the SPY-TEC by extending the incremental nearest neighbor algorithm proposed in [10]. We also introduce a metric that can be used to guide an ordered best-first traversal when finding nearest neighbors on the SPYTEC. Finally, we show that our technique significantly outperforms the related techniques in processing k-nearest neighbor queries by comparing it to the R*-tree, the X-tree, and the sequential scan through extensive experiments.
7138459
Comparison of Feature Extraction Techniques for Watermark Synchronization
This paper evaluates feature extraction techniques in aspect of watermark synchronization. Most watermarking algorithms suffer from geometric distortion attacks that desynchronize the location of the inserted watermark. The process of synchronizing the location for watermark insertion and detection is crucial to design robust watermarking. One solution for watermark synchronization is to use features. This paper reviews feature extraction techniques in feature-based watermarking: the Harris corner detector and the Mexican Hat wavelet scale interaction method. We evaluate the scale-invariant keypoint extractor in comparison with others. After feature extraction, the set of triangles is generated by Delaunay tessellation. These triangles are the location for watermarking. Redetection ratio of triangles is measured against geometric distortion attacks and signal processing attacks. Experimental results show that the scale–invariant keypoint extractor is appropriate for robust watermarking.
15007668
Wakeup scheduling in wireless sensor networks
A large number of ractical sensing and actuating applications require immediate notification of rare but urgent events and also fast delivery of time sensitive actuation commands. In this a er,we consider the design of efficient wakeup scheduling schemes for energy constrained sensor nodes that adhere to the bidirectional end-to-end delay constraints posed by such applications. We evaluate several existing scheduling schemes and propose novel scheduling methods that outperform existing ones.We also resent a new family of wakeu methods,called multi-parent schemes, which take a cross-layer a roach where multiple routes for transfer of messages and wakeup schedules for various nodes are crafted in synergy to increase longevity while reducing message delivery latencies. We analyze the power-delay and lifetime-latency tradeoffs for several wakeup methods and show that our proposed techniques significantly improve the performance and allow for much longer network lifetime while satisfying the latency constraints.
36948650
Constructing SSML Documents with Automatically Generated Intonation Information in a Combinatory Categorial Grammar Framework
As of now, Text-to-Speech (TTS) systems are widely used throughout the full spectrum of our activities, and various natural language processing techniques have been utilized to enhance the performance of such TTS systems. As TTS systems begin to play an important role for communication between human and machine, naturalness is considered the most crucial measure of performance for TTS systems, in addition to correctness. General statistical approaches, though widely adopted, are not appropriate for the phenomena as they assign the same intonation to the same sentence. We analyze various kinds of corpus to extract informative features for intonation generation in a Combinatory Categorial Grammar framework, and express intonation-annotated document using Speech Synthesis Markup Language for target system neutral application.
5325970
Nearly Dynamic Task Model Scheduling with Aperiodic Tasks