31246040
Global Memory Management in Client-Server Database Architectures
Earlier performance studies of client-server database systems have investigated algorithms for caching locks and data at client worhxtations to reafuce latency and offload the server. These studies have been restricted to algorithms in which d&abase pages that were not in the local client buffer pool or the server buffer pool were read in from disk. In this paper we investigate a technique that allows client page requests to be serviced by other clients, thus treating the entire system as a single memory hierarchy. We also present techniques for efficiently exploiting this global memory hierarchy by reducing the replication of pages between client and server buffer pools. Global memory management algorithms that employ various combinalions of these techniques are then described, and the performance tradeoffs among the algorithms we investigated under a range of workloads and system conjiguratio~ using a simulation model.
2567437
Dynamic Query Operator Scheduling for Wide-Area Remote Access
Distributed databases operating over wide-area networks such as the Internet, must deal with the unpredictable nature of the performance of communication. The response times of accessing remote sources can vary widely due to network congestion, link failure, and other problems. In such an unpredictable environment, the traditional iterator-based query execution model performs poorly. We have developed a class of methods, called query scrambling, for dealing explicitly with the problem of unpredictable response times. Query scrambling dynamically modifies query execution plans on-the-fly in reaction to unexpected delays in data access. In this paper we focus on the dynamic scheduling of query operators in the context of query scrambling. We explore various choices for dynamic scheduling and examine, through a detailed simulation, the effects of these choices. Our experimental environment considers pipelined and non-pipelined join processing in a client with multiple remote data sources and delayed or possibly bursty arrivals of data. Our performance results show that scrambling rescheduling is effective in hiding the impact of delays on query response time for a number of different delay scenarios.
2815522
Efficient Filtering of XML Documents for Selective Dissemination of Information
Information Dissemination applications are gaining increasing popularity due to dramatic improvements in communications bandwidth and ubiquity. The sheer volume of data available necessitates the use of selective approaches to dissemination in order to avoid overwhelming users with unnecessaryinformation. Existing mechanisms for selective dissemination typically rely on simple keyword matching or “bag of words” information retrieval techniques. The advent of XML as a standard for information exchangeand the development of query languages for XML data enables the development of more sophisticated filtering mechanisms that take structure information into account. We have developed several index organizations and search algorithms for performing efficient filtering of XML documents for large-scale information dissemination systems. In this paper we describe these techniques and examine their performance across a range of document, workload, and scale scenarios.
1006062
The design of an acquisitional query processor for sensor networks
We discuss the design of an acquisitional query processor for data collection in sensor networks. Acquisitional issues are those that pertain to where, when, and how often data is physically acquired (sampled) and delivered to query processing operators. By focusing on the locations and costs of acquiring data, we are able to significantly reduce power consumption over traditional passive systems that assume the a priori existence of data. We discuss simple extensions to SQL for controlling data acquisition, and show how acquisitional issues influence query optimization, dissemination, and execution. We evaluate these issues in the context of TinyDB, a distributed query processor for smart sensor devices, and show how acquisitional techniques can provide significant reductions in power consumption on our sensor devices.
7889988
Crash recovery in client-server EXODUS
In this paper, we address the correctness and performance issues that arise when implementing logging and crash recovery in a page-server environment. The issues result from two characteristics of page-server systems: 1) the fact that data is modified and cached in client database buffers that are not accessible by the server, and 2) the performance and cost trade-offs that are inherent in a client-server environment. We describe a recovery system that we have implemented for the client-server version of the EXODUS storage manager. The implementation supports efficient buffer management policies, allows flexibility in the interaction between clients and the server, and reduces the server load by generating log records at clients. We also present a preliminary performance analysis of the implementation.
2033914
Data Staging for On-Demand Broadcast
:A>@<b_DCGAdPBEG>R<:c\A8:Q@L]J.A8<0H(L[MOz:CTL0PBc:zbP[<bc4EGADCG ? >@_DA8EHGbP[HP[CTA>@<::ADCTAD<.HTQRJz:CTL0PBcb_DPBEwHw_DPBbP[zbQRA bP0EqPBc\A>Uc\ADPBCGAdP$c:P]HFP z:CGL.PBc:_8PBEwHP[<P]HGHGCFPB_ HG>@?BA4c:P]HFP c\A8QR>@?BA8CGJ P[QRHGA8CG<kP]HG>@?BA2MSLBCQ@PBCG0A&_Q@>RA8<.H  LB:a:QUP]HT>RL0<bE8`v:ADCTAbP0Evz ADAD<Ew>@B<:>Rk_8P[<.HvyL0CGZ HGL]P[CFc:EOc\A8?BA8QRL0:>R<b$LB<\QR>@<:Az:CTL0P0c:_DP0EKHET_F:Adc\a:QR >@<:P[Q@BLBCT>RHG:E MSLBCEGJ\EKHTADE :ADCTA!P[Q@Q c:P]HFP >RHGADEOPBCGAyCGAdPBc\>@QRJPY?]PB>RQUP[z:Q@A>@<¡HG:AEGADCT?BADCd¢ E6P[>@< ADLBCTJB` :A8EGA£EwHGabc:>RAdE(>@B<bLBCTA HG:Ac:P]HFP2P[<: P[0ADAD<.H>UETEwa:AdEOHTbP]HP[CT>@EGA:A8<HG:A c:P[HTP HTL£z A z:CTL0P0c:_DP0EKH£akEKH&z A L0z\HTPB>R<bA8c MSCGL0¤EGA8_DLB<bcbP[CTJ EwHGLBCFP[0A LBC,CTADL[HTA Q@L\_DP]HT>RL0<bE8`¥<¦HT:>@E4bPBkA8C8V  A§:CTLB L0EGA HG:CTADA_LB:Q@ADA8<0HFP[CTJ ̈EGLBQ@a\HG>@LB<kE HGL EGab_F ̈©Ba[«a ¬­«aD®B ̄±°.®_L0<b_A8CG<kED2§L0: LBCGHGa:<:>UEw HG>U_ ET_F:A8c:a:QR>@<:kVEGADCT?BA8C2_DP0_F:>R<bbVP[<bc bCGADMSAHT_F: >@<:b`&bA8EGAHGA8_Fb<:>@3.a:AdE$A ́\:Q@LB>RH:>@<.HTE$:CTL]? >@c:A8c z J,HG:AET_F:A8c\abQR>@<:,P[Q@BLBCT>RHG:,`$μ¶c:AHTPB>RQ@A8c kA8Cw MSLBCTP[<b_DA AD?]P[Q@abP]HT>RL0< akEw>@<:P[<·¥K ̧o1 a:QRHG>U_DPBEwHw zbP0EwAdc HGAdEKHTzkAdc EG:L]vE$HTbP]HHG:AdEwA4c:P]HFP EwHTPBB>@<: HGAd_F:<:>U3.a:A8Ev_8P[< c\CFP[P]HT>@_8P[Q@QRJA8<:bPB<b_A HT:A$kA8Cw MSLBCTP[<b_DA L[M£P Q@PBCG0AEG_8P[Q@A,LB<\c\ADPB<bcz:CTL0P0c  _DP0EKHvEGJ\EKHTAD,`
14708115
Distributed computing systems and checkpointing
This paper examines the performance of synchronous checkpointing in a distributed computing environment with and without load redistribution. Performance models are developed, and optimum checkpoint intervals are determined. The analysis extends earlier work by allowing for multiple nodes, state dependent checkpoint intervals, and a performance metric which is coupled with failure-free performance and the speedup functions associated with implementation of parallel algorithms. Expressions for the optimum checkpoint intervals for synchronous checkpointing with and without load redistribution are derived and the results are then used to determine when load redistribution is advantageous.<<ETX>>
37466607
Analysis of parallel mixed-mode simulation algorithms
This paper presents a performance analysis of several parallel algorithms for the mixed-mode simulation of digital systems. The performance model is an architectural simulation of the parallel algorithms running on a hypercube multiprocessor. Workload data is collected from a uniprocessor-based mixed-mode simulator on several benchmark circuits, and two distinct circuit partitioning algorithms are considered. The results indicate that the performance of the parallel simulations is highly circuit dependent, in some cases performing worse than a uniprocessor and in others approaching optimal performance.<<ETX>>
18934348
Anomalies with variable partition paging algorithms
Five types of anomalous behaviour which may occur in paged virtual memory operating systems are defined. One type of anomaly, for example, concerns the fact that, with certain reference strings and paging algorithms, an increase in mean memory allocation may result in an increase in fault rate. Two paging algorithms, the page fault frequency and working set algorithms, are examined in terms of their anomaly potential, and reference string examples of various anomalies are presented. Two paging algorithm properties, the inclusion property and the generalized inclusion property, are discussed and the anomaly implications of these properties presented.
33759482
Working Set and Page Fault Frequency Paging Algorithms: A Performance Comparison
Performance of a paged virtual memory computer system operating under working set (WS) and page fault frequency (PFF) paging algorithms is analyzed analytically. Performance sensitivity to program reference behavior and paging algorithm parameter is studied for the two paging algorithms. The results indicate that when performance with the two algorithms is compared, the WS algorithm is generally less sensitive to changes in program behavior. Results are also provided relating to performance sensitivity to algorithm parameter selection.
583321
Performance models for network processor design
To provide a variety of new and advanced communications services, computer networks are required to perform increasingly complex packet processing. This processing typically takes place on network routers and their associated components. An increasingly central component in router design is a chip-multiprocessor (CMP) referred to as "network processor" or NP. In addition to multiple processors, NPs have multiple forms of on-chip memory, various network and off-chip memory interfaces, and other specialized logic components such as CAMs (content addressable memories). The design space for NPs (e.g., number of processors, caches, cache sizes, etc.) is large due to the diverse workload, application requirements, and system characteristics. System design constraints relate to the maximum chip area and the power consumption that are permissible while achieving defined line rates and executing required packet functions. In this paper, an analytic performance model that captures the processing performance, chip area, and power consumption for a prototypical NP is developed and used to provide quantitative insights into system design trade offs. The model, parameterized with a networking application benchmark, provides the basis for the design of a scalable, high-performance network processor and presents insights into how best to configure the numerous design elements associated with NPs