6565484
A timing-constrained simultaneous global routing algorithm
Proposed in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. The authors' approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities that can be exploited for congestion reduction under timing constraints. These flexibilities are expressed through the concepts of a soft edge and a slideable Steiner node. Starting with an initial solution where timing-driven routing is performed on each net without regard to congestion constraints, this algorithm hierarchically bisects a routing region and assigns soft edges to the cell boundaries along the bisector line. The assignment is achieved through a network flow formulation so that the amount of timing slack used to reduce congestions; is adaptive to the congestion distributions. Finally, a timing-constrained rip-up-and-reroute process is performed to alleviate the residual congestions. Experimental results on benchmark circuits are quite promising and the run time is between 0.02 s and 0.15 s per two-pin net.
14326045
A simple yet effective merging scheme for prescribed-skew clock routing
In order to achieve multi-GHz operation frequency for VLSI design, clock networks need to be designed in a very elaborated manner and be able to deliver prescribed useful skews rather than merely zero-skew. Although traditional zero-skew clock muting methods can be extended directly to prescribed skews, they tend to result in excessive wirelength as the differences among delay-targets for clock sinks are neglected. In this paper, we propose the maximum delay-target and minimum merging-cost merging scheme for prescribed-skew clock routing. This scheme is simple yet surprisingly effective on wirelength reduction. Experimental results on benchmark circuits show that our merging scheme yields 53%-61% wirelength reduction compared to traditional clock routing methods.
10406726
Associative Skew Clock Routing for Difficult Instances
In clock network synthesis, sometimes skew constraints are required only within certain groups of clock sinks and do not exist between different groups. This is the so-called associative skew clock routing problem. Although the number of constraints is reduced, the problem becomes more difficult to solve due to the enlarged solution space. The perhaps only previous work used a very primitive delay model and cannot handle difficult instances in which sink groups are intermingled. We reuse existing techniques to solve this problem, including the difficult instances, based on a more accurate and popular delay model. Experimental results show that our algorithm can reduce the total clock routing wirelength by 12% on average compared to greedy-DME which is one of the best zero skew routing algorithms
11408697
Path-Based Buffer Insertion
Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.
1271597
An improved AMG-based method for fast power grid analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve AMG-based power grid analysis: (1) dynamic reduction threshold; (2) weighted interpolation; and (3) a new error smoothing scheme. Experimental results on power grid with up to 1.6 million nodes show that these techniques can improve accuracy by over 10 times compared to a reported industrial method while retaining the same fast speed
28075982
Clock buffer polarity assignment for power noise reduction
13136257
An agent-based architecture for distributed interfaces and timed media in a storytelling application
This paper presents an agent-based architecture that enables the presentation of interactive timed media to distributed and networked devices. The architecture provides an automatic mapping of the same document to different environments. It uses a hierarchy of PAC (Presentation-Abstraction-Control) agents, which allows separating the presentation aspects from the control aspects and dynamically registering the new PAC agents to the system.
2207402
Bias properties of infinitesimal perturbation analysis for systems with parallel servers
Abstract Infinitesimal pertubation analysis (IPA) is a technique for estimating derivatives of performance measures from a single simulation of a stochastic discrete-event system, which might, for example, be modeling a computer/communication network or a manufacturing system. Such derivative estimates are useful in sensitivity analysis of the system and in optimizing—or at least improving—the performance of the system through gradient algorithms. However, it is well-known that IPA gives biased estimates for systems with multiple servers (channels or machines) in parallel when the server characteristics are not identical. In this paper, we investigate the seriousness of the bias both theoretically and experimentally. From our study, we believe the IPA estimator is relatively insensitive to small differences in the service time distributions of the servers. Specifially, we conjecture that for nearly-identical servers, the bias is proportional to the square of the difference between the means of the service time distributions. To support this conjecture, we present a tractable analytical example and investigate, via simulation experiments, more general systems.
15186294
The ARKdb: genome databases for farmed and other animals
The ARKdb genome databases provide comprehensive public repositories for genome mapping data from farmed species and other animals (http://www.thearkdb.org) providing a resource similar in function to that offered by GDB or MGD for human or mouse genome mapping data, respectively. Because we have attempted to build a generic mapping database, the system has wide utility, particularly for those species for which development of a specific resource would be prohibitive. The ARKdb genome database model has been implemented for 10 species to date. These are pig, chicken, sheep, cattle, horse, deer, tilapia, cat, turkey and salmon. Access to the ARKdb databases is effected via the World Wide Web using the ARKdb browser and Anubis map viewer. The information stored includes details of loci, maps, experimental methods and the source references. Links to other information sources such as PubMed and EMBL/GenBank are provided. Responsibility for data entry and curation is shared amongst scientists active in genome research in the species of interest. Mirror sites in the United States are maintained in addition to the central genome server at Roslin.
1128036
Conceptual framework and architecture for service mediating workflow management
This paper proposes a three-layer workflow concept framework to realize workflow enactment flexibility by dynamically binding activities to their implementations at run time. A service mediating layer is added to bridge business process definition and its implementation. Based on this framework, we propose an extended workflow management systems architecture, in which service contracting layer, service binding layer and service invocation layer are extensions to support the proposed service mediating concept. According to an enactment specification, different instances of the same activity can be bound to different services to achieve enactment flexibility. The conceptual framework and architecture together provide a comprehensive approach to flexible service enactment in B2B collaborative settings.
5276231
Open-ended robust design of analog filters using genetic programming
Most existing research on robust design using evolutionary algorithms (EA) follows the paradigm of traditional robust design, in which parameters of a design solution are tuned to improve the robustness of the system. However, the topological structure of a system may set a limit on the possible robustness achievable through parameter tuning. This paper proposes a new robust design paradigm that exploits the open-ended topological synthesis capability of genetic programming to evolve more robust systems. As a case study, a methodology for automated synthesis of dynamic systems, based on genetic programming and bond graph modeling (GPBG), is applied to evolve robust low-pass and high-pass analog filters. Compared with a traditional robust design approach based on a state-of-the-art real-parameter genetic algorithm (GA), it is shown that open-ended topology search by genetic programming with a fitness criterion rewarding robustness can evolve more robust systems with respect to parameter perturbations than what was achieved through parameter tuning alone, for our test problems.