33350706
Evolutionary Modular MLP with Rough Sets and ID3 Algorithm for Staging of Cervical Cancer
This paper describes a way of designing a hybrid system for detecting the different stages of cervical cancer. Hybridisation includes the evolution of knowledge-based subnetwork modules with GAs using rough set theory and the ID3 algorithm. Crude subnetworks for each module are initially obtained via rough set theory and the ID3 algorithm. These subnetworks are then combined, and the final network is evolved using genetic algorithms. The evol-ution uses a restricted mutation operator which utilises the knowledge of the modular structure, already generated, for faster convergence. The GA tunes the network weights and structure simultaneously. The aforesaid integration enhances the performance in terms of classification score, network size and training time, as compared to the conven-tional MLP. This methodology also helps in imposing a structure on the weights, which results in a network more suitable for rule extraction.
9622081
Modular Rough Fuzzy MLP: Evolutionary Design
The article describes a way of designing a hybrid system for classification and rule generation, integrating rough set theory with a fuzzy MLP using an evolutionary algorithm. An l-class classification problem is split into l two-class problems. Crude subnetworks are initially obtained for each of these two-class problems via rough set theory. These subnetworks are then combined and the final network is evolved using a GA with restricted mutation operator which utilizes the knowledge of the modular structure already generated, for faster convergence.
15125333
Evolutionary modular design of rough knowledge-based network using fuzzy attributes
This article describes a way of integrating rough set theory with a fuzzy MLP using a modular evolutionary algorithm, for classification and rule generation in soft computing paradigm. The novelty of the method lies in applying rough set theory for extracting dependency rules directly from a real-valued attribute table consisting of fuzzy membership values. This helps in preserving all the class representative points in the dependency rules by adaptively applying a threshold that automatically takes care of the shape of membership functions. An l-class classification problem is split into l two-class problems. Crude subnetwork modules are initially encoded from the dependency rules. These subnetworks are then combined and the final network is evolved using a GA with restricted mutation operator which utilizes the knowledge of the modular structure already generated, for faster convergence. The GA tunes the fuzzification parameters, and network weight and structure simultaneously, by optimising a single fitness function. This methodology helps in imposing a structure on the weights, which results in a network more suitable for rule generation. Performance of the algorithm is compared with related techniques.
1158736
Specifying and proving properties of timed I/O automata in the TIOA toolkit
Timed I/O Automata (TIOA) is a mathematical framework for modeling and verification of distributed systems that involve discrete and continuous dynamics. TIOA can be used for example, to model a real-time software component controlling a physical process. The TIOA model is sufficiently general to subsume other models in use for timed systems. The TIOA toolkit, currently under development, is aimed at supporting system development based on TIOA specifications. The TIOA toolkit is an extension of the IOA toolkit, which provides a specification simulator, a code generator, and both model checking and theorem proving support for analyzing specifications. This paper focuses on modeling of timed systems with TIOA and the TAME-based theorem proving support provided in the toolkit, for proving system properties, including timing properties. Several examples are provided by way of illustration
11095930
II-DFT: a hybrid dft architecture for low-cost high quality structural testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to industrial designs demonstrate significant savings in test cost in terms of test data volume and test application time without compromising test quality. Implementation of the HDFT architecture on Intel ASIC and microprocessor designs are described.
15363008
Word-voter: a new voter design for triple modular redundant systems
Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy (TMR) is a widely used redundancy technique that masks faults. In a TMR system, we have three implementations of the same logic function and their outputs are voted using a voter circuit. In this paper, we present a new voter design called the Word-Voter that has some distinct advantages over the bit-by-bit voting schemes used in conventional TMR systems. This paper demonstrates the usefulness of the word-voter design in increasing the data integrity (reducing the probability of corrupt outputs) of TMR systems. The area and delay overhead of the word-voter design is compared to that of the bit-by-bit voter. An efficient design of a TMR-Simplex system using the word-voter is also presented.
41028818
DFT assisted built-in soft error resilience
In this talk, we describe a new paradigm to design in soft error resilience by reusing already existent on-chip DFT resources. For example, scan systems that are required for manufacturing test and debug involve significant circuitry that are used only during post-silicon debug and production testing. These resources are then left unused throughout the entire lifetime of the product as they are not required for normal system operation. These structures continue to occupy additional silicon area and draw additional leakage power. We demonstrate how to reuse these scan resources to enable a built-in soft error resilience (BISER) design paradigm. These circuits result in more than 20 times reduction in soft error rate while incurring a system-level power overhead of 3-5%. Additional power-saving techniques are possible. The BISER techniques produce the best results in terms of power, performance and area overheads (when all 3 attributes are considered) compared to traditional major redundancy techniques. These techniques are also suitable for adaptive applications targeting a wide range of applications (e.g., networking ASICs, microprocessors) with various power, performance and soft error rate trade-offs.
28682159
Delay defect screening using process monitor structures
This paper presents delay test data collected from test chips fabricated in a 0.18 /spl mu/ technology. The experimental data shows that process monitor structures such as on-chip ring oscillators are effective in identifying slow parts while performing transition fault testing at frequencies slower than the rated frequency.