1811523
Route recovery mechanisms for ad hoc networks equipped with switched single beam antennas
In this paper we propose a novel three phase route recovery mechanism for routing over switched single beam directional antennas. We enhance the popular dynamic source routing (DSR) protocol to the underlying directional layer and include an improved broadcast mechanism to facilitate an efficient route discovery. In the event of a link failure, our optimized directional routing protocol (DRP) proceeds in three phases to recover the route to the destination: (i) antenna beam handoff (ii) local route recovery and (iii) zonal route recovery. We have compared the performance of DRP with the DSR protocol over both omnidirectional and directional antenna models in conditions of varying network mobility. Our results clearly indicate that DRP is robust to link failures even in highly mobile scenarios.
40094538
A Generic Design Methodology for Deadlock-Free Routing in Multicomputer Networks
This paper introduces a generic methodology for defining deadlock-free wormhole routing schemes in any arbitrary network. The basic strategy is to partition a graph into subdigraphs with no cyclic dependencies and selectively assign virtual channels. The usefulness of our scheme is shown for the n-dimensional hypercube, the n-dimensional mesh, and the k-ary n-cube torus by identifying subdigraph characteristics that ensure acyclic routing. Further generalization which allows partial cyclic dependencies without deadlock is achieved by our extended generic methodology. We also illustrate how to identify shortest fixed path and nonminimal adaptive routing schemes using minimum required channels.
22890668
Arithmetic Algorithms in a Negative Base
Algorithms are described for the basic arithmetic operations in a negative base. These algorithms are simpler, faster, and more general than those proposed by Sankar et al.
15237323
Testing and Fault Tolerance of Multistage Interconnection Networks
Test length is independent of network size in this simple, straightforward methodology for testing MINs (multistage interconnection networks). It requires only four test sequences for single-fault diagnosis. 26 references.
26743853
Design and Analysis of a Class of Highly Scalable Hierarchical Networks: PdBCube
Abstract A class of hierarchical networks called the dBCube, that provides cost-effective and high-performance communication in large multicomputer systems, has recently been introduced. Such a compound graph of a hypercube and a de Bruijn (dB) graph utilizes every node of the hypercube as a gateway for intercluster communication. This paper presents a partially connected dBCube subclass (PdBCube), wherein the use of fewer nodes as gateways makes the PdBCube highly scalable in terms of both the hypercube and the dB size. This enhancement in scalability can be achieved by two different approaches to assigning gateways. Performance degradation of the proposed PdBCube is illustrated in terms of diameter and average distance. Improvement in track efficiency and reduction in cost are observed to be directly related to a decrease in the number of remote links.
43408451
Network Intrusion Detection System Using Random Projection Technique
11368060
Packet classifiers in ternary CAMs can be smaller
Serving as the core component in many packet forwarding, differentiating and filtering schemes, packet classification continues to grow its importance in today's IP networks. Currently, most vendors use Ternary CAMs (TCAMs) for packet classification. TCAMs usually use brute-force parallel hardware to simultaneously check for all rules. One of the fundamental problems of TCAMs is that TCAMs suffer from range specifications because rules with range specifications need to be translated into multiple TCAM entries. Hence, the cost of packet classification will increase substantially as the number of TCAM entries grows. As a result, network operators hesitate to configure packet classifiers using range specifications. In this paper, we optimize packet classifier configurations by identifying semantically equivalent rule sets that lead to reduced number of TCAM entries when represented in hardware. In particular, we develop a number of effective techniques, which include: trimming rules, expanding rules, merging rules, and adding rules. Compared with previously proposed techniques which typically require modifications to the packet processor hardware, our scheme does not require any hardware modification, which is highly preferred by ISPs. Moreover, our scheme is complementary to previous techniques in that those techniques can be applied on the rule sets optimized by our scheme. We evaluate the effectiveness and potential of the proposed techniques using extensive experiments based on both real packet classifiers managed by a large tier-1 ISP and synthetic data generated randomly. We observe significant reduction on the number of TCAM entries that are needed to represent the optimized packet classifier configurations.
6124477
A counterexample to a Voronoi region conjecture
Given a 2D-symmetric lattice /spl Lambda/, it was conjectured by Forney (1989) that the projection of the Voronoi region R(/spl Lambda/) onto two coordinates equals the Voronoi region of the constituent 2D-sublattice /spl Lambda//spl nu//sub 2/. We present a three-dimensional counterexample. >
3172403
On overlay schemes to support point-in-range queries for scalable grid resource discovery
A resource directory is a critical component of a grid architecture. P2P computing paradigm could address some of the scalability issues that make distributed resource discovery services challenging. Unfortunately, most existing distributed hash table (DHT) based P2P overlays have difficulty in treating attribute range queries that are common in resource discovery lookups. This paper proposes a general framework for range-based resource discovery. In particular, the proposed framework maps tree-structured logical data (i.e., range indexing) onto a DHT-based physical node space (i.e., resource brokers). In this paper, we consider three mapping schemes from the logical space onto the physical space. Each mapping scheme uses a different replication mechanism to reduce range search time and to achieve load balance. We analytically and experimentally compare the performance characteristics (query/update costs and workload distributions) of these schemes and discuss their applicability under different resource discovery service scenarios.
1021221
Inferring client response time at the web server
As businesses continue to grow their World Wide Web presence, it is becoming increasingly vital for them to have quantitative measures of the client perceived response times of their web services. We present Certes (CliEnt Response Time Estimated by the Server), an online server-based mechanism for web servers to measure client perceived response time, as if measured at the client. Certes is based on a model of TCP that quantifies the effect that connection drops have on perceived client response time, by using three simple server-side measurements: connection drop rate, connection accept rate and connection completion rate. The mechanism does not require modifications to http servers or web pages, does not rely on probing or third party sampling, and does not require client-side modifications or scripting. Certes can be used to measure response times for any web content, not just HTML. We have implemented Certes and compared its response time measurements with those obtained with detailed client instrumentation. Our results demonstrate that Certes provides accurate server-based measurements of client response times in HTTP 1.0/1.1 [14] environments, even with rapidly changing workloads. Certes runs online in constant time with very low overhead. It can be used at web sites and server farms to verify compliance with service level objectives.
202287
Wire speed packet classification without tcams: a few more registers (and a bit of logic) are enough
Packet classification is the foundation of many Internet functions such as QoS and security. A long thread of research has proposed efficient software-based solutions to this problem. Such software solutions are attractive because they require cheap memory systems for implementation, thus bringing down the overall cost of the system. In contrast, hardware-based solutions use more expensive memory systems, e.g., TCAMs, but are often preferred by router vendors for their faster classification speeds. The goal of this paper is to find a "best-of-both-worlds" solution -- a solution that incurs the cost of a software-based system and has the speed of a hardware-based one. Our proposed solution, called smart rule cache achieves this goal by using minimal hardware -- a few additional registers -- to cache evolving rules which preserve classification semantics, and additional logic to match incoming packets to these rules. Using real traffic traces and real rule sets from a tier-1 ISP, we show such a setup is sufficient to achieve very high hit ratios for fast classification in hardware. Cache miss ratios are 2 ∼ 4 orders of magnitude lower than flow cache schemes. Given its low cost and good performance, we believe our solution may create significant impact on current industry practice.