1639783
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion
In this paper, we propose a high performance asynchronous on-chip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order/out-of-order completion increases by 31.3% / 34.3%, while power consumption overhead is only 6.76% / 3.98% respectively, compared to a simple asynchronous on-chip bus with only a single issue feature.
29667666
Building a distributed asynchronous control unit through automatic derivation of hierarchically decomposed AFSMs from a CDFG
Although there are several successful asynchronous logic synthesis tools, it is still unwieldy for designers to conceive and describe behaviors for a number of controllers constituting an asynchronous control unit of a target system manually. In this paper, building a distributed asynchronous control unit automatically through automatic derivation of hierarchically decomposed AFSMs from a CDFG is suggested. A resulting control unit consists of small asynchronous controllers and has complete separation of 'execution controllers' and 'execution order controllers'. This distributive feature leads to significant improvements in the aspects of area, performance and synthesis time of derived control circuits.
19612327
Instruction level redundant number computations for fast data intensive processing in asynchronous processors
Instruction level parallelism (ILP) is strictly limited by various dependencies. In particular, data dependency is a major performance bottleneck of data intensive applications. In this paper we address acceleration of the execution of instruction codes serialized by data dependencies. We propose a new computer architecture supporting a redundant number computation at the instruction level. To design and implement the scheme, an extended data-path and additional instructions are also proposed. The architectural exploitation of instruction level redundant number computations (IL-RNC) makes it possible to eliminate carry propagations. As a result execution of instructions which are serialized due to inherent data dependencies is accelerated. Simulations have been performed with data intensive processing benchmarks and the proposed architecture shows about a 1.2-1.35 fold speedup over a conventional counterpart. The proposed architecture model can be used effectively for data intensive processing in a microprocessor, a digital signal processor and a multimedia processor.
7800252
Imprecise data computation for high performance asynchronous processors
Instruction level parallelism(ILP) is strictly limited by various dependencies. In particular , data dependency is the major performance bottleneck of data intensive applications. To accelerate the execution of sequential code serialized due to data dependencies, this paper proposes an imprecise computation as a fast data computing technique for a high-performance asynchronous processor. To show the performance benefits of the suggested computing model, simulation results are presented. The imprecise computation can be used effectively in data intensive processing with a microprocessor, a Digital Signal Processor or a multimedia processor.
14687978
Procedural Constraints in the Extended RBAC and the Coloured Petri Net Modeling
This paper presents the Coloured Petri Net modeling for security analysis of the Extended Role Based Access Control systems.
12271296
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization
Asynchronous circuit design is very attractive as a high performance design method since it can achieve average-case delay. However, it is hard to make use of such an advantage in a pipelined architecture due to the blocking/starvation effects between stages. In most of current solutions, buffers are allocated to reduce the blocking/starvation effects but it is difficult to find a distribution of buffers over an asynchronous linear pipeline(ALP) that is optimal in terms of ‘time*area’ cost.
16719880
Jikzi - a new framework for security policy, trusted publishing and electronic commerce
In this paper, we will describe a thread of research, which we have followed off and on at Cambridge for about three years. Our topic is the security of electronic documents, in the broad sense: how can we be sure of the authenticity of things that are published electronically? This started off as a relatively small project, which we thought would take only a few weeks. The goal was to help our medical informatics department publish information such as drug formularies and treatment protocols on the hospital LAN or PC diskettes, in an appropriately dependable way. It rapidly became clear that the problem was much larger and more complex; a general solution would not only cope with 'content' - text, audio, video, software, whatever - but also with objects such as public key certificates. If done properly, it would give us a systematic way to deal with security policy on the web. Our goal now is to let people build integrated publishing and e-commerce services using simple, uniform and appropriate mechanisms. Our proposed solution is a single transparent markup language that allows us to support multiple security policies, plus supporting material ranging from a test implementation to an authentication logic.
41744891
Agent and e-business models
17626222
Controlling salinity in a potable water supply system using a constraint programming approach
Salinity is the relative concentration of salts in water. In a city of southern China, the local water supply company pumps water from a nearby river for potable use. During the winter dry season, the intrusion of sea water raises the salinity of the river to a high level and affects approximately the daily life of 450,000 residents of the city. In this paper, we report the application of constraint programming to optimize the logistical operations of the raw water system so as to satisfy the daily water consumption requirement of the city and to keep the potable salinity below a desirable level for as many days as possible. Our system has already been delivered to the water supply company for deployment
13264531
An efficient scattered data approximation using multilevel B-splines based on quasi-interpolants
In this paper, we propose an efficient approximation algorithm using multilevel B-splines based on quasi-interpolants. Multilevel technique uses a coarse to fine hierarchy to generate a sequence of bicubic B-spline functions whose sum approaches the desired interpolation function. To compute a set of control points, quasi-interpolants gives a procedure for deriving local spline approximation methods where a B-spline coefficient only depends on data points taken from the neighborhood of the support corresponding the B-spline. Experimental results show that the smooth surface reconstruction with high accuracy can be obtained from a selected set of scattered or dense irregular samples.
316350
Dynamic Repartitioning of Real-Time Schedule on a Multicore Processor for Energy Efficiency
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as the performance requirements are increasing. Though DVS may reduce power consumption for hard real time applications on single core processors, it introduces a new implication for multicore systems since all the cores in a chip should run at the same performance. Blind adoption of existing DVS algorithms may result in waste of energy since a core which requires low performance should run at the same high frequency with other cores. Based on the existing partitioning algorithms for the multiprocessor hard real-time scheduling, this article presents dynamic task repartitioning algorithm that balances task loads among cores to avoid the phenomena dynamically during execution. Simulation results show that in general cases our scheme makes additional energy saving more than 10% than that without our scheme even when the schedules are generated by WFD partitioning algorithm which is known as the best energy efficient partitioning algorithm.