7704531
A TCAM-based distributed parallel IP lookup scheme and performance analysis
Using ternary content addressable memory (TCAM) for high-speed IP address lookup has been gaining popularity due to its deterministic high performance. However, restricted by the slow improvement of memory accessing speed, the route lookup engines for next-generation terabit routers demand exploiting parallelism among multiple TCAM chips. Traditional parallel methods always incur excessive redundancy and high power consumption. We propose in this paper an original TCAM-based IP lookup scheme that achieves both ultra-high lookup throughput and optimal utilization of the memory while being power-efficient. In our multi-chip scheme, we devise a load-balanced TCAM table construction algorithm together with an adaptive load balancing mechanism. The power efficiency is well controlled by decreasing the number of TCAM entries triggered in each lookup operation. Using four 133 MHz TCAM chips and given 25% more TCAM entries than the original route table, the proposed scheme achieves a lookup throughput of up to 533 MPPS while remains simple for ASIC implementation
14245590
RED with optimized dynamic threshold deployment on shared buffer
Prior survey of RED algorithm deployment on multiqueue system with shared buffer was unfair and sensitive to congestion level by statically setting the parameters. In this paper, our goal is to deploy the Random Early Detection (RED) algorithm in routers on shared buffer and solve these problems. A novel buffer management scheme that dynamically adjusts the parameters of RED named RED-ODT is proposed. Simulations under uniform traffic load and nonuniform traffic load are given, the results of which ascertain and demonstrate the superiority of the proposed scheme in terms of low packet drop ratio, satisfying buffer utilization and fairness. Simulation also shows that RED-ODT is insensitive to congestion level.
15265299
An ultra high throughput and power efficient TCAM-based IP lookup engine
Ternary content-addressable memory (TCAM) is widely used in high-speed route lookup engines. However, restricted by the memory access speed, the route lookup engines for next-generation terabit routers demand exploiting parallelism among multiple TCAMs. Traditional parallel methods always incur excessive redundancy and high power consumption. We propose in this paper an original TCAM-based IP lookup scheme that achieves an ultra high lookup throughput and a high utilization of the memory while being power efficient. In our multichip scheme, we devise a load-balanced TCAM table construction algorithm together with an adaptive load balancing mechanism. The power efficiency is well controlled by decreasing the number of TCAM entries triggered in each lookup operation. Using 133 MHz TCAM chips and given 25% more TCAM entries than the original route table, the proposed scheme achieves a lookup throughput of up to 533 Mpps and is simple for ASIC implementation
863906
Per-Flow Queueing by Dynamic Queue Sharing
Per-flow queuing is believed to be able to guarantee advanced Quality of Service (QoS) for each flow. With the dramatic increase of link speed and number of traffic flows, per-flow queuing faces a great challenge since millions of queues need to be maintained for implementation in a traditional sense. In this paper, by setting only a small number of physical queues, we propose a Dynamic Queue Sharing (DQS) mechanism to achieve an equal performance to the pure per-flow queuing with a lower cost. The proposed mechanism is based on an interesting fact that the number of simultaneous active flows in the router buffer is far less than that of in-progress flows. In DQS, a physical queue is dynamically created on-demand when a new flow comes and then dynamically released when the flow temporarily pauses. Hashing and binary sorting tree (or linked list) are combined to manage the mapping between flows and queues, so as to isolate flows in different queues. Theoretical analysis and traces experiments are conducted to evaluate DQS. The results demonstrate that when the parameters are well set, the operation delay is less than two time cycles in average with an extra memory of 16k bits.
14850039
Provisioning Quality Controlled Medium Access in UltraWideBand-Operated WPANs
Quality of service (QoS) provisioning is one of the most important criteria in newly emerging UWB-operated WPANs, as they are expected to support a wide variety of applica- tions from time-constrained, multimedia streaming to throughput- hungry, content transfer applications. As such, the Enhanced Distributed Coordinated Access (EDCA) mechanism has been adopted by MultiBand OFDM Alliance in its UWB MAC proposal. In this paper, we conduct a rigorous, comprehensive, theoretical analysis and show that with the currently recommended parame- ter setting, EDCA cannot provide adequate QoS. In particular, without responding to the system dynamics (e.g., taking into account of the number of active class-i stations), EDCA cannot allocate bandwidth in a deterministic proportional manner and the system bandwidth is under-utilized. After identifying the deficiency of EDCA, we propose, in compliance with the EDCA-incorporated UWB MAC protocol proposed in (15) (20), a framework, along with a set of theoretically grounded methods for controlling medium access with determin- istic QoS for UWB networks. We show that in this framework, 1) real-time traffic is guaranteed of deterministic bandwidth via a contention-based reservation access method; 2) best-effort traffic is provided with deterministic proportional QoS; and moreover, 3) the bandwidth utilization is maximized. We have also validated and evaluated the QoS provisioning capability and practicality of the proposed MAC framework both via simulation and empirically by leveraging the MADWifi (Multiband Atheros Driver for WiFi) Linux driver for Wireless LAN devices with the Atheros chipset.
35202136
Supporting Problem Solving with Case-Stories Learning Scenario and Video-based Collaborative Learning Technology
In this paper, we suggest that case-based resources, which are used for assisting cognition during problem solving, can be structured around the work of narratives in social cultural psychology. Theories and other research methods have proposed structures within narratives and stories which may be useful to the design of case-based resources. Moreover, embedded within cases are stories which are contextually rich, supporting the epistemological groundings of situated cognition. Therefore the purposes of this paper are to discuss possible frameworks of case-stories; derive design principles as to “what” constitutes a good case story or narrative; and suggest how technology can support story-based learning. We adopt video-based Computer-Supported Collaborative Learning (CSCL) technology to support problem solving with casestories learning scenarios. Our hypothesis in this paper is that well-designed case-based resources are able to aid in the cognitive processes undergirding problem solving and meaning making. We also suggest the use of an emerging video-based collaborative learning technology to support such an instructional strategy.
206993144
Charge-based core and the model architecture of BSIM5
The paper outlines the charge-based core and the architecture of the BSIM5 MOSFET model for sub-100 nm CMOS circuit simulation. The BSIM5 model is a continuous, completely symmetric and accurate non charge-sheet based MOS transistor model derived from the basic device physics, including various physics effects. Comparison of the inversion charge between the BSIM5 prediction and self-consistent numerical solution shows good agreement. The demonstration of fully symmetric characteristics of BSIM5, such as channel current and its high-order derivative in the Gummel symmetry test, and charge and trans-capacitances in a SPICE simulation, also implies BSIM5 is the physically symmetric MOSFET model valid for RF-analog circuit simulations.
1743563
Toward an evaluation infrastructure for power and energy optimizations
Execution-driven simulators are often used for power/energy and performance evaluation. Simulators can provide semantic details but they provide insufficient speed and accuracy for compiler and OS research. Physical measurement is fast and objective but lacks a semantic connection between the measurement result and the evaluated program. The objective of our research is to bring together the advantages of simulation and physical measurement to build an infrastructure for power and energy optimization. Power and energy behavior is obtained through physical measurement. Simulation is used for observing the connection between power and energy behavior and the evaluated program. Our preliminary results demonstrate the ability of this infrastructure to capture detailed power behavior of any region of a program. To simplify the power/energy evaluation of programs with long execution times and overcome the limitation of physical devices, we propose using the SimPoints methodology developed by researchers at UC San Diego to find representative slices of a program. Through simulation, we validate the feasibility of the SimPoint idea in simplifying power/energy evaluation. We expect that this infrastructure will help researchers in OS/compiler power/energy optimization to evaluate their optimizations more efficiently and observe more optimization opportunities.
14957395
A statistical performance simulation methodology for VLSI circuits
A statistical performance simulation (SPS) methodology for VLSI circuits is presented. Traditional methods of worst-case corner analysis lack accuracy and Monte-Carlo simulations cannot be applied to VLSI circuits because of their complexity. SPS methodology is accurate because no statistical information about the device parameter variation is lost. It achieves efficiency by analyzing the smaller circuit blocks and generating the performance distribution for the entire circuit. Circuit evaluation at any specified performance level is possible.