6450321
A 32-bit carry lookahead adder using dual-path all-N logic
We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.
13548202
Noise constrained power optimization for dual V/sub T/ domino logic
In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
13489029
An integrated approach to realistic worst-case design optimization of MOS analog circuits
The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>
14376041
Feasible region approximation using convex polytopes
A new technique for polytope approximation of the feasible region for a design is presented. This method is computationally less expensive than the simplicial approximation method. Results on several circuits are presented. It is shown that the quality of the polytope approximation is substantially better than an ellipsoidal approximation.<<ETX>>
44275614
Cell-level placement for improving substrate thermal distribution
The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.
16309802
Virtual Navigation of Complex Scenes using Clusters of Cylindrical Panoramic Images
The traditional approach of generating novel virtual views of an object or a scene is to render the appropriate 3-D model. Higher realism can be achieved by texture-mapping object surfaces or simulating surface reflectance properties. The alternative is to render directly from the original images; this approach, which is based on pixel interpolation or reprojection, is called image-based rendering. In this technical report, we describe a technique that enables virtual navigation within a complex environment using an image-based rendering technique. In particular, we make use of clusters of cylindrical panoramic images. Each cluster of panoramic images allows the user to smoothly navigate within a particular area, say within a single room. Having a collection of such interconnected clusters would enable the user to seamlessly navigate within a complex environment, such as an entire floor of a building, with each cluster representing a room. To achieve this goal, we examine a few techniques for image-based rendering using a cluster of cylindrical panoramic images to synthesize views from virtual viewpoints. We also describe our method for enabling smooth transition between clusters. 1Computer Science Dept., Duke University, Durham, NC 27708 c Digital Equipment Corporation, 1997 This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of the Cambridge Research Laboratory of Digital Equipment Corporation in Cambridge, Massachusetts; an acknowledgment of the authors and individual contributors to the work; and all applicable portions of the copyright notice. Copying, reproducing, or republishing for any other purpose shall require a license with payment of fee to the Cambridge Research Laboratory. All rights reserved. CRL Technical reports are available on the CRL’s web page at http://www.crl.research.digital.com. Digital Equipment Corporation Cambridge Research Laboratory One Kendall Square, Building 700 Cambridge, Massachusetts 02139
589178
Multi-Layered Image-Based Rendering
In this article, we describe a multi-layered image-based rendering system that can use different types of input to produce and render new environments. Each separate input that can be manipulated independently is called a layer. In our implementation, the types of layers that can be manipulated are the image-based and 3-D-based layers. The computation required for rendering the newlycrafted environment is reduced by using cached composite snapshots of that environment at reference poses. These cached snapshots are used to directly generate novel views, and the original layers are used only when necessary. Another key concept is the identification of types of holes generated as a result of pixel transfer from the composite snapshots to the generated view. For optimal rendering quality, the algorithm used in filling these holes is specific to the hole type (either intralayer or interlayer). The ideas embodied in our multi-layered IBR system are useful in augmenting the capabilities of applications that require fast and geometrically consistent rendering of 3-D scenes such as video editing.
2096181
Video editing using figure tracking and image-based rendering
We describe a new approach to video editing based on the semi-automatic segmentation of video into multiple layers and the composition of layers using image-based rendering. Using figure tracking and background motion estimation, we can segment a moving figure and reconstruct the background. Using geometrically-correct pixel reprojection, layers can be composited on the basis of the geometry of the underlying scene and the position of a virtual camera. We have implemented a prototype editing system called SpliceWorld.
41028764
Large environment rendering using plenoptic primitives
One of the most difficult tasks in computer graphics is to enable virtual walkthroughs in very large and complicated environments that are photorealistic, seamless, and in real time. Current image-based rendering techniques, while capable of photorealism and interactive speeds, have failed in practice to extend to visualizations of such environments. We demonstrate an approach that defines a virtual walkthrough experience using plenoptic primitives (PPs). A PP can be any type of local visual experience: 360/spl deg/ static panorama, panoramic video (PV), lumigraph/light field representation, or concentric mosaics (CMs). By combining them judiciously, user experience can be authored with significantly reduced effort while maintaining high-quality user experience. We illustrate our technique on synthetic and real environments using PVs and CMs and show how the problem of achieving smooth transitions among PVs and CMs can be solved by using position-dependent local geometries.
46574524
3-D scene data recovery using omnidirectional multibaseline stereo
A traditional approach to extracting geometric information from a large scene is to compute multiple 3-D depth maps from stereo pairs or direct range finders, and then to merge the 3-D data. However, the resulting merged depth maps may be subject to merging errors if the relative poses between depth maps are not known exactly. In addition, the 3-D data may also have to be resampled before merging, which adds additional complexity and potential sources of errors. This paper provides a means of directly extracting 3-D data covering a very wide field of view, thus by-passing the need for numerous depth map merging. In our work, cylindrical images are first composited from sequences of images taken while the camera is rotated 360/spl deg/ about a vertical axis. By taking such image panoramas at different camera locations, we can recover 3-D data of the scene using a set of simple techniques: feature tracking, an 8-point structure from motion algorithm, and multibaseline stereo. We also investigate the effect of median filtering on the recovered 3-D point distributions, and show the results of our approach applied to both synthetic and real scenes.