18525423
An efficient and optimal algorithm for simultaneous buffer and wire sizing
In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10000 segments and buffers, the CPU time is only 0.255 s. We then extend our result to handle interconnect trees. We present an algorithm SBWS-T which always gives the optimal solution. Experimental results show that SBWS-T is faster than the greedy wire sizing algorithm in practice.
6722156
An efficient and effective detailed placement algorithm
In the past few years, there has been a lot of research in the area of global placement. In comparison, not much attention has been paid to the detailed placement problem. Existing detailed placers either fail to improve upon the excellent solution quality enabled by good global placers or are very slow. To handle the above problems, we focus on the detailed placement problem. We present an efficient and effective detailed placement algorithm to handle the wirelength minimization problem. The main contributions of our work are: (1) an efficient Global Swap technique to identify a pair of cells that can be swapped to reduce wirelength; (2) a flow that combines the Global Swap technique with other heuristics to produce very good wirelength; (3) an efficient single-segment clustering technique to optimally shift cells within a segment to minimize wirelength. On legalized mPL5 global placements on the IBM standard-cell benchmarks, our detailed placer can achieve 19.0%, 13.2% and 0.5% more wirelength reduction compared to Fengshui5.0, rowironing and Domino respectively. Correspondingly we are 3.6/spl times/ 2.8/spl times/ and 15/spl times/ faster. On the ISPD05 benchmarks (Gi-Joon Nam et al., 2005), we achieve 8.1% and 9.1% more wirelength reduction compared to Fengshui5.0 and rowironing respectively. Correspondingly we are 3.1/spl times/ and 2.3/spl times/ faster.
24078054
Greedy wire-sizing is linear time
The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, which implies that the run time of GWSA is linear with respect to the number of wire segments for any fixed precision of the solution. Moreover, we also prove that this is true for any starting solution. This is a surprising result because previously it was believed that in order to guarantee convergence, GWSA had to start from a solution in which every wire segment is set to the minimum (or maximum) possible width. Our result implies that GWSA can use a good starting solution to achieve faster convergence. We demonstrate this point by showing that the minimization of maximum delay and the minimization of area subject to maximum delay bound using Lagrangian relaxation can be sped up by more than 50%.
53246587
A revisit to floorplan optimization by Lagrangian relaxation
6347443
IPR: An Integrated Placement and Routing Algorithm
In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all previous placement approaches optimize some very primitive interconnect models during placement. These models are far from the actual interconnect implementation in the routing stage. As a result, placement solution considered to be good by primitive interconnect models may turn out to be poor after routing. In addition, the placement may not even be routable and timing closure may not be achievable. In this paper, we propose to address the inconsistency between the placement and routing objectives by fully integrating global routing into placement. As a first attempt to this novel approach, we focus on routability issue. We call the proposed algorithm for routing congestion minimization IPR (integrated placement and routing). To ensure the algorithm to be computationally efficient, efficient placement and routing algorithms FastPlace, FastDP and FastRoute are integrated, and well-designed methods are proposed to integrate them efficiently and effectively. Experimental results show that IPR reduces overflow by 36%, global routing wirelength by 3.6%, and runtime by 36% comparing to ROOSTER, which is the previous best academic routability- driven placer.
52810492
Optimal cell flipping in placement and floorplanning
In a placed circuit, there are a lot of movable cells that can be flipped to further reduce the total wirelength, without affecting the original placement solution. We aim at solving this flipping problem optimally. However, solving such a problem optimally is non-trivial given the gigantic sizes of modern circuits. We are able to identify a large portion of cells (about 75%) of which the orientation (flipped or not flipped) can be determined independent of the orientations of all the other cells. We have derived three non-trivial conditions to identify those so called independent cells, strictly solvable cells and conditionally solvable cells. In this way, we can greatly reduce the number of cells whose orientations are dependent on each other. Finally, the cell flipping problem of the remaining dependent cells can be formulated as a mixed integer linear programming (MILP) problem and solved optimally. However, this may still be too slow for extremely large circuits and we have applied two other methods, linear programming (LP) and linear programming followed by mixed integer linear programming (LP+MILP) to solve the problem. Experimental results show that by identifying those independent and solvable cells first and applying the LP+MILP technique, we can solve this flipping problem effectively and obtain results just 0.01% more than the optimal. In addition, we can improve the wirelength and number of overflow tiles by 5% and 9% respectively on the floorplanning benchmarks
42221171
The generalized Direction Vector I test
Abstract The Direction Vector I (DVI) test [IEEE Transaction on Parallel and Distributed Systems 4 (11) (1993) 1280] is an efficient and precise data dependence method to determine whether integer solutions exist for one-dimensional arrays with constant bounds under any given direction vectors. In this paper, we generalize the (DVI) test. The generalized Direction Vector I (GDVI) test can be applied towards determining whether integer solutions exist for one-dimensional arrays with both constant and variable limits under any given direction vectors, improving the precision and applicability of the DVI test. Experiments with benchmark showed that among 12 152 pairs of tested one-dimensional arrays consisting of the same pair of array references with different direction vectors, 2124 had their data dependence analysis amended by the GDVI test. That is, the GDVI test increases the success rate of the DVI test by approximately 17.5%.
22379683
Analyzing reconfigurable algorithms for managing replicated data
We analyze reconfigurable algorithms for managing replicated data to determine how often one should detect and react to failure conditions so that reorganization operations can be performed at the appropriate time to improve the availability of replicated data. We use dynamic voting as a case study to reveal design trade-offs for designing such reconfigurable algorithms and illustrate how often failure detection and reconfiguration activities should be performed so as to maximize data availability. Stochastic Petri nets are used as a tool to facilitate our analysis.
17686405
A time-series biclustering algorithm for revealing co-regulated genes
Although existing bicluster algorithms claimed to be able to discover co-regulated genes under a subset of given experiment conditions, they ignore the inherent sequential relationship between crucial time points and thus are not applicable to analyze time-series gene expression data. A simple and effective deletion-based algorithm, using the mean squared residue score as a measure, was developed to bicluster time-series gene expression data. While enforcing a threshold value for the score, the algorithm alternately eliminates genes and time points according to their correlation to the bicluster. To ensure the time locality, only the starting and ending points in the time interval are eligible for deletion. As a result, the number of genes and the length of time interval are simultaneously maximized. Our experimental results shown that the proposed method is capable of identifying co-regulated genes characterized by partial time-course data that previous methods failed to discover.
7900750
A Web-service oriented framework for building SCORM compatible learning management systems
Managing the large amount of learning content involved in the development of an expandable learning management system (LMS) is a critical task for most educational organizations. In designing such a system, consideration must be given not only to the requirement of instructors and students, but also to the adaptive qualities of the system itself, because of the rapidly changing software environment. Unlike most enterprises, educational organization can't afford high system maintenance. Development of a flexible, expandable and reliable learning management system is, therefore, imperative. This paper proposes a Web service oriented framework in building a sharable content object reference model (SCORM) compatible LMS. We integrated the SCORM concept with distributed computing technologies to build the components of the LMS and demonstrate how these services can be configured to create a complete system. This framework increases reusability and reduces the maintenance requirements of the LMS. It provides a way for small educational organizations, with limited resources, to build a complete SCORM compatible LMS. In such an ideal situation, the content provider not only provides the content, but also the service for the consumers of that content.
27561759
Splice site prediction using support vector machines with a Bayes kernel
One of the most important tasks in correctly annotating genes in higher organisms is to accurately locate the DNA splice sites. Although relatively high accuracy has been achieved by existing methods, most of these prediction methods are computationally extensive. Due to the enormous amount of DNA sequences to be processed, the computational speed is an important issue to consider. In this paper, we present a new machine learning method for predicting DNA splice sites, which first applies a Bayes feature mapping (kernel) to project the data into a new feature space and then uses a linear Support Vector Machine (SVM) as a classifier to recognize the true splice sites. The computation time is linear to the number of sequences tested, while the performance is notably improved compared with the Naive Bayes classifier in terms of classification accuracy, precision, and recall. Our classification results are also comparable to the solution quality obtained by the SVMs with polynomial kernels, while the speed of our proposed method is significantly faster. This is a notable improvement in computational modeling considering the huge amount of DNA sequences to be processed.