14345809
A geometric algorithm for automated design of multi-stage molds for manufacturing multi-material objects
This paper describes a geometric algorithm for automated design of multi-stage molds for manufacturing multi-material objects. In multi-stage molding process, the desired multi-material object is produced by carrying out multiple molding operations in a sequence, adding one material in the target object in each mold-stage. We model multi-material objects as an assembly of single-material components. Each mold-stage can only add one type of material. Therefore, we need a sequence of mold-stages such that (1) each mold-stage only adds one single-material component either fully or partially, and (2) the molding sequence completely produces the desired object. In other to find a feasible mold-stage sequence, our algorithm decomposes the multi-material object into a number of homogeneous components to find a feasible sequence of homogeneous components that can be added in sequence to produce the desired multi-material object. Our algorithm starts with the final object assembly and considers removing components either completely or partially from the object one-at-a-time such that it results in the previous state of the object assembly. If the component can be removed from the target object leaving the previous state of the object assembly a connected solid then we consider such decomposition a valid step in the stage sequence. This step is recursively repeated on new states of the object assembly, until the object assembly reaches a state where it only consists of one component. When an object-decomposition has been found that leads to a feasible stage sequence, the gross mold for each stage is computed and decomposed into two or more pieces to facilitate the molding operation. We expect that our algorithm will provide a step towards automating the design of multi-stage molds and therefore will help in reducing the mold design lead-time for multi-stage molds.
6821018
Concurrent evaluation of machinability during product design
An approach to evaluating the machinability of a part during the design stage, which performs systematic generation and evaluation of machining alternatives, is discussed. The results of the analysis provide feedback to the designer about problems that might arise with the machining and information to the manufacturing engineer about which machining processes and process parameters are most desirable.<<ETX>>
7211906
Manufacturing feature instances: which ones to recognize?
Manufacturing features and feature-based representations have become an integral part of research on manufacturing systems, largely due to their ability to model correspondences between design information and manufacturing operations. However, several research challenges still must be addressed in order to place feature technologies into a solid scientific and mathematical framework. One challenge is the issue of alternatives in feature-based planning. Even after one has decided upon an abstract set of features to use for representing manufacturing operations, the set of feature instances used to represent a part is by no means unique. For a complex part, many (sometimes infinitely many) different manufacturing operations can potentially be used to manufacture various portions of the part. Some of these feature instances will appear in useful manufacturing plans, and others will not. In order to reduce the number of alternative manufacturing plans that must be examined, we require a systematic means of specifying which feature instances are of interest. This paper addresses the issue of alternatives by introducing the notion of primary feature instances, which we contend are sufficient to generate all manufacturing plans of interest. To substantiate our argument, we describe how various instances in the primary feature set can be used to produce the desired plans. Furthermore, we discuss how this formulation overcomes computational difficulties faced by previous work, and present some complexity results for this approach in the domain of machined parts. “Also with: Nationaf Institute of Standards and Technology, Manufacturing Systems Integration Division Building 220, Room A-127, Gaithersburg, MD 20899. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advanta$e, the ACM copyright notice and the title of the publication and Its date appear, and notice is given that copying is by permission of the Association of Computing Machinery.To copy otherwise, or to republish, requires a fee and/or specific permission. Solid Modeling ’95, Salt Lake City, Utah USA
12219775
Geometric algorithms for containment analysis of rotational parts
Abstract This paper describes a system and underlying algorithms to perform geometric containment analysis to determine if a newly designed rotational part can be manufactured from a part in an existing database of rotational parts. Only material removal of the database part is considered in order to obtain the newly designed part from the database part. The system uses a three-step algorithm to test for containment. The first step analyzes feasibility of containment using bounding cylinders. If the bounding cylinder of the query part is bigger than the part in the database, then the database part cannot contain the query part and it is eliminated from consideration. The second step analyzes feasibility of containment by ignoring off-axis features. Any part that fails to satisfy containment at this stage is eliminated from consideration. The third step analyzes the remaining parts from the database for feasibility of containment by including the off-axis features. Finally, the system rank-orders all the database parts that can contain the query part based on their volume differences with the query part. The system described in this paper can be used by designers and process planners to find an existing part that can be used as a stock to manufacture a newly designed part. This capability is expected to significantly reduce proliferation of parts, to improve manufacturing responsiveness, and to reduce the cost of new products.
532672
IMACS: A Case Study in Real-World Planning
This article discusses the complexities of real-world planning and how to create planning systems to address them. IMACS (Interactive Manufacturability Analysis and Critiquing System), an automated designer's aid, evaluates machined parts and suggests design modifications to improve their manufacturability, offering advantages over the planning techniques used in classical planning systems.
13998462
Geometric algorithms for computing cutter engagement functions in 2.5D milling operations
Cutter engagement is a measure that describes what portion of the cutter is involved in machining at a given instant of time. During profile milling of complex geometries, cutter engagement varies significantly along the cutter path. Cutter engagement information helps in determining the efficiency of the cutter path and also helps in improving it by adjusting the feed rate. This paper describes geometric algorithms for computing piece-wise continuous closed-form cutter engagement functions for 2.5D milling operations. The results produced by our algorithm are compared with the results obtained by discrete simulations of the cutting process and appear to match very well.
15204415
Dynamic conditional branch balancing during the high-level synthesis of control-intensive designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branches with fewer scheduling steps. This increases the opportunities to apply code motions, such as conditional speculation that duplicate operations into the branches of a conditional block. (2) Determining if an operation can be conditionally speculated into multiple basic blocks either by using existing idle resources or by creating new scheduling steps. These strategies lead to balancing of the number of steps in the conditional branches without increasing the longest path through the conditional block. Algorithms for these strategies have been implemented within the Spark high-level synthesis framework that accepts a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. Experiments on two moderately complex industrial-strength applications, namely, MPEG-1 and the GIMP image processing tool, demonstrate that conditional speculation is ineffective without using these strategies.
37175673
A methodology to design efficient BIST test pattern generators
This paper describes a new technique to design efficient test pattern generators (TPGs) for built-in self-test (BIST). The proposed technique identifies compatible circuit inputs that can be connected to the same TPG stage in the test mode. Compatibility between circuit inputs is determined by analyzing the circuit function to guarantee coverage of all faults in a given target fault set. Unlike pseudo-exhaustive testing, circuit inputs that fanout to the same output can be compatible, provided that connecting them to the same TPG stage does not cause any loss of fault coverage. Experimental results show that TPGs designed by the proposed technique achieve 100% stuck-at fault coverage in practical test length (/spl les/2/sup 28/) with low hardware overhead and performance penalty for a wide range of benchmark circuits.
8613156
Loop shifting and compaction for the high-level synthesis of designs with complex control flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a technique called loop shifting that incrementally exploits loop level parallelism across iterations by shifting and compacting operations across loop iterations. Our experimental results show that loop shifting is particularly effective for the synthesis of designs with complex control especially when resource utilization is already high and/or under tight resource constraints. In situations when further loop unrolling (or initiating another iteration of the loop body) leads to a sharp increase in the longest combinational path in the circuit and the circuit area, loop shifting is able to achieve up to 20% reduction in the input-to-output delay in the synthesized circuit. We implemented loop shifting within the SPARK parallelizing high-level synthesis framework and present results for experiments on designs derived from multimedia and image processing applications.
8312479
Using global code motions to improve the quality of results for high-level synthesis
The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code-motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We have implemented these code transformations, along with supporting code-motion techniques and variable renaming techniques, in a high-level synthesis research framework called Spark. Spark takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. We present results for experiments on designs derived from three real-life multimedia and image processing applications, namely, the MPEG-1 and -2 and GNU image manipulation program applications. We find that the speculative-code motions lead to reductions between 36% and 59% in the number of states in the finite-state machine (controller complexity) and the cycles on the longest path (performance) compared with the case when only nonspeculative code motions are employed. Also, logic synthesis results show fairly constant critical path lengths (clock period) and a marginal increase in area.
29303565
Delay Fault Testing: How Robust are Our Models?
This panel will debate fundamental concepts in delay fault testing. A basic assumption in delay fault testing is that for a given transition propagated along a path, the path delay does not depend on values and transitions at circuit nodes that do not belong to the path. Is this assumption justified? If not, as some panelists will argue, then our current test procedures may miss some of the faults they target, and a lot of the current work in robust delay fault testing and in the synthesis of robust-testable circuits may be unreliable. A related question to be debated by the panel is whether a circuit passing a complete set of robust path delay tests at clock period T is guaranteed to perform its intended function at any clock period >= T. What are the delay models for which the answer is always true? What are the limitations of these models? Do we need to change the way we test circuits for delay faults? Other important questions deal with the hardware generating the tests: Can the response to the test be measured in a meaningful way (from a timing point of view)? Is the generating hardware capable of applying all two-pattern tests ? What delay model should be use to have a reasonable trade-off between accuracy and practicality? 502 O-8186-7304-4/96 $05.00