5304492
Design specifications of a generic supply chain simulator
This paper describes a design specification for a generic, supply-chain-simulation system. The proposed simulation system is based on schedule-driven and stock-driven control methods to support the supply chain management. The simulation system includes three processing modes: business process flows, material process flows, and information process flows. The paper also discusses interface data requirements for the proposed supply-chain-simulation system.
6621245
Application of Machine Shop Data Model in Manufacturing Simulation
Simulation technology holds tremendous promise for the manufacturing industry. A machine shop data model has been developed at the National Institute of Standards and Technology (NIST) to represent neutral machine shop data for supporting machine shop manufacturing simulation [1]. This paper discusses the data model and its application in manufacturing simulation. The paper also proposes an application framework that integrates the simulation model, machine shop database, and machine shop XML (Extensible Markup Language) data document. A prototype system is developed to present the application of machine shop data model using the proposed framework.
7326399
A Scalable Update Management Mechanism for Query Result Caching Systems at Database-Driven Web Sites
A key problem in using caching technology for dynamic contents lies in update management. An update management scheme should be very efficient without imposing much extra burden to the system, especially to the original database server. We propose an scalable update management mechanism for query result caching in database-backed Web sites. Our mechanism employs a two-phase consistency checking method, which prunes out unaffected queries at the earliest possible moment. The method scales well with a high number of cached instances.
10094158
System and software designs for transaction processing in asymmetric communication environments
Observing that it is impractical to use traditional methods to control concurrency in broadcast-based asymmetric communication environments, we introduce a concurrency control protocol designed for broadcast-based transaction processing called Server Timestamp and Update Broadcast Supported Concurrency (STUBcast). STUBcast supports two new correctness criteria proposed in this paper—Single Serializability and Local Serializability. These criteria are weaker than global serializability, but are practical and easier to achieve in broadcast environments. This article also discusses the software design for the simulation program and the protocol implementation. Simulation results collected using our simulation program suggest that STUBcast could be very efficient in realistic application environments. Copyright © 2003 John Wiley & Sons, Ltd.
46434197
Flow Control Strategy for Flexible Machining and Assembly System
Abstract In this paper an effective flow control strategy for a Flexible Machining and Assembly System is proposed using the concepts of operation-oriented and, combined push and pull control method. The proposed flow control mechanism could meet production demands with a minimum makespan while satisfying assigned due-dates and keeping a low volume of work-in-process at the same time. It also considers machine failures and rush jobs.
206579905
Improving multistage network performance under uniform and hot-spot traffics
The major performance drawbacks of multistage interconnection networks are due to link contention and message blockage. To remedy this problem, the authors propose a switch design which uses two independent routes between each input port and each output port within a switch. With proper routing control mechanisms, the adverse effect on link conflicts can be greatly reduced. Various simulations are used to illustrate the performance improvement of this new design under both uniform and hot-spot traffic patterns.<<ETX>>
30590203
Efficient State-Saving Architectures for Power-Mode Switching
Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce switching speed and energy. We present a heuristic to save the most relevant cache contents so that power and delay overheads are minimized. To measure the area overhead a synthesizable VHDL model was designed.