3264607
Congestion Control in Computer Networks: Trends and Issues
Myths about congestion control are examined, and an explanation of why the trend toward cheaper memory, higher-speed links, and higher-speed processors has intensified the need to solve the congestion problem is provided. A number of proposed solutions are described, and a classification of congestion problems as well as their solutions is presented. The reasons why the problem is so difficult are identified, and the protocol design decisions that affect the design of a congestion control scheme are discussed. The author's recent proposals, namely, timeout-based congestion control, a DECbit scheme and a delay-based scheme for congestion avoidance are described, and areas for future research are suggested. >
62102705
Performance analysis of FDDI token ring networks: effect of parameters and guidelines for setting TTRT
Fiber-Distributed Data Interface (FDDI) is a 100-Mbps Local Area Network (LAN) standard being developed by the American National Standards Institute (ANSI). It uses a timed-token access method and allows up to 500 stations to be connected with a total fiber length of 200 km. We analyze the performance of FDDI using a simple analytical model and a simulation model. The performance metrics of response time, efficiency, and maximum access delay are considered. The efficiency is defined as the ratio of maximum obtainable throughput to the nominal bandwidth of the network. The access delay is defined as the time it takes to receive a usable token. The performance of FDDI depends upon several workload parameters; for example; the arrival pattern, frame size, and configuration parameters, such as the number of stations on the ring, extent of the ring, and number of stations that are waiting to transmit. In addition, the performance is affected by a parameter called the Target Token Rotation Time (TTRT), which can be controlled by the network manager. We considered the effect of TTRT on various performance metrics for different ring configurations, and concluded that a TTRT value of 8 ms provides a good performance over a wide range of configurations and workloads.
609563
A definition of general weighted fairness and its support in explicit rate switch algorithms
We give a general definition of weighted fairness and discuss how a pricing policy can be mapped to general weighted (GW) fairness. The GW fairness can be achieved by calculating the excess fairshare (weighted fairshare of the left over bandwidth) for each VC. We show how a switch algorithm can be modified to support the GW fairness by using the excess fairshare term. We use ERICA+ as an example switch algorithm and show how it can be modified to achieve the general fairness. Simulations results are presented to demonstrate that, the modified switch algorithm achieves GW fairness. An analytical proof for convergence of the modified ERICA+ algorithm is given in the appendix.
789958
Myths about Congestion Management in High Speed Networks
Weaknesses in several recently proposed ideas about congestion control and avoidance in high-speed netwroks are identified. Both sides of the debate concerning prior reservation of resources versus walk-in service, open-loop control versus feedback control, rate control versus window control, and router-based control versus source-based control are presented. The circumstances under which backpressure is useful or not are discussed, and it is argued that a single congestion scheme is not sufficient, but that a combination of several schemes is required for complete congestion management in a network.
3236747
Use-it-or-lose-it Policies for the Available Bit Rate (ABR) Service in ATM Networks
Abstract The Available Bit Rate (ABR) service has been developed to support data applications over Asynchronous Transfer Mode (ATM). The ABR service uses a closed-loop rate-based traffic management framework where the network divides left-over bandwidth among contending sources. The ATM Forum traffic management group also incorporated open-loop control capabilities to make the ABR service robust to temporary network failures and source inactivity. An important problem addressed was whether rate allocations of sources should be taken away if sources do not use them. The proposed solutions, popularly known as the Use-It-or-Lose-It (UILI) policies, have had significant impact on the ABR service capabilities. In this paper we discuss the design, development, and the final shape of these policies and their impact on the ABR service. We compare the various alternatives through a performance evaluation.
16677800
AQuaFWiN: adaptive QoS framework for multimedia in wireless networks and its comparison with other QoS frameworks
In a wireless environment, due to topology changes and characteristics of media (interference in radio signals) the bandwidth of a link is unpredictable and possibly very low, the error rates are variable and extremely high. Provisioning and guaranteeing quality of service (QoS) in such an environment is a very challenging problem. In this paper we propose an adaptive and QoS framework to support multimedia applications in a wireless networking environment. The proposed framework is hierarchical in nature with cluster of mobile end hosts connected to a base station, base stations are connected to a supervisory node, which in turn is connected to the wired infrastructure. The changing conditions in wireless due to interference and possibly mobility, entitle that the real-time applications needing stringent QoS should be adaptable. The framework uses a generic feedback mechanism to support adaptability at all layers of the wireless network. An overview of existing wireless architectures which support QoS is given. The architectures discussed are WAMIS (wireless adaptive multimedia information system), SWAN (seamless wireless ATM network), MMWN (multimedia support for mobile wireless networks), and QGMC (QoS guarantees in mobile computing). The proposed approach is compared with these existing methods.
7565598
Towards coarse-grained mobile QoS
Supporting Quality of Service is an important objective for future mobile and wireless systems, and requires resource reservation and admission control to achieve. In this paper, we introduce a novel coarse grained approach to admission control termed Virtual Bottleneck Cell. Our approach is designed to scale to many users and handoffs, while simultaneously controlling “hot spots” and system bottlenecks. The key technique is to hierarchically control the virtual system, ensuring QoS objectives are satisfied without requiring models or accurate predictions of the users’ future locations. We develop a simple analytical model to study the system and illustrate several key components of the approach. Finally, we perform simulations in a two-dimensional network to compare the performance obtained with Virtual Bottleneck Cell with alternate schemes, including the optimal off line algorithm.
13629855
An integrated CAD system for algorithm-specific IC design
LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described. >
16168118
Defect-aware design paradigm for reconfigurable architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to avoid defects. If nanotechnology based fabrications are applied, the yield may even go down to zero, as avoiding defects during fabrication will not be a feasible option. Hence, future architectures have to be defect-tolerant. Most of the current defect-tolerance schemes introduce redundancy in architecture to combat defects. Alternatively we can introduce defect tolerance in the design-flow. In this paper we analyze the bottlenecks faced by current design-methodologies while addressing defect tolerance. We study the performance of present place and route tools on a defective fabric in terms of area and critical delay penalty, and explore routing aware placement in this context. We have proposed a new cost function, CA-RISA for improving the performance in a defect-aware environment
17211338
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall power dissipation is dominated by read and write operations in the memory subsystem. The proposed architecture and computation sequence, called low-power block-scan, takes into account the EBCOT (embedded block coding with optimized truncation) code block size, which reduces the intermediate buffer requirement between the DWT and EBCOT modules. The impact of different memory subsystem optimization techniques on the overall memory power for 2D-DWT computation was modeled. The proposed model explores the different data access patterns, memory bank partitioning, and custom memory architectures to arrive at a power-efficient DWT architecture
47572575
The Art of Computer Systems Performance Analysis
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