13972401
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing
Pseudo-exhaustive testing involves applying all possible input patterns to individual output cones of a circuit. Circuits with output cones driven by a large number of inputs often need to be partitioned to reduce the test application time. In this paper, we present an efficient heuristic partitioning procedure of polynomial complexity. Experiments on combinational benchmark circuits validate the efficiency and quality of our approach.
5894578
Test embedding with discrete logarithms
When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >
206516479
BIST TPG for SRAM cluster interconnect testing at board level
A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths.
206766191
Accurate and efficient static timing analysis with crosstalk
We have developed an accurate and efficient methodology to perform static timing analysis (STA) in combinational logic blocks in the presence of multiple crosstalk-induced noise effects. The crosstalk model used is more accurate because it considers skew, input transition times, and driver strengths. This crosstalk model is enhanced to handle timing ranges for performing STA. The methodology also uses more accurate delay models for gates. The presence of one or more coupling capacitances can create cyclic timing dependencies, even in an otherwise acyclic circuit. We have developed an approach to partition the circuit into minimal timing-iterative subcircuits (TISs) that encapsulate the cyclic timing dependencies. When used in conjunction with our levelization procedure, iterative timing analysis is confined within individual TISs. We have demonstrated that the maximum arrival time values computed by the proposed STA using integrated delay models are much closer to detailed circuit simulation results than an STA that uses the 3C/sub c/ delay model.
5347587
Process aggravated noise (PAN): new validation and test problems
How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.
45533435
BIST TPG for combinational cluster (glue logic) interconnect testing at board level
Due to the expense and complexity of boundary scan architecture (BSA) circuitry, non-boundary scan ICs (cluster ICs) are still used in modern circuit boards. A novel BIST architecture and a TPG design methodology to program this architecture are presented for testing inter-IC interconnects among combinational cluster ICs via IEEE 1149.1 BSA at board level. The two main issues that are tackled are: (1) safe testing, i.e., avoidance of conflicts at all multi-driver nets; and (2) obtaining complete coverage of all detectable faults in the interconnect. We have proposed a realistic model of interconnects that contain combinational cluster ICs, identified test requirements that must be satisfied by the TPG to achieve the above objectives, and developed a new TPG architecture that satisfies these test requirements. We have theoretically proven that the proposed technique guarantees safe and comprehensive testing of cluster interconnects and also demonstrated this fact via its applications to a few example circuits.
384064
Proximity based access control in smart-emergency departments
In this paper, we propose a proximity based automated access control (PBAC) model for smart-ED environments which improves the existing ED work-flow by automating mundane administrative procedure for secure information access, allowing caregivers to focus on the treatment of patients. The proposed access model builds on the traditional role-based access control model and extends it by including multiple authentication levels for preventing unauthorized access. We also provide a semi-formal specification for the PBAC model. We further validate it using ultra-wide-band (UWB) based prototype which was tested in ED
8454699
An Efficient Geometric Algorithm For Extracting Structural Elements to Facilitate Automated MEMS Extraction
Micro-electro-mechanical systems (MEMS) are very small devices that contain both mechanical and electrical elements with sizes in the order of microns. Design cycle time is an important consideration in the development and introduction of MEMS devices in the market. To develop extraction tools for MEMS designs, we need geometric algorithms to analyze the spatial layout of the mechanical portion of the MEMS device and extract a net-list of mechanical components. Such extracted net-list of mechanical components can be combined with the electronic component net-list to provide the complete device schematic. A key step in the extraction of mechanical elements is classification of various portions of the layout into structural elements. Because MEMS designs consist of a large number of elements, computational efficiency of the underlying extraction algorithm is very important for it to work on complex devices. This paper describes an efficient geometric algorithm for extracting structural elements from spatial layout of MEMS designs.
18759063
The Software Concordance: using a uniform document model to integrate program analysis and hypermedia
Since the source code is only one of many types of documents that must be maintained as a software system evolves, modern software development could be improved by better interoperability between source code and other software documents. The Software Concordance is a prototype programming environment that uses hypermedia services and a uniform document model to achieve this interoperability. The Software Concordance editor allows developers to enhance their inline documentation with multimedia objects and hyperlinks, while still supporting advanced program analysis including lexing, parsing and type checking. We motivate the need for environments like the Software Concordance, describe the design and implementation of its program editor, and discuss lessons learned while creating it. The system is based on a uniform, Web compatible document model for both program source code and nonprogram software documents and a corresponding API. Important technical problems addressed by this research include creating a persistent representation of program lexemes that the analysis suite considers to be ephemeral (such as keywords), providing a simple incremental parsing system, and embedding multimedia in source code without disrupting program analysis. Based on insight gained in the process of implementing the document API, a new approach to the design of a more suitable program analysis infrastructure is suggested.
15929474
Optimal offline and online registration techniques for location management with overlapping registration areas
Personal communication services (PCS) standards such as the IS-41 and the GSM use a location management scheme, which is based on registration areas (RA). Overlapping of registration areas has been proposed to reduce the overhead of location updates in such systems. Overlapping provides multiple choices for the selection of a registration area, a feature that does not appear in environments of nonoverlapping RAs. In this paper, we demonstrate how the choice of a registration area affects the number of subsequent registrations and define the problem of optimal choice based on minimization of subsequent registrations. We study two versions of the problem: 1) the deterministic (or offline) version, in which the entire trajectory of the mobile unit is known a priori, and 2) the stochastic (or online) version, in which the trajectory of the mobile unit is not known a priori, but the system has the knowledge of the mobility pattern of the mobile. The mobility pattern is modeled as a random walk across coverage area. In the deterministic case, the method presented computes an optimal solution to the registration problem. In the stochastic case, we present a method that determines the registration that minimizes the expected number of registrations by looking ahead in the probable future paths of the mobile unit. The algorithm's time complexity has exponential dependence on the length of the look-ahead. The cost of search is independent of the choice, therefore the algorithm does not increase the search cost. We also consider an alternative cost model for the stochastic case and propose a preemptive and a nonpreemptive approach each of which incurs different numbers of hard and soft registration operations. Simulation results show a reduction of 25-30 percent in number of registrations over a random-choice scheme. This can be translated to 5-20 percent effective location management load reduction for most cases, subject to the call-to-mobility ratio (CMR) of a mobile unit and search-cost-to-update-cost ratio (CCR) in the network.
13275430
Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions
In this paper, we present a framework for synthesizing I/O efficient out-of-core programs for block recursive algorithms, such as the fast Fourier transform (FFT) and block matrix transposition algorithms. Our framework uses an algebraic representation which is based on tensor products and other matrix operations. The programs are optimized for the striped Vitter and Shriver's two-level memory model in which data can be distributed using various cyclic(B) distributions in contrast to the normally used physical track distribution cyclic(B/sub d/), where B/sub d/ is the physical disk block size. We first introduce tensor bases to capture the semantics of block-cyclic data distributions of out-of-core data and also data access patterns to out-of-core data. We then present program generation techniques for tensor products and matrix transposition. We accurately represent the number of parallel I/O operations required for the synthesized programs for tensor products and matrix transposition as a function of tensor bases and data distributions. We introduce an algorithm to determine the data distribution which optimizes the performance of the synthesized programs. Further, we formalize the procedure of synthesizing efficient out-of-core programs for tensor product formulas with various block-cyclic distributions as a dynamic programming problem. We demonstrate the effectiveness of our approach through several examples. We show that the choice of an appropriate data distribution can reduce the number of passes to access out-of-core data by as large as eight times for a tensor product and the dynamic programming approach can largely reduce the number of passes to access out-of-core data for the overall tensor product formulas.