80432
Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization
Coarse-grained reconfigurable architectures aim to achieve goals of both high performance and flexibility. However, existing reconfigurable array architectures require many resources without considering the specific application domain. Functional resources that take long latency and/or large area can be pipelined and/or shared among the processing elements. Therefore, the hardware cost and the delay can be effectively reduced without any performance degradation for some application domains. We suggest such a reconfigurable array architecture template and a design space exploration flow for domain-specific optimization. Experimental results show that our approach is much more efficient, in both performance and area, compared to existing reconfigurable architectures.
18399312
Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture
Coarse-grained reconfigurable architecture aims to achieve both performance and flexibility. However, power consumption is no less important for the reconfigurable architecture to be used as a competitive processing core in embedded systems. In this paper, we show how power is consumed in a typical coarse-grained reconfigurable architecture. Based on the power breakdown data, we suggest a power-conscious configuration cache structure and code mapping technique, which reduce power consumption without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size
1907049
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
In this work, we investigate the problem of automatically mapping applications onto a coarse-grained reconfigurable architecture and propose an efficient algorithm to solve the problem. We formalize the mapping problem and show that it is NP-complete. To solve the problem within a reasonable amount of time, we divide it into three subproblems: covering, partitioning and layout. Our empirical results demonstrate that our technique produces nearly as good performance as hand-optimized outputs for many kernels
6826338
Geometric crossover for multiway graph partitioning
Geometric crossover is a representation-independent generalization of the traditional crossover defined using the distance of the solution space. Using a distance tailored to the problem at hand, the formal definition of geometric crossover allows to design new problem-specific crossovers that embed problem-knowledge in the search. The standard encoding for multiway graph partitioning is highly redundant: each solution has a number of representations, one for each way of labeling the represented partition. Traditional crossover does not perform well on redundant encodings. We propose a new geometric crossover for graph partitioning based on a labeling-independent distance that filters the redundancy of the encoding. A correlation analysis of the fitness landscape based on this distance shows that it is well suited to graph partitioning. Our new genetic algorithm outperforms existing ones.
6422061
A new branch and bound algorithm for minimizing mean tardiness in two-machine flowshops
Abstract We consider the two-machine flowshop scheduling problem with the objective of minimizing mean tardiness. Presented are several properties that are used to calculate lower bounds on total tardiness of jobs for a given partial sequence and to identify sequences dominated by others. We develop a branch and bound algorithm using these bounds and dominance rule. This algorithm is compared with an existing algorithm on randomly-generated test problems.
30845722
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders
Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. In addition, carry-save-adder (CSA) has been proven to be one of the most efficient implementation units in optimizing timing and/or area of arithmetic circuits. However, the existing approaches are restricted in using CSAs, i.e., optimizing operation trees separately without any interaction between them, resulting in a locally optimized CSA circuit. To overcome this limitation, we propose a practically efficient solution to the problem of an accurate exploration of timing and area trade-offs in optimizing arithmetic circuits in the presence of multiple operation trees using CSAs. The application of our approach is able to find a best CSA implementation of circuit in terms of timing and area.
61949387
Quantizer design and distributed encoding algorithm for source localization in sensor networks
In this paper, we propose a quantizer design algorithm that is optimized for source localization in sensor networks. For this application, the goal is to minimize the amount of information that the sensor nodes have to exchange in order to achieve a certain source localization accuracy. We show that this goal can be achieved more efficiently when "application-specific" quantizers are used. Our proposed quantizer design algorithm uses a cost function that takes into account the distance between the actual source position and the position estimated based on quantized data. We also propose a distributed encoding algorithm that is applied after quantization and achieves rate savings by merging quantization bins without any degradation of localization performance. The merging technique in the encoding algorithm exploits the fact that certain combinations of quantization bins at each node cannot occur because the corresponding spatial regions have an empty intersection. We apply these algorithms to a system where an acoustic sensor model is employed for localization. For this case, we introduce the equally distance-divided quantizer (EDQ), designed so that quantizer partitions correspond to a uniform partitioning in terms of distance. Our simulations show the improved performance of our quantizer over traditional quantizer designs. In addition, they show rate savings (32.8%, 5 nodes, 4 bits per node) when our novel bin-merging algorithms are used. Our results also show that an optimized bit allocation leads to significant improvements in localization performance with respect to a bit allocation that uses the same number of bits for each node.
2304269
Lightweight logging and recovery for distributed shared memory over virtual interface architecture
As software Distributed Shared Memory(DSM) systems become attractive on larger clusters, the focus of attention moves toward improving the reliability of systems. In this paper, we propose a lightweight logging scheme, called remote logging, and a recovery protocol for home-based DSM. Remote logging stores coherence-related data to the volatile memory of a remote node. The logging overhead can be moderated with high-speed system area network and user-level DMA operations supported by modern communication protocols. Remote logging tolerates multiple failures if the backup nodes of failed nodes are alive. It makes the reliability of DSM grow much higher. Experimental results show that our fault-tolerant DSM has low overhead compared to conventional stable logging and it can be effectively recovered from some concurrent failures.