5894578
Test embedding with discrete logarithms
When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >
12850641
Fault-oriented Test Generation for Multicast Routing Protocol Design
We present a new algorithm for automatic test generation for multicast routing. Our algorithm processes a finite state machine (FSM) model of the protocol and uses a mix of forward and backward search techniques to generate the tests. The output tests include a set of topologies, protocol events and network failures, that lead to violation of protocol correctness and behavioral requirements. We target protocol robustness in specific, and do not attempt to verify other properties in this paper. We apply our method to a multicast routing protocol; PIM-DM, and investigate its behavior in the presence of selective packet loss on LANs and router crashes. Our study unveils several robustness violations in PIM-DM, for which we suggest fixes with the aid of the presented algorithm.
19051554
BIST test pattern generators for stuck-open and delay testing
Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs.<<ETX>>
5121481
Switch-level delay test of domino logic circuits
We address the testing of delay faults in domino circuits that contain complex gates. The different ways in which these faults can cause errors are demonstrated. We identify structures in both the evaluate and the precharge logic that should be tested for delay faults. We propose conditions to generate delay tests for them, and outline extensions to handle mixed static-domino circuits. Testability results are reported for benchmark circuits that are mapped to domino gates and in-house domino circuits.
206766191
Accurate and efficient static timing analysis with crosstalk
We have developed an accurate and efficient methodology to perform static timing analysis (STA) in combinational logic blocks in the presence of multiple crosstalk-induced noise effects. The crosstalk model used is more accurate because it considers skew, input transition times, and driver strengths. This crosstalk model is enhanced to handle timing ranges for performing STA. The methodology also uses more accurate delay models for gates. The presence of one or more coupling capacitances can create cyclic timing dependencies, even in an otherwise acyclic circuit. We have developed an approach to partition the circuit into minimal timing-iterative subcircuits (TISs) that encapsulate the cyclic timing dependencies. When used in conjunction with our levelization procedure, iterative timing analysis is confined within individual TISs. We have demonstrated that the maximum arrival time values computed by the proposed STA using integrated delay models are much closer to detailed circuit simulation results than an STA that uses the 3C/sub c/ delay model.
2431223
Switch-level delay test
Gate-level models are usually used to generate tests for circuits containing non-primitive CMOS gates. It is shown that tests generated using these models and classical conditions for robust path delay testing can fail to detect delay faults in such circuits. A new delay-independent, switch-level delay test methodology, called /spl tau/-robust testing, is proposed that defines new entities called targets and proposes conditions to generate tests for each target. It is proven that, under the assumed delay model, a circuit that passes a test set containing a /spl tau/-robust test for every target is guaranteed to operate correctly at the desired speed. The effectiveness of the proposed methodology is demonstrated by (a) illustrating the difference between the delays excited by classical robust and /spl tau/-robust tests via circuit simulation, and (b) generation of /spl tau/-robust tests for benchmark circuits and comparison of /spl tau/-robust coverage of classical robust and /spl tau/-robust test sets.
8368503
Synthesis of testable RTL designs
With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to "learn" to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.
384064
Proximity based access control in smart-emergency departments
In this paper, we propose a proximity based automated access control (PBAC) model for smart-ED environments which improves the existing ED work-flow by automating mundane administrative procedure for secure information access, allowing caregivers to focus on the treatment of patients. The proposed access model builds on the traditional role-based access control model and extends it by including multiple authentication levels for preventing unauthorized access. We also provide a semi-formal specification for the PBAC model. We further validate it using ultra-wide-band (UWB) based prototype which was tested in ED
16361691
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection.
16692732
Versioned Hypermedia can improve software document management
This research was supported by the U. S. Department of Defense and by NSF CAREER award CCR-9734102. The Software Concordance project is addressing the software document management problem by providing a fine-grained version control model for software documents and their relationships using hypermedia versioning. A set of tools needed to maintain, visualize and analyze software documents is being constructed. This short paper presents research issues, initial results and a scheme for using hypermedia versioning and time stamps to automate detection of possible semantic non-conformance among software artifacts.
6938010
Flip-flop chaining architecture for power-efficient scan during test application
Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature, does not incorporate reordering of scan cells; thus avoiding timing and routing overheads. ATPG software ATALANTA was used for test vector generation. The algorithm was verified for ISCAS’89 benchmark circuits, where it showed as much as 27.3% of reduction in switching activity during scan operations.