15619003
A Graphical User Interface Design for Network Simulation
Abstract This article describes a prototyping effort of a flexible graphical user interface (GUI) for a simulation tool called COPS. The GUI is designed to allow parameter setup for all modules in simulation model, and can be easily replaced by new GUIs implemented in different languages/graphical tools. This article provides design guidelines and implementation details of the flexible GUI.
30064725
Potential Fraudulent Usage in Mobile Telecommunications Networks
This paper investigates the fraudulent usage of mobile telecommunications services due to cloned subscriber identity modules (SIMs). In GSM or the Universal Mobile Telecommunication System (UMTS), a mobile phone or mobile station uses its SIM to gain network access through authentication. If the SIM of a legal user is cloned, then the cloned SIM can be used for GSM/UMTS authentication and fraudulent usage may occur. Under the existing GSM/UMTS mobility management and call setup procedures, we show how quickly the fraudulent usage can be detected. We also propose a simple solution to speed up the detection of potential fraudulent usage.
6968436
Optimal memory management for time warp parallel simulation
Recently there has been a great deal of interest in performance evalution of parallel simulation. Most work is devoted to the time complexity and assumes that the amount of memory available for parallel simulation is unlimited. This paper studies the space complexity of parallel simulation. Our goal is to design an efficient memory management protocol which guarantees that the memory consumption of parallel simulation is of the same order as sequential simulation. (Such an algorithm is referred to as a optimal.) First, we derive the relationships among the space complexities of sequential simulation, Chandy-Misra simulation [2], and Time Warp simulation [7]. We show that Chandy-Misra may consume more storage than sequential simulation, or vice versa. Then we show that Time Warp never consumes less memory than sequential simulation. Then we describe cancelback, an optimal Time Warp memory management protocol proposed by Jefferson. Although cancelback is considered to be complete solution for the storage management problem in Time Warp, some efficiency issues in implementing this algorithm must be considered. We propose an optimal algorithm called artifical rollback. We show that this algorithm is easy to implement and analyze. An implementation of artificial rollback is given, which is integrated with processor scheduling to adjust the memory consumption rate based on the amount of free storage available in the system.
18781018
Eliminating the boundary effect of a large-scale personal communication service network simulation
Eliminating the boundary effects is an important issue for a large-scale personal communication service (PCS) network simulation. A PCS network is often modeled by a network of hexagonal cells. The boundary may significantly bias the ouput statistics if the number of hexagonal cells is small in a PCS network simulation. On the other hand, if the simulation is to be completed within a reasonable time on the available computing resources, the number of cells in the simulation cannot be too large. To avoid the inaccuracy caused by the boundary effect for a PCS network simulation with limited computing resources, we propose wrapping the hexagonal mesh into a homogeneous graph (i.e., all nodes in the graph are topologically identical). We show that by using the wrapped hexagonal mesh, the inaccuracy of the output measures can be limited even though the number of cells in the simulation is small. We can thus obtain the same statistical accuracy while using significantly less computation power than required for a simulation without cell wrapping.
206549585
vGPRS: a mechanism for voice over GPRS
This paper proposes vGPRS, a voice over IP (VoIP) mechanism for a general packet radio service (GPRS) network. In this approach, a new network element called VoIP mobile switching center (VMSC) is introduced to replace standard GSM MSC. The vGPRS approach is implemented using standard H.323, GPRS, and GSM protocols. Thus, existing GPRS and H.323 network elements are not modified. Furthermore, both standard GSM and GPRS mobile stations can be used to receive vGPRS service, which need not be equipped with the VoIP (i.e., H.323) terminal capabilities.
10935949
A time-division algorithm for parallel simulation
Most parallel simulation algorithms (e.g., Chandy and Misra’s algorithm or the Time Warp algorithm) are based on a “space-division” approach. The parallelism of this approach is limited by the causality constraints. Another approach, the “time-division” approach, may provide more parallelism if the time domain is appropriately partitioned. We present a time-division parallel simulation algorithm that partitions the time domain via state matching, We show that linear speed up can be achieved. For a complex system, the best parallel simulation approach is to integrate “time-division” and “space-division” algorithms: the simulated system is partitioned into several subsystems; a subsystem may be simulated by the time-division approach (e. g., our algorithm), while the overall system is simulated by the space-division approach.
27728163
Hybrid routing
A general-purpose routing algorithm for very-large-scale integrated (VLSI) circuits and printed circuit board (PCB) designs is proposed. Ideas behind the maze-running algorithm and the hierarchical routing algorithm are combined into a powerful algorithm called hybrid routing. The new algorithm demonstrates a speed compatible to a hierarchical router and produces routings with quality equivalent to that obtained by a maze router. Hybrid routing is based on the maze-running method with a third search dimension added. The extra search space is built by recursively constructing a hierarchy of coarser grid meshes. By means of a parameter-controlled expansion into the coarser meshes, the hybrid router is able to find the preferred search region very quickly and will not miss local information as a hierarchical router does. A user-given parameter can turn the algorithm into a pure maze router, a pure hierarchical router, or a wide spectrum of hybrid routers with different speed/quality characteristics between the extremes. The algorithm has been implemented and integrated into a global router that can handle large-scale routing, such as that encountered in the sea-of-gates layout. >
10756003
A 3-step approach for performance-driven whole-chip routing
We propose a 3-step approach for whole-chip detail routing. In the first step, we construct a performance-driven Steiner tree for each net ignoring the existence of other nets. In the second step, we optimally assign significant wire segments of all trees to the tracks of a two-dimensional, two-layer grid under the design rule constraint. Finally, in the third step, we complete the remaining local short connection between net terminals and those assigned wire segments and resolve any violations or congestion. We have incorporated this approach into an industrial VDSM design flow. Experimental results on large benchmark circuits implemented in a TSMC 0.18um CMOS process have demonstrated the effectiveness of the proposed approach. We achieve more than 14% improvement over a state-of-art commercial performance-driven router in a critical path delay. Our tool can be viewed as a preprocessor for a router. Users do not have to change their existing design flow. Only a small time-efficient step is needed to achieve the performance gain.
37430657
On the boundary inequality for bandwidth of graphs
28156768
A VLSI implementation of the blowfish encryption/decryption algorithm
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-rescheduling method, the critical path delay is improved by 21.7%. We have successfully implemented it using Compass cell library targeted at a 0.6 μm TSMC SPTM CMOS process. The die size is 5.7x6.1 mm and the maximum frequency is 50MHz.
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >