18607273
X-tolerant test response compaction
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.
5825110
Debating the Future of Burn-In
2345381
Optimized reseeding by seed ordering and encoding
Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern; and 3) shifting the captured response out of the scan chains. The shifting of the test pattern out of the scan chains is overlapped with shifting in the next test pattern. The pattern shifted into the scan chains comes from the output of the pseudorandom pattern generator (PRPG); this pattern is determined by the initial state or seed of the PRPG (the contents of the PRPG at the beginning of the shifting operation). In a pseudorandom cycle, the initial state is the final state (last PRPG contents) from the previous cycle. The initial state of a deterministic cycle is shifted into the PRPG either from an a tester or from an on-chip BIST controller. This paper describes techniques to minimize the number of deterministic seeds that must be used: the number of seeds determines the required storage either on the ATE or the chip being tested. These techniques interleave pseudorandom and deterministic cycles rather than first applying all of the pseudorandom cycles and then the deterministic cycles. The decision of when to change from a pseudorandom cycle to a deterministic cycle is made by comparing the final state of the pseudorandom cycle with previously generated ATPG patterns or by carrying out fault simulation on the final state. Which deterministic pattern is chosen for the deterministic cycle critically influences the remainder of the test. A methodology for doing this is described. In addition to interleaving test cycles, it is possible to use partial cycles in which the PRPG operates for a few clocks without loading the scan chains. This allows a new seed to be present without loading the seed from the ATE or controller. As might be suspected, this reduces the number of stored seeds at the penalty of more complexity in the control sequence. These techniques were simulated and compared with conventional reseeding for some ISCAS'89 benchmarks. Improvements varied between 25% and 85% in the required seed storage.
206458818
Delay defect characteristics and testing strategies
Several factors influence production delay testing and corresponding DFT techniques: defect sources, design styles. ability to monitor process characteristics, test generation time. available test time, and tester memory. We present an overview of delay defect characteristics and the impact of delay defects on IC quality. We also discuss practical delay-testing strategy in terms of test pattern generation, test application speed, DFT, and test cost.
35844193
Design for testability and testing of IEEE 1149.1 TAP controller
The Test Access Port (TAP) controller is a very important circuit present in all IC chips that are compliant with the IEEE 1149.1 Boundary Scan standard. Although the main purpose of boundary scan is to facilitate board-level testing, it is also used for many other testing and non-testing purposes (e.g., memory and logic BIST wrappers to enable embedded core test, programming FPGAs, checkpointing and recovery of dependable systems, etc.). Hence, it is important to thoroughly test the TAP controller before using it for other purposes. In this paper, we present techniques for designing and testing the TAP controller. Our design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results. Our TAP controller design technique does not require any extra I/O pins and can be easily automated and incorporated into test tools.
5916562
Testing digital circuits with constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of logic values in digital circuits and two techniques for preventing them from damaging the circuit or corrupting the test results. The hardware overhead of our technique is minimal and imposes negligible delay overhead. Simulation results show that the area overhead of our techniques is less than 1%. Unlike previous techniques, the fault coverage of the legal test patterns in a given test set is not sacrificed with our techniques. Furthermore, our techniques are applicable during IC production test, BIST, board-level tests and system-level tests.
35096806
Human Face Identification from Video Based on Frequency Domain Asymmetry Representation Using Hidden Markov Models
In this paper we introduce a novel human face identification scheme from video data based on a frequency domain representation of facial asymmetry. A Hidden Markov Model (HMM) is used to learn the temporal dynamics of the training video sequences of each subject and classification of the test video sequences is performed using the likelihood scores obtained from the HMMs. We apply this method to a video database containing 55 subjects showing extreme expression variations and demonstrate that the HMM-based method performs much better than identification based on the still images using an Individual PCA (IPCA) classifier, achieving more than 30% improvement.
45398591
A One Bit Facial Asymmetry Code (FAC) in Fourier Domain for Human Recognition
The present paper introduces a novel set of biometrics based on facial asymmetry measures in the frequency domain using a compact one-bit representation. A simplistic Hamming distance-type classifier is proposed as a means for matching bit patterns for identification purposes which is more efficient than PCA-based classifiers from storage and computation point of view, and produces equivalent results. A comparison with spatial intensity-based asymmetry measures suggests that our proposed measures are more robust to intra-personal distortions with a misclassification rate of only 4.24% on the standard facial expression database (Cohn-Kanade) consisting of 55 individuals. In addition, a rigorous statistical analysis of the matching algorithm is presented. The role of asymmetry of different face parts (e.g., eyes, mouth, nose) is investigated to determine which regions provide the maximum discrimination among individuals under different expressions.
8080205
Using Feature Combination and Statistical Resampling for Accurate Face Recognition Based on Frequency Domain Representation of Facial Asymmetry
This paper explores the efficiency of facial asymmetry in face identification tasks using a frequency domain representation. Satisfactory results are obtained for two different tasks, namely, human identification under extreme expression variations and expression classification, using a PCA-type classifier on a database with 55 individuals, which establishes the robustness of these measures to intra-personal distortions. Furthermore, we demonstrate that it is possible to improve upon these results significantly by simple means such as feature set combination and statistical resampling methods like bagging and random subspace method (RSM) using the same PCA-type base classifier. This even succeeds in attaining perfect classification results with 100% accuracy in some cases. Moreover, both these methods require few additional resources (computing time and power), hence they are useful for practical applications as well and help establish the effectiveness of frequency domain representation of facial asymmetry in automatic identification tasks
13253511
Verifying Average Dwell Time by Solving Optimization Problems
A switched system is a hybrid system whose discrete mechanisms are abstracted away in terms of an exogenous switching signal which brings about the mode switches. For switched systems, the Average Dwell time (ADT) property defines restricted classes of switching signals which can be used for proving stability. In this paper, we develop optimization-based methods for automatically verifying ADT properties of hybrid systems. This enables us to prove stability of hybrid systems, provided the individual modes of the system are stable. For two special classes of hybrid systems, we show that the resulting optimization problems can indeed be solved efficiently using standard mathematical programming techniques. We also present simulation relation-based proof methods for establishing equivalence of hybrid systems with respect to ADT. The proposed methods are applied to verify ADT properties of a linear hysteresis switch and a nondeterministic thermostat.
11380579
Bitmap indexes for large scientific data sets: a case study
The data used by today's scientific applications are often very high in dimensionality and staggering in size. These characteristics necessitate the use of a good multidimensional indexing strategy to provide efficient access to the data. Researchers have previously proposed the use of bitmap indexes for high-dimension scientific data as a way of overcoming the drawbacks of traditional multidimensional indexes such as R-trees and KD-trees, which are bulky and whose performance does not scale well as the number of dimensions increases. However, the techniques proposed in previous work on bitmap indexes are not sufficient to address all problems that arise in practice. In experiments with real datasets, we experienced problems with index size and query performance. To overcome these shortcomings, we propose the use of adaptive, multilevel, multi-resolution bitmap indexes, and evaluate their performance in two scientific domains. Our preliminary experiments with a parallel query processor and index creator also show that it is very easy to parallelize a bitmap index