8584813
Generation of alternative feature-based models and precedence orderings for machining applications
Incre=ing global competition is challenging the U.S. manufacturing industry to bring competitively-priced, well-designed and well-manufactured products to market in a timely fashion. Since decisions made during the design stage can have significant effects on product cost, quality, and lead time, increasing research attention is being given to integrating engineering design and manufacturing, with a focus on design for manufacturability. Consider the task of designing and manufacturing machined parts. Often there can be several different ways to machine a part. Which way is best depends on several factors, including dimensions, tolerances, surface finishes, availability of machine tools and cutting tools, fixturability, and optimization criteria. Thus, to evaluate the manufacturability of the proposed design, we may need to consider more than one way to machine it. This paper outlines our approach for generating and evaluating alternative ways to machine a part. For additional details, see [1]; for other related work, see [2, 3].
14208903
A Survey of Shape Similarity Assessment Algorithms for Product Design and Manufacturing Applications
Shape similarity assessment is a fundamental geometric reasoning problem that finds application in several different product design and manufacturing applications. A computationally efficient way to assess shape similarity is to first abstract 3D object shapes into shape signatures and use shape signatures to perform similarity assessment. Several different types of shape signatures have been developed in the past. This paper provides a survey of existing algorithms for computing and comparing shape signatures. Our survey consists of a description of the desired properties of shape signatures, a scheme for classifying different types of shape signatures, and descriptions of representative algorithms for computing and comparing shape signatures. This survey concludes by identifying directions for future research. 1 Corresponding Author
7211906
Manufacturing feature instances: which ones to recognize?
Manufacturing features and feature-based representations have become an integral part of research on manufacturing systems, largely due to their ability to model correspondences between design information and manufacturing operations. However, several research challenges still must be addressed in order to place feature technologies into a solid scientific and mathematical framework. One challenge is the issue of alternatives in feature-based planning. Even after one has decided upon an abstract set of features to use for representing manufacturing operations, the set of feature instances used to represent a part is by no means unique. For a complex part, many (sometimes infinitely many) different manufacturing operations can potentially be used to manufacture various portions of the part. Some of these feature instances will appear in useful manufacturing plans, and others will not. In order to reduce the number of alternative manufacturing plans that must be examined, we require a systematic means of specifying which feature instances are of interest. This paper addresses the issue of alternatives by introducing the notion of primary feature instances, which we contend are sufficient to generate all manufacturing plans of interest. To substantiate our argument, we describe how various instances in the primary feature set can be used to produce the desired plans. Furthermore, we discuss how this formulation overcomes computational difficulties faced by previous work, and present some complexity results for this approach in the domain of machined parts. “Also with: Nationaf Institute of Standards and Technology, Manufacturing Systems Integration Division Building 220, Room A-127, Gaithersburg, MD 20899. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advanta$e, the ACM copyright notice and the title of the publication and Its date appear, and notice is given that copying is by permission of the Association of Computing Machinery.To copy otherwise, or to republish, requires a fee and/or specific permission. Solid Modeling ’95, Salt Lake City, Utah USA
8985111
AI Planning Versus Manufacturing-Operation Planning: A Case Study
Although AI planning techniques can potentially be useful in several manufacturing domains, this potential remains largely unrealized. In order to adapt AI planning techniques to manufacturing, it is important to develop more realistic and robust ways to address issues important to manufacturing engineers. Furthermore, by investigating such issues, AI researchers may he able to discover principles that are relevant for AI planning in general. As an example, in this paper we describe the techniques for manufacturing-operation planning used in IMACS (Interactive Manufacturability Analysis and Critiquing System), and compare and contrast them with the techniques used in classical AI planning systems. We describe how one of IMACS's planning techniques may be useful for AI planning in general--and as an example, we describe how it helps to explain a puzzling complexity result in AI planning.
5689615
Generating sacrificial multi-piece molds using accessibility driven spatial partitioning
This paper describes an algorithm based on accessibility-driven partitioning approach to automate the design of sacrificial multi-piece molds. Sacrificial multi-piece molds are used for producing geometrically complex gelcast ceramic parts. The algorithm presented in this paper analyzes the accessibility of the gross mold shape and partitions using accessibility information. Each partitioning step improves accessibility of decomposed mold pieces. By performing successive decomposition, this algorithm finally produces a set of mold components that are accessible and therefore can be manufactured using milling and drilling operations. Using the algorithm presented in this paper, mold design steps can be significantly automated for making geometrically complex parts and facilitating the creation of physical part from the CAD model in a matter of hours.
2930416
Towards multiprocessor feature recognition
Abstract The availability of low-cost computational power is enabling the development of increasingly sophisticated cad software. Automation of design and manufacturing activities poses many difficult computational problems—significant among them is how to develop interactive systems that enable designers to explore and experiment with alternative ideas. As more downstream manufacturing activities are considered during the design phase, computational costs become problematic. Creating working software-based solutions requires a sophisticated allocation of computational resources in order to perform realistic design analyses and generate feedback. This paper presents our initial efforts to employ multiprocessor algorithms to recognize machining features from solid models of parts with large numbers of features and many geometric and topological entities. Our goal is to outline how improvements in computation time can be obtained by migrating existing software tools to multiprocessor architectures. An implementation of our approach is discussed.
45533435
BIST TPG for combinational cluster (glue logic) interconnect testing at board level
Due to the expense and complexity of boundary scan architecture (BSA) circuitry, non-boundary scan ICs (cluster ICs) are still used in modern circuit boards. A novel BIST architecture and a TPG design methodology to program this architecture are presented for testing inter-IC interconnects among combinational cluster ICs via IEEE 1149.1 BSA at board level. The two main issues that are tackled are: (1) safe testing, i.e., avoidance of conflicts at all multi-driver nets; and (2) obtaining complete coverage of all detectable faults in the interconnect. We have proposed a realistic model of interconnects that contain combinational cluster ICs, identified test requirements that must be satisfied by the TPG to achieve the above objectives, and developed a new TPG architecture that satisfies these test requirements. We have theoretically proven that the proposed technique guarantees safe and comprehensive testing of cluster interconnects and also demonstrated this fact via its applications to a few example circuits.
18759063
The Software Concordance: using a uniform document model to integrate program analysis and hypermedia
Since the source code is only one of many types of documents that must be maintained as a software system evolves, modern software development could be improved by better interoperability between source code and other software documents. The Software Concordance is a prototype programming environment that uses hypermedia services and a uniform document model to achieve this interoperability. The Software Concordance editor allows developers to enhance their inline documentation with multimedia objects and hyperlinks, while still supporting advanced program analysis including lexing, parsing and type checking. We motivate the need for environments like the Software Concordance, describe the design and implementation of its program editor, and discuss lessons learned while creating it. The system is based on a uniform, Web compatible document model for both program source code and nonprogram software documents and a corresponding API. Important technical problems addressed by this research include creating a persistent representation of program lexemes that the analysis suite considers to be ephemeral (such as keywords), providing a simple incremental parsing system, and embedding multimedia in source code without disrupting program analysis. Based on insight gained in the process of implementing the document API, a new approach to the design of a more suitable program analysis infrastructure is suggested.
5347587
Process aggravated noise (PAN): new validation and test problems
How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.
1246119
Interface synthesis using memory mapping for an FPGA platform
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.
1313286
ATPG for heat dissipation minimization during test application
A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application. The objective is to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds. Three new functions, namely transition controllability, observability and test generation costs, have been defined. It has been shown that the transition test generation cost is the minimum number of transitions required to test the corresponding stuck-at fault in fanout free circuits. This cost function is used for target fault selection while the other two functions are used to guide the backtrace and objective selection procedures of PODEM. The tests generated by the proposed ATPG decrease heat dissipation during test application by a factor of 2-23 for benchmark circuits.