11414897
Trace-based analysis and tuning for distributed parallel applications
We present an integrated approach to deal with timestamp consistency, and trace based performance analysis techniques for distributed parallel applications. Our trace generation facility captures message passing and system events such as process dispatch with minimal trace overhead. Trace driven analysis tools are developed for post execution analysis, reporting information such as the time stolen by other processes in each node, and the observed message passing time and local wait time for each message. We then present our techniques to reduce total elapsed times based on observed message passing times and local wait times.
7845091
A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities
The architecture, design, and performance of a hybrid number system processor are described. The processor performs multiplication, division, square root, and square in the logarithmic number system (LNS) domain. However, the input, output, addition, and subtraction are all executed in the 32-b IEEE standard floating-point number system. With the LNS multiplier and pipelined architecture, the processor is able to perform the geometric and complex arithmetic very effectively. The processor is also shown to compare well to an existing 32-b floating-point DSP (digital signal processor) chip. For the same level of CMOS technology, the performance ratios between the hybrid number system and the floating-point processor are shown to be 6.4:1 and 8:1 for division and square root, respectively; for the complex FFT (fast Fourier transform) algorithm, the ratio is around 2:1. >
14149213
Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches
We propose efficient stack simulation algorithms for shared memory multiprocessor (MP) caches. A stack simulation algorithm for write-updated MP caches is first presented. It produces the number of write-updates as well as misses for all cache configurations in a single run. We then devise a new stack simulation algorithm for writeinvalidate MP caches. Our algorithm takes into account cross-invalidation among processors, and generates the number of invalidations as well as misses for all cache configurations in a single run. A cache simulator based on our algorithms for MP caches is developed and the results on sample traces are reported. Our results show that effi cient stack simulation is a powerful technique for multi processor cache analysis.
11513370
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. The authors classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), their classification results in four combinations or cache types. The real address caches with virtual tags for high-performance computer systems in this study are prediction-based, since index bins are generated from a small array and predictions could be false. As a result, they also discuss and evaluate real address MRU caches with real tags, and propose virtually indexed MRU caches with real tags. Each of the four cache types and MRU caches are discussed and evaluated using trace-driven simulation. The results show that a virtually indexed MRU cache with real tags is a good choice for high-performance computer systems. >
463160
A Rule-Based Circuit Representation for Automated CMOS Design and Verification
A novel rule-based circuit representation is proposed to describe the connectivities of CMOS circuits at the transistor level. The unique feature of the rule-based representation is its ability to automate CMOS circuit design and verification. A precise symbolic description of the functionality of a transistor-level circuit can be derived based on a set of production rules in linear time. Automated synthesis and verification of CMOS logic circuits are demonstrated.
7629632
Speech content authentication integrated with CELP speech decoders
A speech content authentication scheme, which is integrated with CELP speech coders to minimize the total computational cost is proposed in this research. Speech features relevant to semantic meaning are extracted, encrypted and attached as the header information. A low cost synchronization algorithm is used to resolve mis-synchronization caused by content preserving operations. Silent and tonal regions in the speech are identified with algorithms of low complexity to enhance the precision of integrity verification. This scheme is not only much faster than traditional cryptographic bitstream integrity algorithms, but also more compatible for a variety of applications. Experimental results are collected by using the GSM-AMR speech coder, and statistical analysis is performed to calculate the false positive rate of tamper detection.
6331913
Speech content integrity verification integrated with ITU G.723.1 speech coding
A speech content integrity verification scheme integrated with ITU G.723.1 speech coding to minimize the total computational cost is proposed in this research. Speech features relevant to the semantic meaning are extracted, encrypted and attached as the header information. This scheme is not only much faster than cryptographic bitstream integrity algorithms, but also more compatible with a variable of applications. The speech signal could go through recompression, amplification, transcoding, re-sampling, D/A and A/D conversion and minor white noise pollution without triggering the verification alarm.
29409365
A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems
The problem of distributed garbage collection is discussed. An algorithm for parallel distributed asynchronous garbage collection is presented. The liveness and safety properties of this method are demonstrated. The algorithm does not require a global clock, complex termination detection methods, or distributed synchronization techniques. A new color code is introduced to distinguish between local cells (black) and those that are exclusively accessible from the remote pointers (gray). The mutator operation is revised to handle a multiple mutator scheme on a given local memory. Simulation results show that the developed distributed and parallel algorithm performs much better than the sequential method as tested on a Balance 8000 computer. >
27793990
Fail Safe Distributed Fault Diagnosis of Multiprocessor Systems
15660415
On-the-fly sharing for streamed aggregation
Data streaming systems are becoming essential for monitoring applications such as financial analysis and network intrusion detection. These systems often have to process many similar but different queries over common data. Since executing each query separately can lead to significant scalability and performance problems, it is vital to share resources by exploiting similarities in the queries. In this paper we present ways to efficiently share streaming aggregate queries with differing periodic windows and arbitrary selection predicates. A major contribution is our sharing technique that does not require any up-front multiple query optimization. This is a significant departure from existing techniques that rely on complex static analyses of fixed query workloads. Our approach is particularly vital in streaming systems where queries can join and leave the system at any point. We present a detailed performance study that evaluates our strategies with an implementation and real data. In these experiments, our approach gives us as much as an order of magnitude performance improvement over the state of the art.