1671645
Domino logic synthesis minimizing crosstalk
Based on the new concept of crosstalk immunity set (CIS), procedures to minimize capacitive cross-coupling effects are developed for domino logic circuit. The nets in a crosstalk immunity set are free from crosstalk effects for any combination of input vectors. New algorithms for CIS identification and minimization are proposed to maximize the chance of crosstalk minimization in routing step. Our routing algorithm augmented with CIS information searches for optimal solution to minimize maximum crosstalk the circuit would experience. Experimental results show that the reduction of maximum crosstalk is up to 30% with CIS-augmented routing.
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
24075467
Analytic transient solution of general MOS circuit primitives
The exact analytic transient solution is presented for a general MOS circuit primitive. In the circuit primitive, I-V characteristics of transistors are modeled by quadratic equations and node voltages by piecewise-linear waveforms. The proposed MOS circuit primitive, of which an inverter is a special case, is shown to be more suitable for switch level and fast timing simulations than the commonly used inverter. For circuit simulation of medium-size digital circuits containing a few hundred transistors, the application of this analytic solution has resulted in two to three orders of speed improvement over the conventional circuit simulator. The speed improvement factor is expected to grow with the circuit size. It is also shown that the exact transient solution of a macromodel which models the charge sharing can be obtained in the same way. >
36636082
An accurate analytical delay model for BiCMOS driver circuits
An analytical delay model for BiCMOS driver circuits is presented. The model is based on physical device parameters and can be used to estimate both the pull-up and the pull-down times for a variety of circuit configurations. The intrinsic delay associated with the bipolar transistors is taken into consideration by using a charge control model that incorporates the high-injection effects upon the current gain and the base transport factor. Separate sets of delay equations are derived for the pull-up and pull-down transient responses to account for significant differences between the two cases. The comparison with SPICE circuit simulation results shows that the new model predicts the respective delay times with less than 10% error in most cases. The influence of device dimensions upon the driver delay time is also investigated. The model has been applied to find an optimal area allocation between the CMOS and bipolar parts of the driver circuit when the total available area is limited as in the standard cell configuration. >
16084555
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop
This paper describes a radio architecture with fast analog frequency offset cancellation loop which is based on a SigmaDelta fractional-N frequency synthesizer and a frequency offset detector. The offset detector is composed of a frequency/phase detector (PFD) and a new non-uniform resolution time-to-digital converter (TDC). By adopting the weighted delay-length for the TDC, only 60-DFFs are used to generate digitized timing difference of 250ns with a minimum resolution of 1ns. For the 2.4GHz ZigBee transceiver with 4MHz IF, designed for 0.18mum CMOS process, the frequency offset cancellation time takes about 30mus under the PLL loop-bandwidth of 100 kHz
36602039
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic
We have developed Dual Path All-N-logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35 /spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N-transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35 /spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.
26233543
Appearance-Based Structure from Motion Using Linear Classes of 3-D Models
In this paper, we address the problem of recovering 3-D models from sequences of partly calibrated images with unknown correspondence. To that end, we integrate tracking, structure from motion with geometric constraints (specifically in the form of linear class models) in a single framework. The key to making the proposed approach work is the use of appearance-based model matching and refinement which updates the estimated correspondences on each iteration of the algorithm. Another key feature is the matching of a 3-D model directly with the input images without the conventional 2-step approach of stereo data recovery and 3-D model fitting. Initialization of the linear class model to one of the input images (the reference image) is currently partly manual.This synthesis and refine approach, or appearance-based constrained structure from motion (AbCSfm), is especially useful in recovering shapes of objects whose general structureis known but which may have little discernable texture in significant parts of their surfaces. We applied the proposed approach to 3-D face modeling from multiple images to create new 3-D faces for DECface, a synthetic talking head developed at Cambridge Research Laboratory, Digital Equipment Corporation. The DECface model comprises a collection of 3-D triangular and rectangular facets, with nodes as vertices. In recovering the DECface model, we assume that the sequence of images is taken with a camera with unknown focal length and pose. The geometric constraints used are of the form of linear combination of prototypes of 3-D faces of real people. Results of this approach show its good convergence properties and its robustness against cluttered backgrounds.
589178
Multi-Layered Image-Based Rendering
In this article, we describe a multi-layered image-based rendering system that can use different types of input to produce and render new environments. Each separate input that can be manipulated independently is called a layer. In our implementation, the types of layers that can be manipulated are the image-based and 3-D-based layers. The computation required for rendering the newlycrafted environment is reduced by using cached composite snapshots of that environment at reference poses. These cached snapshots are used to directly generate novel views, and the original layers are used only when necessary. Another key concept is the identification of types of holes generated as a result of pixel transfer from the composite snapshots to the generated view. For optimal rendering quality, the algorithm used in filling these holes is specific to the hole type (either intralayer or interlayer). The ideas embodied in our multi-layered IBR system are useful in augmenting the capabilities of applications that require fast and geometrically consistent rendering of 3-D scenes such as video editing.
32568915
Event Sentence Extraction in Korean Newspapers
Information extraction is to extract information about the main events in the text. This paper presents an event sentence extraction method in Korean newspapers for information extraction. Event sentences contain meaningful information such as the agent, the time and the place of an event. To extract these sentences, we acquire various features such as verbs, nouns, noun phrases, 3Ws, and their weights. And then, the system computes weights of sentences and extracts event sentences by our extraction algorithm. The experimental result shows the average precision of 86.1%.
40534720
A robot system that observes and replicates grasping tasks
To alleviate the problem of overwhelming complexity in grasp synthesis and path planning associated with robot task planning, we adopt the approach of teaching the robot by demonstrating in front of it. The system has four components: the observation system, the grasping task recognition module, the task translator and the robot system. The observation system comprises an active multibaseline stereo system and a dataglove. The data stream recorded is then used to track object motion; this paper illustrates how complimentary sensory data can be used for this purpose. The data stream is also interpreted by the grasping task recognition module, which produces higher levels of abstraction to describe both the motion and actions taken in the task. The resulting information are provided to the task translator which creates commands for the robot system to replicate the observed task. In this paper we describe how these components work with special emphasis on the observation system. The robot system that we use to perform the grasping tasks comprises the PUMA 560 arm and the Utah/MIT hand.<<ETX>>
11955356
Automatic Segmentation of Words using Syllable Bigram Statistics
We present a syllable bigram model for segmenting a Korean sentence into words and correcting word-spacing errors in the spelling checker. We evaluated the system’s performance for automatic word segmentation, word-spacing error detection, and the word-splitting problem of the character recognition system at the end of a line.