16023163
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance
In order to achieve high instruction level parallelism (ILP), designers are turning to very long instruction word (VLIW) based designs, in which different types of instructions are grouped together as bundles of 128 bits or longer. In VLIW, the added nops increase the code size, limit processor performance by the under-utilization of functional units. In examining these performance issues of VLIW systems, we consider Intel first 64-bit architecture, the IA-64, and its first implementation, the Itanium, which employs Intel version of VLIW. We present a comprehensive analysis of the problem of under-utilization due to nops and stops across a wide range of application domains through the use of three different benchmark suites: SPEC CPU 2000, MediaBench, and PacketBench. Our results show that, on average, nops create an under-utilization factor of 28.46% in the case of SPEC CPU, 32.27% in MediaBench, and 29.76% in PacketBench. We also analyze the characteristics of different instruction bundle formats, which we obtain by collecting statistics concerning the frequency of the bundle formats
14115714
Energy-efficient compressed address transmission
To realize energy-efficient buses in current nanometer-scale technologies, techniques like compression or encoding that exploit information redundancy have been explored. However, available compression techniques for buses do not always ensure energy-efficient transmission of compressed information. In this work, we present various techniques that can be used with compression schemes for buses to ensure high energy efficiency. Our best scheme, applied to a stream of 38-bit addresses issued in a typical microprocessor, yields about 14.7% energy reduction on the average across a wide range of compressed bus widths ranging and over many SPEC CPU2000 benchmarks. Our proposed techniques especially perform better - up to 28.8% energy reduction is obtained - for narrower bus widths in the range 8-16 bits.
52848704
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction
Interconnect area and energy dissipation are critical factors in any system designed today. In this work, we present techniques to help reduce area/cost and energy dissipation of address buses with significant temporal redundancy. We describe two encoding techniques for such buses, called pattern adjuster (PA) encoding and dynamic charge/discharge encoding (DCDE), that use simple hardware and no extra bus lines for control signals. Results show that, using PA encoding, self energy reduces by 18-38%, coupling toggle energy by 19-96%, and coupling charge/discharge energy by 14-40%. In addition, with DCDE applied on top of PA, coupling charge/discharge energy reduces by up to 48%. Overall, up to 25% address bus energy savings can be obtained using our techniques compared to the energy dissipation of the original bus, with 26-79% reduction in the number of bus lines. Our techniques use very simple hardware and will have negligible encoding/decoding latencies that are much lower than those of low-power bus encoding schemes.
43415133
The performance advantage of applying compression to the memory system
The memory system stores information comprising primarily instructions and data and secondarily address information, such as cache tag fields. It interacts with the processor by supporting related traffic (again comprising addresses, instructions, and data). Continuing exponential growth in processor performance, combined with technology, architecture, and application trends, place enormous demands on the memory system to permit this information storage and exchange at a high-enough performance (i.e., to provide low latency and high bandwidth access to large amounts of information). This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the memory system and evaluates the potential of compression in improving performance of the memory system. Analysis of traces obtained with Sun Microsystems' Shade simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite yield impressive results. Well-designed compression schemes may provide benefits in performance that far outweigh the extra time and logic for compression and decompression. This will be more so in the future since the speed and size of logic (which will be used to perform compression/decompression) are improving and are projected to improve at a much higher rate compared to those of interconnect (which will be used to communicate the information), both on-chip and off-chip.
17015441
Dynamic address compression schemes: a performance, energy, and cost study
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this work, we investigate two such schemes and determine their optimal parameters that result in the highest area/cost reductions and least performance penalty for various address buses (both on- and off-chip) in current systems. For addresses compressed with these schemes, we study energy reduction of buses in current and future nanometer technology nodes. Our study uses the cycle-accurate simulator for the Alpha 21264 processor called sim-alpha for performance estimation and accurate interconnect models considering inter-wire capacitances for bus energy estimation. Results show that using address compression results in only small performance overheads (less than 1% for compressing a 38-bit bus to 14 bits) and reduce bus energy dissipation by as much as 13% when applied to on-chip buses in current technologies.
29548669
From Individual Based Modeling to Autonomy Oriented Computation
In this chapter, we generalize autonomy oriented computation. We characterize the application-independent features of two main components of AOC systems, namely, entities and environment. We identify the self-organizating process of entities as the core of AOC systems. We also address the autonomy deployed in AOC systems and compare them with those in other work. Moreover, we use three typical examples, a natural system, a man-made system, and a computational system, to show how AOC is embodied and how AOC works in different cases.
4908568
Insignificant shadow detection for video segmentation
To prevent moving cast shadows from being misunderstood as part of moving objects in change detection based video segmentation, this paper proposes a novel approach to the cast shadow detection based on the edge and region information in multiple frames. First, an initial change detection mask containing moving objects and cast shadows is obtained. Then a Canny edge map is generated. After that, the shadow region is detected and removed through multiframe integration, edge matching, and region growing. Finally, a post processing procedure is used to eliminate noise and tune the boundaries of the objects. Our approach can be used for video segmentation in indoor environment. The experimental results demonstrate its good performance.
5754031
Group management for mobile Ad Hoc networks: design, implementation and experiment
Mobile ad hoc networks (MANET) offer a convenient basis toward realization of pervasive computing, due to its ease of deployment and inherent support for anytime, anywhere network access for mobile users. However, the development of applications over such networks is faced by the challenge of network dynamics attributed to node mobility and the scalability issue. Group management poses as a promising paradigm to ease the development of distributed applications for dynamic, mobile networks. Specifically, group management makes transparent the failures due to node mobility and assembles mobile nodes to meet target functional and non-functional properties. Various network-level grouping schemes over MANET have been investigated over the last couple of years. In this paper, we introduce the design and implementation of a generic group service for MANET, defined with respect to the various attributes of relevance. Generic group management is further demonstrated with its support of scalable service discovery in MANET.
15358098
Multi-agent oriented constraint satisfaction
This paper presents a multi-agent oriented method for solving CSPs (Constraint Satisfaction Problems). In this method, distributed agents represent variables and a two-dimensional grid-like environment in which the agents inhabit corresponds to the domains of the variables. Thus, the positions of the agents in such an environment constitute the solution to a CSP. In order to reach a solution state, the agents will rely on predefined local reactive behaviors; namely, better-move, least-move, and random-move. While presenting the formalisms and algorithm, we will analyze the correctness and complexity of the algorithm, and demonstrate the proposed method with two benchmark CSPs, i.e., n-queen problems and coloring problems. In order to further determine the effectiveness of different reactive behaviors, we will examine the performance of this method in deriving solutions based on behavior prioritization and different selection probabilities.
5135154
Linking UML models of design and requirement
Both a UML model of requirement and a UML model of a design are defined as a pair of class diagram and a family of sequence diagrams. We then give an unified semantics for models of requirements and designs. We define the consistency between a design class diagram and the interaction diagrams and show how the removal of inconsistency can be treated as a model refinement. We then formally define the correctness of UML model of design with respect to the model of requirement.