3890410
Strongly Connected Spanning Subdigraphs with the Minimum Number of Arcs in Quasi-transitive Digraphs
We consider the problem of finding a strongly connected spanning subdigraph with the minimum number of arcs in a strongly connected digraph. This problem is NP-hard for general digraphs since it generalizes the Hamiltonian cycle problem. We show that the problem is polynomially solvable for quasi-transitive digraphs. We describe the minimum number of arcs in such a spanning subdigraph of a quasi-transitive digraph in terms of the path covering number. Our proofs are based on a number of results (some of which are new and interesting in their own right) on the structure of cycles and paths in quasi-transitive digraphs and in extended semicomplete digraphs. In particular, we give a new characterization of the longest cycle in an extended semicomplete digraph. Finally, we point out that our proofs imply that the MSSS problem is solvable in polynomial time for all digraphs that can be obtained from strong semicomplete digraphs on at least two vertices by replacing each vertex with a digraph belonging to a family of digraphs whose path covering number can be decided in polynomial time.
10979198
Weakly Hamiltonian-connected ordinary multipartite tournaments
Abstract We characterize weakly Hamiltonian-connected ordinary multipartite tournaments. Our result generalizes such a characterization for tournaments by Thomassen and implies a polynomial algorithm to decide the existence of a Hamiltonian path connecting two given vertices in an ordinary multipartite tournament and finds one, if it exists.
43442956
Representation characterizations of chordal bipartite graphs
A bipartite graph is chordal bipartite if it does not contain an induced cycle of length at least six. We give three representation characterizations of chordal bipartite graphs. More precisely, we show that a bipartite graph is chordal bipartite if and only if the complement is the intersection graph of a family of pairwise compatible claws in a weighted hypercircle. (A hypercircle is a graph which consists of internally vertex disjoint paths between two distinguished vertices, and a claw in a hypercircle is a connected subgraph containing exactly one of the two distinguished vertices.) We also introduce two classes of bipartite graphs, both containing interval bigraphs and interval containment bigraphs. They are compatible subtree intersection bigraphs and compatible subtree containment bigraphs. We show that these two classes are identical to the class of chordal bipartite graphs.
31025959
A Note on Spanning Local Tournaments in Locally Semicomplete Digraphs
We prove a result which implies that every k-connected locally semicomplete digraph which is not a semicomplete digraph must contain a k-connected spanning local tournament. This improves an earlier result of Guo and partially answers a question of Jackson and Thomassen.
4333882
Linear-Time Representation Algorithms for Proper Circular-Arc Graphs and Proper Interval Graphs
Our main result is a linear-time (that is, time $O(m+n)$) algorithm to recognize and represent proper circular-arc graphs. The best previous algorithm, due to A. Tucker, has time complexity $O(n^2)$. We take advantage of the fact that (among connected graphs) proper circular-arc graphs are precisely the graphs orientable as local tournaments, and we use a new characterization of local tournaments. The algorithm depends on repeated representation of portions of the input graph as proper interval graphs. Thus we also find it useful to give a new linear-time algorithm to represent proper interval graphs. This latter algorithm also depends on an orientation characterization of proper interval graphs. It is conceptually simple and does not use complex data structures. As a byproduct of the correctness proof of the algorithm, we also obtain a new proof of a characterization of proper interval graphs by forbidden subgraphs.
4789976
In-Tournament Digraphs
Abstract In this paper we introduce a generalization of digraphs that are locally tournaments (and hence of tournaments). This is the class of in-tournament digraphs-the set of predecessors of every vertex induces a tournament. We show that many properties of local tournament digraphs can be extended even to in-tournament digraphs. For instance, any strongly connected in-tournament digraph has a directed hamiltonian cycle. We prove that the underlying graph of any in-tournament digraph is l-homotopic. We investigate the problem of which graphs are orientable as in-tournament digraphs and prove that any graph representable as an intersection subgraph of a unicyclic graph can be so oriented. It is shown that there is a polynomial algorithm for recognizing those graphs that can be oriented as in-tournament digraphs.
1720329
Toward Inductive Logic Programming for Collaborative Problem Solving
In this paper, we tackle learning in distributed systems and the fact that learning does not necessarily involve the participation of agents directly in the inductive process itself. Instead, many systems frequently employ multiple instances of induction separately. The paper's main contribution is a new approach that tightly integrates processes of induction between distributed agents, based on inductive logic programming techniques, for a wider class of problem solving tasks. The approach combines inverse entailment with an epistemic approach to reasoning about knowledge, facilitating a systematic approach to the sharing of knowledge and invention of predicates only when required. We illustrate the approach for learning declarative program fragments and for a well-known path planning problem and compare results empirically to (multiple instances of) single agent-based induction over varying distributions of data. Given a chosen path planning algorithm, our algorithm enables agents to combine their local knowledge in an effective way to avoid central control while significantly reducing communication costs.
27000200
An on-chip short-time interval measurement technique for testing high-speed communication links
In this paper, we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specifications, e.g., the rise/fall time of modern high-speed communication transceivers. To reduce hardware overhead, the proposed BIST technique uses the coherent under-sampling principle, and measures implicitly the time interval in a two-pass manner. Simulation results are shown to validate the proposed technique.
16721854
Learning from labeled and unlabeled data on a directed graph
We propose a general framework for learning from labeled and unlabeled data on a directed graph in which the structure of the graph including the directionality of the edges is considered. The time complexity of the algorithm derived from this framework is nearly linear due to recently developed numerical techniques. In the absence of labeled instances, this framework can be utilized as a spectral clustering method for directed graphs, which generalizes the spectral clustering approach for undirected graphs. We have applied our framework to real-world web classification problems and obtained encouraging results.
17903854
The Superthreaded Processor Architecture
The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism that are available in general-purpose application programs. Unlike other CMAs that rely primarily on hardware for run-time dependence detection and speculation, the superthreaded processor combines compiler-directed thread-level speculation of control and data dependences with run-time data dependence verification hardware. This hybrid of a superscalar processor and a multiprocessor-on-a-chip can utilize many of the existing compiler techniques used in traditional parallelizing compilers developed for multiprocessors. Additional unique compiler techniques, such as the conversion of data speculation into control speculation, are also introduced to generate the superthreaded code and to enhance the parallelism between threads. A detailed execution-driven simulator is used to evaluate the performance potential of this new architecture. It is found that a superthreaded processor can achieve good performance on complex application programs through this close coupling of compile-time and run-time information.
3242205
OmniSeer: A Cognitive Framework for User Modeling, Reuse of Prior and Tacit Knowledge, and Collaborative Knowledge Services
This paper describes the current state of the OmniSeer system. OmniSeer supports intelligence analysts in the handling of massive amounts of data, the construction of scenarios, and the management of hypotheses. OmniSeer models analysts with dynamic user models that capture an analyst's context, interests, and preferences, thus enabling more efficient and effective information retrieval. OmniSeer explicitly represents the prior and tacit knowledge of analysts, thus enabling transfer and reuse of such knowledge. Both the user and cognitive models employ a Bayesian network fragment representation, which supports principled probabilistic reasoning and analysis. An independent evaluation of OmniSeer was carried out at NIST and will be used to guide further development.