14750422
Reducing power with performance constraints for parallel sparse applications
Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computation-to-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties.
15399936
Compiler-guided leakage optimization for banked scratch-pad memories
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
1780811
Reducing code size through address register assignment
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.
25434953
A data-centric approach to checksum reuse for array-intensive applications
Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive components. While many systems implement hardware-based protection techniques like ECC and other approaches to ensure an acceptable level of robustness against these errors, such solutions are generally very rigid and costly. Recent research discussed checksum-based software solutions that can be used in the context of array-intensive computations. While a checksum-based scheme can be more flexible than a hardware-based approach to reliability, it can also bring significant runtime overheads. Focusing on array-intensive applications, this paper proposes a compiler-directed data-centric strategy that maximizes reuse of checksums. A unique characteristic of the proposed scheme is that it can work with a given checksum assignment, and automatically - under compiler guidance - restructures the entire application code to maximize checksum reuse. This scheme can reduce checksum recomputing even further by inter-procedural checksum reuse. Our experiments clearly show that the proposed approach reduces the number of checksum calculations required by the previous work.
2974807
Address Register Assignment for Reducing Code Size
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55&percnt). This work presents a compiler-based optimization strategy to reduce the code size in embedded systems. Our strategy maximizes the use of indirect addressing modes with post-increment and post-decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring).
2166475
Temperature-sensitive loop parallelization for chip multiprocessors
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9/spl deg/C (4.3/spl deg/C) when averaged over all the applications tested, incurring small performance/power penalties.
207117262
Using Memory Compression for Energy Reduction in an Embedded Java System
The Java programming language is being increasingly used for application development for mobile and embedded devices. Limited energy and memory resources are important constraints for such systems. Compression is an useful and widely employed mechanism to reduce the memory requirements of the system. As the leakage energy of a memory system increases with its size and because of the increasing contribution of leakage to overall system energy, compression also has a significant effect on reducing energy consumption. However, storing compressed data/instructions has a performance and energy overhead associated with decompression at runtime. The underlying compression algorithm, the corresponding implementation of the decompression and the ability to reuse decompressed information critically impact this overhead. In this paper, we explore the influence of compression on overall memory energy using a commercial embedded Java virtual machine (JVM) and a customized compression algorithm. Our results show that compression is effective in reducing energy even when considering the runtime decompression overheads for most applications. Further, we show a mechanism that selectively compresses portions of the memory to enhance energy savings. Finally, a scheme for clustering the code and data to improve the reuse of the decompressed data is presented.
8895078
An Adaptive-Filtering Policy for Distributed Virtual Environments
In this paper, an adaptive-filtering policy for distributed virtual environments (DVEs) was brought forward. It took advantages of two traditional filtering policies (static-filtering policy and equidistance-transmission policy) and could adaptively select the fittest filtering policy corresponding to current motion characteristic of the virtual object in DVEs. An experiment was designed to compare this filtering policy with the two traditional filtering policies on task performance. Objective (task completion time, state updates transmitted and state updates per second) and subjective (filtering quality) evaluations were recorded in the experiment. The experiment results show that if mean state updates per second is equal or greater than 20 in the task, SUT and SUPS can be decreased by adaptive-filtering policy without task performance affected obviously. However, if mean state updates per second is around 10 in the task, accompanied with SUT and SUPS decreased by adaptive-filtering policy, task performance also deteriorated badly
30915392
An HCI method to improve the human performance reduced by local-lag mechanism
Local-lag mechanism can maintain consistency for replicated continuous applications, but with a tradeoff of adding delay to local operations. To relieve the negative effects of the delay, this paper proposes an HCI method named echo. With the help of the echo method users can immediately perceive the results of their operations and how large the lag is. In order to evaluate the proposed method, a desktop collaborative virtual environment (CVE) system and a virtual object control task were employed to study the effects of the echo method on human performance (including task completion time, error count, and interaction quality). Experimental results indicate that when the lag exceeds 100ms the echo method can improve human performance with the effects becoming more evident when a larger lag is used.
8564003
Ramsey Problems Involving Degrees in Edge-colored Complete Graphs of Vertices Belonging to Monochromatic Subgraphs
We consider monochromatic subragraphs in two-colored graphs as guaranteed by Ramsey's theorem, and ask various questions concerning the degree in the two-colored complete graphs of vertices which are part of these subgraphs.
24161285
Effects of Local-Lag Mechanism on Task Performance in a Desktop CVE System
Consistency maintenance is a kernel problem in Collaborative Virtual Environment (CVE) research. The approaches used in Networked Virtual Environments (e.g., DR algorithm) could not be used in CVEs, for they could not prevent short-term inconsistency. Therefore, local-lag mechanism has been proposed to eliminate short-term inconsistency in CVEs. Choosing a proper lag value is a key problem in local-lag mechanism. This paper studied the effects of lag value (0ms–900ms) on task performance in a desktop CVE system. Experimental results indicate that the effect of lag value on task performance is not linear. The effect could be separated into four segments by three dividing points: 150ms, 300ms and 600ms. Lag has no effect on task performance while ranging from 0ms to 150ms. From 150ms to 300ms, lag slightly affects task performance. Lag deteriorates task performance seriously while ranging from 300ms to 600ms. When lag is longer than 600ms, the task cannot be accomplished sometimes.