1488910
Modeling interconnect variability using efficient parametric model order reduction
Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computational cost and model complexity. In this paper we present an efficient yet accurate parametric model order reduction algorithm for addressing the variability of IC interconnect performance. The efficiency of the approach lies in a novel combination of low-rank matrix approximation and multi-parameter moment matching. The complexity of the proposed parametric model order reduction is as low as that of a standard Krylov subspace method when applied to a nominal system. Under the projection-based framework, our algorithm also preserves the passivity of the resulting parametric models.
605614
Noise macromodel for radio frequency integrated circuits
Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some model of the noise is represented at the highest levels of abstraction during the design process. In this paper we propose a noise macromodel for analog circuits and demonstrate it by way of implementation in a system level simulator based on MATLAB. We also explain our process of macromodel extraction via reformulation of frequency-domain noise analysis results, and the corresponding steps of model order reduction. The results demonstrate the efficacy of this macromodel for frequency domain system level simulation.
13285231
Analog and RF circuit macromodels for system-level analysis
Design and validation of mixed-signal integrated systems require system-level model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF component macromodels, but their complexity can sometimes limit their utility for time-varying systems and large circuits with complex device models or numerous parasitics. In this paper we propose simple and efficient analog and RF circuit macromodels that provide accurate model abstractions for large, complex time-varying circuits over frequency bands of interest. By starting with the system-level block diagram model structures and focusing on the narrow RF bands, the proposed macromodels can efficiently capture the nonlinear behavior as well as the impact of RLC coupling parasitics via compact reduced-order model forms. While the macromodel can trade accuracy for simplicity in terms of the number of frequency expansion points, we find that expansion about one frequency point provides the accuracy required for system-level analysis of most RF and narrow-band analog components. The macromodel form corresponds to block diagram structures that are easily incorporated into our system-level simulation tool based on Simulink.
2872365
A frequency relaxation approach for analog/RF system-level simulation
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and simulation approaches have been successfully applied for such purposes (e.g. Simulink); however, analog circuits are often best analyzed in the frequency domain. Circuit-level analyses, such as harmonic balance, have been successfully extended to the frequency domain [2], but these algorithms are impractical for simulating large systems with wide-band input and noise signals. In this paper we proposed a frequency-domain approach for analog/RF system-level simulation that is capable of capturing various second order effects (e.g. nonlinearity, noise, etc.) for both time-invariant and time-varying systems with wide-band inputs. The simulator directly evaluates the frequency domain response at each node via a relaxation scheme that is proven to be convergent under typical circuit conditions. Our experimental results demonstrate the accuracy and efficiency of the proposed simulator under various wide-band input and noise excitations.
2303584
Constructing high assurance asynchronous real-time distributed systems: a proof-based system engineering approach
Asynchronous real-time distributed systems raise fundamental issues of how to build timely systems that operate in the presence of uncertain timeliness, and furthermore, how to certify that such systems will deliver properties including timeliness and safety. In this paper, we discuss an approach for constructing certifiable asynchronous real-time distributed systems.
42771841
Passive velocity field control of mechanical manipulators
Two concepts for the task specification and control for mechanical manipulators are advocated: the coding of tasks in terms of velocity fields; and controllers that maintain the passivity relationship between the manipulator and its physical environment. A passive velocity field tracking controller is proposed. The proposed dynamic controller mimics a flywheel: it stores and releases energy to the manipulator, but does not generate any. The controller has the interesting property that it stabilizes any multiple (positive or negative) of the desired velocity field, and exponentially stabilizes the particular multiple which is related to the total kinetic energy of the manipulator+controller.
51883995
Energy-efficient, utility accrual scheduling under resource constraints for mobile embedded systems
We present an energy-efficient real-time scheduling algorithm called the Resource-constrained Energy-Efficient Utility Accrual Algorithm (or ReUA). ReUA considers an application model where activities are subject to time/utility function-time constraints, resource dependencies including mutual exclusion constraints, and statistical performance requirements including probabilistically satisfied, activity (timeliness) utility bounds. Further, ReUA targets mobile embedded systems where system-level energy consumption is a major concern. For such a model, we consider the scheduling objectives of (1) satisfying statistical performance requirements, and (2) maximizing system-level energy efficiency, while respecting resource dependencies. Since the problem is NP-hard, ReUA allocates resources using statistical properties of application cycle demands and heuristically computes schedules with a polynomial-time cost. We analytically establish several timeliness and non-timeliness properties of the algorithm. Further, our simulation experiments illustrate ReUA's effectiveness.
14905620
Unscented Kalman filter for visual curve tracking
Abstract Visual contour tracking in complex background is a difficult task. The measurement model is often nonlinear due to clutter in images. Traditional visual trackers based on Kalman filters employ simple linear measurement models, and often collapse during the tracking process. This paper presents a new contour tracker based on unscented Kalman filter that is superior to extended Kalman filter both in theory and in many practical situations. The new tracker employs a more accurate nonlinear measurement model, without computation of a Jacobian matrix. During each time step, the tracker makes multiple measurements in terms of the set of appropriately chosen sample points, thus obtaining the best observation according to the measurement density. The resulting algorithm is able to obtain a more exact estimate of the state of the system, while having the same order of complexity as that of an extend Kalman Filter. The experiments show that the new algorithm is superior to those based on Kalman filters.
10769697
Advanced control flow in Java card programming
Java Card technology simplifies the development of smart card applications by providing a high-level programming language similar to Java. However, the master-slave programming model used in current Java Card platform creates control flow difficulties when writing complex card programs, making it inconvenient, tedious, and error-prone to implement Java Card applications. This paper examines these drawbacks of the master-slave model and proposes a concurrent thread model for developing future Java Card programs, which is much closer to conventional Java network programming. This paper also presents a code translation algorithm and a corresponding tool that makes it possible to write card programs in the concurrent thread model without losing compatibility with the existing Java Card API.