980425
Stack-Based Typed Assembly Language
In previous work, we presented a Typed Assembly Language (TAL). TAL is sufficiently expressive to serve as a target language for compilers of high-level languages such as ML. This work assumed such a compiler would perform a continuation-passing style transform and eliminate the control stack by heap-allocating activation records. However, most compilers are based on stack allocation. This paper presents STAL, an extension of TAL with stack constructs and stack types to support the stack allocation style. We show that STAL is sufficiently expressive to support languages such as Java, Pascal, and ML; constructs such as exceptions and displays; and optimizations such as tail call elimination and callee-saves registers. This paper also formalizes the typing connection between CPS-based compilation and stack-based compilation and illustrates how STAL can formally model calling conventions by specifying them as formal translations of source function types to STAL types.
10548039
Typed memory management via static capabilities
Region-based memory management is an alternative to standard tracing garbage collection that makes operation such as memory deallocation explicit but verifiably safe. In this article, we present a new compiler intermediate language, called the Capability Language (CL), that supports region-based memory management and enjoys a provably safe type systems. Unlike previous region-based type system, region lifetimes need not be lexically scoped, and yet the language may be checked for safety without complex analyses. Therefore, our type system may be deployed in settings such as extensible operating systems where both the performance and safety of untrusted code is important. The central novelty of the language is the use of static capabilities to specify the permissibility of various operations, such as memory access and deallocation. In order to ensure capabilities are relinquished properly, the type system tracks aliasing information using a form of bounded quantification. Moreover, unlike previous work on region-based type systems, the proof of soundness of our type system is relatively simple, employing only standard syntactic techniques. In order to show how our language may be used in practice, we show how to translate a variant of Tofte and Talpin's high-level type-and-effects system for region-based memory management into our language. When combined with known region inference algorithms, this translation provides a way to compile source-level languages to CL.
283023
Typed memory management in a calculus of capabilities
An increasing number of systems rely on programming language technology to ensure safety and security of low-level code. Unfortunately, these systems typically rely on a complex, trusted garbage collector. Region-based type systems provide an alternative to garbage collection by making memory management explicit but verifiably safe. However, it has not been clear how to use regions in low-level, type-safe code.We present a compiler intermediate language, called the Capability Calculus, that supports region-based memory management, enjoys a provably safe type system, and is straightforward to compile to a typed assembly language. Source languages may be compiled to our language using known region inference algorithms. Furthermore, region lifetimes need not be lexically scoped in our language, yet the language may be checked for safety without complex analyses. Finally, our soundness proof is relatively simple, employing only standard techniques.The central novelty is the use of static capabilities to specify the permissibility of various operations, such as memory access and deallocation. In order to ensure capabilities are relinquished properly, the type system tracks aliasing information using a form of bounded quantification.
14655625
A type system for expressive security policies
Certified code is a general mechanism for enforcing security properties. In this paradigm, untrusted mobile code carries annotations that allow a host to verify its trustworthiness. Before running the agent, the host checks the annotations and proves that they imply the host's security policy. Despite the flexibility of this scheme, so far, compilers that generate certified code have focused on simple type safety properties rather than more general security properties.
Security automata can specify an expressive collection of security policies including access control and resource bounds. In this paper, we describe how to instrument well-typed programs with security checks and typing annotations. The resulting programs obey the policies specified by security automata and can be mechanically checked for safety. This work provides a foundation for the process of automatically generating certified code for expressive security policies.
215896794
From system F to typed assembly language
We motivate the design of typed assembly language (TAL) and present a type-preserving ttranslation from Systemn F to TAL. The typed assembly language we pressent is based on a conventional RISC ass...
195349403
Stack-based typed assembly language
17178263
Accurate fault modeling and fault simulation of resistive bridges
This paper presents accurate fault models, an accurate fault simulation technique, and a new fault coverage metric for resistive bridging faults in gate level combinational circuits at nominal and reduced power supply voltages. We show that some faults have unusual behavior, which has been observed in practice. On the ISCAS85 benchmark circuits we show that a zeroohm bridge fault model can be quite optimistic in terms of coverage of voltage-testable bridging faults.
21446187
Is IDDQ Test of Microprocessors Feasible?
Quiescent leakage current (Iddq) test has proven very effective for detecting defects that escape other test methods, such as small delay faults or reliability hazards. However, leakage currents in microprocessors, digital signal processors, and graphics processors have risen to the point that these products no longer use Iddq test. Quality must be achieved through other test methods, often at higher development and application cost. We propose to bring Iddq  test back to high performance chips by using a practical built-in current sensor (BICS). 180 nm test chip results show that a small sensor can achieve a resolution of 54 muA, which is adequate to detect most small delay defects and reliability hazards
15554842
Resistive bridge fault modeling, simulation and test generation
In this work/sup 1/ we develop models of resistive bridging faults and study the fault coverage on ISCAS85 circuits of different test sets using resistive and zero-ohm bridges at different supply voltages. These results explain several previously observed anomalous behaviors. In order to serve as a reference, we have developed the first resistive bridging fault ATPG, which attempts to detect the maximum possible bridging resistance at each fault site. We compare the results of the ATPG to the coverage obtained from other test sets, and coverage obtained by using the ATPG in a clean-up mode. Results on ISCAS85 circuits show that stuck-at test sets do quite well, but that the ATPG can still improve the coverage. We have also found that the loss of fault coverage is predominantly due to undetected faults, rather than faults in which only a small resistance is detected. This suggests that lower-cost fault models can be used to obtain high resistive bridge fault coverage.
827988
On Synchronous and Asynchronous Mobile Processes
This paper studies the relationship between synchronous and asynchronous mobile processes, in the setting of the π-calculus. A type system for processes of the asynchronous monadic subcalculus is introduced and used to obtain a full-abstraction result: two processes of the polyadic π-calculus are typed barbed congruent iff their translations into the subcalculus are asynchronous-monadic-typed barbed congruent.
14018858
Single event burnout in power diodes: Mechanisms and models
Power electronic devices are susceptible to catastrophic failures when they are exposed to energetic particles; the most serious failure mechanism is single event burnout (SEB). SEB is a widely recognized problem for space applications, but it also may affect devices in terrestrial applications. This phenomenon has been studied in detail for power MOSFETs, but much less is known about the mechanisms responsible for SEB in power diodes. This paper reviews the current state-of-knowledge of power-diode vulnerability to SEB, based on both experimental and simulation results. It is shown that present models are limited by the lack of detailed descriptions of thermal processes that lead to physical failure.