26328440
A Generic Network Design for a Closed-Loop Supply Chain Using Genetic Algorithm
Recently much research has focused on both the supply chain and reverse logistics network design problem. The rapid progress in computer and network technology and the increasingly fierce competition in recent times have compelled global company to consider these two networks in integrated view for efficient decision-making throughout the supply chain. The integrated problem, however, resembles a combinatorial problem, whose computation time to obtain an optimal solution increases exponentially in proportion to the size of the problem. Therefore, an algorithm able to generate a relatively good solution within a reasonable time is needed. In this study, we propose an LP- based genetic algorithm. The experimental results show that the proposed algorithm is superior to MIP solver in time and to traditional genetic algorithm in quality.
37359525
Central Point Crossover for Neuro-genetic Hybrids
In this paper, we consider each neural network as a point in a multi-dimensional problem space and suggest a crossover that locates the central point of a number of neural networks. By this, genetic algorithms can spend more time around attractive areas. We also apply representational normalization to neural networks to maintain genotype consistency in crossover. For the normalization, we utilize the Hungarian method of matching problems. The experimental results of our neuro-genetic algorithm overall showed better performance over the traditional multi-start heuristic and the genetic algorithm with a traditional crossover. These results are evidence that it is attractive to exploit central areas of local optima.
854647
Coupling-aware minimum delay optimization for domino logic circuits
Minimum delay associated with the hold time requirement is a concern to circuit designers, since race-through hazards are inherent to any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields significant increase of min-delay without incurring max-delay violation.
11692640
A new data model for biological classification
In the domain of biological classification, classifications are performed hierarchically. There are no standard classifications which are unanimously accepted by the community of each domain; many different interacting views of classification exist about the same data, and the discovery of new data results in changes to the existing classification. Even a single individual may change his or her own classification of a particular group. Since multiple classification views interact, they are semantically related. It is difficult to model this kind of dynamically evolving and semantically interacting classification system using traditional data models, which lack the structural flexibility necessary to support dynamic views of hierarchic classifications, and cannot properly capture the history of these complex interactions. We have developed a new data model which is suitable for supporting semantically interacting dynamic views of hierarchic biological classifications. On the basis of our new data model we have developed a prototype database system called HICLAS (HIerarchical CLAssification System); its domain is plant taxonomy. HICLAS is available through the Internet and an X-window interface has been implemented to support queries to classification data.
207003797
Optimal timing for skew-tolerant high-speed domino logic
When low threshold voltage (V/sub t/) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency.
31991923
Timing constraints for domino logic gates with timing-dependent keepers
Low threshold voltage (V/sub t/) can be applied to domino logic to improve the performance in dual threshold voltage technology. Then, the keeper transistor should be up-sized to compensate for reduced noise margin due to the significant subthreshold current of low V/sub t/ transistor. However, a large keeper transistor degrades performance. To resolve the tradeoff between performance and noise margin, the authors propose a new domino logic which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of the proposed domino logic yields optimal timing conditions wherein a contention-free skew-tolerant window is maximized. A broad range of the skew-tolerant window connotes robustness against noise and design parameter variations, while reduced contention between keeper and evaluation NMOS transistors ensures high-speed switching. The authors show that the dual keeper structure increases noise tolerance and delay logic gates fortify signal skew tolerance. Simulation results verify that the proposed domino logic is robust to noise and signal skew while presenting high performance and power efficiency.