5834794
Layer assignment for crosstalk risk minimization
In ultra-deep submicron technology, crosstalk noise is so severe that crosstalk avoidance merely in detailed routing is not adequate and it has to be considered in earlier design stages. In this paper, we propose two heuristics for crosstalk mitigation in layer assignment, which is a stage between global routing and detailed routing, so that subsequent crosstalk avoidance in detailed routing can be more attainable. The pre-detailed-routing crosstalk is estimated through a probabilistic model. The constraint on the amount of vias is also considered. Experimental results on benchmark circuits confirm the effectiveness of the proposed heuristics.
11408697
Path-Based Buffer Insertion
Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing.
1271597
An improved AMG-based method for fast power grid analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which needs to be modeled accurately in circuit design and verification. Meanwhile, the huge size of power grid requires its analysis to be fast and highly scalable. Algebraic multigrid (AMG) has been recognized as a promising approach for fast power grid analysis. We propose several techniques to improve AMG-based power grid analysis: (1) dynamic reduction threshold; (2) weighted interpolation; and (3) a new error smoothing scheme. Experimental results on power grid with up to 1.6 million nodes show that these techniques can improve accuracy by over 10 times compared to a reported industrial method while retaining the same fast speed
7189153
Antenna avoidance in layer assignment
The sustained progress of very-large-scale-integration (VLSI) technology has dramatically increased the likelihood of the antenna problem in the manufacturing process and calls for corresponding considerations in the routing stage. In this paper, the authors propose a technique that can handle the antenna problem during the layer-assignment (LA) stage, which is an important step between global routing and detailed routing. The antenna-avoidance problem is modeled as a tree-partitioning problem with a linear-time-optimal-algorithm solution. This algorithm is customized to guide antenna avoidance in the LA stage. A linear-time optimal jumper-insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 76% antenna-violation reduction and 99% via-violation reduction.
28075982
Clock buffer polarity assignment for power noise reduction
10406726
Associative Skew Clock Routing for Difficult Instances
In clock network synthesis, sometimes skew constraints are required only within certain groups of clock sinks and do not exist between different groups. This is the so-called associative skew clock routing problem. Although the number of constraints is reduced, the problem becomes more difficult to solve due to the enlarged solution space. The perhaps only previous work used a very primitive delay model and cannot handle difficult instances in which sink groups are intermingled. We reuse existing techniques to solve this problem, including the difficult instances, based on a more accurate and popular delay model. Experimental results show that our algorithm can reduce the total clock routing wirelength by 12% on average compared to greedy-DME which is one of the best zero skew routing algorithms
13437077
Scheduling reusable instructions for power reduction
In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the issue queue is reusing instructions, no instruction cache access is needed since the instructions are supplied by the issue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages before register renaming). Results using array-intensive codes show that up to 82% of the total execution cycles, the pipeline front-end can be gated, providing a power reduction of 72% in the instruction cache, 33% in the branch predictor, and 21% in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code.
827612
Compiler-directed cache polymorphism
Classical compiler optimizations assume a fixed cache architecture and modify the program to take best advantage of it. In some cases, this may not be the best strategy because each loop nest might work best with a different cache configuration and transforming a nest for a given fixed cache configuration may not be possible due to data dependences. Working with a fixed cache configuration can also increase energy consumption in loops where the best required configuration is smaller than the default (fixed) one. In this paper, we take an alternate approach and modify the cache configuration for each nest depending on the access pattern exhibited by the nest. We call this technique compiler-directed cache polymorphism (CDCP). More specifically, in this paper, we make the following contributions. First, we present an approach for analyzing data reuse properties of loop nests. Second, we give algorithms to simulate the footprints of array references in their reuse space. Third, based on our reuse analysis, we present an optimization algorithm to compute the cache configurations for each nest. Our experimental results show that CDCP is very effective in finding the near-optimal data cache configurations for different nests in array-intensive applications.
18760651
Modelling of SACK TCP and application to the HTTP file transfer environment
It is known that analytic modelling for TCP latency is a non trivial task. Recently, some significant progress has been made, such as the comprehensive result by Sikdar et al. However, models similar to these often rely on trial and error methods such as "data fitting". This can lead to a very limited scope for the resulting model and also large estimation error. In this paper, we propose improvements to Sikdar's SACK TCP model. A new delayed acknowledgement slow start model is developed that is analytically derived from the slow start algorithm which provides a novel mechanism to model the relationship between RTT and the delayed acknowledgement timer. We introduce a simple mechanism to include time taken to send an HTTP get request to broaden the scope of our SACK TCP model to Website file transfer. Simulation and live Internet experimentation has validated our scheme
15489348
A Gradient Based Weighted Averaging Method for Estimation of Fingerprint Orientation Fields
Estimation of orientation fields is an essential module in a fingerprint recognition system. Conventional gradient based approaches are popular but very sensitive to noise. In this paper, we propose a new implementation that is more resistant to noise. Our basic idea is to conduct redundant estimation over four overlapping neighborhoods for each target block. Following this idea, we devise a weighted averaging scheme operated on the base blocks directly. Thus, each block (including the target one) in the overlapping neighborhoods has different impact on estimation of the dominant orientation fields. Our preliminary experiment results suggest that the proposed weighted averaging algorithm is more robust against noise in comparison with other gradient based methods.
11197335
Traffic grooming, routing, and wavelength assignment in optical WDM mesh networks
In this paper, we consider the traffic grooming, routing, and wavelength assignment (GRWA) problem for optical mesh networks. In most previous studies on optical mesh networks, traffic demands are usually assumed to be wavelength demands, in which case no traffic grooming is needed. In practice, optical networks are typically required to carry a large number of lower rate (sub-wavelength) traffic demands. Hence, the issue of traffic grooming becomes very important since it can significantly impact the overall network cost. In our study, we consider traffic grooming in combination with traffic routing and wavelength assignment. Our objective is to minimize the total number of transponders required in the network. We first formulate the GRWA problem as an integer linear programming (ILP) problem. Unfortunately, for large networks it is computationally infeasible to solve the ILP problem. Therefore, we propose a decomposition method that divides the GRWA problem into two smaller problems: the traffic grooming and routing problem and the wavelength assignment problem, which can then be solved much more efficiently. In general, the decomposition method only produces an approximate solution for the GRWA problem. However, we also provide some sufficient condition under which the decomposition method gives an optimal solution. Finally, some numerical results are provided to demonstrate the efficiency of our method.