42440717
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards
Multi-FPGA boards(MFBs) are extensively used by the designers for logic emulation, rapid prototyping, custom computing and low volume sub-system implementation. Efficient use of an MFB does not only require a good routing topology, but also a good set of CAD tools to partition the given circuits and embed them on the MFB. Khalid et al[1] have shown that among the MFB topologies, hybrid series of architectures containing fixed FPGA-FPGA connections and programmable connections through Field Programmable Interconnect Devices(FPIDs) are better than other architectures. Programmable connections can connect different pairs of FPGAs under program control, but require additional wires, extra delays etc. compared to fixed connection. 
 
An MFB, to be used in rapid prototyping, is expected to emulate a large number of digital circuits. To accommodate the routing requirement generated by partitioning them, MFB is required to have significantly large number of programmable connections. In this paper, we have shown that an efficient embedding tool can substantially reduce the requirement of programmable connections. The paper presents an optimal as well as a fast heuristic for embedding. Our methods can work with a large class of hybrid routing topologies.
2205933
Hybrid Multi-FPGA board evaluation by limiting multi-hop routing
Multi-FPGA Boards (MFBs) have been in use for more than a decade for emulation of the digital circuits in many applications. Key feature of an MFB architecture is its inter-FPGA connections. There are two types of inter-FPGA connections namely: i) fixed connection (FC)-connecting a pair of FPGAs through a dedicated wire between them, ii) programmable connection (PC)-connecting a pair of FPGAs through a programmable switch like Field-Programmable Interconnect Device (FPID). Hence, a PC requires two wires compared to one wire in FC. Khalid et al. (1999) have shown that the MFBs consisting of both the types of connections (hybrid MFBs) are better than other architectures for emulation of the circuits, if the number of PCs are minimum required. Hence, we evaluate the hybrid MFBs for the required number of PCs as an evaluation metric. Availability of technology mapping, partitioning, embedding and routing tools is another important requirement for emulation. A routing tool (multi-hop router) prefers one or more unused FCs (multi-hops) in lieu of one PC. Available multihop routers are specific to MFB architecture and use unlimited hops in the routes. For evaluation, a generic multi-hop router for any hybrid architecture is required which obeys the given limit on maximum number of hops in every route. This paper presents the development of routing tool for the same. A heuristic, a lower bound and an optimal algorithm has been implemented for this purpose. For the test cases, it has been observed that the optimal results (within 3 hours) are achievable by the heuristic (within a minute). Also the results are more precise than the available results.
17585976
Evaluation of various routing architectures for multi-FPGA boards
Multi-FPGA boards are being used for logic emulation, rapid prototyping, custom computing and low volume subsystem implementation. A key feature which characterizes these boards is their routing architecture (RA). Inter-FPGA connections in an RA can be of two types, named, fired connections through direct wires and programmable connections through intermediate Field-Programmable Interconnect Devices. This paper presents an analytical approach for evaluating routing performance of an RA employing both types of connections. Our approach consists of two steps: 1) generation of a random interconnection requirement matrix for modeling real circuits with an orientation towards the available interconnection architecture. 2) Checking the routability of the generated matrix on the given RA. The evaluation experiments for many RAs demonstrate that our methodology matches in results with purely experiment based approaches. However, it is more versatile in that it can evaluate new RAs. Also it provides more observability and controllability of architectural, circuit and performance parameters.
17397415
Analyzing the supply chain for a large logistics operation using simulation
This paper presents a case study of using simulation for analyzing the impact of proposed changes in the supply chain processes for a large logistics operation. The major changes explored include business process changes, and use of new supply chain software. The results of the analysis indicate that the changes in forecast accuracy provide much larger savings compared to process automation changes. A number of insights are drawn from the results of the analyses.
6477912
Stress testing a supply chain using simulation
Simulation provides the capability to evaluate performance of a system operating under current or proposed configurations, policies and procedures. It is very applicable to evaluation of strategic and operational level plans for supply chains. It is especially useful for exploring the viability of a supply chain before beginning production. This paper describes the use of simulation for determining the readiness of a supply chain designed by a small company for providing sub-systems to a defense contractor. The supply chain had to be stress tested at surge and mobilization volume levels to meet the requirements. Simulation provided the ideal methodology to identify and demonstrate the behavior of the supply chain under stress and evaluate strategies to meet the defined volumes. It was used to prove the readiness of the supply chain reducing perceived risks in using the virtual operation.
206721
An approximation to the greedy algorithm for differential compression of very large files
This paper presents a new differential compression algorithm that combines the hash value and suffix array technique. In this algorithm, hash values for every block of the reference file is computed. Next, suffix arrays on these block hash values are computed. This algorithm finds the longest matches for every offset of the version file. This algorithm depends upon the utilization of three new data structures, the block hash table, the quick index array, and the pointer array, which improves the run-time of the algorithm, and compress very large files.
9214465
Performance prediction tools for parallel discrete-event simulation
We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important factors in the actual speedup of a parallel simulation program: the simulation protocol used; and the inherent parallelism in the simulation model. The first two tools are a performance/parallelism analyzer for a conservative, asynchronous simulation protocol, and a similar analyzer for a conservative, synchronous (super-step) protocol. Each analyzer allows us to study how the speedup of a model changes with increasing number of processors, when a specific protocol is used. The third tool-a critical path analyzer-gives on ideal upper bound to the model's speedup. This paper gives an overview of the prediction tools, and reports the predictions from applying the tools to a discrete-event wafer fabrication simulation model. The predictions are close to speedups from actual parallel implementations. These tools help us to set realistic expectations of the speedup from a parallel simulation program, and to focus our work on issues which are more likely to yield performance improvement.
39123560
High Quality Compression of Educational Videos Using Content-Adaptive Framework
With multimedia E-learning becoming popular, better compression algorithms are required that are space efficient but maintain the quality of video data, particularly slide and blackboard text. In this paper, an educational video compression technique is presented that dynamically allocates the space according to the content importance of each video segment in the educational videos. We present a phase correlation based motion estimation and compensation algorithm to encode important moving objects in efficient manner. Temporal coherence is exploited in a two phase manner. First, the frames with high similarity are categorized and encoded efficiently. Secondly, the compression ratio is adapted according to the frame content. The algorithm is compared with the state-of-the-art standards such as H.261, MPEG-4, etc. on large database. The comparison shows that for similar bit rates, the video quality for our algorithm is significantly better than the other methods.