10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
6164806
Deterministic Models of Software Aging and Optimal Rejuvenation Schedules
Automated modeling of software aging processes is a prerequisite for cost-effective usage of adaptive software rejuvenation as a self-healing technique. We consider the problem of such automated modeling in server-type applications whose performance degrades depending on the "work" done since last rejuvenation, for example the number of served requests. This type of performance degradation - caused mostly by resource depletion - is common, as we illustrate in a study of the popular Axis Soap server 1.3. In particular, we propose deterministic models for approximating the leading indicators of aging and an automated procedure for statistical testing of their correctness. We further demonstrate how to use these models for finding optimal rejuvenation schedules under utility functions. Our focus is on the important case that the utility function is the average of a performance metric (such as maximum service rate). We also consider optional SLA constraints under which the performance should never drop below a specified level. Our approach is verified by a study of the aging processes in the Axis Soap 1.3 server. The experiments show that the deterministic modeling technique is appropriate in this case, and that the optimization of rejuvenation schedules can greatly improve the average maximum service rate of an aging application.
16534842
Formal Verification of Component-Based Software Systems
In this work we present a methodology for formal modeling and verification of component based software systems. The methodology is based on software architecture, components, and reuse of Petri Nets models. With this process, we are contributing for the visual composition, verification, and formal validation of software. We also show an example of the application of this methodology into two different domains.
14315671
Implementing distributed shared memory on top of MPI: the DSMPI library
Distributed shared memory has been recognized as an alternative programming model to exploit the parallelism in distributed memory systems since it provides a higher level of abstraction than simple message passing. DSM combines the simple programming model of shared-memory with the scalability of distributed memory machines. This paper presents DSMPI, a parallel library that runs atop of MPI and provides a distributed shared memory abstraction. It provides an easy-to-use programming interface, is flexible, portable and supports heterogeneity. Moreover, it supports different coherence protocols and models of consistency. We present some performance results taken in a network of workstations and in a Cray T3D which show that DSMPI can be competitive with MPI for some applications.
14564941
PetroGrapher: managing petrographic data and knowledge using an intelligent database application
This paper describes the PetroGrapher system, an intelligent database application to support petrographic analysis, interpretation of oil reservoir rocks, and management of relevant data using resources from both knowledge-based system technology and database technology. In this project, the visual tacit knowledge applied in petrographic analysis was rendered explicit through the collection of cases (rock descriptions), which were then used in the development of a domain ontology organized in a partonomy. Expert-level basic features, which we call ‘visual chunks’, were identified. The cases were further compared against the ontology to elucidate the relations between features in descriptions of rocks, visual chunks and expert interpretations. The domain knowledge was represented through a set of frames and knowledge graphs. The knowledge graphs are applied to recognize the visual chunks in the user data and retrieved the related interpretation. The system was developed as a structure tightly coupled with a relational database system, which acts as a repository for the knowledge base and the user data, and an object-oriented component, which preserves the semantics of data and develops inferences. The system was validated by three groups of users with different levels of expertise. q 2003 Elsevier Ltd. All rights reserved.
18094279
DGSchedSim: a trace-driven simulator to evaluate scheduling algorithms for desktop grid environments
This paper describes DGSchedSim, a trace driven simulator to evaluate scheduling algorithms focused on minimising turnaround time of applications executed in heterogeneous desktop grid systems. The simulator can be used to model task farming applications comprised of a set of independent and equal sized tasks similarly to numerous @Home public computing projects like the popular SETI@Home. DGSchedSim permits to assess scheduling policies under several scenarios allowing to control parameters such as the application's requirements (number of tasks, individual requirements of tasks like needed CPU time), the properties of the environment (machines computing capabilities and availabilities) and the characteristics of the execution (frequency and storage location of checkpoints, etc.). The simulations are driven by traces collected from real desktop grid systems. Besides DGSchedSim, the paper presents the Cluster Ideal Execution Time (CIET) algorithm that computes the ideal wall-clock time required by a fully dedicated and totally reliable cluster of M heterogeneous machines to process the T tasks of an application. As a test to the simulator capabilities, the paper analyses the suitability of two scheduling algorithms, FCFS and MinMax, for delivering fast turnaround time in desktop grids. Both algorithms, when combined with a centrally stored checkpoint policy, achieve efficiency close to 50% of CIET for certain scenarios.