42022872
Template Directed Development of Web-Based Information Systems
30084488
Design Patterns for Parallel Programming
4599558
Pruning Update Log Files in Intermittently Connected Databases
Modern databases allow mobile clients that subscribe to replicated data, to process the replica without requiring continuous connectivity, and to receive the updates while connected to the server. In such an environment—usually known as the Intermittently Connected Database (ICDB) system—the server should maintain the updates to the database in the log file(s). These update log files should be pruned to reduce update retrieval time. In this paper we propose two pruning algorithms, based on the periodic connectivity of the clients, that consider two scenarios: uniform client connectivity patterns and widely varying client connectivity patterns. In the former case, the complete pruning algorithm is effective in keeping the log file size within a bound, hence reducing both disk I/O during update propagation, and disk storage space; whereas, in case of the latter, the partial pruning algorithm achieves significant further reduction in disk I/O while retrieving the updates. Any reduction in CPU or I/O time in turn reduces wireless connection time for each client resulting in significant savings in time and costs. Experimental results demonstrate the effectiveness of these algorithms.
28610861
A User Level, Reliable, and Reconfigurable Transport Layer Protocol
It is well known that TCP is not suitable for a number of environments such as wireless, satellite, and long-fat-pipe networks. At the same time, there is no other single transport protocol that would outperform TCP in all situations. In this paper, we explore an alternative transport layer protocol that is more suitable for today’s mobile as well as other non-conventional network environments. The result is a user-level, reconfigurable, TCP-friendly (asymptotically converges to fairness as in the case of LIMD (Linear Increase Multiplicative Decrease) algorithms) transport layer protocol, called RRTP (Reliable and Reconfigurable Transport Protocol), which runs atop of UDP. We evaluate our protocol using the standard network simulation tool (ns2). Several representative network configurations are used to benchmark the performance of our protocol against TCP in terms of network throughput and congestion loss rate. It is observed that under normal operating conditions, our protocol has a performance advantage of 30% to 700% over TCP in lossy, wireless environments as well as high bandwidth, high latency networks.
5517060
Structuring Distributed Algorithms in a Workstation Environment: The FrameWorks Approach
42975476
An Integrated Performance Analysis Tool for SPMD Data-Parallel Programs
Abstract A new generation of data parallel languages have been proposed whereby a user specifies how data structures are to be distributed amongst the processor nodes of a distributed-memory machine. Based on this information, the compiler then generates code for the parallel application. Although this approach significantly simplifies the development of the initial version of a parallel application, selection of good data distributions leading to efficient computations is often quite difficult. Therefore, performance debuggers are needed to yield insights into the data distribution effects. On the other hand, most of the existing approaches to performance debugging are very general and thus do not provide the user feedback in terms of the high level programming model or the source code of the parallel application. In this paper, we describe a novel approach to performance debugging of data parallel programs. The design and implementation of a visual performance debugger is described that is specifically targeted to meet the performance debugging requirements of a data-parallel programming model based on user-specified data distributions. The performance debugger is part of an integrated programming environment, called EPPP, which also supports a data parallel compiler and a parallel architecture simulator. Thus development and performance debugging of an application may be done either on the real hardware or by using the simulator. The code for EPPP can be obtained free of cost (contact web address, http://www.crim.ca/apar).
2485299
Sizing CMOS circuits for increased transient error tolerance
The continuous shrinking of microelectronic device sizes with every technology generation, along with the reduction in supply voltages, is causing a significant decrease in circuit noise margins. This leads to increased susceptibility of circuits to transient errors. In this paper, we propose a methodology to increase the robustness of combinational circuits to transient errors by sizing the gates of the circuit in such a way that the number of errors propagated to the primary output is minimized while the timing requirement is met. Using SPICE simulation, we validate that combinational circuits propagate fewer numbers of transient errors to the circuit output after application of our sizing algorithm.
15601419
A Peer-to-Peer Reference Architecture
Peer-to-peer (P2P) applications are extremely popular on the Internet because they allow users to share information in a decentralized manner. Internet users use file-sharing applications (e.g., BitTorrent, KaZaA) to share and exchange files and collaboration applications (e.g., Jabber, Groove) to exchange chat messages and work on shared documents. A reference architecture for a domain provides an architecture template which can be used as a starting point for designing the software architecture of a system in that domain. Despite the popularity of P2P applications there is no reference architecture for the P2P domain. This paper presents a reference architecture for the P2P domain. The reference architecture has been designed to satisfy the concerns that a P2P application needs to address. The reference architecture takes a service-centric view of the P2P domain. The reference architecture can be used to describe the structure of existing P2P applications and middlewares. The paper validates the reference architecture by describing the structure of some of the existing P2P applications and middlewares using the reference architecture
6105186
Query-based debugging of object-oriented programs
Object relationships in modem software systems are becoming increasingly numerous and complex. Programmers who try to find violations of such relationships need new tools that allow them to explore objects in a large system more efficiently. Many existing debuggers present only a low-level, one-object-at-a-time view of objects and their relationships. We propose a new solution to overcome these problems: query-based debugging. The implementation of the query-based debugger described here offers programmers an effective query tool that allows efficient searching of large object spaces and quick verification of complex relationships. Even for programs that have large numbers of objects, the debugger achieves interactive response times for common queries by using a combination of fast searching primitives, query optimization, and incremental result delivery.
9094346
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.
13609251
Creating an adaptive network of hubs using Schelling's model
Adjusting the overlay network topology in a peer-to-peer network to satisfy performance criteria.