1246119
Interface synthesis using memory mapping for an FPGA platform
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.
1656626
Coordinated parallelizing compiler optimizations and high-level synthesis
We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the <i>SPARK</i> framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.
1958013
Analysis of high-level address code transformations for programmable processors
Memory intensive applications require considerable arithmetic for the computation and selection of the different memory access pointers. These memory address calculations often involve complex (non) linear arithmetic expressions which have to be calculated during program execution under tight timing constraints, this becoming a critical bottleneck in the overall system performance. This paper explores applicability and effectiveness of source-level optimisations (as opposed to instruction-level) for address computations in the context of multimedia. We propose and evaluate two processor-target independent source-level optimisation techniques, namely, global scope operation cost minimisation complemented with loop-invariant code hoisting, and nonlinear operator strength reduction. The transformations attempt to achieve minimal code execution within loops and reduced operator strengths. The effectiveness of the transformations is demonstrated with two real-life multimedia application kernels by comparing the improvements in the number of execution cycles, before and after applying the systematic source-level optimisations. Using state-of-the-art C compilers on several popular RISC platforms.
2982914
Network topology exploration of mesh-based coarse-grain reconfigurable architectures
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these architectures: (a) changing the interconnection between PEs; (b) changing the way the network topology is traversed while mapping operations to the PEs; and (c) changing the communication delays on the interconnects between PEs. We propose network topology traversal strategies that first schedule PEs that are spatially close and that have more interconnections among them. We use an interconnect aware list scheduling heuristic as a vehicle to perform the network topology exploration experiments on a set of designs derived from DSP applications. Our experimental results show that a spiral traversal strategy, coupled with a two neighbor interconnect topology leads to good performance for the DSP benchmarks considered. Our prototype framework thus provides an exploration environment for system architects to explore and tune coarse-grain reconfigurable architectures for particular application domains.
8312479
Using global code motions to improve the quality of results for high-level synthesis
The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code-motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We have implemented these code transformations, along with supporting code-motion techniques and variable renaming techniques, in a high-level synthesis research framework called Spark. Spark takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. We present results for experiments on designs derived from three real-life multimedia and image processing applications, namely, the MPEG-1 and -2 and GNU image manipulation program applications. We find that the speculative-code motions lead to reductions between 36% and 59% in the number of states in the finite-state machine (controller complexity) and the cycles on the longest path (performance) compared with the case when only nonspeculative code motions are employed. Also, logic synthesis results show fairly constant critical path lengths (clock period) and a marginal increase in area.
5173214
Dynamic common sub-expression elimination during scheduling in high-level synthesis
We introduce a new approach, "Dynamic Common Sub-expression Elimination (CSE)", that dynamically eliminates common sub-expressions based on new opportunities created during scheduling of control-intensive designs. Classical CSE techniques fail to eliminate several common sub-expressions in control-intensive designs due to the presence of a complex mix of control and data-flow. Aggressive speculative code motions employed to schedule control-intensive designs often re-order, speculate and duplicate operations, hence changing the control flow between the operations with common sub-expressions. This leads to new opportunities for applying CSE dynamically. We have implemented dynamic CSE in a high-level synthesis framework called Spark and present results for experiments performed using various combinations of CSE and dynamic CSE. The benchmarks used consist of four functional blocks derived from two moderately complex industrial-strength applications, namely, MPEG-1 and the GIMP image processing tool. Our dynamic CSE techniques result in improvements of up to 22% in the controller size and up to 31% in performance; easily surpassing the improvements obtained by the traditional CSE approach. We also observe an unexpected (and significant) reduction in the number of registers using our approach.
6948566
Process variations and their impact on circuit operation
The statistical variations in electrical parameters, such as transistor gain factors and interconnect resistances, due to variations in the manufacturing process are studied using data obtained from a 0.8 /spl mu/m CMOS process. The impact of these variations and correlations on circuit operation is illustrated. Examples show that circuit delay can increase from the mean by about 100% due to crosstalk effects aggravated by process variations. Case studies emphasize the need for a tighter coupling between fabrication and circuit design and the need for new design corners based on process information.
28095704
An automatic test pattern generator for at-speed robust path delay testing
At-speed robust path delay testing is more desirable than the commonly employed slow-fast delay testing due to lower test application time, lower area overhead, and increased possibility of detecting unmodeled faults that cause errors only during at-speed circuit operation. However, it has been observed in practice that at-speed application of tests generated by existing test generators can lead to their invalidation. In this paper, we first present techniques to modify tests generated by existing test generators to avoid invalidation during at-speed testing. We then present a new procedure to generate tests suitable for at-speed delay testing of combinational circuits. Experimental results show that (a) at-speed application of test sets generated by existing generators leads to significant test invalidation, where the degree of invalidation is approximately proportional to the degree of compactness of the test set, and (b) the at-speed robust path delay tests generated by the proposed test generator are significantly shorter than those obtained by modifying the tests generated by existing generators.
18759063
The Software Concordance: using a uniform document model to integrate program analysis and hypermedia
Since the source code is only one of many types of documents that must be maintained as a software system evolves, modern software development could be improved by better interoperability between source code and other software documents. The Software Concordance is a prototype programming environment that uses hypermedia services and a uniform document model to achieve this interoperability. The Software Concordance editor allows developers to enhance their inline documentation with multimedia objects and hyperlinks, while still supporting advanced program analysis including lexing, parsing and type checking. We motivate the need for environments like the Software Concordance, describe the design and implementation of its program editor, and discuss lessons learned while creating it. The system is based on a uniform, Web compatible document model for both program source code and nonprogram software documents and a corresponding API. Important technical problems addressed by this research include creating a persistent representation of program lexemes that the analysis suite considers to be ephemeral (such as keywords), providing a simple incremental parsing system, and embedding multimedia in source code without disrupting program analysis. Based on insight gained in the process of implementing the document API, a new approach to the design of a more suitable program analysis infrastructure is suggested.
18593367
Biosec: a biometric based approach for securing communication in wireless networks of biosensors implanted in the human body
Advances in microelectronics, material science and wireless technology have led to the development of sensors that can be used for accurate monitoring of inaccessible environments. Health monitoring, telemedicine, military and environmental monitoring are some of the applications where sensors can be used. The sensors implanted inside the human body to monitor parts of the body are called biosensors. These biosensors form a network and collectively monitor the health condition of their carrier or host. Health monitoring involves collection of data about vital body parameters from different parts of the body and making decisions based on it. This information is of personal nature and is required to be secured. Insecurity may also lead to dangerous consequences. Due to the extreme constraints of energy, memory and computation securing the communication among the biosensors is not a trivial problem. Key distribution is central to any security mechanism. In this paper we propose an approach wherein, biometrics derived from the body are used for securing the keying material. This method obviates the need for expensive computation and avoids unnecessary communication making our approach novel compared to existing approaches.
13275430
Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions
In this paper, we present a framework for synthesizing I/O efficient out-of-core programs for block recursive algorithms, such as the fast Fourier transform (FFT) and block matrix transposition algorithms. Our framework uses an algebraic representation which is based on tensor products and other matrix operations. The programs are optimized for the striped Vitter and Shriver's two-level memory model in which data can be distributed using various cyclic(B) distributions in contrast to the normally used physical track distribution cyclic(B/sub d/), where B/sub d/ is the physical disk block size. We first introduce tensor bases to capture the semantics of block-cyclic data distributions of out-of-core data and also data access patterns to out-of-core data. We then present program generation techniques for tensor products and matrix transposition. We accurately represent the number of parallel I/O operations required for the synthesized programs for tensor products and matrix transposition as a function of tensor bases and data distributions. We introduce an algorithm to determine the data distribution which optimizes the performance of the synthesized programs. Further, we formalize the procedure of synthesizing efficient out-of-core programs for tensor product formulas with various block-cyclic distributions as a dynamic programming problem. We demonstrate the effectiveness of our approach through several examples. We show that the choice of an appropriate data distribution can reduce the number of passes to access out-of-core data by as large as eight times for a tensor product and the dynamic programming approach can largely reduce the number of passes to access out-of-core data for the overall tensor product formulas.