19852972
Distributed Instruction Set Computer Architecture
The Distributed Instruction Set Computer Architecture (DISC) is proposed as a fine-grained multiprocessing computer architecture. DISC uses a parallel instruction set and a distributed control mechanism to explore fine-grained, parallel processing in a multiple-functional-unit system. Multiple instructions are executed in parallel and/or out of order at the highest speed of n instructions/cycle, where n is the number of functional units. Based on this architecture, a hardware system is developed. Extensive studies were conducted on a behavioral DISC system model to investigate the performance level, the effect of program sizes, and the hardware utilization. Simulation showed that a DISC system incorporating 16 functional units can run 7.7 times faster than a single-functional-unit DISC system. >
15881866
Performance analysis of circuit switching, baseline interconnection networks
Performance evaluation, using both analytical and simulation models, of circuit switching baseline networks is presented. Two configurations of the baseline networks, single and dual, are evaluated. In each configuration, two different conflict resolution strategies, drop and hold, are tried to see the performance difference. Our analytical models are based on a more realistic assumption. New analyses are given and are verified by simulation results. In single network configuration, it is shown that the drop strategy is better than the hold strategy in the case that the data transfer time is longer than 10 cycles under a high request rate. In the dual network configuration, five different communication strategies are investigated and the optimum performance level is shown to be dependent on the length of the data transfer time.
31789422
Performance Analysis of Multistage Interconnection Network Configurations and Operations
A performance evaluation using both analytical and simulation models, of circuit-switching multistage interconnection networks in aspects of configurations and operations is presented. Two configurations of the networks, single and dual, are evaluated. Network operations considered include conflict resolution strategies and communication strategies. Two different conflict resolution strategies, drop and hold, are analyzed. New analyses using Markov chains, are given, and are verified by simulation results. In the single-network configuration, it is shown that the drop strategy is better than the hold strategy for randomly distributed traffic. In the dual network configuration, five different communication strategies are investigated, and the optimum performance level is shown to be dependent on the length of the data transfer time. >
206622161
The Reverse-Exchange Interconnection Network
Properties of the reverse-exchange interconnection network are used to develop a reconfiguration scheme and a two-pass structure for enhancing the efficiency of a class of multistage interconnection networks. Functional relationships among a class of multistage interconnection networks are first derived. According to the functional relationships, we propose a reconfiguration scheme which enables a network to accomplish various interconnection functions of other networks. Then the admissible permutations along with related recursive control algorithms of the reverse-exchange interconnection network are specified through a set of theorems. Using the reverse-exchange property, we also prove that the algorithms actually work. Finally, we prove that arbitrary permutations can be realized in two passes (or 2 · 1og2N switching steps where N is the network size). By taking advantage of Benes network control algorithms, a way to control the two-pass structure is also developed.
27793990
Fail Safe Distributed Fault Diagnosis of Multiprocessor Systems
41641437
Network Facility for a Reconfigurable Computer Architecture
15142715
A cokriging method for estimating population density in urban areas
Population information is typically available for analysis in aggregate socioeconomic reporting zones, such as census blocks in the United States and enumeration districts in the United Kingdom. However, such data mask underlying individual population distributions and may be incompatible with other information sources (e.g. school districts, transportation analysis zones, metropolitan statistical areas, etc.). Moreover, it is well known that there are potential significance issues associated with scale and reporting units, the modifiable areal unit problem (MAUP), when such data are used in analysis. This may lead to biased results in spatial modeling approaches. In this study, impervious surface fraction derived from Thematic Mapper (TM) imagery was applied to derive the underlying population of an urban region. A cokriging method was developed to interpolate population density by modeling the spatial correlation and cross-correlation of population and impervious surface fraction. Results suggest that population density can be accurately estimated using cokriging applied to impervious surface fraction. In particular, the relative population estimation error is � 0.3% for the entire study area and 10–15% at block group and tract levels. Moreover, unlike other interpolation methods, cokriging gives estimation variance at the TM pixel level. 2005 Elsevier Ltd. All rights reserved.
40872599
Timestamp consistency and trace-driven analysis for distributed parallel systems
A continuous stream of event data describing the progress of parallel program execution is realized for trace-driven analysis. Unfortunately, it is often the case that separate streams are produced independently by multiple processors in the system, and the logical order of events cannot be guaranteed due to discrepancy among local clocks. We present an integrated approach for timestamp consistency and performance analysis techniques for IBM SPn systems. The trace facility requires no source code modification, and can generate message passing and system events with minimal trace overhead. Trace-driven analysis tools are developed to extract useful information. Analysis results for NAS kernel benchmarks are reported.<<ETX>>
14149213
Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches
We propose efficient stack simulation algorithms for shared memory multiprocessor (MP) caches. A stack simulation algorithm for write-updated MP caches is first presented. It produces the number of write-updates as well as misses for all cache configurations in a single run. We then devise a new stack simulation algorithm for writeinvalidate MP caches. Our algorithm takes into account cross-invalidation among processors, and generates the number of invalidations as well as misses for all cache configurations in a single run. A cache simulator based on our algorithms for MP caches is developed and the results on sample traces are reported. Our results show that effi cient stack simulation is a powerful technique for multi processor cache analysis.
3236118
Human performance modeling in temporary segmentation Chinese character handwriting recognizers
Human performance in Chinese character handwriting recognizers is critical to the satisfaction and acceptance of their users. Based on Teal's [CHI'92 (1992) p. 295] interactive model, a static model describing the independent factors in determining the task completion time was set up with a simple mathematical inference; in addition, a dynamic model describing these factors' direct and indirect causal relationship was established by the path analytic method. Results in Experiment 1 indicated that both the static model and the dynamic model could fit observed task completion time satisfactorily with minor modifications. In addition, with users' average writing time around 1500 ms for each frequently used character, it was found that the user's performance was impaired significantly when segmentation time was longer than 1040 ms. An integrated model was devised after combining the static and dynamic models. Experiment 2 testified the integrated model in another handwriting recognizer and found that it could still fit human performance data with users in three different training conditions. Implications of the integrated model are that: (1) when recognition accuracy and number of inputting characters are constant, the weights of average writing time for each character, segmentation time, recognition time in determining task completion time are equal but bigger than the weight of the repairing time; (2) when the repairing time, average writing time for each character, segmentation time and recognition time are constant, there is an inverse model between task completion time and recognition accuracy; when recognition accuracy is from 50% to 93%, every 1% increase of recognition accuracy will reduce task completion time from 1989 to 1915 ms; when recognition accuracy increases from 94% to 100%, every 1% increase of recognition accuracy will reduce task completion time from 1895 to 1392 ms. Guidelines in designing these recognizers were given based on these implications.
11414897
Trace-based analysis and tuning for distributed parallel applications
We present an integrated approach to deal with timestamp consistency, and trace based performance analysis techniques for distributed parallel applications. Our trace generation facility captures message passing and system events such as process dispatch with minimal trace overhead. Trace driven analysis tools are developed for post execution analysis, reporting information such as the time stolen by other processes in each node, and the observed message passing time and local wait time for each message. We then present our techniques to reduce total elapsed times based on observed message passing times and local wait times.