161273
Dynamic power management for streaming data
This paper presents a method that uses data buffers to smoothen request variations and to create long idleness for power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes and the amount of data to store in the buffers. We use video prefetching as a case study and obtain power savings of more than 74% for MPEG-1 and 34% for MPEG-2 videos.
11944586
Comparing System-Level Power Management Policies
Reducing power consumption is a challenge to system designers. Portable systems, such as laptop computers and personal digital assistants (PDAs), draw power from batteries, so reducing power consumption extends their operating times. For desktop computers or servers, high power consumption raises temperature and deteriorates performance and reliability. Soaring energy prices and rising concern about the environmental impact of electronics systems further highlight the importance of low power consumption. Power reduction techniques can be classified as static and dynamic. Static techniques, such as synthesis and compilation for low power, are applied at design time. In contrast, dynamic techniques use runtime behavior to reduce power when systems are serving light workloads or are idle. These techniques are known as dynamic power management (DPM). DPM can be achieved in different ways; for example, dynamic voltage scaling (DVS) changes supply voltage at runtime as a method of power management. Here, we use DPM specifically for shutting down unused I/O devices. We built an experimental environment on a laptop computer running Microsoft Windows. We implemented existing power management policies and quantitatively compared their effects on power saving and performance degradation.
7685891
Quantitative comparison of power management algorithms
Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated to be effective in certain applications. We quantitatively compare the power saving and performance impact of these algorithms on hard disks of a desktop and notebook computers. This paper has three contributions. First, we build a framework in Windows NT to implement power managers running realistic workloads and directly interacting with users. Second, we define performance degradation that reflects user perception. Finally, we compare power saving and performance of existing algorithms and analyze the difference.
8031661
Requester-aware power reduction
Typically, power reduction is conducted by hardware techniques, such as varying clock frequencies and/or supply voltages. However, hardware devices consume power to serve the requests from software programs. Consequently, it is essential to consider software for power reduction. This paper proposes "requester-aware" power reduction through the collaboration with programs. Experimental results show that this approach can save nearly 70% power with negligible performance degradation.
14287933
Statistically optimal dynamic power management for streaming data
This paper presents a method that uses data buffers to create long periods of idleness to exploit power management. This method considers the power consumed by the buffers and assigns an energy penalty for buffer underflow. Our approach provides analytic formulas for calculating the optimal buffer sizes without subjective or heuristic decisions. We simulate four different hardware configurations with MPEG-1, MPEG-2, and MPEG-4 formats as a case study. Our results indicate that the optimal buffer size varies significantly for different data formats on different hardware. Simulation results indicate that 16 MB buffers are sufficient for MPEG-1, MPEG-2, and MPEG-4 video streams from a microdrive or a network card, but transfers from an IDE disk require buffer sizes ranging from 16 MB to 176 MB, depending on each video's statistical properties.
5831663
Program counter-based prediction techniques for dynamic power management
Reducing energy consumption has become one of the major challenges in designing future computing systems. This paper proposes a novel idea of using program counters to predict I/O activities in the operating system. It presents a complete design of program-counter access predictor (PCAP) that dynamically learns the access patterns of applications and predicts when an I/O device can be shut down to save energy. PCAP uses path-based correlation to observe a particular sequence of program counters leading to each idle period and predicts future occurrences of that idle period. PCAP differs from previously proposed shutdown predictors in its ability to: 1) correlate I/O operations to particular behavior of the applications and users, 2) carry prediction information across multiple executions of the applications, and 3) attain higher energy savings while incurring lower mispredictions. We perform an extensive evaluation study of PCAP using a detailed trace-driven simulation and an actual Linux implementation. Our results show that PCAP achieves lower average mispredictions and higher energy savings than the simple timeout scheme and the state-of-the-art learning tree scheme
1552056
Pama: a Fast String Matching Algorithm
String matching is a fundamental operation in computer science, and its performance has great impact on many applications including database query, text processing, DNA and protein sequence analysis. In this paper, we propose a fast string matching algorithm, PAMA (PAttern MAtching). The shift rule used by PAMA not only subsumes both the bad character rule and the good suffix rule employed by the well-known Boyer-Moore algorithm, but also employs an additional key observation to enable faster shifting during the string matching process. Theoretically, we prove that from the same alignment, the next shift of PAMA will be at least as much as that of the Boyer-Moore algorithm. Experimentally, we show that PAMA indeed significantly outperforms the original Boyer-Moore algorithm in almost all cases, and outperforms other Boyer-Moore variants such as Tuned-BM, Turbo-BM and Horspool for long patterns (length ≥ 128) or for small alphabets (size < 8).
702707
Rate-distortion analysis for H.264/AVC video coding and its application to rate control
In this paper, an efficient rate-control scheme for H.264/AVC video encoding is proposed. The redesign of the quantization scheme in H.264/AVC results in that the relationship between the quantization parameter and the true quantization stepsize is no longer linear. Based on this observation, we propose a new rate-distortion (R-D) model by utilizing the true quantization stepsize and then develop an improved rate-control scheme for the H.264/AVC encoder based on this new R-D model. In general, the current R-D optimization (RDO) mode-selection scheme in H.264/AVC test model is difficult for rate control, because rate control usually requires a predetermined set of motion vectors and coding modes to select the quantization parameter, whereas the RDO does in the different order and requires a predetermined quantization parameter to select motion vectors and coding modes. To tackle this problem, we develop a complexity-adjustable rate-control scheme based on the proposed R-D model. Briefly, the proposed scheme is a one-pass process at frame level and a partial two-pass process at macroblock level. Since the number of macroblocks with the two-pass processing can be controlled by an encoder parameter, the fully one-pass implementation is a subset of the proposed algorithm. An additional topic discussed in this paper is about video buffering. Since a hypothetical reference decoder (HRD) has been defined in H.264/AVC to guarantee that the buffers never overflow or underflow, the more accurate rate-allocation schemes are proposed to satisfy these requirements of HRD.
42676253
Synchronization of large sequential circuits by partial reset
In this paper, we present a technique to synchronize large synchronous sequential circuits, which uses partial reset to break feedback loops in the circuits such that they become synchronizable. The method also provides a synchronizing sequence. Experimental results for ISCAS'89 benchmark circuits are presented, including the largest circuits, which were not synchronized previously.
7735246
Identifying cycling genes by combining sequence homology and expression data
MOTIVATION
The expression of genes during the cell division process has now been studied in many different species. An important goal of these studies is to identify the set of cycling genes. To date, this was done independently for each of the species studied. Due to noise and other data analysis problems, accurately deriving a set of cycling genes from expression data is a hard problem. This is especially true for some of the multicellular organisms, including humans.


RESULTS
Here we present the first algorithm that combines microarray expression data from multiple species for identifying cycling genes. Our algorithm represents genes from multiple species as nodes in a graph. Edges between genes represent sequence similarity. Starting with the measured expression values for each species we use Belief Propagation to determine a posterior score for genes. This posterior is used to determine a new set of cycling genes for each species. We applied our algorithm to improve the identification of the set of cell cycle genes in budding yeast and humans. As we show, by incorporating sequence similarity information we were able to obtain a more accurate set of genes compared to methods that rely on expression data alone. Our method was especially successful for the human dataset indicating that it can use a high quality dataset from one species to overcome noise problems in another.


AVAILABILITY
C implementation is available from the supporting website: http://www.cs.cmu.edu/~lyongu/pub/cellcycle/.
16579446
Mining Correlation between Motifs and Gene Expression
One of the major challenges in the post-genomic era is to determine all DNA-binding transcription factors (TFs) and their regulatory binding sites (motifs) within the genomes. To discover the relationship between the motifs and changes in gene expression, we propose a new algorithm, co-miner (correlation miner). Correlation rules are generated based on the expression profiles of genes with significant expression change through the time course of gene expression. Thus, we may consider the change in gene expression to be causatively associated with the transcription binding sites in the upstream sequences. In addition, we introduce partition and constraint pushing techniques to improve the performance and demonstrate their effectiveness by our experiments. By applying co-miner to a yeast dataset, the relationships between motifs and gene expression revealed by co-miner are confirmed in the literature.