17056117
Integrating SNMP into a Mobile Agent Infrastructure
Mobile Code is an emerging paradigm that is gaining momentum in several fields of application. Network Management is a potential area for the use of this technology, provided it will be able to interoperate with well established solutions for Network Management. This paper presents the integration a classic NM protocol, like SNMP, into a platform of Mobile Agents. Our platform, called JAMES, has been developed in the context of an Eureka Project (Σ!1921) where the project partners are University of Coimbra, Siemens SA and Siemens AG. Since the main target of the platform is network management, it includes a set of SNMP services allowing mobile agents to easily interface with SNMP agents, as well as with legacy SNMP-based management applications. In the paper we present a brief overview of the general architecture of the platform and we describe in some detail the framework we used to provide for integration between mobile agent applications and SNMP.
11507520
Web-based Metacomputing with JET
7711926
A flexible mobile-agent framework for accessing information systems in disconnected computing environments
Over the last few years, the importance of mobile computing has been steadily increasing. While it is important to provide support for accessing databases in disconnected computing environments, many of the information systems being deployed today are using a three-tier architecture. It is becoming vital to find ways of providing reliable access to the business logic present in the middle-tier for mobile applications. The authors present a component based framework that enables client applications to send mobile agents to interact with application servers in disconnected computing environments. This framework allows the applications to benefit from the advantages of using mobile agents in disconnected computing environments, and at the same time provides integration between mobile clients and corporate information systems.
12469936
JAMES: A Platform of Mobile Agents for the Management of Telecommunication Networks
This paper presents an overview of JAMES, a Java-based platform of mobile agents that is mainly oriented for the management of data and telecommunication networks. This platform has been developed on behalf of a Eureka Project (Σ!1921) and the project partners are Siemens SA, University of Coimbra and Siemens AG. We describe the main architecture of the platform giving more emphasis to the most important features. To show the effectiveness of some of the techniques that have been implemented we will present some performance results that compare the JAMES platform with the Aglets Workbench. 
 
The main target of our platform is network management and telecommunication applications. In this line, we have done a Java-based implementation of SNMP that has been integrated within the platform. The industrial partners of our project (i.e. Siemens S.A.) have developed a prototype application for TMN performance management. Although it is still a prototype it is being used to validate the technological advantages of using mobile agents in the management of telecommunication networks.
30244538
Fault-tolerance on regular decomposition grid applications
Writing parallel applications is considerably more complex due to additional problems not found in the sequential environment. The main problems include communication, synchronization data partitioning and distribution, mapping of processes, heterogeneity and fault tolerance. Fault tolerance is a very important feature in parallel/distributed systems since the mean time between failures of the system decreases with the number of processors, and the failure of just one process(or) can lead to the crash of the entire application. This paper presents an example of a parallel library (PUL-RD) that solves most of the problems pointed out before and provides support for fault tolerance. The original version of the library offers high-level support for parallelism in a portable way and can be used to write grid-based parallel applications which have a regular decomposition. In this paper, we will describe the fault-tolerance issues that were incorporated into the PUL-RD, giving special attention to the functionality of the checkpointing scheme.<<ETX>>
9570610
Towards Manageable Mobile Agent Infrastructures
This paper addresses the problem of managing distributed mobile agent infrastructures. First, the weaknesses of current mobile agent implementations will be discussed and identified from the manageability viewpoint. The solutions devised and experimented in order to alleviate these weaknesses in our own agent platform will then be presented. These solutions are generic and could easily be applied to the majority of existing mobile agent implementations. The paper will finish with the discussion of a new approach we are following in the M&M Project, based on a rather different architecture that significantly reduces the manageability requirements.
10991338
Variation-Aware, Library Compatible Delay Modeling Strategy
Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation
16788771
Efficient Computation of the Worst-Delay Corner
Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.
528194
Algorithms for solving Boolean satisfiability in combinational circuits
Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.
16534842
Formal Verification of Component-Based Software Systems
In this work we present a methodology for formal modeling and verification of component based software systems. The methodology is based on software architecture, components, and reuse of Petri Nets models. With this process, we are contributing for the visual composition, verification, and formal validation of software. We also show an example of the application of this methodology into two different domains.
9436195
Satisfiability models and algorithms for circuit delay computation
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay computation, accounting for false paths, as a sequence of instances of Boolean satisfiability. Several path sensitization models and delay models are studied. In addition we evaluate some of the most competitive Boolean satisfiability algorithms seeking to identify which are best suited for solving circuit delay computation problems. Finally, realistic delay modeling (taking into account extracted interconnect delays and fanout data) is considered in order to experimentally evaluate the complexity of solving real-world instances.