25434953
A data-centric approach to checksum reuse for array-intensive applications
Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive components. While many systems implement hardware-based protection techniques like ECC and other approaches to ensure an acceptable level of robustness against these errors, such solutions are generally very rigid and costly. Recent research discussed checksum-based software solutions that can be used in the context of array-intensive computations. While a checksum-based scheme can be more flexible than a hardware-based approach to reliability, it can also bring significant runtime overheads. Focusing on array-intensive applications, this paper proposes a compiler-directed data-centric strategy that maximizes reuse of checksums. A unique characteristic of the proposed scheme is that it can work with a given checksum assignment, and automatically - under compiler guidance - restructures the entire application code to maximize checksum reuse. This scheme can reduce checksum recomputing even further by inter-procedural checksum reuse. Our experiments clearly show that the proposed approach reduces the number of checksum calculations required by the previous work.
1915474
Runtime integrity checking for inter-object connections
Ensuring integrity of heap resident data is critical for many embedded systems. Ever-scaling process technology combined with power-saving techniques employed in embedded systems is increasing vulnerability of such systems to hardware-related errors such as soft errors. While such errors are transient and do not harm the architecture, they can corrupt data. In this study, we explore solutions to the inter-object connectivity problem in heap memory of Java-based embedded environments. Our objective is to ensure that the connections between the objects are consistent. In particular, we want to detect the cases where an inter-object link disappears or points to a wrong object. To address this problem, we propose a rule based approach, where the application programmer expresses the important connectivity rules to be satisfied using a special rule language, and a modified JVM (Java virtual machine) checks these rules at runtime.
15399936
Compiler-guided leakage optimization for banked scratch-pad memories
Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.
37185470
An ILP-Based Approach to Locality Optimization
One of the most important factors that determine performance of data-intensive applications is data locality. A program with high data locality makes better use of fast, on-chip memories and can avoid large main memory latencies. Although previous compiler research investigated numerous techniques for enhancing locality, we lack of formal techniques, against which the existing heuristics can be compared. Motivated by this observation, this paper presents a fresh look at locality optimization based on integer linear programming (ILP). We formulate the conditions for data locality, and present a system of constraints whose solution gives optimal computation re-ordering and data-to-memory assignment under our objective function and cost model. Our experimental results using three data-intensive applications clearly indicate that the ILP-based approach generates very good results and outperforms a previously proposed heuristic solution to locality.
525351
Memory Space Conscious Loop Iteration Duplication for Reliable Execution
Soft errors, a form of transient errors that cause bit flips in memory and other hardware components, are a growing concern for embedded systems as technology scales down. While hardware-based approaches to detect/correct soft errors are important, software-based techniques can be much more flexible. One simple software-based strategy would be full duplication of computations and data, and comparing the results of the corresponding original and duplicate computations. However, while the performance overhead of this strategy can be hidden during execution if there are idle hardware resources, the memory demand increase due to data duplication can be dramatic, particularly for array-based applications that process large amounts of data. 
 
Focusing on array-based embedded computing, this paper presents a memory space conscious loop iteration duplication approach that can reduce memory requirements of full duplication (of array data), without decreasing the level of reliability the latter provides. Our “in-place duplication” approach reuses the memory locations from the same array to store the duplicates of the elements of a given array. Consequently, the memory overhead brought by the duplicates can be reduced. Further, we extend this approach to incorporate “global duplication”, which reuses memory locations from other arrays to store duplicates of the elements of a given array. This paper also discusses how our approach operates under a memory size constraint. The experimental results from our implementation show that the proposed approach is successful in reducing memory requirements of the full duplication scheme for twelve array-based applications.
1582700
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. The advantage of placing multiple cores into a single die is that it reduces on-chip communication costs (in terms of both execution cycles and power consumption) between the processor cores that are traditionally very high in conventional high-performance parallel architectures (such as SMPs). However, on the negative side, this tighter integration exerts an even higher pressure on off-chip accesses to the memory system. This makes minimizing the number of off-chip accesses a critical optimization goal.This paper discusses a compiler-based solution to this problem for the embedded applications that perform stencil computations. An important characteristic of this solution is that it distinguishes between the intra-processor data reuse and inter-processor data reuse. The first of these captures the data reuse that occurs across loop iterations assigned to the same processor, whereas the second one represents the data reuse that takes place across the loop iterations assigned to different processors. The proposed approach then optimizes inter-processor reuse by re-organizing the loop iterations of each processor carefully, considering how data elements are shared across processors. The goal is to ensure that the different processors access the shared data within a short period of time, so that the data can be captured in the on-chip memory space at the time of the reuse. This paper also presents an evaluation of the proposed optimization and compares it to an alternate scheme that optimizes data locality for each processor in isolation. The results obtained by applying our implementation to eight loop-intensive benchmark codes from the embedded computing domain show that our approach improves over the mentioned alternate scheme by 15.6% on average.
6244297
A layered communication system generator
Abstract Although many approaches have been proposed for modeling and automatically validating communication protocol entities, no approaches have been proposed for automatically implementing various layered communication systems. In the article, we propose a layered communication system generator that can automatically implement various layered communication systems. The layered communication system generator is established on the basis of a generalized communication system framework. In addition, a layered communicating finite state machine is introduced to specify the layered communication systems, and a matrix approach is proposed for protocol validation. We have implemented the proposed layered communication system generator in DOS and UNIX environments, in which several real-world protocols from Department of Defense and IEEE 802 standards organizations have been successfully developed.
207117262
Using Memory Compression for Energy Reduction in an Embedded Java System
The Java programming language is being increasingly used for application development for mobile and embedded devices. Limited energy and memory resources are important constraints for such systems. Compression is an useful and widely employed mechanism to reduce the memory requirements of the system. As the leakage energy of a memory system increases with its size and because of the increasing contribution of leakage to overall system energy, compression also has a significant effect on reducing energy consumption. However, storing compressed data/instructions has a performance and energy overhead associated with decompression at runtime. The underlying compression algorithm, the corresponding implementation of the decompression and the ability to reuse decompressed information critically impact this overhead. In this paper, we explore the influence of compression on overall memory energy using a commercial embedded Java virtual machine (JVM) and a customized compression algorithm. Our results show that compression is effective in reducing energy even when considering the runtime decompression overheads for most applications. Further, we show a mechanism that selectively compresses portions of the memory to enhance energy savings. Finally, a scheme for clustering the code and data to improve the reuse of the decompressed data is presented.
5706395
Combinatorial Properties of Generalized Hypercube Graphs
This paper investigates combinatorial properties of generalized hypercube graphs including best containers, wide diameter, and fault diameter. These properties have received much attention recently in the study of interconnection networks.
13201367
Generalized Diameters of the Mesh of Trees
Abstract
The mesh of trees, which owns two favorable properties, small diameter and large bisection,
is known as the fastest network when considered in terms of speed. In this paper we show that
the wide diameter, fault diameter and Rabin number, which are three generalizations of diameter,
of a two-dimensional 2n×2n mesh of trees are equal to 5n + 1.


5559036
Dynamic compilation for energy adaptation
While previous compiler research indicates that significant improvements in energy efficiency may be possible if properly optimized code is used, the energy constraints under which a given application code should be optimized may not always be available at compile-time. More importantly, these constraints may change dynamically during the course of execution. In this work, we present a dynamic recompilation/linking framework using which the energy behavior of a given application can be optimized while the application is being executed. Our preliminary experiments indicate that large energy gains are possible through dynamic code recompilation/linking at the expense of a relatively small increase in execution time.