10935949
A time-division algorithm for parallel simulation
Most parallel simulation algorithms (e.g., Chandy and Misra’s algorithm or the Time Warp algorithm) are based on a “space-division” approach. The parallelism of this approach is limited by the causality constraints. Another approach, the “time-division” approach, may provide more parallelism if the time domain is appropriately partitioned. We present a time-division parallel simulation algorithm that partitions the time domain via state matching, We show that linear speed up can be achieved. For a complex system, the best parallel simulation approach is to integrate “time-division” and “space-division” algorithms: the simulated system is partitioned into several subsystems; a subsystem may be simulated by the time-division approach (e. g., our algorithm), while the overall system is simulated by the space-division approach.
22500122
Performance of hot billing mobile prepaid service
Abstract Prepaid service has become an important mobile application with rapid growth for subscription rate in the recent years. Implementation of prepaid service may generate large network traffic that significantly affects the performance of a mobile network. This paper studies the hot billing solution for prepaid service. We investigate how the amount of prepaid credit and the frequency of call detail record (CDR) transmissions affect network signaling and potential bad debt that a service provider may bear. Our study suggests that a prepaid service provider should encourage customers to buy large prepaid credits by giving them discounts. Furthermore, based on call traffic, an optimal CDR transmission frequency can be found by using our modeling technique.
16848330
A flexible graphical user interface for performance modeling
We identify three goals for the graphical user interface (GUI) of a network simulation environment: user friendliness, model re-usability, and application extensibility. We address the user friendliness issue by proposing a simple yet efficient approach to setup parameters for the simulation models. We address the application extensibility issue by a two-layer GUI architecture. The two layers are loosely-coupled, and the first layer can be easily replaced (without affecting the other components of the simulation environment). We address the model re-usability issue by subnetworks. Unlike most existing simulation packages where subnetwork is simply a method to group the nodes, the subnetwork construct in our approach is an integral part of the simulation environment (i.e., all operations for a basic node also apply to a subnetwork). The port concept is used to explicitly define the I/O relationship between a subnetwork and the outside world. Parameter dialog boxes are used to set up the parameters for a subnetwork conveniently. Finally, a simple stack mechanism is proposed to measure subnetwork-wide output statistics.<<ETX>>
2805042
A new random walk model for PCS networks
This paper proposes a new approach to simplify the two-dimensional random walk models capturing the movement of mobile users in personal communications services (PCS) networks. Analytical models are proposed for the new random walks. For a PCS network with hexagonal configuration, our approach reduces the states of the two-dimensional random walk from (3n/sup 2/+3n-5) to n(n+1)/2, where n is the layers of a cluster. For a mesh configuration, our approach reduces the states from (2n2-2n+1) to (n/sup 2/+2n+4)/4 if n is even and to (n/sup 2/+2n+5)/4 if n is odd. Simulation experiments are conducted to validate the analytical models. The results indicate that the errors between the analytical and simulation models are within 1%. Three applications (i.e., microcell/macrocell configuration, distance-based location update, and GPRS mobility management for data routing) are used to show how our new model can be used to investigate the performance of PCS networks.
16744149
Performance Analysis for Dual Band PCS Networks
In a dual band personal communications services (PCS) network, heavy traffic areas are covered by microcells which overlay macrocells. In such a network, microcells and macrocells utilize different frequency bands. We propose an analytic model to study the performance of a dual band PCS architecture. Our model assumes that a PCS subscriber has a general residence time distribution in a microcell and the macrocell residence time distribution is derived from the microcell residence time distribution. An iterative algorithm is used to compute the overflow traffic from a microcell to its overlaid macrocell. Then, the call incompletion probability is computed by a macrocell model based on the overflow traffic. Our study indicates that the variance of the microcell residence time distribution and the number of microcells covered by a macrocell have significant effects on the call incompletion probability.
5110930
A comparison study of the two-tier and the single-tier personal communications services systems
A two-tier PCS system integrates the high tier PCS system and the low tier PCS systems into a single system to provide the advantages of both tiers. Such a system is expected to provide better service (more available and more cost effective to the users) at the expense of the extra tier switching management. We compare the performance of the two-tier PCS system and the single low tier system in two aspects: the registration traffic and the service availability. Because of the tier management, the two-tier system generates more registration traffic than the single low tier system. Under the range of the input parameters in our study, we show that the two-tier system generates less than 10% extra registration traffic than the single low tier system in most cases and generates less than 20% registration traffic in the worst cases. It is clear that for the service availability, the two-tier system is better than the single one tier system. We also study the probability that a call is forced terminated in the single low tier system because the low tier becomes unavailable during the call (such a call can be continued in the two-tier system).
15077607
A transformation-based method for loop folding
We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported. >
26702573
Evolution and Evaluation of Internet Content Delivery
Discover the methods for content delivery and distribution of Web-based media in the Web 2.0 world. The concept of Web caches has existed as long as the Web and evolved from storage of frequently accessed files on an individual's personal computer or proxy server to Internet-based Web cache servers provided by companies as a paid subscription service for content providers. As multimedia has become more prevalent on the Web, content delivery networks (CDNs) have become a critical component of the Internet and an enabler of Web 2.0 applications like IPTV, mobile Web and TV devices, and content-rich Web databases such as Wikimedia.
14489226
A performance-driven standard-cell placer based on a modified force-directed algorithm
We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudo net is added to link the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified I/O pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move a cell to its force-balanced location assuming all other cells are fixed. The process stops when no cell can be moved farther than a threshold distance. Next, cell rows are adjusted one at a time starting from the top and bottom. After forming these two rows (top/bottom), all movable core cells force-balanced locations are updated. The row-formation-and-update process continues until all rows are adjusted and, hence, a legal placement is obtained.
 We have integrated the proposed approach into an industrial APR flow. Experimental results on benchmark circuits up to 191K-cell (500K-gate) show that the critical path delay can be improved by as much as 11.5%. We also study the effect on both layout quality and CPU time consumption due to the amount of pseudo net added. We found that the introduction of pseudo net indeed significantly improves the layout quality.
28386887
New Systolic Arrays for the Longest Common Subsequence Problem
Abstract New systolic arrays are presented to solve the longest common subsequence (LCS) problem. The first array is based on a previous work to compute the length of an LCS. The second array improves on the first one. The second array is about 1 4 faster than the first array, and each processing element (PE) of the second array requires one less port for both input and output to transfer one less value. Either of the two arrays can be equipped with a content-addressable memory in each PE to recover an LCS. The resulting array requires fewer steps than the previously proposed one.
16924532
Expansion of layouts of complete binary trees into grids
Let Th be the complete binary tree of height h. Let M be the infinite grid graph with vertex set Z2, where two vertices (x1, y1) and (x2, y2) of M are adjacent if and only if |x1-x2| + |y1-y2|= 1. Suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of M. Motivated by issues in optimal VLSI design, we show that the point expansion ratio n(T)/n(Th) = n(T)/(2h+1 - 1) is bounded below by 1.122 for h sufficiently large. That is, we give bounds on how many vertices of degree 2 must be inserted along the edges of Th in order that the resulting tree can be laid out in the grid. Concerning the constructive end of VLSI design, suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of the n × n grid graph. Define the expansion ratio of such a layout to be n2/n(Th)=n2/(2h+1 - 1). We show constructively that the minimum possible expansion ratio over all layouts of Th is bounded above by 1.4656 for sufficiently large h. That is, we give efficient layouts of complete binary trees into square grids, making improvements upon the previous work of others. We also give bounds for the point expansion and expansion problems for layouts of Th into extended grids, i.e. grids with added diagonals.