57256946
Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
An efficient mechanism to track and enforce memory dependences is crucial to an out-of-order microprocessor. The conventional approach of using cross-checked load queue and store queue, while very effective in earlier processor incarnations, suffers from scalability problems in modern high-frequency designs that rely on buffering many in-flight instructions to exploit instruction-level parallelism. In this paper, we make a case for a very different approach to dynamic memory disambiguation. We move away from the conventional exact disambiguation strategy and adopt an opportunistic method: we allow loads and stores to access an L0 cache as they are issued out of program order, hoping that with such a laissez-faire approach, most loads actually obtain the right value. To guarantee correctness, they execute a second time in program order to access the nonspeculative L1 cache. A discrepancy between the two executions triggers a replay. Such a design completely eliminates the necessity of real-time violation detection and thus avoids the conventional approach's complexity and the associated scalability issue. We show that even a simplistic design can provide similar performance level achieved with a conventional queue-based approach with optimisticallysized queues. When simple, optional optimizations are applied, the performance level is close to that achieved with ideally-sized queues.
6607773
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-order execution of memory instructions. Traditional CAM-based associative queues can be very slow and energy hungry. In this paper we introduce two new management schemes. The first one is a filtering scheme based on simple age-tracking. This scheme can easily avoid 95-98% of associative load queue (LQ) searches using only a few registers. This translates into significant power savings. More importantly, however, this filtering makes our second scheme, delayed memory dependence checking (DMDC), practical. With a small hash table, DMDC completely avoids the need for an associative LQ and relies on indexing-based checking at the commit phase and hence cuts the energy spent on LQ by an average of 95%. At an average of about 0.3%, the performance impact is negligible. When the energy cost of the increased execution time is factored in, the processor still makes net energy savings of about 3-8%, depending on the configuration and the applications
7442937
SEED: Scalable, efficient enforcement of dependences
Instruction issue logic is a critical component in modern high-performance out-of-order processors. The ever increasing latencies found in modern processors, mostly associated with memory accesses and longer pipelines, can be attenuated using large issue queues. Conventional designs rely on atomic wakeup-select cycles to ensure compact scheduling. These designs must aggressively utilize broadcasting, compaction, and heavily-ported structures that scale poorly in terms of both power consumption and access time. To provide high scheduling flexibility and large instruction capacity without incurring prohibitive latency and energy overhead, we propose a novel scheme that uses an out-of-order, broadcast-free instruction wakeup block feeding an in-order scheduler. Multi-banked, index-based structures are used throughout this scheme to provide a high degree of scalability while achieving efficient dependence tracking, resulting in good overall performance and energy efficiency. We call this design "Scalable, Efficient Enforcement of Dependences (SEED)". We present a detailed design and analysis of SEED through an extensive evaluation. Compared to a conventional issue queue design, which is assumed favorably to scale in size without any impact on cycle time, the performance degradation of our design is 3% for both INT and FP suites of SPEC CPU2000. For such a small performance cost, SEED enjoys a 19% reduction in total chip power consumption for a 32-entry configuration. We also synthesize SEED and a conventional issue logic with 90nm standard cell logic. Synthesis results show that SEED can cycle twice the speed of a conventional issue logic of equivalent size. Cycling at the same frequency, SEED consumes ten times less dynamic power and five times less static power while achieving substantial area savings.
31549238
Online Animated Graph Drawing for Web Navigation
This paper describes an online animated graph drawing method. The method deals with huge graphs which are partially unknown. It is instantiated in OFDAV, a web diagram visualizer.
2042207
Hybrid Authentication and Key Management Scheme for WSANs
Wireless Sensor and Actor Networks (WSANs) consist of three types of nodes with different capabilities and functions. Because of these heterogeneities, current network security mechanisms would be hard to satisfy the security/cost requirements of all types of nodes. In this paper, we propose an integrated security approach, called Hybrid Security Scheme (HSS). It splits a WSAN into two layers, the sink-actor layer and the actor-sensor layer, according to nodes’ functionalities and capacities. Different security mechanisms are provided to achieve the security services at corresponding levels. Furthermore, an adaptive switching mechanism is provided to satisfy the dynamic topology of network, and several methods are also used to reduce the system costs.
34980398
Efficient Checkers for Number-Theoretic Computations
Blum has recently proposed a new approach to the problem of program correctness, the program checker. Here, efficient program checkers are presented for two important number theory problems, integer GCD and modular exponentiation. The former result answers an open problem posed by Blum. The latter result paves the way for more robust cryptographic programs, as modular exponentiation is the basis for several cryptosystems. Taken together, these results lay the foundation for more reliable number-theoretic programs.
40799553
Function Field Sieve Method for Discrete Logarithms over Finite Fields
We present a function field sieve method for discrete logarithms over finite fields. This method is an analog of the number field sieve method originally developed for factoring integers. It is asymptotically faster than the previously known algorithms when applied to finite fields Fpn, where p6?n.
29173670
Dynamic Visualization of Spatially Referenced Information
This paper proposes a dynamic visualization approach that combines the graph metaphor and the spatial metaphor for visualizing and navigating spatially referenced data. It provides users with a “marching” scheme for viewing a series of graphs G1, G2, ... Gn that are related to a spatial map. Moreover, It provides three types of navigation mechanisms. This dynamic visualization can facilitate the processes of spatially referenced data mining.