86206
Wire length prediction-based technology mapping and fanout optimization
In modern VLSI systems early wire optimization is essential in achieving required performance, routability, and power. The cost functions optimized during traditional logic synthesis do not capture interconnect effects, which may lead to sub-optimal designs. In this paper, we propose a method for applying pre-layout wire-length prediction techniques in logic synthesis, targeting wiring cost and ways to minimize congestion. Specifically, we focus on technology mapping and fanout optimization. Experimental results show that our wire-length-prediction-based technology mapping (WP-Map) and fanout optimization (WP-Fanout) result in 8.7% improvement in average congestion, 17.2% improvement in peak congestion, and 3.3% improvement in timing performance.
17618621
Semi-individual wire-length prediction with application to logic synthesis
A new concept for wire-length prediction, the semi-individual wire-length prediction, is introduced. Structural metrics, such as mutual contraction and net range, are used to predict which interconnects have a tendency to be long or short in the final layout. The very good correlation of the prelayout measures with the postlayout interconnect lengths is demonstrated. The prelayout wire-length-prediction techniques are applied in logic synthesis, targeting wiring cost, and congestion minimization. This paper focuses on technology mapping and fan-out optimization. Experiments on LGSyn93 and ITC'99 benchmark suites show that the wire-length-prediction-based technology mapping and fan-out-optimization algorithms produce layout-friendly netlists. After placement and global routing, the netlists yield smaller total wire length, are more routable, and achieve better timing than the netlists obtained using traditional logic-synthesis flow in SIS.
47092078
A study of netlist structure and placement efficiency
In this paper, we examine the relationship between netlist structure and the efficiency of placers measured in terms of quality and stability of results. We analyze three types of placers: analytic, simulated-annealing based, and partition based. We have tested these placers on industrial and synthetic benchmarks. Based on our observations and analyzes of experimental results, we draw several useful conclusions: 1) Various placers favor netlists with different structural characteristics; 2) placement efficiency correlates with interconnection complexity of the circuits; 3) global nets increase the effort to eliminate overlaps of cells and degrade the efficiency of analytic placers; and 4) global nets can improve placement stability of partition-based placers.
10460404
Pre-layout wire length and congestion estimation
In this paper, we study the pre-layout wire length and congestion estimation. We find that two structural metrics, mutual contraction and net range, can be used to predict wire lengths. These metrics have different application ranges and complement each other. We also propose a new metric, the structural pin density, to capture the peak routing congestion of designs. Larger maximum pin densities usually lead to larger peak congestions in circuits with similar average congestions. We demonstrate experimentally very good correlation of our pre-layout measures with post layout interconnect lengths. We also isolate the structural netlist properties which cause the peak congestion.
15497881
A congestion-driven placement framework with local congestion prediction
In this paper, we present a novel congestion-driven placement methodology. We analyze netlist structure and perform local congestion prediction to determine the amount of white space which will be attached to each cell. We place the modified netlist using a total-wire-length-driven placer and obtain an initial legal placement. We extract the congestion information and determine the target white space distribution. Finally, we apply placement migration, an incremental placement technique, to transform the initial placement into a placement which satisfies the target white space distribution. We provide experimental data to demonstrate the effectiveness of our congestion driven placement framework. Compared with the recent academic routability-driven placer Dragon [12], we achieve significant routability improvements in much shorter cpu run time.
8945696
Synthesis and placement flow for gain-based programmable regular fabrics
In this paper we present the Gain-based Logic Block Array (GLA), a new via-programmable regular fabric. GLA is an array of Gain-based Logic Blocks (GLBs). The GLB is a semi-universal logic block designed based on logical effort theory[12]. Customization of the GLBs is provided by programmable vias. To achieve the best performance, appropriate fabric has to be selected from a family of GLAs with different performance-area trade-offs. We describe a synthesis and placement flow which, for a given design to be implemented, allows us to select the best GLA from the candidate family.
8754175
Summarizing level-two topological relations in large spatial datasets
Summarizing topological relations is fundamental to many spatial applications including spatial query optimization. In this article, we present several novel techniques to effectively construct cell density based spatial histograms for range (window) summarizations restricted to the four most important level-two topological relations: contains, contained, overlap, and disjoint. We first present a novel framework to construct a multiscale Euler histogram in 2D space with the guarantee of the exact summarization results for aligned windows in constant time. To minimize the storage space in such a multiscale Euler histogram, an approximate algorithm with the approximate ratio 19/12 is presented, while the problem is shown NP-hard generally. To conform to a limited storage space where a multiscale histogram may be allowed to have only k Euler histograms, an effective algorithm is presented to construct multiscale histograms to achieve high accuracy in approximately summarizing aligned windows. Then, we present a new approximate algorithm to query an Euler histogram that cannot guarantee the exact answers; it runs in constant time. We also investigate the problem of nonaligned windows and the problem of effectively partitioning the data space to support nonaligned window queries. Finally, we extend our techniques to 3D space. Our extensive experiments against both synthetic and real world datasets demonstrate that the approximate multiscale histogram techniques may improve the accuracy of the existing techniques by several orders of magnitude while retaining the cost efficiency, and the exact multiscale histogram technique requires only a storage space linearly proportional to the number of cells for many popular real datasets.
3992721
Error minimization in approximate range aggregates
Histogram techniques have been used in many commercial database management systems to estimate a query result size. Recently, it has been shown that they are very effective to support approximation of query processing especially aggregates. In this paper, we investigate the problem of minimizing average errors of approximate aggregates using histogram techniques. Firstly, we present a novel linear-spline histogram model that is more accurate than the existing models. Secondly, we propose a novel histogram construction technique for minimizing such average errors, which is shown to generate a near optimal histogram. Our experiment results demonstrate that the new histogram construction techniques lead to a great accuracy improvement on the existing techniques.
5635390
Image Complexity and Feature Extraction for Steganalysis of LSB Matching Steganography
In this paper, we present a scheme for steganalysis of LSB matching steganography based on feature extraction and pattern recognition techniques. Shape parameter of generalized Gaussian distribution (GGD) in the wavelet domain is introduced to measure image complexity. Several statistical pattern recognition algorithms are applied to train and classify the feature sets. Comparison of our method and others indicates our method is highly competitive. It is highly efficient for color image steganalysis. It is also efficient for grayscale steganalysis in the low image complexity domain
12061046
Parsing the Penn Chinese Treebank with Semantic Knowledge
We build a class-based selection preference sub-model to incorporate external semantic knowledge from two Chinese electronic semantic dictionaries. This sub-model is combined with modifier-head generation sub-model. After being optimized on the held out data by the EM algorithm, our improved parser achieves 79.4% (F1 measure), as well as a 4.4% relative decrease in error rate on the Penn Chinese Treebank (CTB). Further analysis of performance improvement indicates that semantic knowledge is helpful for nominal compounds, coordination, and N⋄V tagging disambiguation, as well as alleviating the sparseness of information available in treebank.
14783314
Ontology Capture Based on Granular Computing
Ontology capture is a key topic in constructing an ontology, and it is a procedure of knowledge acquisition. In this paper, by applying the principle of granular computing, some concepts about information granules, including domain feature information granule, domain object information granule, were defined, the context of the domain ontology may be granulated. A domain granule and a domain granule lattice were presented. An algorithm of generating the domain granule lattice was proposed, and was illustrated by a real example. With the domain granule lattice, ontology capture can be fulfilled. Therefore, granular computing should be of great help in representing and constructing an ontology