1984219
Incorporation of input glitches into power macromodeling
Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glitches, which are generated by the previous stage of circuitry. In this paper, we investigate the impact of input glitches on the power dissipation of a circuit. Specifically, we show that the frequency and average duration of input glitches are two important factors affecting the overall power consumption. Input glitches can also increase output glitching by a surprisingly large amount. We present a simple yet effective analytical power macromodeling approach incorporating the effects of input glitching. In experiments with ISCAS-85 benchmark circuits, the average error of the proposed technique is 4.44%.
10662727
Power macromodeling of global interconnects considering practical repeater insertion
In this paper, we present a simple yet highly effective power macromodeling technique for global interconnects that considers optimal repeater insertion. Specifically,our model estimates the interconnect power dissipation from the interconnect length, the timing budget, the repeater location flexibility, and the signal activity using an analytical function that is derived for a given repeater library and fabrication technology. In experiments with different standard cell libraries, the average error of our technique is less than 2%.
26613748
A Markov chain sequence generator for power macromodeling
In this paper, we present a novel sequence generator based on a Markov chain model. Specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. We also give a practical heuristic that computes such a matrix and generates a sequence of l n-bit vectors in O(nl + n/sup 2/) time. Derived from a strongly mixing Markov chain, our generator yields binary vector sequences with accurate statistics, high uniformity, and high randomness. Experimental results show that our sequence generator can cover more than 99% of the parameter space. Sequences of 2,000 48-bit vectors are generated in less than 0.05 seconds, with average deviations of the signal statistics p, d, and s equal to 1.6%, 1.8%, and 2.8%, respectively. Our generator enables the detailed study of power macromodeling. Using our tool and the ISCAS-85 benchmark circuits, we have assessed the sensitivity of power dissipation to the three input statistics p, d, and s. Our investigation reveals that power is most sensitive to transition density, while only occasionally exhibiting high sensitivity to signal probability and spatial correlation. Our experiments also show that input signal imbalance can cause estimation errors as high as 100% in extreme cases, although errors are usually within 25%.
17545097
Design of Rotary Clock Based Circuits
Rotary clock technique has been shown to reduce the power dissipation of clock distribution by up to 80%. However, to our knowledge, no practical digital synchronous circuit has been designed that utilizes the rotary technique due to the multi-phase nature of rotary clock signals and the strong coupling between a rotary clock network and the circuit it drives. In this paper, we make the first attempt to design rotary based circuit by proposing a unified clock and circuit design methodology. Given a sequential circuit and a clock frequency, our scheme derives a rotary clock network and a functionally equivalent circuit so that they can be integrated to operate reliably at the target frequency. We have applied our scheme to design several rotary clock based DSP modules. Simulation results show that all designs operate correctly with no timing violation. Compared with designs using conventional clock trees, our designs achieve an average clock power saving of more than 70%.
13241066
Retiming and clock scheduling for digital circuit optimization
This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are explored: (1) clock period minimization and (2) tolerance maximization to clock-signal delay variations. Exact mixed-integer linear programming formulations and efficient heuristics are given for both problems. When both long and short paths are considered, circuits optimized by the combined application of retiming and clock scheduling can achieve shorter clock periods or demonstrate greater tolerance to clock-signal delay variations than circuits optimized by retiming or clock scheduling. Experiments with benchmark circuits demonstrate the effectiveness of the combined optimization. In comparison with the best result obtained by either of the two optimizations, the joint application of retiming and clock scheduling increased operating speeds by more than 8% on the average. It also increased tolerance to clock delay variations by an average of 12% over a broad range of target clock frequencies. Larger relative improvements were achieved for shorter clock periods, thus suggesting that simultaneous retiming and clock scheduling can play an important role in high-speed design.
5855159
Skew spreading for peak current reduction
This paper presents a circuit optimization technique called skewspreading. Given an edge-triggered sequential circuit, skew spreadingderives the required clock arrival times for all registers so that theskews are distributed evenly in a preselected time window without changing the operating frequency of the circuit. Skew spreading is ideal for peak current reduction, since it distributes clock activities and the ensuing signal activities widely in time. We have developed a skew spreading algorithm and applied it to a suite of benchmark circuits. Simulation results demonstrate that the variance of the resulting skew from the uniform distribution can be reduced to 4% on the average. In comparison to other gate-level peak current reduction techniques, our scheme achieves an average improvement of 17% with a speedup of up to 13.9 times.
9910585
Video based human animation technique
Human animation is a challenging domain in computer animation. To aim at many shortcomings in conventional techniques, this paper proposes a new video based human animation technique. Given a clip of video, firstly human joints are tracked with the support of Kalman filter and morph-block based match in the image sequence. Then corresponding sequence of three-dimension (3D) human motion skeleton is constructed under the perspective projection using camera calibration and human anatomy knowledge. Finally a motion library is established automatically by annotating multiform motion attributes, which can be browsed and queried by the animator. This approach has the characteristic of rich source material, low computing cost, efficient production, and realistic animation result. We demonstrate it on several video clips of people doing full body movements, and visualize the results by re-animating a 3D human skeleton model.
368408
A framework for opportunistic scheduling in wireless networks
Abstract We present a method, called opportunistic scheduling, for exploiting the time-varying nature of the radio environment to increase the overall performance of the system under certain quality of service/fairness requirements of users. We first introduce a general framework for opportunistic scheduling, and then identify three general categories of scheduling problems under this framework. We provide optimal solutions for each of these scheduling problems. All the proposed scheduling policies are implementable online; we provide parameter estimation algorithms and implementation procedures for them. We also show how previous work by us and others directly fits into or is related to this framework. We demonstrate via simulation that opportunistic scheduling schemes result in significant performance improvement compared with non-opportunistic alternatives.
7819313
Constrained Fairing for Meshes
In this paper, we present a novel fairing algorithm for the removal of noise from uniform triangular meshes without shrinkage and serious distortion. The key feature of this algorithm is to keep all triangle centers invariant at each smoothing step by including some constraints in the energy minimization functional. The constrained functional is then minimized efficiently using an iterative method. Further, we apply this smoothing technique to a multiresolution representation to remove arbitrary levels of detail. A volume-preserving decimation algorithm is presented to generate the multiresolution representation. The experimental results demonstrate the combined algorithm's stability and efficiency.
65741
WebDG - A Platform for E-Government Web Services
Web services are deemed as the natural choice for deploying e-government applications. Their use enables e-government to fully get advantage of the envisioned Semantic Web. In this paper, we propose WebDG, a comprehensive Web Service Management System for e-government applications. It aims to improve government-citizen interactions through an infrastructure built around the ”life experience” of citizens. WebDG provides a framework for automatically composing e-government services, optimized querying services, and preserving privacy.
292448
Efficient Network Utilization for Multimedia Wireless Networks
In this paper, we present an access scheme to satisfy the QoS requirements for two classes of traffic during the contention phase of packet-switched wireless communications. In the proposed scheme, difierent classes of users contend with other users for resources based on controlled class-dependent permission probabilities. We prove that our algorithm is stable for a large class of arrival processes. Under certain QoS requirements, we derive an upper-bound on the throughput for a general class of random access algorithms. We show that the throughput of our algorithm asymptotically approaches this upper-bound. We also show, through numerical examples, that our algorithm achieves high network utilization.