31231657
Understanding and addressing the noise induced by electrostatic discharge in multiple power supply systems
The design of on-chip ESD protection has become increasingly difficult and critical because of shrinking device feature sizes, high operating speed, and system on a chip (SoC) environments. A complex ESD protection network in an SoC can cause the degradation of circuit performance during normal operation. The loss introduced by ESD stress and protection networks is defined as ESD noise. In this paper, we present the generation and characterization of three different types of noise induced by ESD. The effect of ESD protection networks on sensitive circuits is investigated with a test chip processed in a 0.18 /spl mu/m CMOS technology. Experimental results suggest appropriate optimization of a tradeoff between ESD robustness and power supply coupling. It is important to note that, for mixed-signal design, the performance of a sensitive circuit is highly dependent on the ESD noise generated in the vicinity of the sensitive circuit, as well as circuit design techniques.
13489029
An integrated approach to realistic worst-case design optimization of MOS analog circuits
The authors present a new integrated approach for the optimization of MOS analog circuit performance by using realistic worst-case device parameter files, each corresponding to a performance measure. Nonlinear response surfaces are constructed for the performance measures of interest, and the worst-case device parameter files are identified by solving a set of suitably cast nonlinear programming problems. The worst-case files are shown to depend on the values of the designable parameters. An efficient method of incorporating this dependence during worst-case design optimization has been developed. This method enables the design of circuits with optimal performance and high parametric yields. Some illustrative analog circuit examples are given to demonstrate the application of the worst-case design optimization procedure.<<ETX>>
13548202
Noise constrained power optimization for dual V/sub T/ domino logic
In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
14376041
Feasible region approximation using convex polytopes
A new technique for polytope approximation of the feasible region for a design is presented. This method is computationally less expensive than the simplicial approximation method. Results on several circuits are presented. It is shown that the quality of the polytope approximation is substantially better than an ellipsoidal approximation.<<ETX>>
40491047
Domino logic synthesis based on implication graph
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3%.
44275614
Cell-level placement for improving substrate thermal distribution
The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.
16869035
An approach to virtual allocation in storage systems
This article presents virtual allocation, a scheme for flexible storage allocation. Virtual allocation separates storage allocation from the file system. It employs an allocate-on-write strategy which lets applications fit into the actual usage of storage space, without regard to the configured file system size. This improves flexibility by allowing storage space to be shared across different file systems. This article presents the design of virtual allocation and its evaluation through benchmarks. To illustrate our approach, we implemented a prototype system on PCs running Linux. We present the results from the prototype implementation and its evaluation.
6698506
Multi-layer active queue management and congestion control for scalable video streaming
Video streaming is becoming an increasingly important part of the present Internet. To guarantee a high-quality streaming environment to end users, many video applications require a strict form of network QoS that is not available in the present Internet. Thus, to supplement the best-effort model of existing networks, we study a new video streaming framework that allows applications to mark their own packets with different priority and use multiqueue congestion control inside routers to effectively drop the less-important packets during buffer overflows. We describe priority AQM algorithms that provide "optimal" performance to video applications under arbitrary network loss and study a variation of Kelly's congestion control in combination with our framework. We call the combined architecture PELS - partitioned enhancement layer streaming.
14238528
Is appearance-based structure from motion viable?
Most structure from motion work assumes that tracking is a separate issue from recovery of structure and motion. This paper argues that in certain cases, it helps to use the original images to refine the tracking in the course of estimating structure and motion. We illustrate this by presenting two algorithms: one for appearance-based structure from complete rotation and another for 3-D face modeling from three images. We come to the following conclusion: use appearance prediction only if the gross shape or type of shape deformation is known. Otherwise, one is very likely better off just using the currently known tracks.
8305231
Packet-pair bandwidth estimation: stochastic analysis of a single congested node
We examine the problem of estimating the capacity of bottleneck links and available bandwidth of end-to-end paths under non-negligible cross-traffic conditions. We present a simple stochastic analysis of the problem in the context of a single congested node and derive several results that allow the construction of asymptotically-accurate bandwidth estimators. We first develop a generic queuing model of an Internet router and solve the estimation problem assuming renewal cross-traffic at the bottleneck link. Noticing that the renewal assumption on Internet flows is too strong, we investigate an alternative filtering solution that asymptotically converges to the desired values of the bottleneck capacity and available bandwidth under arbitrary (including non-stationary) cross-traffic. This is one of the first methods that simultaneously estimates both types of bandwidth and is provably accurate. We finish the paper by discussing the impossibility of a similar estimator for paths with two or more congested routers.
2215768
Separating reflections in human iris images for illumination estimation
A method is presented for separating corneal reflections in an image of human irises to estimate illumination from the surrounding scene. Previous techniques for reflection separation have demonstrated success in only limited cases, such as for uniform colored lighting and simple object textures, so they are not applicable to irises which exhibit intricate textures and complicated reflections of the environment. To make this problem feasible, we present a method that capitalizes on physical characteristics of human irises to obtain an illumination estimate that encompasses the prominent light contributors in the scene. Results of this algorithm are presented for eyes of different colors, including light colored eyes for which reflection separation is necessary to determine a valid illumination estimate