1368534
Use of Computation-Unit Integrated Memories in High-Level Synthesis
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller datapath associated with a memory subsystem (monolithic, partitioned, etc.). An architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated is proposed. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This paper addresses the challenge of providing a systematic synthesis framework for a CIM-based architecture. This framework can analyze the various tradeoffs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance low-overhead implementation. Efficient data reuse of register files have also been fully exploited to further improve system performance. Experiments with several behaviors indicate that an average performance improvement of 2.02times(a maximum of 2.70times) is possible with very low area overheads. The energy-delay product improves by an average of 2.5times(maximum of 3.8times)
1476959
High-level synthesis of distributed logic-memory architectures
With the increasing cost of global communication on-chip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout a chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This work provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the trade-offs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps.We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (upto, 5.31X average of 3.45X) performance improvements over well-optimized conventional designs with small area overheads (upto 19.3%, 15.1% on average).
16039010
Design, Implementation and Evaluation of a Real-Time Active Content Distribution Service
The phenomenal growth of the world-wide web has made it the most popular Internet application today. Web caching and content distribution services have been recognized as valuable techniques to mitigate the explosion of web traffic. An increasing fraction of web traffic today is dynamically generated and therefore intrinsically difficult to replicate or cache using present static approaches. Scalable delivery of such active content poses a myriad of challenges, including content replication, update propagation, and consistency management. This paper makes two contributions: it (1) describes a scalable architecture for transparent demand-driven distribution of active content; and (2) presents a system that can provide real-time delay guarantees on content access. Our approach involves migrating the scripts which generate dynamic web traffic, and their data, from the origin servers to active content distribution proxies nearest to the clients. We also present mechanisms on these proxies to enforce real-time delay guarantees for client requests. Our system is implemented and deployed on Planetlab (2004), a real-world distributed Internet testbed. Experimental data show that significant improvements are observed in effective throughput and client response time, and that delay bounds on content access can be guaranteed with a very high probability.
10038411
On personal data license design and negotiation
Web applications often require users to provide personal information for customization, identification, or completing a transaction. However, the way we disclose our information in current cyberspace does not allow us to control the usage, release and circulation of the information, violating the basic principle of personal information privacy. Online personal data licensing (OPDL) is a framework to bring the control of personal information back to individuals by requiring application and service providers to obtain a license from a person before collecting, processing, and using his personal information. In this paper we present the license design and automation of the license negotiation process.
54735
An architecture for real-time active content distribution
The phenomenal growth of the World Wide Web has made it the most popular Internet application today. Web caching and content distribution services have been recognized as valuable techniques to mitigate the explosion of Web traffic. An increasing fraction of Web traffic today is dynamically generated and therefore intrinsically difficult for replication using present static approaches. Scalable delivery of such active content poses a myriad of challenges, including content replication, update propagation, and consistency management. This paper makes two contributions: (1) it describes a scalable architecture for transparent demand-driven distribution of active content; (2) the system can provide real-time delay guarantee on content access. Our approach involves migrating the scripts which generate the dynamic Web traffic, and their data, from the server to active content distribution proxies nearest to the clients and mechanisms on these proxies to enforce real-time delay guarantees for client requests. Our system is implemented and deployed on PlanetLab, a real-world distributed Internet testbed. Experimental data show that significant improvements are observed in effective throughput and client response time, and delay bounds on content access can be guaranteed with a very high probability.
14027625
On test and diagnostics of flash memories
Embedded flash memory has been widely used in applications that require non-volatile on-chip storage elements. However, test and diagnostics of flash memories needs further investigation so that the overall cost of the products can be reduced. This paper presents the challenges and issues for test and diagnostics of flash memories, based on our recent experiences. We also suggest improvement of the test and diagnosis flow, including design-for-testability (DFT) using built-in self-test (BIST), built-in self-repair (BISR), and failure analysis. In addition, we present a configurable flash memory tester using FPGA for low-cost testing and diagnostics. Experimental results on industrial flash chips justify the effectiveness of our test and diagnostics system.
7537228
Achieving strong scaling with NAMD on Blue Gene/L
NAMD is a scalable molecular dynamics application, which has demonstrated its performance on several parallel computer architectures. Strong scaling is necessary for molecular dynamics as problem size is fixed, and a large number of iterations need to be executed to understand interesting biological phenomenon. The Blue Gene/L machine is a massive source of compute power. It consists of tens of thousands of embedded Power PC 440 processors. In this paper, we present several techniques to scale NAMD to 8192 processors of Blue Gene/L. These include topology specific optimizations, new messaging protocols, load-balancing, and overlap of computation and communication. We were able to achieve 1.2 TF of peak performance for cutoff simulations and 0.99 TF with PME.