2930416
Towards multiprocessor feature recognition
Abstract The availability of low-cost computational power is enabling the development of increasingly sophisticated cad software. Automation of design and manufacturing activities poses many difficult computational problems—significant among them is how to develop interactive systems that enable designers to explore and experiment with alternative ideas. As more downstream manufacturing activities are considered during the design phase, computational costs become problematic. Creating working software-based solutions requires a sophisticated allocation of computational resources in order to perform realistic design analyses and generate feedback. This paper presents our initial efforts to employ multiprocessor algorithms to recognize machining features from solid models of parts with large numbers of features and many geometric and topological entities. Our goal is to outline how improvements in computation time can be obtained by migrating existing software tools to multiprocessor architectures. An implementation of our approach is discussed.
12219775
Geometric algorithms for containment analysis of rotational parts
Abstract This paper describes a system and underlying algorithms to perform geometric containment analysis to determine if a newly designed rotational part can be manufactured from a part in an existing database of rotational parts. Only material removal of the database part is considered in order to obtain the newly designed part from the database part. The system uses a three-step algorithm to test for containment. The first step analyzes feasibility of containment using bounding cylinders. If the bounding cylinder of the query part is bigger than the part in the database, then the database part cannot contain the query part and it is eliminated from consideration. The second step analyzes feasibility of containment by ignoring off-axis features. Any part that fails to satisfy containment at this stage is eliminated from consideration. The third step analyzes the remaining parts from the database for feasibility of containment by including the off-axis features. Finally, the system rank-orders all the database parts that can contain the query part based on their volume differences with the query part. The system described in this paper can be used by designers and process planners to find an existing part that can be used as a stock to manufacture a newly designed part. This capability is expected to significantly reduce proliferation of parts, to improve manufacturing responsiveness, and to reduce the cost of new products.
532672
IMACS: A Case Study in Real-World Planning
This article discusses the complexities of real-world planning and how to create planning systems to address them. IMACS (Interactive Manufacturability Analysis and Critiquing System), an automated designer's aid, evaluates machined parts and suggests design modifications to improve their manufacturability, offering advantages over the planning techniques used in classical planning systems.
13998462
Geometric algorithms for computing cutter engagement functions in 2.5D milling operations
Cutter engagement is a measure that describes what portion of the cutter is involved in machining at a given instant of time. During profile milling of complex geometries, cutter engagement varies significantly along the cutter path. Cutter engagement information helps in determining the efficiency of the cutter path and also helps in improving it by adjusting the feed rate. This paper describes geometric algorithms for computing piece-wise continuous closed-form cutter engagement functions for 2.5D milling operations. The results produced by our algorithm are compared with the results obtained by discrete simulations of the cutting process and appear to match very well.
7211906
Manufacturing feature instances: which ones to recognize?
Manufacturing features and feature-based representations have become an integral part of research on manufacturing systems, largely due to their ability to model correspondences between design information and manufacturing operations. However, several research challenges still must be addressed in order to place feature technologies into a solid scientific and mathematical framework. One challenge is the issue of alternatives in feature-based planning. Even after one has decided upon an abstract set of features to use for representing manufacturing operations, the set of feature instances used to represent a part is by no means unique. For a complex part, many (sometimes infinitely many) different manufacturing operations can potentially be used to manufacture various portions of the part. Some of these feature instances will appear in useful manufacturing plans, and others will not. In order to reduce the number of alternative manufacturing plans that must be examined, we require a systematic means of specifying which feature instances are of interest. This paper addresses the issue of alternatives by introducing the notion of primary feature instances, which we contend are sufficient to generate all manufacturing plans of interest. To substantiate our argument, we describe how various instances in the primary feature set can be used to produce the desired plans. Furthermore, we discuss how this formulation overcomes computational difficulties faced by previous work, and present some complexity results for this approach in the domain of machined parts. “Also with: Nationaf Institute of Standards and Technology, Manufacturing Systems Integration Division Building 220, Room A-127, Gaithersburg, MD 20899. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advanta$e, the ACM copyright notice and the title of the publication and Its date appear, and notice is given that copying is by permission of the Association of Computing Machinery.To copy otherwise, or to republish, requires a fee and/or specific permission. Solid Modeling ’95, Salt Lake City, Utah USA
6821018
Concurrent evaluation of machinability during product design
An approach to evaluating the machinability of a part during the design stage, which performs systematic generation and evaluation of machining alternatives, is discussed. The results of the analysis provide feedback to the designer about problems that might arise with the machining and information to the manufacturing engineer about which machining processes and process parameters are most desirable.<<ETX>>
9949265
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These effects are becoming more prevalent due to short signal switching times and deep submicron circuitry. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We first present a new way for predicting the output waveform produced by an inverter due to a non-square wave pulse at its input. Our modeling technique captures such properties as the amplitude of a pulse and its rise/fall times and the delay through a device. To expedite the computation of the response of a logic gate to an input pulse, we have developed a novel way of modeling such gates by an equivalent inverter. We have developed a mixed-signal test generator that incorporates classical PODEM-like static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. We also present a new analog cost function that is used to guide the search process. Comparison of results with SPICE simulations confirms the accuracy of this approach. This paper focuses primarily on crosstalk induced pulses, but these results have been extended to deal with speedup and slowdown effects.
12850641
Fault-oriented Test Generation for Multicast Routing Protocol Design
We present a new algorithm for automatic test generation for multicast routing. Our algorithm processes a finite state machine (FSM) model of the protocol and uses a mix of forward and backward search techniques to generate the tests. The output tests include a set of topologies, protocol events and network failures, that lead to violation of protocol correctness and behavioral requirements. We target protocol robustness in specific, and do not attempt to verify other properties in this paper. We apply our method to a multicast routing protocol; PIM-DM, and investigate its behavior in the presence of selective packet loss on LANs and router crashes. Our study unveils several robustness violations in PIM-DM, for which we suggest fixes with the aid of the presented algorithm.
16692732
Versioned Hypermedia can improve software document management
This research was supported by the U. S. Department of Defense and by NSF CAREER award CCR-9734102. The Software Concordance project is addressing the software document management problem by providing a fine-grained version control model for software documents and their relationships using hypermedia versioning. A set of tools needed to maintain, visualize and analyze software documents is being constructed. This short paper presents research issues, initial results and a scheme for using hypermedia versioning and time stamps to automate detection of possible semantic non-conformance among software artifacts.
40067645
A BIST methodology for comprehensive testing of RAM with reduced heat dissipation
The severity of excessive heat dissipation during concurrent BIST of memory modules has been documented previously (1993). In this paper, the authors present new versions of several memory tests that reduce heat dissipation during testing. Each proposed test has the same fault coverage and time complexity as the original version but it reduces heat dissipation by a factor of two or more. For three of the tests, the heat dissipation is reduced by factors of four to sixteen. The design of BIST circuitry required to implement the proposed tests are presented and it is shown that additional area overhead incurred is very small.
5347587
Process aggravated noise (PAN): new validation and test problems
How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.