28095704
An automatic test pattern generator for at-speed robust path delay testing
At-speed robust path delay testing is more desirable than the commonly employed slow-fast delay testing due to lower test application time, lower area overhead, and increased possibility of detecting unmodeled faults that cause errors only during at-speed circuit operation. However, it has been observed in practice that at-speed application of tests generated by existing test generators can lead to their invalidation. In this paper, we first present techniques to modify tests generated by existing test generators to avoid invalidation during at-speed testing. We then present a new procedure to generate tests suitable for at-speed delay testing of combinational circuits. Experimental results show that (a) at-speed application of test sets generated by existing generators leads to significant test invalidation, where the degree of invalidation is approximately proportional to the degree of compactness of the test set, and (b) the at-speed robust path delay tests generated by the proposed test generator are significantly shorter than those obtained by modifying the tests generated by existing generators.
5347587
Process aggravated noise (PAN): new validation and test problems
How the trends in circuit design are increasing the significance of noise effects, such as crosstalk and ground bounce, is demonstrated. Further aggravated by process variations, these process aggravated noise (PAN) effects must be considered as an integral part of the design validation methodology. It is shown that the validation of a design in the presence of PAN effects requires simulation at new design corners that are not typically considered during the validation of digital CMOS circuits. Furthermore, it is shown that the choice of a new design corner depends not only on the particular PAN effect under consideration, but also on the nature of the circuit. We demonstrate the need for automating the process of selecting design corners as well as test sequences for validation and outline strategies for their automation.
45533435
BIST TPG for combinational cluster (glue logic) interconnect testing at board level
Due to the expense and complexity of boundary scan architecture (BSA) circuitry, non-boundary scan ICs (cluster ICs) are still used in modern circuit boards. A novel BIST architecture and a TPG design methodology to program this architecture are presented for testing inter-IC interconnects among combinational cluster ICs via IEEE 1149.1 BSA at board level. The two main issues that are tackled are: (1) safe testing, i.e., avoidance of conflicts at all multi-driver nets; and (2) obtaining complete coverage of all detectable faults in the interconnect. We have proposed a realistic model of interconnects that contain combinational cluster ICs, identified test requirements that must be satisfied by the TPG to achieve the above objectives, and developed a new TPG architecture that satisfies these test requirements. We have theoretically proven that the proposed technique guarantees safe and comprehensive testing of cluster interconnects and also demonstrated this fact via its applications to a few example circuits.
206766191
Accurate and efficient static timing analysis with crosstalk
We have developed an accurate and efficient methodology to perform static timing analysis (STA) in combinational logic blocks in the presence of multiple crosstalk-induced noise effects. The crosstalk model used is more accurate because it considers skew, input transition times, and driver strengths. This crosstalk model is enhanced to handle timing ranges for performing STA. The methodology also uses more accurate delay models for gates. The presence of one or more coupling capacitances can create cyclic timing dependencies, even in an otherwise acyclic circuit. We have developed an approach to partition the circuit into minimal timing-iterative subcircuits (TISs) that encapsulate the cyclic timing dependencies. When used in conjunction with our levelization procedure, iterative timing analysis is confined within individual TISs. We have demonstrated that the maximum arrival time values computed by the proposed STA using integrated delay models are much closer to detailed circuit simulation results than an STA that uses the 3C/sub c/ delay model.
5894578
Test embedding with discrete logarithms
When using Built-In Self Test (BIST) for testing VLSI circuits, a major concern is the generation of proper test patterns that detect the faults of interest. Usually a linear feedback shift register (LFSR) is used to generate test patterns. We first analyze the probability that an arbitrary pseudo-random test sequence of short length detects all faults. The term short is relative to the probability of detecting the fault having the fewest test patterns. We then show how to guide the search for an initial state (seed) for a LFSR with a given primitive feedback polynomial so that all the faults of interest are detected by a minimum length test sequence. Our algorithm is based on finding the location of test patterns in the sequence generated by this LPSR. This is accomplished using, the theory of discrete logarithms. We then select the shortest subsequence that includes test patterns for all the faults of interest, hence resulting in 100% fault coverage. >
206516479
BIST TPG for SRAM cluster interconnect testing at board level
A Built-In Self-Test (BIST) methodology and a test pattern generation (TPG) architecture for testing static random access memory (SRAM) interconnect at board level via IEEE 1149.1 Boundary Scan (BS) Architecture are presented. Due to the expense and complexity of BS circuitry the widely-used SRAMs on most modern telecommunication circuit boards seldom contain BS architecture. (We call such non-boundary scan ICs cluster-ICs.) Hence, a methodology that tests the large numbers of board-level interconnects at the control, address, and data lines of cluster SRAMs is necessary. This is especially essential for board-level interconnect BIST which is used not only for manufacturing testing but also for system testing after integration. Newly identified prohibited conditions, which enable re-arrangement and merger of tests, are incorporated into test conditions for SRAM cluster interconnects. These improvements have been exploited to develop an efficient test procedure that is suitable for BIST. The proposed BIST methodology generates TPGs that (i) guarantee the avoidance of multi-driver conflicts when testing via BSA, (ii) guarantee the detection of all testable SRAM cluster interconnect faults, (iii) have low area overhead, and (iv) have short test lengths.
8613156
Loop shifting and compaction for the high-level synthesis of designs with complex control flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a technique called loop shifting that incrementally exploits loop level parallelism across iterations by shifting and compacting operations across loop iterations. Our experimental results show that loop shifting is particularly effective for the synthesis of designs with complex control especially when resource utilization is already high and/or under tight resource constraints. In situations when further loop unrolling (or initiating another iteration of the loop body) leads to a sharp increase in the longest combinational path in the circuit and the circuit area, loop shifting is able to achieve up to 20% reduction in the input-to-output delay in the synthesized circuit. We implemented loop shifting within the SPARK parallelizing high-level synthesis framework and present results for experiments on designs derived from multimedia and image processing applications.
118731
A theoretical study of optimization techniques used in registration area based location management: models and online algorithms
We describe a study of optimization techniques which have been proposed in the literature for registration area based location management from the perspective of optimal on-line algorithms. We show that most of these optimization techniques such as forwarding pointers and overlapped registration areas can be modeled using metrical task systems. Some of these models are simple while others are somewhat intricate. These representations directly imply the applicability of existing results on metrical task systems to algorithm design for location management. However, this also means that general lower bounds known for online metrical task systems carry over to our formulations of location management. We also discuss some restricted models in which much better (and simpler) algorithms are possible.
6938010
Flip-flop chaining architecture for power-efficient scan during test application
Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature, does not incorporate reordering of scan cells; thus avoiding timing and routing overheads. ATPG software ATALANTA was used for test vector generation. The algorithm was verified for ISCAS’89 benchmark circuits, where it showed as much as 27.3% of reduction in switching activity during scan operations.
1656626
Coordinated parallelizing compiler optimizations and high-level synthesis
We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the <i>SPARK</i> framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing tool, validate the utility of our approach to the behavioral synthesis of designs with complex control flows.
2982914
Network topology exploration of mesh-based coarse-grain reconfigurable architectures
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these architectures: (a) changing the interconnection between PEs; (b) changing the way the network topology is traversed while mapping operations to the PEs; and (c) changing the communication delays on the interconnects between PEs. We propose network topology traversal strategies that first schedule PEs that are spatially close and that have more interconnections among them. We use an interconnect aware list scheduling heuristic as a vehicle to perform the network topology exploration experiments on a set of designs derived from DSP applications. Our experimental results show that a spiral traversal strategy, coupled with a two neighbor interconnect topology leads to good performance for the DSP benchmarks considered. Our prototype framework thus provides an exploration environment for system architects to explore and tune coarse-grain reconfigurable architectures for particular application domains.