8642618
Stationary subdivision schemes reproducing polynomials
A new class of subdivision schemes is presented. Each scheme in this class is a quasi-interpolatory scheme with a tension parameter, which reproduces polynomials up to a certain degree. We find that these schemes extend and unify not only the well-known Deslauriers-Dubuc interpolatory schemes but the quadratic and cubic B-spline schemes. This paper analyzes their convergence, smoothness and accuracy. It is proved that the proposed schemes provide at least the same or better smoothness and accuracy than the aforementioned schemes, when all the schemes are based on the same polynomial space. We also observe with some numerical examples that, by choosing an appropriate tension parameter, our new scheme can remove undesirable artifacts which usually appear in interpolatory schemes with irregularly distributed control points.
509415
A New Class of Non-stationary Interpolatory Subdivision Schemes Based on Exponential Polynomials
We present a new class of non-stationary, interpolatory subdivision schemes that can exactly reconstruct parametric surfaces including exponential polynomials. The subdivision rules in our scheme are interpolatory and are obtained using the property of reproducing exponential polynomials which constitute a shift-invariant space. It enables our scheme to exactly reproduce rotational features in surfaces which have trigonometric polynomials in their parametric equations. And the mask of our scheme converges to that of the polynomial-based scheme, so that the analytical smoothness of our scheme can be inferred from the smoothness of the polynomial based scheme.
40047629
Error Detection Process - Model, Design, and Its Impact on Computer Performance
Conventionally, reliability analyses either assume that a fault/error is detected immediately as it occurs, or ignore damage caused by imperfect detection mechanisms and error latency, namely, the time interval between the occurrence of an error and the detection of that error.
12406392
Measurement and Application of Fault Latency
The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate effects impossible. To remedy this deficiency, we 1) present a new methodology for indirectly measuring fault latency, 2) derive the distribution of fault latency from the methodology, and 3) apply the knowledge of fault latency to the analysis of two important examples.
5304492
Design specifications of a generic supply chain simulator
This paper describes a design specification for a generic, supply-chain-simulation system. The proposed simulation system is based on schedule-driven and stock-driven control methods to support the supply chain management. The simulation system includes three processing modes: business process flows, material process flows, and information process flows. The paper also discusses interface data requirements for the proposed supply-chain-simulation system.
27214261
Circular window control schemes in fast packet switches
In this paper, we investigate a scheduling algorithm, called the Circular Window Control (CWC) scheme, for packet switch fabrics. The scheme is simple and efficient. It uses a fixed length window with circular transmission sequences to minimize possible switch and output contentions. The scheme can attain a maximal throughput of 100% in non-blocking switches as well as Banyan-based blocking switches. The performance analyses and simulation results of the CWC scheme are also presented.
206579905
Improving multistage network performance under uniform and hot-spot traffics
The major performance drawbacks of multistage interconnection networks are due to link contention and message blockage. To remedy this problem, the authors propose a switch design which uses two independent routes between each input port and each output port within a switch. With proper routing control mechanisms, the adverse effect on link conflicts can be greatly reduced. Various simulations are used to illustrate the performance improvement of this new design under both uniform and hot-spot traffic patterns.<<ETX>>