17529460
Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over AWGN and Rayleigh channels
The novel family of redundant residue number system (RRNS) codes is studied. RRNS codes constitute maximum-minimum distance block codes, exhibiting identical distance properties to Reed-Solomon codes. Binary to RRNS symbol-mapping methods are proposed, in order to implement both systematic and nonsystematic RRNS codes. Furthermore, the upper-bound performance of systematic RRNS codes is investigated, when maximum-likelihood (ML) soft decoding is invoked. The classic Chase algorithm achieving near-ML soft decoding is introduced for the first time for RRNS codes, in order to decrease the complexity of the ML soft decoding. Furthermore, the modified Chase algorithm is employed to accept soft inputs, as well as to provide soft outputs, assisting in the turbo decoding of RRNS codes by using the soft-input/soft-output Chase algorithm
21840466
Acquisition of$m$-Sequences Using Recursive Soft Sequential Estimation
A novel sequential estimation method is proposed for the initial synchronization of pseudonoise (PN) signals derived from m-sequences. This sequential estimation method is designed based on the principle of recursive soft-in/soft-out (SISO) decoding, and we refer to it as the recursive soft sequential estimation (RSSE) acquisition scheme. The RSSE acquisition scheme exhibits a complexity similar to that of a conventional m-sequence generator, which increases only linearly with the number of stages in the m-sequence generator. Our simulation results also show that the acquisition time of the proposed RSSE acquisition scheme is also linearly dependent on the number of stages in the m-sequence generator. Owing to the above properties, the employment of the proposed RSSE acquisition scheme is beneficial for the acquisition of long m-sequences.
26409739
Guest Editors' Introduction
11280884
A novel cache design for vector processing
This paper introduces an innovative cache design for vector computers, called prime-mapped cache. By utilizing the special properties of a Mersenne prime, the new design does not increase the critical path length of a processor, nor does it increase the cache access time as compared to a direct-mapped cache. The prime-mapped cache minimizes cache miss ratio caused by line interferences that have been shown to be critical for numerical applications by previous investigators. We show that significant performance gains are possible by adding the proposed cache memory into an existing vector computer provided that application programs can be blocked. The performance gain will increase with the increase of the speed gap between processors and memories. We develop an analytical performance model based on a generic vector computation model to study the performance of the design. Our preliminary performance analysis on various vector access patterns shows that the prime-mapped cache can provide as much as a factor of 2 to 3 performance improvement over the conventional direct-mapped cache in the vector processing environment. Moreover, the additional hardware cost introduced by the new mapping scheme is negligible.
974543
A framework for sensor management in wireless and heterogeneous sensor network
This paper proposes a framework for sensor configuration and management in wireless multi sensor network system, which is responsible for taking decisions in order to coordinate the assignment and scheduling of sensors best suited for the application. A sensor manager operates over a heterogeneous sensor network, which provides sensory data from multiple types of sensors. The application of this work is tracking the movement of objects in a moderately occupied confined space. Simulations were run to study the operations of the proposed sensor manage in such application. The simulation results are compared to other published results to show the effectiveness of this work.
2764337
Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems
Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network nodes and portable consumer electronics. The most widely-used sensor network nodes have only 4-10 KB of RAM and do not contain memory management units (MMUs). It is very difficult to implement increasingly complex applications under such tight memory constraints. Nonetheless, price and power consumption constraints make it unlikely that increases in RAM in these systems will keep pace with the requirements of applications.We propose the use of automated compile-time and run-time techniques to increase the amount of usable memory in MMU-less embedded systems. The proposed techniques do not increase hardware cost, and are designed to require few or no changes to existing applications. We have developed a fast compression algorithm well suited to this application, as well as run-time library routines and compiler transformations to control and optimize the automatic migration of application data between compressed and uncompressed memory regions. These techniques were experimentally evaluated on Crossbow TelosB sensor network nodes running a number of data collection and signal processing applications. The results indicate that available memory can be increased by up to 50% with less than 10% performance degradation for most benchmarks.
2470832
Statistical data reduction for efficient application performance monitoring
There is a growing need for systems that can monitor and analyze application performance data automatically in order to deliver reliable and sustained performance to applications. However, the continuously growing complexity of high performance computer systems and applications makes this process difficult. We introduce a statistical data reduction method that can be used to guide the selection of system metrics that are both necessary and sufficient to describe observed application behavior, thus reducing the instrumentation perturbation and data volume to be managed. To evaluate our strategy, we applied it to one CPU-bound grid application using cluster machines and GridFTP data transfer in a wide area testbed. A comparative study shows that our strategy produces better results than other techniques. It can reduce the number of system metrics to be managed by about 80%, while still capturing enough information for performance predictions.