16361691
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection.
6938010
Flip-flop chaining architecture for power-efficient scan during test application
Power dissipation in CMOS circuits during test time poses a crucial bottleneck for circuit performance and robustness. The power consumption due to switching activity while scan-in of test vectors and scan-out of responses is of particular concern. In this paper a methodology for scan chain modification and test vector adaptation is proposed to effectively reduce the scan test power consumption by controlling this switching activity. Proposed approach, unlike the many in published literature, does not incorporate reordering of scan cells; thus avoiding timing and routing overheads. ATPG software ATALANTA was used for test vector generation. The algorithm was verified for ISCAS’89 benchmark circuits, where it showed as much as 27.3% of reduction in switching activity during scan operations.
794427
UpdateSearch: A New Dynamic Channel Allocation Scheme for Mobile Networks That Can Adjust to System Loads
Distributed dynamic channel allocation techniques are an integral part of distributed mobile computing systems where nodes communicate among themselves via wireless radio channels. The channel allocation schemes can be broadly categorized as search based or update based. Search based techniques have low messaging complexity and are suited for high system load and low request rates. On the other hand update based schemes have higher messaging complexity but are more suitable for low system load and high request rates. This paper presents a combined scheme, called UpdateSearch, which provides the advantages of both types of schemes. UpdateSearch is parameterized by the number of channel classes k, 1≤k≤n, where n is the total number of channels in the system. The parameter k can be adjusted to control the number of concurrent searches and degree of contention between cells competing for channels in the system. For k=1 and k=n the scheme respectively behaves as basic search and basic update scheme [2]. A simple analytical model is used to compare the performance of UpdateSearch for various values of k with the basic update and search techniques in terms of channel allocation time and number of simultaneous channel selections allowed in the system under different system loading conditions.
33983442
Test generation for ground bounce in internal logic circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.
1958013
Analysis of high-level address code transformations for programmable processors
Memory intensive applications require considerable arithmetic for the computation and selection of the different memory access pointers. These memory address calculations often involve complex (non) linear arithmetic expressions which have to be calculated during program execution under tight timing constraints, this becoming a critical bottleneck in the overall system performance. This paper explores applicability and effectiveness of source-level optimisations (as opposed to instruction-level) for address computations in the context of multimedia. We propose and evaluate two processor-target independent source-level optimisation techniques, namely, global scope operation cost minimisation complemented with loop-invariant code hoisting, and nonlinear operator strength reduction. The transformations attempt to achieve minimal code execution within loops and reduced operator strengths. The effectiveness of the transformations is demonstrated with two real-life multimedia application kernels by comparing the improvements in the number of execution cycles, before and after applying the systematic source-level optimisations. Using state-of-the-art C compilers on several popular RISC platforms.
40067645
A BIST methodology for comprehensive testing of RAM with reduced heat dissipation
The severity of excessive heat dissipation during concurrent BIST of memory modules has been documented previously (1993). In this paper, the authors present new versions of several memory tests that reduce heat dissipation during testing. Each proposed test has the same fault coverage and time complexity as the original version but it reduces heat dissipation by a factor of two or more. For three of the tests, the heat dissipation is reduced by factors of four to sixteen. The design of BIST circuitry required to implement the proposed tests are presented and it is shown that additional area overhead incurred is very small.
37175673
A methodology to design efficient BIST test pattern generators
This paper describes a new technique to design efficient test pattern generators (TPGs) for built-in self-test (BIST). The proposed technique identifies compatible circuit inputs that can be connected to the same TPG stage in the test mode. Compatibility between circuit inputs is determined by analyzing the circuit function to guarantee coverage of all faults in a given target fault set. Unlike pseudo-exhaustive testing, circuit inputs that fanout to the same output can be compatible, provided that connecting them to the same TPG stage does not cause any loss of fault coverage. Experimental results show that TPGs designed by the proposed technique achieve 100% stuck-at fault coverage in practical test length (/spl les/2/sup 28/) with low hardware overhead and performance penalty for a wide range of benchmark circuits.