18504704
Instruction Scheduling with Timing Constraints on a Single RISC Processor with 0/1 Latencies
In this paper, We propose a faster algorithm for the following instruction scheduling problem: Given a set of UET (Unit Execution Time) instructions with precedence constraints in the form of a DAG(Directed Acyclic Graph), latency constraints where latencies between any two instructions are restricted to be either 0 or 1, timing constraints in the form of individual integer release times and deadlines and a single RISC processor, find a feasible schedule which satisfies all constraints. The time complexity of our algorithm is O(n2 log n) + min{O(ne), O(n2.376)}, where n is the number of instructions and e is the number of edges in the precedence graph. Our algorithm is faster than the existing algorithm which runs in O(n3α(n)) time, where α(n) is the inverse of Ackermann function. In addition, our algorithm can be used to solve the maximum lateness minimization problem in O(n2 log2 n + min{ne, n2.376}) time.
8343325
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (instruction level parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimising compiler for ILP processors needs to find a feasible schedule for a set of time-constrained instructions. In this paper, we present a fast algorithm for scheduling instructions with precedence-latency constraints, individual integer release times and deadlines on an ILP processor with multiple functional units. The time complexity of our algorithm is O(n2 logd)+min{O(de), O(ne)}+min{O(ne), O(n2.376)}, where n is the number of instructions, e is the number of edges in the precedence graph and d is the maximum latency. Our algorithm is guaranteed to find a feasible schedule whenever one exists in the following special cases: 1) one functional unit, arbitrary precedence constraints, latencies in {0,1}, integer release times and deadlines; 2) two identical functional units, arbitrary precedence constraints, latencies of 0, integer release times and deadlines; 3) multiple identical functional units or multiple functional units of different types, monotone interval-ordered graph, integer release times and deadlines; 4) multiple identical functional units, in-forest, equal latencies, integer release times and deadlines. In case 1) our algorithm improves the existing fastest algorithm from O(n2 logn)+min{O(ne), O(n2.376)} to min{O(ne), O(n2.376)}. In case 2) our algorithm improves the existing fastest algorithm from O(ne+n2 logn) to min{O(ne), O(n2.376)}. In case 3) no polynomial time algorithm for multiple functional units of different types was known before
546715
Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor
Energy-aware task scheduling is critical for real-time embedded systems. Although dynamic power has traditionally been a primary source of processor power consumption, leakage power is becoming increasingly important. In this paper, we present two optimal energy-aware polynomial-time algorithms for scheduling a set of tasks with release times, deadlines and precedence constraints on a single processor with continuous voltages. Our algorithms are guaranteed to minimise the total energy consumption of all tasks while minimising their maximum lateness under two power models: the dynamic power model where the dynamic power dominates the processor power consumption and the dynamic and leakage power model where both dynamic power and leakage power are significant sources of the processor power consumption. The time complexities of both algorithms are O(n3) , where n is the number of tasks
7266719
Two processor scheduling with real release times and deadlines
In a hard real-time system, critical tasks are subject to timing constraints such as release times and deadlines. All timing constraints must be satisfied when tasks are executed. Nevertheless, given a set of tasks, finding a feasible schedule which satisfies all timing constraints is NP-complete even on one processor.In this paper, we study the following special non-pre-emptive two processor scheduling problem: Given a set of UET (Unit Execution Time) tasks with arbitrary precedence constraints, individual real release times and deadlines, find a feasible schedule on two identical processors whenever one exists. The complexity status of this problem has been open for a long time. we propose the first polynomial algorithm for this problem. Our algorithm is underpinned by the key consistency notion: successor-tree-consistency. The time complexity of our algorithm is O(n4), where n is the number of tasks.
2876560
Utility Accrual Real-Time Scheduling under Variable Cost Functions
We present a utility accrual real-time scheduling algorithm called CIC-VCUA for tasks whose execution times are functions of their starting times (and, potentially, other factors). We model such variable execution times using variable cost functions (or VCFs). The algorithm considers application activities that are subject to time/utility function time constraints, execution times described using VCFs, and mutual exclusion constraints on concurrent sharing of non-CPU resources. We consider the twofold scheduling objective of 1) assuring that the maximum interval between any two consecutive, successful completions of job instances in an activity must not exceed the activity period (an application-specific objective) and 2) maximizing the system's total accrued utility while satisfying mutual exclusion resource constraints. Since the scheduling problem is intractable, CIC-VCUA is a polynomial-time heuristic algorithm. The algorithm statically computes worst-case task sojourn times, dynamically selects tasks for execution based on their potential utility density, and completes tasks at specific times. We establish that CIC-VCUA achieves optimal timeliness during underloads, and tightly upper bounds inter and intratask completion times. Our simulation experiments confirm the algorithm's effectiveness and superiority
9865654
A reversible data hiding approach to mesh authentication
This paper proposes a reversible data hiding method to authenticate 3D meshes by modulating the distances from the mesh faces to the mesh centroid to embed a fragile watermark. It keeps the modulation information in the watermarked mesh so that the reversibility of the embedding process is achieved. Since the embedded watermark is sensitive to geometrical and topological processing, unauthorized modifications on the watermarked mesh can be therefore detected by retrieving and comparing the embedded watermark with the original one. Furthermore, as long as the watermarked mesh is intact, the original mesh can be recovered using some priori knowledge.
31035436
Contractible Elements in Graphs and Matroids
Let G be a simple 3-connected graph with at least five vertices. Tutte [13] showed that G has at least one contractible edge. Thomassen [11] gave a simple proof of this fact and showed that contractible edges have many applications. In this paper, we show that there are at most $\frac{|V(G)|}{5}$ vertices that are not incident to contractible edges in a 3-connected graph G. This bound is best-possible. We also show that if a vertex v is not incident to any contractible edge in G, then v has at least four neighbours having degree three, and each such neighbour is incident to exactly two contractible edges. We give short proofs of several results on contractible edges in 3-connected graphs as well. We also study the contractible elements for k-connected matroids. We partially solve an open problem for regular matroids.
16198255
Accurate Emulation of Wireless Sensor Networks
Wireless sensor networks (WSNs) have a wide range of useful, data-centric applications, and major techniques involved in these applications include in-network query processing and query-informed routing. Both techniques require realistic environments and detailed system feedback for development and evaluation. Unfortunately, neither real sensor networks nor existing simulators/emulators are suitable for this requirement. In this design paper, we propose a distributed sensor network emulator, a Virtual Mote Network (VMNet), to meet this requirement. We describe the system architecture, the synchronization of the nodes and the virtual time emulation with a focus on mechanisms that are effective for accurate emulation.
6769302
A utility accrual scheduling algorithm for real-time activities with mutual exclusion resource constraints
This paper presents a uni-processor real-time scheduling algorithm called the generic utility scheduling algorithm (which we refer to simply as GUS). GUS solves a previously open real-time scheduling problem-scheduling application activities that have time constraints specified using arbitrarily shaped time/utility functions and have mutual exclusion resource constraints. A time/ utility function are a time constraint specification that describes an activity's utility to the system as a function of that activity's completion time. Given such time and resource constraints, we consider the scheduling objective of maximizing the total utility that is accrued by the completion of all activities. Since this problem is NP-hard, GUS heuristically computes schedules with a polynomial-time cost of O(n/sup 3/) at each scheduling event, where n is the number of activities in the ready queue. We evaluate the performance of GUS through simulation and by an actual implementation on a real-time POSIX operating system. Our simulation studies and implementation measurements reveal that GUS performs close to, if not better than, the existing algorithms for the cases that they apply. Furthermore, we analytically establish several properties of GUS.