5689495
A hardware accelerator IP for EBCOT tier-1 coding in JPEG2000 standard
We propose a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standard. EBCOT Tier-1 accounts for more than 70% of encoding time due to extensive bit-level processing. Our architecture consists of a 16-way parallel context formation module and a 3-stage pipelined arithmetic encoder. We reduce power consumption by properly shutting down parts of the circuit. Compared with the known best design, we reduce 17% of the cycle count and reach a level within 5% of the theoretical lower bound. We have implemented the design in synthesizable Verilog RTL with an AMBA-AHB interface for SOC design. FPGA prototyping has been successfully demonstrated and substantial speedup achieved.
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
15619003
A Graphical User Interface Design for Network Simulation
Abstract This article describes a prototyping effort of a flexible graphical user interface (GUI) for a simulation tool called COPS. The GUI is designed to allow parameter setup for all modules in simulation model, and can be easily replaced by new GUIs implemented in different languages/graphical tools. This article provides design guidelines and implementation details of the flexible GUI.
7307200
Exploiting Lookahead in Parallel Simulation
Lookahead is the ability of a process to predict its future behavior. The feasibility of implicit lookahead for non-FCFS stochastic queuing systems is demonstrated. Several lookahead exploiting techniques are proposed for round-robin (RR) system simulations. An algorithm that generates lookahead in O(1) time is described. Analytical models and experiments are constructed to evaluate these techniques. A lookahead technique for preemptive priority (PP) systems is evaluated using an analytical model. The performance metric for these techniques is the lookahead ratio, which is correlated with other performance measures of more direct interest, such as speedup. The analyses show that using implicit lookahead can significantly improve the lookahead ratios of RR and PP system simulations. >
17890167
A Parallelism Analyzer for Conservative Parallel Simulation
Most small-scale simulation applications are implemented by sequential simulation techniques. As the problem size increases, however, sequential techniques may be unable to manage the time complexity of the simulation applications adequately. It is natural to consider re-implementing the corresponding large-scale simulations using parallel techniques, which have been reported to be successful in reducing the time complexity for several examples. However, parallel simulation may not be effective for every application. Since the implementation of parallel simulation for an application is usually very expensive, it is required to investigate the performance of parallel simulation for a particular application before re-implementing the simulation. The Chandy-Misra parallel, discrete-event simulation paradigm has been utilized in many large-scale simulation experiments, and several significant extensions have been based on it. Hence the Chandy-Misra protocol is adopted here as a basic model of parallel simulation to which our performance prediction techniques are applied. For an existing sequential simulation program based on the process interaction model, this paper proposes a technique for evaluating Chandy-Misra parallel simulation without actually implementing the parallel program. The idea is to insert parallelism analysis code into the sequential simulation program. When the modified sequential program is executed, the time complexity of the parallel simulation based on the Chandy-Misra protocol is computed. Our technique has been used to determine whether a giant Signaling System 7 simulation (sequential implementation) should be re-implemented using the parallel simulation approach. >
9700596
Implicit Deregistration with Forced Registration for PCS Mobility Management
Registration/deregistration with a mobility database called Visitor Location Registers (VLRs) is required in a PCS network when a mobile phone moves between registration areas. Several schemes were proposed to deregister a mobile phone after it moves out of a registration area. A simple scheme, called implicit deregistration, is studied in this paper, which does not specifically deregister any obsolete record in the VLR. If the VLR is full when a mobile phone arrives, a record in the VLR is deleted and the reclaimed storage is reassigned to the incoming mobile phone. It is possible that a valid record will be deleted. If so, the VLR record of a mobile phone may be deleted before a call to the mobile phone arrives. Our previous work assumed that the incoming call setup would be lost. In this paper, we propose forced registration to restore the VLR record before the call setup operation can proceed. With this modification, implicit deregistration totally eliminates the deregistration traffic at the cost of creating some forced registration traffic.We derive the record-missing probability and the portion of the network traffic saved by implicit deregistration. Our study indicates that implicit deregistration with forced registration may significantly reduce the deregistration traffic if the user mobility is high and the number of mobile phones in a registration area is not very large.
7180014
A software architecture for GPRS session management
General packet radio service (GPRS) provides efficient access to the integrated services Internet from wireless networks. When the GPRS-attached mobile station attempts to send or receive data, a packet data protocol (PDP) context shall be established. The GPRS session management (SM) supports the PDP context handling, which consists of PDP context activation, deactivation, and modification procedures. In this paper, we propose an SM software architecture for the serving GPRS support node. Our design goals are to achieve compatibility, modularity, and flexibility. More importantly, our approach can accommodate the design of the SM software architecture for third-generation wireless networks. Copyright © 2001 John Wiley & Sons, Ltd.