60476874
High-level synthesis using computation-unit integrated memories
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASIC) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). We propose an architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This work addresses the challenge of providing an automatic synthesis framework for a CIM-based architecture. Our framework can analyze the various trade-offs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance, low-overhead implementation. Experiments with several behaviors indicate that an average performance improvement of 1.88/spl times/ (a maximum of 2.63/spl times/) is possible with very low area overheads. The energy-delay product improves by an average of 2.1/spl times/ (maximum of 3.4/spl times/).
1368534
Use of Computation-Unit Integrated Memories in High-Level Synthesis
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller datapath associated with a memory subsystem (monolithic, partitioned, etc.). An architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated is proposed. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This paper addresses the challenge of providing a systematic synthesis framework for a CIM-based architecture. This framework can analyze the various tradeoffs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance low-overhead implementation. Efficient data reuse of register files have also been fully exploited to further improve system performance. Experiments with several behaviors indicate that an average performance improvement of 2.02times(a maximum of 2.70times) is possible with very low area overheads. The energy-delay product improves by an average of 2.5times(maximum of 3.8times)
1476959
High-level synthesis of distributed logic-memory architectures
With the increasing cost of global communication on-chip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout a chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This work provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing data and computations, carefully examines the trade-offs (i.e., communication overheads, synchronization costs, area overheads) in choosing one solution over another, and utilizes conventional HLS techniques for intermediate steps.We have evaluated the proposed framework on several benchmarks by generating register-transfer level (RTL) implementations using an existing commercial HLS tool with and without our enhancements, and by subjecting the resulting RTL circuits to logic synthesis and layout. The results show that circuits designed as distributed logic-memory architectures using our framework achieve significant (upto, 5.31X average of 3.45X) performance improvements over well-optimized conventional designs with small area overheads (upto 19.3%, 15.1% on average).
10038411
On personal data license design and negotiation
Web applications often require users to provide personal information for customization, identification, or completing a transaction. However, the way we disclose our information in current cyberspace does not allow us to control the usage, release and circulation of the information, violating the basic principle of personal information privacy. Online personal data licensing (OPDL) is a framework to bring the control of personal information back to individuals by requiring application and service providers to obtain a license from a person before collecting, processing, and using his personal information. In this paper we present the license design and automation of the license negotiation process.
2648412
Performance evaluation of adaptive MPI
Processor virtualization via migratable objects is a powerful technique that enables the runtime system to carry out intelligent adaptive optimizations like dynamic resource management. Charm++ is an early language/system that supports migratable objects. This paper describes Adaptive MPI (or AMPI), an MPI implementation and extension, that supports processor virtualization. AMPI implements virtual MPI processes (VPs), several of which may be mapped to a single physical processor. AMPI includes a powerful runtime support system that takes advantage of the degree of freedom afforded by allowing it to assign VPs onto processors. With this runtime system, AMPI supports such features as automatic adaptive overlapping of communication and computation, automatic load balancing, flexibility of running on arbitrary number of processors, and checkpoint/restart support. It also inherits communication optimization from Charm++ framework. This paper describes AMPI, illustrates its performance benefits through a series of benchmarks, and shows that AMPI is a portable and mature MPI implementation that offers various performance benefits to dynamic applications.
6505998
Failure factor based yield enhancement for SRAM designs
With increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-for-yield (DFY) methodologies have an increasing impact on the yield learning of modem silicon chips. However, a major part of a system chip is typically occupied by memories, which dominate the yield of the chip. During chip integration, it is important that we pick the right design of memory cores that will maximize the yield under the specific process technology chosen. Traditionally, yield prediction is only based on layout and defect statistics. In this paper, we propose to estimate the yield with a failure factor. We thus develop a memory failure factor analyzer (FFA), based on that, we can select the memory design that is more suitable for the given process technology. Experimental results show that we can efficiently evaluate the yields of different memory designs for the same specification, so that the most robust one, that results in the highest yield, can be selected.
14027625
On test and diagnostics of flash memories
Embedded flash memory has been widely used in applications that require non-volatile on-chip storage elements. However, test and diagnostics of flash memories needs further investigation so that the overall cost of the products can be reduced. This paper presents the challenges and issues for test and diagnostics of flash memories, based on our recent experiences. We also suggest improvement of the test and diagnosis flow, including design-for-testability (DFT) using built-in self-test (BIST), built-in self-repair (BISR), and failure analysis. In addition, we present a configurable flash memory tester using FPGA for low-cost testing and diagnostics. Experimental results on industrial flash chips justify the effectiveness of our test and diagnostics system.
5351237
Game traffic analysis: an MMORPG perspective
Online gaming is one of the most profitable businesses over the Internet. Among all genres of the online games, the popularity of the MMORPG (Massive Multiplayer Online Role Playing Games) is especially prominent in Asia. Opting for a better understanding of the game traffic and the economic well being of the Internet, we analyze a 1,356-million-packet trace from a sizeable MMORPG, ShenZhou Online. This work is, as far as we know, the first formal analysis on the MMORPG server traces.We find that the MMORPG and FPS (First-Person Shooting) games are similar in that they both generate small packets and require low bandwidths. In particular, the bandwidth requirement of MMORPG is even lower due to the less real-time game play. More distinctive are the strong periodicity, temporal locality, and irregularity observed in the MMORPG traffic. The periodicity is due to a common practice in game implementation, where the game state updates are accumulated within a fixed time window before transmission. The temporal locality in the game traffic is largely due to the game nature where one action leads to another. The irregularity, particular unique in MMORPG traffic, is due to the diversity of game design where the user behavior can be drastically different depending on the quest at hand.