27186635
Register minimization beyond sharing among variables
Traditionally, it is assumed that every variable in the input HDL (hardware description language) behavioral description needs to be held in a register; a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been shown effective for signal-flow-like computations such as various DSP algorithms. However, the same is not true for the synthesis of control-dominated circuits, which usually have variables of different bit-width as well as very long lifetime. To go beyond register minimization by lifetime-analysis-based sharing, we propose holding some variables in the state registers, some signal nets, some unclocked sequential networks or a combination of above. We identify the conditions in which the substitution is feasible. We have implemented the proposed method in a software program called VReg. Experimental results have demonstrated that VReg minimizes the number of registers more effectively than the lifetime-analysis-based approach does. Better register area minimization also generally leads to faster designs.
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
28156768
A VLSI implementation of the blowfish encryption/decryption algorithm
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-rescheduling method, the critical path delay is improved by 21.7%. We have successfully implemented it using Compass cell library targeted at a 0.6 μm TSMC SPTM CMOS process. The die size is 5.7x6.1 mm and the maximum frequency is 50MHz.
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
9314572
Demand re‐registration for PCS database restoration
In a Personal Communications Services (PCS) network, mobility databases such as Home Location Register (HLR) and Visitor Location Register (VLR) are utilized to support mobility management for Mobile Stations (MSs). If the location databases fail, the location information loss or corruption will seriously degrade the service offered to the subscribers. In this paper, we propose a new VLR failure recovery scheme called demand re‐registration. In this scheme, the VLR broadcasts a re‐registration request to all MSs after the VLR failure. When an MS receives the re‐registration request, it sends a registration message to the VLR to recover the location record. Since all MSs will re‐register after receiving the broadcasting request, traffic jam (and thus collisions) may occur. If a collision occurs, then the involved MSs must re‐send the registration messages. This paper studies the performance of demand re‐registration by investigating how effectively the re‐registration can recover the location record for an MS before the first MS call termination occurs. Our results indicate that demand re‐registration can effectively recover VLR failure.
1571256
Parallelism analyzers for parallel discrete event simulation
Discrete event simulation is usually time consuming. Recently, there has been a great deal of interest in using parallel computers to speed up the simulation process. Before the parallel simulation approach is applied, it is important to understand the inherent parallelism of simulation applications. A simple technique called critical path analysis was proposed to study paralllelism of simulation applications. This paper describes three critical path analysis algorithms based on different event-scheduling (process scheduling) policies. These algorithms are much simpler than a previous approach, where the events must be recorded in a trace and an extra pass is required to process the event trace. In our approach, the critical path analysis algorithms are integrated with the sequential simulation. At the end of the sequential simulation, the optimal parallel execution time is also computed. Livny proposed an algorithm similar to our approach (His, however, was designed for a specific language). Our algorithms can be integrated with sequential simulation programs written by users or be integrated with simulation languages. Another advantage of our algorithms over previous approaches is that ours can be used to study load balancing under different event-scheduling policies. Since our algorithms can be easily inserted in sequential simulation programs, critical path analysis can be applied to existing sequential programs without difficulty. The results can then be used to predict the performance of parallel simulation on similar applications. An example is given to show how useful information can be obtained from our algorithms.
30064725
Potential Fraudulent Usage in Mobile Telecommunications Networks
This paper investigates the fraudulent usage of mobile telecommunications services due to cloned subscriber identity modules (SIMs). In GSM or the Universal Mobile Telecommunication System (UMTS), a mobile phone or mobile station uses its SIM to gain network access through authentication. If the SIM of a legal user is cloned, then the cloned SIM can be used for GSM/UMTS authentication and fraudulent usage may occur. Under the existing GSM/UMTS mobility management and call setup procedures, we show how quickly the fraudulent usage can be detected. We also propose a simple solution to speed up the detection of potential fraudulent usage.
119947006
All (k;g)-cages are k-edge-connected
A (k;g)-cage is a k-regular graph with girth g and with the least possible number of vertices. In this paper, we prove that (k;g)-cages are k-edge-connected if g is even. Earlier, Wang, Xu, and Wang proved that (k;g)-cages are k-edge-connected if g is odd. Combining our results, we conclude that the (k;g)-cages are k-edge-connected. © 2005 Wiley Periodicals, Inc. J Graph Theory 48: 219–227, 2005
9700596
Implicit Deregistration with Forced Registration for PCS Mobility Management
Registration/deregistration with a mobility database called Visitor Location Registers (VLRs) is required in a PCS network when a mobile phone moves between registration areas. Several schemes were proposed to deregister a mobile phone after it moves out of a registration area. A simple scheme, called implicit deregistration, is studied in this paper, which does not specifically deregister any obsolete record in the VLR. If the VLR is full when a mobile phone arrives, a record in the VLR is deleted and the reclaimed storage is reassigned to the incoming mobile phone. It is possible that a valid record will be deleted. If so, the VLR record of a mobile phone may be deleted before a call to the mobile phone arrives. Our previous work assumed that the incoming call setup would be lost. In this paper, we propose forced registration to restore the VLR record before the call setup operation can proceed. With this modification, implicit deregistration totally eliminates the deregistration traffic at the cost of creating some forced registration traffic.We derive the record-missing probability and the portion of the network traffic saved by implicit deregistration. Our study indicates that implicit deregistration with forced registration may significantly reduce the deregistration traffic if the user mobility is high and the number of mobile phones in a registration area is not very large.