13626417
Synthesis of systems specified as interacting VHDL processes
Abstract This paper presents an approach to synthesis of hardware systems specified as interacting VHDL processes. Different from traditional high-level synthesis methodologies our approach takes into account the interactions and interdependence between concurrent processes. Two methods have been developed. The first method supports an unrestricted use of signals and wait statements and synthesizes synchronous hardware with global control of process synchronization for signal update. The second method allows hardware synthesis without the strict synchronization required by the VHDL simulation-based semantics. In both methods VHDL system specification are first translated into an internal design representation based on time Petri nets, which is then synthesized into hardware implementation structures at register-transfer level. Our main objective is to preserve simulation/synthesis correspondence during synthesis and to produce hardware that operates with a high degree of parallelism. Experimental results with practical design examples demonstrate that the proposed methods are efficient in terms of both resulted hardware and optimization time.
13280070
Modeling and formal verification of embedded systems based on a Petri net representation
In this paper we concentrate on aspects related to modeling and formal verification of embedded systems. First, we define a formal model of computation for embedded systems based on Petri nets that can capture important features of such systems and allows their representation at different levels of granularity. Our modeling formalism has a well-defined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process. Second, we propose an approach to the problem of formal verification of embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking tools. We propose two strategies for improving the verification efficiency, the first by applying correctness-preserving transformations and the second by exploring the degree of parallelism characteristic to the system. Some examples, including a realistic industrial case, demonstrate the efficiency of our approach on practical applications.
10406156
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems
We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.
7975456
Schedulability-driven frame packing for multi-cluster distributed embedded systems
We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.
9707498
Efficient test solutions for core-based designs
A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.
1992062
Inter-domain movement of functionality as a repartitioning strategy for hardware/software co-design
Abstract This paper describes how initial hardware/software partitions can be modified by moving functionality between hardware and software. This inter-domain movement of functionality combined with a transformation-based design methodology enables the use of repartitioning as an optimization technique for co-design. This is made possible because of a unified co-design representation where Petri nets are used to represent controllers of both hardware and software module. To model data manipulation we use datapaths in hardware and instruction dependence graphs in software. We demonstrate in this paper how datapaths can be mapped into instruction dependence graphs and vice versa. Using this technique, systems may be repartitioned whithout the complex and time-consuming resynthesis of the functionality to be moved or the whole design.
36553676
Time and Space Efficient Algorithms for Constrained Sequence Alignment
In this paper, we study the constrained sequence alignment problem, which is a generalization of the classical sequence alignment problem with the additional constraint that some characters in the alignment must be positioned at the same columns. The problem finds important applications in Bioinformatics. Our major result is an O(ln2)-time and O(ln)-space algorithm for constructing an optimal constrained alignment of two sequences where n is the length of the longer sequence and l is the length of the constraint. Our algorithm matches the best known time complexity and reduces the best known space complexity by a factor of n for solving the problem. We also apply our technique to design time and space efficient heuristic and approximation algorithm for aligning multiple sequences.
7886387
An Efficient Reduction from Constrained to Unconstrained Maximum Agreement Subtree
We propose and study the Maximum Constrained Agreement Subtree (MCAST) problem, which is a variant of the classical Maximum Agreement Subtree (MAST) problem. Our problem allows users to apply their domain knowledge to control the construction of the agreement subtrees in order to get better results. We show that the MCAST problem can be reduced to the MAST problem efficiently and thus we have algorithms for MCAST with running times matching the fastest known algorithms for MAST.
43554221
Online and Dynamic Recognition of Squarefree Strings
The online squarefree recognition problem is to detect the first occurrence of a square in a string whose characters are provided as input one at a time. We present an efficient algorithm to solve this problem for strings over arbitrarily ordered alphabets. Its running time is O(n log n), where n is the ending position of the first square, which matches the running times of the fastest known algorithms for the analogous offline problem. We also present a very simple algorithm for a dynamic version of the problem over general alphabets in which we are initially given a squarefree string, followed by a series of updates, and the objective is to determine after each update if the resulting string contains a square and if so, report it and stop.
1176441
Secure Audit Logging with Tamper-Resistant Hardware
Secure perimeter schemes (e.g. DRM) and tracing traitor schemes (e.g. watermarking, audit logging) strive to mitigate the problems of content escaping the control of the rights holder. Secure audit logging records the user's actions on content and enables detection of some forms of tampering with the logs. We implement Schneier and Kelsey's secure audit logging protocol, strengthening the protocol by using tamper-resistant hardware (an iButton) in two ways: Firstly our implementation of the protocol works offline as well as online. Secondly, we use unforgeable time stamps to increase the possibilities of fraud detection. We provide a performance assessment of our implementation to show under which circumstances the protocol is practical to use.
7761822
An integrated system-on-chip test framework
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.