502799
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers. We leverage an existing full-system functional simulation infrastructure (Simics [14]) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system and microprocessors. This simulator infrastructure enables us to run architectural experiments using a suite of scaled-down commercial workloads [3]. To enable other researchers to more easily perform such research, we have released these timing simulator modules as the Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset, release 1.0, under GNU GPL [9].
7022714
Simulating a $2M Commercial Server on a $2K PC
As dependence on database management systems and Web servers increases, so does the need for them to run reliably and efficiently-goals that rigorous simulations can help achieve. Execution-driven simulation models system hardware. These simulations capture actual program behavior and detailed system interactions. The authors have developed a simulation methodology that uses multiple simulations, pays careful attention to the effects of scaling on workload behavior, and extends Virtutech AB's Simics full system functional simulator with detailed timing models. The Wisconsin Commercial Workload Suite contains scaled and tuned benchmarks for multiprocessor servers, enabling full-system simulations to run on the PCs that are routinely available to researchers.
53245552
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
In this article, we first show that existing net ordering formulations to minimize noise are no longer sufficient with the presence of inductive noise, and shield insertion is needed to minimize inductive noise. Using a Keff model as the figure of merit for inductive coupling, we then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a minimal area SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a minimal area SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NP-hard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 51p to 82p fewer shields compared to uniform shield insertion and net ordering (US + NO), and uses from 4p to 47p fewer shields compared to separated net ordering and shield insertion (NO + SI). Furthermore, the SINO/NB solutions under practical noise bounds use from 38p to 61p fewer shields compared to SINO/NF solutions, and use up to 36p fewer shields compared to the theoretical lower bound for optimal SINO/NF solutions. Moreover, we show that the Keff model has a high fidelity versus the noise voltage computed using accurate RLC circuit models and SPICE simulations. To the best of our knowledge, it is the first work that presents an in-depth study on the automatic layout optimization of multiple nets to minimize both capacitive and inductive noise.
1185541
A serializability violation detector for shared-memory server programs
We aim to improve reliability of multithreaded programs by proposing a dynamic detector that detects potentially erroneous program executions and their causes. We design and evaluate a Serializability Violation Detector (SVD) that has two unique goals: (I) triggering automatic recovery from erroneous executions using backward error recovery (BER), or simply alerting users that a software error may have occurred; and (II) helping debug programs by revealing causes of error symptoms.Two properties of SVD help in achieving these goals. First, to detect only erroneous executions, SVD checks serializability of atomic regions, which are code regions that need to be executed atomically. Second, to improve usability, SVD does not require a priori annotations of atomic regions; instead, SVD approximates them using a heuristic. Experimental results on three widely-used multithreaded server programs show that SVD finds real bugs and reports modest false positives. The goal of this paper is to develop a detector suitable for (I) BER-based avoidance of erroneous program executions; and (II) alerting users as software errors occur. We argue that such a detector should have the following two properties.
441080
An efficient model for frequency-dependent on-chip inductance
this paper, we propose an ecient table-based model for frequency-dependent on-chip inductance, and apply it to com- pute mutual inductance between random wires and loop induc- tance for cascade wires, respectively. Our inductance computa- tion achieves around 5% error when compared to the numerical solution, and matches frequency-dependent impact very well. We also apply the inductance model to generate RLC circuit models for on-chip interconnects, and present a complexity- ecient normalized RLC circuit model for multiple parallel wires. These results are extremely ecient, and can be eectively used during iterative design procedure. Further, the table-based in- ductance model has been implemented as a Web-based tool to generate inductance matrix for given random wires.
1971121
A "flight data recorder" for enabling full-system multiprocessor deterministic replay
Debuggers have been proven indispensable in improving software reliability. Unfortunately, on most real-life software, debuggers fail to deliver their most essential feature --- a faithful replay of the execution. The reason is non-determinism caused by multithreading and non-repeatable inputs. A common solution to faithful replay has been to record the non-deterministic execution. Existing recorders, however, either work only for datarace-free programs or have prohibitive overhead.As a step towards powerful debugging, we develop a practical low-overhead hardware recorder for cachecoherent multiprocessors, called Flight Data Recorder (FDR). Like an aircraft flight data recorder, FDR continuously records the execution, even on deployed systems, logging the execution for post-mortem analysis.FDR is practical because it piggybacks on the cache coherence hardware and logs nearly the minimal threadordering information necessary to faithfully replay the multiprocessor execution. Our studies, based on simulating a four-processor server with commercial workloads, show that when allocated less than 7% of system's physical memory, our FDR design can capture the last one second of the execution at modest (less than 2%) slowdown.
10735574
Forwarding indices of folded n-cubes
For a given connected graph G of order n, a routing R is a set of n(n - 1) elementary paths specified for every ordered pair of vertices in G. The vertex (resp. edge) forwarding index of a graph is the maximum number of paths of R passing through any vertex (resp. edge) in the graph. In this paper, the authors determine the vertex and the edge forwarding indices of a folded n-cube as (n-1)2n-1 +1-((n+l)/2) (n ⌊n+1/2⌋) and 2n-(n,⌊n+1/2⌋),respectively.
13407089
Event detection and period extraction using multi-scale symmetry and entropy
We present a system for detecting discrete periodic events over a short interval and in the presence of interference. In the first stage symmetries are identified using scale-space representation. This process detects signal events with a low signal-to-noise ratio but has the potential to introduce a number of false responses. This process is followed by an entropy-based algorithm that can robustly extract periodicities from a set of observed discrete events in the presence of a large number of false alarms. The event detection and period extraction processes have a low computational cost and can extract signal periodicity after a short observation time. This scheme was evaluated against four previously reported methods. Results demonstrate that the period extraction algorithm presented here is more reliable than three of the previously reported algorithms. The reliability of the algorithm presented here was similar to that of the fourth method but the computational cost was much less.
1797921
Arc-transitive circulant digraphs of odd prime-power order
In this paper, the full automorphism group of a circulant digraph of prime-power order is investigated, and as a result, a complete classification of arc-transitive circulant graphs of odd prime-power order is given.
207795841
Automorphism groups of tetravalent Cayley graphs on regular p-groups
Let Cay(G,S) be a connected tetravalent Cayley graph on a regular p-group G and let Aut(G) be the automorphism group of G. In this paper, it is proved that, for each prime p 2,5, the automorphism group of the Cayley graph Cay(G,S) is the semidirect product R(G)@?Aut(G,S) where R(G) is the right regular representation of G and Aut(G,S)={@[email protected]?Aut(G)|S^@a=S}. The proof depends on the classification of finite simple groups. This implies that if p 2,5 then the Cayley graph Cay(G,S) is normal, namely, the automorphism group of Cay(G,S) contains R(G) as a normal subgroup.
19879470
The multiscale medial properties of interfering image structures
The multiscale medial axis (MMA) is a robust shape representation in analysing objects in greylevel images. It is computed as ridges in the medialness scale-space of an image. In this paper the multiscale medial properties of overlapping objects are investigated, the result of which is novel to the community in that the existing studies only concentrated on isolated objects. To improve the distinguishability of these objects, a sliding window algorithm is proposed to detect locally optimal scale ridges in scale space. When used in the medialness scale-space of an image, this efficient method can extract a complete set of MMAs for interfering objects, in contrast with the globally optimal scale ridge definition which has been widely used. This is demonstrated in the applications in medical images.