2734062
A design diversity metric and reliability analysis for redundant systems
Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs. Based on this metric, we derive analytical reliability models that show a simple relationship between design diversity, system failure rate, and mission time. In addition, we present simulation results to demonstrate the effectiveness of design diversity in Duplex and Triple Modular Redundant (TMR) systems. For independent multiple-module failures, we show that, mere use of different implementations does not always guarantee higher reliability compared to redundant systems with identical implementations-it is important to analyze the reliability of redundant systems using our metric. For common-mode failures and design faults, there is a significant gain in using different implementations-however, as our analysis shows, the gain diminishes as the mission time increases. Our simulation results also demonstrate the usefulness of diversity for enhancing the self-testing properties of redundant systems.
5825110
Debating the Future of Burn-In
35844193
Design for testability and testing of IEEE 1149.1 TAP controller
The Test Access Port (TAP) controller is a very important circuit present in all IC chips that are compliant with the IEEE 1149.1 Boundary Scan standard. Although the main purpose of boundary scan is to facilitate board-level testing, it is also used for many other testing and non-testing purposes (e.g., memory and logic BIST wrappers to enable embedded core test, programming FPGAs, checkpointing and recovery of dependable systems, etc.). Hence, it is important to thoroughly test the TAP controller before using it for other purposes. In this paper, we present techniques for designing and testing the TAP controller. Our design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results. Our TAP controller design technique does not require any extra I/O pins and can be easily automated and incorporated into test tools.
206458818
Delay defect characteristics and testing strategies
Several factors influence production delay testing and corresponding DFT techniques: defect sources, design styles. ability to monitor process characteristics, test generation time. available test time, and tester memory. We present an overview of delay defect characteristics and the impact of delay defects on IC quality. We also discuss practical delay-testing strategy in terms of test pattern generation, test application speed, DFT, and test cost.
18607273
X-tolerant test response compaction
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.
5916562
Testing digital circuits with constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of logic values in digital circuits and two techniques for preventing them from damaging the circuit or corrupting the test results. The hardware overhead of our technique is minimal and imposes negligible delay overhead. Simulation results show that the area overhead of our techniques is less than 1%. Unlike previous techniques, the fault coverage of the legal test patterns in a given test set is not sacrificed with our techniques. Furthermore, our techniques are applicable during IC production test, BIST, board-level tests and system-level tests.
6745026
Translating Timed I/O Automata Specifications for Theorem Proving in PVS
Timed Input/Output Automaton (TIOA) is a mathematical framework for specification and analysis of systems that involve discrete and continuous evolution. In order to employ an interactive theorem prover in deducing properties of a TIOA, its state-transition based description has to be translated to the language of the theorem prover. In this paper, we describe a tool for translating TIOA to the language of the Prototype Verification System (PVS)—a specification system with an integrated interactive theorem prover. We describe the translation scheme, discuss the design decisions, and briefly present three case studies to illustrate the application of the translator in the verification process.
9622081
Modular Rough Fuzzy MLP: Evolutionary Design
The article describes a way of designing a hybrid system for classification and rule generation, integrating rough set theory with a fuzzy MLP using an evolutionary algorithm. An l-class classification problem is split into l two-class problems. Crude subnetworks are initially obtained for each of these two-class problems via rough set theory. These subnetworks are then combined and the final network is evolved using a GA with restricted mutation operator which utilizes the knowledge of the modular structure already generated, for faster convergence.
1899140
Learning Cycle-Linear Hybrid Automata for Excitable Cells
We show how to automatically learn the class of Hybrid Automata called Cycle-Linear Hybrid Automata (CLHA) in order to model the behavior of excitable cells. Such cells, whose main purpose is to amplify and propagate an electrical signal known as the action potential (AP), serve as the "biologic transistors" of living organisms. The learning algorithm we propose comprises the following three phases: (1) Geometric analysis of the APs in the training set is used to identify, for each AP, the modes and switching logic of the corresponding Linear Hybrid Automata. (2) For each mode, the modified Prony's method is used to learn the coefficients of the associated linear flows. (3) The modified Prony's method is used again to learn the functions that adjust, on a per-cycle basis, the mode dynamics and switching logic of the Linear Hybrid Automata obtained in the first two phases. Our results show that the learned CLHA is able to successfully capture AP morphology and other important excitable-cell properties, such as refractoriness and restitution, up to a prescribed approximation error. Our approach is fully implemented in MATLAB and, to the best of our knowledge, provides the most accurate approximation model for ECs to date.
3106881
Path vector face routing: geographic routing with local face information
Existing geographic routing algorithms depend on the planarization of the network connectivity graph for correctness, and the planarization process gives rise to a well-defined notion of "faces". In this paper, we demonstrate that we can improve routing performance by storing a small amount of local face information at each node. We present a protocol, path vector exchange (PVEX), that maintains local face information at each node efficiently, and a new geographic routing algorithm, greedy path vector face routing (GPVFR), that achieves better routing performance in terms of both path stretch and hop stretch than existing geographic routing algorithms by exploiting available local face information. Our simulations demonstrate that GPVFR/PVEX achieves significantly reduced path and hop stretch than greedy perimeter stateless routing (GPSR) and somewhat better performance than greedy other adaptive face routing (GOAFR+) over a wide range of network topologies. The cost of this improved performance is a small amount of additional storage, and the bandwidth required for our algorithm is comparable to GPSR and GOAFR+ in quasi-static networks.
13253511
Verifying Average Dwell Time by Solving Optimization Problems
A switched system is a hybrid system whose discrete mechanisms are abstracted away in terms of an exogenous switching signal which brings about the mode switches. For switched systems, the Average Dwell time (ADT) property defines restricted classes of switching signals which can be used for proving stability. In this paper, we develop optimization-based methods for automatically verifying ADT properties of hybrid systems. This enables us to prove stability of hybrid systems, provided the individual modes of the system are stable. For two special classes of hybrid systems, we show that the resulting optimization problems can indeed be solved efficiently using standard mathematical programming techniques. We also present simulation relation-based proof methods for establishing equivalence of hybrid systems with respect to ADT. The proposed methods are applied to verify ADT properties of a linear hysteresis switch and a nondeterministic thermostat.