7075872
Lookback:a new way of exploiting parallelism in discrete event simulation
Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performance on the Closed Queuing Network (CQN) simulation is discussed. We also discuss in detail the relation between lookahead and lookback. Finally, we demonstrate that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.
2548796
Four types of lookback
We present a classification that groups lookback into four types: direct strong lookback, universal strong lookback, direct weak lookback, and universal weak lookback. They are defined in terms of absolute and dynamic impact times. We discuss relationships between lookback types by considering when rollbacks and/or antimessages are avoided. From different types of lookback, we also derive three optimization techniques for optimistic simulation and point out their advantages over lazy cancellation. Finally, we show that all four types of lookback exist in the PCS network simulation and can be exploited by either lookback-based or optimistic protocols.
2371887
Locality-conscious process scheduling in embedded systems
In many embedded systems, the existence of a data cache might influence the effectiveness of process scheduling policy significantly. Consequently, a scheduling policy that takes inter-process data reuse into account might result in large performance benefits. In this paper, we focus on array-intensive embedded applications and present a locality-conscious scheduling strategy where we first evaluate the potential data reuse between processes, and then, using the results of this evaluation, select an order for process executions. We also show how process codes can be transformed by an optimizing compiler for increasing inter-process data reuse, thereby making locality-conscious scheduling more effective. Our experimental results obtained using two large, multi-process application codes indicate significant runtime benefits.
9256979
Convergence of difference schemes with high resolution for conservation laws
We are concerned with the convergence of Lax-Wendroff type schemes with high resolution to the entropy solutions for conservation laws. These schemes include the original Lax-Wendroff scheme proposed by Lax and Wendroff in 1960 and its two step versions-the Richtmyer scheme and the MacCormack scheme. For the convex scalar conservation laws with algebraic growth flux functions, we prove the convergence of these schemes to the weak solutions satisfying appropriate entropy inequalities. The proof is based on detailed L P estimates of the approximate solutions, H -1 compactness estimates of the corresponding entropy dissipation measures, and some compensated compactness frameworks. Then these techniques are generalized to study the convergence problem for the nonconvex scalar case and the hyperbolic systems of conservation laws.
21308144
EmoEars: An Emotion Recognition System for Mandarin Speech
In this paper, an emotion recognition system for mandarin speech is presented. Five basic human emotions including angry, fear, happy, neutral and sad are investigated. The recognizer is based on neural network with OCON and ACON architecture. Some novel feature selection methods are also added as optional tool to enhance the efficiency and classification accuracy. The system can train speaker dependent emotion speech model through online emotional utterance recording. Experiment results show that emotion can be recognized through neural network model, the best mean accuracy is 86.7%. In addition, the feature selection module is effective to reduce the compute load and increase the generalization ability of the recognizer.
17810541
An adaptive locality-conscious process scheduler for embedded systems
A critical component of a real-time operating system (RTOS) is its process scheduler. While the prior research on process scheduling focuses mostly on meeting hard/soft deadlines, preemption and priory assignment related issues, problems arise from existence of cache memories are largely ignored. Focusing on data accesses and a cache based embedded system, this paper proposes an adaptive locality-conscious process scheduling algorithm. The main goal of the proposed algorithm is to exploit (reuse) the contents of the on-chip cache memory to the highest extent possible. The algorithm tries to achieve its goal by determining the order in which the processes get scheduled such that the successively-executing processes share a large number of data elements. We implemented our scheduler within a customized simulation platform and simulated it using a set of benchmark codes. Our experimental results reveal that the proposed scheduling algorithm is very successful in practice, and reduces process completion times significantly for both rate-monotonic scheduling (RMS) and earliest-deadline-first scheduling (EDF). We also explain how process code transformations can be used for increasing the savings achieved by the locality-conscious scheduler, and show how the proposed approach operates with a base scheduler such as RMS and EDF.
7830647
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as well. This paper embarks on a new philosophy for reducing the number of accesses to the instruction TLB (iTLB) for power and performance optimizations. The overall idea is to keep a translation currently being used in a register and avoid going to the iTLB as far as possible --- until there is a page change. We propose four different approaches for achieving this, and experimentally demonstrate that one of these schemes that uses a combination of compiler and hardware enhancements can reduce iTLB dynamic power by over 85% in most cases.These mechanisms can work with different instructioncache (iL1) lookup mechanisms and achieve significant iTLB power savings without compromising on performance. Their importance grows with higher iL1 miss rates and larger page sizes. They can work very well with large iTLB structures, that can possibly consume more power and take longer to lookup, without the iTLB getting into the common case. Further, we also experimentally demonstrate that they can provide performance savings for virtually-indexed, virtually-tagged iL1 caches, and can even make physically indexed, physically-tagged iL1 caches a possible choice for implementation.