2982914
Network topology exploration of mesh-based coarse-grain reconfigurable architectures
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these architectures: (a) changing the interconnection between PEs; (b) changing the way the network topology is traversed while mapping operations to the PEs; and (c) changing the communication delays on the interconnects between PEs. We propose network topology traversal strategies that first schedule PEs that are spatially close and that have more interconnections among them. We use an interconnect aware list scheduling heuristic as a vehicle to perform the network topology exploration experiments on a set of designs derived from DSP applications. Our experimental results show that a spiral traversal strategy, coupled with a two neighbor interconnect topology leads to good performance for the DSP benchmarks considered. Our prototype framework thus provides an exploration environment for system architects to explore and tune coarse-grain reconfigurable architectures for particular application domains.
1533259
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with little or no resource constraints but tight bounds on the cycle time. Extreme parallelization, conditional and speculative execution of operations is essential to meet the processor performance goals. However, this is a tedious task for which classical high-level synthesis (HLS) formulations are inadequate and thus rarely used. In this paper, we present a new methodology for application of HLS targeted to such microprocessor functional blocks that can potentially speed up the design space exploration for microprocessor designs. Our methodology consists of a coordinated set of source-level and fine-grain parallelizing compiler transformations that targets these behavioral descriptions, specifically loop constructs in them and enables efficient chaining of operations and high-level synthesis of the functional blocks. As a case study in understanding the complexity and challenges in the use of HLS, we walk the reader through the detailed design of an instruction length decoder drawn from the Pentium®-family of processors. The chief contribution of this paper is formulation of a domain-specific methodology for application of high-level synthesis techniques to a domain that rarely, if ever, finds use for it.
15929474
Optimal offline and online registration techniques for location management with overlapping registration areas
Personal communication services (PCS) standards such as the IS-41 and the GSM use a location management scheme, which is based on registration areas (RA). Overlapping of registration areas has been proposed to reduce the overhead of location updates in such systems. Overlapping provides multiple choices for the selection of a registration area, a feature that does not appear in environments of nonoverlapping RAs. In this paper, we demonstrate how the choice of a registration area affects the number of subsequent registrations and define the problem of optimal choice based on minimization of subsequent registrations. We study two versions of the problem: 1) the deterministic (or offline) version, in which the entire trajectory of the mobile unit is known a priori, and 2) the stochastic (or online) version, in which the trajectory of the mobile unit is not known a priori, but the system has the knowledge of the mobility pattern of the mobile. The mobility pattern is modeled as a random walk across coverage area. In the deterministic case, the method presented computes an optimal solution to the registration problem. In the stochastic case, we present a method that determines the registration that minimizes the expected number of registrations by looking ahead in the probable future paths of the mobile unit. The algorithm's time complexity has exponential dependence on the length of the look-ahead. The cost of search is independent of the choice, therefore the algorithm does not increase the search cost. We also consider an alternative cost model for the stochastic case and propose a preemptive and a nonpreemptive approach each of which incurs different numbers of hard and soft registration operations. Simulation results show a reduction of 25-30 percent in number of registrations over a random-choice scheme. This can be translated to 5-20 percent effective location management load reduction for most cases, subject to the call-to-mobility ratio (CMR) of a mobile unit and search-cost-to-update-cost ratio (CCR) in the network.
8454699
An Efficient Geometric Algorithm For Extracting Structural Elements to Facilitate Automated MEMS Extraction
Micro-electro-mechanical systems (MEMS) are very small devices that contain both mechanical and electrical elements with sizes in the order of microns. Design cycle time is an important consideration in the development and introduction of MEMS devices in the market. To develop extraction tools for MEMS designs, we need geometric algorithms to analyze the spatial layout of the mechanical portion of the MEMS device and extract a net-list of mechanical components. Such extracted net-list of mechanical components can be combined with the electronic component net-list to provide the complete device schematic. A key step in the extraction of mechanical elements is classification of various portions of the layout into structural elements. Because MEMS designs consist of a large number of elements, computational efficiency of the underlying extraction algorithm is very important for it to work on complex devices. This paper describes an efficient geometric algorithm for extracting structural elements from spatial layout of MEMS designs.
76622
Machining feature-based similarity assessment algorithms for prismatic machined parts
Abstract This paper presents algorithms for identifying machined parts in a database that are similar to a given query part based on machining features. In this paper we only consider parts that are machined on 3-axis machining centers. We utilize reduced feature vectors consisting of machining feature access directions, feature types, feature volumes, feature dimensional tolerances and feature group cardinality as a basis for assessing shape similarity. We have defined a distance function between two sets of reduced feature vectors to assess the similarity between them from the machining effort point of view. To assess the similarity between the two parts, one set of reduced feature vectors is transformed in space using rigid body transformations with respect to the other set such that the distance between them is minimized. The distance between the two sets of aligned reduced feature vectors is used as a measure of similarity between the two parts. The existing machined parts are rank ordered based on the value of the distance with respect to the query part. The cost of previously machined parts that have a very small distance from the query part can be used as a basis for estimating the cost of machining the new part.
17496994
On finding optimal registrations in presence of overlapping registration areas
Personal Communication Services (PCS) standards such as IS-41 and GSM use a location management scheme which is based on registration areas (RA). Overlapping of registration areas has been proposed to reduce the overhead of location updates in such systems (4]. Overlapping RAs form regions in which a mobile has a choice in selecting which RA to register to. The choice of current RA has implication on the number of registrations a mobile may require in the future. In this paper we investigate the problem of finding the best (or optimal) registration for a user in a cellular PCS environment with overlapping Registration Areas (RAs). We study two versions of the problem: (i) the deterministic version, where the entire trajectory of the mobile is known a-priori, and (ii) the stochastic version, where the trajectory of the mobile is not known a-priori but the system has the knowledge of mobility pattern of the mobile. The mobility pattern is modeled as a stochastic random walk across regions. In the deterministic case the method presented computes an optimal solution to the registration problem. In the stochastic case we present a method which determines the registration which minimizes the expected number of registrations by looking ahead at the probable paths which may be traversed by the mobile in future. The paper also proposes a preemptive and a non-preemptive version of the stochastic method which incur different numbers of hard and soft registration operations.
12873659
TARA: Thermal-Aware Routing Algorithm for Implanted Sensor Networks
Implanted biological sensors are a special class of wireless sensor networks that are used in-vivo for various medical applications. One of the major challenges of continuous in-vivo sensing is the heat generated by the implanted sensors due to communication radiation and circuitry power consumption. This paper addresses the issues of routing in implanted sensor networks. We propose a thermal-aware routing protocol that routes the data away from high temperature areas (hot spots). With this protocol each node estimates temperature change of its neighbors and routes packets around the hot spot area by a withdraw strategy. The proposed protocol can achieve a better balance of temperature rise and only experience a modest increased delay compared with shortest hop, but thermal-awareness also indicates the capability of load balance, which leads to less packet loss in high load situations.