5297326
Parametric Circuit Representation Using Inductive Boolean Functions
We have developed a methodology based on symbolic manipulation of inductive Boolean functions (IBFs) for formal verification of inductively-defined hardware. This methodology combines the techniques of reasoning by induction and symbolic tautologychecking in an automated and potentially efficient way. In this paper, we describe a component of this methodology that regards various mechanisms used to represent inductivelydefined circuits in the form of IBFs. The focus is on general parameterization issues, such as multiple parameter functions, multiple output functions, interaction of different parameters for supporting compositions etc. These mechanisms, which may be useful in other applications involving parametric circuit descriptions, are illustrated through practical circuit examples along with preliminary results. We also describe an application of our formal verification methodology, where a proof by induction is performed by automatic symbolic manipulation of parametric circuit representations.
685138
Tradeoffs in canonical sequential function representations
State space exploration is of prime importance in the study of finite state sequential systems, with several efforts aimed at compact representation of the state space in order to tackle the state explosion problem. In the work presented on formal verification of inductively-defined hardware, we have identified a useful class of Boolean functions called linearly inductive functions (LIFs). We explore the relationship between our LIF representation and the classic DFA (deterministic finite state automaton) representation of a sequential function, and examine the associated tradeoffs. We show that our LIF representation corresponds to a minimal reverse DFA, i.e. a minimal DFA which accepts the language consisting of the reverse input strings, where our implicit method for obtaining an LIF representation does not require explicit construction of a forward DFA. Its practical usefulness arises from our demonstration that reverse DFAs for several datapath circuits are exponentially more compact than the classic forward DFAs. Furthermore, in comparison to the traditional representation of DFAs as state transition diagrams, our LIF representations allow for state-sharing while maintaining decomposition, resulting in memory savings in practice.<<ETX>>
25366029
Formal hardware verification methods: A survey
Growing advances in VLSI technology have led to an increased level of complexity in current hardware systems. Late detection of design errors typically results in higher costs due to the associated time delay as well as loss of production. Thus it is important that hardware designs be free of errors. Formal verification has become an increasingly important technique towards establishing the correctness of hardware designs. In this article we survey the research that has been done in this area, with an emphasis on more recent trends. We present a classification framework for the various methods, based on the forms of the specification, the implementation, and the proff method. This framework enables us to better highlight the relationships and interactions between seemingly different approaches.
8920735
Partition-based decision heuristics for image computation using SAT and BDDs
Methods based on Boolean satisfiability (SAT) typically use a conjunctive normal form (CNF) representation of the Boolean formula, and exploit the structure of the given problem through use of various decision heuristics and implication methods. We propose a new decision heuristic based on separator-set induced partitioning of the underlying CNF graph. It targets those variables whose choice generates clause partitions with disjoint variable supports. This can potentially improve performance of SAT applications by decomposing the problem dynamically within the search. In the context of a recently proposed image computation method combining SAT and BDDs, this results in simpler BDD subproblems. We provide algorithms for CNF partitioning - one based on a clause-variable dependency matrix, and another based on standard hypergraph partitioning techniques, and also for the use of partitioning information in decision heuristics for SAT. The effectiveness of the proposed partition-based heuristic is shown with practical results for reachability analysis of benchmark sequential circuits.
7444548
A wavelet data model for image databases
This paper defines wavelet transforms as a datatype suitable for inclusion in databases and an algebra for the manipulation of this data type.
8665183
Dynamic detection and removal of inactive clauses in SAT with application in image computation
In this paper, we present a new technique for the efficient dynamic detection and removal of inactive clauses, i.e. clauses that do not affect the solutions of interest of a Boolean satisfiability (SAT) problem. The algorithm is based on the extraction of gate connectivity information during generation of the Boolean formula from the circuit, and its use in the inner loop of a branch-and-bound SAT algorithm. The motivation for this optimization is to exploit the circuit structure information, which can be used to find unobservable gates at circuit outputs under dynamic conditions. It has the potential to speed up all applications of SAT in which the SAT formula is derived from a logic circuit. In particular, we find that it has considerable impact on an image computation algorithm based on SAT. We present practical results for benchmark circuits which show that the use of this optimization consistently improves the performance for reachability analysis, in some cases enabling the prototype tool to reach more states than otherwise possible.
326701
A modeling and execution environment for distributed scientific workflows
We illustrate how a domain scientist can perform a complex scientific task by interleaving data access, querying, and manipulation, as well as analytical steps and computations in complex, problem specific ways. We show how our system is used by a geneticist for solving the problem of discovering the so-called "co-regulated" genes by interlinking data and computation from several Web sites, local computations, as well as local and remote databases. The main distinctive features of our system (compared, e.g., to the ZOO environment (Ioannidis et al., 1996)) include: (i) executable workflows run as Web services; (ii) abstract workflows employ concept names and semantic types that are higher-level (and thus more "scientist friendly") than executable workflows; and (iii) our system supports automatic translation of the latter into the former.
39505715
Iterative Abstraction using SAT-based BMC with Proof Analysis