41028818
DFT assisted built-in soft error resilience
In this talk, we describe a new paradigm to design in soft error resilience by reusing already existent on-chip DFT resources. For example, scan systems that are required for manufacturing test and debug involve significant circuitry that are used only during post-silicon debug and production testing. These resources are then left unused throughout the entire lifetime of the product as they are not required for normal system operation. These structures continue to occupy additional silicon area and draw additional leakage power. We demonstrate how to reuse these scan resources to enable a built-in soft error resilience (BISER) design paradigm. These circuits result in more than 20 times reduction in soft error rate while incurring a system-level power overhead of 3-5%. Additional power-saving techniques are possible. The BISER techniques produce the best results in terms of power, performance and area overheads (when all 3 attributes are considered) compared to traditional major redundancy techniques. These techniques are also suitable for adaptive applications targeting a wide range of applications (e.g., networking ASICs, microprocessors) with various power, performance and soft error rate trade-offs.
2705949
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
2734062
A design diversity metric and reliability analysis for redundant systems
Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs. Based on this metric, we derive analytical reliability models that show a simple relationship between design diversity, system failure rate, and mission time. In addition, we present simulation results to demonstrate the effectiveness of design diversity in Duplex and Triple Modular Redundant (TMR) systems. For independent multiple-module failures, we show that, mere use of different implementations does not always guarantee higher reliability compared to redundant systems with identical implementations-it is important to analyze the reliability of redundant systems using our metric. For common-mode failures and design faults, there is a significant gain in using different implementations-however, as our analysis shows, the gain diminishes as the mission time increases. Our simulation results also demonstrate the usefulness of diversity for enhancing the self-testing properties of redundant systems.
900289
Techniques and algorithms for fault grading of FPGA interconnect test configurations
Conventional fault simulation techniques for field programmable gate arrays (FPGAs) are very complicated and time consuming. The alternative, FPGA fault emulation technique, is incomplete and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. The presented technique is able to report all detectable and undetectable faults and, compared with conventional methods, is orders of magnitude faster.
18607273
X-tolerant test response compaction
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.
2397835
Speed clustering of integrated circuits
Experimental data on 0.18 /spl mu/ test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.
2481844
Proving Atomicity: An Assertional Approach
Atomicity (or linearizability) is a commonly used consistency criterion for distributed services and objects. Although atomic object implementations are abundant, proving that algorithms achieve atomicity has turned out to be a challenging problem. In this paper, we initiate the study of systematic ways of verifying distributed implementations of atomic objects, beginning with read/write objects (registers). Our general approach is to replace the existing operational reasoning about events and partial orders with assertional reasoning about invariants and simulation relations. To this end, we define an abstract state machine that captures the atomicity property and prove correctness of the object implementations by establishing a simulation mapping between the implementation and the specification automata. We demonstrate the generality of our specification by showing that it is implemented by three different read/write register constructions: the message-passing register emulation of Attiya, Bar-Noy and Dolev, its optimized version based on real time, and the shared memory register construction of Vitanyi and Awerbuch. In addition, we show that a simplified version of our specification is implemented by a general atomic object construction based on the Lamport’s replicated state machine algorithm.
45398591
A One Bit Facial Asymmetry Code (FAC) in Fourier Domain for Human Recognition
The present paper introduces a novel set of biometrics based on facial asymmetry measures in the frequency domain using a compact one-bit representation. A simplistic Hamming distance-type classifier is proposed as a means for matching bit patterns for identification purposes which is more efficient than PCA-based classifiers from storage and computation point of view, and produces equivalent results. A comparison with spatial intensity-based asymmetry measures suggests that our proposed measures are more robust to intra-personal distortions with a misclassification rate of only 4.24% on the standard facial expression database (Cohn-Kanade) consisting of 55 individuals. In addition, a rigorous statistical analysis of the matching algorithm is presented. The role of asymmetry of different face parts (e.g., eyes, mouth, nose) is investigated to determine which regions provide the maximum discrimination among individuals under different expressions.
3106881
Path vector face routing: geographic routing with local face information
Existing geographic routing algorithms depend on the planarization of the network connectivity graph for correctness, and the planarization process gives rise to a well-defined notion of "faces". In this paper, we demonstrate that we can improve routing performance by storing a small amount of local face information at each node. We present a protocol, path vector exchange (PVEX), that maintains local face information at each node efficiently, and a new geographic routing algorithm, greedy path vector face routing (GPVFR), that achieves better routing performance in terms of both path stretch and hop stretch than existing geographic routing algorithms by exploiting available local face information. Our simulations demonstrate that GPVFR/PVEX achieves significantly reduced path and hop stretch than greedy perimeter stateless routing (GPSR) and somewhat better performance than greedy other adaptive face routing (GOAFR+) over a wide range of network topologies. The cost of this improved performance is a small amount of additional storage, and the bandwidth required for our algorithm is comparable to GPSR and GOAFR+ in quasi-static networks.
10906898
The Role of Statistical Models in Biometric Authentication
The current paper demonstrates the role of statistical models in authentication tasks – both in system development and in performance evaluation. We first introduce a model-based face authentication system based on the Fourier domain phase using Gaussian Mixture Models (GMM) which yields verification error rates as low as 0.3% on a face database of 65 individuals with extreme illumination variations. We then present a statistical framework for predicting authentication error rates for future populations in a rigorous way. This is in contrast to most evaluation protocols used today that are based on observational studies and valid only for the databases at hand. Applications establish that our model-based approach has better predictive performance than an existing state-of-the-art authentication technique.
206590610
Modeling Phase Spectra Using Gaussian Mixture Models for Human Face Identification
It has been established that information distinguishing one human face from another is contained to a large extent in the Fourier domain phase component of the facial image. However, to date, formal statistical models for this component have not been deployed in face recognition tasks. In this paper we introduce a model-based approach using Gaussian mixture models (GMM) for the phase component for performing human identification. Classification and verification are performed using a MAP estimate and we show that we are able to achieve identification error rates as low as 2% and verification error rates as low as 0.3% on a database with 65 individuals with extreme illumination variations. The proposed method is easily able to deal with other distortions such as expressions and poses, and hence this establishes its robustness to intra-personal variations. A potential use of the method in illumination normalization is also discussed.