14126389
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.
23543872
Register Transfer Level Synthesis: From Theory to Practice
10085601
Considering circuit observability don't cares in CNF satisfiability
Boolean satisfiability (SAT) has seen significant use in various tasks in circuit verification. A key contributor to the efficiency of contemporary SAT solvers is fast deduction using Boolean constraint propagation (BCP). This can be efficiently implemented with a conjunctive normal form (CNF) representation of a circuit. However, most circuit verification tasks start from a logic circuit description of the problem instance. A simple conversion from a logic circuit to a CNF (Tseitin, G.S., 1968), that enables the use of the CNF representation even for circuit verification tasks, loses some information regarding the structure of the circuit. One example of such structural information is circuit observability don't cares. Several recent papers have addressed the issue of handling circuit unobservability in CNF-based SAT, but none of them accurately captures the conditions for use of this information in all stages of a CNF-based SAT solver. To take such don't care information into consideration in a CNF-based SAT solver, we propose a broader approach that adds certain don't care literals to clauses in the CNF representation. These literals are treated differently at different times during the solution process, much like don't cares in logic synthesis. The major merit of this scheme is that the solver can continue to use this don't care information during the learning process, which is an important part of contemporary SAT solvers. We have implemented this approach in the zChaff SAT solver and experiments show that significant performance gain can be obtained.
2094926
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification problems can be formulated as QBF instances. A closely related research area to QBF is Boolean Satisfiability (SAT). Recent advances in SAT research have resulted in some very efficient SAT solvers. One of the critical techniques employed in these solvers is Conflict Driven Learning. In this paper, we adapt conflict driven learning for application in a QBF setting. We show that conflict driven learning can be regarded as a resolution process on the clauses. We prove that under certain conditions, tautology clauses obtained from resolution in QBF also obey the rules for implication and conflicts of regular (non-tautology) clauses; and therefore they can be treated as regular clauses and used in future search. We have implemented this idea in a new QBF solver called Quaffle and our initial experiments show that conflict driven learning can greatly speed up the solution process for most of the benchmarks we tested.
45769666
Test generation for cyclic combinational circuits
Circuits that have an underlying acyclic topology are guaranteed to be combinational since feedback is necessary for sequential behavior. However, the reverse is not true, i.e., feedback is not a sufficient condition since there do exist combinational logic circuits that are cyclic. Such combinational circuits occur often in bus structures in data paths. This class of circuits has largely been ignored by conventional combinational single-stuck-at fault test pattern generators which assume that the circuit topology is acyclic. There has been no formal study of the test generation problem for these circuits and no algorithms and tools exist for this purpose. In practice, test generation for these circuits is handled in an awkward manner, typically with poor fault coverage. This paper provides, for the first time, a formal analysis of the test generation problem for these circuits. This analysis leads to a clear insight into generation of tests, as well as a classification of untestable faults for such circuits. We demonstrate that unlike acyclic circuits, where an untestable fault corresponds to a redundancy, cyclic combinational circuits may have untestable faults that do not correspond to redundancies. This insight is then translated to a testing algorithm which has been implemented in the program RAM. RAM has been successful is providing almost complete coverage on a range of typical examples, which Is significantly higher than that provided by conventional techniques.
39883686
Delay abstraction in combinational logic circuits
In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. Such abstractions are useful when considering the delay of cascaded circuits in high-level synthesis and other such applications in synthesis. The proposed graphical data structure is called the concise delay network, and is of size proportional to (m+n) in best case, where m and n refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input-output pair has size proportional to m/spl times/n. For circuits with hundreds of inputs and outputs, this storage and the associated computations become quite expensive, especially when they need to be done repeatedly during synthesis. We present heuristic algorithms for deriving these concise delay networks. Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m+n).
188423
Report on the INEX 2004 interactive track
As scientific data repositories, digital libraries and publishers increasingly use the eXtensible Markup Language (XML) for publication and storage interest has arisen in exploiting this formatting for retrieval purposes. XML is attractive because it defines the logical structure of the documents and has the potential to assist IR systems in providing more appropriate results to users, i.e., to return relevant document components (i.e. XML elements) rather than whole documents. In addition, the XML tags often have specific semantics that may be exploited purposefully in IR.
2699297
The Interactive Track at INEX 2004
An interactive track was included in INEX for the first time in 2004. The main aim of the track was to study the behaviour of searchers when interacting with components of XML documents. In this paper, we describe the motivation and aims of the track in detail, we outline the methodology and we present some initial findings from the analysis of the results.