195884052
Token Coherence: decoupling performance and correctness
Many future shared memory multiprocessor servers will both target commercial workloads and use highly integrated "glueless" designs. Implementing low latency cache coherence in these systems is difficult, because traditional approaches either add indirection for common cache to cache misses (directory protocols) or require a totally ordered interconnect (traditional snooping protocols). Unfortunately, totally ordered interconnects are difficult to implement in glueless designs. An ideal coherence protocol would avoid indirections and interconnect ordering; however, such an approach introduces numerous protocol races that are difficult to resolve. We propose a new coherence framework to enable such protocols by separating performance from correctness. A performance protocol can optimize for the common case (i.e., absence of races) and rely on the underlying correctness substrate to resolve races, provide safety, and prevent starvation. We call the combination Token Coherence, since it explicitly exchanges and counts tokens to control coherence permissions. We develop TokenB, a specific Token Coherence performance protocol that allows a glueless multiprocessor to both exploit a low latency unordered interconnect (like directory protocols) and avoid indirection (like snooping protocols). Simulations using commercial workloads show that our new protocol can significantly outperform traditional snooping and directory protocols.
7972983
Using speculation to simplify multiprocessor design
Summary form only given. Modern multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that rare corner-case events behave correctly. We propose using "speculation for simplicity " to enable designers to focus on common-case scenarios. Our approach is to speculate that rare events will not occur and rely on an efficient recovery mechanism to undo the effects of misspeculations. We illustrate the potential of speculation to simplify multiprocessor design with three examples. First, we simplify the design of a directory cache coherence protocol by speculatively relying on point-to-point ordering of messages in an adoptively routed interconnection network. Second, we simplify a snooping cache coherence protocol by treating a rare coherence state transition as a misspeculation. Third, we simplify interconnection network design by removing the virtual channels and then recovering from deadlocks when they occur. Experiments with full-system simulation and commercial workloads show that speculation is a viable approach for simplifying system design. Systems can incur as many as ten recoveries per second due to misspeculations without significantly degrading performance, and our speculatively simplified designs incur far fewer recoveries.
8147536
Active memory: a new abstraction for memory-system simulation
This paper describes the active memory abstraction for memory-system simulation. In this abstraction---designed specifically for on-the-fly simulation, memory references logically invoke a user-specified function depending upon the reference's type and accessed memory block state. Active memory allows simulator writers to specify the appropriate action on each reference, including "no action" for the common case of cache hits. Because the abstraction hides implementation details, implementations can be carefully tuned for particular platforms, permitting much more efficient on-the-fly simulation than the traditional trace-driven abstraction.Our SPARC implementation, Fast-Cache, executes simple data cache simulations two or three times faster than a highly-tuned trace-driven simulator and only 2 to 7 times slower than the original program. Fast-Cache implements active memory by performing a fast table look up of the memory block state, taking as few as 3 cycles on a SuperSPARC for the no-action case. Modeling the effects of Fast-Cache's additional lookup instructions qualitatively shows that Fast-Cache is likely to be the most efficient simulator for miss ratios between 3% and 40%.
3338486
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scalingof transistor and conventional on-chip interconnect performancepresents a major barrier to future high performancesystems. Previous research has focused on wire-centricdesigns that use parallelism, locality, and on-chipwiring bandwidth to compensate for long wire latency.An alternative approach to this problem is to exploitnewly-emerging on-chip transmission line technology toreduce communication latency. Compared to conventionalRC wires, transmission lines can reduce delay by up to afactor of 30 for global wires, while eliminating the needfor repeaters. However, this latency reduction comes at thecost of a comparable reduction in bandwidth.In this paper, we investigate using transmission linesto access large level-2 on-chip caches. We propose a familyof Transmission Line Cache (TLC) designs that representdifferent points in the latency/bandwidth spectrum.Compared to the recently-proposed Dynamic Non-UniformCache Architecture (DNUCA) design, the base TLCdesign reduces the required cache area by 18% andreduces the interconnection network's dynamic powerconsumption by an average of 61%. The optimized TLCdesigns attain similar performance using fewer transmis-sionlines but with some additional complexity. Simulationresults using full-system simulation show that TLC providesmore consistent performance than the DNUCAdesign across a wide variety of workloads. TLC caches arelogically simpler than DNUCA designs, but requiregreater circuit and manufacturing complexity.
12937575
Application-specific protocols for user-level shared memory
Recent distributed shared memory (DSM) systems and proposed shared-memory machines have implemented some or all of their cache coherence protocols in software. One way to exploit the flexibility of this software is to tailor a coherence protocol to match an application's communication patterns and memory semantics. This paper presents evidence that this approach can lead to large performance improvements. It shows that application-specific protocols substantially improved the performance of three application programs-appbt, em3d, and barnes-over carefully tuned transparent shared memory implementations. The speed-ups were obtained on Blizzard, a fine-grained DSM system running on a 32-node Thinking Machines CM-5.<<ETX>>
970409
Fine-grain access control for distributed shared memory
This paper discusses implementations of fine-grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing.
This paper categorizes techniques based on where access control is enforced and where access conflicts are handled. We incorporated three techniques that require no additional hardware into Blizzard, a system that supports distributed shared memory on the CM-5. The first adds a software lookup before each shared-memory reference by modifying the program's executable. The second uses the memory's error correcting code (ECC) as cache-block valid bits. The third is a hybrid. The software technique ranged from slightly faster to two times slower than the ECC approach. Blizzard's performance is roughly comparable to a hardware shared-memory machine. These results argue that clusters of workstations or personal computers with networks comparable to the CM-5's will be able to support the same shared-memory interfaces as supercomputers.
2381269
Track Layouts of Graphs
Graph drawing problems originate from diverse application domains. In some, such as software engineering and cartography, graphs are required to be visualized or drawn in ways that are easy to read and understand. In others, such as VLSI design, graphs are required to be laid out while satisfying some physical constraint. For example, when a drawing is to be displayed on a page or a computer screen, or is to be used for VLSI design, it is important to keep its area/volume small to avoid wasting space. 
More often than not however, the idea of a good drawing, regardless of its purpose, coincides with having no edge crossings or having very few crossings. Unfortunately, whichever of the numerous drawing styles one considers, a problem requiring a crossing minimization of sorts will, almost certainly, be NP -hard. The theory of fixed parameter tractability (FPT) provides a new and promising approach for coping with intractable problems. In the first part of this thesis we apply algorithmic techniques developed in this theory to well-known graph drawing problems. In particular, we contribute efficient FPT algorithms for crossing minimization and planarization problems concerning the 2-layer drawing style. 
In the second part of this thesis we introduce and comprehensively study so-called track layouts of graphs and their subdivisions. A relationship between this combinatorial structure and several well-known types of graph layouts is established, leading to a number of new results. For example, our study of track layouts of bounded treewidth graphs settles an open problem due to Ganley and Heath (2001) regarding queue layouts of such graphs. Moreover, the study also establishes that graphs of bounded treewidth have three-dimensional straight-line grid drawings with linear volume. 
Through the study of track layouts of subdivisions, we determine that every graph with n vertices and m edges has a three-dimensional polyline grid drawing with the vertices on a rectangular prism, O (n + m log n) volume and O (log n) bends per edge.
1926264
L Codes and Number Systems
Abstract The notion of an L code is introduced as a generalization of the customary notion of a code. Attention is focused on unary L codes. where the target alphabet consists of one letter only. Unary L codes can be identified with such number systems where the representation is unique. Surprisingly many unary morphisms are L codes. Furthermore, even for non-L-codes there is only one ‘exceptional length’ We also give a complete classification for the binary case.
28004475
EOL forms
SummaryIn this paper the notions of “L form” and its “interpretations” are introduced to define families of structurally similar L systems. The families of L systems thus defined are studied from a number of different points of view. It is felt that this novel approach will shed new light on many questions concerning L systems.
7533318
Completeness of Context-Free Grammar Forms
The notions of a grammar form and g-interpretation were first introduced in [2]. However, it quickly became apparent, particularly for EOL forms [5], that (strict) interpretations had a wider interest as well as being better motivated mathematically. The study of parsing of grammar forms detailed in [4], the basic investigation in [8] on linear completeness amongst other results, the study of density in [9, lo] and the connections with graph theory shown in [ 1 l] have affirmed this position. The present paper continues the approach of [8] focussing on the characterization of complete grammar forms, that is grammar forms which generate all’ context-free languages. Some decidability problems will also be discussed. For further morivation and background material we refer the reader to [8, 141, while for all unexplained concepts in language theory, see [ 131. After giving the necessary definitions in the remainder of this section we characterize complete grammar forms in Section 2, 3 and 4. In Section 2 we introduce the central concept of expansion spectrum and in Section 3 the recently proved super normal form theorem [ 121, while in Section 4 the characterization is completed and generators and hierarchies are briefly mentioned. Consider context-free grammars G = (V, C, P, S), where Z is the alphabet of terminals, VZ the alphabet of nonterminals, P is the set of productions and
123658090
Simultaneous diagonal flips in plane triangulations
Simultaneous diagonal flips in plane triangulations are investigated. It is proved that every triangulation with n ≥ 6 vertices has a simultaneous flip into a 4-connected triangulation, and that the set of edges to be flipped can be computed in $\cal O$(n) time. It follows that every triangulation has a simultaneous flip into a Hamiltonian triangulation. This result is used to prove that for any two n-vertex triangulations, there exists a sequence of $\cal O$(logn) simultaneous flips to transform one into the other. Moreover, o(log n) simultaneous flips are needed for some pairs of triangulations. The total number of edges flipped in this sequence is $\cal O$(n). The maximum size of a simultaneous flip is then studied. It is proved that every triangulation has a simultaneous flip of at least ${{1}\over{3}}({n}-{2})$ edges. On the other hand, every simultaneous flip has at most n - 2 edges, and there exist triangulations with a maximum simultaneous flip of ${{6}\over{7}}({n}-{2})$ edges. © 2006 Wiley Periodicals, Inc. J Graph Theory 54: 307–330, 2007 
 
A preliminary version of this paper was published in the Proceedings of the 17th Annual ACM-SIAM Symposium on Discrete Algorithms (SODA'06). 
 
Research partially completed at Carleton University and McGill University (Montreal).