17852820
Fault pattern oriented defect diagnosis for memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.
904578
Simulation-based test algorithm generation for random access memories
Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.
14027625
On test and diagnostics of flash memories
Embedded flash memory has been widely used in applications that require non-volatile on-chip storage elements. However, test and diagnostics of flash memories needs further investigation so that the overall cost of the products can be reduced. This paper presents the challenges and issues for test and diagnostics of flash memories, based on our recent experiences. We also suggest improvement of the test and diagnosis flow, including design-for-testability (DFT) using built-in self-test (BIST), built-in self-repair (BISR), and failure analysis. In addition, we present a configurable flash memory tester using FPGA for low-cost testing and diagnostics. Experimental results on industrial flash chips justify the effectiveness of our test and diagnostics system.
29576760
A configurable AES processor for enhanced security
26839737
A BIST scheme for FPGA interconnect delay faults
In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.
10023746
Test and diagnosis of word-oriented multiport memories
Conventionally, the test of multiport memories is considered difficult because of the complex behavior of the faulty memories and the large number of inter-port faults. This paper presents an efficient approach for testing and diagnosing multiport RAMs. Our approach takes advantage of the higher access bandwidth due to the increased number of read/write ports, which also provides higher observability and controllability that effectively reduces the test time. Our key idea is that a sequence of March operations for any memory cell can be folded and executed within a single access cycle. We have also developed an efficient test algorithm for port-specific faults as well as traditional cell faults. The port-specific faults include the stuck-open, address decoder, and inter-port faults, for both bit-oriented and word-oriented RAMs. Experimental results for our folding scheme show that the test time reduction is about 28% for a commercial 8 KB embedded SRAM. An efficient diagnostic algorithm is also proposed for the port-specific faults and traditional cell faults.
1691242
The Open Language Archives Community and Asian Language Resources
The Open Language Archives Community (OLAC) is a new project to build a worldwide system of federated language archives based on the Open Archives Initiative and the Dublin Core Metadata Initiative. This paper aims to disseminate the OLAC vision to the language resources community in Asia, and to show language technologists and linguists how they can document their tools and data in such a way that others can easily discover them. We describe OLAC and the OLAC Metadata Set, then discuss two key issues in the Asian context: language classification and multilingual resource classification.
41188840
Finding Double Euler Trails of Planar Graphs in Linear Time
This paper answers an open question in the design of complimentary metal-oxide semiconductor VLSI circuits. The question asks whether a polynomial-time algorithm can decide if a given planar graph has a plane embedding ${\cal E}$ such that ${\cal E}$ has an Euler trail P = e1 e2 ... em and its dual graph has an Euler trail $P^*=e^*_1 e^*_2 \ldots e^*_m$, where $e^*_i$ is the dual edge of ei for i=1,2,...,m. This paper answers this question in the affirmative by presenting a linear-time algorithm.
60476874
High-level synthesis using computation-unit integrated memories
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASIC) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). We propose an architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This work addresses the challenge of providing an automatic synthesis framework for a CIM-based architecture. Our framework can analyze the various trade-offs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance, low-overhead implementation. Experiments with several behaviors indicate that an average performance improvement of 1.88/spl times/ (a maximum of 2.63/spl times/) is possible with very low area overheads. The energy-delay product improves by an average of 2.1/spl times/ (maximum of 3.4/spl times/).
14432070
Monitoring cycles for fault detection in meshed all-optical networks
Fault detection is critical for all-optical networks (AONs). This paper introduces the concept of monitoring cycle and proposes a fault detection mechanism based on decomposing AONs into a set of cycles (a cycle cover), in which each one is defined as a monitoring cycle. Two cycle-finding algorithms are developed and compared for the proposed fault detection mechanism: heuristic depth first searching (HDFS) and shortest path Eulerian matching (SPEM). The degradation of wavelength utilization and the cardinality of cycle covers are analyzed for evaluating the proposed mechanism. The proposed mechanism is applied to four network examples: NSFNET, ARPA2, SmallNet and Bellcore. The evaluation results show that the proposed fault detection mechanism is effective and cost efficient.
9639915
Support for adaptivity in ARMCI using migratable objects
Many new paradigms of parallel programming have emerged that compete with and complement the standard and well-established MPI model. Most notable, and successful, among these are models that support some form of global address space. At the same time, approaches based on migratable objects (also called virtualized processes) have shown that resource management concerns can be separated effectively from the overall parallel programming effort. For example, Charm++ supports dynamic load balancing via an intelligent adaptive run-time system. It is also becoming clear that a multi-paradigm approach that allows modules written in one or more paradigms to coexist and co-operate will be necessary to tame the parallel programming challenge. ARMCI is a remote memory copy library that serves as a foundation of many global address space languages and libraries. This paper presents our preliminary work on integrating and supporting ARMCI with the adaptive run-time system of Charm++ as a part of our overall effort in the multi-paradigm approach