39753705
A programmable built-in self-test core for embedded memories
28276441
A Programmable BIST Core for Embedded DRAM
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy.
37411387
Automatic generation of memory built-in self-test cores for system-on-chip
Memory testing is becoming the dominant factor in testing a system-on-chip (SoC), with the rapid growth of the size and density of embedded memories. To minimize the test effort, we present an automatic generation framework of memory built-in self-test (BIST) cores for SoC designs. The BIST generation framework is a much improved one of our previous work. Test integration of heterogeneous memory architectures and clusters of memories are focused on. The automatic test grouping and scheduling optimize the overhead in test time, performance, power consumption, etc. Furthermore, with our novel BIST architecture, the BIST cores can be accessed via an on-chip bus interface (e.g., AMBA), which eases the control of testing and diagnosis in a typical SoC scenario. With a configurable and extensible architecture, the proposed framework facilitates easy memory test integration for core providers as well as system integrators.
14059927
Test scheduling of BISTed memory cores for SoC
The test scheduling of memory cores can significantly affect the test time and power of system chips. We propose a test scheduling algorithm for BISTed memory cores to minimize the overall testing time under the test power constraint. The proposed algorithm combines several approaches for a near-optimal result, based on the properties of BISTed memory cores. By proper partitioning, an analytic exhaustive search finds optimal results for large memory cores, while a heuristic ordering with simulated annealing further handles a large amount of smaller memory cores. On the average, the results are within 1% difference of the optimal solution for the cases of 200 memory cores.
43442956
Representation characterizations of chordal bipartite graphs
A bipartite graph is chordal bipartite if it does not contain an induced cycle of length at least six. We give three representation characterizations of chordal bipartite graphs. More precisely, we show that a bipartite graph is chordal bipartite if and only if the complement is the intersection graph of a family of pairwise compatible claws in a weighted hypercircle. (A hypercircle is a graph which consists of internally vertex disjoint paths between two distinguished vertices, and a claw in a hypercircle is a connected subgraph containing exactly one of the two distinguished vertices.) We also introduce two classes of bipartite graphs, both containing interval bigraphs and interval containment bigraphs. They are compatible subtree intersection bigraphs and compatible subtree containment bigraphs. We show that these two classes are identical to the class of chordal bipartite graphs.
37356020
Thread transparency in information flow middleware
Applications that process continuous information flows are challenging to write because the application programmer must deal with flow-specific concurrency and timing requirements, necessitating the explicit management of threads, synchronization, scheduling and timing. We believe that middleware can ease this burden, but many middleware platforms do not match the structure of these applications, because they focus on control-flow centric interaction models such as remote method invocation. Indeed, they abstract away from the very things that the informatian-flow centric programmer must control.This paper describes Infopipes--a new high-level abstraction for information flow applications--and a middleware framework that supports them. Infopipes handle the complexities associated with control flow and multi-threading, relieving the programmer of these tasks. Starting from a high-level description of an information flow pipeline, the framework determines which parts of a pipeline require separate threads or coroutines, and handles synchronization transparently to the application programmer. The framework also gives the programmer the freedom to write or reuse components in a passive style, even through the configuration will actually require the use of a thread or coroutine. Conversely, it is possible to write a component using a thread and know that the thread will be eliminated if it is not needed in a pipeline. This allows the most appropriate programming model to be chosen for a given task, and existing code to be reused irrespective of its activity model.
14132755
Efficient Name Disambiguation for Large-Scale Databases
Name disambiguation can occur when one is seeking a list of publications of an author who has used different name variations and when there are multiple other authors with the same name. We present an efficient integrative framework for solving the name disambiguation problem: a blocking method retrieves candidate classes of authors with similar names and a clustering method, DBSCAN, clusters papers by author. The distance metric between papers used in DBSCAN is calculated by an online active selection support vector machine algorithm (LASVM), yielding a simpler model, lower test errors and faster prediction time than a standard SVM. We prove that by recasting transitivity as density reachability in DBSCAN, transitivity is guaranteed for core points. For evaluation, we manually annotated 3,355 papers yielding 490 authors and achieved 90.6% pairwise-F1. For scalability, authors in the entire CiteSeer dataset, over 700,000 papers, were readily disambiguated.
11615380
A sigma-delta modulation based BIST scheme for mixed-signal circuits
In this work, we present the analysis of a built-in self-test (BIST) scheme for mixed-signal circuits that is intended to provide on-chip stimulus generation and response analysis. Based on the sigma-delta modulation principle, the proposed scheme can produce high-quality stimuli and obtain accurate measurements without the need of precise analog circuitry. Numerical simulations are conducted to validate our idea and the results show that the scheme is a promising BIST approach for mixed-signal circuits.
18846046
Fluid ontologies for digital museums
With the advent and accessibility of the Internet, artistic and indigenous communities are beginning to realize how digital technologies can be used as a means for documenting and preserving their histories and cultures. However, it is not yet clear what knowledge architectures are most appropriate for creating a digital museum in order to facilitate an effective collection, organization, conservation, and experience of cultural and artistic heritage. In this paper, we discuss the concept of “fluid ontologies,” a novel, dynamic structure for organizing and browsing knowledge in a digital museum. Fluid ontologies are flexible knowledge structures that evolve and adapt to communities’ interest based on contextual information articulated by human contributors, curators, and viewers, as well as artificial bots that are able to track interaction histories and infer relationships among knowledge pieces and preferences of viewers. Fluid ontologies allow for a tighter coupling between communities’ interests and the browsing structure of a digital museum. We present the key ideas behind the use of fluid ontologies within the context of digital museum design and seminal work in metadata/dynamic ontologies, particularly as it pertains to objects of cultural heritage, and discuss these characteristics in three concrete examples: (1) Village Voice, an online agora that ties together the narratives created by a group of Somali refugees using an iteration of community-designed ontologies, (2) Eventspace, a node-based collaborative archive for design activities, and (3) Tribal Peace, an online digital museum still under construction and evaluation that uses proactive agents to tie distributed Kumeyaay, Luiseno, and Cupeno reservations together in their quest to achieve greater political sovereignty .