7329070
Fault-tolerant routing and disjoint paths in dual-cube: a new interconnection network
In this paper, we introduce a new interconnection network, the dual-cube, its topological properties, and the routing/broadcasting algorithms in the dual-cube. The advanced subjects such as fault-tolerant routing and constructing multiple disjoint paths in dual-cubes are also included in this paper. The binary hypercube, or r-cube, can connect 2/sup r/ nodes. In contrast, a dual-cube with r links for each node, F/sub r/, can connect 2/sup 2r-1/ nodes while keeps most of topological properties of hypercubes. Fault-tolerant routing and constructing multiple disjoint paths in dual-cubes can be solved elegantly using a new structure, called extended cube. We show that for any two nonfaulty nodes s and t in F/sub r/ which contains up to r-1 faulty nodes, we can find a fault-free path s to t, of length at most 3d(s,t) in O(r) optimal time, where d(s,t) is the distance between s and t. We also show that, in a fault-free F/sub r/, r disjoint paths s to t, of length at most d(s,t)+6 can be constructed in O(r/sup 2/) optimal time.
17967920
Exploiting Java instruction/thread level parallelism with horizontal multithreading
Java bytecodes can be executed with the following three methods: a Java interpreter running on a particular machine interprets bytecodes; a Just-in-Time (JIT) compiler translates bytecodes to the native primitives of the particular machine and the machine executes the translated codes; and a Java processor executes bytecodes directly. The first two methods require no special hardware support for the execution of Java bytecodes and are widely used currently. The last method requires an embedded Java processor, picoJavaI or picoJavaII for instance. The picoJavaI and picoJavaII are simple pipelined processors with no ILP (instruction level parallelism) and TLP (thread level parallelism) supports. A so-called MAJC (microprocessor architecture for Java computing) design can exploit ILP and TLP by using a modified VLIW (very long instruction word) architecture and vertical multithreading technique, but it has its own instruction set and cannot execute Java bytecodes directly. In this paper, we investigate a processor architecture which can directly execute Java bytecodes meanwhile can exploit Java ILP and TLP simultaneously. The proposed processor consists of multiple slots implementing horizontal multithreading and multiple functional units shared by all threads executed in parallel. Our architectural simulation results show that the Java processor could achieve an average 20 IPC (instructions per cycle), or 7.33 EIPC (effective IPC), with 8 slots and a 4-instruction scheduling window for each slot. We also check other configurations and give the utilization of functional units as well as the performance improvement with various kinds of working loads.
6040880
Rupture degree of graphs
We introduce a new graph parameter, the rupture degree. The rupture degree for a complete graph K n is defined as 1−n, and the rupture degree for an incomplete connected graph G is defined by r(G)=max{ω(G−X)−|X|−m(G−X):X⊂V(G), ω(G−X)>1}, where ω(G−X) is the number of components of G−X and m(G−X) is the order of a largest component of G−X. It is shown that this parameter can be used to measure the vulnerability of networks. Rupture degrees of several specific classes of graphs are determined. Formulas for the rupture degree of join graphs and some bounds of the rupture degree are given. We also obtain some Nordhaus–Gaddum type results for the rupture degree.
39892461
The XOO7 Benchmark
As XML becomes the standard for electronic data interchange, benchmarks are needed to provide a comparative performance analysis of XML Management Systems (XMLMS). Typically a benchmark should adhere to four criteria: relevance, portability, scalability and simplicity [1]. The data structure of a benchmark for XML must be complex enough to capture the characteristics of XML data representation. Data sets should be in various sizes. Benchmark queries should only be defined with the primitives of the language.
8401209
Optimal Traffic-Oblivious Energy-Aware Routing for Multihop Wireless Networks
Energy efficiency is an important issue in multihop wireless networks with energy concerns. Usually it is achieved with accurate knowledge of the traffic pattern and/or the current network information such as the remaining energy level. We investigate the problem of designing a routing scheme to minimize the maximum energy utilization of a multihop wireless network with weak assumption of the traffic pattern and without ongoing collection of network information. We develop polynomial size LP models to design such a routing scheme. We discuss generalizations of the LP models to various radio transmission models. In an interference-limited scenario, we show how to guarantee schedulability of the oblivious routing. We present an extension to consider lossy links. We also discuss implementation issues. The LP models achieve performance close to what an oracle can achieve in the performance study. The results for multihop wireless networks with a single sink are especially good. We make a first stride in designing a traffic-oblivious energy-aware routing framework in multihop wireless networks.
14874981
On the performance of a dual round-robin switch
The dual round-robin matching (DRRM) switch has a scalable, low complexity architecture which allows for an aggregate bandwidth exceeding 1 Tb/s using current CMOS technology. In this paper we prove that the DRRM switch can achieve 100% throughput under i.i.d. and uniform traffic. The DRRM is the first practical matching scheme for which this property has been proved. The performance of the DRRM switch is then studied and compared with the iSLIP switch. The delay performance under uniform traffic and the hot-spot throughput of DRRM is better than that of iSLIP, while the throughput of iSLIP under some nonuniform traffic scenarios is slightly higher than that of DRRM. Since throughput drops below 100%, under nonuniform traffic, we also examine some variations of the DRRM matching scheme for nonuniform traffic.
27961753
Effective Algorithms for Tag Snp Selection
Single nucleotide polymorphisms (SNPs), due to their abundance and low mutation rate, are very useful genetic markers for genetic association studies. However, the current genotyping technology cannot afford to genotype all common SNPs in all the genes. By making use of linkage disequilibrium, we can reduce the experiment cost by genotyping a subset of SNPs, called Tag SNPs, which have a strong association with the ungenotyped SNPs, while are as independent from each other as possible. The problem of selecting Tag SNPs is NP-complete; when there are large number of SNPs, in order to avoid extremely long computational time, most of the existing Tag SNP selection methods first partition the SNPs into blocks based on certain block definitions, then Tag SNPs are selected in each block by brute-force search. The size of the Tag SNP set obtained in this way may usually be reduced further due to the inter-dependency among blocks. This paper proposes two algorithms, TSSA and TSSD, to tackle the block-independent Tag SNP selection problem. TSSA is based on A* search algorithm, and TSSD is a heuristic algorithm. Experiments show that TSSA can find the optimal solutions for medium-sized problems in reasonable time, while TSSD can handle very large problems and report approximate solutions very close to the optimal ones.