17285109
Concurrent operations on priority queues
Among the fastest priority queue implementations, skew heaps have properties that make them particularly suited to concurrent manipulation of shared queues. A concurrent version of the top down implementation of skew heaps can be produced from previously published sequential versions using almost mechanical transformations. This implementation requires O(log n) time to enqueue or dequeue an item, but it allows new operations to begin after only O(1) time on a MIMD machine. Thus, there is potential for significant concurrency when multiple processes share a queue. Applications to problems in graph theory and simulation are discussed in this article.
14456192
Improved interpretation of UNIX-like file names embedded in data
When the data processed by a program span several files, the common practice of including file names as data in some of the files leads to difficulties in moving or sharing that data. In systems using tree structured directories, this problem can be solved by making a syntactic distinction between absolute and relative file names.
42995338
Assembly Language as Object Code
The set of meanings that may be encoded in most object languages is a subset of the meanings that may be encoded in most assembly languages. Careful exploitation of this fact in the design of the SMAL assembly and object language allows the SMAL assembler itself to be used as a linkage editor, thus eliminating the need for an expensive and often misunderstood system program. The SMAL assembler is no more complex than many assemblers in common use today, nor are the relevant aspects of the SMAL language particularly unique.
14144660
Systematic protection mechanism design
This work describes an attempt to systematically design a hardware resource protection mechanism when given the requirements of a particular language as a target. The design process is formalized as a structured walk through the multidimensional computer design space towards a hypothetical class of optimal machines. Each step in this walk involves a change in the distribution of work between the compiler and run-time system but no change in the source language semantics. The starting point for this walk is the result of a semantic analysis of the language to be implemented; typically, this produces a very high level machine where the compiler, if any, is trivial. The walk ends when no changes result in a net improvement. This does not guarantee that the result is even locally optimal, since the changes tried depend on the ingenuity and persistence of the designer.
 This design approach has been used to arrive at a practical, general purpose protection mechanism oriented towards the needs of the Ada language (preliminary version). This architecture was evaluated by comparing it with the PDP-11/45. For the purpose of this comparison, the protection mechanism was incorporated into a partially specified PDP-11 like instruction set. The number of bits making up the processor state and the number of operations involved in address computation were evaluated. On this basis, the result appears to be competitive and worth further investigation.
12941967
Application of splay trees to data compression
The splay-prefix algorithm is one of the simplest and fastest adaptive data compression algorithms based on the use of a prefix code. The data structures used in the splay-prefix algorithm can also be applied to arithmetic data compression. Applications of these algorithms to encryption and image processing are suggested.
14105636
Experience with concurrent simulation
We have successfully implemented a concurrent simulator and we report initial speedup measurements for this technique. Our algorithm requires a shared-memory multiprocessor and is appropriate to any discrete-event simulation model. In addition, our algorithm places no constraints on minimum service times or the presence of cycles in the simulation model. Our experimental simulator runs on an Encore Multimax computer and is applicable to closed product-form queueing networks. We have observed speedups of 2.3 for a central-server queueing model using our simulator.
14721450
Implementation of a block based neural branch predictor
This paper contributes to a dynamic branch predictor algorithm based on a perceptron in two directions: Firstly, a new block form of computation is introduced that reduces theoretically by half the combinational critical path for computing a prediction. Secondly, implementation in FPGA hardware is fully developed for quantitative comparison purposes. FPGA circuits for a one-cycle block predictor produces 1.7 faster clock rates than a direct implementation of the original perceptron predictor. This faster clock allows to realize predictions with longer history lengths for the same hardware budget.
11953858
Joint source channel matching for a wireless image transmission
Application of joint source-channel matching in heterogeneous multi-media environments will demand general source-channel optimization schemes suitable for a wide variety of source coding standards, channel coders, and variable channel conditions. We develop a general approach for joint source-channel matching based on a parametric distortion model that can be accurately applied to most classes of source and channel coders. Our simulations indicate that it may be possible to obtain nearly all of the benefits of joint source-channel optimization by matching existing source and channel coding standards using the simple and general approach we propose.
26900731
A new organization for a perceptron-based branch predictor and its FPGA implementation
An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.
5890482
FPGA organization for the fast path-based neural branch predictor
This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor. Our results suggest that practical sizes of prediction tables are limited to around 32KB to 64KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However, the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.
17269099
Edge detection in ultrasound speckle noise
Presents a statistical approach to edge detection in ultrasound speckle, and uses actual noise statistics to derive an expression for an optimal detection rule. The authors compute the optimal detector for the special case of uncorrelated speckle, and an approximation to the optimal detector for the case when signal-to-noise ratio (SNR) is high. They also discuss a simple sub-optimal detection scheme, and show that its performance is close to that of the optimal uncorrelated speckle detection rule, and surpasses that of the high-SNR approximation except in the case of extremely high SNR, in which case they both perform equally well.<<ETX>>