17981801
Studying storage-recomputation tradeoffs in memory-constrained embedded processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we witness an unprecedented proliferation of embedded/mobile applications. Most of the environments that execute these applications have severe power, performance, and memory space constraints that need to be accounted for. In particular, memory limitations can present serious challenges to embedded software designers. The current solutions to this problem include sophisticated packaging techniques and code optimizations for effective memory utilization. While the first solution is not scalable, the second one is restricted by intrinsic data dependences in the code that prevent code restructuring. In this paper, we explore an alternate approach for reducing memory space requirements of embedded applications. The idea is to re-compute the result of a code block (potentially multiple times) instead of storing it in memory and performing a memory operation whenever needed. The main benefit of this approach is that it reduces memory space requirements, that is, no memory space is reserved for storing the result of the code block in question.
13941129
Compiler-directed thermal management for VLIW functional units
As processors, memories, and other components of today's embedded systems are pushed to higher performance in more enclosed spaces, processor thermal management is quickly becoming a limiting design factor. While previous proposals mostly approached this thermal management problem from circuit and architecture angles, software can also play an important role in identifying and eliminating thermal hotspots as it is the main factor that shapes the order and frequency of accesses to different hardware components in the chip. This is particularly true for compiler-scheduled Very Long Instruction Word (VLIW) datapath.In this paper, we focus on a compiler-based approach to make the thermal profile more balanced in the integer functional units of VLIW architectures. For balanced thermal behavior and peak temperature minimization, we propose techniques based on load balancing across the integer functional units with or without rotation of functional unit usage. As leakage power is exponentially dependent on temperature and temperature is dependent on total power (i.e., switching and leakage), in our techniques, we also consider leakage power optimization by IPC tuning (instructions issued per cycle). By taking a code that is already scheduled for maximum performance as input, our scheduling strategies modify this performance-oriented schedule for balanced thermal behavior with negligible performance degradation. We simulate our scheduling strategies using a framework that consists of the Trimaran infrastructure, a power model, and the HotSpot. Our experimental results using several benchmark programs reveal that the peak temperature can be reduced through compiler scheduling.
2691860
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this paper is to study the challenges for L2 design and management in 3D chip multiprocessors. Our first contribution is to propose a router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory. Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections. In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration. This also helps reduce power consumption in L2 due to a reduced number of data movements
11226444
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over complex single core based systems, compilation issues for these architectures have relatively received less attention. Programming MPSOCs can be challenging as several potentially conflicting issues such as data locality, parallelism and load balance across processors should be considered simultaneously. Most of the compilation techniques discussed in the literature for parallel architectures (not necessarily for MPSOCs) are loop based, i.e., they consider each loop nest in isolation. However, one key problem associated with such loop based techniques is that they fail to capture the interactions between the different loop nests in the application. This paper takes a more global approach to the problem and proposes a compiler-driven data locality optimization strategy in the context of embedded MPSOCs. An important characteristic of the proposed approach is that, in deciding the workloads of the processors (i.e., in parallelizing the application) it considers all the loop nests in the application simultaneously. The authors' experimental evaluation with eight embedded applications showed that the global scheme brings significant power/performance benefits over the conventional loop based scheme.
6208153
Maximizing data reuse for minimizing memory space requirements and execution cycles
Embedded systems in the form of vehicles and mobile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints. Therefore, their performance demands must be balanced very well against their memory space requirements and power consumption. Automatic tools that can optimize for memory space utilization and performance are expected to be increasingly important in the future as increasingly larger portions of embedded designs are being implemented in software. In this paper, we describe a novel optimization framework that can be used in two different ways: (i) deciding a suitable on-chip memory capacity for a given code, and (ii) restructuring the application code to make better use of the available on-chip memory space. While prior proposals have addressed these two questions, the solutions proposed in this paper are very aggressive in extracting and exploiting all data reuse in the application code, restricted only by inherent data dependences
11193384
Compiler-directed voltage scaling on communication links for reducing power consumption
Reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. Most of the prior efforts on network power optimization are hardware-based schemes. These schemes are predictive by definition as they control communication link status based on the observations made In the past. Since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. This paper proposes a compiler driven approach to communication link voltage management. In this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. This information along with network topology is used for identifying the link access patterns. These patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. Our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. We exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which In turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.
8300930
Browsing digital video
Video in digital format played on programmable devices presents opportunities for significantly enhancing the user's viewing experience. For example, time compression and pause removal can shorten the viewing time for a video, textual and visual indices can allow personalized navigation through the content, and random-access digital storage allows instantaneous seeks into the content. To understand user behavior when such capabilities are available, we built a software video browsing application that combines many such features. We present results from a user study where users browsed video in six different categories: classroom lectures, conference presentations, entertainment shows, news, sports, and travel. Our results show that the most frequently used features were time compression, pause removal, and navigation using shot boundaries. Also, the behavior was different depending on the content type, and we present a classification. Finally, the users found the browser to be very useful. Two main reasons were: i) the ability to save time and ii) the feeling of control over what content they watched.
6484880
Spatio-temporal aggregation using sketches
Several spatio-temporal applications require the retrieval of summarized information about moving objects that lie in a query region during a query interval (e.g., the number of mobile users covered by a cell, traffic volume in a district, etc.). Existing solutions have the distinct counting problem: if an object remains in the query region for several timestamps during the query interval, it will be counted multiple times in the result. We solve this problem by integrating spatio-temporal indexes with sketches, traditionally used for approximate query processing. The proposed techniques can also be applied to reduce the space requirements of conventional spatio-temporal data and to mine spatio-temporal association rules.
8773045
Characterizing and Exploiting Reference Locality in Data Stream Applications
In this paper, we investigate a new approach to process queries in data stream applications. We show that reference locality characteristics of data streams could be exploited in the design of superior and flexible data stream query processing techniques. We identify two different causes of reference locality: popularity over long time scales and temporal correlations over shorter time scales. An elegant mathematical model is shown to precisely quantify the degree of those sources of locality. Furthermore, we analyze the impact of locality-awareness on achievable performance gains over traditional algorithms on applications such asMAX-subset approximate sliding window join and approximate count estimation. In a comprehensive experimental study, we compare several existing algorithms against our locality-aware algorithms over a number of real datasets. The results validate the usefulness and efficiency of our approach.
8583268
Proportional degradation services in wireless/mobile adaptive multimedia networks
Adaptive multimedia services are very attractive since resources in wireless/mobile networks are relatively scarce and widely variable, and more importantly the resource fluctuation caused by mobility and channel fading can be mitigated using adaptive services. Therefore, there are extensive research activities on Quality of Service (QoS), call admission control, as well as bandwidth degradation and adaptation for adaptive multimedia services in wireless/mobile networks in recent years. However, fairness of bandwidth degradation has largely been ignored in previous work and remains an important issue in adaptive multimedia service provisioning. In this paper, we propose and study proportional degradation service provisioning in wireless/mobile networks that offer multiple classes of adaptive multimedia services. The proposed proportional degradation fairness model guarantees the proportional bandwidth degradation among different classes of services. Two proportional degradation scenarios are studied in this paper. In the first scenario, we study the proportional degradation provisioning with two QoS parameters for adaptive multimedia: the degradation ratio (DR) and the degradation degree (DD). In the second scenario, we study the proportional degradation provisioning with a new QoS parameter for adaptive multimedia: the degradation area (DA). For each scenario, based on the QoS parameters, proportional degradation adaptation algorithms are proposed to approximate the proportional degradation model, to fairly adapt calls' degradations, to utilize the system resource efficiently, as well as to optimize QoS parameters. Performance studies show that in the first scenario, proportional DR has been achieved very well, whereas proportional DD has not been well achieved. In other words, DR outperforms DD in terms of proportional degradation. In the second scenario, proportional DA has been well achieved. Furthermore, bandwidth resources have been efficiently utilized and DA has been minimized. Copyright © 2004 John Wiley & Sons, Ltd.
2441510
Interactive Rendering of Deforming NURBS Surfaces
The non-uniform rational B-splines (NURBS) has been widely accepted a s a standard tool f or geometry representation and design. Its r ich g eometric properties allow it t o represent both analytic shapes and free-form curves and surfaces precisely. Moreover, a set of tools is available for shape modification or more implicitly, object deformation. Existing NURBS rendering methods include de Boor algorithm, Oslo algorithm, Shantz’s adaptive forward differencing algorithm and Silbermann’s high speed implementation o f NURBS. However, these methods consider only speeding u p the rendering p rocess of individual f rames. Recently, Kumar et al. proposed an incremental method for rendering NURBS surfaces, but it is still limited to static surfaces. In realtime applications such a s virtual reality, interactive display is needed. If a virtual environment contains a lot of deforming objects, these methods cannot provide a good solution. In this paper, we propose an efficient method for interactive rendering of deformable objects by maintaining a polygon model of each d eforming NURBS surface and a daptively refining the resolution o f the polygon model. We also look at how this method may be applied to multi-resolution modelling.