525351
Memory Space Conscious Loop Iteration Duplication for Reliable Execution
Soft errors, a form of transient errors that cause bit flips in memory and other hardware components, are a growing concern for embedded systems as technology scales down. While hardware-based approaches to detect/correct soft errors are important, software-based techniques can be much more flexible. One simple software-based strategy would be full duplication of computations and data, and comparing the results of the corresponding original and duplicate computations. However, while the performance overhead of this strategy can be hidden during execution if there are idle hardware resources, the memory demand increase due to data duplication can be dramatic, particularly for array-based applications that process large amounts of data. 
 
Focusing on array-based embedded computing, this paper presents a memory space conscious loop iteration duplication approach that can reduce memory requirements of full duplication (of array data), without decreasing the level of reliability the latter provides. Our “in-place duplication” approach reuses the memory locations from the same array to store the duplicates of the elements of a given array. Consequently, the memory overhead brought by the duplicates can be reduced. Further, we extend this approach to incorporate “global duplication”, which reuses memory locations from other arrays to store duplicates of the elements of a given array. This paper also discusses how our approach operates under a memory size constraint. The experimental results from our implementation show that the proposed approach is successful in reducing memory requirements of the full duplication scheme for twelve array-based applications.
14750422
Reducing power with performance constraints for parallel sparse applications
Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computation-to-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties.
37185470
An ILP-Based Approach to Locality Optimization
One of the most important factors that determine performance of data-intensive applications is data locality. A program with high data locality makes better use of fast, on-chip memories and can avoid large main memory latencies. Although previous compiler research investigated numerous techniques for enhancing locality, we lack of formal techniques, against which the existing heuristics can be compared. Motivated by this observation, this paper presents a fresh look at locality optimization based on integer linear programming (ILP). We formulate the conditions for data locality, and present a system of constraints whose solution gives optimal computation re-ordering and data-to-memory assignment under our objective function and cost model. Our experimental results using three data-intensive applications clearly indicate that the ILP-based approach generates very good results and outperforms a previously proposed heuristic solution to locality.
1582700
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. The advantage of placing multiple cores into a single die is that it reduces on-chip communication costs (in terms of both execution cycles and power consumption) between the processor cores that are traditionally very high in conventional high-performance parallel architectures (such as SMPs). However, on the negative side, this tighter integration exerts an even higher pressure on off-chip accesses to the memory system. This makes minimizing the number of off-chip accesses a critical optimization goal.This paper discusses a compiler-based solution to this problem for the embedded applications that perform stencil computations. An important characteristic of this solution is that it distinguishes between the intra-processor data reuse and inter-processor data reuse. The first of these captures the data reuse that occurs across loop iterations assigned to the same processor, whereas the second one represents the data reuse that takes place across the loop iterations assigned to different processors. The proposed approach then optimizes inter-processor reuse by re-organizing the loop iterations of each processor carefully, considering how data elements are shared across processors. The goal is to ensure that the different processors access the shared data within a short period of time, so that the data can be captured in the on-chip memory space at the time of the reuse. This paper also presents an evaluation of the proposed optimization and compares it to an alternate scheme that optimizes data locality for each processor in isolation. The results obtained by applying our implementation to eight loop-intensive benchmark codes from the embedded computing domain show that our approach improves over the mentioned alternate scheme by 15.6% on average.
1915474
Runtime integrity checking for inter-object connections
Ensuring integrity of heap resident data is critical for many embedded systems. Ever-scaling process technology combined with power-saving techniques employed in embedded systems is increasing vulnerability of such systems to hardware-related errors such as soft errors. While such errors are transient and do not harm the architecture, they can corrupt data. In this study, we explore solutions to the inter-object connectivity problem in heap memory of Java-based embedded environments. Our objective is to ensure that the connections between the objects are consistent. In particular, we want to detect the cases where an inter-object link disappears or points to a wrong object. To address this problem, we propose a rule based approach, where the application programmer expresses the important connectivity rules to be satisfied using a special rule language, and a modified JVM (Java virtual machine) checks these rules at runtime.
1780811
Reducing code size through address register assignment
In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.
316842
Cycles in 4-connected planar graphs
Let G be a 4-connected planar graph on n vertices. Previous results show that G contains a cycle of length k for each k ∈ {n, n - 1,n - 2, n - 3} with k ≥ 3. These results are proved using the "Tutte path" technique, and this technique alone cannot be used to obtain further results in this direction. One approach to obtain further results is to combine Tutte paths and contractible edges. In this paper, we demonstrate this approach by showing that G also has a cycle of length k for each k ∈ {n - 4, n - 5, n - 6} with k ≥ 3. This work was partially motivated by an old conjecture of Malkevitch.
1160338
Graph Connectivity After Path
Removal
Let G be a graph and
u, v be two distinct vertices of
G. A u—v path P is called nonseparating if
G—V(P) is connected. The purpose of this
paper is to study the number of nonseparating
u—v path for two arbitrary
vertices u and
v of a given graph. For a
positive integer k, we will
show that there is a minimum integer α(k) so that if G is an α(k)-connected graph and
u and v are two arbitrary vertices in
G, then there exist
k vertex disjoint paths
P1[u,v], P2[u,v], . . ., Pk[u,v], such that G—V (Pi[u,v]) is connected for every
i (i = 1, 2, ..., k). In fact, we will prove that
α(k) ≤ 22k+2. It is known that α(1) = 3.. A
result of Tutte showed that α(2) = 3. We show that α(3) = 6. In
addition, we prove that if G
is a 5-connected graph, then for every pair of vertices
u and v there exists a path
P[u, v] such that G—V(P[u,
v]) is 2-connected.
13165468
A note on fragile graphs
In this note, we show that every graph on n vertices and at most 2n - 4 edges contains a vertex-cut S which is also an independent set of G. The result is best possible and answers a question proposed by Caro in the affirmative.
6370123
Full integration of subtyping and if-expression
The combination of full subsumption and conditional expression is a challenging problem, because in such a system, a term might not have a type which is a representative of all types of the term. Therefore, the traditional type checking technique fails. Due to such a difficulty, Java typing rule for if-expression uses only a restricted form of subtyping. In this paper, we propose a type system which includes both of the above mentioned features and enjoys decidable type checking. We also show that the system has the subject reduction property. It is expected that this technique could be used to improve the type system of Java with full subsumption.
6873995
Policy-driven data dissemination for context-aware applications
Context-aware pervasive-computing applications require continuous monitoring of their physical and computational environment to make appropriate adaptation decisions in time. The data streams produced by sensors, however, may overflow the queues on the dissemination path. Traditional flow-control and congestion-control policies either drop data or force the sender to pause. When the data sender is sensing the physical environment, however, a pause is equivalent to dropping data. Instead of arbitrarily dropping data that may contain important events, we present a policy-driven data dissemination service named PACK, based on an overlay-based infrastructure for efficient multicast delivery. PACK enforces application-specified policies that define how to discard or summarize data flows wherever queues overflow on the data path, notably at the mobile hosts where applications often reside. A key contribution of our approach is to uniformly apply the data-stream "packing" abstraction to queue overflow caused by network congestion, slow receivers, and temporary disconnection. We present experimental results and a detailed application study of the PACK service.