15551235
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC
We propose a hardware accelerator for context-based adaptive binary arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Experimental result with FPGA prototyping shows that our design is sufficient to decode main profile CIF video streams at 30 fps.
195838317
Data path allocation based on bipartite weighted matching
Proposes a graph-theoretic approach for the data path allocation problem. The problem is decomposed into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian method. The third subproblem is solved using a greedy method. It is shown that, by taking the other into consideration while solving one, equally satisfactory results can be obtained, regardless of the order in which (1) and (2) are performed. Two programs, LYRA and ARYL, are implemented which solve the subtasks in different orders. For register allocation, the approach is the first one to guarantee minimal use of registers while being able to take the interconnection cost into account. This research has demonstrated that the bipartite weighted matching algorithm is indeed a good solution for the data path allocation problem.<<ETX>>
53235373
Performance-optimal clustering with retiming for sequential circuits
6763648
An effective methodology for functional pipelining
We address the problem of given a loop behavior, a target initiation interval and resource constraints, scheduling a loop in a pipelined fashion such that the iteration time (turn-around time) is minimized. The iteration time is an important quality measure of a data path design because of its direct correlationship with both the storage and the control costs. Our scheduler starts with performing an As Soon As Possible Pipelined (ASAPp) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.
195837942
Optimum and heuristic data path scheduling under resource constraints
An integer linear programming model for the scheduling problem in high-level synthesis under resource constraints is presented. The following applications are considered: multicycle operations with nonpipelined or pipelined function units: mutually exclusive operations: functional pipelining: loop-folding; and scheduling under bus constraint. Besides the model, a new technique, called zone scheduling (ZS), is proposed to solve large-size problems. ZS partitions the distribution graph into several zones and sequentially solves the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing a more global view of a scheduling problem to be taken.<<ETX>>
16396963
Performance-driven interconnection optimization for microarchitecture synthesis
This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design. >
37430657
On the boundary inequality for bandwidth of graphs
15619003
A Graphical User Interface Design for Network Simulation
Abstract This article describes a prototyping effort of a flexible graphical user interface (GUI) for a simulation tool called COPS. The GUI is designed to allow parameter setup for all modules in simulation model, and can be easily replaced by new GUIs implemented in different languages/graphical tools. This article provides design guidelines and implementation details of the flexible GUI.
6968436
Optimal memory management for time warp parallel simulation
Recently there has been a great deal of interest in performance evalution of parallel simulation. Most work is devoted to the time complexity and assumes that the amount of memory available for parallel simulation is unlimited. This paper studies the space complexity of parallel simulation. Our goal is to design an efficient memory management protocol which guarantees that the memory consumption of parallel simulation is of the same order as sequential simulation. (Such an algorithm is referred to as a optimal.) First, we derive the relationships among the space complexities of sequential simulation, Chandy-Misra simulation [2], and Time Warp simulation [7]. We show that Chandy-Misra may consume more storage than sequential simulation, or vice versa. Then we show that Time Warp never consumes less memory than sequential simulation. Then we describe cancelback, an optimal Time Warp memory management protocol proposed by Jefferson. Although cancelback is considered to be complete solution for the storage management problem in Time Warp, some efficiency issues in implementing this algorithm must be considered. We propose an optimal algorithm called artifical rollback. We show that this algorithm is easy to implement and analyze. An implementation of artificial rollback is given, which is integrated with processor scheduling to adjust the memory consumption rate based on the amount of free storage available in the system.
16053955
Design Issues for Optimistic Distributed Discrete Event Simulation
Simulation is a powerful tool for studying the dynamics of a system. However, simulation is time-consuming. Thus, it is natural to attempt to use multiple processors to speed up the simulation process. Many protocols have been proposed to perform discrete event simulation in multi-processor environments. Most of these distributed discrete event simulation protocols are either conservative or optimistic. The most common optimistic distributed simulation protocol is called Time Warp. Several issues must be considered when designing a Time Warp simulation; examples are reducing the state saving overhead and designing the global control mechanism (i. e., global virtual time computation, memory management, distributed termination, and fault tolerance). This paper addresses these issues. We propose a heuristic to select the checkpoint interval to reduce the state saving overhead, generalize a previously proposed global virtual time computation algorithm, and present new algorithms for memory management, distributed termination, and fault tolerance. The main contribution of this paper is to provide guidelines for designing an efficient Time Warp simulation.
10935949
A time-division algorithm for parallel simulation
Most parallel simulation algorithms (e.g., Chandy and Misra’s algorithm or the Time Warp algorithm) are based on a “space-division” approach. The parallelism of this approach is limited by the causality constraints. Another approach, the “time-division” approach, may provide more parallelism if the time domain is appropriately partitioned. We present a time-division parallel simulation algorithm that partitions the time domain via state matching, We show that linear speed up can be achieved. For a complex system, the best parallel simulation approach is to integrate “time-division” and “space-division” algorithms: the simulated system is partitioned into several subsystems; a subsystem may be simulated by the time-division approach (e. g., our algorithm), while the overall system is simulated by the space-division approach.