45616322
Increasing FPGA resilience against soft errors using task duplication
17981801
Studying storage-recomputation tradeoffs in memory-constrained embedded processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we witness an unprecedented proliferation of embedded/mobile applications. Most of the environments that execute these applications have severe power, performance, and memory space constraints that need to be accounted for. In particular, memory limitations can present serious challenges to embedded software designers. The current solutions to this problem include sophisticated packaging techniques and code optimizations for effective memory utilization. While the first solution is not scalable, the second one is restricted by intrinsic data dependences in the code that prevent code restructuring. In this paper, we explore an alternate approach for reducing memory space requirements of embedded applications. The idea is to re-compute the result of a code block (potentially multiple times) instead of storing it in memory and performing a memory operation whenever needed. The main benefit of this approach is that it reduces memory space requirements, that is, no memory space is reserved for storing the result of the code block in question.
2691860
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together. Considering the trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this paper is to study the challenges for L2 design and management in 3D chip multiprocessors. Our first contribution is to propose a router architecture and a topology design that makes use of a network architecture embedded into the L2 cache memory. Our second contribution is to demonstrate, through extensive experiments, that a 3D L2 memory architecture generates much better results than the conventional two-dimensional (2D) designs under different number of layers and vertical (inter-wafer) connections. In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration. This also helps reduce power consumption in L2 due to a reduced number of data movements
11193384
Compiler-directed voltage scaling on communication links for reducing power consumption
Reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. Most of the prior efforts on network power optimization are hardware-based schemes. These schemes are predictive by definition as they control communication link status based on the observations made In the past. Since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. This paper proposes a compiler driven approach to communication link voltage management. In this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. This information along with network topology is used for identifying the link access patterns. These patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. Our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. We exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which In turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.
6208153
Maximizing data reuse for minimizing memory space requirements and execution cycles
Embedded systems in the form of vehicles and mobile devices such as wireless phones, automatic banking machines and new multi-modal devices operate under tight memory and power constraints. Therefore, their performance demands must be balanced very well against their memory space requirements and power consumption. Automatic tools that can optimize for memory space utilization and performance are expected to be increasingly important in the future as increasingly larger portions of embedded designs are being implemented in software. In this paper, we describe a novel optimization framework that can be used in two different ways: (i) deciding a suitable on-chip memory capacity for a given code, and (ii) restructuring the application code to make better use of the available on-chip memory space. While prior proposals have addressed these two questions, the solutions proposed in this paper are very aggressive in extracting and exploiting all data reuse in the application code, restricted only by inherent data dependences
17088807
Reducing NoC energy consumption through compiler-directed channel voltage scaling
While scalable NoC (Network-on-Chip) based communication architectures have clear advantages over long point-to-point communication channels, their power consumption can be very high. In contrast to most of the existing hardware-based efforts on NoC power optimization, this paper proposes a compiler-directed approach where the compiler decides the appropriate voltage/frequency levels to be used for each communication channel in the NoC. Our approach builds and operates on a novel graph based representation of a parallel program and has been implemented within an optimizing compiler and tested using 12 embedded benchmarks. Our experiments indicate that the proposed approach behaves better - from both performance and power perspectives - than a hardwarebased scheme and the energy savings it achieves are very close to the savings that could be obtained from an optimal, but hypothetical voltage/frequency scaling scheme.
8583268
Proportional degradation services in wireless/mobile adaptive multimedia networks
Adaptive multimedia services are very attractive since resources in wireless/mobile networks are relatively scarce and widely variable, and more importantly the resource fluctuation caused by mobility and channel fading can be mitigated using adaptive services. Therefore, there are extensive research activities on Quality of Service (QoS), call admission control, as well as bandwidth degradation and adaptation for adaptive multimedia services in wireless/mobile networks in recent years. However, fairness of bandwidth degradation has largely been ignored in previous work and remains an important issue in adaptive multimedia service provisioning. In this paper, we propose and study proportional degradation service provisioning in wireless/mobile networks that offer multiple classes of adaptive multimedia services. The proposed proportional degradation fairness model guarantees the proportional bandwidth degradation among different classes of services. Two proportional degradation scenarios are studied in this paper. In the first scenario, we study the proportional degradation provisioning with two QoS parameters for adaptive multimedia: the degradation ratio (DR) and the degradation degree (DD). In the second scenario, we study the proportional degradation provisioning with a new QoS parameter for adaptive multimedia: the degradation area (DA). For each scenario, based on the QoS parameters, proportional degradation adaptation algorithms are proposed to approximate the proportional degradation model, to fairly adapt calls' degradations, to utilize the system resource efficiently, as well as to optimize QoS parameters. Performance studies show that in the first scenario, proportional DR has been achieved very well, whereas proportional DD has not been well achieved. In other words, DR outperforms DD in terms of proportional degradation. In the second scenario, proportional DA has been well achieved. Furthermore, bandwidth resources have been efficiently utilized and DA has been minimized. Copyright © 2004 John Wiley & Sons, Ltd.
6484880
Spatio-temporal aggregation using sketches
Several spatio-temporal applications require the retrieval of summarized information about moving objects that lie in a query region during a query interval (e.g., the number of mobile users covered by a cell, traffic volume in a district, etc.). Existing solutions have the distinct counting problem: if an object remains in the query region for several timestamps during the query interval, it will be counted multiple times in the result. We solve this problem by integrating spatio-temporal indexes with sketches, traditionally used for approximate query processing. The proposed techniques can also be applied to reduce the space requirements of conventional spatio-temporal data and to mine spatio-temporal association rules.
35956760
Analysis of recursive feature elimination methods
Recursive feature elimination using SVM (SVM-RFE) has become an effective approach in selecting predictive features. For example, [1] found 8 genes from 7,000 for cancer prediction using SVM-RFE. It is not well understood, however, whether the success of SVM-RFE comes from the recursive process or the choice of the classifier? And, more generally, what property of a classifier would make it successful in RFE? We answer this question by examining multiple classifiers (SVM, ridge regression (RR) and Rocchio) with feature selection in recursive and non-recursive settings, on two DNA microarray datasets and a text categorization benchmark dataset (Reuters-21578).
2365659
A Trajectory-Preserving Synchronization Method for Collaborative Visualization
In the past decade, a lot of research work has been conducted to support collaborative visualization among remote users over the networks, allowing them to visualize and manipulate shared data for problem solving. There are many applications of collaborative visualization, such as oceanography, meteorology and medical science. To facilitate user interaction, a critical system requirement for collaborative visualization is to ensure that remote users would perceive a synchronized view of the shared data. Failing this requirement, the user's ability in performing the desirable collaborative tasks would be affected. In this paper, we propose a synchronization method to support collaborative visualization. It considers how interaction with dynamic objects is perceived by application participants under the existence of network latency, and remedies the motion trajectory of the dynamic objects. It also handles the false positive and false negative collision detection problems. The new method is particularly well designed for handling content changes due to unpredictable user interventions or object collisions. We demonstrate the effectiveness of our method through a number of experiments
15260186
Using recursive classification to discover predictive features
Finding most predictive features for statistical classification is a challenging problem and has important applications. Support Vector Machines (SVMs), for example, have been found successful with a recursive procedure in selecting most important genes for cancer prediction. It is not well understood, however, how much the success depends on the choice of the classifier, and how much on the recursive procedure. We answer this question by examining multiple classifiers (SVM, ridge regression and Rocchio) with feature selection in recursive and non-recursive settings, on a DNA microarray dataset (AMLALL) and a text categorization benchmark (Reuters-21578). We found recursive ridge regression most effective: its best classification performance (zero error) on the AMLALL dataset was obtained when using only 3 genes (selected from over 7000), which is more impressive than the best published result on the same benchmark - zero error of recursive SVM using 8 genes. On Reuters-21578, recursive ridge regression also achieves the best result ever published (the improvement was verified in a significance test). An in-depth analysis of the experimental results shows that the choice of classifier heavily influences the recursive feature selection process: the ridge regression classifier tends to penalize redundant features to a much larger extent than the SVM does.