206472480
Energy-Efficient Thread-Level Speculation
Chip multiprocessors with thread-level speculation have become the subject of intense research, this article refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism
14227266
Thread-Level Speculation on a CMP can be energy efficient
Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research. However, TLS is suspected of being too energy inefficient to compete against conventional processors. In this paper, we refute this claim. To do so, we first identify the main sources of dynamic energy consumption in TLS. Then, we present simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact. The resulting TLS CMP, populated with four 3-issue cores, speeds-up full SPECint 2000 codes by 1.27 on average, while keeping the fraction of the chip's energy consumption due to TLS to only 20%. Compared to a 6-issue superscalar at the same frequency, the TLS CMP is on average faster, while consuming only 85% of its total on-chip power.
10470214
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must exploit multiple sources of speculative task-level parallelism, including any nesting levels of both subroutines and loop iterations. Unfortunately, these environments are hard to support in decentralized CMP hardware: since tasks are spawned out-of-order and unpredictably, maintaining key TLS basics such as task ordering and efficient resource allocation is challenging.While the concept of out-of-order spawning is not new, this paper is the first to propose a set of microarchitectural mechanisms that, altogether, fundamentally enable fast TLS with out-of-order spawn in a CMP. Moreover, we develop a fully-automated TLS compiler for aggressive out-of-order spawn. With our mechanisms, a TLS CMP with four 4-issue cores achieves an average speedup of 1.30 for full SPECint 2000 applications; the corresponding speedup for in-order only spawn is 1.04. Overall, our mechanisms unlock the potential of TLS for the toughest applications.
1862113
iWatcher: efficient architectural support for software debugging
Recent impressive performance improvements in computer architecture have not led to significant gains in ease of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root cause of a bug. Moreover, program execution typically slows down significantly, often by 10-100 times. To address this problem, this paper introduces the Intelligent Watcher (iWatcher), novel architectural support to monitor dynamic execution with minimal overhead, automatically, and flexibly. iWatcher associates program-specified monitoring functions with memory locations. When any such location is accessed, the monitoring function is automatically triggered with low overhead. To further reduce overhead and support rollback, iWatcher can leverage Thread-Level Speculation (TLS). To test iWatcher, we use applications with various bugs. Our results show that iWatcher detects many more software bugs than Valgrind, a well-known open-source bug detector. Moreover, iWatcher only induces a 4-80% execution overhead, which is orders of magnitude less than Valgrind. Even with 20% of the dynamic loads monitored in a program, iWatcher adds only 66-174% overhead. Finally, TLS is effective at reducing overheads for programs with substantial monitoring.
893220
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Dynamic software bug detection tools are commonly used because they leverage run-time information. However, they suffer from a fundamental limitation, the path coverage problem: they detect bugs only in taken paths but not in non-taken paths. In other words, they require bugs to be exposed in the monitored execution. This paper makes one of the first attempts to address this fundamental problem with a simple hardware extension. First, we propose PathExpander, a novel design that dynamically increases the code path coverage of dynamic bug detection tools with no programmer involvement. As a program executes, PathExpander selectively executes non-taken paths in a sandbox without side effects. This enables dynamic bug detection tools to find bugs that are present in these non-taken paths and would otherwise not be detected. Second, we propose a simple hardware extension to control the huge overhead in its pure software implementation to a moderate level. To further minimize overhead, PathExpander provides an optimization option to execute non-taken paths on idle cores in chip multi-processor architectures that support speculative execution. To evaluate PathExpander, we use three dynamic bug detection methods: dynamic software-only checker (CCured), dynamic hardware-assisted checker (iWatcher) and assertions; and conduct side-by-side comparison with PathExpander's counterpart software implementation. Our experiments with seven buggy programs using general inputs that do not expose the tested bugs show that PathExpander is able to help these tools detect 21 (out of 38) tested bugs that are otherwise missed. This is because PathExpander increases the code coverage of each test case from 40% to 65% on average, based on the branch coverage metric. When applications are tested with multiple inputs, the cumulative coverage also significantly improves by 19%. We also show that PathExpander introduces modest false positives (4 on average) and overhead (less than 9.9%). The 3-4 orders of magnitude lower overhead compared with pure-software implementation further justifies the hardware design in PathExpander
8941770
Efficient and flexible architectural support for dynamic monitoring
Recent impressive performance improvements in computer architecture have not led to significant gains in the case of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root cause of a bug. Moreover, program execution typically slows down significantly, often by 10--100 times.To address this problem, this paper introduces the intelligent watcher (iWatcher), a novel architectural scheme to monitor dynamic execution automatically, flexibly, and with minimal overhead. iWatcher associates program-specified monitoring functions with memory locations. When any such location is accessed, the monitoring function is automatically triggered with low overhead. To further reduce overhead and support rollback, iWatcher can optionally leverage thread-level speculation (TLS). The iWatcher architecture can be used to detect various bugs, including buffer overflow, accessing freed locations, memory leaks, stack-smashing and value-invariant violations. To evaluate iWatcher, we use seven applications with various real and injected bugs. Our results show that iWatcher detects many more software bugs than Valgrind, a well-known open-source bug detector. Moreover, iWatcher only induces a 0.1--179&percent; execution overhead, which is orders of magnitude less than Valgrind. Our sensitivity study shows that even with 20&percent; of the dynamic loads monitored in a program, iWatcher adds only 72--182&percent; overhead. Finally, TLS is effective at reducing overheads for programs with substantial monitoring.
12391996
A Framework for Multi-Agent Belief Revision
ix
23049563
A Framework for Multi-Agent Belief Revision, Part I: The Role of Ontology
In this paper, we identify that failure to cater for the various forms of heterogeneity is one of the major drawbacks of the previous research on multi-agent belief revision (MABR). Three major categories of heterogeneity, namely social, semantic and syntactic heterogeneity are clarified. Several issues posed by such heterogeneities are addressed in the context of BR. The use of ontology is proposed as a powerful tool to tackle the heterogeneity issues so as to achieve the necessary reliable communication find system interoperability required by MABR. The question of what kind of ontology would be suitable to support MABR in a heterogenous setting is answered in Part I. In its sequel, Part II, a general framework for MABR is presented based on a shared knowledge structure which serves as the theoretical basis for ontology design.
5898020
Robust estimators for expression analysis
MOTIVATION
We consider the problem of estimating values associated with gene expression from oligonucleotide arrays. Such estimates should linearly track concentration, yield non-negative results, have statistical guarantees of robustness against outliers, and allow estimates of significance and variance.


RESULTS
A hierarchy of simple models is used to design robust estimators meeting these goals for both stand alone and comparative experiments. This algorithm has been validated against an extensive panel of known spike experiments, and shows comparable performance to existing standards.
13990206
Towards a flash search engine based on expressive semantics
Flash, as a multimedia format, becomes more and more popular on the Web. However, previous works on Flash are totally based on low-level features, which make it unpractical to build a content-based Flash search engine. To address this problem, our paper proposes expressive semantics for bridging the gap between low-level features and user queries. To smoothly incorporate expressive semantics into a search engine, an eigenvector-based model is devised to map a user query to expressive semantics with the aid of link analysis method. Our experiment results confirm that expressive semantics is a promising approach to understanding and hence searching Flash movies more efficiently.
5248211
A smart bi-directional telemetry unit for retinal prosthetic device
This paper describes a smart bi-directional telemetry unit for an implantable retinal prosthetic device. The system is designed to deliver 250 mW to the intra-ocular unit via an inductive link and provide wireless communication capability. A novel dual frequency carrier approach is used to optimize the power link for maximum transfer efficiency and the forward telemetry for high data rates. The power link uses a smart feedback system via reverse telemetry to compensate for instantaneous changes in power level due to coil misalignment and load variations. The system is optimized to minimize the power losses in the analog front-end of the intraocular unit while ensuring proper device operation. Preliminary results are shown in AMI 1.6 /spl mu/m bulk CMOS process for the reverse telemetry and power feedback system.