35844193
Design for testability and testing of IEEE 1149.1 TAP controller
The Test Access Port (TAP) controller is a very important circuit present in all IC chips that are compliant with the IEEE 1149.1 Boundary Scan standard. Although the main purpose of boundary scan is to facilitate board-level testing, it is also used for many other testing and non-testing purposes (e.g., memory and logic BIST wrappers to enable embedded core test, programming FPGAs, checkpointing and recovery of dependable systems, etc.). Hence, it is important to thoroughly test the TAP controller before using it for other purposes. In this paper, we present techniques for designing and testing the TAP controller. Our design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results. Our TAP controller design technique does not require any extra I/O pins and can be easily automated and incorporated into test tools.
2705949
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
900289
Techniques and algorithms for fault grading of FPGA interconnect test configurations
Conventional fault simulation techniques for field programmable gate arrays (FPGAs) are very complicated and time consuming. The alternative, FPGA fault emulation technique, is incomplete and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. The presented technique is able to report all detectable and undetectable faults and, compared with conventional methods, is orders of magnitude faster.
41662557
Soft Errors: Technology Trends, System Effects, and Protection Techniques
Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level modeling of soft errors, architectural impact of soft errors, challenges associated with evaluation of run-time behaviors of systems in the presence of soft errors, actual data on system behaviors in the presence of soft errors, metrics for quantifying soft error vulnerabilities, design of architectures with Built-in-Soft-Error-Resilience techniques, and actual case studies.
42903241
Test vector compression using EDA-ATE synergies
This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.
15807495
Application-independent testing of FPGA interconnects
We present a new automatic test-configuration-generation technique for application-independent manufacturing testing of the interconnection network of static-random-access-memory-based field programmable gate arrays (FPGAs). This technique targets detection of open and bridging faults in the wiring channels and programmable switches in the interconnects. Experimental results on Xilinx Virtex FPGAs show that very few test configurations are required to cover stuck-open, stuck-closed, open, and bridging faults in the interconnects.
45398591
A One Bit Facial Asymmetry Code (FAC) in Fourier Domain for Human Recognition
The present paper introduces a novel set of biometrics based on facial asymmetry measures in the frequency domain using a compact one-bit representation. A simplistic Hamming distance-type classifier is proposed as a means for matching bit patterns for identification purposes which is more efficient than PCA-based classifiers from storage and computation point of view, and produces equivalent results. A comparison with spatial intensity-based asymmetry measures suggests that our proposed measures are more robust to intra-personal distortions with a misclassification rate of only 4.24% on the standard facial expression database (Cohn-Kanade) consisting of 55 individuals. In addition, a rigorous statistical analysis of the matching algorithm is presented. The role of asymmetry of different face parts (e.g., eyes, mouth, nose) is investigated to determine which regions provide the maximum discrimination among individuals under different expressions.
45280262
Leveraging information in multi-echelon inventory systems
Abstract Decision-making in multi-echelon inventory systems is often facilitated by the availability of information. In this paper, we examine the effect of utilising demand information in a one-warehouse two-retailer system operating under periodic-review. A common and fixed replenishment interval is assumed for all stages. The lead times are deterministic, and are small compared to the replenishment interval. The warehouse does not maintain any cycle stock, i.e., as soon as replenishment arrives at the warehouse, retailers’ demands are fulfilled from the available stock. In the event of a shortage at the warehouse, two cases have been considered––emergency shipment and allocation. For both the cases, expected total cost (ETC) models have been developed, and it has been shown through numerical examples that the optimal ETC in the presence of demand information is always lower than that in the absence of demand information. It is also noted that the order-up-to level at the warehouse has to be dynamic to reap the benefits of availability of demand information.
33350706
Evolutionary Modular MLP with Rough Sets and ID3 Algorithm for Staging of Cervical Cancer
This paper describes a way of designing a hybrid system for detecting the different stages of cervical cancer. Hybridisation includes the evolution of knowledge-based subnetwork modules with GAs using rough set theory and the ID3 algorithm. Crude subnetworks for each module are initially obtained via rough set theory and the ID3 algorithm. These subnetworks are then combined, and the final network is evolved using genetic algorithms. The evol-ution uses a restricted mutation operator which utilises the knowledge of the modular structure, already generated, for faster convergence. The GA tunes the network weights and structure simultaneously. The aforesaid integration enhances the performance in terms of classification score, network size and training time, as compared to the conven-tional MLP. This methodology also helps in imposing a structure on the weights, which results in a network more suitable for rule extraction.
13253511
Verifying Average Dwell Time by Solving Optimization Problems
A switched system is a hybrid system whose discrete mechanisms are abstracted away in terms of an exogenous switching signal which brings about the mode switches. For switched systems, the Average Dwell time (ADT) property defines restricted classes of switching signals which can be used for proving stability. In this paper, we develop optimization-based methods for automatically verifying ADT properties of hybrid systems. This enables us to prove stability of hybrid systems, provided the individual modes of the system are stable. For two special classes of hybrid systems, we show that the resulting optimization problems can indeed be solved efficiently using standard mathematical programming techniques. We also present simulation relation-based proof methods for establishing equivalence of hybrid systems with respect to ADT. The proposed methods are applied to verify ADT properties of a linear hysteresis switch and a nondeterministic thermostat.
29308229
Safety Verification of Model Helicopter Controller Using Hybrid Input/Output Automata
This paper presents an application of the Hybrid I/O Automaton (HIOA) framework [12] in verifying a realistic hybrid system. A supervisory pitch controller for a model helicopter system is designed and then verified. The design of the supervisor is limited by the actuator bandwidth, the sensor inaccuracies, and the sampling rates. Verification is carried out by induction over the length of an execution of the composed system automaton. The HIOA model makes the inductive proofs tractable by decomposing them into independent discrete and continuous parts. The paper also presents a set of language constructs for specifying hybrid I/O automata.