1663822
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. JPEG2000 standard defines an irreversible DWT by a lifting scheme of factorized coefficients using (9, 7) Daubechies coefficients. The paper proposed optimizations on lifting based 1D-DWT data flow graph resulting in a new pipelining scheme, which is more power-efficient than existing approaches. The authors have shown that the constant multipliers defined by JPEG2000 standard, have latency of about 1.6 times the general adder latency. Hence, while finding the critical path, the basic assumption of multiplier latency being much greater than the adder latency does not hold for DWT in JPEG2000. How 75% multiplications can be reduced at the scaling step by this 2D-DWT implementation was also shown. This multiplication reduction not only saves power but also results in area saving by eliminating three multipliers in the hardware
17211338
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall power dissipation is dominated by read and write operations in the memory subsystem. The proposed architecture and computation sequence, called low-power block-scan, takes into account the EBCOT (embedded block coding with optimized truncation) code block size, which reduces the intermediate buffer requirement between the DWT and EBCOT modules. The impact of different memory subsystem optimization techniques on the overall memory power for 2D-DWT computation was modeled. The proposed model explores the different data access patterns, memory bank partitioning, and custom memory architectures to arrive at a power-efficient DWT architecture
16168118
Defect-aware design paradigm for reconfigurable architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to avoid defects. If nanotechnology based fabrications are applied, the yield may even go down to zero, as avoiding defects during fabrication will not be a feasible option. Hence, future architectures have to be defect-tolerant. Most of the current defect-tolerance schemes introduce redundancy in architecture to combat defects. Alternatively we can introduce defect tolerance in the design-flow. In this paper we analyze the bottlenecks faced by current design-methodologies while addressing defect tolerance. We study the performance of present place and route tools on a defective fabric in terms of area and critical delay penalty, and explore routing aware placement in this context. We have proposed a new cost function, CA-RISA for improving the performance in a defect-aware environment
9429113
Control theory optimization of MECN in satellite networks
Congestion in the Internet results in wasted bandwidth and also stands in the way of guaranteeing QoS. The effect of congestion is multiplied many fold in satellite networks, where the resources are very expensive. Thus congestion control has a special significance in the performance of satellite networks. In today's Internet, congestion control is implemented mostly using some of the de facto standard, RED. We have proposed previously a new scheme called the multi-level explicit congestion notification (MECN), which works with the framework of ECN, but enhances the performance using multiple level congestion feedback from the network. But like RED, the tuning of MECN could be a problem. Tuning of parameters is necessary for achieving high throughput with corresponding low delays. Also it is desirable to keep the oscillations in the queue low to reduce jitter, which is the major concern in real-time applications such as voice or video over IP. In this paper, we use a linearized fluid flow model of TCP-MECN to study the performance and stability of the queue in the router. We use classical control tools such as delay margin and tracking error to provide guidelines for optimizing satellite IP networks, which use MECN. We apply our results for optimizing the performance of satellite networks. We use ns simulator to validate the results of our analysis.
6846204
Improving explicit congestion notification with the mark-front strategy
Abstract Delivering congestion signals is essential to the performance of networks. Current TCP/IP networks use packet losses to signal congestion. Packet loss not only reduces TCP performance, but also adds large delay. Explicit congestion notification (ECN) delivers a faster indication of congestion and has better performance. However, current ECN implementations mark the packet from the tail of the queue. In this paper, we propose the mark-front strategy to send an even faster congestion signal. We show that mark-front strategy reduces buffer size requirement, improves link efficiency and provides better fairness among users. Simulation results that verify our analysis are also presented.
26267925
Divergence of Timeout Algorithms for Packet Retransmissions
The problem of adaptively setting the timeout interval for retransmitting a packet has been discussed. A layered view of the algorithms has been presented. It is shown that a timeout algorithm consists of essentially five layers or procedures which can be independently chosen and modified. A number of timeout algorithms proposed in the literature have been decomposed into these five layers. 
One of the key layers not discussed in the literature is that of determining the sample round trip delay for packets that have been transmitted more than once. It is shown that this layer has a significant impact on the network performance. 
Under repeated packet loss, most timeout algorithms either diverge or converge to a wrong value. A number of alternative schemes have been presented. It is argued that divergence is preferable to false convergence. It is a feature that is helpful in reducing network traffic congestion.
56552
Buffer Requirements For TCP/IP Over ABR
We study the buffering requirements for zero cell loss for TCP over ABR. We show that the maximum buffers required at the switch is proportional to the maximum round trip time (RTT) of all VCs through the link. The number of round-trips depends upon the the switch algorithm used. With our ERICA [erica-final] switch algorithm, we find that the buffering required is independent of the number of TCP sources. We substantiate our arguments with simulation results.
5474275
Overload based explicit rate switch schemes with MCR guarantees
An explicit rate switch scheme monitors the load at each link and gives feedback to the sources. We define the overload factor as the ratio of the input rate to the available capacity. In this paper, we present three overload-based switch schemes which provide MCR (minimum cell rate) guarantees for the ATM (asynchronous transfer mode) ABR (available bit rate) service. The switch schemes proposed use the overload factor and other terms including current source rate and target utilization to calculate feedback rates. A dynamic queue control mechanism is used to achieve efficient usage of the link, control queues and, achieve constant queuing delay at steady state. The proposed algorithms are studied and compared using several configurations. The configurations were chosen to test the performance of the algorithms in the presence of link bottlenecks, source bottlenecks and transient sources. Finally, a comparison of the proposed algorithms based on the simulation results is given.