1639978
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring delays, network-on-chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust. Both NoC performance and energy budget depend heavily on the routers' buffer resources. This paper introduces a novel unified buffer structure, called the dynamic virtual channel regulator (ViChaR), which dynamically allocates virtual channels (VC) and buffer resources according to network traffic conditions. ViChaR maximizes throughput by dispensing a variable number of VCs on demand. Simulation results using a cycle-accurate simulator show a performance increase of 25% on average over an equal-size generic router buffer, or similar performance using a 50% smaller buffer. ViChaR's ability to provide similar performance with half the buffer size of a generic router is of paramount importance, since this can yield total area and power savings of 30% and 34%, respectively, based on synthesized designs in 90 nm technology
12627938
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analysis of these reliability hazards and the incorporation of comprehensive protection measures into all network-on-chip (NoC) designs. In this paper, we examine the impact of transient failures on the reliability of on-chip interconnects and develop comprehensive counter-measures to either prevent or recover from them. In this regard, we propose several novel schemes to remedy various kinds of soft error symptoms, while keeping area and power overhead at a minimum. Our proposed solutions are architected to fully exploit the available infrastructures in an NoC and enable versatile reuse of valuable resources. The effectiveness of the proposed techniques has been validated using a cycle-accurate simulator
15201877
A stable feedback control of the buffer state using the controlled Lagrange multiplier method
We propose a stable feedback control algorithm of the buffer state using the controlled Lagrange multiplier in combined rate-distortion characteristics for a buffer-constrained adaptive quantization. The proposed algorithm is established using feedback control theory and is described by the state equation with nonlinearity in the feedback path. The nonlinearity of the state equation comes from the average distortion-rate curve of the information source. The stability of this buffer control algorithm is shown using Lyapunov stability theory. It is shown that the stability of the algorithm depends on average distortion-rate curve and buffer size, and sufficient conditions for the algorithm to be stable are obtained from the usual average distortion-rate curve. In addition, it is observed from experimental results that the performance of the proposed algorithm and the optimal algorithm is not significantly different. Although the proposed algorithm does not provide optimal performance, the algorithm can be implemented easily with quite low computational complexity, as compared with others.
38006761
Adaptive Bayesian decision model for motion segmentation
Abstract A new method is proposed for modeling of the target and background event based on the classical decision theory using a Bayesian model. The implementation of an adaptive video motion detection system at the existing board level is also addressed using DATACUBE image processing hardware.