Planarization techniques for multilevel HTS integrated circuit process
Various approaches to achieve planarization for a multilevel Y/sub 1/Ba/sub 2/Cu/sub 3/O/sub 7-x/ (YBCO) circuit process are discussed and compared. Results on ion beam planarization (IBP) and etch-back planarization (EBP) techniques are reported, and their application to a potential high-temperature superconductive (HTS) circuit process is demonstrated. Since IBP is based on the mechanical action of etching, its advantage is that, in principle, it can be used to planarize any dielectric film. But it does not have much selectivity; hence, it is very difficult to control etching in a multilayer process. The success of this technique also depends, to some extent, on the pattern to be planarized. As seen from the experimental results, the degree of planarization (DOP) varies inversely, with the linewidth of the pattern. The DOP for 1- mu m line was found to be more than 70% after 45 min of ion milling. In the EBP technique using dry etching, a DOP of around 60% was obtained. This can be improved with thicker resist layers. In wet etching selectivity can be put to an advantage so that etching can be stopped at a desired point.<<ETX>>