Implementation of single bit Error detection and Correction using Embedded hamming scheme
Multiple bit upsets due to radiation-induced soft errors are a major concern in Nano scale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx SPARTAN 3 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous scheme. Hamming and embedded hamming schemes are proposed from the literature survey and memory overhead is reduced in order toachieve the successful implementation of error detection and correction codes. Keywords-Hammingcode, Embedded hamming code, Xilinx,moore‟s law,Spartan3