Using error tolerance of target application for efficient reliability improvement of digital circuits
With the technology scaling, nanoscale devices are becoming more and more sensitive to external influences. Reliability analysis is expected to play a major role for the design process of nanoscale systems. In fact, understanding the relations between circuit structure and its reliability allows the designer to implement tradeoffs that can improve the resulting design. In this work, we propose and verify a method for reliability evaluation, named effective reliability, that can tolerate errors based on a pertinent quality metric. In order to demonstrate the impact of the proposed approach, we designed two operators using reliability as a constraint: an 8-bit ripple carry adder and a 4-bit multiplier. Comparing the resulting designs using the traditional reliability evaluation method and the proposed one, we can observe significant savings in circuit area.