Building ATMR circuits using approximate library and heuristic approaches
Abstract Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.