Single Event Upset Sensitivity of D-Flip Flop: Comparison of PDSOI With Bulk Si at 130 nm Technology Node
Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers in D flip-flop chains are used to determine the impact of various cell designs and PDSOI hardening technique on upset sensitivity. Various flip-flops are designed and connected as shift-register chains, and the error numbers induced by irradiation are recorded to examine the effectiveness of the PDSOI technology. It was found that PDSOI technology has better performance in terms of upset robustness versus bulk Si at the 130nm technology node. The same design structure implemented in PDSOI technology has higher SEU threshold LET and much lower saturation cross section due to its full dielectric isolation structure which does not allow the charge generated in the substrate to be collected by the electrically active junctions in the thin top region of the device and reduces the sensitive volume of p-n junctions in the transistor. As shown in the experiment result, NRH_SOI (not radiation hardening SOI) saves about 25% area while having much lower SER versus DICE_Si, which means PDSOI still has obvious advantage at reducing SEU rate, even though its necessary body contact has to consume certain extra area.