VLSI Implementation of High-speed AES IP Core
This paper presented a new VLSI architecture for the high-speed AES IP core. To achieve this aim, some efficient solutions are proposed. And at algorithmic level, the mixcolumn module in key expand module is removed but keeping the result right. At circuit level, the pipeline technology is introduced for outer and inner of the round operation, which can reduce the critical path, then increase the maximum frequency, also can improve the data throughput. Based on SMIC 0.18um CMOS technology, 400MHz clock frequency is achieved and the data throughput rate is 51.2 Gbps with the area cost of 164 K-gates.