Comparison of different on-chip ESD protection structures in a 0.35 μm CMOS technology
In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifinger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (HBM) and Charged Device Model (CDM) test results, as well as Transmission Line Measurement (TLM) and light emission results support this finding.