Improved layout of the odd-even sorting network
Sorting networks are of great interest in many VLSI architectures. We study a problem of minimizing area of odd-even sorting network (defined by Batcher). By now, the best known result is presented by Shimon Even in 2001 - a layout of 3N^2 area. In this paper, we describe layouts, of 2N^2 and 213N^2 with and without knock-knees, respectively.