A 0.18 μm CMOS linear-in-dB AGC post-amplifier for optical communications
Abstract This paper presents a fully integrated 10GBase-LX4 Ethernet receiver front-end automatic gain control amplifier realized in a 0.18 μm CMOS process. Based on a very compact and reliable inductorless design, the proposed differential post-amplifier, comprises three main digitally programmable gain stages, a DC offset cancellation network and an automatic gain feedback control loop. Experimental results demonstrate a −3 dB cut-off frequency above 2.3 GHz over a −3 to 33 dB linear-in-dB controlled gain range with a sensitivity of 2.0 mV p–p with a BER of 10 −12 at 2.5 Gb/s. For the aforementioned standard, 3.125 Gb/s, an input dynamic range above 50 dB is achieved, from 2.5 mV p–p to 800 mV p–p , indicating a BER of 10 −12 . The chip core area is 0.3 × 0.3 mm 2 and it consumes 58 mW with a single supply voltage of 1.8 V.