Statistical distributions of row-hammering induced failures in DDR3 components
Abstract As process technology shrinks down, the distances among storage cells in DRAMs gets smaller. Smaller distances among cells cause the cell-to-cell interference to increase. Due to the proximity to neighboring cells, a DRAM cell loses the stored charge in the cell faster with repetitive accesses on an adjacent row. Such phenomenon is known as row hammering failure and has been reported to occur in the commodity DDR3 components manufactured with the process technologies under 3 × nm technology. This work developed a statistical model of row hammering failures based on experimental results obtained with commodity DDR3 SDRAMs of 3 × nm technology. The statistical distribution for the failing rows with respect to the number of hammerings matched the normal distribution. The means μ HMR and standard deviations σ HMR of the number of hammerings that cause row hammering failure were apparently different among three different manufacturers. The means of the manufacturers varied by more than 200% and could be sufficiently used to characterize the reliability of the device from a row hammering stress perspective. Based on the derived statistical model, the failed parts-per-million (ppm) was calculated to give, on average, 164.6, 82.6 and 22.2, respectively, for the manufacturers.