Investigation on the origin of the anomalous tail bits on nitrided charge trap flash memory
Abstract In this work, the origin of the anomalous tail bits have been examined thoroughly on 43 nm nitride based charge trap flash memory devices. Tunnel oxide nitridation was implemented on the device under study to enhance its immunity to charge loss mechanism. Due to the extensive program/erase cycling, the increment in the defect density in tunnel oxide layer has generated significant tail bits that exhibited detrimental charge loss at room temperature. The findings have indicated that these tail bits are attributed to randomly distributed defects due to extensive program/erase cycling stress. Furthermore, these tail bits enhanced with longer storage duration at room temperature but deterred at high storage temperature. In this work, the anomalous tail bits were suppressed at high storage temperature. The underlying physical mechanism for these anomalous tail bits was found to be attributed to trap-assisted-tunneling mechanism that enables trapped charges from nitride storage layer to leak out along the vertical path of oxide–nitride–oxide stack of nitrided flash memory. These findings have implied that the anomalous tail bits are one of the critical reliability concerns that need to be addressed to achieve desired reliability performance. This work also demonstrated that room temperature storage test is a critical test to investigate the generation of the detrimental anomalous tail bits in reliability characterization and qualification for future nitrided flash memory.