Understanding the Key Parameter Dependences Influencing the Soft-Error Susceptibility of Standard Combinational Logic
This article presents neutron radiation-induced soft error rate (SER) statistics and detailed analysis thereof, revealing a multitude of circuit parameters impacting the soft-error susceptibility of standard combinational logic in advanced CMOS nodes. A high-density array-based soft-error characterization vehicle is presented, featuring standard logic gate chains of varying lengths. Neutron irradiation data obtained from gate variants employing devices with distinct channel widths and threshold voltage flavors is analyzed at multiple supply voltages, ranging from nominal down to near-threshold. Supplemented with first-order simulations, measured SER cross-section results obtained from test structures implemented in a 65-nm planar CMOS technology node reveal the complex interplay between factors, such as supply voltage, node capacitance, restore current ( $I_{\mathrm {RESTORE}}$ ), gate topology, and logic chain length responsible in contributing toward the collective soft error susceptibility of a standard gate type, which constitutes the main focus of this article. In addition, the easy process portability of the proposed macro is demonstrated through implementation in a 16-nm FinFET process.