Digital control system monitor having a predetermined output under fault conditions
An electrical control system monitor includes a microprocessor which conducts a series of control and test functions and outputs a sequence of data words which are representative of the operating status of the system being monitored and the monitor itself. This sequence of data words is fed to a comparator along with a second sequence of data words. Corresponding data words from the two sequences are presented to the comparator during successive partially overlapping time intervals. The comparator produces a given logic level output when its inputs agree and a second given logic level output when its inputs disagree. If the comparator output does not oscillate in a prescribed manner, the output of the monitor is forced into a predetermined output state.