Analysis and suppression of drain current drift in graphene FETs
The cause of drain current (ID) drift in graphene field-effect transistors is analyzed and a method to suppress the drift is proposed. By analyzing ID-time characteristics, a condition of reasonable gate, drain and source biases (VG, VD, and VS) is proposed to suppress ID drift. Based on this result, we find a condition for VG during off-time (Vbase), VD, and VS in pulsed I-V measurement to obtain the intrinsic ID-VG curves, and analyze the effect of Vbase on the Dirac point shift. Through an analysis of ID-time characteristics depending on VG, ID drift according to the range of VG is explained.