Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI
ion, 7 Addition block carry lookahead generator (BCLG), 36 carry lookahead adder (CLA), 34 carry lookahead generator (CLG), 34 carry propagate addition (CPA), 29 carry select adder (CSEA), 43 carry skip adder (CKSA), 40 generate, 29 half adders, 28 prefix adder, 49 propagate, 29 reduced full adder (RFA), 38 ripple carry adder (RCA), 30 ripple carry adder/subtractor (RCAS), 31 Baseline units, 5 Booth decoder, 91 Booth selector, 91 Booth’s algorithm, 86 Brent-Kung adder, 51 Canonical SD representation, 85 Carry chain, 29 Carry propagate addition, 57 Carry save example, 58 Column compression multipler, 66 Control logic, 4 Convergence, 163 Counter, 29 Dadda’s reduction, 65 Datapath design, 3 DesignWare example, 24 Desing process, 9 Device under test (DUT), 18 DEVS, 22 Digit recurrence, 104 Divide and conquer, 15 Dividend, 114 Division constant comparison, 107 continuity, 106 overlapping stages, 124 quotient overlap, 107 radix 16 division, 122 radix 2 division, 112 radix 4 division with carry-save adder, 119 radix 4 division, 115 selection interval, 106 Divisor, 114 Elementary function bipartite table methods, 141 SBTM, 142 STAM, 143 constant approximation, 133 CORDIC, 147 linear approximation, 136 piecewise constant approximation, 134 table lookup, 131 Error analysis, 129 Fractional multiplication, 92 Gajski-Kuhn Y chart, 8 Golden file, 19 Goldschmidt’s Division example, 167 Goldschmidt’s division, 166 Hierarchy, 8 Logarithmic shifter, 152 Maple, 137 Minimax, 137 Modified full adder (MFA), 60 Most Significant Digit First (MSDF), 108 Multiplexor, 43 Multiplicand, 56 Multiplication matrix, 56 Multiplication carry save array Booth multiplier, 88 radix-4 modified Booth multiplier, 89 signed modified radix4 modified Booth multiplier, 91 steps, 56 tree multiplier, 61 180 DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN Dadda multiplier, 65 Reduced Area (RA) multiplier, 68 Wallace multiplier, 61 truncated multiplication, 72 constant correction truncated multiplier (CCT), 72 hybrid correction truncated (VCT) multiplier, 76 variable correction truncated (VCT) multiplier, 73 two’s complement multiplication, 78 unsigned binary multiplication, 56 Multiplicative divide, 161 division by convergence, 166 Newton-Raphson, 161 Multiplier, 56 Negating modified full adder (NMFA), 81 Newton-Raphson Division example, 162 Objective, 2 On-the-fly-conversion, 108 Parallel multiplier, 55 Parallel prefix addition, 47 Partial product reduction, 63 Partial remainder, 115 Pentium bug, 17 PLA, 107 Product, 56 QST, 104 Quadratic convergence, 161 Quotient digit selection, 105 Quotient, 103 Recurrence relation, 104 Reduced full adder (RFA), 73 Redundant adder, 118 Round to nearest-even (RNE), 138 Rounding, 138 RTL level, 2 Serial multiplier, 55 Siged Digit (SD) numbers, 82 SRT, 113 Symmetry for SBTM and STAM, 145 Time borrowing, 4 Unit in the last position (ulp), 81 Verilog bitwise operator, 87 concatenation, 19 delay-based timing, 23 DesignWare, 24 event-based timing, 23 full adders, 29 IEEE1364-1995, 1 IEEE1364-2001, 24 IEEE1364.1, 13 instantiation, 11 intellectual property (IP), 24 memory, 14 ROM, 15 module call, 16 module declaration, 16 module structure, 15 naming methodology, 10 nets, 12 number readability, 11 output format, 21 radices, 11 registers, 13 replication, 21 standard output, 21 stopping a stimulation, 21 test bench design, 19 test bench, 18 testing methodology, 17 testing, 16 timing, 22 vectors, 14 wire naming convention, 25 Wallace’s equation, 62 Wire naming convention, 25