Latchup in voltage tolerant circuits: a new phenomenon
Abstract The semiconductor industry relies on latchup testing of integrated circuits (ICs) to detect and prevent catastrophic failures under extreme conditions. The test is mandatory to ensure that parasitic components do not adversely affect the normal behavior of the ICs, especially in CMOS technologies. This phenomenon has been well documented over the years. For the newer technologies with lower power consumption (supplies in the range of 1–2 V), one might consider them to be less susceptible to latchup. However, the presently designed ICs with nanometer technologies continue to require “high voltage” interface compatibility through applications such as PCI, etc. Moreover, some of the IC pins are exposed to much higher level ESD stresses (IEC test) due to pin connections between systems. As a consequence, latchup has become more difficult while manifesting itself into new scenarios including system level ESD effects. This paper first reviews the background of the latchup phenomenon and then introduces a new form of latchup called Signal Latchup that could very well be a critical issue for the newer IC applications where high voltage compatibility is required. In this same context, System Level ESD latchup is also described. This paper gives the background of CMOS latchup, followed by a description of the latchup initiation and latchup immunity test methods. The system board reliability is discussed. The new Signal Latchup phenomenon is introduced. An illustration of Signal Latchup occurring in voltage tolerant circuits and the design improvement to overcome this are presented in detail. The impact of process technology on these new latchup effects is evaluated and the system ESD latchup is presented. The Signal Latchup and ESD system Latchup testing is covered. Finally, the conclusions are given.