Single event upset test structures for digital CMOS application specific integrated circuits
A test structure methodology for digital CMOS ASICs (application-specific integrated circuits) that can be used to evaluate the hardness of various ASIC libraries and processes is described. The method identifies categories of ASIC cells and uses a select set of worst-case test structures to obtain the parameters necessary to evaluate a library and process, and make a tractable, bounded estimate of the expected chip hardness. In addition, if the error rates prove to be excessive, this method helps identify the cells in which hardening efforts will be most productive. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU (single event upset) response and designing a structure to characterize each response for each category. These methods are being applied in the development of ASIC options for hardened chip design and have already been used to design an SEU hardened ASIC controller. >