High-throughput Layered Decoder Design for LDPC Codes
A novel quasi-parallel layered LDPC decoder was presented,which can complete real-time decoding for 1/2 code rate,(3,6) regular QC-LDPC code with 4608-bit code length.Whole design was synthesized under Stratix II EP2S60 FPGA of Altera,Inc.Highest clock frequency after routed reaches 94.47 MHz,when maximum iterative No.is set to 25,corresponding decoder throughputs come to over 58 Mbps.Compared with traditional TPMP decoding strategy,average iterative No.were decreased nearly by half,consumed RAM block No.were reduced greatly,too.With LDPC parity-check matrix pattern plus row-weight information recorded,this LDPC decoder also can support any code lengths and code rates for arbitrary QC-LDPC codes.