Design-in-reliability: From library modeling and optimization to gate-level verification
Abstract A novel and comprehensive framework for aging analysis is presented in this work, comprehending degradation from BTI, hot-carriers and electro-migration. For the first time, all the primary variables affecting the aging of an interconnect and the transistor – namely, the equivalent duty-cycles, slews and frequencies are incorporated into the calculation. Additionally, from electro-migration stand-point, the framework allows calculation of the exact RMS and ‘recovered’ average current for every metal segment internal to the circuit, thus making it practically a universal model for aging analysis. Through detailed waveform-processor developed for validation, the aging model is ensured to be within 5% of exact SPICE calculations. The immediate application of such an extensive and accurate modeling is drawn in terms of influencing changes to the library design/architecture itself, showcased through circuit and layout optimization from EM, hot-carriers and NBTI constraints. Finally, we demonstrate the ultimate benefit from such a library model for doing exact gate-level aging analysis, as well as against asymmetric aging. Results from 28 nm production library models and complex SoC are shared.