Reliability improvement of EEPROM by using WSi2 polycide gate
Abstract Recent technology fabrication of EEPROM developed by STMicroelectronics involves tungsten-based polycide for the gate of the transistors. The EEPROM design is based on one floating gate. The main objective was to increase the data retention capability on product using this polycide, and this after cycling. Thus, we have set up a new process called integrated process involving a cluster tool which avoids any contamination during the manufacturing of the polycide stacked layers in comparison with the standard process. In addition, the tungsten chemistry induces an insertion of fluorine in the tunnel oxide. The presence of the fluorine is verified and can explain the modification of the threshold voltages and the evolution of the programming window. Analyses of test cells and product vehicles were made. This new process improves the data retention capability of the EEPROM after one million cycles, and also decreases the cumulative percentage of defects; these results were good enough to insert this process in the production line.