Design and analysis of a self-testing-and-repairing random access memory “STAR–RAM” with error correction
Abstract This paper presents the philosophy and design of a fault-tolerant dynamically-reconfigurable random access memory (RAM) system with a built-in Self-Testing-And-Repairing “STAR” engine. The STAR engine, supported by SEC–DED capability, provides on-line fault detection, correction, analysis and repair without destroying useful data stored in the memory. Reliability analysis of the presented system has been accomplished using a SMART simulation approach [1] , and results show significant reliability enhancement over SEC–DED RAM designs. The memory system employs a hardware parallel address-comparison mechanism for rapid processing of incoming addresses during normal read/write operations to minimize memory access delay. The flexible STAR architecture and the low hardware overhead enables utilization of the proposed approach in VLSI memory chips as well as in WSI and large memory modules.