Simulation of design dependent failure exposure levels for CMOS ICs
The effects of design and bias on the radiation tolerance of ICs are studied, and an automated design tool is described that produces different designs for a logic function and presents important parameters of each design to a circuit designer for tradeoff analysis. It was shown by simulation and experimentally verified that the logic implementation of a circuit and the bias applied during irradiation are significant in determining the radiation tolerance of ICs. The software package aids designers in designing radiation-hard integrated circuits. >