Effect of dopants on the thermal processing of salicided (titanium disilicided) CMOS structures
The effect of thermal processing on salicided (self-aligned TiSi2) CMOS structures with phosphorus-doped gates has been investigated in the temperature range of 800-1000 degrees C. The salicided layer in the submicrometre structures reported in this paper was formed by rapid thermal processing of the titanium film on doped substrates in a nitrogen ambient. The interface contact resistance as a function of temperature (i.e. TiSi2/Si contact resistance) increases for both n-(As) and p-(BF2) implanted junctions, the increase is greater for the case of p (BF2) junctions. The sheet resistances measured on Van der Pauw patterns (large area) are affected by annealing temperature, time and dopant species, in addition to the substrate microstructure. The BF2-implanted phosphorus-doped polysilicon shows the maximum increase in sheet resistance on Van der Pauw patterns with thermal processing, as compared with any other case. The narrower (1.0 mu m) runners of polysilicon show greater increase in sheet resistances on thermal processing than do large-area Van der Pauw patterns.