A switched priority scheduling mechanism for ATM switches with multi-class output buffers
Abstract In this paper, we propose a switched priority scheduling mechanism for an Asynchronous Transfer Mode (ATM) switch with multi-class output buffers. The switched priority scheduling mechanism is composed of a model-based linear controller, a heuristic nonlinear controller and the corresponding switching law of the controllers. The nonlinear controller is first applied to bring each class buffer into a small neighborhood of its operating point such that the linear controller can be used. The linear controller is then used to ensure that each buffer occupancy converges to its desired operating point. The service rate of each class buffer is periodically computed and dynamically adjusted. We derive the design formulae of the control mechanism such that each buffer occupancy globally converges to its desired operating point related to quality-of-service requirements.