An application specific instruction set processor (ASIP) for the niederreiter cryptosystem
The Niederreiter public-key cryptosystem forms its security basis over the assumption that decoding generic linear binary codes is NP complete, and therefore is regarded as an alternative post-quantum solution to resist attacks based on quantum computing. Existing hardware implementations for the Niederreiter cryptosystem mostly focus on data encryption/decryption, few of which consider the adoption of digital signature since the signature scheme differs significantly from the encryption/decryption scheme. In this work, we provide a unified architecture to achieve efficient Niederreiter digital signature and extend it to perform encryption/decryption on reconfigurable hardware. FPGA experiments show that the proposed unified architecture can achieve encryption, decryption and signature with 1.41 μs, 798.57 μs and 14.07 s respectively while maintaining acceptable area tradeoffs (4254 × slices, 29×36Kb-BRAMs and 3 × DSPs) on a Virtex-6 device.