Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View
New Number Field Sieves (NFS) attacks on the discrete logarithm problem have led to increase the key size of pairing-based cryptography and more precisely pairings on most popular curves like BN. To ensure 128-bit security level, recent costs estimations recommand to switch for BLS24 curves. However, using BLS24 curves for pairing requires to have an efficient arithmetic in Fp4 . In this paper, we transposed previous work on multiplication over extesnsion fields using Newton’s interpolation to construct a new formula for multiplication in Fp4 and propose time× area efficient hardware implementation of this operation. This co-processor is implemented on Kintex-7 Xilinx FPGA. The efficiency of our design in terms of time× area is almost 3 times better than previous specific architecture for multiplication in Fp4 . Our architecture is used to estimate the efficiency of hardware implementations of full pairings on BLS12 and BLS24 curves with a 128-bit security level. This co-processeur can be easily modified to anticipate further curve changes.