Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology
This paper focuses on the design and optimization of different power P-channel LDMOS transistors (VBR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (Ron-sp/VBR trade-off) and dynamic (Ron × Qg) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor Ron-sp/VBR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance.