Gate recess structure engineering using silicon-nitride-assisted process for increased breakdown voltage in pseudomorphic HEMTs
We report the fabrication of pseudomorphic high electron mobility transistors (pHEMTs) with engineered recess structure of any width of choice, by a single lithography and etching step with the help of silicon-nitride-assisted process. In this process, a silicon nitride layer is deposited prior to gate lithography. First, the silicon nitride is etched by buffered hydrofluoric acid (BHF) in the gate opening and then selective recessing is performed. The recess base width can be engineered by varying etch time of silicon nitride in BHF. The base width increases linearly with etch time as shown by SEM. We demonstrate that the top photoresist gate opening that decides the gate length is unaffected by any duration of silicon nitride etch time. Thereby, we have engineered the distance from gate edge to n+-GaAs (Lgn+) which decides the gate-to-drain breakdown voltage (BVgd). With this method, BVgd?increased from 12 to 20?V as a function of Lgn+. The electric field distribution across the recess structure has been simulated to interpret this result. Since the high BVgd?of pHEMT is essential for power applications as well as switch applications, this method can be easily adopted even though the corresponding reduction in transconductance and unit current gain cut-off frequency (ft) is only marginal from 375 to 350 mS mm?1?and from 39 to 31?GHz, respectively.