Surface ESD (ESDFOS) in assembly fab machineries as a functional and reliability risk - Failure analysis, tool diagnosis and on-site-remedies
Abstract ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. However, during the device assembly, wafers and bare dies are subject to fully robotic processed, where they are partially mounted even on electrostatic active protection (backgrinding) and carrier foils (wafer dicing). In addition, water cleaning/spraying steps are included in assembly processing. Many of these processes include high risks of generating electrostatic charge; subsequent discharge into devices, however, directly happens into the chip surface, by cracking slightly the passivation layer. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS. This failure type frequently is mixed up with other mechanisms, since it sometimes looks like mechanical damage. The tutorial introduces into basics of electrostatics, shows the failure texture on semiconductor devices and explains the engineering approach how to handle such cases in assembly lines by useful tool-specific ESD risk assessments.