Design and Implementation of Pipelining Reversible S-BOX in AES Algorithm
In AES Algorithm,S-BOX is a nonlinear Substitute Bytes,larger proportion and important processing of AES.In this paper,S-box algorithm and characteristics with Fermat's theorem is analyzed,base on this algorithm,we de-signed a reversible S-BOX circuit in Verilog HDL,reversible S-BOX is realized by FPGA.The reversible S-BOX cir-cuit is composed of pipelining circuit,with small-scale,and high speede,it implements both S-BOX and inverse S-BOX operations for speeding up the process of reversible s-box operations,reducing the scale of AES encryption and decrypt-ion circuit,these circuits hold practical value to AES Algorithm with Hardware implementation.