Challenges in hardening technologies using shallow-trench isolation
Challenges related to radiation hardening CMOS technologies with shallow-trench isolation are explored. It is shown that developing a radiation-hardened CMOS technology with shallow trench isolation is more complex than using a traditional hardened field oxide as the trench insulator. We illustrate the use of device simulations in concert with measurements on test structures to provide detailed physical insight into methods for improving total-dose radiation response. Mechanisms that can limit the total-dose radiation hardness of shallow trench isolation such as high electric fields and ion implantation damage are explored. We demonstrate the successful conversion of a non-radiation hardened technology with LOCOS isolation (Sandia's CMOS6) into a greater than 1 Mrad(SiO/sub 2/) radiation-hardened shallow-trench isolated technology (Sandia's CMOS6r).