Peak minimisation based gate delay compensation for active current balancing of parallel IGBT system
Abstract The non-uniform current sharing among the paralleled devices is consequential due to non-identical layout and alteration in parameters of the system consists of power semiconductor devices and gate drivers. The persistent non-uniform current among the paralleled devices arise the various concerns such as de-rating, uneven losses, and heat consequently can lead to reliability and failure issues of the system. This paper presents a simple yet intelligent and effective automatic control for gate delay compensation to achieve active current balancing through current peak minimisation. The current peak minimisation control approach can serve the purpose of minimising system de-rating as well as obtaining nearly uniform dynamic current sharing. The four parallel connected discrete IGBT system is used for experimental validation under unbalanced operating condition. Moreover, the current peak minimization trend evaluation is introduced for gate delay compensation.