Cache lifetime enhancement technique using hybrid cache-replacement-policy
Abstract Driven by the trends of emerging technologies in memories, a non-volatile memory (NVM) has been considered as an alternate technology to replace SRAM in an on-chip cache. Spin-transfer torque random access memory (STT-RAM), a new type of NVM technology has low leakage power and huge density of cells. Besides having advantages, the emerging NVM technologies have limited writes and huge error rates. The write endurance and error rates are influenced by the cache replacement algorithm, which ultimately dictates the lifetime of a cache. Hence, it becomes necessary to develop or modify the cache replacement algorithms for improving the lifetime of the STT-RAM caches. The proposed Hybrid-Cache-Replacement (HCR) policy reduces the impact of the replacement algorithm in such a way that its write endurance improves with reduction in error rate. The incoming data are appropriately placed in the existing block, which have minimum error rates and less number of writes. It has been implemented by comparing the incoming bits with the existing bits in a cache set. The simulation results show that the lifespan of the STT-RAM caches improves by 135%, 165% and 27% along with 2%, 2% and 1% performance overhead when compared to the existing methods.