Failure analysis defect location on a real case 55 nm memory using dynamic power supply emulation
Abstract Static and dynamic techniques for defect location are well established in the failure analysis flow of a failing integrated circuit. When a circuit shows an overconsumption on power supply, the useful static techniques are laser stimulation (OBIRCH, TIVA, LIVA, etc.) or photoemission. When the electrical signature is a soft fail, a functional fault or a timing issue the analyst will use dynamic techniques like dynamic laser mapping (SDL, xVM, LVI, etc.), dynamic photoemission or internal probing (Ebeam, TRE, LVP, etc.) by applying a looping test sequence which emulates the fail. In this paper we will present a real case analysis on a circuit showing a static signature (over consumption) and also a functional fault. Both static and dynamic location techniques have been used for the defect location, plus a non conventional approach by applying a clocked power supply sequence to the circuit. A comparison is done between the different signatures and we show that dynamic power supply emulation can bring some additional information on the defect location which is not detected with the conventional static/dynamic approach.