An automated approach for locating multiple faulty LUTs in an FPGA
Abstract This paper presents a new approach for locating any multiple faulty look-up tables (LUTs) in a field programmable gate array (FPGA). This is a high resolution approach, in which the position of each of the multiple faulty LUTs is precisely determined without any fault masking. To identify the fault location, a new technique is used by correlating the position of each of the LUT to a particular select signal of a dedicated wide input multiplexer along with a control logic. This off-line built in self test (BIST) method can be invoked automatically whenever the testing is required to be carried out. The total testing time of the LUTs under test for different configurations have been reduced to a greater extend as the reconfiguration is performed at the physical circuit description level rather than at the high level abstract. It is shown that average reconfiguration duration is approximately 30 s for Spartan series FPGAs. Also, it is shown that the total testing time required to test 9312 LUTs exhaustively per configuration is 2 min and 4 s. Thus, it is possible to exhaustively test LUTs with multiple configurations in a shorter span of time. Moreover, this approach uses minimal IOBs and provides 100% logic fault coverage. This approach is tested on Xilinx Spartan family FPGAs, and results are provided.