Modelling challenges in sub-100 nm gate stack MOSFETs
The aim of this work is to present a two-dimensional analysis for different gate stack dielectric structured n-MOSFETs with carrier quantization effects. The model is developed using Green's function for solving Poisson's equation, without implying the extensive effort required for a fully self-consistent solution of the Schrodinger and Poisson equations. Explicit results for potential distribution, threshold voltage and drain current, with different structural and bias parameters, have been presented, typical in the operation of modern devices. The model includes short channel, drain bias, and junction curvature effects. Based on extensive simulation and developed formulation, it is found that the conventional concept of a scaled transformation method for gate stack structures to replace silicon-dioxide (SiO2) dielectric thickness with a thicker high dielectric does not predict the same characteristics. It has also been shown that using double-layer gate stack structures with low-k dielectric as the spacer material can well confine the electric fields within the channel, thereby enhancing gate controllability on the channel charge. Comparison of the results thus obtained is done with simulated results to justify the analysis.