Design of Adaptive Variable-Frequency Embedded Microprocessor
Variable-frequency is a usual technique for low power design. An embedded microprocessor core, which is compatible with MIPS32-4Kec and named as SRISC-I, is presented. A phase-locked-loop (PLL) controlled by software is embedded in SRISC-I to vary the core frequency. Besides work mode, SRISC-I can stay in idle mode or sleep mode by shutting down system clock and/or PLL to lower the power. The simulation results show that SRISC-I can work at a maximal frequency of 250MHz in 0.18um CMOS process, and its working frequency can scale between 10MHz and 250MHz adaptively in 10MHz step by configuring the PLL parameter. The power consumption for different frequency when running Dhrystone2.1 is also given, which is 82.466mWatt at 250MHz and only 28uWatt in sleep mode.