Source engineering on ruggedness and RF performance of n-channel RFLDMOS
Abstract The state-of-art n-channel RFLDMOS (Radio Frequency Lateral Double-diffusion Metal Oxide Semiconductor) FETs with different source engineering have been fabricated using 0.18 μm BCD (Bipolar/COMS/DMOS) process. The ruggedness and RF performance of RFLDMOS have been studied with TLP (Transmission Line Pulse) test, VSWR (Voltage Stop Wave Ratio) test, and source/load-pull test. It was found that PBL (P+ buried layer) source engineering could improve its ruggedness remarkably. The mechanism of this improvement has been studied by introducing equivalent parasitic circuit. The dominant factor is the resistor RB which delays turn-on characteristic of parasitic NPN in equivalent circuit. And the computational model of RB is proposed. Furthermore, the optimal performance of RFLDMOS has also been discussed.