Characterization and improvement of a YBCO multilayer film process for HTS circuit applications
We have developed a 2" multilayer HTS integrated circuit process which contains up to three superconducting YBCO layers, epitaxial dielectric (SrTiO/sub 3/ or SrTiO/sub 3/+Sr/sub 2/AlTaO/sub 6/ combination), Ag wiring, an integrated resistor and non-epitaxial Si/sub x/N/sub y/ dielectric. We have incorporated the use of n-factorial and Taguchi designed experiments to develop and optimize various aspects of this process. This article highlights the designed experiments which addressed fabrication issues for HTS superconducting crossovers, dielectric integrity, and HTS/Ag metal contact resistance.