Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2 films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current density Jc was set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.