Design of CMOS logic gates with enhanced robustness against aging degradation
The continuous scaling in transistor dimensions for improving speed and functionality turns device reliability one of the major concerns for nanometer design. This work aims to evaluate the effects of three aging mechanisms acting on the CMOS logic gate reliability for different styles and topologies. Electrical simulations associated to analytical and Spice wearout models are used to compute the circuit degradation. Simulation results reveal that the restructuring of intra-cell transistor networks avoids up to 17% of delay increase due to aging, while the decomposition of single stage circuits into multi-stage topologies tends to produce worse results in terms of performance aging depreciation.