photonic network on chip
67872709
Optics in Computing: From Photonic Network on Chip to Chip to Chip Interconnects and Disintegrated Architectures
Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network on Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip to chip (C2C) computing architectures rather than on chip layouts toward reaping their benefits while avoiding technology limitations on the way to manycore set ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single hop low latency setup for even more than four interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically enabled eight socket boards can be combined via a 256 x 256 Hipolaos Optical Packet Switch into a powerful 256 node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency critical rack scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a mean to increase the number of synergized high performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off die ultrafast optical cache memory chiplets.
Journal of Lightwave Technology
Theonitsa Alexoudi Nikolaos Terzenidis Stelios Pitris Miltiadis Moralis-Pegios Pavlos Maniotis Christos Vagionas Charoula Mitsolidou George Mourgias-Alexandris George T Kanellos Amalia N Miliou Konstantinos Vyrsokinos Nikos Pleros
155109458
A Group Based Laser Power Supply Scheme for Photonic Network on Chip
It is expected that the future multicore systems will significantly benefit from photonic interconnect technology because of its large bandwidth. However, the static power consumed by laser sources accounts for a large proportion of the overall power budget; thus, it has a negative impact on the performance of future photonic network on chip. In this paper, GLaP, a group based static laser power supply approach is proposed. The communication backbone is investigated based on single write multiread crossbar. Generic laser power delivery and allocation architectures are proposed to match the bandwidths with the requirements of different nodes. The laser sources are shared across the network which enables significant reduction in laser power consumption. The evaluation results show that the laser power can be significantly saved compared with traditional laser supply schemes.
IEEE Photonics Journal
Xiaolu Wang Huaxi Gu Yintang Yang Kun Wang
52985273
Scheduling computation and communication on a software defined photonic Network on Chip architecture for high performance real time systems
Abstract This paper presents a novel scheduling approach that efficiently schedules the computational and the communicational resources of a Software Defined Photonic Network on Chip (SD PNoC) Architecture designed for high performance real time systems. The proposed scheduling approach extends the conventional cyclic executive scheduling algorithm from the one that schedules solely the computational resources into a general one that schedules both the computational and the communicational resources together in a synchronized manner. The proposed SD PNoC architecture employs Software Defined Network (SDN) approach by using application specific conflict free and contention free communication patterns to solve the routing and wavelength assignment (RWA) problem exists in photonic networks. The implementations of the collective communication primitives such as broadcast and all to broadcast are also presented to demonstrate the system as a whole.
J. Syst. Archit.
Huseyin Temucin Kayhan M Imre
125098913
Six port optical switch for cluster mesh photonic network on chip
Abstract Photonic network on chip for high performance multi core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non blocking six port optical switch for cluster mesh photonic network on chip. The architecture is constructed by substituting three optical switching units of typical Spanke Benes network to optical waveguide crossings. Compared with Spanke Benes network, the number of optical switching units is reduced by 20% while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal to noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.
Hao Jia Ting Zhou Yunchou Zhao Yuhao Xia Jincheng Dai Lei Zhang Jianfeng Ding Xin Fu Lin Yang
52960692
BiGNoC: Accelerating Big Data Computing with Application Specific Photonic Network on Chip Architectures
In the era of big data, high performance data analytics applications are frequently executed on large scale cluster architectures to accomplish massive data parallel computations. Often, these applications involve iterative machine learning algorithms to extract information and make predictions from large data sets. Multicast data dissemination is one of the major performance bottlenecks for such data analytics applications in cluster computing, as terabytes of data need to be distributed frequently from a single data source to hundreds of computing nodes. To overcome this bottleneck for big data applications, we propose <italic>BiGNoC</italic> a manycore chip platform with a novel application specific photonic network on chip (PNoC) fabric. <italic>BiGNoC</italic> is designed for big data computing and exploits multicasting in photonic waveguides. For high performance data analytics applications, <italic> BiGNoC</italic> improves throughput by up to <inline formula><tex math notation="LaTeX"{9.9}\times$/tex math> <alternatives><inline graphic xlink:href="chittamuru ieq1 2833876.gif"/alternatives>/inline formula> while reducing latency by up to 88 percent and energy per bit by up to 98 percent over two state of the art PNoC architectures as well as a broadcast optimized electrical mesh NoC architecture, and a traditional electrical mesh NoC architecture.
IEEE Transactions on Parallel and Distributed Systems
Sai Vineel Reddy Chittamuru Dharanidhar Dang Sudeep Pasricha Rabi N Mahapatra
53086562
A Single Wavelength Photonic Network on Chip Design Based on Optical Orthogonal Codes
Silicon photonic based interconnects are becoming a very promising solution for multi core system on chip (SoC) platforms. In this paper, a novel photonic network on chip (PNoC) design for multi core SoC is proposed, based on optical code division multiple access (OCDMA) using a single on/off chip laser diode (LD) The proposed design offers a much lower optical power consumption, and consequently, cost, as compared to the state of the art PNoC designs, in which multiple on/off chip LDs are usually utilized. The core to core communication over the proposed PNoC is simulated, with the bit error rate (BER) as the performance metric of interest. Simulation results confirm the analytical BER expressions and show that an error free core to core transmission is achieved.
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Mohamed Shehata Mohamed Sameh Said Hassan Mostafa
27954484
8 x 8 x 40 Gbps fully integrated silicon photonic network on chip
We demonstrate a fully integrated photonic network on chip circuit with wavelength division multiplexing transceivers on silicon. The total transmission capacity is up to 8x8x40 Gbps for intra and inter chip interconnections.
Chong Zhang Shangjian Zhang Jonathan Peters John E Bowers
5101353
Mode Division Multiplexing for Silicon Photonic Network on Chip
Optical interconnect is a potential solution to attain the large bandwidth on chip communications needed in high performance computers in a low power and low cost manner. Mode division multiplexing (MDM) is an emerging technology that scales the capacity of a single wavelength carrier by the number of modes in a multimode waveguide, and is attractive as a cost effective means for high bandwidth density on chip communications. Advanced modulation formats with high spectral efficiency in MDM networks can further improve the data rates of the optical link. Here, we demonstrate an intra chip MDM communications link employing advanced modulation formats with two waveguide modes. We demonstrate a compact single wavelength carrier link that is expected to support 2 x 100 Gb/s mode multiplexed capacity. The network comprised integrated microring modulators at the transmitter, mode multiplexers, multimode waveguide interconnect, mode demultiplexers, and integrated germanium on silicon photodetectors. Each of the mode channels achieves 100 Gb/s line rate with 84 Gb/s net payload data rate at 7% overhead for hard decision forward error correction (HD FEC) in the OFDM/16 QAM signal transmission.
Journal of Lightwave Technology
Xinru Wu Chaoran Huang Ke Xu Chester Shu Hon Ki Tsang
125455595
Method to optimize optical switch topology for photonic network on chip
Abstract In this paper, we propose a method to optimize the optical switch by substituting optical waveguide crossings for optical switching units and an optimizing algorithm to complete the optimization automatically. The functionality of the optical switch remains constant under optimization. With this method, we simplify the topology of optical switch, which means the insertion loss and power consumption of the whole optical switch can be effectively minimized. Simulation result shows that the number of switching units of the optical switch based on Spanke Benes can be reduced by 16.7% 20% 20% 19% and 17.9% for the scale from 4 x 4 to 8 x 8 respectively. As a proof of concept, the experimental demonstration of an optimized six port optical switch based on Spanke Benes structure by means of silicon photonics chip is reported.
Ting Zhou Hao Jia
2424570
Four Port Optical Switch for Fat Tree Photonic Network on Chip
We demonstrate a four port optical switch for the fat tree photonic network on chip architecture, which contains four silicon Mach Zehnder optical switch elements tuned by the plasma dispersion effect. The optical signal to noise ratio of the device is over 10.0 dB in the wavelength range from 1525 to 1565 nm. The routing functionality of the device is verified and 50 x 32 Gb/s wavelength division multiplexing data transmission for one optical link is demonstrated. The rise and fall times (10% 90% and 90% 10% of the optical switch element are both ~2 ns. The average power consumption of the device is ~56.8 mW.
Journal of Lightwave Technology
Hao Jia Yuhao Xia Libo Zhang Jianfeng Ding Xin Fu Lin Yang