micro-core
211536752
High level programming abstractions for leveraging hierarchical memories with micro core architectures
Abstract Micro core architectures combine many low memory, low power computing cores together in a single package. These are attractive for use as accelerators but due to limited on chip memory and multiple levels of memory hierarchy, the way in which programmers offload kernels needs to be carefully considered. In this paper we use Python as a vehicle for exploring the semantics and abstractions of higher level programming languages to support the offloading of computational kernels to these devices. By moving to a pass by reference model, along with leveraging memory kinds, we demonstrate the ability to easily and efficiently take advantage of multiple levels in the memory hierarchy, even ones that are not directly accessible to the micro cores. Using a machine learning benchmark, we perform experiments on both Epiphany III and MicroBlaze based micro cores, demonstrating the ability to compute with data sets of arbitrarily large size. To provide context of our results, we explore the performance and power efficiency of these technologies, demonstrating that whilst these two micro core technologies are competitive within their own embedded class of hardware, there is still a way to go to reach HPC class GPUs.
J. Parallel Distributed Comput.
Maurice Jamieson Nick Brown
222247493
Micro core decompression combined with intralesional zoledronic acid as a treatment of osteonecrosis of femoral head: a novel technique
Background: Avascular necrosis (AVN)/osteonecrosis of the femoral head is a debilitating condition affecting the hip joint and is one of the most common causes of total hip replacement. The available treatments include pharmacological and surgical options with total hip arthroplasty (THA) being the mainstay of treatment. This present study is a novel technique of combining micro core decompression with intra lesional bisphosphonate as a treatment for osteonecrosis of the hip. Methods: A prospective study of 19 hips was done. There were 11 males and 4 females ranging 42 63 years. Four hips were stage I, ten hips were stage IIA, three hips were stage IIb and two hips were stage III. 16 hips (40% had stage IIb and 24 hips (60% had stage III ONFH. The minimum period of follow up was 24 months. All patients were assessed according to the Harris hip score. The operative procedure includes decompressing the avascular area with drilling then injecting the zoledronic acid locally. Results: The mean preoperative modified Harris hip score in stage I (n=4) stage IIa (n=10) stage IIb (n=3) and stage III (n=2) were 81.9, 72.7, 68.8 and 59.2 respectively. The mean postoperative modified Harris hip score at two years in stage I, stage IIa, stage IIb and stage III were 97.3, 91.1, 88.4 and 82.5 respectively. Conclusions: We found that the use of micro core decompression with intra lesional bisphosphonate will provide higher chances towards hip preservation especially in late cases or cases with larger lesions where core decompression may not be successful.
Muhammed Ashraf Jyothis Thomas George Ibad Sha I
226290074
Benchmarking micro core architectures for detecting disasters at the edge
Leveraging real time data to detect disasters such as wildfires, extreme weather, earthquakes, tsunamis, human health emergencies, or global diseases is an important opportunity. However, much of this data is generated in the field and the volumes involved mean that it is impractical for transmission back to a central data centre for processing. Instead, edge devices are required to generate insights from sensor data streaming in, but an important question given the severe performance and power constraints that these must operate under is that of the most suitable CPU architecture. One class of device that we believe has a significant role to play here is that of micro cores, which combine many simple low power cores in a single chip. However, there are many to choose from, and an important question is which is most suited to what situation. This paper presents the Eithne framework, designed to simplify benchmarking of micro core architectures. Three benchmarks, LINPACK, DFT and FFT, have been implemented atop of this framework and we use these to explore the key characteristics and concerns of common micro core designs within the context of operating on the edge for disaster detection. The result of this work is an extensible framework that the community can use help develop and test these devices in the future.
2020 IEEE/ACM HPC for Urgent Decision Making (UrgentHPC)
Maurice Jamieson Nick Brown
221338468
Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro core architectures using ePython
Micro core architectures combine many simple, low memory, low power computing cores together in a single package. These can be used as a co processor or standalone but due to limited on chip memory and esoteric nature of the hardware, writing efficient parallel codes for these chips is challenging. In this paper we discuss our very low memory implementation of Python, ePython, supporting the rapid development of parallel Python codes for these co processors. An offload abstraction is introduced, where programmers decorate specific functions in their Python code, running under any Python interpreter on the host CPU, with the underlying technology then taking care of the low level data movement, scheduling and ePython execution on the microcore co processor. A benchmark solving Laplace's equation for diffusion via Jacobi iteration is used to explore the performance of ePython on three different micro core architectures, and introduces work around native compilation for micro cores and the performance advantages that this can provide.
Maurice Jamieson Nick Brown Sihang Liu
213600311
Eithne: A framework for benchmarking micro core accelerators
Maurice Jamieson Nicholas Brown
209021938
Leveraging hierarchical memories for micro core architectures
Nicholas Brown Maurice Jamieson
69993097
ePython a tiny Python implementation for micro core architectures
Nicholas Brown
114275417
Fabricating micro core by EDM with multi station narrow slit electrode
A method of fabricating micro core on hard materials by electro discharge machining (EDM) with multi station narrow slit electrode was proposed. Instead of changing electrodes traditionally, the method of transforming the electrode station was applied, and the positioning error could be avoided. With the narrow slit structure of the electrode, the discharge debris could be excreted easily and the high depth to width ratio of micro core could be fabricated. NAK80 was selected as the core material, while copper tungsten alloy (70 W) as the electrode material to carry out the fundamental experiments in which the relationship between the number of electrode stations and forming accuracy of micro core was researched. The results demonstrate that using four electrode stations, the dimensional precision is within 3 mm, the root radius is within 10 mm, and the surface roughness is Ra 0.198 mm, and all this can be satisfied with the demand of molding for microfluidic chip. On the basis of the fundamental experiment results, a variable section micro core was manufactured. The machining results show that the forming accuracy of the convex becomes worse with the decrease of the forming convex height. This phenomenon was analyzed in EDM principle and the error reflection mechanism.
M C Song Yi Liu Wei min Li
235615467
Micro Core decompression combined with intralesional zoledronic acid as a treatment of osteonecrosis of femoral head: A novel technique
Background: Avascular Necrosis Osteonecrosis of the femoral head is a debilitating condition affecting the hip joint and is one of the most common causes of total hip replacement. The available treatments include pharmacological and surgical options with Total hip arthroplasty (THA) being the mainstay of treatment. We here is studying a novel technique of combining micro core decompression with intra lesional bisphosphonate as a treatment for osteonecrosis of the hip. Materials and Methods: A prospective study of 19 hips was done. There were 11 males and 4 females ranging 42 63 years. Four hips were stage I, ten hips were stage IIA, three hips were stage IIb and two hips were stage III. 16 hips (40% had stage IIb and 24 hips (60% had stage III ONFH. The minimum period of follow up was 24 months. All patients were assessed according to the Harris Hip Score (HHS) The operative procedure include decompressing the avascular area with drilling then injecting the zoledronic acid locally. Results: The mean preoperative modified Harris Hip Score in stage I (n=4) stage IIa (n=10) stage IIb (n=3) and Stage III (n=2) were 81.9, 72.7, 68.8 and 59.2 respectively. The mean postoperative modified Harris Hip Score at two years in stage I, stage IIa, stage IIb and Stage III were 97.3, 91.1, 88.4 and 82.5 respectively. Conclusion: We found that the use of micro core decompression with intra lesional bisphosphonate will provide higher chances towards hip preservation especially in late cases or cases with larger lesions where core decompression may not be successful.
Muhammed Ashraf Jyothis Thomas George I Ibad Sha
231786394
Compact native code generation for dynamic languages on micro core architectures
Micro core architectures combine many simple, low memory, low power consuming CPU cores onto a single chip. Potentially providing significant performance and low power consumption, this technology is not only of great interest in embedded, edge, and IoT uses, but also potentially as accelerators for data center workloads. Due to the restricted nature of such CPUs, these architectures have traditionally been challenging to program, not least due to the very constrained amounts of memory (often around 32KB) and idiosyncrasies of the technology. However, more recently, dynamic languages such as Python have been ported to a number of micro cores, but these are often delivered as interpreters which have an associated performance limitation. Targeting the four objectives of performance, unlimited code size, portability between architectures, and maintaining the programmer productivity benefits of dynamic languages, the limited memory available means that classic techniques employed by dynamic language compilers, such as just in time (JIT) are simply not feasible. In this paper we describe the construction of a compilation approach for dynamic languages on micro core architectures which aims to meet these four objectives, and use Python as a vehicle for exploring the application of this in replacing the existing micro core interpreter. Our experiments focus on the metrics of performance, architecture portability, minimum memory size, and programmer productivity, comparing our approach against that of writing native C code. The outcome of this work is the identification of a series of techniques that are not only suitable for compiling Python code, but also applicable to a wide variety of dynamic languages on micro cores.
CC
Maurice Jamieson Nick Brown