chiplet
218613741
Centaur: A Chiplet based, Hybrid Sparse Dense Accelerator for Personalized Recommendations
Personalized recommendations are the backbone machine learning (ML) algorithm that powers several important application domains (e.g. ads, e commerce, etc) serviced from cloud datacenters. Sparse embedding layers are a crucial building block in designing recommendations yet little attention has been paid in properly accelerating this important ML algorithm. This paper first provides a detailed workload characterization on personalized recommendations and identifies two significant performance limiters: memory intensive embedding layers and compute intensive multi layer perceptron (MLP) layers. We then present Centaur, a chiplet based hybrid sparse dense accelerator that addresses both the memory throughput challenges of embedding layers and the compute limitations of MLP layers. We implement and demonstrate our proposal on an Intel HARPv2, a package integrated \mathrm{C}\mathrm{P}\mathrm{U}$FPGA device, which shows a 1.7 17.2\times$ performance speedup and $1.7 19.5\times \mathrm{e}\mathrm{n}\mathrm{e}\mathrm{r}\mathrm{g}\mathrm{y} efficiency improvement than conventional approaches.
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
Ranggi Hwang Taehun Kim Youngeun Kwon Minsoo Rhu
215800319
2.2 AMD Chiplet Architecture for High Performance Server and Desktop Products
AMO's "Rome" and "Matisse" are second generation AMD Infinity Fabric based SoCs using 3 unique hybrid process technology chiplets to achieve leading performance, performance/ and performance/W, targeting server and client markets, respectively (Fig. 2.2.1) The chiplet architecture enables leading edge 7nm [1] CPUs for multiple markets, while retaining backward compatibility to complex 10 and memory subsystems in a scalable design with high reuse for improved time to market. A key benefit is the heterogeneous technology deployed between the CPUs and the 10/mixed signaIP. It is well known that shrink factors in advanced nodes are much lower for analog circuitry than for digital logic and SRAM. By keeping the memory interfaces and SerOes in mature 12nm technology, costs are mitigated since those circuits see a very small shrink factor to 7nm and very little performance or power gain from advanced nodes. A low cost 12nm 10 die (IOD) with the high yielding 8 "Zen2" core, 74mm2 7nm CPU compute die (CCD) combine to provide very cost effective performance.
2020 IEEE International Solid State Circuits Conference (ISSCC)
Samuel Naffziger Kevin M Lepak Milam Paraschou Mahesh Subramony
214197690
A 7 nm 4 GHz Arm1 Core Based CoWoS1 Chiplet Design for High Performance Computing
We present a dual chiplet interposer based system in package (SiP) octo core processor using Chip on Wafer on Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7 nm CMOS with 15 metal layers and has four Arm Cortex A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2 mm flop to flop distance is distributed throughout the chiplet for high speed on die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low voltage In Package INterCONnect (LIPINCON) clock forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3 V transmitter swing without receiver termination to achieve 0.56 pJ/bit energy efficiency and 1.6 Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on die data bus, and inter chiplet link. The built in LIPINCON eye scan feature validates inter chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.
IEEE Journal of Solid State Circuits
Mu-Shan Lin Tze-Chiang Huang Chien-Chun Tsai King Ho Tam Kenny Cheng-Hsiang Hsieh Ching-Fang Chen Wen-Hung Huang Chi-Wei Hu Yu-Chi Chen Sandeep Kumar Goel Chin-Ming Fu Stefan Rusu Chao-Chieh Li Sheng-Yao Yang Mei Wong Shu-Chun Yang Frank Lee
198335054
CAMON: Low Cost Silicon Photonic Chiplet for Manycore Processors
While many new applications prefer manycore processor with a large number of cores, the exploding communications among multiple cores, caches, and off chip memories is posing a fundamental challenge on manycore designs. Silicon photonics based interconnection network promises high bandwidth, low latency, and high energy efficiency, and can potentially meet the communication requirements of manycore processors. In this paper, we propose CAMON, a small low cost silicon photonic chiplet integrated into the manycore processor package. CAMON chiplet can effectively alleviate the communication bottlenecks of manycore processors and improve the energy efficiency of data movement, especially for large scale systems. We develop a distributed arbitration system, a low power low latency optical interface, and an off chip laser preactivation mechanism for CAMON. The experimental results show that compared with the electrical network, CAMON can improve the full system performance per energy by <inline formula> <tex math notation="LaTeX"$4.6\times /tex math>/inline formula> speedup the manycore processor by <inline formula> <tex math notation="LaTeX"$2.7\times /tex math>/inline formula> and save the area of the processor die by 3% in a 512 core system.
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Zhehui Wang Zhifei Wang Jiang Xu Yi-Shing Chang Jun Feng Xuanqi Chen Shixi Chen Jiaxu Zhang
219548434
Special Session: Test Challenges in a Chiplet Marketplace
Chiplet based designs enable the heterogeneous integration of die from multiple process nodes into a single packaged product. High bandwidth memory is a well known high volume chiplet based product. Today, most chiplet based logic products are single vendor products built with proprietary die to die (D2D) interfaces between the chiplets in a package. Industry and academia have developed standards and methods to address the test challenges expected with chiplet based products. These efforts have focused on improving die yield and test access structures. The Open Compute Project's Open Domain Specific Architecture (ODSA) is a new effort that aims to define an open physical and logical D2D interface and create a marketplace of chiplets. With an open interface, product developers can integrate best in class chiplets from multiple vendors. An open D2D interface offers both new opportunities and challenges in testing multi chiplet products. The opportunity is in leveraging economies of scale. The challenge is in enabling greater interoperability between test structures in different chiplets and across vendors. This paper reviews recent developments in chiplet test, especially leveraging work on HBM and discusses their extension to testing products based on open D2D interfaces.
2020 IEEE 38th VLSI Test Symposium (VTS)
M Hutner Rajamani Sethuram Bapiraju Vinnakota David Armstrong A Copperhall
218776269
Chiplet Heterogeneous Integration Technology Status and Challenges
As a heterogeneous integration technology, the chiplet based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore's law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry's efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.
Tao Li Jie Hou Jinli Yan Rulin Liu Honbo Yang Zhigang Sun
214691429
Chiplet Package Co Design For 2.5D Systems Using Standard ASIC CAD Tools
Chiplet integration using 2.5D packaging is gaining popularity nowadays which enables several interesting features like heterogeneous integration and drop in design method. In the traditional die by die approach of designing a 2.5D system, each chiplet is designed independently without any knowledge of the package RDLs. In this paper, we propose a Chip Package Co Design flow for implementing 2.5D systems using existing commercial chip design tools. Our flow encompasses 2.5D aware partitioning suitable for SoC design, Chip Package Floorplanning, and post design analysis and verification of the entire 2.5D system. We also designed our own package planners to route RDL layers on top of chiplet layers. We use an ARM Cortex M0 SoC system to illustrate our flow and compare analysis results with a monolithic 2D implementation of the same system. We also compare two different 2.5D implementations of the same SoC system following the drop in approach. Alongside the traditional die by die approach, our holistic flow enables design efficiency and flexibility with accurate cross boundary parasitic extraction and design verification.
2020 25th Asia and South Pacific Design Automation Conference (ASP DAC)
M D Arafat Kabir Yarui Peng
227219809
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet Package Co Design
In recent years, 2.5D chiplet package designs have gained popularity in system integration of heterogeneous technologies. Currently, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die by die design approach does not consider any package layers during extraction and optimization, and an accurate chiplet package extraction can not be applied to heterogeneous designs without fundamental changes in standard CAD tools. In this paper, we present our Holistic and In Context chiplet package co design flows for high performance high density 2.5D systems using standard ASIC CAD tools with zero overhead on IO pipeline depth. Our flow encompasses 2.5D aware partitioning, chiplet package co planning, in context extraction, iterative optimization, and post design analysis and verification of the entire 2.5D system. We design our package planner with a routing and pin planning strategy to minimize package routing congestion and timing overhead. An ARM Cortex M0 based microcontroller system is designed as the benchmark. The performance gap to the reference 2D design reduces by 62.5% when chip package interactions are taken into account in the holistic flow. Our in context extraction achieves only 0.71% and 0.79% error on ground and coupling capacitance on a homogeneous system. Further, we implement a heterogeneous 2.5D system to demonstrate our novel in context design and optimization methodology.
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
M D Arafat Kabir Dusan Petranovic Yarui Peng
225079697
Architecture, Chip, and Package Codesign Flow for Interposer Based 2.5 D Chiplet Integration Enabling Heterogeneous IP Reuse
A new trend in system on chip (SoC) design is chiplet based IP reuse using 2.5 D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off the shelf intellectual properties (IPs) allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5 D designs. Our target design is 64 core architecture based on Reduced Instruction Set Computer (RISC) V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64 core processor into chiplets, which are enhanced with our centralized network on chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip to chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5 D design. Our design space exploration (DSE) study shows that 2.5 D integration incurs $1.29\times power and $2.19\times area overheads compared with 2 D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5 D integrated chip (IC) designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jinwoo Kim Gauthaman Murali Heechun Park Eric Qin Hyoukjun Kwon Venkata Chaitanya Krishna Chekuri Nael Mizanur Rahman Nihar Dasari Ashutosh Kumar Singh Minah Lee Hakki Mert Torun Kallol Roy Madhavan Swaminathan S Mukhopadhyay Tushar Krishna Sung Kyu Lim
215800437
2.3 A 220GOPS 96 Core Processor with 6 Chiplets 3D Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter Chiplet Interconnects and 156mW/mm2@ 82% Peak Efficiency DC DC Converters
In the context of high performance computing and big data applications, the quest for performance requires modular, scalable, energy efficient, low cost manycore systems. Partitioning the system into multiple chiplets 3D stacked onto large scale interposers organic substrate [1] 2.5D passive interposer [2] or silicon bridge [3] leads to large modular architectures and cost reductions in advanced technologies by the Known Good Die (KGD) strategy and yield management. However, these approaches lack flexible efficient long distance communications, smooth integration of heterogeneous chiplets, and easy integration of less scalable analog functions, such as power management [4] and system IOs. To tackle these issues, this paper presents an active interposer integrating: i) a Switched Capacitor Voltage Regulator (SCVR) for on chip power management; ii) flexible system interconnect topologies between all chiplets for scalable cache coherency support; iii) energy efficient 3D plugs for dense inter layer communication; iv) a memory IO controller and PHY for socket communication. The chip (Fig. 2.3.7) integrates 96 cores in 6 chiplets in 28nm FDSOI CMOS, 30 stacked in a face to face configuration using 20um pitch micro bumps (u bumps) onto a 200 mm2 active interposer with 40um pitch Through Silicon Via (TSV) middle in a 65nm technology node. Even though complex functions are integrated, active interposer yield is high thanks to the mature 65nm node and a reduced complexity (0.08transistors/um2) with 30% of interposer area devoted to a SCVR variability tolerant capacitors scheme.
2020 IEEE International Solid State Circuits Conference (ISSCC)
Pascal Vivet Eric Guthmuller Yvain Thonnart Gael Pillonnet Guillaume Moritz Ivan Miro-Panades Cesar Fuguet Tortolero Jean Durupt Christian Bernard Didier Varreau Julian J H Pontes Sebastien Thuries David Coriat Michel Harrand Denis Dutoit Didier Lattard Lucile Arnaud Jean Charbonnier Perceval Coudrain Arnaud Garnier Frederic Berger Alain Gueugnot Alain Greiner Quentin L Meunier Alexis Farcy Alexandre Arriordaz Severine Cheramy Fabien Clermidy