CMOS analog neural network sigma delta
14474926
VLSI delta sigma cellular neural network for analog random vector generation
We present a cellular neural network architecture for parallel analog random vector generation, including experimental results from an analog VLSI prototype with 64 channels. Nearest neighbor coupling between cells produces parallel channels of uniformly distributed random analog values, with statistics that are truly uncorrelated across channels and over time. The cell for each random channel emulates an integrating nonlinearity essentially implementing a delta sigma modulator, and measures 100 /spl mu/m/spl times/120 /spl mu/m in 2 /spl mu/m CMOS technology. Applications include analog encryption and secure communications, analog built in self test, stochastic neural networks, and simulated annealing optimization and learning.
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
Gert Cauwenberghs
49320286
An Analog Neural Network Computing Engine Using CMOS Compatible Charge Trap Transistor (CTT)
An analog neural network computing engine based on CMOS compatible charge trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog digital interfaces. By implementing the sequential analog fabric, the engine's mixed signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof of concept 784 by 784 CTT computing engine is implemented using TSMC 28 nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8 bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem classifying handwritten digits on MNIST database and obtained a performance comparable to state of the art fully connected neural networks using 8 bit fixed point resolution.
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Yuan Du L Du Xuefeng Gu Jieqiong Du X Shawn Wang Boyu Hu Mingzhe Jiang Xiaoliang Chen Subramanian S Iyer Mau-Chung Frank Chang
198931820
Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma delta quantization
Artificial Neural Networks (ANNs) show great performance in several data analysis tasks including visual and auditory applications. However, direct implementation of these algorithms without considering the sparsity of data requires high processing power, consume vast amounts of energy and suffer from scalability issues. Inspired by biology, one of the methods which can reduce power consumption and allow scalability in the implementation of neural networks is asynchronous processing and communication by means of action potentials, so called spikes. In this work, we use the well known sigma delta quantization method and introduce an easy and straightforward solution to convert an Artificial Neural Network to a Spiking Neural Network which can be implemented asynchronously in a neuromorphic platform. Briefly, we used asynchronous spikes to communicate the quantized output activations of the neurons. Despite the fact that our proposed mechanism is simple and applicable to a wide range of different ANNs, it outperforms the state of the art implementations from the accuracy and energy consumption point of view. All source code for this project is available upon request for the academic purpose1.
2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Amirreza Yousefzadeh Sahar Hosseini Priscila C Holanda Sam Leroux Thilo Werner Teresa Serrano-Gotarredona Bernabe Linares-Barranco B Dhoedt Pieter Simoens
3224674
Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites
New satellites generations have regenerative payload. Received signals are demodulated in order to be processed, before being modulated again and amplified on board. For correcting non linearities due to high power amplifier (HPA) operating near saturation, a predistortion system based on neural networks (NNs) was developed. For size, consumption and bandwidth purposes, the multi layer perceptron (MLP) type NNs were implemented in a 0.6 mum CMOS ASIC. This paper presents the linearization ability of the analog integrated NN to correct the AM/AM distortion due to the HPA for changing simulation conditions (temperature drifts, ageing variations)
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
Laurent Gatet Helene Tap-Beteille Daniel Roviras Francis Gizard
50772576
An Analog to Digital Converter Using Delta Sigma Modulator Network
An analog to digital converter (ADC) using a deltasigma modulator network is proposed, and signal level simulations are carried out as a proof of concept. The present architecture is based on a feedforward artificial neural network, where an N bit digital output is generated through N channels containing one comparator per channel. A moving average of delta sigma modulator outputs is taken to obtain a multi level feedforward signal. Simulation results show proper operations of present ADCs consisting of either first order or second order delta sigma modulators. The effective number of bits (ENOB) increases as the number of channels increases. Comparison with conventional architectures is also discussed.
2018 IEEE 48th International Symposium on Multiple Valued Logic (ISMVL)
Takao Waho
34276649
Design of sigma delta analog to digital converters implemented in 65nm digital CMOS process for LoRa
In the evolving field of Internet of Things (IoT) wireless sensor networks serve as the backbone for data acquisition, processing, and transmission. Deployed sensor nodes are expected to communicate with one another, or with a base station. A new modulating scheme known as LoRa allows communication over long ranges but still consumes low power. One block that is needed to realize this is the analog to digital converter (ADC) This paper designed a Sigma Delta ADC due to its high resolution and relatively low power consumption among other ADCs. Four topologies were implemented to survey which one will give the best performance. Finally, the first order continuous time sigma delta ADC was found to be the best topology. It can accept an input amplitude range of 350uV to 500mV and frequency range of up to 39MHz. Lastly, the measured least significant bit is 0.0708mV with a low power of 1.44mW.
TENCON 2017 2017 IEEE Region 10 Conference
Doreen Dellosa Mel-Jie Bentz del Mundo Gelyn Manzanares Edrian Daniel Marqueses Edzhel Rose Valverde Louis Alarcon Chris Vincent Jagunap Densing Rico Jossel Mindoro Maestro Marc Driz Rosales Maria Theresa G de Leon
22222578
Measurement Range Increase of a Phase Shift Laser Rangefinder Using a CMOS Analog Neural Network
An analog neural network (NN) was designed, implemented in 0.35 mum complementary metal oxide semiconductor technology, and tested to increase the distance measurement interval of a phase shift laser rangefinder and to classify different types of surfaces for varying distances and incidence angles. This paper focuses on the ability of the NN to remove the indecision on the distance value deduced from the phase shift measurement. The NN architecture is a multilayer perceptron (MLP) with two inputs, three processing neurons in the hidden layer, and one output neuron. The amplified and filtered photoelectric signal provided by the rangefinder is set at one input. The NN is trained so that its output voltage is proportional to the distance for easy evaluation. By combining both measurements coming from the rangefinder and the NN, it is possible to obtain a resolution of 50 mum on a distance interval [0.5 m; 3.2 m] whereas the rangefinder measurement range width is limited to 0.9 m. This paper presents the complete system, concentrating more on the training phase of the implemented NN and on the experimental results.
IEEE Transactions on Instrumentation and Measurement
Laurent Gatet Helene Tap-Beteille
52143225
Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits
The on chip implementation of learning algorithms would speed up the training of neural networks in crossbar arrays. The circuit level design and implementation of a back propagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we propose analog backpropagation learning circuits for various memristive learning architectures, such as deep neural network, binary neural network, multiple neural network, hierarchical temporal memory, and long short term memory. The circuit design and verification are done using TSMC 180 nm CMOS process models and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character, and Yale face image databases.
IEEE Transactions on Circuits and Systems I: Regular Papers
Olga Krestinskaya Khaled Nabil Salama A P James
3210932
Modular 128 Channel \Delta$ \Delta \Sigma$ Analog Front End Architecture Using Spectrum Equalization Scheme for 1024 Channel 3 D Neural Recording Microsystems
We report an area and energy efficient integrated circuit architecture of a 128 channel <inline formula> <tex math notation="LaTeX"\Delta$ /tex math>/inline formula> modulated <inline formula> <tex math notation="LaTeX"\Delta \Sigma$ /tex math>/inline formula> analog front end <inline formula> <tex math notation="LaTeX"\Delta$ /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"\Delta \Sigma$ /tex math>/inline formula> AFE) for 1024 channel 3 D massive parallel neural recording microsystems. Our platform has adopted a modularity of 128 channels and consists of eight multi shank neural probes connected to individual AFEs through interposers in a small form factor. In order to reduce both area and energy consumption in the recording circuits, we implemented a spectrum equalization scheme to take advantage of the inherent spectral characteristics of neural signals, where most of the energy is confined in low frequencies and follows a ~1/f curve in the spectrum. This allows us to implement the AFE with a relaxed dynamic range by ~30 dB, thereby contributing to the significant reduction of both energy and area without sacrificing signal integrity. The <inline formula> <tex math notation="LaTeX"\Delta$ /tex math>/inline formula> <inline formula> <tex math notation="LaTeX"\Delta \Sigma$ /tex math>/inline formula> AFE was fabricated using 0.18 <inline formula> <tex math notation="LaTeX"\mu \text{m} /tex math>/inline formula> CMOS processes. The single channel AFE consumes 3.05 <inline formula> <tex math notation="LaTeX"\mu \text{W} /tex math>/inline formula> from 0.5 and 1.0 V supplies in an area of 0.05 mm<sup>2</sup> with 63.8 dB signal to noise and distortion ratio, 3.02 noise efficiency factor (NEF) and 4.56 NEF<sup>2</sup>V<sub>DD</sub> We also have achieved an energy area product, a figure of merit most critical for massive parallel neural recording systems, of 6.34 fJ/<inline formula> <tex math notation="LaTeX"\text{C}\cdot \text{s}\cdot$ /tex math>/inline formula>mm<sup>2</sup>
IEEE Journal of Solid State Circuits
Sung-Yun Park Jihyun Cho Kyounghwan Na Euisik Yoon
53085648
A 70.8 dB 0.0045 mm2 Low power Continuous Time Incremental Delta Sigma Modulator for Multi Site Neural Recording Interfaces
The implementation of implantable multi site neural recording systems is a very challenging task for which area efficient low power pre amplifiers and analog to digital converters (ADCs) are needed. For such applications, the design and implementation of an area and power optimized continuous time incremental Delta Sigma ADC are presented in this paper. The second order continuous time modulator features an active RC integrator based loop filter of type cascade of integrators with distributed feedback with area optimized passive components. The ADC is implemented in a 0.18 mm CMOS process and achieves a signal to noise and distortion ratio of 70.8 dB in a bandwidth of 10 kHz. It occupies an area of 0.0045 mm2 and consumes a power of 16.6 mW whereby the Schreier figure of merit results in 165.4 dB.
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Boyu Shui Matthias Keller Matthias Kuhl Yiannos Manoli