head in pillow
135936541
Effects of Package Warpage on Head in Pillow Defect
Head in pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50 mm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments. [doi:10.2320/matertrans.MI201404]
Zhenyu Zhao Chuan Chen Changyoung Park Yuming Wang Li-Zhi Liu Guisheng Zou Jian Cai Qian Wang
6963807
Characterization of after reflow misalignment on Head in Pillow defect in BGA assembly
Head in Pillow (HiP) defect is a common issue in the Ball Grid Array (BGA) assembly. The defect is caused by several factors, individually or jointly, which includes warpage, misalignment, oxidation of the BGA ball, solder paste oxidation barrier capability, ect. The influence of before reflow misalignment on HiP ratio(%HiP) has been studied. However, before reflow misalignment can't describe HiP defect accurately when other conditions changed. This paper focused on the influence of after reflow misalignment on HiP ratio. Meanwhile, the influence of several factors like solder paste oxidation barrier capability, reflow time, weight of package(PKG) on after reflow misalignment had also been investigated. Three kinds of reflow profiles were designed. Different oxidation barrier capability pastes were obtained with different soak times; and different reflow profiles were adjusted by setting different reflow time and soak time. In the experiment, all samples had the same before reflow misalignment. Results showed that the HiP ratio could be predicted by comparing the after reflow misalignment with the same solder paste oxidation barrier capability. There would be no or very low risk of HiP defect when the after reflow misalignment was small. Solder paste oxidation barrier capability is a key factor that impact the after reflow misalignment; low capability would cause the after reflow misalignment to be much larger than that before reflow; and %HiP increased rapidly with the increase of after reflow misalignment. That is, when increasing the solder paste oxidation barrier capability, the %HiP will be more and more insensitive to the change of after reflow misalignment. With the increase of solder paste oxidation barrier capability and reflow time, the after reflow misalignment will decrease; while it will increase with the increase of package (PKG) weight.
2014 15th International Conference on Electronic Packaging Technology
Chuan Chen Jian Cai Qian Ying Wang Yuming Wang Guisheng Zou Zhengyu Zhao Changyoung Park
20394826
Hidden Head In Pillow soldering failures
One of the upcoming reliability issues which is related to the lead free solder introduction, are the head in pillow solderability problems, mainly for BGA packages. These problems are due to excessive package warpage at reflow temperature. Both convex and concave warpage at reflow temperature can lead to the head in pillow problem where the solder paste and solder ball are in mechanical contact but not forming one uniform joint. With the thermo Moire profile measurements, this paper explains for two flex BGA packages the head in pillow. Both local and global height differences higher than 100 mm have been measured at solder reflow temperature. This can be sufficient to have no contact between the molten solder ball and solder paste. Finally, the impact of package drying is measured.
2014 15th International Conference on Thermal, Mechanical and Mulit Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)
Bart Vandevelde Geert Willems Bart Allaert
137948429
Testing and prevention of head in pillow
Head in pillow (HIP) is ailing the electronic industry when assembling BGAs or CSPs onto PCBs. It is caused by warpage of components or boards at reflow process, and is aggravated by oxidation. Methods for assessing the potential for occurrence of HIP are highly desired by the industry. Besides using BGA rework station followed by tedious dye and pry treatment, two other simpler methods are introduced in this work, Tiny Dot Paste method and Ball Onto Paste method. Tiny Dot Paste method stressed on the assessment of oxidation barrier capability of solder paste, while Ball Onto Paste method assesses combined capability of oxidation resistance and excessive fluxing capacity. Both methods are quick, easy, and close simulation, with the latter being better in real process simulation. Prevention of HIP can be accomplished by (1) designing packages without warpage, (2) printing more paste, (3) dipping solder paste or flux, (4) using inert reflow atmosphere, (5) reducing reflow temperature, (6) placing heat shield on BGA or CSP, (7) avoiding using water soluble solder paste for BGA bumped with no clean process, (8) using solder bumps or solder powder with oxidation resistant alloy, (9) using fluxes with high oxidation barrier capability and high fluxing capacity. Among all options listed above, using solder paste with high oxidation barrier capability and high fluxing capacity is considered the most easily implemented approaches.
ECTC 2010
Yan Liu Mauro Fiacco Ning-Cheng Lee
222264056
Influence of Salt Residues on BGA Head in Pillow (Hip)
The oxide layers are known as wetting inhibitors in component and PCB metallizations. The oxide acts as barrier that prevent the tin diffusion from happening. Besides, in corrosion studies, the role of salt residues with Cl ionon some metals is known as being promoters of oxidation or corrosion. On the other hand, most of corrosion studies with tin metallization are focused mainly on the corrosion resistance of tin alloys, but little has been done respecting to the influence of salts on tin metallization wetting. In this paper, a series of experiments was carried over to know the influence of specifically NaCl on BGA wetting given Head in Pillow (HiP) as result. The aging of components was done following the procedure of J STD 002C in which the components are exposed to a low amount of steam water for several hours. As a procedure modification, NaCl was added to the water that forms steam in several concentrations. The results show the more time of steam exposition, the more HiPs are obtained. Additionally, the higher concentration of NaCl in the water, the more HiPs are formed. As a conclusion, NaCl presence could inhibit tin wetting when the proper conditions of energy and environment exist. One interesting fact is during the analysis of BGAs with SEM/EDX; the presence of NaCl was not detected on the solder/BGA ball interface but was found on its edges. This finding would be explained because solder flux tries to remove the contaminants of the interface putting them around the Ball/solder interface. Besides, the oxygen concentration on BGA balls analyzed by SEM increased little or none at all showing the oxide increase cannot be detected by this type of analysis. Because of that, TOF SIMS analysis was carried over showing an increase of oxide on tin surface. Introduction In the electronics industry, Surface Mounting Technology (SMT) has allowed the assembly miniaturization making the products smaller and more productive[1] Inside of this type of technology, the component packages have played an important role creating or having hundreds of electrical connections to the active components (Transistors, Memories, Microcontrollers, etc) in a reduced area. One of the most popular component packages is BGA (Ball Grid Array) see Figure 1. The BGAs are electronic components in which the solder joints are ball shaped and found underneath of component body. Because the component surface is used to create hundreds of solder joints, BGA may have a large number of connections giving flexibility to designers. This is very useful to exchange a lot of information (digital and analog) plus other necessary connections (Power, clock, reset, etc) therefore, many Microprocessors use BGA package as the main one to reduce their size. However, the connections are underneath the component or substrate body so it is difficult to inspect them visually (with a microscope) that is the main inspection used in SMT; Because of this, a faulty connection is very difficult to catch or detect, for example, a nonwetting solder joint using visual inspection only. One specific type of defect that has become more prevalent on Ball Grid Arrays is Head on Pillow (HoP) or Head in Pillow (Hip)[2] Head in Pillow is a BGA solder joint defect in which the solder paste wets the pad but does not fully wet the ball, see Figure 2. The solder ball physically touches the solder paste deposit but there is not a metallurgical joint. The improper electrical connection situation becomes more severe because many of these type of connections would be electrically intermittent. This is due to a lack of solderability between the ball surface and solder paste alloy due to oxidation, contamination or a mechanisms that prevents the solder alloy to form a joint with the solder balls. One of the main possible causes is excessive oxidation even though the excess oxidation has mainly been attributed to external control problems of solder paste handling or reflow profile. The Head in Pillow defects have become more prevalent since BGA components started to use lead free alloys because higher temperatures are used and fluxes are more sensitivity to oxide thicknesses. The growing use of lead free soldering in electronics manufacturing has increased defects that require proper identification and troubleshooting. Besides, a warpage effect can increase the probability of failure, when the solder reaches the liquid phase during soldering, the balls and solder As originally published in the IPC APEX EXPO Conference Proceedings. paste deposits are separated physically. Consequently, there would not be sufficient fluxing activity left to break down the oxide layer when the solder ball and solder paste deposits touches again, resulting in possible HiP defects [3] However, we have found cases in which reflow profile agrees with the recommendations of the solder paste supplier, and/or you have a proper management of solder paste, but you can have still problems with HiP One of the possible causes of Head in Pillow not investigated deeply is the presence of contaminants that could alter the solderability of the solder balls. In a recent study, we found that the presence of chlorine could inhibit the solderability of the tin metallization (SOD 123) [4] In this report, we investigated how the chlorine presence would alter the BGA solder ball solderability The tool used to perform these tests is the Design of Experiments (DOE) The DOE is defined as a set of tests in which changes in parameters that control a system or process are made in order to analyze, observe and identify the impact on the output variable or process responses. All phenomena, which can be observed and have features susceptible that would be measured, exhibit a variable behavior and we can analyze with a DOE. The design is the part that can be controlled by the experimenter, and its factor and level structure is the base of the experiments. Some of the main parts of a DOE are the Factors (Each variable that can potentially influence the outcome of an experiment, for example: temperature, time, pressure) Interactions (Effect produced by the action of a factor, modified by changes in other factors) Levels (Discrete values taken by a factor in all experiments) Main Effects (Variations in the response of the system, attributable to the change in the level of a factor) and Answers (Values of the variable being optimized for example: performance of a chemical reaction, stability of an emulsion) Figure 1. An example of Ball Grid Array (BGA) Figure 2. Head In Pillow Defect in a BGA connection (See the red circle) In the next section, several DOEs are carried over to show the influence of Chlorine on the solderability of BGA solder balls. For that, the procedure to age components is according to J STD 002, in which the metallizations are set over a small steam flow for several hours (The most recommended are 8 hrs although 16 hrs can also be used) to simulate aging or storage time. The modification is to add Cl in form of salt (NaCl or similar ones) to the steaming water and the purpose is to verify how the aging conditions would be altered with the presence of additional elements or contaminants. The suggested hypothesis is Cl presence on BGA balls before any electrical test or long storage time would diminish the wetting capacity of the BGA balls. In order to speed up storage time, the next specific procedure is followed: Components are put over steam (approx 89degC) in similar conditions described in J STD 002 but NaCl is added to the steaming water. Steam will give the energy that is given by electrical tests or storage conditions to alter BGA ball wetting. A series of DOEs was performed to analyze the solderability. I. DOE 1. Creating HiPs I.1. Objective In this DOE, a study was conducted to verify the influence of various elements including Cl on BGA solderability. The aim was to show the influence of Cl presence (in form of salts) on BGA soldering and if Head in Pillow can be created in the SMT process. The form to add Cl is using the aging steam procedure similar to J STD 002 but using tap water with NaCl added at 10% I.2. Description Table 1 shows the factor to study which is time and its levels are 3: 4, 8, 16 hrs. The constants are: Stencil, LF Profile, SMT Line, and Lead Free solder paste. The variations are component coplanarity (BGA) Pick and Place Position, Reflow oven variability. The experimental unit is a BGA with 208 solder balls and 1mm pitch. The DOE is one way Anova. Table 1. Cl presence (in form of NaCl Salt) on BGA SMT process Factors Levels Output Constant Noisy Variable Instrument of Verification Experimental Unit Type Time 3 (Steam NaCl) 4, 8, 16 hrs BGA HiP Stencil Component coplanarity Visual by Expert detaching components BGA 208 1 mm pitch One Way Anova Current Profile Pick and Place Position SMT Production Line Reflow Variability LF Solder Paste I.3. Results In residual plot analyses, see Figure 3(a) we can see there are some outliers, but we would consider these have low influence. The model would give good correlation, although the variances are influenced due to the final value, see top right graph in Figure 3(a) The p value is lower than 0.05, see Figure 3(b) This means the time under the salt containing steam has influence on BGA HiP. (a) (b) Figure 3. (a) Residual Plot Analysis, (b) Result for DOE 1 Anova: HiP versus steaming hour In the box plot, Figure 4(a) the results of HiP created per component versus time are shown. The more time, the more HiPs are created up to making the entire component not solderable. Because there is a clear relationship between HiP and time, a linear regression is proposed, see Figure 4(b) The linear regression has a R of 0.80 which is an acceptable correlation. (a) (b) Figure 4. (a) Box Plot Graph: The results of HiP number versus time, (b) Linear regression with a R of 0.80 (good correlation) I.4. HiP Images The images in Figure 5 show the
J Servin C Gomez M Isabel Dominguez
211116483
Advanced Second Level Assembly Analysis Techniques Troubleshooting Head In Pillow, Opens, and Shorts with Dual Full Field 3D Surface Warpage Data Sets
SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller, with denser interconnect arrays, and processes such package on package assembly become prevalent, advanced methods using dual surface full field data become critical for effective Assembly Planning, Quality Assurance, and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required, to effectively address the challenges of modern SMT assembly. To fully understand and characterize variation in the gap that is the main cause of solder joint defects such as head in pillow, shorts, and opens, analysis of the interface between the mating surfaces needs to be: Full field: A high density of data represents surface warpage much more finely than an approximation such as coplanarity, allowing area specific review and analysis Dual surface: Making assumptions about how the "bottom" surface is shaped when mounting a component neglects the complex behavior the land area might exhibit during the thermal cycle, and is a deficiency when attempting thorough assembly planning or failure analysis Full profile: Making assumptions about when the single temperature when warpage of surfaces is important during the thermal cycle can lead to missing critical parts of the reflow process, overlooking when defects such as head in pillow can be caused Statistical: A large enough quantity of samples should be measured to allow confident calculation of expected average, maximum, minimum, and extreme (3s) gaps between surfaces. After measuring warpage of multiple surface mount components and land areas separately, the collected data can be combined into statistical summaries for each temperature point. Reviewing the combined data at the start of assembly planning can provide an overview of dual surface warpage at each temperature, and for the entire thermal profile. The measurement and analysis results that follow include a package to board assembly interface case study, and calculations, graphs, and methodology highlighting the use of gap limits and pass/fail maps to visualize areas with potential assembly issues. This analysis method provides new capabilities when planning and monitoring the assembly interface across a full reflow cycle that can help predict and compensate for defects such as head in pillow. Introduction The APEX 2009 publication "Telecommunications Case Studies Address Head in Pillow (HnP) Defects and Mitigation through Assembly Process Modifications and Control" is one of the most thorough published reviews of the head in pillow defect problem and how those responsible for troubleshooting poor yields analyze the problem and mitigate its severity. 1 In the past few years since it was published, the problem of head in pillow, or head on pillow as it is also called, has become more widely documented and discussed. It continues to grow as a concern and a detriment to both initial yield and end user field reliability, as trends in electronics design push the limits of component size, thinness, and materials, with everdecreasing interconnect pitches and solder ball sizes. All these forces make the reliable assembly of parts during the reflow process more challenging. The following is a review of a relatively new dual surface analysis method that electronics manufacturers are now using to more fully understand component shapes throughout the reflow process, during the preproduction design, assembly planning and troubleshooting, and quality assurance phases of product development and manufacturing. Warpage Standards One of the major causes of head in pillow defects, opens, and shorts/bridging, is component warpage. 2 Since packages began to be manufactured without ceramic substrates, warpage has become an important factor when assembling BGA devices, both die to substrate, and second level package to PCB. The effects of warpage have continued to increase. One of the biggest product design, production yield, and reliability issues is warpage, since excess warpage and even small variations in the amount of warpage can cause an unacceptable defect rate. 3 For many years, coplanarity has been the measure used to indicate warpage, or deviation from flatness, in the electronics industry. Simply stated, coplanarity is the distance between the highest point and the lowest point measured. Optionally, a or sign may also be assigned, indicating a 'smiling' or 'crying' shape, whether the shape is concave or convex when looked at from the side. 4 All the related industry standards in wide use today deal specifically with package warpage. How to measure it, and in some cases the allowable limits a package can demonstrate and still assemble reliably. 5 Individual companies also have their own internal, proprietary limits for components, in many cases. These limits on coplanarity are derived through calculations, experimentation, or both, and given certain process controls they serve to 'ensure' an acceptable production yield. But coplanarity limits have their own limitations. There is frustration in the industry because, while a standard that indicates a method for measuring warpage throughout the reflow cycle may be universally applicable, the standards that set specific numerical acceptance limits (such as 'package coplanarity must be less than 100 microns' can be useless or even harmful to decision making in some cases. 6 It is very likely that an assembly of components demonstrating a coplanarity within 'standard limits' could fail in certain cases, and also likely that packages with more than the established coplanarity can assemble with zero defects. Those responsible for assembly, with millions of production units to assemble and high pressure deadlines, cannot rely on the current published or proprietary standards to make the best decisions related to component shape compatibility and expected reliability. Why traditional coplanarity limits are too limited There are several reasons that setting coplanarity limits doesn't work as well as those setting the limits intend. Some of them are: The limits are generated from a relatively small set of components, under controlled conditions. All the variables in the process are not recorded, such as exact flux types and equipment settings, but the limits are derived from work done within those controlled conditions. The limits assume a low, symmetrical warpage from the land area (such as a PCB surface) Standards may indicate a warpage 'budget' for the land area of a small percentage of the total warpage, such as 20% 7 It is common for a BGA land area to demonstrate much higher warpage than this limit, even with conventional PCB materials. 8 Newer 'cutting edge' materials tend to demonstrate even higher warpage than standard materials. The limits assume peak warpage/coplanarity is the important measure, and that it occurs at a particular temperature point, such as peak temperature. Defects, especially head in pillow and non wet opens, can develop at critical points during the reflow cycle other than at peak temperature. The solder ball oxidation that results in head inpillow defects, for example, happens earlier in the cycle. 9 The limits address the warpage of a single surface, not the shape compatibility of the two surfaces that are actually attaching during assembly. With a single surface, knowing the gap that will exist at an interconnect location at a particular temperature point, which is critical to predicting reliability, is impossible. 'Gap per Interconnect' analysis prerequisites Head in pillow and most other assembly defects traditionally associated with warpage are caused by the gap between attaching surfaces at each interconnect, at different points during the reflow assembly process. For reasons including those listed above, a thorough analysis of SMT component assembly must include identifying these gaps. To be effective, the method needs to be: Dual surface for anyone who wants the true gap at each interconnect, making assumptions about half of the attachment area is not sufficient. Both surfaces must be measured, then the two surfaces must be analyzed together in a shared (x,y,z) coordinate system. Full field modern methods of measuring warpage typically include optical technologies with a fairly high data density, usually greater than 1 point per square mm. This is worth listing as a requirement though, since surfaces can have complex shapes, and checking only a few points, such as at the corners and center, cannot register shapes sufficiently to reliably establish the gap at each interconnect. Data density must be sufficient to represent the fullfield shape of the attach area. Full profile understanding the wide range of defects that can happen due to gaps during the reflow process requires analyzing gaps at various temperature points throughout that process. In most cases, evaluating gaps at multiple temperature points is necessary for thorough understanding of how the surfaces interact. Statistical enough samples must be measured, of both attachment surfaces, to be confident that they represent a statistically relevant sampling of the component population. When checking gaps at the interconnect locations, it is useful to have surfaces that represent the maximum gap expected, minimum gap, average gap, and even statistically calculated gaps such as average gap 3*(standard deviation of the gap) for each interconnect. Depending on the intent of the analysis, or the nature of the troubleshooting issue, different statistical gaps could be of more use than others. Methodology and Data For best results, dual surface
Ken Chiavone
138905570
Study on Head in Pillow Defect for Lead Free BGA
Solder paste and solder ball are not completely fused into one BGA head in pillow,Upside down as head on a pillow.Four effective methods for observing are introduced.And analyze the potential factors of this defect from design, materials and process.Then select PCBthg point,stencil thickness,BGA mounting deviant and reflow chain speed as four factors to DOE.After successfully copy the head in pillow defect,discuss the effect of all factors.Finally find that the chain speed is the most significant one.
Hou Chang-jin Smt Lab
128266102
Head in Pillow HnP Defects and Mitigation through Assembly Process Modifications and Control
One of the most perplexing phenomena in the electronic manufacturing industry today is the defect called "head in pillow." Head in Pillow (HnP) defects occur on the blind solder joints of area array packages such as FBGAs, mBGAs and CSPs. Often these insufficient or intermittent solder joint defects go undetected during manufacturing despite inspection with conventional X ray systems. They also are insidious reliability defects that often escape the normal testing procedures and fail at the end user site. The head in pillow defects typically occur at the corner pins and outer rows of packages and are associated with package warpage. There are new 3D imaging systems that can help detect this, but they rely on the operator to interpret the images. There are BGA video inspection systems that can view under most devices, depending on the standoff, but they are dependent on the access, viewing angle, and operator interpretation. These x ray and video processes also are very slow and costly. There are several factors that can contribute to the head in pillow phenomena including package co planarity, package warpage, and assembly issues associated with solder paste characteristics and stencil printing. From a process standpoint, the cause of the head in pillow often is the result of the sum of all of the component and assembly process tolerances. This paper will discuss several contributing factors to the head in pillow defects and techniques to control them. It will include reviewing DOE for solder paste deposition of five different pastes, Shadow Moire scans on several problematic devices, cross section analysis of failed solder joints, and solder paste analysis of "head in pillow" pastes. The case studies presented show that process control can mitigate HnP defects but may not be successful for some severe examples of HnP defects. This paper uses components from telecommunication product case studies to demonstrate the effects of different contributing factors and mitigation techniques for HnP defects. The case studies include reviewing solder paste printing modifications, solder paste DOE, Shadow Moire scans on several problematic BGA packages, effectiveness of x ray inspection, and crosssection analysis of failed HnP solder joints. Together, these case studies show that BGA package warpage is a major contributor, but HnP defects can occur when almost any of the assembly process parameters deviate from acceptable practices. INTRODUCTION There are several trends in the electronics industry that have increased the challenges of surface mount (SMT) board assembly. These include conversion to Pb free manufacturing, increased density at both the printed circuit board (PCB) and package level, new package constructions, new laminate material sets, and thicker PCB constructions. One of the consequences of the evolving and challenging technologies has been the increased occurrence of an open joint ball grid array (BGA) defect called head in pillow [1 ref] This defect is known by many other names such as head on pillow, head and pillow, ball in cup, ball in socket, and hidden pillow. For the purpose of this paper, the defect will be referred to by the acronym HnP. The HnP phenomena are characterized by complete melting of both the solder paste and the BGA solder ball but with insufficient coalescence to produce well formed solder joints. Figure 1 shows examples of HnP defects using: a) an optical photomicrograph of a typical HnP metallographic cross section and b) an optical photomacrograph of the outer row of a BGA with an HnP defect. Figure 1a shows that the BGA ball sits on the solidified paste without forming a contiguous, well formed solder joint. These are latent defects that are not detected using standard manufacturing test methods such as visual inspection, x ray, and particularly electrical screening. The latter is important because these defects can pass in circuit and functional test, only to fail completely or give an intermittent connection after some period of deployment in service. The increased frequency of HnP defects has coincided with a decrease in component interconnection pitch below 1mm, a decrease in solder paste deposits below 6 mil thickness and an increase in processing temperature to accommodate Pb Free assembly. HnP is now recognized to the point that inspection systems and solder pastes are being developed to target this problem. Additionally, standards development organizations are attempting to address this from a device standpoint [ref] Despite these efforts, HnP defects have not been eliminated and in fact, probably are increasing because assembly process windows are decreasing. Typically, HnP defects are associated with the higher reflow temperatures used in Pb free manufacturing. Although surface contamination can cause HnP, it is more common for the defect to be attributed to the excessive component and PCB warpage that results from higher temperature processing. This paper will use a number of case studies to illustrate that sufficient warpage can occur in the SnPb reflow range as well as the Pb free range resulting in HnP defects. The paper also will discuss several contributing factors to the HnP defects and techniques used to mitigate or control them. This will include reviewing DOE data for solder paste deposition of five different pastes, Shadow Moire data on several problem devices, cross section analysis of failed solder joints, and a comparison of solder pastes used to mitigate HnP. The case studies presented show that process control can mitigate HnP defects but may not be completely effective in some severe examples of HnP defects. Figure 1. Examples of HnP defects a) optical micrograph of solder joint cross section, and b) Side view of a row of BGA balls with HnP at arrow. HEAD in PILLOW DESCRIPTION The HnP defects are created during the reflow process and have been described in the work by Amir et al (Intel [1] Figure 2 shows pictorially how a gap develops between the ball and the solder paste due to dynamic warpage of the package or PCB. If there is insufficient flux activity to remove the oxide coating on the surface of the ball, or there is some contamination on the solder ball or molten solder paste mass, these two will not coalesce as shown in Figure 2d. The end result is an HnP solder joint defect when the package cools below solidification (Figure 2e) Deleted:
Russell Nowland
20442437
Head in pillow defect role of the solder ball alloy
Head in pillow (HIP) defect is a growing concern in the electronics industry. This defect is usually believed to be the result of several factors, individually or in combination. Some of the major contributing factors to the HIP defect are: surface quality of the BGA spheres, activity of the paste flux, improper placement misalignment of the components, a non optimal reflow profile, and warpage of the components.
2010 12th Electronics Packaging Technology Conference
Ranjit S Pandher Navendra Jodhan Rahul Goroba Raut Michael James Liberatore
211115017
Addressing the Challenge of Head In Pillow Defects in Electronics Assembly
The head in pillow defect has become a relatively common failure mode in the industry since the implementation of Pb free technologies, generating much concern. A head in pillow defect is the incomplete wetting of the entire solder joint of a BallGrid Array (BGA) Chip Scale Package (CSP) or even a Package On Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head in pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process material) of the head in pillow defects. It will thoroughly review these three issues and how they relate to result in head inpillow defects. In addition, a head in pillow elimination plan will be presented with real life examples will be to illustrate these head in pillow solutions. INTRODUCTION: While the electronics manufacturing industry has been occupied with the challenge of RoHS compliance and with it Pb free soldering, trends towards increasing functionality and miniaturization have continued. The growing use of ultra fine pitch and area array devices presents challenges in both printing and flux technology. The decreasing size and pitch of said components create new problems, such as head in pillow. What does head in pillow look like? A head in pillow defect is the incomplete coalescence of the solder joint between a Ball Grid Array (BGA) Chip Scale Package (CSP) or Package on Package (PoP) and the printed solder paste. For some reason, the printed wiring board's (PWB's) printed solder and the package's solder spheres do not come together to form a single mass. At first glance, it looks as if a film has formed on the surface of the molten solder, preventing the merging of the printed and package solders. In fact, this may be true, as in some instances there seems to be an oxide film on the surface of the molten solders. In other instances, it appears that upon cooling, the exterior has already cooled enough to prevent the coalescence of the printed paste and the sphere at re connect when the warpage subsides. From the cross sections, it actually looks like a head has pressed into a soft pillow (see Figure 1) Figure 1: Example of a Head in pillow (HIP) defect It is these issues that are the cause of head in pillow defects: poor wetting and warping of the component. Upon examination, the two causes are indistinguishable, but can be identified because random head in pillow defects are caused by poor wetting, As originally published in the IPC APEX EXPO Proceedings.
Mario Scalzo