FO-WLP
212645669
Magnetic Inductor Integration in FO WLP using RDL first Approach
FO WLP with integrated solenoidal magnetic core inductor in the RDL layer was proposed and developed in this work. This provide a packaging solution to integrate high performance inductors for high efficiency power conversion to the embedded device chips without sacrificing valuable chip estate as compared to integrating the inductors on the surface of device chip. Two photo dielectric materials were evaluated and it was found that material with higher tensile strength and percent elongation was able to sustain the magnetic film deposition and patterning process without showing cracks or delamination. Different patterning methods of the magnetic film were explored. Wet etching method has residue issues on low lying features in valley and contact vias. The sidewall of the magnetic core was highly sloped for thicker magnetic film due isotropic nature of the wet process. Dry etching was inefficient to etch the thick magnetic film. A new patterning method was developed to overcome the wet etching issues to produce magnetic core with vertical sidewall with no residue issues. Electrical characterization was performed on the fabricated inductor. The inductor shows a flat inductance response up to its self resonance frequency, and a quality factor of 14 can be achieved. These indicates that the inductor has low loss and can be utilized in high efficient power conversion.
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)
Soh Siew Boon David Ho Soon Wee Raju Salahuddin Ravinder Pal Singh
212645061
High Density RDL build up on FO WLP using RDL first Approach
FO WLP based on RDL first integration flow with 8 metal layers in a single side was proposed and demonstrated to meet advanced, high density applications for SiP. 7 layers of Cu RDL and 1 layer of UBM were fabricated using semi additive process and low temperature cured photo definable dielectrics were used as the passivation. The minimum Cu trace L/S of $2 \mu \mathrm{m} and contact via openings of $5\ \mu \mathrm{m} were implemented in the test vehicle. Electrical test structures were used to characterize the Cu RDL electrical performance. Electrical continuity was achieved across the daisy chain structure connected to each metal layers. Meander line comb structures shows pico ampere range leakage current for both intra and inter layer Cu traces. I V curve of $2\ \mu \mathrm{m} LW Cu wire shows ohmic behavior with slight increase in resistance with increasing current, due to increasing current density associated with small LW wiring. S parameters were characterized on GSSG transmission line test structure with $2\ \mu \mathrm{m} LW Cu traces and 8 mm wire length. Insertion loss was greater 2 dB, due to the small cross sectional area and long wire length of the signal line. Maximum cross talk between adjacent signal lines with $4\ \mu \mathrm{m} spacing is 20.5 dB.
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)
Soon Wee Ho Hsiao Hsiang-Yao Simon Siak Boon Lim Chong Ser Choong Sharon Lim Pei Siang Chai Tai Chong
146729269
Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan Out Wafer Level Packaging (FO WLP)
This chapter provides an overview of advanced dielectric materials developed by HD Micro Systems (HDM) that are based on polyimide (PI) and polybenzo xazole (PBO) technologies and that are targeted for use as redistribution layers (RDL) in fan out wafer level package (FO WLP) applications where lithographic and reliability performances are important requirements. The first PI products for semiconductor applications were introduced in the early 1970s for use as stress buffers or passivation layers on integrated circuits as well as interlayer dielectrics in high density interconnects on multi chip modules. It is well known that dielectrics based on PI and PBO technologies are widely used as RDL in fan in wafer level packaging (WLP) flip chip chip scale packaging (FCCSP) and other applications to relocate I/O connections and reduce stress as well as allowing die stacking. The chapter details the process flow, lithography, material properties, and reliability performance that have been generated for PBO Gen3 to date and where PBO Gen2 is used as a reference.
Advances in Embedded and Fan Out Wafer Level Packaging Technologies
Tetsuya Enomoto Takeharu Motobe
208631961
Latest Technologies of Epoxy Molding Compound (EMC) for FO WLP
FO WLP is used for RF etc. for mobile as a package excellent in low profile, low warpage, cost reduction, electric performance etc. and this market is expanding since it began to be used in Application processer (AP) in 2016. It is expected that adoption to AP for mobile will continue to grow and further expansion to other products is also expected. Meanwhile, Epoxy molding compound (EMC) for FO WLP is required to have functions not found in EMC for low end packages. For example, since the molding area is large and the molding thickness is thin, if a conventional EMC is used, the warpage becomes large after curing and it cannot proceed to the subsequent process. In order to control warpage after curing, it is important to reduce cure shrinkage of EMC. In addition, in order to fill completely the gap between flip chip bumps of large size chip, control of filler size, melt viscosity etc. is more severely required.
2019 International Wafer Level Packaging Conference (IWLPC)
Takeshi Mori
232236208
Solder Joint Reliability Assessment and Pad Size Studies of FO WLP With Glass Substrate
In recent years, the use of fan out packaging solutions has boomed in semiconductor related fields. There are primarily two versions used for mass production: wafer level and panel level. In this research, a glass substrate was used in the design of a fan out wafer level package (FO WLP) and simulations were conducted to predict the reliability of the solder joints. The advantages of glass substrates are their excellent electrical properties, good mechanical rigidity, flatness, and adjustable coefficient of thermal expansion. To verify the robustness of the simulations, a FO WLP test vehicle was designed, manufactured, and tested under JEDEC thermal cycling condition. In this study, the simulation results were used in an empirical equation to estimate the reliability of the FO WLP under accelerated thermal cycling conditions. After simulation validated by experiments, parametric simulations of different design factors can be performed. Using this methodology, we developed a reliable finite element analysis procedure. Thus, structural optimization of the FO WLP was possible via simulations using various design factors to improve its reliability. The simulation results indicate that a suitable combination of upper, lower pad sizes and the thickness of buffer layer could significantly enhance the reliability life of FO WLP, and that designers should devote greater attention to these factors to achieve better long term reliability performance.
IEEE Transactions on Device and Materials Reliability
P H Wang Y C Lee Ching Kuan Lee H H Chang K N Chiang
208631503
Novel Temporary Bonding and Debonding Solutions Enabling an Ultrahigh Interonnect Density Fo Wlp Structure Assembly with Quasi Zero Die Shift
Next generation temporary bonding adhesive material is introduced into imec's high interconnect density flip chip on fan out wafer level package (FC FOWLP) concept [1] [2] After molding on silicon substrates, an ultralow die shift with an average of 2\mu \mathrm{m} die to carrier mismatch and warpage of 200\mu \mathrm{m} were achieved in a full 300 mm wafer. These values are orders of magnitude improvement over results reported in literature and has major implications on the processing of overmolded substrates. The combination of this low warp and ultralow distortion opens the possibility for fine pitch RDL combined with a chip first approach, which was impossible until now. The evolution of warpage and die shift through multiple processing steps will also be discussed in this paper.
2019 International Wafer Level Packaging Conference (IWLPC)
Arnita Podpod Andy Miller Gerald Beyer Eric Beyne Alice Guerrero Xiao Liu Qi Wu Kim Yess Kim Arnold Alain Phommahaxay Pieter Bex Koen Kennes Julien Bertheau Hariharan Arumugam Tom Cochet Kenneth June Rebibis E Sleeckx
54444320
FO WLP multi DOF inertial sensor for automotive applications
Fan out wafer level packaging (FO WLP) is the fastest growing packaging technology. Besides providing greater number of IOs than could be obtained by fan in wafer level packaging (WLP) it also offers interesting opportunities for multi die packaging with minimum package dimensions. Combined inertial sensor is an established category of automotive sensor components. with of two or more MEMS sensor dies for 36 axis motion measurement and an interface circuit die. It is used for electronic chassis stability control (ESC) and for advanced driver assistant systems (ADAS) Currently the sensor is packaged in various standard or proprietary configurations: ceramic cavity packages, pre molded plastic cavity packages, over molded SOIC, PBGA. The demand is towards smaller foot print and smaller height, lower cost and better robustness to vibrations. FO WLP offers some excellent characteristics like small size, compatible cost, vibration robustness and low stress to sensitive MEMS dies. Present work shows that it will also reach automotive reliability requirements and pass high temperature, thermal cycle and temperature humidity tests. Three fracture mechanism of the solder ball IOs were identified at 2000 thermal cycles. Solder fatigue was no issue and by design changes two other mechanisms can be corrected. Two fold redundancy will make an IO failure rate low enough. EMI and internal cross talk protection was found better than with existing devices. Reversible humidity dependence due to moisture absorption by polyimide film was seen and a lay out change was implemented to overcome it.
2018 7th Electronic System Integration Technology Conference (ESTC)
Heikki Kuisma Andre Cardoso Nikolai Mantyoja Rudiger Rosenkrantz S Nurmi Martin Gall
51980854
Board Level Reliability Investigation of FO WLP Package
As current technology development trend of microelectronic industry driven by portable and wearable electronic products, adopting advanced IC fabrication process technology and a powerful integrated fan out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices[1][3] This fan out wafer level package (FO WLP) to extend the functionality performance within thin form factor for fulfilling product application requirements is essential and important to a successful new product development, especially for Application Processor, Field Programmable Gate Array (FPGA) and power management IC (PMIC) products[1] FO WLP is good electrical performance package by its very short distance package level interconnection, and it has been rapidly adopted for 12 inch copper fabrication process technologies. Knowing its very thin package without package substrate as stress buffer between IC chip and system board, board level reliability performance of FO WLP becomes challenge as products moving to large die size for enabling more functionality on the same or less space due to higher package stress induced by larger die size[2] The board level underfill(UF) has been implemented in Surface Mount Technology(SMT) assembly process to prevent mechanical stress induced solder ball and redistribution layer (RDL) damage[4] In general, the UF will help to reduce the mechanical stress to impact solder joint reliability. However, due to less sophistication of SMT UF process compared with flip chip assembly UF process, such as no pre plasma treatment, high dispensing speed and no CSAM inspection to detect the dispensing quality, SMT UF dispensing quality brings a great of quality and reliability concern to the FO WLP package joint on board, especially electrical leakage issue due to small ball pitch of the package. Therefore, it becomes the objective of this study on SMT production quality and reliability risk of FO WLP package on board with focusing on board level UF filling into BGA balls of FO WLP package impact to product reliability.
2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
S M Hou K H Tsai M F Wu M Ku P H Tsao L H Chu
67874831
Development of Antenna on FO WLP
This paper describes the process development of fan out wafer level package (FO WLP) package that uses mold encapsulation to form the antenna element. The FO WLP package is designed with a target frequency of 60GHz for wireless local area network (WLAN) applications. The package consists of embedding a radio frequency integrated circuit (RFIC) chip in mold compound to form a reconstructed wafer. Redistribution layers (RDL) are then processed on the reconstructed wafer to form interconnections and excitation elements of the RF chips. The reconstructed wafer is then encapsulated with a 2nd level mold on the RDL side and Cu patch radiators are fabricated on top of it. The 2nd level mold will be sandwiched between the excitation elements and patch radiator and hence can function as the patch antennas for WLAN applications. Through mold vias (TMV) are then laser drilled through reconstructed wafer to form vertical interconnections with the embedded RFIC chips. The bottom RDL layer is then fabricated on the backside to function as the ground planes and solder pads for board level package assembly.
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)
Serine Soh Siew Boon David Ho Soon Wee Hsiao Hsiang Yao Simon Lim Siak Boon Sharon Lim Pei Shan Chong Ser Choong Chai Tai Chong
52933277
Warpage Simulation and Optimization of Fan Out Wafer level Package(FO WLP) with TMV under Different Processes
Fan Out wafer level package (FO WLP) has become a mainstream advanced packaging technology and from the first generation fan out package, the second generation of new fan out packaging technologies, such as FO MCP, FO POP, and POP SiP is gradually derived. In FO WLP, wafer warpage caused by mismatch of coefficients of thermal expansion (CTE) between materials has always been an important matter. This paper aims at a FO POP package, which uses through mold via (TMV) to achieve the upper and lower interconnections between packages. The packaging method is chip first and face up. The wafer warpage in each thermal process of the package is simulated and analyzed. At the same time, the chip spacing, molding compound thickness, TMV diameter, carrier thickness and material effect on warpage in the plastic molding process and copper layer thickness, copper area ration, dielectric layer thickness and material effect on warpage in the re distribution layer (RDL) process is studied. And an effective method for reducing wafer warpage in each thermal process is proposed.
2018 19th International Conference on Electronic Packaging Technology (ICEPT)
Yanhui Guo Guohua Zhang Jianfeng Wang