10626
All trees contain a large induced subgraph having all degrees 1 (mod k)
We prove that, for integers n ? 2 and k ? 2, every tree with n vertices contains an induced subgraph of order at least 2?(n + 2k ? 3)/(2k ? 1)? with all degrees congruent to 1 modulo k. This extends a result of Radcliffe and Scott, and answers a question of Caro et al.
34464594
On Quadrilaterals and Cycle Covers in a Bipartite Graph
12358667
On Covering a Bipartite Graph with Cycles
We conjectured in [H. Wang, Australas. J. Combin., 19 (1999), pp. 115--121] that, for each integer $k\geq 2$, there exists N(k) such that if G=(V1,V2;E) is a bipartite graph with $|V_1|=|V_2|=n\geq N(k)$ and d(x)+d(y)\geq n+k$ for each pair of nonadjacent vertices x and y of G with $x\in V_1$ and $y\in V_2$, then for any k independent edges e1, . . ., ek of G, there exist k vertex-disjoint cycles C1, . . . ,Ck in G such that $e_i\in E(C_i)$ for all $i\in\{1,\ldots ,k\}$ and $V(C_1\cup\cdots \cup C_k)=V(G)$. This conjecture is also verified for k=2 in [H. Wang, Australas. J. Combin., 19 (1999), pp. 115--121]. We prove this conjecture for k=3 in this paper.
36127171
Packing Three Copies of a Tree into a Complete Graph
Abstract A three T of order n is said to be 3-placeable if there are three edge-disjoint copies of T in Kn. In this paper we characterize all the trees T such that T is 3-placeable.
5245849
On Independent Cycles in a Bipartite Graph
Abstract. Let G=(V1,V2;E) be a bipartite graph with 2k≤m=|V1|≤|V2|=n, where k is a positive integer. We show that if the number of edges of G is at least (2k−1)(n−1)+m, then G contains k vertex-disjoint cycles, unless e(G)=(2k−1)(n−1)+m and G belongs to a known class of graphs.
30994252
An extension of a theorem on cycles containing specified independent edges
We give an alternative proof of a conjecture due to Wang (J. Graph Theory 26 (1997) 105) in a stronger form. The main theorem states that for any integer k ≥ 2 if G is a graph of order n ≥ 4k - 1 and d(u) + d(υ) ≥ n + 2k - 2 for each pair of non-adjacent vertices u and υ of G, then, for any k independent edges e1,... ,ek of G, there exist k vertex-disjoint cycles C1,..., Ck in G such that (i) ei ∈ E(Ci) for all 1 ≤ i ≤ k, (ii) V(C1)∪ ... ∪V(Ck) = V(G), and (iii) #{i ≤ k||Ci| a > n - 4k + 2). It strengthens the conjecture of Wang, which was first proven by Egawa et al. (Graphs Combin. 16 (2000) 81).
424163
Reliable Observer-Based Control Against Sensor Failures for Systems With Time Delays in Both State and Input
For systems with both state and input time delays, a novel state and sensor fault observer is proposed in this paper to estimate system states and sensor faults simultaneously. In this design, a descriptor system approach and a linear matrix inequality technique are adopted, where the considered sensor fault may be in any form, even unbounded. Unbounded sensor faults will make the system fail unavoidably; it is indispensable to derive a reliable control scheme against sensor failures. Using the estimated state and sensor fault, a reliable observer-based controller is proposed, which makes the system work well no matter whether sensor faults occur or not. The present approaches are next extended to the case for systems with multiple time delays. Finally, a simulation example of the network of three cascaded reactors is used to illustrate the design procedure and demonstrate the efficiency of the present techniques.
35232295
Implementing a scalable ASC processor
Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.
17116425
Dynamic modelling and control for multivariable output distribution systems
Following the recently developed strategies for the modelling and control for multi-input multi-output (MIMO) distribution control systems, this paper presents a dynamic model for the control of combined probability density function. A multilayer perceptron (MLP) neural network is used to approximate the probability density function (PDF) of the systems and a high-order dynamic nonlinear state-space model is obtained. Then nonlinear principal component analysis (NLPCA) is adopted to reduce the obtained model order and a lower-order time-varying system is achieved. The controller design for the lower-order time-varying system is given. The effectiveness of the result has been demonstrated by two examples in the end.
27036581
Output PDF Shaping of Singular Weights System: Monotonical Performance Design
For a group of stochastic systems whose output probability density function (PDF) is modelled by the B-spline neural networks with singular weights dynamics, the output PDF is controlled towards the desired PDF by an innovative optimization design with monotonically decreasing performance. The controller is developed based on the transformed equivalent non-singular system with sufficient conditions given for the monotonic performance.
15405424
Intel nehalem processor core made FPGA synthesizable
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.