17027582
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache, for short. The CAT cache exploits locality property that exists among addresses of memory references. By keeping only a limited number of distinct tags of cached data, rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache, with only a few tag entries, performs as well as ordinary caches, while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip-area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.
14739906
Helper threads via virtual multithreading
Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent
62483723
Dynamic speculative precomputation
A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.
15405424
Intel nehalem processor core made FPGA synthesizable
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.
13981080
Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.
45664762
On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers
18081608
Covering vertices of a graph by k disjoint cycles
Abstract Let d, k and n be three integers with k⩾3, d⩾4k−1 and n ⩾3 k . We show that if d ( x )+ d ( y )⩾ d for each pair of nonadjacent vertices x and y of a graph G of order n , then G contains k vertex-disjoint cycles converting at least min{ d , n } vertices of G .
205762515
Minimum entropy of B-spline PDF systems with mean constraint
For the B-spline approximation of the continuous probability density function (PDF), the relationships between the B-spline weights and entropy both in general and under the mean constraint have been analyzed. It provides the conditions under which the minimum entropy can be achieved subject to the mean constraint. The difference between the entropy of continuous and discrete distributions has also been clarified. A minimum entropy controller with the mean constraint is then developed and several simulations are performed to verify the main results. (c) 2006 Elsevier Ltd. All rights reserved.
27662001
MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.
22681240
Distribution function tracking filter design using hybrid characteristic functions
A new tracking filtering algorithm for a class of multivariate dynamic stochastic systems is presented. The system is expressed by a set of time-varying discrete systems with non-Gaussian stochastic input and nonlinear output. A new concept, such as hybrid characteristic function, is introduced to describe the stochastic nature of the dynamic conditional estimation errors, where the key idea is to ensure the distribution of the conditional estimation error to follow a target distribution. For this purpose, the relationships between the hybrid characteristic functions of the multivariate stochastic input and the outputs, and the properties of the hybrid characteristic function, are established. A new performance index of the tracking filter is then constructed based on the form of the hybrid characteristic function of the conditional estimation error. An analytical solution, which guarantees the filter gain matrix to be an optimal one, is then obtained. A simulation case study is included to show the effectiveness of the proposed algorithm, and encouraging results have been obtained.
7096747
A Performance Study of Secure Data Mining on the Cell Processor
This paper examines the potential of the Cell processor as a platform for secure data mining on the future volunteer computing systems. Volunteer computing platforms have the potential to provide massive computing power. However, privacy and security concerns prevent using volunteer computing for data mining of sensitive data. The Cell processor comes with a hardware security feature. The secure volunteer data mining can be achieved by using this hardware security feature. In this paper, we present a general security scheme for the volunteer computing, and a secure parallelized K-Means clustering algorithm for the Cell processor. We also evaluate the performance of the algorithm on the Cell secure system simulator. Evaluation results indicate that the proposed secure data clustering outperforms a non-secure clustering algorithm on the general purpose CPU, but incurs a huge performance overhead introduced by the decryption process of the Cell security features.