6672981
Control Flow Optimization Via Dynamic Reconvergence Prediction
This paper presents a novel microarchitecture technique for accurately predicting control flow reconvergence dynamically. A reconvergence point is the earliest dynamic instruction in the program where we can expect program paths to reconverge regardless of the outcome or target of the current branch. Thus, even if the immediate control flow after a branch is uncertain, execution following the reconvergence point is certain. This paper proposes a novel hardware re-convergence predictor which is both implementable and accurate, with a 4KB predictor achieving more than 95% accuracy for SPEC INT, and larger implementations achieving greater than 99% accuracy. The information provided from reconvergence prediction can increase the effectiveness of a range of previously proposed performance optimizations, including speculative multithreading, control independence, and squash reuse. This paper also demonstrates a new technique that takes advantage of the dynamic reconvergence prediction information in order to predict a wrong path excursion ahead of branch resolution. On average, 34% of wrong path fetches are eliminated.
15405424
Intel nehalem processor core made FPGA synthesizable
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-of-order micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlike the Intel Atom core which was made FPGA synthesizable on a single Xilinx Virtex-5 in a previous endeavor, the Nehalem core is a more complex design with aggressive clock-gating, double phase latch RAMs, and RTL constructs that have no true equivalent in FPGA architectures. Despite these challenges, we are successful in making the RTL synthesizable with only 5% RTL code modifications, partitioning the design across five FPGAs, and emulating the core at 520 KHz. The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.
13981080
Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.
40482370
Quantitative evaluation of the register stack engine and optimizations for future Itanium processors
This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.
45664762
On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers
14739906
Helper threads via virtual multithreading
Memory latency dominates the performance of many applications on modern processors, despite advances in caches and prefetching techniques. Numerous prefetching techniques, both in hardware and software, try to alleviate the memory bottleneck. One such technique, known as helper threading improves single-thread performance on a simultaneous multithreaded architecture (SMT), which shares processor resources, including caches, among logical threads. It uses otherwise idle hardware thread contexts to execute speculative threads on behalf of the main thread. Helper threading accelerates a program by exploiting a processor's multithreading capability to run assist threads. Based on the helper threading usage model, virtual multithreading (VMT), a form of switch-on-event user-level multithreading, can improve performance for real-world workloads with a wall-clock speedup of 5.0 to 38.5 percent
35232295
Implementing a scalable ASC processor
Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.
27662001
MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.
19061048
A minimized zero mean entropy approach to networked control systems
A novel control method is proposed for networked control systems with nonlinear process, probably non-Gaussian process noise and time delays. The performance index of closed loop control system consists of entropy, mean value and control energy constraint. Two stochastic control methods for networked control systems are given under the same general frame. One method utilizes gradient optimal techniques to obtain an optimal control law, and the stability of closed loop systems is analyzed. The other method gives the optimal solution of control law directly. The implementation issues are emphasized. The sliding window techniques and non-parametric probability density function estimation techniques are employed to obtain the entropy of tracking error recursively. As a result, the controller can be on-line tuned. Finally, the methodology is illustrated by simulations.
2699916
Deception Detection Via Blob Motion Pattern Analysis
Deception dectection is one of the most difficult problems in affect recognition and expression research area. Recently, non-verbal methods of detecting deception have appeared to be promising. Thomas[1] presented a proof-of-concept study based on the blob analysis of some suspects' interviews and mock experiments video clips. In this paper, we present our recent research work in the direction of developing an automated deception detection system. We propose a blob motion pattern analysis approach to solve this problem.
7007458
An Algorithm for Identification of Reduced-Order Dynamic Models of Gas Turbines
Model based approaches show a lot of advantages for fault detection and condition monitoring. Particularly, it is true in employing reduced order models for real-time parameter identification and output prediction of gas turbines. Many algorithms have been developed, but most of them focus on one-step-ahead prediction models and involve complex computation. These algorithms are not acceptable for long-term prediction and real-time condition monitoring. In this paper, an improved gradient method (dynamic gradient descent) is proposed. The idea is to take account of the dependency of prediction errors and calculate the gradient information recursively. Not only low computation expense is achieved, but the non-Gaussian errors can also be overcome when this approach is applied to estimate parameters of a reduced order gas turbine model and to improve long-term prediction