34464594
On Quadrilaterals and Cycle Covers in a Bipartite Graph
39356858
Vertex-disjoint quadrilaterals in graphs
Let k be a positive integer and G a graph of order n. In (Discrete Math. 203 (1999) 229), we proved that if n=4k and @d(G)>=2k then G contains k-1 vertex-disjoint quadrilaterals. In this paper, we investigate vertex-disjoint quadrilaterals in G with n@?0(mod4), and we have found the best minimum degree condition @d(G)>=@?12n@? such that G contains @?14n@? vertex-disjoint quadrilaterals. As a result of our method, we have improved our previous result as follows: If n=4k and @d(G)>=2k-1 then G contains k-1 vertex-disjoint quadrilaterals.
9527664
Vertex-Disjoint Triangles in Claw-Free Graphs with Minimum Degree at Least Three
. Our main result is as follows: For any integer , if G is a claw-free graph of order at least and with minimum degree at least 3, then G contains k vertex-disjoint triangles unless G is of order and G belongs to a known class of graphs. We also construct a claw-free graph with minimum degree 3 on n vertices for each such that it does not contain k vertex-disjoint triangles. We put forward a conjecture on vertex-disjoint triangles in -free graphs.
36844780
Partition of a directed bipartite graph into two directed cycles
Abstract Let D = (V1, V2; A) be a directed bipartite graph with |V1| = |V2| = n ⩾ 2. Suppose that dD(x) + dD(y) ⩾ 3n + 1 for all x ϵ V1 and y ϵ V2. Then D contains two vertex-disjoint directed cycles of lengths 2n1 and 2n2, respectively, for any positive integer partition n = n1 + n2. Moreover, the condition is sharp for even n and nearly sharp for odd n.
5245849
On Independent Cycles in a Bipartite Graph
Abstract. Let G=(V1,V2;E) be a bipartite graph with 2k≤m=|V1|≤|V2|=n, where k is a positive integer. We show that if the number of edges of G is at least (2k−1)(n−1)+m, then G contains k vertex-disjoint cycles, unless e(G)=(2k−1)(n−1)+m and G belongs to a known class of graphs.
30994252
An extension of a theorem on cycles containing specified independent edges
We give an alternative proof of a conjecture due to Wang (J. Graph Theory 26 (1997) 105) in a stronger form. The main theorem states that for any integer k ≥ 2 if G is a graph of order n ≥ 4k - 1 and d(u) + d(υ) ≥ n + 2k - 2 for each pair of non-adjacent vertices u and υ of G, then, for any k independent edges e1,... ,ek of G, there exist k vertex-disjoint cycles C1,..., Ck in G such that (i) ei ∈ E(Ci) for all 1 ≤ i ≤ k, (ii) V(C1)∪ ... ∪V(Ck) = V(G), and (iii) #{i ≤ k||Ci| a > n - 4k + 2). It strengthens the conjecture of Wang, which was first proven by Egawa et al. (Graphs Combin. 16 (2000) 81).
207181396
BLoG: Post-Silicon bug localization in processors using bug localization graphs
Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.
2699916
Deception Detection Via Blob Motion Pattern Analysis
Deception dectection is one of the most difficult problems in affect recognition and expression research area. Recently, non-verbal methods of detecting deception have appeared to be promising. Thomas[1] presented a proof-of-concept study based on the blob analysis of some suspects' interviews and mock experiments video clips. In this paper, we present our recent research work in the direction of developing an automated deception detection system. We propose a blob motion pattern analysis approach to solve this problem.
14869090
CPR: Composable performance regression for scalable multiprocessor models
Uniprocessor simulators track resource utilization cycle by cycle to estimate performance. Multiprocessor simulators, however, must account for synchronization events that increase the cost of every cycle simulated and shared resource contention that increases the total number of cycles simulated. These effects cause multiprocessor simulation times to scale superlinearly with the number of cores. Composable performance regression (CPR) fundamentally addresses these intractable multiprocessor simulation times, estimating multiprocessor performance with a combination of uniprocessor, contention, and penalty models. The uniprocessor model predicts baseline performance of each core while the contention models predict interfering accesses from other cores. Uniprocessor and contention model outputs are composed by a penalty model to produce the final multiprocessor performance estimate. Trained with a production quality simulator, CPR is accurate with median errors of 6.63, 4.83 percent for dual-, quad-core multiprocessors. Furthermore, composable regression is scalable, requiring 0.33x the simulations required by prior regression strategies.
7692886
Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation
The performance of in-order execution Itanium/sup TM/ processors can suffer significantly due to cache misses. Two memory latency tolerance approaches can be applied for the Itanium processors. One uses an out-of-order (OOO) execution core; the other assumes multithreading support and exploits cache prefetching via speculative precomputation (SP). This paper evaluates and contrasts these two approaches. In addition, this paper assesses the effectiveness of combining the two approaches. For a select set of memory-intensive programs, an in-order SMT Itanium processor using speculative precomputation can achieve performance improvement (92%) comparable to that of an out-of-order design (87%). Applying both 000 and SP yields a total performance improvement of 141% over the baseline in-order machine. OOO tends to be effective in prefetching-for L1 misses; whereas SP is primarily good at covering L2 and L3 misses. Our analysis indicates that the two approaches can be redundant or complementary depending on the type of delinquent loads that each targets. Both approaches are effective on delinquent loads in the loop body; however only SP is effective on delinquent loads found in loop control code.
205433865
Model reference adaptive control of the output stochastic distributions for unknown linear stochastic systems
This paper presents a model reference based adaptive control approach for the control of the output probability density function for unknown linear time-invariant stochastic systems. Different from most existing models used in stochastic control, it is assumed here that the measured control input directly affects the distribution of the system output in probability sense. As such, the purpose of control is to make the shape of the probability density function of the system output as close as possible to a prespecified one. Using the weighted integration of the measurable output probability density functions, two adaptive on-line updating rules are developed which guarantee the global stability for theclosed loop adaptive control system under certain conditions. Ithas been shown, when there is no external disturbance, that the so-formed closed loop system also realizes the perfect tracking (i.e., the probability density function of the system output approaches a class of given distributions asymptotically)...