31601692
Register renaming and scheduling for dynamic execution of predicated code
To achieve higher processor performance requires greater synergy between advanced hardware features and innovative compiler techniques. Recent advancement in compilation techniques for predicated execution has provided significant opportunity in exploiting instruction level parallelism. However, little research has been done on how to efficiently execute predicated code in a dynamic microarchitecture. In this paper, we evaluate hardware optimizations for executing predicated code on a dynamically scheduled microarchitecture. We provide two novel ideas to improve the efficiency of executing predicated code. On a generic Intel Itanium processor pipeline model, we demonstrate that, with some microarchitecture enhancements, a dynamic execution processor can achieve about 16% performance improvement over an equivalent static execution processor.
8477294
Criticality-based optimizations for efficient load processing
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Previous work has shown that the criticality of instructions can be dynamically predicted with high accuracy, and that this information can be leveraged to optimize the performance of load value prediction and instruction steering for clustered architectures. In this work, we revisit the idea of criticality, but we propose several processor enhancements that can exploit criticality information and can be directly applied to modern x86 microarchitectures. For the investment of a small (less than 1KB) criticality predictor, we can make a conventional single-read-port data cache achieve the performance of an ideal dual-read-port cache, yielding an average 10% performance improvement. Our remaining techniques can reuse the predictor (i.e., no additional overhead) to further optimize other aspects of load processing (e.g., caching decisions, store-to-load forwarding, etc.), yielding an overall performance improvement of 16% over a conventional processor. Some of these techniques also allow us to decrease power and area costs for several related hardware structures.
7692886
Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation
The performance of in-order execution Itanium/sup TM/ processors can suffer significantly due to cache misses. Two memory latency tolerance approaches can be applied for the Itanium processors. One uses an out-of-order (OOO) execution core; the other assumes multithreading support and exploits cache prefetching via speculative precomputation (SP). This paper evaluates and contrasts these two approaches. In addition, this paper assesses the effectiveness of combining the two approaches. For a select set of memory-intensive programs, an in-order SMT Itanium processor using speculative precomputation can achieve performance improvement (92%) comparable to that of an out-of-order design (87%). Applying both 000 and SP yields a total performance improvement of 141% over the baseline in-order machine. OOO tends to be effective in prefetching-for L1 misses; whereas SP is primarily good at covering L2 and L3 misses. Our analysis indicates that the two approaches can be redundant or complementary depending on the type of delinquent loads that each targets. Both approaches are effective on delinquent loads in the loop body; however only SP is effective on delinquent loads found in loop control code.
13981080
Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.
62483723
Dynamic speculative precomputation
A large number of memory accesses in memory-bound applications are irregular, such as pointer dereferences, and can be effectively targeted by thread-based prefetching techniques like Speculative Precomputation. These techniques execute instructions, for example on an available SMT thread context, that have been extracted directly from the program they are trying to accelerate. Proposed techniques typically require manual user intervention to extract and optimize instruction sequences. This paper proposes Dynamic Speculative Precomputation, which performs all necessary instruction analysis, extraction, and optimization through the use of back-end instruction analysis hardware, located off the processor's critical path. For a set of memory limited benchmarks an average speedup of 14% is achieved when constructing simple p-slices, and this gain grows to 33% when making use of aggressive optimizations.
17027582
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique is Caching Address Tags, or CAT cache, for short. The CAT cache exploits locality property that exists among addresses of memory references. By keeping only a limited number of distinct tags of cached data, rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache, with only a few tag entries, performs as well as ordinary caches, while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip-area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.
43797306
On the Maximum Number of Independent Cycles in a Bipartite Graph
LetG=(V1, V2; E) be a bipartite graph with |V1|=|V2|=n?2k, wherekis a positive integer. Suppose that the minimum degree ofGis at leastk+1. We show that ifn>2k, thenGcontainskvertex-disjoint cycles. We also show that ifn=2k, thenGcontainsk?1 quadrilaterals and a path of order 4 such that all of them are vertex-disjoint. Moreover, the condition on degrees is sharp. We conjecture that whenn=2k,Gindeed containskvertex-disjoint quadrilaterals.
43643177
Adaptive Tracking Control for the Output PDFs Based on Dynamic Neural Networks
In this paper, a novel adaptive tracking control strategy is established for general non-Gaussian stochastic systems based on two-step neural network models. The objective is to control the conditional PDF of the system output to follow a given target function by using dynamic neural network models. B-spline neural networks are used to model the dynamic output probability density functions (PDFs), then the concerned problem is transferred into the tracking of given weights corresponding to the desired PDF. The dynamic neural networks with undetermined parameters are employed to identify the nonlinear relationships between the control input and the weights. To achieve control objective, an adaptive state feedback controller is given to estimate the unknown parameters and control the nonlinear dynamics.
205433865
Model reference adaptive control of the output stochastic distributions for unknown linear stochastic systems
This paper presents a model reference based adaptive control approach for the control of the output probability density function for unknown linear time-invariant stochastic systems. Different from most existing models used in stochastic control, it is assumed here that the measured control input directly affects the distribution of the system output in probability sense. As such, the purpose of control is to make the shape of the probability density function of the system output as close as possible to a prespecified one. Using the weighted integration of the measurable output probability density functions, two adaptive on-line updating rules are developed which guarantee the global stability for theclosed loop adaptive control system under certain conditions. Ithas been shown, when there is no external disturbance, that the so-formed closed loop system also realizes the perfect tracking (i.e., the probability density function of the system output approaches a class of given distributions asymptotically)...
206733269
A Fast and Robust Ellipse Detection Algorithm Based on Pseudo-random Sample Consensus
Ellipse is one of the most common features that appears in images. Over years in research, real-timing and robustness have been two very challenging problems aspects of ellipse detection. Aiming to tackle them both, we propose an ellipse detection algorithm based on pseudo-random sample consensus (PRANSAC). In PRANSAC we improve a contour-based ellipse detection algorithm (CBED), which was presented in our previous work. In addition, the parallel thinning algorithm is employed to eliminate useless feature points, which increases the time efficiency of our detection algorithm. In order to further speed up, a 3-point ellipse fitting method is introduced. In terms of robustness, a "robust candidate sequence" is proposed to improve the robustness performance of our detection algorithm. Compared with the state-of-the-art ellipse detection algorithms, experimental results based on real application images show that significant improvements in time efficiency and performance robustness of the proposed algorithm have been achieved.
781332
Minimum entropy control of nonlinear ARMA systems over a communication network
In this paper, the entropy concept has been utilized to characterize the uncertainty of the tracking error for nonlinear ARMA stochastic systems over a communication network, where time delays in the communication channels are of random nature. A recursive optimization solution has been developed. In addition, an alternative algorithm is also proposed based on the probability density function of the tracking error, which is estimated by a neural network. Finally, a simulation example is given to illustrate the efficiency and feasibility of the proposed approach.