10613404
Enhancing Network Processor Simulation Speed with Statistical Input Sampling
While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the simulation, especially in modeling chip multi-proce- ssors with multi-threading such as the network processors (NP). We have observed that for NP cycle level simulation, several days of simulation time covers only about one second of the real-world network traffic. Existing approaches to accelerating simulation are through either code analysis or execution sampling. Unfortunately, they are not applicable in speeding up NP simulations due to the small code size and the iterative nature of NP applications. We propose to sample the traffic input to the NP so that a long packet trace is represented by a much shorter one with simulation error bounded within ±3% and 95% confidence. Our method resulted one order of magnitude improvement in the NP simulation speed.
8043010
Low power network processor design using clock gating
Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multi-threading to achieve maximum parallel processing capabilities. We observed that under low incoming traffic rates, most processing elements (PEs) in NPs are nearly idle and yet still consume dynamic power. This paper develops a low power technique to reduce the activities of PEs according to the varying traffic volume. We propose to monitor the average number of idle threads in a time window, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. We show that our technique brings significant reduction in power consumption (up to 30%) of NPs with no packet loss and little impact to the overall throughput.
1926620
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network application domains. A remarkable difference with general multiprocessor task scheduling is that NPs are often programmed into a hybrid parallel and pipeline topology. In this paper, we introduce a multilevel balancing and refining algorithm for NP program mapping. We use a divide- and-conquer approach to recursively bipartition the task graph into disjoint subdomains. At each level of bipartition, the processing resources will be co-allocated so that an estimation of throughput can be derived. The bipartition continues until the code of the tasks can be fit into the instruction memory of processing elements. Then the algorithm iteratively refines the solution by migrating tasks from the bottleneck stage to other stages. The performance of our scheme is evaluated with a suite of NP benchmarks using SUIF/Machine SUIF compiler and Intel IXA Architecture Tool. The throughput improvement is significant: average throughput is increased by 20%, and the maximum is 108%.
17946266
Reverse link capacity of SIR-based power-controlled CDMA systems with antenna arrays
SUMMARY In this paper, reverse link capacity, in terms of user capacity, of a code-division multiple access (CDMA) system with both beamforming and antenna diversity under a multipath environment is analyzed and compared. Signal-tointerference ratio (SIR) based power control is assumed in the system. Antenna elements are divided into several groups to achieve antenna diversity gain. Antenna elements in a group are closely spaced to perform beamforming in order to suppress the own-cell and other-cell interference, while those groups are widely spaced to achieve the diversity gain. Based on the comparison, a most efficient use of the antenna array according to the distribution of antenna elements among the groups is obtained. Instead of using tedious iterative methods to evaluate user capacity, a simple closed-form capacity expression with respect to antenna diversity and beamforming gains, a target SIR and the CDMA processing gain is derived. Numerical results indicate significant capacity improvement with the antenna array. Copyright # 2003 John Wiley & Sons, Ltd.
7079167
Text classification without negative examples revisit
Traditionally, building a classifier requires two sets of examples: positive examples and negative examples. This paper studies the problem of building a text classifier using positive examples (P) and unlabeled examples (U). The unlabeled examples are mixed with both positive and negative examples. Since no negative example is given explicitly, the task of building a reliable text classifier becomes far more challenging. Simply treating all of the unlabeled examples as negative examples and building a classifier thereafter is undoubtedly a poor approach to tackling this problem. Generally speaking, most of the studies solved this problem by a two-step heuristic: first, extract negative examples (N) from U. Second, build a classifier based on P and N. Surprisingly, most studies did not try to extract positive examples from U. Intuitively, enlarging P by P' (positive examples extracted from U) and building a classifier thereafter should enhance the effectiveness of the classifier. Throughout our study, we find that extracting P' is very difficult. A document in U that possesses the features exhibited in P does not necessarily mean that it is a positive example, and vice versa. The very large size of and very high diversity in U also contribute to the difficulties of extracting P'. In this paper, we propose a labeling heuristic called PNLH to tackle this problem. PNLH aims at extracting high quality positive examples and negative examples from U and can be used on top of any existing classifiers. Extensive experiments based on several benchmarks are conducted. The results indicated that PNLH is highly feasible, especially in the situation where |P| is extremely small.
27420151
Recent Advances in PC-Linux Systems for Electronic Structure Computations by Optimized Compilers and Numerical Libraries
One of the most frequently used packages for electronic structure research, GAUSSIAN 98, is compiled on Linux systems with various hardware configurations, including AMD Athlon (with the "Thunderbird" core), AthlonMP, and AthlonXP (with the "Palomino" core) systems as well as the Intel Pentium 4 (with the "Willamette" core) machines. The default PGI FORTRAN compiler (pgf77) and the Intel FORTRAN compiler (ifc) are respectively employed with different architectural optimization options to compile GAUSSIAN 98 and test the performance improvement. In addition to the BLAS library included in revision A.11 of this package, the Automatically Tuned Linear Algebra Software (ATLAS) library is linked against the binary executables to improve the performance. Various Hartree-Fock, density-functional theories, and the MP2 calculations are done for benchmarking purposes. It is found that the combination of ifc with ATLAS library gives the best performance for GAUSSIAN 98 on all of these PC-Linux computers, including AMD and Intel CPUs. Even on AMD systems, the Intel FORTRAN compiler invariably produces binaries with better performance than pgf77. The enhancement provided by the ATLAS library is more significant for post-Hartree-Fock calculations. The performance on one single CPU is potentially as good as that on an Alpha 21264A workstation or an SGI supercomputer. The floating-point marks by SpecFP2000 have similar trends to the results of GAUSSIAN 98 package.
5943191
Reliability measurement: from theory to practice
The gap between theory and practice of reliability measurement in software design is discussed, and key issues that underlie reliability measurement's evolution from theory to practice are presented. A panel discussion in which reliability measurement's salient issues, basic concepts, and underlying theory are outlined is included. Reliability measurement's role in the development life cycle is also discussed.<<ETX>>
15858355
Asymptotics of Efficiency Loss in Competitive Market Mechanisms
We consider the loss of efficiency in competitive market mechanisms used to allocate network resources. We model large heterogeneous populations of users assuming that each user has a random utility function. We show that if the utility functions are bounded, the competitive equilibrium will be nearly as efficient as the social optimum with high probability as the number of users increases. This is the case for inelastic capacity as well as elastic capacity, under some standard assumptions. This result extends to a network setup where sources and destinations are picked at random. If, however, the utility functions are not bounded, then the loss of efficiency does not converge to zero. Collaborating simulations are also presented.