32110636
Power-delay product minimization in high-performance 64-bit carry-select adders
This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.
42724595
Standard-cell-based design methodology for high-performance support chips
We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. Custom library elements are used wherever needed for performance reasons. Using this approach, a density has been achieved that is comparable to those of contemporary custom designs, combined with very attractive turnaround times.
18337709
Synergetic Tool Environments
In the field of parallel programming we notice a considerable lack of efficient on-line tools for debugging, performance analysis etc. This is due to the fact that the construction of those tools must be based on a complicated software infrastructure. In the case of such software being available tools from different vendors are almost always incompatible as they use proprietary implementations for it. We will demonstrate in this paper that only a common infrastructure will ease the construction of on-line tools and that it is a necessary precondition for eventually having interoperable tools. Interoperable tools form the basis for synergetic tool environments and yield an added value over just integrated environments.
280666
RAxML-OMP: An Efficient Program for Phylogenetic Inference on SMPs
Inference of phylogenetic trees comprising hundreds or even thousands of organisms based on the Maximum Likelihood (ML) method is computationally extremely intensive. In order to accelerate computations we implemented RAxML-OMP, an efficient OpenMP-parallelization for Symmetric Multi-Processing machines (SMPs) based on the sequential program RAxML-V (Randomized Axelerated Maximum Likelihood). RAxML-V is a program for inference of evolutionary trees based upon the ML method and incorporates several advanced search algorithms like fast hill-climbing and simulated annealing. We assess performance of RAxML-OMP on the widely used Intel Xeon, Intel Itanium, and AMD Opteron architectures. RAxML-OMP scales particularly well on the AMD Opteron architecture and achieves even super-linear speedups for large datasets (with a length ≥ 5.000 base pairs) due to improved cache-efficiency and data locality. RAxML-OMP is freely available as open source code.
37677833
An Open Monitoring System for Parallel and Distributed Programs
The on-line monitoring interface specification OMIS provides means for developing more powerful tool environments for parallel and distributed systems. It specifies the interaction between any tool and a monitoring system which is responsible for observing and manipulating the programs' execution. By having this well defined interface it is now possible to concurrently use several tools of possibly different developers with the same program run. The research group at LRR-TUM currently designs an OMIS compliant monitoring system for PVM running on workstation clusters. Tool developers can use this implementation to attach their own on-line tools to the system.
44650935
Airport simulation using CORBA and DIS
This paper presents the SEEDS simulation environment for the evaluation of distributed traffic control systems. Starting with an overview of the general simulator architecture, performance measurements of the simulation environment carried out with a prototype for airport ground-traffic simulation are described.