6367354
Realization of Video Object Plane Decoder on On-Chip Network Architecture
System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired bus-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. In this paper, we present interconnected network topologies and analyze their performances with a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.
195605809
Designing On-Chip Network Based on Optimal Latency Criteria
A new chip design paradigm, so called Network on Chip, has been introduced based on the demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks. The Network on Chip design not only requires the good performance but also the minimization of several physical constraints such as the network latency, the used area as well as the power consumption of design. This paper analyzes the average latency of heterogeneous Network on Chip architectures in which the shortest path routing algorithm is applied. This average latency includes the queuing latency and the wire latency, and is calculated for general cases of allocating IPs onto the fixed generic switching architectures such as 2-D Mesh and Fat-Tree. With different allocation schemes of IPs, the network has different average latencies. Hence, this article presents an optimal search that adopts the Branch and Bound algorithm to find out the optimal mapping scheme to achieve the minimal network latency. This algorithm automatically map the desired IPs onto the target Network on Chip architecture with the criteria of lowest network latency. Some experiments of On Chip Multiprocessor Network application are simulated. The results show that the network latency is significantly saved with the optimized allocation scheme for the several cases of generic architectures of On Chip Multiprocessor Network application.
7707803
Realization of video object plane decoder on mesh on-chip network architecture
21559865
The Optimum Network on Chip Architectures for Video Object Plane Decoder Design
On Chip Network (OCN) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, three differently heterogenous Tree-based network topologies are proposed as the OCN architectures for Video Object Plane Decoder (VOPD). The topologies are designed in order to maximize the system throughput. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic energies of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and power consumptions.
5939692
Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design
The demand of integration of many heterogeneous semiconductor intellectual property (IP) blocks has been introducing a new chip design paradigm so called on chip network. This paradigm promisingly offers a packet switched network among IPs to reduce the main problems in the very deep sub micron technologies that arise from non-scalable global wire delay, failure to achieve global synchronization, errors due to the signal integrity, non-scalable bus based functional interconnection, etc. This paper introduces interconnected or switched network topologies and also analyze their performances in terms of communication protocol related to the issues such as routing strategy, buffer size, routing algorithm , etc. The above mentioned evaluations are done by utilizing the tool that has been widely used in the research domain of computer network design, so called NS-2.
30297846
Throughput Aware Mapping for Network on Chip Design of H.264 Decoder
Network-on-Chip (NoC) has been proposed as a new methodology for addressing the design challenges of future massly integrated system in nanoscale. In this paper, we present the queuing theory based model for router to evaluate the performance of NoC in terms of drop probability, throughput and energy consumption. Then we apply the linear programming to optimize the allocation of the heterogeneously functional blocks (IPs) onto the given heterogeneous NoC architecture so as to obtain the maximum throughput as well as to optimize the energy dissipation of whole system. Finally, the three differently heterogenous Tree-based network topologies are proposed as the NoC architectures for the study case of H.264 Decoder. This paper also evaluates the proposed topologies by comparing them to other conventional topologies such as 2-D Mesh and Fat-Tree with respects to throughput, power consumption and size. We use the power modelling tool, known as Orion model to calculate the static powers, areas, and dynamic powers of three topologies. The experiment results show that our Tree-based topologies offer similar throughputs as Fat-Tree does and much higher throughputs compared to 2-D Mesh while use less chip areas and energy consumptions.
38939818
Link-disjoint embedding of complete binary trees in meshes
9824119
Loopback recovery from neighboring double-link failures in WDM mesh networks
Traditional survivable network design assumes that at any time at most a single link or node fails. In optical networks, a single point of failure may lead to the failure of multiple links. In this paper, we consider the design of an optical network that can survive the failures of any two neighboring links. We present a loopback recovery method that requires the computation of backup paths for each link. An optimal algorithm for computing the backup paths is presented. Numerical results comparing the performance of our algorithm with other loopback approaches indicate that a slight increase in capacity can achieve 100% protection under this failure model.
18455665
Restoration in IP over WDM optical networks
An important requirement in any high speed network is to ensure the network's survivability, i.e., the ability to provide reroutes of ongoing connections after the failure of network components. We consider the problem of embedding an IP layer topology in the WDM transport network layer with the objective of achieving the network's survivability in the IP layer. Specifically, we consider the problem of embedding an arbitrary IP layer topology in a WDM wavelength-routing ring network such that the IP topology remains connected under the presence of the failure of any link in the WDM layer.
7484493
Dual power management for network connectivity in wireless sensor networks
Summary form only given. As the energy consumption in wireless sensor nodes is dominated by the radio transmission circuitry, the network configuration must be designed to minimize the power consumption by transmission radios. Sensor nodes are generally equipped with short-range radios that require low power consumption. But the current technology allows each node to adjust its transmission power. We consider the dual power radios in which the radio of each node can be assigned high-or low-power during the network initializing stage. Our primary goal in such an assignment is to minimize the overall power consumption by radios to maximize the network lifetime while maintaining the full network connectivity, the most fundamental network functionality. Using a graph-theoretic approach, we formulate the problem as a "minimum subgraph" problem, show its NP-completeness, establish upper and lower bounds on the optimum solution, and present a near-optimal heuristic algorithm and simulation results.
16215403
Medial axis transform and offset curves by Minkowski Pythagorean hodograph curves
Abstract We present a new approach to medial axis transform and offset curve computation. Our algorithm is based on the domain decomposition scheme which reduces a complicated domain into a union of simple subdomains each of which is very easy to handle. This domain decomposition approach gives rise to the decomposition of the corresponding medial axis transform which is regarded as a geometric graph in the three dimensional Minkowski space R 2,1 . Each simple piece of the domain, called the fundamental domain, corresponds to a space-like curve in R 2,1 . Then using the new spline, called the Minkowski Pythagorean hodograph curve which was recently introduced, we approximate within the desired degree of accuracy the curve part of the medial axis transform with a G 1 cubic spline of Minkowski Pythagorean hodograph. This curve has the property of enabling us to write all offset curves as rational curves. Further, this Minkowski Pythagorean hodograph curve representation together with the domain decomposition lemma makes the trimming process essentially trivial. We give a simple procedure to obtain the trimmed offset curves in terms of the radius function of the MPH curve representing the medial axis transform.