22681240
Distribution function tracking filter design using hybrid characteristic functions
A new tracking filtering algorithm for a class of multivariate dynamic stochastic systems is presented. The system is expressed by a set of time-varying discrete systems with non-Gaussian stochastic input and nonlinear output. A new concept, such as hybrid characteristic function, is introduced to describe the stochastic nature of the dynamic conditional estimation errors, where the key idea is to ensure the distribution of the conditional estimation error to follow a target distribution. For this purpose, the relationships between the hybrid characteristic functions of the multivariate stochastic input and the outputs, and the properties of the hybrid characteristic function, are established. A new performance index of the tracking filter is then constructed based on the form of the hybrid characteristic function of the conditional estimation error. An analytical solution, which guarantees the filter gain matrix to be an optimal one, is then obtained. A simulation case study is included to show the effectiveness of the proposed algorithm, and encouraging results have been obtained.
8670131
An Intelligent Mill Load Switching Control of the Pulverizing System for an Alumina Sintering Process
This paper proposes an intelligent switching control strategy for the pulverizing system for an alumina sintering process. The control strategy consists of a coordinating controller, a proportional-integral (PI) controller, a rule-based reasoning controller and a switching mechanism. The practical application to a pulverizing system in an alumina sintering process has shown that when the hot air temperature is low and varies frequently, this control strategy ensures that the mill load and the temperature of the mill outlet are both within their required ranges, and also controls the mill load at the level corresponding to the maximum mill output. Moreover, it has been observed that the proposed control strategy can avoid the fault operating condition and effectively reduce the unit energy consumption.
7971167
Robust minimum entropy tracking control with guaranteed stability for nonlinear stochastic systems under modeling errors
In this paper, robust minimum entropy tracking control problem is considered for nonlinear stochastic systems. The controlled systems are described by nonlinear non-Gaussian difference equations with the un-modeled uncertainty and modeling error, as well as time delays. Entropy is adopted to characterize the uncertainty of the tracking error. The nonlinear multi-step-ahead predictive cost function is used and the relationship between the probability density functions of the input and the tracking error via the uncertain mapping is established. With these formulations, the cost function can be bounded as a nonlinear functional of the control input and the known bounds of the errors. Explicit design algorithms are presented for the robust suboptimal controller and further for the stabilization controllers. The Renyi's entropy has also been used to simplify the cost function. Simulations are given to demonstrate the effectiveness of the proposed control algorithm.
27662001
MIMO Probability Density Function Control Using Simple LOG-MLP Neural Networks
This paper presents a new model for the control of multivariable output probability density function (PDF). Firstly, a Multi-Layer Perceptron (MLP) neural network is adopted to approximate the static output PDF of the MIMO systems. Nonlinear principal component analysis (NLPCA) is then used to reduce the order of the obtained static neural network model and the dynamics of the system is considered based on the lower-order model. After this, an integrated solution is provided to set up the system with lower-order dynamics for the purpose of stochastic distribution control. The controller design is then presented in detail. Finally, a simulation example is given to demonstrate the effectiveness of the method and encouraging results have been obtained.
20772220
Descriptor observer approaches for multivariable systems with measurement noises and application in fault detection and diagnosis
In this paper, new descriptor observer design approaches are presented for multivariable systems with measurement noises. If the system matrix is stable, the proposed modified proportional and derivative observer technique allows us not only to decouple the measurement noise in any forms completely, but also obtain accurate estimations of both system states and measurement noises. If the system is detectable and the noise is bounded, it has been shown that two design parameters can provide more degrees of freedom. In this context, the derivative gain parameter is chosen to reduce the amplification of the noise, and the proportional gain is then selected to guarantee the stability of the error dynamics. For systems with both measurement output noises and input disturbances, a modified proportional, derivative and integral observer is constructed to asymptotically estimate states, input disturbances, and output noises at the same time. The applications of the proposed observers for systems with actuator and sensor faults are also discussed. Numerical examples are given to illustrate the design procedures, and the simulation results show the satisfactory tracking performance.
781332
Minimum entropy control of nonlinear ARMA systems over a communication network
In this paper, the entropy concept has been utilized to characterize the uncertainty of the tracking error for nonlinear ARMA stochastic systems over a communication network, where time delays in the communication channels are of random nature. A recursive optimization solution has been developed. In addition, an alternative algorithm is also proposed based on the probability density function of the tracking error, which is estimated by a neural network. Finally, a simulation example is given to illustrate the efficiency and feasibility of the proposed approach.
26838865
Speculative precomputation: long-range prefetching of delinquent loads
This paper explores Speculative Precomputation, a technique that uses idle thread contexts in a multithreaded architecture to improve performance of single-threaded applications. It attacks program stalls from data cache misses by pre-computing future memory accesses in available thread contexts, and prefetching these data. This technique is evaluated by simulating the performance of a research processor based on the Itanium/sup TM/ ISA supporting Simultaneous Multithreading. Two primary forms of Speculative Precomputation are evaluated. If only the non-speculative thread spawns speculative threads, performance gains of up to 30% are achieved when assuming ideal hardware. However, this speedup drops considerably with more realistic hardware assumptions. Permitting speculative threads to directly spawn additional speculative threads reduces the overhead associated with spawning threads and enables significantly more aggressive speculation, overcoming this limitation. Even with realistic costs for spawning threads, speedups as high as 169% are achieved, with an average speedup of 76%.
661328
Physical experimentation with prefetching helper threads on Intel's hyper-threaded processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the ever-increasing memory latency. A number of pre-execution techniques based on hardware, compiler, or both have been proposed and studied extensively by researchers. They report promising results on simulators that model a simultaneous multithreading (SMT) processor. We apply the helper threading idea on a real multithreaded machine, i.e., Intel Pentium 4 processor with hyper-threading technology, and show that indeed it can provide wall-clock speedup on real silicon. To achieve further performance improvements via helper threads, we investigate three helper threading scenarios that are driven by automated compiler infrastructure, and identify several key challenges and opportunities for novel hardware and software optimizations. Our study shows a program behavior changes dynamically during execution. In addition, the organizations of certain critical hardware structures in the hyper-threaded processors are either shared or partitioned in the multithreading mode and thus, the tradeoffs regarding resource contention can be intricate. Therefore, it is essential to judiciously invoke helper threads by adapting to the dynamic program behavior so that we can alleviate potential performance degradation due to resource contention. Moreover, since adapting to the dynamic behavior requires frequent thread synchronization, having light-weight thread synchronization mechanisms is important.
6292073
Real-time pose estimation for outdoor mobile robots using range data
Pose estimation is a key issue in mobile robots and important to moving object tracking. In this paper, we present a tangent based hybrid pose estimation algorithm with real-time performance using range data from laser radar, which consists of Iterative Tangent weighted Closest Point (ITCP) and Hough transform based Tangent Angle Histogram (HTAH) algorithms to overcome problems with past methods, such as local minimum, aperture-like, and high computation problems. The algorithm has been tested on both synthetic and real range data in outdoor environments. Experimental results demonstrate its high accuracy, low computation, wide applicability and high robustness to aperture-like problems, occlusion and noise.
12425936
CAT—caching address tags: a technique for reducing area cost of on-chip caches
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memory of microprocessors. The main idea of the technique Caching Address Tags, or CAT cache for short. The CAT cache exploits locality property that exists among addresses of memory references for the purpose of minimizing chip area-cost of address tags. By keeping only a limited number of distinct tags of cached data rather than having as many tags as cache lines, the CAT cache can reduce the cost of implementing tag memory by an order of magnitude without noticeable performance difference from ordinary caches. Therefore, CAT represents another level of caching for cache memories. Simulation experiments are carried out to evaluate performance of CAT cache as compared to existing caches. Performance results of SPEC92 programs show that the CAT cache with only a few tag entries performs as well as ordinary caches while chip-area saving is significant. Such area saving will increase as the address space of a processor increases. By allocating the saved chip area for larger cache capacity, or more powerful functional units, CAT is expected to have a great impact on overall system performance.
13981080
Pangaea: A tightly-coupled IA32 heterogeneous chip multiprocessor
Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multi-cores, extending the current state-of-the-art CPU-GPU integration that physically “fuses” existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3D-specific graphics processing is used to build more general-purpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.