A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution methodology for ASIC design. From the oorplan and the estimated power consumption, the power network size is determined at an early design stage. Next, without detailed gate-level netlist, clock interconnect sizing, the number and strength of clock bu ers are planned for balanced clock distribution. This early planning methodology at the full-chip level enables us to x the global interconnect issues before the detailed layout composition is started.