Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) al gorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.