Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
Write-through policy employed in many high-performance microprocessors provides good tolerance to soft errors in cache systems. However, it also incurs large energy overhead due to the increased accesses to caches at the lower level (e.g., the L2 cache) during write operations. In this paper, we propose a new cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through cache systems. By maintaining the way tags of the L2 cache in the L1 cache during read operations, the proposed technique enables the L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. This leads to significant energy reduction. Simulation results on the SPEC CPU2000 benchmarks demonstrate that the proposed technique achieves 65.4% energy savings on average with about 0.02% area overhead and no performance degradation.