A Method for Phase Noise Analysis of RF Circuits
In this paper we present a method for analysis of phase noise in logic circuits. This method allows the design and verification of phase noise critical circuits using a digital toolchain, significantly reducing the design time and effort compared to the traditional approach using analog tools such as SPICE simulation. It is based on a set of pre-characterized standard cells and the generated phase noise is estimated using a lookup table approach. Comparison of the estimation results with back-annotated analog simulations in 28 nm CMOS technology show that the error of the estimation is within 7.2 % of the actual phase noise, and the runtime is reduced by three orders of magnitude.