Abstracting the hardware/software boundary through a standard system support layer and architecture
Reconfigurable computing is often lauded as having the potential to bridge the performance gap between computational needs and computational resources. Although numerous successes exist, difficulties persist bridging the CPU/FPGA boundary due to relegating hardware and software systems as separate and inconsistent computational models. Alternatively, the work presented in this thesis proposes using parallel programming models to abstract the CPU/FPGA boundary. Computational tasks would exist either as traditional CPU bound threads or as custom hardware threads running within the FPGA. 
Achieving an abstract parallel programming model that spans the hardware/software boundary depends on: extending an existing software parallel programming model into hardware, abstracting communication between hardware and software tasks, and providing equivalent high-level language constructs for hardware tasks. This thesis demonstrates that a shared memory multi-threaded programming model with high-level language semantics may be extended to hardware, consequently abstracting the hardware/software boundary. 
The research for this thesis was conducted in three phases, and used the KU-developed Hybridthread Computational Model as its base operating system and platform. The first phase extended the semantics of a running thread to a new, independent and standard hardware system support layer known as the Hardware Thread Interface (HWTI). In this phase hardware threads are given a standard interface providing communication between the hardware thread and system. The second phase of the research extended and augmented the initial design to support a meaningful abstraction. Mechanisms in this phase include globally distributed local memory, a standard function call stack including support for recursion, high level language semantics, and a remote procedure call model. The third phase evaluated the HWTI by comparing the semantic and implementation differences between hardware and software threads, by using an adapted POSIX conformance and stress test-suite, and by demonstrating that well-known algorithms may be translated and ran as hardware threads using the HWTI. 
This thesis concludes that parallel programming models can abstract the hardware/software boundary. Creating a meaningful abstraction depends both on migrating the communication and synchronization policies to hardware, but also providing high level language semantics to each computational tasks.