In many multimedia and digital signal processing systems, fixed-width multipliers are used where a fixed format is desirable and a tolerable level of loss in accuracy is permitted. This paper proposes the design of a low error fixed-width radix-8 Booth multiplier which produces an n-bit product with two n-bit inputs. The truncation of the 2n product bits to n bits is achieved by removing about half the adder cells that are required to add the partial products. However, in order to keep the truncation error to a minimum, error compensation biases are obtained and applied to the inputs of the retained adder cells. In this proposed technique, the number of partial products is reduced to n/3 and also the number of adder cells is reduced by 50% compared with the full-width multiplier with an additional overhead of one full adder for compensation biasing. Simulation results reveal that a significant amount of error reduction is achieved with this technique. Standard EDA design environment using 180nm technology has been employed. Validation has further been made in comparison against the modified Booth fixed-width multiplier architecture. © 2014 IEEE.