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Intel's i960 (or 80960) was a RISC-based microprocessor design that became quite popular during the early 1990s as an embedded microcontroller, for some time likely the best-selling CPU in that field, pushing the AMD 29000 from that spot. In spite of its success, Intel formally dropped i960 marketing in the late 1990s as a side effect of a lawsuit with DEC, in which Intel received the rights to produce the StrongARM CPU.
The i960 design was started as a response to the failure of Intel's i432 design of the early 1980s. The i432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory -- such as Ada and Lisp -- in hardware. Because of its instruction-set complexity, its multi-chip implementation, and other design flaws, the i432 was very slow in comparison to other processors of its time.
In 1984 Intel and Siemens started a joint project, ultimately called BiiN, to create a high-end fault-tolerant object-oriented computer system programmed entirely in Ada. Many of the original i432 team members joined this project, though a new lead architect was brought in from IBM, Glenford Myers. The intended market for the BiiN systems were high-reliability computer users such as banks, industrial systems and nuclear power plants, and the protected-memory concepts from the i432 influenced the design of the BiiN system.
To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, and the memory subsystem was made 33-bits wide -- for a 32-bit word and a "tag" bit to indicate protected memory. In many other ways the i960 followed the original Berkeley RISC design, notably in its use of register windows, an implementation-specific number of caches for the per-subroutine registers, allowing for fast routine calls. The competing Stanford University design, commercialized as MIPS did not use this system, relying on the compiler to generate optimal subroutine call and return code instead. Unlike the i386, but in common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation. The i960 architecture also anticipated a superscalar implementation, with instructions being simultaneously dispatched to more than one unit within the processor.
The first 960 processors "taped-out" in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986. The BiiN effort eventually failed, due to market forces, and the 960MC was left without a use. Myers attempted to save the design by outlining several subsets of the full capability architecture created for the BiiN system. Myers tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and i386 (which "taped-out the same month as the first 960), as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs's for use in the NeXT system. Competition within and outside of Intel came not only from the i386 camp, but also from the i860 processor, yet another RISC processor design emerging within Intel at the time.
Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems. The protected-memory architecture was considered proprietary to BiiN and wasn't mentioned in the product literature, leading many to wonder why the i960MC was so large and had so many pins labeled "no connect". A version of the RISC core without memory management or an FPU became the i960KA, and the RISC core with the FPU became the i960KB. The versions were, however, all identical internally -- only the labelling was different.
The "full" 960MC was never released for the non-military market, but the i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations. which removed the complex memory sub-system. The first pure RISC implementation was the i960CA, which used a newly-designed superscalar RISC core and added an unusual addressable on-chip cache. The i960CA is widely considered to have been the first single-chip superscalar RISC implementation. The C-series only included one ALU, but could dispatch an arithmetic instruction, a memory reference, and a branch instruction at the same time. Later, the i960CF included a floating-point unit, but continued to omit an MMU.
Intel attempted to bolster the i960 in the I/O device controller market with the I2O standard, but this had little success and the design work was eventually ended. By the mid-90's its price/performance ratio had fallen behind competing chips of more recent design, and Intel never produced a reduced power-consumption version that could be used in battery-powered systems.
In 1990 the i960 team was redirected to be the "second team" working in parallel on future i386 implementations -- specifically the P6 processor, which later became the Pentium Pro. The i960 project was sent to another, smaller development team, essentially ensuring its ultimate demise.
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