LCHC-DFT: A Low-Cost High-Coverage Design-for-Testability Technique to Detect Hard-to-Detect Faults in STT-MRAMs in the Presence of Process Variations

This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on introducing a voltage mismatch in the sense amplifier (SA). This mismatch along with the defects in the cell may bias the SA, leading to an incorrect read output which in turn make the HtD faults detectable. The efficacy of the proposed scheme is evaluated by calculating its detection capability in the presence of resistive defects. Evaluation results obtained for a 20nm STT-MRAM memory design show that the proposed scheme provides HtD fault coverage of 81.8% and 86.5%, on average, for intra-cell and inter-cell defects, respectively, with a negligible area overhead (1.1% for a 2Kbit array). In comparison with conventional March tests, which only detect easy-to-detect (EtD) faults, the proposed DFT technique covers both HtD and EtD faults with a faster approach, namely by using a single read operation. Furthermore, to guarantee that the cells affected by HtD faults trigger an incorrect read output under process variation (PV), a timing strategy based on modifying the control unit of the proposed DFT is suggested. The strategy controls the stress introduced by the DFT unit by altering the timing of DFT control signals. The timing alteration enables the detection of HtD faults in the devices with higher deviations from the nominal one due to PV, avoiding yield loss or test escapes.