A Discrete-Time Framework for Designing Stable Digital V$^{2}$ Controllers for the Buck Converter

V<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> control architecture is popular due to its simple compensation and fast load transient response. The stability margin of an analog V<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> controlled buck converter improves as the input voltage or capacitor effective-series resistance (ESR) increases. However, due to voltage-loop sampling, stability margin of a digital V<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> controlled buck converter degrades as the input voltage or capacitor ESR increases. Intuitively, it can be said that this happens due to sampling as sampling eliminates the ESR ripple from the output voltage. However, to get more clear insight and to propose a stabilizing solution, this article proposes an approximate discrete-time model-based framework. Analysis shows that the stability boundary of the controller's gain depends on the input and output voltages, and ESR. The stability boundary of the controller's gain is enhanced using an additional ramp compensation. Furthermore, a discrete-time small-signal model is developed to assess the slow-scale behavior of the buck converter. The model demonstrates an existence of complex conjugate poles with a low value of ESR. An analytical expression of critical value of ESR to keep the poles on the real axis is presented. To improve the load transient performance with a low ESR, a lag-lead compensator design technique is proposed. The proposed controller is realized in an FPGA device. Effectiveness of the proposed controller and accuracy of the analysis are validated experimentally.