Investigation of Staggered PWM Scheme for AC Common Mode Current Minimization in SiC-Based Three-Phase Inverters

The advent of SiC devices which results in lower rise times and steep <inline-formula> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> at the inverter terminal can compromise the common mode (CM)-conducted emissions’ compliance, motor peak ac -CM currents, and leakage currents. Consequently, this results in a high ac and dc side CM filter weight. AC filters at the inverter output terminal are effective in reducing the slew rate of inverter voltage thereby reducing the peak CM current. However, a special case with high <inline-formula> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> arising from low duty cycles is found to increase the peak ac-CM current significantly. Reduced CM voltage (CMV) schemes are popular pulsewidth modulation (PWM) methods to minimize the peak CMV but suffer from high <inline-formula> <tex-math notation="LaTeX">$\text{d}v/\text{d}t$ </tex-math></inline-formula> under this special case as well. In this article, a staggered PWM scheme to minimize such peak ac -CM currents for a high-speed variable frequency drive (VFD) is evaluated using a three-level SiC-based T-type inverter as a demonstrator. From the analysis, the proposed switching pattern shows benefits over conventional sinusoidal PWM (SPWM) scheme and is found to be scalable to other PWM schemes and voltage levels. Simulation and experimental results are shown to validate the performance of the proposed switching pattern.