Star Power Factor Correction Architecture

Conventional two-stage power factor correction (PFC) architecture based on a boost PFC front end and an isolated dc–dc back end is increasingly challenged by the recent trend toward higher power density and efficiency. One key reason for the challenge is the difficulty of increasing the operating frequency of the boost PFC stage. This article presents a new star PFC architecture that allows the boost PFC stage to operate efficiently at a higher frequency while maintaining the performance of the second dc–dc stage, leading to a high-power-density and high-efficiency ac–dc converter design across a universal input. The high performance of star architecture is enabled by realizing: 1) continuous-conduction-mode (CCM) operation of the boost PFC stage; and 2) full-range zero-voltage-switching (ZVS) of all active switches. In addition, the star architecture can: 1) operate at a constant frequency via a proper selection of the circuit topology and modulation method; and 2) be controlled based on simple and low-cost analog circuits. A 300-kHz, 240-W, 48-V-output, and universal-input prototype is built to verify the performance of the star architecture, showcasing high power factor, constant output voltage, 97.1 % full-load efficiency, 55.6 W/in$^{3}$ power density by box volume.