VLSI Implementation of Integrated Massive MIMO Systems (IMMS) for N-point FFT/IFFT Processor

The 5G technologies and OFDM introduce a substantial element of latency in the baseband Massive MIMO system. To declaim the low delay demand of multiple input and multiple outputs, a Fast Fourier Transform (FFT) and also consequent implementation was proposed. The main idea of this proposed system is to utilize the VLSI chip routing technology and reduce computations, processing time, and low latency. This proposed system is to reduce the number of computational complexities in the downlink and reorder the uplink. In OFDM implementation, the chip area of FFTs and IFFTs is occupied by memories, and these memories can be extracted using registers or RAM. An efficient data programming approach for memories and butterflies has been developed using embedded VLSI technology with multiple inputs and outputs (MIMO), known as mass embedded MIMO systems. Using this proposed scheme (Integrated Massive MIMO), N point FFT/IFFT processor design achieves a better throughput and lowest latency than for single-input pipelined FFT or IFFT architectures. In an N-point FFT/IFFT, the introduced scheme using VLSI Technology leads to more reduction in the latency. This N-point FFT/IFFT implementation is named “Integrated Massive MIMO Systems” (IMMS).