Multi-level compiler concept for high-level synthesis

Modern VLSI (Very-Large-Scale Integration) integrated circuits contain several billion transistors. Systems of this complexity are very difficult to design. Manually designing each transistor at the level of logic gates is beyond the skill of the expert team. Manual verification of the chip design is also beyond the capabilities of even engineering teams. With the increasing complexity of electronic systems, there has been a need to automate both the design and verification stages at more abstract levels. This paper describes concept of multi-level compiler which convert algorithm described in Python language to FPGA bitstream. Compiler transforms automatically high-level description (Python) to low level (bitstream) on different levels based on configuration files. Testing is also done automatically on several levels of abstraction. Process automation enable to reduce designing and testing time. The article propose VHDL Microinstruction compiler, test tools with examples of its use.