An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation

We present a calibration technique to correct the dominant dynamic tracking nonlinearity of CMOS sample-and-hold (S/H) circuits for IF-sampling applications. The error model, derived from the asymmetrical drain/source drive of a clock-bootstrapped switch, is exclusively dependent on the S/H output voltage and its slope. A simple analog high-pass filter (HPF) is used to extract the input slope voltage slope, obviating computationally intensive digital interpolation filters often employed in such applications. A prototype S/H chip fabricated in a 65-nm CMOS process measures an SFDR of ~100 dB for an fin = 300 MHz and of >85 dB for an fin = 500 MHz.