Design and Validation of the Parallel Enhanced Commutation Integrated Nested Multilevel Inverter Topology

In this article, a promising design of power electronics in the field of battery electric vehicles is proposed. The presented parallel enhanced commutation integrated nested multilevel inverter is a symmetrical cascaded multilevel inverter characterized by a minimal number of semiconductor switches compared to its range of functions. In addition to regular four-quadrant operation, the topology is able to reconfigure individual battery cells between serial and parallel interconnection to minimize the internal resistance of the reconfigurable battery system during operation. In particular, by separately considering the internal resistance of the power electronics and the variable internal resistance of the reconfigurable battery, a minimum overall internal resistance is achieved. After a detailed review of related modern topologies, the topology’s inherent structural advantages are presented. Functional spectrum, internal resistance, and efficiency behavior are compared with related topologies frequently studied in the literature. Measurements on a 17-level three-phase prototype show the function and performance of the proposed structure in terms of functional spectrum, low total harmonic distortion, and efficiency. It turns out that the parallel enhanced commutation integrated nested multilevel inverter is a competitive topology that should be investigated further.