Design and Performance of High Voltage Chip-Level Series-Connected SiC MOSFET Module

In medium voltage (MV) and high voltage (HV) applications, HV SiC mosfet with a single chip competes with series-connected low voltage (LV) SiC mosfet. The cost of the former is high due to immature process, and the parasitic inductance of the latter is large due to series-connected devices. In this article, a novel chip-level series-connected SiC mosfet module based on planar packaging is proposed to compromise cost and parasitic inductance. Several LV chips are connected in series through metal layers, and then packaged as a whole. Compared with HV module with a single chip, the proposed module has significant advantages in cost. Considering the effects of the buffer layer and direct bonded copper on the parasitic inductance, junction temperature, thermal stress, and electric field, electro-thermo-mechanical simulation is conducted to optimize the structure. Compared with existing series-connected structures, the parasitic inductance of the proposed module is reduced by at least 50.15%. Finally, 6.5 kV chip-level series-connected module with six 1.2 kV SiC mosfet is fabricated and tested. The results show the performance of the proposed module is comparable with that of HV module with a single chip, which means that the application of the proposed module in MV and HV conditions is promising.