Layout-Dominated Dynamic Current Balancing Analysis of Multichip SiC Power Modules Based on Coupled Parasitic Network Model

Multichip silicon carbide (SiC) power modules with Kelvin-source connections are commonly used in applications requiring large capacity. As a result of the parasitic effect induced by the interconnections in module packaging, the dynamic current mismatch among paralleled dies limits the available capacity of power modules. This article presents a general analysis on the mechanism of layout-dominated dynamic current balancing in multichip SiC power modules, utilizing a coupled parasitic network model. Focusing on the interrelation of parasitic parameters in the power module, a coupled parasitic network model is developed specially for switching transients, and the dynamic current balancing equations are derived. For the multichip power modules with two different layouts, the parasitic parameters pertaining to the proposed model are extracted by the finite-element analysis (FEA). The acquired parasitic parameters considering magnetic coupling are utilized to calculate and verify the dynamic current balancing equations. Moreover, based on these parasitic parameters, the electromagnetic coupling simulation is performed to evaluate the dynamic current sharing. Furthermore, for the validation of the proposed model and equations, experiments are conducted with the fabricated power module prototypes.