Performance Analysis of a Multimodule Staircase (MM-STC)-Type Multilevel Inverter With Reduced Component Count and Improved Efficiency

This article presents a detailed analysis of a reduced component staircase (STC)-type nine-level inverter designed with only two dc sources. Many of the reduced switch multilevel inverters proposed are designed with more voltage sources that are not utilized properly and have more conducting switches. The proposed MLI has a much lesser number of conducting switches; hence, it has higher efficiency. The topology can be extended to a generalized multimodule staircase (MM-STC) inverter that is designed with fewer dc sources and utilizes them properly without H-bridge. The generalized equations of the proposed inverter parameters are derived to find their optimal performances. Furthermore, an optimal MM-STC inverter configuration is derived from the proposed generalized topology to lower the inverter total standing voltage (TSV). An in-depth analysis and comparative studies are presented to prove its superiority over the existing MLIs of similar kinds. An experimental prototype of the proposed nine-level and the optimal 81-level inverter is developed in the laboratory, and the nearest level control (NLC)-based switching scheme is implemented for them using a DS1103-based digital controller. Finally, experimental results corresponding to the different modulation indices are presented to verify the simulation results.