Introduction to Special Section on FPGA 2021

Field-programmable gate arrays (FPGAs) provide a unique combination of programmability, efficiency, and flexibility, which has led to renewed interest in this technology. Key factors that have driven growth include machine learning (ML) as a target application, improvements in device density through heterogeneous packaging technologies, and increasing use of highlevel synthesis (HLS) tools to improve design productivity. This special section comprises extended versions of four papers presented at the 2021 ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2021). The first two papers offer insights on designing efficient accelerators and efficiently utilizing memory systems in modern FPGAs, particularly high bandwidth memory (HBM). Lu et al.’s “Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking” identifies the factors that impact memory bandwidth in accelerators, provides HLS-based microbenchmarks to quantify different memory systems, and presents several case studies. Chen et al.’s “ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS” presents a gather-apply-scatter model to abstract various graph algorithms, facilitating the generation of parallel and memory-efficient accelerators for a range of applications. The tools developed in both articles were designed to be accessible for non-FPGA experts and provide open-source implementations. The remaining two papers focus on the optimization of FPGA architectures for ML applications. Langhammer et al.’s “Stratix 10 NX Architecture” presents a commercially-available architecture optimized for low-precision tensor operations common in ML implementations, based on their AI Tensor Block. This block integrates 30× INT8 or 60× INT4 multipliers with support for wider data types through cascading and additions/accumulations in INT32 or FP32. Arora et al.’s “Tensor Slices: FPGA Building Blocks for the Deep Learning Era” takes a different approach to tensor acceleration, proposing a systolic array supporting common precisions, including INT8, INT16, FP16, and BF16. The two studies demonstrated considerable improvements in throughput and power efficiency as a direct result of the architectural changes. Finally, I would like to thank Lesley Shannon (General Chair) and Michael Adler (Program Chair) for their organization of FPGA 2021; Martin Herbordt, Stephen Neuendorffer, Wei Zhang, and Jing Li for their help as associate editors for this special section; and Megan Shuler, Jeff Goeders, and Deming Chen for their continued hard work and support of TRETS.