On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH state write, but also depletion charge for low-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH state programming, though with lower efficiency; and 3) during the low/high-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low-<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.