Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces

High-speed designs today have multiple high-speed interfaces, and these interfaces have different impedance requirements in the same system. For example: PCIe interface is designed for 85 ohms whereas Gigabit ethernet is designed for 100 ohms. Sometimes due to stack-up cross-sectional restrictions and fixed dielectric constant of the material, it is not easy to meet all characteristic impedance requirements in the design. Design trade-off needs to be performed to analyze which interface is sensitive to impedance variations. With signal speeds going above 100 Gbps, pulse amplitude modulation-4 (PAM4) has become more common and PAM4 signaling is more sensitive to impedance variations due to low signal-to-noise ratio (SNR).In this paper, the impact of channel impedance on 100 Gbps ethernet (802.3ck) interface is analyzed using time-domain and frequency domain analysis. Channel operating margin (COM) analysis is performed for various channel impedances on an 802.3ck-CR topology. It Is found that huge impedance mismatch between the trace breakout and channel impacts channel performance adversely.