Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques

This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.