Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM

Electromigration (EM) has been known as a reliability threatening factor for back-end-of-the-line interconnects. Spin-transfer torque magnetic RAM (STT-MRAM) is an emerging nonvolatile memory that has gained a lot of attention in recent years. However, relatively large operational current magnitude is a challenge for this technology, and hence, EM can be a potential reliability concern, even for the signal lines of this memory. A workload-aware EM modeling needs to capture time-dependent current density in the memory signal lines and to be able to predict the effect of the EM phenomenon on the interconnect for its entire lifetime. In this work, we present methods to effectively model the workload-dependent EM-induced meantime to failure (MTTF) in typical STT-MRAM arrays under a variety of realistic workloads. This allows performing the design-space exploration to co-optimize reliability and other design metrics.