A Low-Cost Novel Structure for Paralleled SiC JFET/Si MOSFET Cascodes to Balance Turn-on Current and Junction Temperature

SiC JFET/Si <sc>mosfet</sc> Cascodes (SSCs) are promising because of their small <sc>on</sc>-resistance and fast switching speed. Parallel operation of multiple SSCs is popular for high-current applications. However, the practical layout can hardly be absolutely symmetric. The mismatches from layout will cause turn-<sc>on</sc> current imbalance among paralleled SSCs. The maximum current stress will be aggravated for some SSCs. Besides, unbalanced current can lead to uneven losses. Then, the junction temperature difference (Δ<italic>T</italic><sub>j</sub>) between paralleled SSCs occurs. The maximum junction temperature (<italic>T</italic><sub>jmax</sub>) among paralleled SSCs increases accordingly. To address the issue, a low-cost and novel structure is proposed to promote turn-<sc>on</sc> current sharing for paralleled SSCs. With aid of the structure, the immunity of turn-<sc>on</sc> current sharing performance to an asymmetric layout can be greatly improved. The mismatched turn-<sc>on</sc> current and losses can be well mitigated. Δ<italic>T</italic><sub>j</sub> and <italic>T</italic><sub>jmax</sub> are suppressed at the same time. The proposed structure is suitable for both the discrete SSCs and bare-die SSCs. In this structure, only some bridging branches are introduced so it takes almost no extra cost. Two prototypes are fabricated with the discrete SSCs and bare-die SSCs, respectively. Double-pulse test and continuous operation are conducted to validate the advantages of the proposed structure.