Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module

In this paper, we design and analyze the hierarchical power distribution network (PDN) for full wafer scale chip (FWSC) module. With its high bandwidth and low latency, FWSC has been considered a promising solution in the artificial intelligence (AI) processor market. However, the huge size of FWSC inevitably leads to long current paths and high impedance that consequently cause large IR drop and power/ground noise. In an effort to overcome these issues, the hierarchical PDN of FWSC module is designed in a 3D structure that allows direct interconnection from PCB to chip to minimize the current path. Although there are several studies related to PDN design for FWSC module, they conducted limited analysis on a specific PDN only. We design the hierarchical PDN for FWSC module composed of PCB PDN, multi-array silicone rubber socket (SRS)-based PDN, multi-array through wafer via (TWV)-based PDN, and on-chip PDN. Each PDN component was modeled into equivalent circuit models. Then, we fully analyzed the overall hierarchical PDN impedance in the frequency domain.