Fabrication and characterization of silicon nano-tip memristor for low-power neuromorphic application

In this work, a memristor using Si nano-tip bottom electrode has been fabricated and evaluated. Compared with the control device fabricated in a planar structure, the invented Si nano-tip device statistically demonstrates 400 times of area shrinkage and 3 and 8 times of current reductions in the low- and high-resistance states, respectively, owing to the effects of highly confined switching area on the operations of multiple-weak-filament (MWF)-type memristor. The results reveal the validity of structural scaling on the MWF-type memristors as effective as a material approach. Moreover, the fabricated Si memristor has been evaluated as a synaptic device via pattern recognition toward neuromorphic applications in consideration of interconnect resistance. The proposed Si memristor shows substantially reduced inference power consumption by an increase in resistances and improved accuracy by 5% compared with the control device.