Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits

Approximate computing (AC) offers benefits by reducing the requirement for full accuracy, thereby reducing power consumption and area. The majority logic (ML) gate functions as the fundamental logic block of many emerging nanotechnologies. In this article, ML-based arithmetic circuits, i.e., multibit adders and multipliers, are proposed. These adders are designed to prevent the propagation of inexact carry-out signals to higher order computing parts to enhance accuracy. We implemented the proposed multiplier by using a unique partial product reduction (PPR) circuitry, which was based on the parallel approximate 6:3 compressor. Several logic implementation costs, error metrics, and layouts implemented by quantum-dot cellular automata (QCA) are analyzed to evaluate the adder designs. A significant improvement is observed over previous ML-based designs based on the experimental results. The proposed designs are further evaluated using both a neural network (NN) accelerator and image processing. A structural similarity (SSIM) value of 1 and a peak signal-to-noise ratio (PSNR) value of infinity are achieved by the proposed adder design.