Xbar-Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits

Conventional in-memory computing (IMC) architectures consist of analog memristive crossbars to accelerate matrix-vector multiplication (MVM), and digital functional units to realize nonlinear vector (NLV) operations in deep neural networks (DNNs). These designs, however, require energy-hungry signal conversion units which can dissipate more than 95% of the total power of the system. Fully-analog IMC circuits remove the need for signal converters by realizing both MVM and NLV operations in the analog domain leading to significant energy savings. However, they are more susceptible to errors caused by interconnect parasitic and noise. Here, we propose Xbar-partitioning, a practical approach to divide large IMC arrays into multiple partitions to alleviate the impacts of noise and parasitics while keeping the computation in the analog domain. The SPICE circuit simulation results for the deployment of a $400\times 120\times 84\times 10$ DNN model on various fully-analog IMC architectures with five different 2-terminal and 3-terminal resistive devices, six different bitcell layouts, and four different partitioning schemes show that the highest accuracy of 98.08% can be obtained for a design using phase-change memory (PCM) devices and 1T-1R bitcell with 13, 4, and 3 horizontal partitions, and 4, 3, and 1 vertical partition for the first, second, and third layers of the DNN, respectively. Finally, we provide a signal-to-noise ratio (SNR) analysis which shows that the IMC architectures can be made more noise-tolerant by using smaller-sized bitcells, higher partitions in the crossbar, and device technologies with higher $R_{off}/R_{on}$ ratio.