3D IC Design-for-Test with Implementation of the IEEE 1149.1-2013, the IEEE 1500-2005, and the IEEE 1838-2019 Standard

The paper presents a design for a testable 3D integrated circuit (IC), and more specifically the Design-for-Test (DfT) method of its stacked layers. It describes how it implements the IEEE 1149.1-2013 Standard, the IEEE 1500-2005 Standard, and the IEEE 1838-2019 Standard. Finally, it presents the instructions that allow for the combined implementation of these Standards, and an analysis of its additional required footprint.