Input Impedance Modeling and Experimental Validation of a Single-Phase PFC in the D-Q Frame

This article models and characterizes the input impedance of a single-phase totem-pole power factor correction (PFC) converter in a virtual synchronous reference (d-q) frame. Due to the dc voltage controller, its d-d channel impedance behaves like a negative resistor, and the cascaded dc–dc converter load reduces its gain and phase at low frequency. Both are detrimental to system stability. The proposed impedance model can be employed to analyze instability issues. As examples, the low-frequency stability of a single-phase and a three-phase four-wire system is analyzed using the model. It is found that the single-phase system will confront the issue of settling to an operating point before any small-signal instability occurs. Whereas in a four-wire system, high neutral line inductance or high dc voltage control bandwidth could lead to small-signal instability. The impedance modeling results are validated by experiments.