CoVerPlan: A Comprehensive Verification Planning Framework leveraging PSS Specifications

With increasing design complexity, the portability of tests across different designs and platforms becomes a key criterion for accelerating verification closure. The Portable Test and Stimulus Standard (PSS) is an emerging industry standard prepared by Accellera for system-on-chip verification and testing. It provides language constructs to create a target-agnostic representation of stimulus and test scenarios reused by various users across many levels of integration. In this paper, we present CoVerPlan, a comprehensive verification framework built to explore the power of action inferencing on test models written in PSS. The proposed verification framework leverages a SAT planner to unwind the actual verification flow from the PSS specifications and automatically synthesizes target-specific constraint-random testbenches and formal assertions. CoVerPlan also carries out assertion-based verification of the synthesized properties. We demonstrate the efficacy of our proposed framework over several case studies, like the AMBA advanced peripheral bus (APB) protocol, a simple RISC processor, and a cache coherence protocol.