MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine

Compute-in-memory (CIM) employing non-volatile memories (NVMs) has been widely investigated as an attractive candidate to accelerate the heavy multiply-and-accumulate (MAC) workloads in deep neural networks (DNNs) inference. While DNNs exhibit error tolerance to a certain extent, the aggregated effects from device and circuit non-idealities may degrade network accuracy to unacceptable levels. In this work, we examine a scalable error-correcting code (ECC), called MAC-ECC, that can be applied to CIM outputs obtained from parallel row accesses. An extrapolative design methodology is proposed to select the suitable MAC-ECC scheme based on the target workload, desirable accuracy, and error level in the utilized CIM hardware. To demonstrate the techniques, we taped-out and validated a resistive random-access memory (RRAM)-based CIM macro with embedded MAC-ECC in TSMC 40 nm process. The design achieves macro-level peak performance of 42.7 TOPS/W energy efficiency and 97.8 GOPS/mm2 compute efficiency at 25 °C. By using the proposed methodology to select the optimal MAC-ECC scheme, the design maintains around 2% accuracy degradation for the investigated workloads at 120 °C with low performance overhead.