The Sparse Synchronous Model on Real Hardware

We present the Sparse Synchronous model (SSM) of computation, which allows a programmer to specify software timing more precisely than the traditional “heartbeat” of mainstream operating systems or the synchronous languages. SSM is a mix of semantics inspired by discrete event simulators and the synchronous languages designed to operate in resource-constrained environments such as microcontrollers. SSM provides precise timing prescriptions, concurrency, and determinism. We implement SSM in SSML, a toy language along with a runtime system that includes a scheduler, memory manager, and an interface that works with an RTOS to keep the model synchronized with the real world. Experimentally, we find our implementation is able to perform jitter-free I/O in the 10s of kHz on a microcontroller.