A Phase-Locked Loop With Inherent DC Offset Rejection for Single-Phase Applications

In this article, we aim to design a simple dc immune phase-locked loop (PLL) for single-phase applications. The dc offset is inherently rejected using only two delay operators. The dc offset in the synchronization unit is a challenging problem that causes oscillation in the estimated grid information. Using conventional filters to solve this problem is ineffective since this degrades the synchronization unit's dynamic performance. Different PLLs have been introduced in this article to mitigate the dc offset. Each has its merits and demerits, such as complex structure, high computational burden, and slow transient response. The proposed PLL incorporates two cascaded delayed signal cancellation operators with an arbitrary-length time delay, rejects the dc offset, and perfectly synchronizes with the grid. This article also presents a small-signal model to facilitate the loop filter design and stability analysis. Besides the simulations, the PLL's performance is validated experimentally under various disturbance conditions, with comparisons with other PLLs.