A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network

It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This paper presents a methodology to obtain the minimal number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results.