String Current Compensation Method in VNAND Flash for Hardware-Based BNNs

This work proposes a method to prevent unwanted string current degradation in multistacks vertical NAND (VNAND) flash memory for hardware-based binary neural networks (BNNs). Simulations investigate the effect of string resistance on the accuracy of a multilayer BNNs, considering the measured cell string characteristics. When the weights obtained from off-chip training are transferred to the BNN without compensation cells, the classification accuracy of the hardware-based BNN is reduced by ~80.3% in 23-layer network. However, the proposed compensation cell model shows a degradation of classification accuracy of 1.4% in the 23-layer BNN compared to the software-based BNN.