Simple Design of Maximum Likelihood Demodulation in Receiver With Few-Bit ADCs for Amplitude-Modulated Signals

An analog-to-digital converter (ADC) with a simple structure but low resolution(few-bits or even one-bit) is emerging to reduce circuit cost and energy consumption, in addition to achieving a high sampling rate. Against these advances, the nonlinear response in the few-bit ADC deteriorates the shape of the input signal, resulting in a significant performance degradation. For example, in broadband wireless communications, the transmitted data often fails to be demodulated correctly. To address this issue, this brief presents a simple design framework for maximum likelihood (ML) demodulation in a receiver with few-bit ADCs, achieving fewer demodulation errors and lesser hardware costs. Based on the statistical behavior of the ADC output, we theoretically introduce three methods to calculate the likelihood simply. Considering that the increased sequence length of the ADC output reduces the demodulation error, our theoretical and numerical investigations show that using the ML-based method with higher-order moments is beneficial for achieving a small demodulation error with a lower hardware cost.