On-Chip Dynamic Gate-Voltage Waveform Sampling in a 200-V GaN-on-SOI Power IC

The continual improvement of GaN-on-Si processes motivates the integration of more complex circuits alongside GaN power devices. Additional transistors can be leveraged to provide control, logic, and protection; however, low-voltage GaN devices consume more power and area than similar CMOS counterparts. This article investigates the feasibility of a monolithic gate-monitoring circuit integrated with a GaN power device and gate driver. The monitoring circuit captures 16 samples within 50 ns during the gate rising transient and stores them in on-chip capacitors. The stored voltages are asynchronously read off-chip through integrated source-follower buffers and a digitally controlled multiplexer. The proposed design incorporates approximately 330 e-HEMT transistors and was fabricated in a 200-V GaN-on-SOI process. A detailed characterization was performed to calibrate the dynamic on-chip gate voltage from the sampled values that are read off-chip, paving the way for future active control based on this feedback. Experimental results and the postcalibration estimate of the on-chip gate voltage highlight that off-chip measurements are poor and pessimistic estimators for the on-chip dynamic excursions. The on-chip gate-voltage waveform was estimated using the sampling circuit while switching the power device at 80 V, 1.5 A, demonstrating more accurate measurements of on-chip signals. This circuit stands as a proof-of-concept for the viability of integrating relatively complex circuits in GaN power ICs to perform critical monitoring and sensing tasks.