SoIC_H Technology for Heterogeneous System Integration

A System on Integrated Chip_Horizontal (SoIC_H) technology for heterogeneous system integration in high-performance computing (HPC) is proposed. Compute logic chiplets and memory cubes are tightly integrated on a Si interposer via ultrafine pitch SoIC bond to provide low parasitic and high density in input/output (I/O) interconnects. To demonstrate the advantages of SoIC_H technology over <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> bump in HPC applications, the electrical performance of a face-to-face (F2F), 3-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> pitch (<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>mP), and low-temperature (LT) SoIC bonding on a silicon interposer was conducted and compared with the ones using <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>bump. Through system technology co-optimization (STCO), the proposed SoIC_H technology at the bond pitch of <inline-formula> <tex-math notation="LaTeX">$3~\mu \text{m}$ </tex-math></inline-formula> improves energy per bit and latency for die-to-die I/O link and on-chip fan-in/fan-out design through the simulation. For memory cube integration, if <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>bumps between stacked dies are replaced by SoIC bonds, lower latency, higher bandwidth, and lower energy per bit for 4-Hi static random access memory (SRAM) cache and 12-Hi high bandwidth memory (HBM) are obtained. Moreover, the proposed structure provides significant thermal resistance improvements along the thermal conduction path of logic and memory cubes attached to the Si interposer. With much improved electrical and thermal performance, the SoIC_H technology enables energy-efficient heterogeneous system integration and applications.