DC-Link Capacitance Reduction in PFC Rectifiers Employing PI+Notch Voltage Controllers

It is well-known that adding a notch filter in series with the typically employed type-II (or PI) regulator allows improving the tradeoff between dc-link voltage dynamics and grid-side current total harmonic distortion (THD) in practical single-phase power factor correction rectifiers. The article demonstrates that notch filter utilization alternatively allows reducing the value of dc-link capacitance in case hold-up time requirement is absent. The revealed value of minimum capacitance is expressed by explicit function of possible mains frequency values range, maximum expected grid voltage magnitude, rated system power, dc-link voltage set point, maximum tolerable grid-side current THD, and the desired phase margin (PM) of dc-link voltage loop. It is demonstrated that the proposed approach yields fourfold reduction of dc-link capacitance for typical values of 5% tolerable grid-side current THD under 40° PM constraint. Experimental results exhibit close-fitting resemblance to corresponding analytical predictions, verifying the proposed methodology.