A CMOS compatible silicon modulator of 3D-optimized interleaved design with high modulation efficiency

Interleaved modulators enable more optimized doping profiles for higher modulation efficiency and lower loss. Nevertheless, as far as we know, complex doping for interleaved modulators has hardly been studied. Hence this work proposes a modulator based on interleaved vertical and U-shaped junctions using the Monte-Carlo simulation. The results illustrate that the modulation efficiency of the designed interleaved period is 0.57 V·cm, while the loss is 15.5 dB/cm. This high-efficiency design verifies the benefits of interleaved 3D modulator design as significantly increasing modulation efficiency with low loss, showing great potential for high-speed application.