Comparison and Optimization of Datasheet-Driven Extraction of Gate-Drain Overlap Oxide Capacitance in IGBT Modeling

Extracting gate-drain overlap oxide capacitance (<italic>C</italic><sub>oxd</sub>) is a necessary step for almost all kinds of insulated-gate bipolar transistor (IGBT) compact models. There are two datasheet-driven methods that are universally accepted, one is based on reverse capacitance voltage characteristics (<italic>C–V</italic> method), and the other uses gate charge characteristics (<italic>Q–V</italic> method). This letter is to reveal the underlying mechanism of these two methods. It is found that the <italic>C–V</italic> method has an inescapable shortcoming which will mistake the turn-<sc>off</sc> delay time forecasted by IGBT models. In this letter, the internal capacitance system of IGBT is modeled and demonstrated completely. Based on this model, the accuracy and feasibility of the <italic>C–V</italic> and <italic>Q–V</italic> methods are analyzed. Moreover, the effect of <italic>C</italic><sub>oxd</sub> on IGBT compact models is studied and further verified by experiments and circuit simulations.