Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula>, respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.