A Modified Space Vector Modulation for DC-Side Current Ripple Reduction in High-Frequency Link Matrix Converter

A high-frequency link matrix converter (HFLMC) has been increasingly used in power conversion for its distinct advantages of high efficiency and compact volume. However, the conventional six-segment space vector PWM (SVPWM) scheme leads to high current ripple on the dc side and distortion on the ac side, which can inevitably destroy the battery load and decrease power quality. This article proposes a modified SVPWM scheme with dwell time and sequence compensation (MC-SVPWM) to reduce the current ripple and distortion under high modulation index conditions. The proposed MC-SVPWM allocates the vector sequence and adjusts the duration of the vector, simultaneously. First, the reasons for the current ripple and distortion under the conventional six-segment SVPWM (6S-SVPWM) scheme are analyzed in detail. The relationship between the vector duration and the dc-side current ripple is revealed. Then, the derivation process of the proposed MC-SVPWM scheme is introduced. Compared with the conventional 6S-SVPWM scheme, the dc-side current ripple is decreased greatly, and the ac-side current distortion is reduced consequently under the proposed MC-SVPWM scheme. Simulation and experimental results verify the effectiveness of the proposed modulation strategy.