A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface

A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 $\mu \text{s}$ by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.