A high-performance FPGA architecture for Acceleration of SVM Machine Learning Training

Support Vector Machines (SVMs) is one of the most popular machine learning algorithms as it provides high-performance and needs minimal tuning. It can be used for classification, regression and other learning tasks. Its design makes the training of large datasets time-consuming, so it is important that solutions are developed that attempt to tackle this problem. One such solution is presented in this paper. Based on the LIBSVM library, one of the most popular and widely used implementations of SVMs, we developed the design that can be executed on an heterogeneous computing system, consisting of an FPGA accelerator card, along with CPU.The first step of the process is to determine the most computationally intensive and parallelizable part of the algorithm. That is found to be a matrix row computation, involving inner products and a mathematical function (one of exp, pow, tanh) for each of the elements. Then, we develop a kernel, that can fully utilize the abilities of the FPGA accelerator card, regarding data processing and computations. In our case that is the Alveo U200 Data Center accelerator card. The results show that the proposed implementation achieves up to 14x speedup in the row computation part of the algorithm compared to a multi-threaded CPU execution on a Ryzen3 2200G, a CPU with a base clock speed of 3.5 GHz.