Device modeling of oxide-semiconductor channel antiferroelectric FETs using half-loop hysteresis for memory operation


 In this work, memory characteristics of oxide-semiconductor (OS) channel antiferroelectric-FETs (AFeFETs) has been investigated by developing a compact model of AFeFETs. The model consists of an analytic junctionless FeFET model and a newly developed AFe Preisach model. The AFe Preisach model can reproduce arbitrary minor loop (ML) measurement results. The key feature of AFeFETs is using the half-loop hysteresis (HLH) of AFe unlike using the full hysteresis of Fe. Only small net charge is required and minority carrier generation is not necessary for erase operation, which is preferable for typical oxide semiconductor (OS) channel. Based on the developed model, we have systematically varied device parameters of OS channel and AFe gate insulator, analyzed memory window (MW) using operation point analysis, then showed the potential of OS channel AFeFETs for memory applications.