The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks

Commercial SRAM-based field-programmable gate arrays (FPGAs) are becoming popular computing platforms for building efficient Neural Network (NN) accelerators for space missions. FPGAs can implement custom NN architectures that are tailored to the requirements of the mission to improve the performance-to-watt ratio of the design. However, SRAM FPGAs are vulnerable to radiation-induced Single Event Upsets (SEUs), imposing significant design-for-reliability challenges. In this work, we study the impact of hardware folding on the dependability of Binarised NN (BNN) FPGA accelerators. Hard-ware folding configures the level of resource sharing in the design. We implemented three design versions of a BNN that performs image classification. The BNNs were generated with FINN, an open-source framework for developing quantised NNs on AMD-Xilinx FPGAs. The BNNs were implemented on a Zynq-7020 system-on-chip FPGA and tested with configuration memory fault injection experiments to estimate their SEU vulnerability. The three BNN design versions have a maximum (Max), medium (Med), and minimum (Min) folding factor, respectively. Assuming a Low Earth Orbit (LEO), our results show that the Med BNN has the highest Mean Time Between Failure (MTBF) and the Min has the lowest MTBF. However, Min has the highest Mean Executions Between Failure (MEBF) due to its high computational performance.