A Method to Derive the Coupling Thermal Resistances at Junction-to-Case Level in Multichip Power Modules

A method to derive the junction-to-case level coupling thermal resistances among paralleling chips in the multichip semiconductor power module has been proposed in this article. It is revealed that the traditional structure function methodology (SFM), which is developed for analyzing the self-heating effect of the driving-point chip, cannot be applied directly in the thermal coupling analysis, where the influence of the driving-point chip on the neighboring acceptor chip is concerned. This article shows that by combining the traditional SFM with the frequency-domain analysis (FDA), the effective separation points between the module case and the external cooling setup can be identified in both time and frequency domains, which correspond to the characteristic frequency points in the complex loci of the thermal impedance curves. By extracting the amplitudes at the characteristic frequencies from the complex loci in the FDA, the junction-to-case level coupling thermal resistances can be derived. Both simulation and experimental study have been carried out to verify the concept. The agreement between the two justifies the proposed method.