Towards disaggregated P4 pipelines with information exchange minimization

With the advent of programmable data plane hardware and the use of P4 as a high-level programming language, switches not only implement existing protocols but can also offload other tasks easily. However, hardware switches introduce several constraints on the number of computational stages, available SRAM/TCAM, ALUs, etc. In future use cases, such a device may potentially host multiple pipelines at the same time, resulting in additional constraints on the available resources for a single pipeline. The limitations of a single switch can however be handled by disaggregating the pipeline and deploying the resulted subpipelines at different switches in the network. In such approach, in addition to handling routing and packet classification, we also have to solve the information exchange between the depending subpipeline elements, adding extra headers transmitting metadata and variables needed for the continuation of the pipeline execution on another switch in the network. This paper explores the disaggregation of P4 pipelines with long-dependency sequences into subpipelines that minimizes the information exchange overhead and considers constraints on the maximum length of dependency chains in each subpipelines in a way to reach a fully automated process eventually.