A Performance Comparison Review of Multiplier Designs

In this paper, different algorithms to design a multiplier is presented along with their advantages and limitations in terms of VLSI matrices. Multiplier is an essential building block of a micro processor and embedded system. It decides the critical path of the system in terms of area or delay or power. Thus it, is important to optimize such building block for low area or low power or high speed. The paper also represent a review analysis based on experimental results. The result shows that modified booth multiplier with wallace tree is best choice to design a multiplier such applications. The paper also represents a review on booth multiplier using higher radix.