EVE/ZeBu
# EVE/ZeBu

EVE/ZeBu is a provider of hardware-assisted verification tools for functional verification of Application-specific integrated circuits (ASICs) and system on chip (SOC) designs and for validation of embedded software (software driver, Operating System and Application software) ahead of implementation in silicon. EVE's hardware acceleration and hardware emulation products work in conjunction with Verilog, SystemVerilog, and VHDL-based simulators from Synopsys, Cadence Design Systems and Mentor Graphics. EVE's flagship product is ZeBu.

## History

In 2000, EVE was founded in France.

In 2002, EVE launched its flagship ZeBu's first emulation product and SystemC support.

In May 2006, EVE introduced a communication link to SystemVerilog simulation, SystemVerilog assertion support, and a register transfer level compiler for mapping an ASIC or System-on-a-chip (SOC) design into ZeBu's arrays of FPGAs.

In January 2007, EVE acquired Tharas, a microprocessor-based hardware acceleration systems supplier.

In July 2009, EVE announced their ZeBu-Server emulator could handle one billion logic gates.

In October 2012, EVE was acquired by Synopsys.

## Management team

* Luc Burgun - CEO President and CTO, Co-founder
* Ludovic Larzul - Engineering VP, Co-founder
* Lauro Rizzatti - EVE-USA General Manager and WW Marketing VP
* William Addi - Chief Financial Officer
* Ron Burns - Sales VP
* Christophe Ballan - Operations VP

## Products

EVE has a ZeBu family of hardware acceleration and FPGA-based hardware emulation products, which EVE claims has design capacity scalable from 10M to 1B ASIC gates and a top speed of 30 MHz.

## Features

The ZeBu emulator supports operational modes for hardware description language (HDL) acceleration, ANSI C++/SystemC/SystemVerilog transaction-based co-emulation, where the testbench described at high-level of abstraction drives the design mapped in ZeBu via communication protocol interfaces called transactors, and an in-circuit emulator mode.

The ZeBu compiler does automation chip division, where one SoC is divided into multiple FPGAs based on user specified parameters for input file paths, such as EDIF Netlist, number of FPGAs the ZeBu board has, and the number of CPUs used for compilation.

ZeBu has static, dynamic and flexible probes for retrieving and depositing data. Static and flexible probes are created during compilation, with speeds exceeding 10 MHz. Dynamic probes do not require compilation, and slow down the execution speed of the emulator to few kilohertz.

ZeBu can be used by up to 25 multiple concurrent users.

