Shadow RAM (Acorn)
# Shadow RAM (Acorn)

Shadow RAM, on the Acorn BBC Micro, Master-series and Acorn Electron microcomputers is the name given to a special framebuffer implementation to free up main memory for use by program code and data. Some implementations of shadow RAM also permit double-buffered graphics.

## Background

The BBC Micro, Master-series and Electron machines use the 8-bit 6502 and 65C102 processors with a 16-bit address space. This address space is split into 32 KB RAM (0x0000 to 0x7FFF), 16 KB sideways "paged" address space (0x8000 to 0xBFFF) and 16 KB operating system space (0xC000 to 0xFFFF). Video or screen memory is typically allocated from 0x7FFF downwards as necessary, occupying as little as 1 KB for Teletext mode 7 (and thus the region from 0x7C00 to 0x7FFF), or as much as 20 KB for modes 0-2 (and thus the region from 0x3000 to 0x7FFF). Thus, screen memory can therefore occupy a considerable amount of the available directly-addressed 32 KB RAM.

## Overview

Shadow RAM is a block of RAM that can be considered to reside in parallel to the normal memory map and is accessed by the system only under certain conditions. When shadow RAM is enabled, the memory region normally used for screen memory becomes available for BASIC program use and for applications employing officially documented operating system interfaces. Given the maximum requirement of 20 KB for screen memory with the systems concerned, the amount of shadow RAM provided is typically 20 KB.

Shadow RAM was fitted as standard on the BBC Micro Model B+ and on the BBC Master series, but was an optional feature provided by third-party expansions on earlier BBC Micro systems and the Acorn Electron. The Aries-B20 product, initially sold by Cambridge Computer Consultants, offered 20 KB shadow RAM for the BBC Model B, transparently diverting non-framebuffer accesses to the shadow RAM for addresses in the 20 KB video memory region.

In systems based on the BBC Model B+, like the Acorn Cambridge Workstation, a programmable array logic (PAL) chip controls access to memory and exposes the screen memory to the CPU by redirecting memory accesses to the appropriate memory locations. When shadow mode is enabled, the PAL chip monitors the addresses of instructions fetched by the CPU, and where such instructions have been fetched from a range of memory from 0xA000 to 0xAFFF or from 0xC000 to 0xDFFF, they are considered to be part of the VDU drivers that may access the screen memory.

Consequently, all memory accesses performed by instructions fetched from these VDU driver regions that then access memory in the range 0x3000 to 0x7FFF are considered to be accessing screen memory, and the PAL chip asserts a signal to select the "shadow" 20 KB memory bank for such instructions so that they may read from or write to the screen. All other RAM accesses while in shadow mode are directed towards a contiguous region of RAM from 0x0000 to 0x7FFF (and potentially up to 0xAFFF, if exposed) that does not host the screen memory. Meanwhile, in non-shadow or "normal" mode, this same contiguous region does host the screen memory, as is the convention in the traditional BBC Micro architecture, and the shadow memory is not accessible.

## BBC Master Implementation

Unlike the expansion boards for earlier systems, the BBC Master implementation of shadow RAM permits the selection of either shadow memory or main memory for use as screen memory, this being done via the Access Control Register. By switching between main and shadow memory on alternate frames, double-buffered video could be used. Acorn provided a demonstration program in BASIC showing scrolling cloud animation with and without double buffering. The video game Firetrack would also use double buffering if shadow RAM was present.

On the BBC Master (and also the BBC Model B+), shadow RAM is activated by setting the most significant bit of the memory mode number. For example, to use mode 1 with shadow RAM enabled, mode 129 (128 combined with 1) is selected.

Another significant difference between the Master implementation of shadow RAM and previous implementations also offering 32 KB of shadow RAM is the allocation of the extra 12 KB beyond the 20 KB shadowing the screen memory. Instead of this memory occupying a single region from 0x8000 to 0xAFFF in sideways RAM space, as it does with the Aries-B32 product and the BBC Model B+, it instead occupies two regions in the Master as "private RAM": a 4 KB region from 0x8000 to 0x8FFF holding function key definitions, workspace for the operating system, and character and font definitions; an 8 KB region from 0xC000 to 0xDFFF holding paged (sideways) ROM and operating system workspace. Thus, the Master was able to support character set redefinition and to allocate memory to filing systems without the amount of available user RAM being reduced.

## Further Refinements

Subsequent products augmented the shadow RAM with additional RAM that could be used for other purposes. For instance, the Aries-B32 product permitted shadow/sideways RAM combinations of 20 KB/12 KB and 16KB/16KB, or the use of the 32 KB RAM as two sideways RAM banks. The Slogger Master RAM Board offered a 32K RAM solution for the Acorn Electron alongside a "turbo mode" enhancement.

## Patent Dispute

A dispute arose between the designers of the Aries-B20 shadow RAM board (Aries Computers Limited) and two other companies offering similar products, Raven Micro Products and Watford Electronics, over the alleged infringement of patent GB2137382A describing techniques employed in the design of the Aries-B20 board. The products involved were the Raven Micro Products (Raven-20) and Watford Electronics (32K RAM Expansion Board). Ultimately, in 1986, Watford Electronics acquired Aries Computers in a "five figure deal" including the patents involved, with Watford subsequently selling Aries' products alongside the company's own.

