IBM Advanced Computer Systems project
# IBM Advanced Computer Systems project

The ACS-1 and ACS-360 are two related supercomputers designed by IBM as part of the IBM Advanced Computing Systems project from 1961 to 1969. Although the designs were never finished and no models ever went into production, the project spawned a number of organizational techniques and architectural innovations that have since become incorporated into nearly all high-performance computers in existence today. Many of the ideas resulting from the project directly influenced the development of the IBM RS/6000 and, more recently, have contributed to the Explicitly Parallel Instruction Computing (EPIC) computing paradigm used by Intel and HP in high-performance processors.

## History

The ACS project began in 1961 as Project Y with a goal of “building a machine that was one hundred times faster than Stretch”. Initial work began at the IBM Watson Research Center. A number of significant computer pioneers contributed to the project, including John Cocke, Herb Schorr, Frances Allen, Gene Amdahl, and Lynn Conway.

A decision by IBM in May 1968 to modify the project to support S/360 compatibility resulted in the name change from ACS-1 to ACS-360 for the computer being designed. At its peak, the ACS-360 project involved over 200 engineers and staff.

The ACS-360 project was canceled in May 1969; however, many of the innovations resulting from the project would eventually find direct realization in the IBM RS/6000 series of machines (later known as the IBM System p line of workstations and servers), apart from influencing the design of other machines and architectures.

## Influence

Although neither the ACS-1 nor the ACS-360 was ever manufactured, the IBM Advanced Computing Systems group responsible for their design developed architectural innovations and pioneered a number of RISC CPU design techniques that would become fundamental to the design of modern computer architectures and systems:

* Aggressive reduction in the number of logic gate levels for pipeline stages to reduce the cycle time
* Tight integration between processor and memory
* Cache memory with streamlined I/O to/from cache
* Compiler optimization techniques
* Virtual-memory operating systems
* Multiple instruction decode and issue (a first)
* Use of a branch target buffer (a first)
* Multithreading implemented in hardware (a first for IBM)
* Dynamic instruction scheduling/out-of-order execution
* Hardware register renaming
* Instruction predication
* Level-sensitive scan design (used by IBM)
* Fixed-head hard disks
* Air-cooled high-speed LSI circuits
* Advanced simulation tools used in the design process
