KOMDIV-32
# KOMDIV-32

The KOMDIV-32 (Russian: КОМДИВ-32) is a family of 32-bit microprocessors developed and manufactured by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences. The manufacturing plant of NIISI is located in Dubna on the grounds of the Kurchatov Institute. The KOMDIV-32 processors are intended primarily for spacecraft applications and many of them are radiation hardened (rad-hard).

These microprocessors are compatible with MIPS R3000 and have an integrated MIPS R3010 compatible floating-point unit.

## Overview

| Designation | Designation | Production start (year) | Process (nm) | Clock rate (MHz) | Remarks |
| - | - | - | - | - | - |
| Russian | English | Production start (year) | Process (nm) | Clock rate (MHz) | Remarks |
| 1В812 | 1V812 | ? | 500 | 33 | |
| 1890ВМ1Т | 1890VM1T | 2000 | 500 | 50 | rad-hard |
| 1890ВМ2Т | 1890VM2T | 2003 | 350 | 90 | |
| 1990ВМ2Т | 1990VM2T | 2008 ? | 350 | 66 | rad-hard |
| 5890ВМ1Т | 5890VM1Т | 2009 | 500 | 33 | rad-hard |
| 5890ВЕ1Т | 5890VE1Т | 2009 | 500 | 33 | rad-hard |
| 1900ВМ2Т | 1900VM2T | 2012 | 350 | 66 | rad-hard |
| 1904ВЕ1Т | 1904VE1T | 2016 | 350 | 40 | |
| 1907ВМ014 | 1907VM014 | 2016 | 250 | 100 | rad-hard |
| 1907ВМ038 | 1907VM038 | 2016 ? | 250 | 125 | rad-hard |
| 1907ВМ044 | 1907VM044 | 2016 ? | 250 | 66 | rad-hard |
| 1907ВМ056 | 1907VM056 | 2016 ? | 250 | 100 | rad-hard |
| 1907ВМ066 | 1907VM066 | 2016 ? | 250 | 100 | rad-hard |
| 1907ВК016 | 1907VK016 | ? | 250 | 100 | rad-hard |

## Details

### 1V812

* 0.5 µm CMOS process, 3-layer metal
* 108-pin ceramic Quad Flat Package (QFP)
* 1.5 million transistors, 8KB L1 instruction cache, 8KB L1 data cache, compatible with IDT 79R3081E

### 1890VM1T

* 0.5 µm CMOS process

### 1890VM2T

* 0.35 µm CMOS process

### 1990VM2T

* 0.35 µm silicon on insulator (SOI) CMOS process
* 108-pin ceramic Quad Flat Package (QFP)
* working temperature from -60 to 125 °C

### 5890VM1Т

* 0.5 µm silicon on insulator (SOI) CMOS process
* 108-pin ceramic Quad Flat Package (QFP)
* cache (8KB each for data and instructions)
* working temperature from -60 to 125 °C

### 5890VE1Т

* 0.5 µm SOI CMOS process
* 240-pin ceramic QFP
* radiation tolerance to not less than 200 kRad, working temperature from -60 to 125 °C
* System-on-a-chip (SoC) including PCI master / slave, 16 GPIO, 3 UART, 3 32-bit timers
* cache (8KB each for data and instructions)
* second-sourced by MVC Nizhny Novgorod under the name 1904VE1T (Russian: 1904ВЕ1Т) with a clock rate of 40 MHz

### 1900VM2T

* development name Rezerv-32
* 0.35 µm SOI CMOS process
* 108-pin ceramic QFP
* radiation tolerance to not less than 200 kRad, working temperature from -60 to 125 °C
* triple modular redundancy on block level with self-healing
* both registers and cache (4KB each for data and instructions) are implemented as dual interlocked storage cells (DICE)

### 1907VM014

* 0.25 µm SOI CMOS process; manufacturing to be moved to Mikron
* 256-pin ceramic QFP
* production planned for 2016 (previously this device was planned to go into production in 2014 under the name 1907VE1T or 1907VM1T)
* radiation tolerance to not less than 200 kRad
* SoC including SpaceWire, GOST R 52070-2003 (Russian version of MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, JTAG
* cache (8KB each for data and instructions)

### 1907VM038

* development name Skhema-10
* 0.25 µm SOI CMOS process; manufacturing to be moved to Mikron
* 675-pin ceramic BGA
* SoC including SpaceWire, GOST R 52070-2003 (MIL-STD-1553), RapidIO, SPI, I²C, 16 GPIO, 2 UART, 3 32-bit timers, JTAG, DSP (same command set as DSP in 1890VM7Ya)
* DDR2 SDRAM controller with ECC
* cache (8KB each for data and instructions)
* working temperature from -60 to 125 °C

### 1907VM044

* development name Obrabotka-10
* 0.25 µm SOI CMOS process; manufactured by Mikron
* 256-pin ceramic QFP
* SoC including SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, JTAG
* radiation tolerance to not less than 200 kRad
* triple modular redundancy in processor core
* both registers and cache (4KB each for data and instructions) are implemented as dual interlocked storage cells (DICE) with 1 parity bit per byte for cache and Hamming code for registers
* SECDED for external memory
* working temperature from -60 to 125 °C

### 1907VM056

* development name Skhema-23
* 0.25 µm SOI CMOS process; manufactured by Mikron
* 407-pin ceramic PGA
* SoC including 8-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, I²C, CAN bus, 32 GPIO, 2 UART, 3 timers, JTAG
* cache (8KB each for data and instructions)

### 1907VM066

* development name Obrabotka-26
* 0.25 µm silicon on insulator (SOI) CMOS process; manufactured by Mikron
* 407-pin ceramic PGA
* SoC including 4-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, I²C, RapidIO, GPIO, 2 UART, 3 timers, JTAG, PCI, co-processor for image processing
* cache (8KB each for data and instructions)

### 1907VK016

* development name Obrabotka-29
* 0.25 µm silicon on insulator (SOI) CMOS process; manufactured by Mikron
* PGA
* SoC including 4-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, 128KB SRAM
* triple modular redundancy in processor core
