Contamination delay
# Contamination delay

In digital circuits, the contamination delay (denoted as $t_{cd})$ is the minimum amount of time from when an input changes until any output starts to change its value. This change in value does not imply that the value has reached a stable condition. The contamination delay only specifies that the output rises (or falls) to 50% of the voltage level for a logic high. The circuit is guaranteed not to show any output change in response to an input change before $t_{cd}$ time units (calculated for the whole circuit) have passed. The determination of the contamination delay of a combined circuit requires identifying the shortest path of contamination delays from input to output and by adding each $t_{cd}$ time along this path.

For a sequential circuit such as two D-flip flops connected in series, the contamination delay of the first flip-flop must be factored in to avoid violating the hold-time constraint of the second flip-flop receiving the output from the first flip flop. Here, the contamination delay is the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q). If there is insufficient delay from the output of the first flip-flop to the input of the second, the input may change before the hold time has passed. Because the second flip-flop is still unstable, its data would then be "contaminated." Every path from an input to an output can be characterized with a particular contamination delay.

Well-balanced circuits will have similar speeds for all paths through a combinational stage, so the minimum propagation time is close to the maximum. This corresponding maximum time is the propagation delay. The condition of data being contaminated is called a race.

