Update to use code-block syntax
@@ -14,7 +14,8 @@ To follow along, go to the root directory of OpenFPGA and enter:
Go to line 187 and replace it with:
-``<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="">``
+.. code-block:: xml
+<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="">
Motivation
~~~~~~~~~~
@@ -54,7 +55,8 @@ The `user_defined_templates.v`_ file can be found starting from the root directo
This file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. The file is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. This file can be included in simulation only if there are modifications to the file.
To implement our own ADDF module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_templates.v`` file with the following:
-``//-------------------------------------------
+.. code-block:: verilog
+//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Template for user-defined Verilog modules
// Author: Xifan TANG
@@ -99,7 +101,7 @@ output [0:0] CO;
assign CO = (A & B) | (A & CI) | (B & CI);
// ----- Internal logic should end here -----
endmodule
-// ----- END Verilog module for ADDF -----``
+// ----- END Verilog module for ADDF -----
We can now link this ``user_defined_templates.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``.
