[Arch] Introduce new XML syntax for global port in tile annotation
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
- <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
+ <global_port name="clk" is_clock="true" default_val="0">
+ <tile name="clb" port="clk"/>
+ </global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
