[engine] apply code format
@@ -531,8 +531,7 @@ class ModuleManager {
vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_wire_; /* If the port is a wire, use for Verilog port definition. If
enabled: <port_type> reg <port_name> */
- vtr::
- vector<ModuleId, vtr::vector<ModulePortId, bool>>
+ vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>>
port_is_register_; /* If the port is a register, use for Verilog port
definition. If enabled: <port_type> reg <port_name>
*/
