Update tutorial to swap in PNGs and fix errors
@@ -6,7 +6,7 @@ Introduction
**In this tutorial, we will**
- Showcase how to create an architecture description based on standard cells, using OpenFPGA's circuit modeling language
- - Use Skywater's Processor Development Kit (`PDK`_) cell library to create an OR Gate circuit model for OpenFPGA
+ - Use Skywater's Process Development Kit (`PDK`_) cell library to create an OR Gate circuit model for OpenFPGA
- Verify that the standard cell library file was correctly bound into the selected architecture file by looking at auto-generated OpenFPGA files and checking simulation waveforms in GTKWave
Through this example, we will show how to bind standard cell library files with OpenFPGA Architectures.
@@ -14,7 +14,10 @@ Through this example, we will show how to bind standard cell library files with
Create and Verify the OpenFPGA Circuit Model
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-In this tutorial, we focus on binding a 2-input **OR** gate from a standard cell library to a circuit model in OpenFPGA's architecture description file. Note that the approach can be generalized to any circuit model. For this tutorial, we start with an example where the HDL netlist of an 2-input **OR** gate that is auto-generated by OpenFPGA. After updating the architecture file, the auto-generated HDL netlist by OpenFPGA will directly instantiate a standard cell from the open-source Skywater 130nm PDK library.
+
+.. note:: In this tutorial, we focus on binding a 2-input **OR** gate from a standard cell library to a circuit model in OpenFPGA's architecture description file. Note that the approach can be generalized to any circuit model.
+
+For this tutorial, we start with an example where the HDL netlist of an 2-input **OR** gate that is auto-generated by OpenFPGA. After updating the architecture file, the auto-generated HDL netlist by OpenFPGA will directly instantiate a standard cell from the open-source Skywater 130nm PDK library.
To follow along, go to the root directory of OpenFPGA and enter:
.. code-block:: bash
@@ -27,7 +30,7 @@ This will run a prebuilt task with OpenFPGA cell libraries. When the task is fin
vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/luts.v
-.. note:: Users can find full details about netlist organization in our documentation: https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/fabric_netlist/
+.. note:: Users can find full details about netlist organization in our documentation: :ref:``fabric_netlists``
The ``luts.v`` file represents a Look Up Table within the OpenFPGA architecture. The important lines of this file for the tutorial are highlighted below.
These lines show the instantiation of OpenFPGA's **OR2** cell library.
@@ -190,11 +193,12 @@ The simulation waveforms should look similar to the following :numref:`fig_contr
.. _fig_control_output:
-.. figure:: ./figures/Control_Waveforms3.svg
+.. figure:: ./figures/Control_Waves.png
:scale: 100%
Control Circuit Model's Simulation Waveforms
+
.. note:: The waveform inputs do not need to exactly match because the testbench provides input in random intervals.
We have now finished creating the control and viewing the important sections for this tutorial. We can now incorporate Skywater's cell library to create a new circuit model.
@@ -462,7 +466,7 @@ The simulation waveforms should look similar to the following :numref:`fig_custo
.. _fig_custom_output:
-.. figure:: ./figures/Custom_Waveforms2.svg
+.. figure:: ./figures/Custom_Waves.png
:scale: 100%
Custom Circuit Model's Simulation Waveforms
