[Doc] Update documentation for new XML syntax "is_data_io"
@@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in
.. option:: <port type="<string>" prefix="<string>" lib_name="<string>" size="<int>"
default_val="<int>" circuit_model_name="<string>" mode_select="<bool>"
- is_global="<bool>" is_set="<bool>" is_reset="<bool>" is_config_enable="<bool>"/>
+ is_global="<bool>" is_set="<bool>" is_reset="<bool>"
+ is_config_enable="<bool>" is_io="<bool>" is_data_io="<bool>"/>
Define the attributes for a port of a circuit model.
@@ -169,10 +170,12 @@ A circuit model may consist of a number of ports. The port list is mandatory in
.. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
- - ``io="true|false"`` Specify if this port should be treated as an I/O port of an FPGA fabric. When this is enabled, this port of each circuit model instanciated in FPGA will be added as an I/O of an FPGA.
+ - ``is_io="true|false"`` Specify if this port should be treated as an I/O port of an FPGA fabric. When this is enabled, this port of each circuit model instanciated in FPGA will be added as an I/O of an FPGA.
.. note:: global ``output`` ports must be ``io`` ports
+ - ``is_data_io="true|false"`` Specify if this port should be treated as a mappable FPGA I/O port for users' implementation. When this is enabled, I/Os of user's implementation, e.g., ``.input`` and ``.output`` in ``.blif`` netlist, can be mapped to the port through VPR.
+
- ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
.. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
