[Test] Deploy the newly added adder benchmarks to tests
@@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
-bench1_top = adder_8
+bench0_top = adder_4
+bench1_top = adder_6
+bench2_top = adder_8
+bench3_top = adder_16
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-##########################
-# The output verilog of yosys is not synthesizable!!!
-# Turn off verification for now
-# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=
