[script] fixed the path to yosys bin for openfpga flow
# Standard Configuration Example
[CAD_TOOLS_PATH]
openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys
misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
-abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
+abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/install/bin/yosys-abc
abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
-abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
-vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
+abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
+vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr
ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
iverilog_path = iverilog
