[Doc] Update documentation about 'default_net_type' option in testbench generators
@@ -76,6 +76,10 @@ write_full_testbench
Use explicit port mapping when writing the Verilog netlists
+ .. option:: --default_net_type <string>
+
+ Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
+
.. option:: --include_signal_init
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
@@ -106,6 +110,10 @@ write_preconfigured_fabric_wrapper
Use explicit port mapping when writing the Verilog netlists
+ .. option:: --default_net_type <string>
+
+ Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
+
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulator can accept
@@ -140,6 +148,11 @@ write_preconfigured_testbench
Use explicit port mapping when writing the Verilog netlists
+ .. option:: --default_net_type <string>
+
+ Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
+
+
.. option:: --support_icarus_simulator
Output Verilog netlists with syntax that iVerilog simulator can accept
