Update customize_subckt.rst
@@ -9,5 +9,5 @@ To make sure the customized SPICE netlists can be correctly included in FPGA-SPI
<input_ports> <output_ports> <sram_ports> <clock_ports> <vdd> <gnd>
It is not necessary to keep the names of ports be the same with what is defined in the SPICE models. But the bandwidth of the ports should be consistent with what is defined in the Circuit models.
-.. note:: If the customized SPICE netlists includes inverters, buffers or transmission gates, it recommended to use those auto-generated by FPGA-SPICE. It is also recommend to use the transistor sub-circuit (vpr_nmos and vpr_pmos) auto-generated by FPGA-SPICE. In the appendix, we introduce how to use these useful sub-circuits.
+.. note:: If the customized SPICE netlists include inverters, buffers or transmission gates, it is recommended to use those auto-generated by FPGA-SPICE. It is also recommended to use the transistor sub-circuit (vpr_nmos and vpr_pmos) auto-generated by FPGA-SPICE. In the appendix, we introduce how to use these useful sub-circuits.
