[Architecture] Bring back pin equivalence for no local routing architecture
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
- <input name="I0" num_pins="4" equivalent="none"/>
- <input name="I1" num_pins="4" equivalent="none"/>
- <input name="I2" num_pins="4" equivalent="none"/>
- <input name="I3" num_pins="4" equivalent="none"/>
+ <input name="I0" num_pins="4" equivalent="full"/>
+ <input name="I1" num_pins="4" equivalent="full"/>
+ <input name="I2" num_pins="4" equivalent="full"/>
+ <input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
However, current annotation engine does not support this
The feature should be enabled after patching
-->
- <input name="I0" num_pins="4" equivalent="none"/>
- <input name="I1" num_pins="4" equivalent="none"/>
- <input name="I2" num_pins="4" equivalent="none"/>
- <input name="I3" num_pins="4" equivalent="none"/>
+ <input name="I0" num_pins="4" equivalent="full"/>
+ <input name="I1" num_pins="4" equivalent="full"/>
+ <input name="I2" num_pins="4" equivalent="full"/>
+ <input name="I3" num_pins="4" equivalent="full"/>
<output name="O" num_pins="4" equivalent="none"/>
<clock name="clk" num_pins="1"/>
<!-- Describe basic logic element.
