[Arch] Fine tune example arch
<routing_segment>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
- <tile_annotation>
+ <tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
- </tile_annotation>
+ </tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
