[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
<clock_setting>
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
<programming frequency="100e6">
- <clock name="shift_register_clk" port="sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
+ <clock name="bl_shift_register_clk" port="bl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
+ <clock name="wl_shift_register_clk" port="wl_sr_clk[0:0]" frequency="auto" is_shift_register="true"/>
</programming>
</clock_setting>
<simulator_option>
