[Test] Bug fix in the test case using lut adder
@@ -32,7 +32,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
##########################
# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR
bench1_top = adder_8
-bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
+bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
