[Script] Bug fix in slow clock frequency in shift register chain contraints
<openfpga_simulation_setting>
<clock_setting>
<operating frequency="auto" num_cycles="auto" slack="0.2"/>
- <programming frequency="100e6">
+ <programming frequency="10e6">
<clock name="bl_sr_clock" port="bl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
<clock name="wl_sr_clock" port="wl_sr_clk[0:0]" frequency="1.5e9" is_shift_register="true"/>
</programming>
