[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
@@ -40,5 +40,5 @@ bench1_top = adder_8
# The output verilog of yosys is not synthesizable!!!
# Turn off verification for now
# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
-#end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
