bug fix in the Verilog codes for frame decoders
@@ -330,8 +330,8 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
* The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
*/
- fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
- fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << "1'b1) begin" << std::endl;
+ fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
+ fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
fp << "\t\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
/* Create a string for addr and data */
for (size_t i = 0; i < data_size; ++i) {
@@ -340,12 +340,20 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size));
fp << ";" << std::endl;
}
+ /* Different from the MUX encoders, architecture decoders will output all-zero by default!!! */
fp << "\t\t\t" << "default : ";
- fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size));
+ fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size));
fp << ";" << std::endl;
fp << "\t\t" << "endcase" << std::endl;
fp << "\t" << "end" << std::endl;
+ /* If not enabled, we output all-zero */
+ fp << "\t" << "else begin" << std::endl;
+ fp << "\t\t" << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size, data_size)) << ";"<< std::endl;
+ fp << "\t" << "end" << std::endl;
+
+ fp << "end" << std::endl;
+
if (true == decoder_lib.use_data_inv_port(decoder)) {
print_verilog_wire_connection(fp, data_inv_port, data_port, true);
}
