Made activity file independent of power option
@@ -234,9 +234,10 @@ def main():
if (args.fpga_flow == "yosys_vpr"):
logger.info('Running "yosys_vpr" Flow')
run_yosys_with_abc()
- if args.power:
+ # TODO Make it optional if activity file is provided
run_ace2()
run_pro_blif_3arg()
+ if args.power:
run_rewrite_verilog()
if (args.fpga_flow == "vpr_blif"):
collect_files_for_vpr()
@@ -642,13 +643,13 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
"--place_file", args.top_module+"_vpr.place",
"--route_file", args.top_module+"_vpr.route",
"--full_stats", "--nodisp",
+ "--activity_file", args.top_module+"_ace_out.act",
]
if route_only:
command += ["--route"]
# Power options
if args.power:
command += ["--power",
- "--activity_file", args.top_module+"_ace_out.act",
"--tech_properties", args.power_tech]
# packer options
if args.vpr_timing_pack_off:
@@ -700,7 +701,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
command += ["--fpga_spice_testbench_load_extraction", "off"]
# FPGA Verilog options
- if (args.power and args.vpr_fpga_verilog):
+ if args.vpr_fpga_verilog:
command += ["--fpga_verilog"]
if args.vpr_fpga_verilog_dir:
command += ["--fpga_verilog_dir", args.vpr_fpga_verilog_dir]
