Added formal verification support to fpga_flow script
@@ -911,13 +911,23 @@ def run_netlists_verification(exit_if_fail=True):
command = [cad_tools["iverilog_path"]]
command += ["-o", compiled_file]
- command += ["./SRC/%s_include_netlists.v" %
- args.top_module]
+ fpga_define_file = "./SRC/fpga_defines.v"
+ fpga_define_file_bk = "./SRC/fpga_defines.v.bak"
+ shutil.copy(fpga_define_file, fpga_define_file_bk)
+ with open(fpga_define_file, "r") as fp:
+ fpga_defines = fp.readlines()
+
+ command += ["./SRC/%s_include_netlists.v" % args.top_module]
command += ["-s"]
if args.vpr_fpga_verilog_formal_verification_top_netlist:
command += [tb_top_formal]
else:
command += [tb_top_autochecked]
+ with open(fpga_define_file, "w") as fp:
+ for eachLine in fpga_defines:
+ if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or
+ "FORMAL_SIMULATION" in eachLine):
+ fp.write(eachLine)
run_command("iverilog_verification", "iverilog_output.txt", command)
vvp_command = ["vvp", compiled_file]
