[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
@@ -2060,7 +2060,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
- bus_group,
+ BusGroup(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
