sample_arch:move cmos/rram variation to technology library XML nodes
<logic_transistors pn_ratio="2" model_ref="M" vdd="0.9">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
+ <variation abs_variation="0.1" num_sigma="3"/>
</logic_transistors>
<io_transistors pn_ratio="2" model_ref="M" vdd="2.5">
<nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</io_transistors>
- <rram model_name="rram_mem" rlrs="1e4" rhrs="1e5"/>
- <rram model_name="rram_logic" rlrs="5e3" rhrs="20e6"/>
+ <rram model_name="rram_mem" rlrs="1e4" rhrs="1e5">
+ <variation abs_variation="0.1" num_sigma="3"/>
+ </rram>
+ <rram model_name="rram_logic" rlrs="5e3" rhrs="20e6">
+ <variation abs_variation="0.1" num_sigma="3"/>
+ </rram>
</technology>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
</openfpga_architecture>
<openfpga_simulation_setting>
<general sim_temp="25" post="false" captab="false" fast="true"/>
- <monte_carlo mc_sim="false" num_mc_points="2" cmos_variation="false" rram_variation="false">
- <cmos abs_variation="0.1" num_sigma="3"/>
- <rram abs_variation="0.1" num_sigma="3"/>
- </monte_carlo>
+ <monte_carlo mc_sim="false" num_mc_points="2"/>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
