[arch] update out-of-date vpr arch from v1.1 to v1.2
-<!--
+<?xml version="1.0" ?><!--
Architecture with no fracturable LUTs
- 40 nm technology
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
+--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
</model>
</models>
<tiles>
- <tile name="io_top" capacity="8" area="0">
+ <tile name="io_top" area="0"> <sub_tile name="io_top" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<loc side="bottom">io_top[4:5].inpad io_top[2:4].outpad</loc>
<loc side="left">io_top[6:7].inpad io_top[5:7].outpad</loc>
</pinlocations>
- </tile>
- <tile name="io_bottom" capacity="6" area="0">
+ </sub_tile> </tile>
+ <tile name="io_bottom" area="0"> <sub_tile name="io_bottom" capacity="6">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<loc side="bottom">io_bottom[3:3].outpad</loc>
<loc side="left">io_bottom[4:5].outpad io_bottom[4:5].inpad</loc>
</pinlocations>
- </tile>
- <tile name="io_right" capacity="2" area="0">
+ </sub_tile> </tile>
+ <tile name="io_right" area="0"> <sub_tile name="io_right" capacity="2">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<loc side="bottom">io_right[0:0].outpad</loc>
<loc side="left">io_right[1:1].inpad</loc>
</pinlocations>
- </tile>
- <tile name="clb" area="53894">
+ </sub_tile> </tile>
+ <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="spread"/>
- </tile>
+ </sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
