[arch] fixed a bug which caused verification failed
<tile_annotations>
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/>
+ <tile name="io" port="clk"/>
</global_port>
<global_port name="op_reset" is_reset="true" default_val="0">
<tile name="clb" port="reset"/>
+ <tile name="io" port="reset"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
