Simplify part of regression test to min_route_chan_width
@@ -32,21 +32,20 @@ bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_mode
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v
bench0_chan_width = 300
-[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
-fix_route_chan_width=300
-vpr_fpga_verilog_include_icarus_simulator=
-vpr_fpga_verilog_formal_verification_top_netlist=
-vpr_fpga_verilog_include_timing=
-vpr_fpga_verilog_include_signal_init=
-vpr_fpga_verilog_print_autocheck_top_testbench=
-vpr_fpga_bitstream_generator=
-vpr_fpga_verilog_print_user_defined_template=
-vpr_fpga_verilog_print_report_timing_tcl=
-vpr_fpga_verilog_print_sdc_pnr=
-vpr_fpga_verilog_print_sdc_analysis=
-#vpr_fpga_x2p_compact_routing_hierarchy=
-end_flow_with_test=
-
+#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
+#fix_route_chan_width=300
+#vpr_fpga_verilog_include_icarus_simulator=
+#vpr_fpga_verilog_formal_verification_top_netlist=
+#vpr_fpga_verilog_include_timing=
+#vpr_fpga_verilog_include_signal_init=
+#vpr_fpga_verilog_print_autocheck_top_testbench=
+#vpr_fpga_bitstream_generator=
+#vpr_fpga_verilog_print_user_defined_template=
+#vpr_fpga_verilog_print_report_timing_tcl=
+#vpr_fpga_verilog_print_sdc_pnr=
+#vpr_fpga_verilog_print_sdc_analysis=
+##vpr_fpga_x2p_compact_routing_hierarchy=
+#end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
min_route_chan_width=1.3
