[Arch] Update sample arch using local clock from physical tile ports
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotation>
- <global_port tile_port="clb.clk" circuit_port="DFFSRQ.clk"/>
+ <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
</tile_annotation>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
