Update fpgaflow_default_tool_path.conf
Update regex for VPR
@@ -24,8 +24,8 @@ mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
memory_blocks = "Netlist memory blocks: ([0-9]+)", str
logic_delay = "Total logic delay: ([0-9.]+)", str
total_net_delay = "total net delay: ([0-9.]+)", str
-total_routing_area = "Total routing area: ([0-9.]+)", str
-total_logic_block_area = "Total used logic block area: ([0-9]+)", str
+total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str
+total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str
total_wire_length = "Total wirelength: ([0-9]+)", str
packing_time = "Packing took ([0-9.]+) seconds", str
placement_time = "Placement took ([0-9.]+) seconds", str
