Update command_line_usage.rst
@@ -40,7 +40,7 @@ FPGA-SPICE Supported Options::
"--fpga_spice_dir <dir_path>", "Specify the directory that all the SPICE netlists will be outputted to. <dir_path> is the destination directory."
"--fpga_spice_print_top_testbench", "Print the full-chip-level testbench for the FPGA."
"--fpga_spice_print_lut_testbench", "Print the testbenches for all the LUTs."
- "--fpga_spice_print_hardlogic_testbench", "Print the test benches for all the hardlogics."
+ "--fpga_spice_print_hardlogic_testbench", "Print the test benches for all the hard logic."
"--fpga_spice_print_pb_mux_testbench", "Print the testbenches for all the multiplexers in the logic blocks."
"--fpga_spice_print_cb_mux_testbench", "Print the testbenches for all the multiplexers in Connection Boxes."
"-- fpga_spice_print_sb_mux_testbench", "Print the testbenches for all the multiplexers in Switch Blocks."
@@ -55,4 +55,4 @@ FPGA-SPICE Supported Options::
"--fpga_spice_testbench_load_extraction_off", "Turn off the load effect on net estimation technique."
"--fpga_spice_sim_mt_num <int>", "Set the number of multi-thread used in simulation"
-.. note:: The parasitic net estimation technique is used to analyze the parasitic net activities which improves the accuracy of power analysis. When turned off, the errors between the full-chip-level and grid/component-level testbenches will increase."
+.. note:: The parasitic net estimation technique is used to analyze the parasitic net activities which improve the accuracy of power analysis. When turned off, the errors between the full-chip-level and grid/component-level testbenches will increase."
