refine the test case for load external arch bitstream
@@ -13,7 +13,7 @@ power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
-fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga
@@ -25,10 +25,17 @@ openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_b
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
[SYNTHESIS_PARAM]
-bench0_top = and2
+bench0_top = or2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
+########################
+# Use a different verilog as reference here
+# This verilog is consistent with the external architecture bitstream generated above
+# As such, we can test if the bitstream database is indeed overwritten by another benchmark
+# which is different than the one given to VPR
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
