reorganize and clean-up sample architecture
</circuit_library>
</openfpga_architecture>
<openfpga_simulation_setting>
- <general sim_temp="25" post="false" captab="false" fast="true"/>
- <monte_carlo mc_sim="false" num_mc_points="2"/>
- <measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
+ <clock_setting>
+ <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
+ <programming frequency="10e6"/>
+ </clock_setting>
+ <simulator_option>
+ <operating_condition temperature="25"/>
+ <output_log post="false" captab="false"/>
+ <accuracy type="abs" value="1e-13"/>
+ <runtime fast_simulation="true"/>
+ </simulator_option>
+ <monte_carlo num_simulation_points="2"/>
+ <measurement_setting>
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
- </measure>
- <stimuli>
- <clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
+ </measurement_setting>
+ <stimulus>
+ <stimuli type="clock">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
- </clock>
- <input>
+ </stimuli>
+ <stimuli type="input">
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
- </input>
</stimuli>
+ </stimulus>
</openfpga_simulation_setting>
