update documentation on circuit model annotation on VPR architecture
@@ -250,18 +250,30 @@ A circuit model may consist of a number of ports. The port list is mandatory in
- ``type="input|output|sram|clock"`` Specify the type of the port, i.e., the directionality and usage. For programmable modules, such as multiplexers and LUTs, SRAM ports MUST be defined. For registers, such as FFs and memory banks, clock ports MUST be defined.
+ .. note:: ``sram`` and ``clock`` ports are considered as inputs in terms of directionality
+
- ``prefix="<string>"`` the name of the port to appear in the autogenerated netlists. Each port will be shown as ``<prefix>[i]`` in Verilog/SPICE netlists.
+ .. note:: if the circuit model is binded to a ``pb_type`` in VPR architecture, ``prefix`` must match the port name defined in ``pb_type``
+
- ``lib_name="<string>"`` the name of the port defined in standard cells or customized cells. If not specified, this attribute will be the same as ``prefix``.
+ .. note:: if the circuit model comes from a standard cell library, using ``lib_name`` is recommended. This is because
+ - the port names defined in ``pb_type`` are very diffrerent from the standard cells
+ - the port sequence is very different
+
- ``size="<int>"`` bandwidth of the port. MUST be larger than zero.
- ``default_val="<int>"`` Specify default logic value for a port, which is used as the initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
- ``circuit_model_name="<string>"`` Specify the name of the circuit model which is connected to this port.
+ .. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
+
- ``mode_select="true|false"`` Specify if this port controls the mode switching in a configurable logic block. This is due to that a configurable logic block can operate in different modes, which is controlled by SRAM bits.
+ .. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
+
- ``is_global="true|false"`` can be either ``true`` or ``false``. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
- ``is_set="true|false"`` Specify if this port controls a set signal. All the set ports are connected to global set voltage stimuli in testbenches.
@@ -270,12 +282,6 @@ A circuit model may consist of a number of ports. The port list is mandatory in
- ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
-.. note:: ``sram`` and ``clock`` ports are considered as inputs in terms of directionality
-
-.. note:: ``circuit_model_name`` is only valid when the type of this port is ``sram``.
-
-.. note:: ``mode_select`` is only valid when the type of this port is ``sram``.
-
.. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``.
.. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.
