[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
@@ -4,4 +4,4 @@ ${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -top ${TOP_MODULE} ${YOSYS_ARGS}
-write_verilog -noattr -nohex ${TOP_MODULE}.v
\ No newline at end of file
+write_verilog -noattr -nohex ${OUTPUT_VERILOG}.v
