[Test] Added the new test cases to regression tests
@@ -136,3 +136,7 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
echo -e "Testing through channels in tileable routing";
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
+
+echo -e "Testing the generation of preconfigured fabric wrapper for different HDL simulators";
+run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --show_thread_logs
+run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs
