fine tune mcnc example script to run Modelsim simulations easily
@@ -37,7 +37,11 @@ build_fabric_bitstream --verbose
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC \
+ --explicit_port_mapping \
+ --include_timing \
+ --include_signal_init
+ #--support_icarus_simulator
# Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists
