[Arch] Add a dummy adder lut circuit model to support HDL simulation
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="DFFRQ" default_val="1"/>
</circuit_model>
+ <!-- dummy circuit model pointer.
+ The idea is just to include the netlist for HDL simulation
+ TODO: This feature SHOULD be supported as an option in write_verilog_testbench command
+ The key idea here is that the openfpga arch XML should focus on physical design aspects
+ Anything related to simulation should be classified in the simulation settings or shell script
+ -->
+ <!-- A dummy model to include the adder_lut verilog code in testbench netlists
+ so that HDL simulation can be run when adder lut is used in users' implementations
+ -->
+ <circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v">
+ <design_technology type="cmos" topology="inverter" size="1"/>
+ </circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>
