[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
@@ -13,7 +13,12 @@ power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
-fpga_flow=yosys_vpr
+# Due to the limitation in ACE2 which cannot output .blif files
+# with correct multi-clock assignments to .latch lines
+# We have to use the vpr_blif flow where the .blif is modified
+# based on yosys outputs with correct clock assignment!
+# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
+fpga_flow=vpr_blif
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
@@ -24,11 +29,14 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
[BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.blif
[SYNTHESIS_PARAM]
bench0_top = counter_2clock
+bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.act
+bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
