[HDL] Now dual-clock counter has only 1 reset pin
module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
input clk0;
- input rst0;
+ input rst;
output [3:0] q0;
reg [3:0] q0;
input clk1;
- input rst1;
output [3:0] q1;
reg [3:0] q1;
@@ -17,7 +16,7 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
always @ (posedge clk0)
begin
- if(rst0)
+ if(rst)
q0 <= 4'b0000;
else
q0 <= q0 + 1;
@@ -25,7 +24,7 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
always @ (posedge clk1)
begin
- if(rst1)
+ if(rst)
q1 <= 4'b0000;
else
q1 <= q1 + 1;
