[Flow] Add comments for the design constraint file
<repack_pin_constraints>
+ <!-- For a given .blif file, we want to assign
+ - the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
+ - the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
+ and ensure no signals could be mapped to
+ - the clk[2] port of all the clb tiles available in the FPGA fabric
+ - the clk[3] port of all the clb tiles available in the FPGA fabric
+ -->
<pin_constraint tile="clb" name="clk[0]" net="clk0"/>
<pin_constraint tile="clb" name="clk[1]" net="clk1"/>
+ <pin_constraint tile="clb" name="clk[2]" net="OPEN"/>
+ <pin_constraint tile="clb" name="clk[3]" net="OPEN"/>
</repack_pin_constraints>
