[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
@@ -464,9 +464,6 @@ void print_verilog_gate_module(const ModuleManager& module_manager,
/* Print timing info */
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
- /* Print signal initialization */
- print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
-
/* Put an end to the Verilog module */
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
}
