bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
@@ -68,18 +68,18 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
// Connect to x-channel wires
unsigned num_wires_x = x_wire_indices.size() * fc;
for (size_t i = 0; i < num_wires_x; i++) {
- rr_graph.create_edge(x_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
+ rr_graph.create_edge(x_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx), true);
}
// Connect to y-channel wires
unsigned num_wires_y = y_wire_indices.size() * fc;
for (size_t i = 0; i < num_wires_y; i++) {
- rr_graph.create_edge(y_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx));
+ rr_graph.create_edge(y_wire_indices[i], clock_index, RRSwitchId(rr_switch_idx), true);
}
// Connect to virtual clock sink node
// used by the two stage router
- rr_graph.create_edge(clock_index, virtual_clock_network_root_idx, RRSwitchId(rr_switch_idx));
+ rr_graph.create_edge(clock_index, virtual_clock_network_root_idx, RRSwitchId(rr_switch_idx), true);
}
}
@@ -183,7 +183,7 @@ void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_gr
if (from_itter == from_rr_node_indices.end()) {
from_itter = from_rr_node_indices.begin();
}
- rr_graph.create_edge(*from_itter, to_index, RRSwitchId(rr_switch_idx));
+ rr_graph.create_edge(*from_itter, to_index, RRSwitchId(rr_switch_idx), true);
from_itter++;
}
}
@@ -292,7 +292,7 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
//Create edges depending on Fc
for (size_t i = 0; i < clock_network_indices.size() * fc; i++) {
- rr_graph.create_edge(clock_network_indices[i], clock_pin_node_idx, RRSwitchId(rr_switch_idx));
+ rr_graph.create_edge(clock_network_indices[i], clock_pin_node_idx, RRSwitchId(rr_switch_idx), true);
}
}
}
