[debug] Enable all thread backtrace for RISC-V
@@ -11,10 +11,14 @@ class Context():
's0', 's1', 's2', 's3', 's4', 's5', 's6', 's7',
't8', 't9', 'k0', 'k1', 'gp', 'sp', 's8', 'ra',
'lo', 'hi', 'cause', 'pc', 'sr', 'bad'],
- 'aarch64': ['x0', 'x1', 'x2', 'x3', 'x4', 'x5', 'x6', 'x7',
- 'x8', 'x9', 'x10', 'x11', 'x12', 'x13', 'x14', 'x15',
- 'x16', 'x17', 'x18', 'x19', 'x20', 'x21', 'x22', 'x23',
- 'x24', 'x25', 'x26', 'x27', 'x28', 'x29', 'lr', 'sp', 'pc']
+ 'aarch64': ['x0', 'x1', 'x2', 'x3', 'x4', 'x5', 'x6', 'x7', 'x8',
+ 'x9', 'x10', 'x11', 'x12', 'x13', 'x14', 'x15', 'x16',
+ 'x17', 'x18', 'x19', 'x20', 'x21', 'x22', 'x23', 'x24',
+ 'x25', 'x26', 'x27', 'x28', 'x29', 'lr', 'sp', 'pc'],
+ 'riscv': ['ra', 'sp', 'gp', 'tp', 't0', 't1', 't2', 's0', 's1', 'a0',
+ 'a1', 'a2', 'a3', 'a4', 'a5', 'a6', 'a7', 's2', 's3', 's4',
+ 's5', 's6', 's7', 's8', 's9', 's10', 's11', 't3', 't4', 't5',
+ 't6', 'pc'],
}
def __init__(self):
@@ -25,6 +29,10 @@ class Context():
if arch_name.startswith('aarch64'):
self.arch = 'aarch64'
self.reg_size = 64
+ if arch_name.startswith('riscv'):
+ prefix_len = len('riscv:rv')
+ self.arch = 'riscv'
+ self.reg_size = int(arch_name[prefix_len:prefix_len+2])
self.regs = OrderedDict()
for name in self.names[self.arch]:
self.regs[name] = 0
