[test] relax minW for counter128, as VPR's router degrades in routability
@@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
# VPR parameters
# # Use a fixed routing channel width to save runtime
-vpr_route_chan_width=60
+vpr_route_chan_width=80
openfpga_vpr_pack_stats_file=vpr_pack_block_usage.txt
[ARCHITECTURES]
