[arch] upgrade arch file which was designed for v1.1
-<!--
+<?xml version="1.0" ?><!--
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
- 40 nm technology
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Authors: Xifan Tang
--->
-<architecture>
+--><architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
- <tile name="io" capacity="8" area="0">
+ <tile name="io" area="0"> <sub_tile name="io" capacity="8">
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
- </tile>
- <tile name="clb" area="53894">
+ </sub_tile> </tile>
+ <tile name="clb" area="53894"> <sub_tile name="clb">
<equivalent_sites>
<site pb_type="clb"/>
</equivalent_sites>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
- </tile>
+ </sub_tile> </tile>
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
