[Arch] Patch arch using DPRAM block with wide = 2
<loc side="left" yoffset="0">memory.clk memory.waddr[0:1] memory.raddr[0:1] memory.data_in[0:0] memory.data_out[0:0]</loc>
<loc side="left" yoffset="1">memory.waddr[2:3] memory.raddr[2:3] memory.data_in[1:1] memory.data_out[1:1]</loc>
<loc side="top" xoffset="0" yoffset="1">memory.waddr[4:5] memory.raddr[4:5] memory.data_in[2:2] memory.data_out[2:2]</loc>
- <loc side="top" xoffset="0" yoffset="1">memory.waddr[6:7] memory.raddr[6:7] memory.data_in[3:3] memory.data_out[3:3]</loc>
+ <loc side="top" xoffset="1" yoffset="1">memory.waddr[6:7] memory.raddr[6:7] memory.data_in[3:3] memory.data_out[3:3]</loc>
<loc side="right" xoffset="1" yoffset="0">memory.waddr[8:8] memory.raddr[8:8] memory.data_in[4:4] memory.data_out[4:4]</loc>
<loc side="right" xoffset="1" yoffset="1">memory.waddr[9:9] memory.raddr[9:9] memory.data_in[5:5] memory.data_out[5:5]</loc>
<loc side="bottom" xoffset="0">memory.wen memory.waddr[10:10] memory.raddr[10:10] memory.data_in[6:6] memory.data_out[6:6]</loc>
