[test] remove verification steps for new test but leave a todo
@@ -39,5 +39,6 @@ bench0_top = clk_divider
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=
+# FIXME: Enable this once VPR can accept clock routing for specific clock signals
+#end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=
