add bitstream file format introduction
Bistream Output File Format
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-**Under Construction**
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+FPGA-Bitstream can generate two types of bitstreams:
+* Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information:
+ - ``hierarchy`` represents the location of this block in FPGA fabric.
+ - ``bitstream`` represents the configuration bits affiliated to this block.
+
+.. code-block:: xml
+
+ <bitstream_block index="0">
+ <hierarchy>
+ <instance level="0" name="fpga_top"/>
+ <instance level="1" name="grid_clb_1_1"/>
+ <instance level="2" name="fle_0"/>
+ <instance level="3" name="lut4_0"/>
+ </hierarchy>
+ <bitstream>
+ <bit memory_port="mem_out[0]" value="1"/>
+ <bit memory_port="mem_out[1]" value="0"/>
+ <bit memory_port="mem_out[2]" value="1"/>
+ <bit memory_port="mem_out[3]" value="0"/>
+ <bit memory_port="mem_out[4]" value="1"/>
+ <bit memory_port="mem_out[5]" value="0"/>
+ <bit memory_port="mem_out[6]" value="1"/>
+ <bit memory_port="mem_out[7]" value="0"/>
+ <bit memory_port="mem_out[8]" value="1"/>
+ <bit memory_port="mem_out[9]" value="0"/>
+ <bit memory_port="mem_out[10]" value="1"/>
+ <bit memory_port="mem_out[11]" value="0"/>
+ <bit memory_port="mem_out[12]" value="1"/>
+ <bit memory_port="mem_out[13]" value="0"/>
+ <bit memory_port="mem_out[14]" value="1"/>
+ <bit memory_port="mem_out[15]" value="0"/>
+ </bitstream>
+ </bitstream_block>
+
+* Fabric-dependent bitstreams, where configuration bits are organized to be loadable to the configuration protocols of FPGAs. The bitstream just sets an order to the configuration bits in the database, without duplicating the database. OpenFPGA framework provides a fabric-dependent bitstream generator which is aligned to our Verilog netlists. The fabric-dependent bitstream can be found in autogenerated Verilog testbenches.
