[test] fixed remaining bugs
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
-read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+read_verilog ${READ_VERILOG_OPTIONS} ${YOSYS_CELL_SIM_VERILOG}
# Technology mapping
hierarchy -top ${TOP_MODULE}
