update documentation on a new option in FPGA-SDC to constrain zero-delay paths
@@ -192,6 +192,10 @@ FPGA-SDC
- ``--constrain_switch_block_outputs`` Constrain all the outputs of switch blocks of FPGA fabric
+ - ``--constrain_zero_delay_paths`` Constrain all the zero-delay paths in FPGA fabric
+
+ .. note:: Zero-delay path may cause errors in some PnR tools as it is considered illegal
+
- ``--verbose`` Enable verbose output
.. option:: write_analysis_sdc
