Lighten the regression test
@@ -63,18 +63,3 @@ vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT]
-fix_route_chan_width=300
-vpr_fpga_verilog_include_icarus_simulator=
-vpr_fpga_verilog_formal_verification_top_netlist=
-vpr_fpga_verilog_include_timing=
-vpr_fpga_verilog_include_signal_init=
-vpr_fpga_verilog_print_autocheck_top_testbench=
-vpr_fpga_bitstream_generator=
-vpr_fpga_verilog_print_user_defined_template=
-vpr_fpga_verilog_print_report_timing_tcl=
-vpr_fpga_verilog_print_sdc_pnr=
-vpr_fpga_verilog_print_sdc_analysis=
-#vpr_fpga_x2p_compact_routing_hierarchy=
-end_flow_with_test=
