add vpr test run in Travis
@@ -18,6 +18,8 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
+./vpr7_x2p/vpr/vpr ./openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif --net_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.net --place_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.place --route_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4n4_test_vpr.route --full_stats --nodisp --activity_file ./openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act --power --tech_properties ./openfpga_flow/tech/PTM_45nm/45nm.xml --fpga_x2p_compact_routing_hierarchy --fpga_verilog --fpga_verilog_dir ./verilog --fpga_verilog_print_autocheck_top_testbench K4n4_test_output_verilog.v --fpga_verilog_include_timing --fpga_verilog_explicit_mapping --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --fpga_verilog_print_sdc_pnr --fpga_verilog_print_user_defined_template --fpga_verilog_print_sdc_analysis --fpga_bitstream_generator --fpga_x2p_rename_illegal_port
+
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298
