[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
@@ -30,12 +30,12 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
[SYNTHESIS_PARAM]
bench1_top = adder_8
-bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
+bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
##########################
# The output verilog of yosys is not synthesizable!!!
# Turn off verification for now
# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
-#end_flow_with_test=
-#vpr_fpga_verilog_formal_verification_top_netlist=
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
