[test] still commment verification out
@@ -40,5 +40,5 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.x
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
# FIXME: Enable this once VPR can accept clock routing for specific clock signals
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=
+#end_flow_with_test=
+#vpr_fpga_verilog_formal_verification_top_netlist=
