[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
@@ -65,27 +65,10 @@ void print_verilog_preconfig_top_module_ports(std::fstream &fp,
}
std::string block_name = atom_ctx.nlist.block_name(atom_blk);
- /* If the pin is part of a bus,
- * - Check if the bus is already in the list
- * - If not, add it to the port list
- * - If yes, do nothing and move onto the next port
- * If the pin does not belong to any bus
- * - Add it to the bus port
- */
- BusGroupId bus_id = bus_group.find_pin_bus(block_name);
- if (bus_id) {
- if (port_list.end() == std::find(port_list.begin(), port_list.end(), bus_group.bus_port(bus_id))) {
- port_list.push_back(bus_group.bus_port(bus_id));
- port_types.push_back(atom_ctx.nlist.block_type(atom_blk));
- }
- continue;
- }
-
/* The block may be renamed as it contains special characters which violate Verilog syntax */
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
-
/* For output block, remove the prefix which is added by VPR */
std::vector<std::string> output_port_prefix_to_remove;
output_port_prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
@@ -101,6 +84,22 @@ void print_verilog_preconfig_top_module_ports(std::fstream &fp,
}
}
+ /* If the pin is part of a bus,
+ * - Check if the bus is already in the list
+ * - If not, add it to the port list
+ * - If yes, do nothing and move onto the next port
+ * If the pin does not belong to any bus
+ * - Add it to the bus port
+ */
+ BusGroupId bus_id = bus_group.find_pin_bus(block_name);
+ if (bus_id) {
+ if (port_list.end() == std::find(port_list.begin(), port_list.end(), bus_group.bus_port(bus_id))) {
+ port_list.push_back(bus_group.bus_port(bus_id));
+ port_types.push_back(atom_ctx.nlist.block_type(atom_blk));
+ }
+ continue;
+ }
+
/* Both input and output ports have only size of 1 */
BasicPort module_port(std::string(block_name), 1);
port_list.push_back(module_port);
