copy yosys output file in case power analysis setting is off
@@ -261,6 +261,8 @@ def main():
run_ace2()
run_pro_blif_3arg()
run_rewrite_verilog()
+ else:
+ shutil.copy(args.top_module+'_yosys_out.blif', args.top_module+".blif")
if (args.fpga_flow == "vpr_blif"):
collect_files_for_vpr()
logger.info("Runing OpenFPGA Shell Engine ")
