text: Contacts Of Silicides Patents and Patent Applications (Class 148/DIG19) - Justia Patents Search
  Justia Patents Metal Treatment Patents Contacts Of Silicides Patents (Class 148/DIG19)
  Contacts Of Silicides Patents (Class 148/DIG19)
  Abstract: The invention provides a novel method, in which self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process. The method is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. That is, this invention provides a self-aligned local-interconnect and contact (SALIC) method for a logic technology to forming the self-aligned, borderless contacts, and local interconnects (LI) simultaneously.
  Inventor: Shih-Wei Sun
  Patent number: 5837608
  Assignee: Hyundai Electronics Industries Co.,
  Raised silicided source/drain electrode formation with reduced substrate silicon consumption
  Patent number: 5830775
  Abstract: A method is provided for forming silicided source/drain electrodes in active devices wherein the electrodes have very thin junction regions. In the process silicidation material is deposited on the wafer and rapid-thermal-annealed at a temperature and for a time calculated to produce metal-rich or silicon-deficient silicide on the electrodes. The metal-rich or silicon-deficient silicide is selectively formed on the semiconductor electrodes and not on oxide or other insulating surfaces. A selective etch removes the silicidation material which has not reacted with silicon, including metal overlying insulating surfaces. Then, after cleaning the silicide surfaces, a layer of silicon is deposited over the structure and a second rapid thermal anneal is performed at a higher temperature than the first rapid thermal anneal.
  Inventors: Jer-shen Maa, Shen Teng Hsu
  Method of manufacturing a raised source/drain MOSFET
  Patent number: 5824586
  Abstract: A method of manufacturing a raised source/drain MOSFET by depositing amorphous silicon on the partially formed MOSFET having the gate and gate oxide spacers formed, ion implanting to form the appropriate source/drain junctions, annealing wherein epitaxial growth takes place in regions where the amorphous silicon is over silicon, and etching the remaining amorphous silicon. A layer of refractory metal is deposited and a second anneal converts the refractory metal overlaying silicon to silicide.
  Inventors: Donald L. Wollesen, Deepak Nayak
  Method of making a semiconductor device having high density 4T SRAM in logic with salicide process
  Patent number: 5719079
  Abstract: A method of forming a local interconnect in an SRAM, simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, is described. A semiconductor substrate on which MOS (Metal Oxide Semiconductor) transistors have been formed is provided. The transistors are separated by field isolation regions, and each transistor has a gate overlying a gate oxide and has source and drain regions in the substrate. Spacers are provided on the sidewalls of the gates, and some of the field oxide regions in the SRAM have polysilicon interconnects, with sidewall spacers. The sidewall spacers are removed from the polysilicon interconnects. A layer of titanium is deposited over the semiconductor substrate. A salicide is formed over the gates, the source and drain regions, and the polysilicon interconnects, so that the local interconnect is formed connecting the polysilicon interconnects to one of the source regions.
  Inventors: Chue-San Yoo, Mong-Song Liang, Jin-Yuan Lee
  Method of fabricating a buried contact structure for SRAM
  Patent number: 5580806
  Abstract: A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect layer. A silicide layer is formed on the sidewall of the interconnect layer. The silicide layer connects a buried contact region with the interconnect layer to make electrical contact between the interconnect layer and a source/drain region.
  Inventors: Tsun-Tsai Chang, Ming-Tsung Liu
  Patent number: 5567642
  Abstract: A method of fabricating a gate electrode of a CMOS device is disclosed including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive layer on the overall surface of said substrate; removing the second conductive layer formed on the protective layer, and partially etching the protective layer to a predetermined thickness; and patterning the second conductive layer, the protective layer, the first conductive layer and the gate insulating layer using a gate electrode pattern.
  Inventors: Hyeon S. Kim, Choong H. Lee
  Process for forming titanium silicide local interconnect
  Patent number: 5543361
  Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.
  Inventors: Steven S. Lee, Kenneth P. Fuchs, Gayle W. Miller
  Method of making a semiconductor device using a titanium-rich silicide film
  Patent number: 5525543
  Abstract: In a method of forming an adhesive layer for a blanket layer filling a contact hole in a semiconductor device, a Ti film, Ti-rich TiN film or a TiSi.sub.x (x being 1.1 to 1.8) film is formed, and then a TiN (stoichiometric) film is formed. The Ti film, Ti-rich TiN film or TiSi.sub.x is annealed to be converted into TiSi.sub.2 film. The formation of the Ti film, Ti-rich TiN film or a TiSi.sub.x is performed by a continuous CVD process.
  Inventor: Shih-Chang Chen
  Patent number: 5470794
  Method of forming silicide in integrated circuit manufacture
  Patent number: 5461005
  Abstract: Electrical discontinuities in a silicide formed on a patterned surface are prevented by forming metal fillets in the recesses of the patterned polysilicon covered surface, and then depositing a metal layer and reacting with silicon to form the silicide. The fillet provides extra metal at a place where there is typically a deficiency in conventional deposition techniques.
  Inventors: Ajit Manocha, Sailesh M. Merchant, Ranbir Singh
  Patent number: 5444024
  Abstract: A method is provided for controlling growth of silicide to a defined thickness based upon the relative position of peak concentration density depth within a layer of titanium. The titanium layer is deposited over silicon and namely over the silicon junction regions. Thereafter the titanium is implanted with argon ions. The argon ions are implanted at a peak concentration density level corresponding to a depth relative to the upper surface of the titanium. The peak concentration density depth can vary depending upon the dosage and implant energies of the ion implanter. Preferably, the peak concentration density depth is at a midpoint between the upper and lower surfaces of the titanium or at an elevational level beneath the midpoint and above the lower surface of the titanium. Subsequent anneal of the argon-implanted titanium causes the argon atoms to occupy a diffusion area normally taken by silicon consumed and growing within overlying titanium.
  Patent number: 5432129
  Abstract: A thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi.sub.2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists.
  Inventor: Robert L. Hodges
  Patent number: 5418179
  Abstract: An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.
  Inventor: Tadahiko Hotta
  Patent number: 5397744
  Abstract: A metallization method in which a fine interconnection hole is filled with an Al-based material and in which low resistance and excellent barrier properties may be achieved simultaneously, is proposed. The present invention resides in improvement in the barrier metal structure. (a) A stack of a TiSi.sub.2 layer and a Ti layer, formed by an modified SALICIDE method, and (b) a layer of a Ti-based material rendered amorphous are used. The TiSi.sub.2 layer is formed in a self-aligned manner by reacting the silicon substrate with the Ti layer by the interposition of e.g. a thin SiO.sub.2 layer and exhibits lower sheet resistance and dense film properties as well as excellent barriering properties. The Ti layer is stacked on the TiSi.sub.2 layer for improving wettability with respect to the layer of the Al-based material. The layer of the amorphous Ti-based material is formed by N.sub.
  Inventors: Hirofumi Sumi, Yukiyasu Sugano
  Method for forming local interconnect for integrated circuits
  Patent number: 5391520
  Abstract: A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed.
  Inventors: Fusen Chen, Fu-Tai Liou, Girish Dixit
  Method for fabricating titanium silicide contacts
  Patent number: 5369055
  Abstract: A method for fabricating titanium silicide contacts wherein prior to a Ti sputtering process, ions having a conductivity opposite to the conductivity of source and drain regions on each well are implanted in the source and drain regions by using the same mask as used in the Ti sputtering process, so as to form low concentration regions at contact surfaces and high concentration regions at regions beneath the contact surfaces.
  Inventor: Ji H. Chung
  Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation
  Patent number: 5344793
  Abstract: An method of providing defect enhanced CoSi2 formation and improved silicided junctions in deep submicron MOSFETs. A silicon wafer having a diffusion window is first precleaned with hydrofluoric acid. After the HF precleaning, the silicon wafer is transferred to a conventional cobalt sputtering tool where it is sputter cleaned by bombardment with low energy Ar+ ions so as to form an ultra-shallow damage region. After the sputter cleaning, and without removing the wafer from the sputtering tool, Cobalt metal is deposited on the silicon wafer at room temperature and a CoSi2 layer is formed in the diffusion window.
  Inventors: Heinrich Zeininger, Christoph Zeller, Udo Schwalke, Uwe Doebler, Wilfried Haensch
  Silicide interconnection with Schottky barrier diode isolation
  Patent number: 5336637
  Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.
  Patent number: 5332692
  Abstract: A sputtering technique is conducted within a sputtering device the inside of which is in the state of vacuum, whereby a second polycrystal silicon film (7) is deposited on a first polycrystal silicon film (3) on the surface of which a natural oxide film (4) exists. The inside of the sputtering device is maintained to be in the state of vacuum after the second polycrystal silicon film (7) is formed. With the same sputtering device, a metal silicide film (5) is deposited on the second polycrystal film under vacuum. When a silicon oxide film is formed on the silicide film, silicons to be oxidized are uniformly supplied through the silicide film. Therefore, the polycrystal silicon film and the silicide film are not separated from each other at the boundary face between them. Further, product yield rate is improved since it is not necessary to perform sputter etching.
  Inventor: Kenji Saitoh
  Oxide-capped titanium silicide formation
  Patent number: 5326724
  Abstract: A titanium nitride layer is deposited between the metal titanium layer and the oxide cap of a conventional oxide capped titanium disilicide technology process. This titanium nitride layer is deposited in-situ after a certain thickness of metal titanium has been deposited by bleeding nitrogen gas into the titanium sputter machine. Thereafter the normal oxide cap is deposited over this titanium nitride layer. The normal titanium react process is performed to produce titanium disilicide. After the titanium disilicide has been produced, it is then necessary to strip off the oxide cap. The extra titanium nitride layer makes it is possible to use a wet etch to remove the oxide cap, with the titanium nitride layer serving as a etch stop. In this manner an isotropic wet etch may be employed to remove all of the oxide cap layer. The isotropic wet etch is preferably a 10% buffered HF etch.
  Method of manufacturing a semiconductor device comprising metal silicide
  Patent number: 5316977
  Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transitition layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere.
  Inventors: Iwao Kunishima, Kyoichi Suguro
  Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed
  Patent number: 5302552
  Abstract: A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semiconductor body (1) is heated during a heat treatment to a temperature at which the Co or Ni forms a metal silicide with the silicon (3, 4, 5, 6), but not with the insulating material (8, 9). On the surface (2) of the layer (12) containing the Co or Ni, according to the invention, a layer of an amorphous alloy of this metal with a metal from a group comprising Ti, Zr, Ta, Mo, Nb, Hf and W is deposited, while furthermore the temperature is so adjusted during the heat treatment that the layer (12) of the amorphous alloy remains amorphous during the heat treatment.
  Inventors: Johan P. W. B. Duchateau, Alec H. Reader, Gerrit J. Van Der Kolk
  Patent number: 5236852
  Abstract: An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).
  Inventors: Michael Cherniawski, Jeffrey M. Barker, Ronald E. Pyle, Vidya S. Kaushik
  Patent number: 5231056
  Abstract: A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with a silane source gas followed by deposition of the tungsten silicide film with a dichlorosilane source gas. This two step process allows dichlorosilane to be used as a silicon source gas for depositing a tungsten silicide film at a lower temperature than would otherwise by possible and without plasma enhancement. Tungsten silicide films deposited by this process are characterized by low impurities, good step coverage, and low stress with the silicon substrate.
  Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
  Patent number: 5227316
  Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base region to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.
  Inventors: Madhukar Vora, Greg Burton, Ashok Kapoor
  Method for forming shallow junctions with a low resistivity silicide layer
  Patent number: 5217924
  Abstract: A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (42) into or through the first layer (38). A relatively thick second layer (48) of metal is deposited over the first layer (38). An anneal process (50) is then performed to out-diffuse the impurities (40) from the first layer (38) into the substrate (32). The anneal also forms a combined metal silicide (52) from the first layer (38) and the second layer (48). The junction (56) thus formed has less surface damage, reduced spiking and reduced implant straggle than junctions formed according to the prior art. An alternate technique is also disclosed wherein an implant into or through a silicide layer is utilized.
  Inventors: Mark S. Rodder, Robert H. Havemann
  Abstract: A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.
  Inventors: Been-Jon K. Woo, Gregory Atwood, Stefan K. C. Lai, T. C. Ong
  Semiconductor device having punch-through protected buried contacts and method for making the same
  Patent number: 5208168
  Abstract: Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.
  Inventors: Louis C. Parrillo, Neil B. Henis, Richard W. Mauntel
  Patent number: 5206187
  Abstract: A method of processing a semiconductor wafer comprises: a) fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations of the wafer; b) providing a layer of transition metal oxide elevationally above the active regions; c) applying an insulating dielectric layer elevationally above the transition metal oxide layer; d) etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and e) etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
  Patent number: 5187122
  Abstract: A process for fabricating a semiconductor device using local silicide interconnection lines make it possible to fabricate an integrated circuit having a plurality of electronic elements disposed on a semi-conductor substrate. The electronic elements are formed on the substrate such that they are grouped into a first region and a second region adjacent to the first region, each of these regions having predetermined conductivities. The first region has a layer of dielectric material disposed upon it with at least one capacitive element disposed on the dielectric layer. The capacitive element includes a first electrode layer and a second electrode layer. The second region has at least one double junction metal-insulator semi-conductor field effect transistor (MISFET) located therein. The MISFET includes at least three regions, a gate region and two active regions, a source region and a drain region.
  Inventor: Maurice Bonis
  Patent number: 5173450
  Abstract: A TiSi.sub.2 LI process solves the problems of poor junction integrity and rapid dopant outdiffusion by adding a second titanium deposition on the amorphous silicon/titanium stack and reducing the initial titanium thickness to its minimum required value for amorphous silicon etch stop. Referring to FIG. 5 of the drawings, titanium layer 60 reacts at exterior surface 58 of sidewall oxide 59 to form TiN layer 57. Layer 57 acts to stop outdiffusion of silicon into the second titanium layer 60. This second titanium deposition on the amorphous silicon/titanium stack minimizes differential TiSi.sub.2 formations because the silicon selected in TiSi.sub.2 formation originates from amorphous silicon layer 54, rather than from the source region 22 or drain region 23, resulting in better junction integrity. This process saves up to 25% of the area otherwise required in contacts for SRAMS, yielding much improved packing density.
  Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
  Patent number: 5162262
  Abstract: An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a secondary refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.
  Inventors: Natsuo Ajika, Hideaki Arima
  Patent number: 5162263
  Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further comprises metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate. The method also includes cooling the top of the substrate to form a temperature gradient that results in increased dopant concentration at the bottom of a silicide layer.
  Inventors: Iwao Kunishima, Tomonori Aoyama, Kyoichi Suguro
  Patent number: 5151387
  Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.
  Inventors: James Brady, Tsiu C. Chan, David S. Culver
  Method of forming self-aligned contacts in a semiconductor process
  Patent number: 5134083
  Abstract: A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface.
  Inventor: James A. Matthews
  Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method
  Patent number: 5108954
  Abstract: Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
  Inventors: Gurtej S. Sandhu, Mohammed Anjum
  Patent number: 5081065
  Abstract: Disclosed is a method of contacting a metal silicide pattern on an integrated semiconductor circuit which is provided with a planarized dielectric layer. A silicide-forming metal layer (9), preferably a titanium layer, is provided on the surface of a silicon substrate having a field oxide patter (2) which is provided with a conductor pattern (4) of silicon. A layer (10) of amorphous (a-) silicon is provided locally on this metal layer to form "straps". The entire device is heated in a nitrogen-containing atmosphere, by which the metal layer (9) is converted at least partly into metal silicide (12). A dielectric layer (13), for example of silicon oxide, is provided over the entire surface. The layer (13) is planarized and provided with contact windows (15) on the metal silicide by etching, after which a metallization (16) is provided.
  Inventors: Alexander G. M. Jonkers, Christopher A. Seams, Harald Godon, Andre Stolmeijer
  Method for forming a silicide film used in a semiconductor chip
  Patent number: 5081066
  Abstract: A method for forming a silicide film on a conducting layer in a semiconductor device is disclosed. The method comprises providing a semiconductor device having a first conducting layer of a doped silicon. A second conducting layer of an undoped silicon is deposited on the first conducting layer. A metal layer on the second conducting layer and the metal layer is heated to cause it to react with the second conducting layer formed with undoped silicon, thereby forming a uniform silicide film in the second conducting layer deposited on the first conducting layer of the semiconductor device.
  Inventor: Jae K. Kim
  Tungsten silicide self-aligned formation process
  Patent number: 5075251
  Abstract: A process for forming tungsten or molybdenum silicide on silicon apparent regions (6) of a silicon wafer surface (1) also comprising oxidized regions (2) includes the steps consisting in uniformly coating the wafer with a tungsten or molybdenum layer (10) and annealing at a temperature ranging from 700.degree. C. to 1000.degree. C. The annealing step is carried out in presence of a low pressure gas forming a chemical composite with tungsten or molybdenum. The composite is then selectively etched.
  Inventors: Joaquim Torres, Jean Palleau, Noureddine Bourhila
  Method of forming low-resistive contact to N+/P+ preohmic regions in very large scale integrated devices
  Patent number: 5070038
  Abstract: A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.
  Inventor: Dae-Je Jin
  Process for making semiconductor-on-insulator device interconnects
  Patent number: 5066613
  Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.
  Inventors: Ronald E. Reedy, Graham A. Garcia, Isaac Lagnado
  Method of forming bipolar transistor having closely spaced device regions
  Patent number: 5064773
  Abstract: A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is below the surface of the epitaxial layer in all regions not covered by the collector region. Low resistance silicide contacts, such as titanium or cobalt, are formed on the structure in a self-aligned fashion. This method is well suited for forming BJTs as part of BiCMOS circuits.
  Inventor: Wolfgang M. Feist
  Patent number: 5059554
  Abstract: A method for fabricating integrated circuits is used to improve contacts between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polycrystalline silicon deposited and patterned. The silicide layer between the polycrystalline interconnect and the underlying silicon ensures that a high quality contact is formed.