code: def addOutputPort(self, node: LNode, name: str,
                        out: Optional[Union[RtlSignalBase, LPort]],
                        side=PortSide.EAST):
          
          oPort = node.addPort(name, PortType.OUTPUT, side)
          if out is not None:
              if isinstance(out, LPort):
                  self.node.addEdge(oPort, out)
              elif out.hidden:
                  raise ValueError("Hidden signals should not be connected to outside", name)
              elif self.isVirtual:
                  # This node is inlined inside of parent.
                  # Mark that this output of subnode should be connected
                  # to output of parent node.
                  ctx, _ = self.netCtxs.getDefault(out)
                  ctx.addDriver(oPort)
              else:
                  # connect my signal to my output port
                  _out = self.portCtx.getInside(out, PortType.OUTPUT)
                  self.node.addEdge(oPort, _out, originObj=out)
                  # mark connection of output port to parent net
                  ooPort = self.portCtx.getOutside(out, PortType.OUTPUT)
                  ctx, _ = self.rootNetCtxs.getDefault(out)
                  ctx.addDriver(ooPort)
  
          return oPort
docs: Add and connect output port on subnode