code: def reset_analog_sample_clock(state=False):
      
      set_digital_line_state(expt_settings.dev1_clock_out_name, state)
      set_digital_line_state(expt_settings.dev2_clock_out_name, state)
      set_digital_line_state(expt_settings.dev3_clock_out_name, state)
      set_digital_line_state(expt_settings.dev4_clock_out_name, state)
docs: Reset the clock line.
  
      Use this just before starting a run to avoid timing issues.