code: def signed_add(a, b):
      
      a, b = match_bitwidth(as_wires(a), as_wires(b), signed=True)
      result_len = len(a) + 1
      ext_a = a.sign_extended(result_len)
      ext_b = b.sign_extended(result_len)
      # add and truncate to the correct length
      return (ext_a + ext_b)[0:result_len]
docs: Return wirevector for result of signed addition.
  
      :param a: a wirevector to serve as first input to addition
      :param b: a wirevector to serve as second input to addition
  
      Given a length n and length m wirevector the result of the
      signed addition is length max(n,m)+1.  The inputs are twos
      complement sign extended to the same length before adding.