code: def _finalize():
      
      from .memory import MemBlock
      from pyrtl.corecircuits import select
      for lhs in _predicate_map:
          # handle memory write ports
          if isinstance(lhs, MemBlock):
              p, (addr, data, enable) = _predicate_map[lhs][0]
              combined_enable = select(p, truecase=enable, falsecase=Const(0))
              combined_addr = addr
              combined_data = data
  
              for p, (addr, data, enable) in _predicate_map[lhs][1:]:
                  combined_enable = select(p, truecase=enable, falsecase=combined_enable)
                  combined_addr = select(p, truecase=addr, falsecase=combined_addr)
                  combined_data = select(p, truecase=data, falsecase=combined_data)
  
              lhs._build(combined_addr, combined_data, combined_enable)
  
          # handle wirevector and register assignments
          else:
              if isinstance(lhs, Register):
                  result = lhs  # default for registers is "self"
              elif isinstance(lhs, WireVector):
                  result = 0  # default for wire is "0"
              else:
                  raise PyrtlInternalError('unknown assignment in finalize')
              predlist = _predicate_map[lhs]
              for p, rhs in predlist:
                  result = select(p, truecase=rhs, falsecase=result)
              lhs._build(result)
docs: Build the required muxes and call back to WireVector to finalize the wirevector build.