code: def add_step(self, value_map):
          
          if len(self.trace) == 0:
              raise PyrtlError('error, simulation trace needs at least 1 signal to track '
                               '(by default, unnamed signals are not traced -- try either passing '
                               'a name to a WireVector or setting a "wirevector_subset" option)')
          for wire in self.trace:
              tracelist = self.trace[wire]
              wirevec = self._wires[wire]
              tracelist.append(value_map[wirevec])
docs: Add the values in value_map to the end of the trace.