code: def read_external(self, address):
          
          self.bus.RD_B <= 1
          self.bus.ADD <= self._x
          self.bus.BUS_DATA <= self._high_impedence
          for _ in range(5):
              yield RisingEdge(self.clock)
  
          yield RisingEdge(self.clock)
          self.bus.ADD <= address + 0x4000
  
          yield RisingEdge(self.clock)
          self.bus.RD_B <= 0
          yield RisingEdge(self.clock)
          self.bus.RD_B <= 0
          yield ReadOnly()
          result = self.bus.BUS_DATA.value.integer
          yield RisingEdge(self.clock)
          self.bus.RD_B <= 1
  
          yield RisingEdge(self.clock)
          self.bus.RD_B <= 1
          self.bus.ADD <= self._x
  
          yield RisingEdge(self.clock)
  
          for _ in range(5):
              yield RisingEdge(self.clock)
  
          raise ReturnValue(result)
docs: Copied from silusb.sv testbench interface