code: def rtl_assert(w, exp, block=None):
      
      block = working_block(block)
  
      if not isinstance(w, WireVector):
          raise PyrtlError('Only WireVectors can be asserted with rtl_assert')
      if len(w) != 1:
          raise PyrtlError('rtl_assert checks only a WireVector of bitwidth 1')
      if not isinstance(exp, Exception):
          raise PyrtlError('the second argument to rtl_assert must be an instance of Exception')
      if isinstance(exp, KeyError):
          raise PyrtlError('the second argument to rtl_assert cannot be a KeyError')
      if w not in block.wirevector_set:
          raise PyrtlError('assertion wire not part of the block to which it is being added')
      if w not in block.wirevector_set:
          raise PyrtlError('assertion not a known wirevector in the target block')
  
      if w in block.rtl_assert_dict:
          raise PyrtlInternalError('assertion conflicts with existing registered assertion')
  
      assert_wire = Output(bitwidth=1, name=assertIndexer.make_valid_string(), block=block)
      assert_wire <<= w
      block.rtl_assert_dict[assert_wire] = exp
      return assert_wire
docs: Add hardware assertions to be checked on the RTL design.
  
      :param w: should be a WireVector
      :param Exception exp: Exception to throw when assertion fails
      :param Block block: block to which the assertion should be added (default to working block)
      :return: the Output wire for the assertion (can be ignored in most cases)
  
      If at any time during execution the wire w is not `true` (i.e. asserted low)
      then simulation will raise exp.