code: def _execute(self, net):
          
          if net.op in 'r@':
              return  # registers and memory write ports have no logic function
          elif net.op in self.simple_func:
              argvals = (self.value[arg] for arg in net.args)
              result = self.simple_func[net.op](*argvals)
          elif net.op == 'c':
              result = 0
              for arg in net.args:
                  result = result << len(arg)
                  result = result | self.value[arg]
          elif net.op == 's':
              result = 0
              source = self.value[net.args[0]]
              for b in net.op_param[::-1]:
                  result = (result << 1) | (0x1 & (source >> b))
          elif net.op == 'm':
              # memories act async for reads
              memid = net.op_param[0]
              mem = net.op_param[1]
              read_addr = self.value[net.args[0]]
              if isinstance(mem, RomBlock):
                  result = mem._get_read_data(read_addr)
              else:
                  result = self.memvalue[memid].get(read_addr, self.default_value)
          else:
              raise PyrtlInternalError('error, unknown op type')
  
          self.value[net.dests[0]] = self._sanitize(result, net.dests[0])
docs: Handle the combinational logic update rules for the given net.
  
          This function, along with edge_update, defined the semantics
          of the primitive ops. Function updates self.value accordingly.