code: def _trivial_mult(A, B):
      
      if len(B) == 1:
          A, B = B, A  # so that we can reuse the code below :)
      if len(A) == 1:
          a_vals = A.sign_extended(len(B))
  
          # keep the wirevector len consistent
          return pyrtl.concat_list([a_vals & B, pyrtl.Const(0)])
docs: turns a multiplication into an And gate if one of the
      wires is a bitwidth of 1
  
      :param A:
      :param B:
      :return: