code: def _cla_adder_unit(a, b, cin):
      
      gen = a & b
      prop = a ^ b
      assert(len(prop) == len(gen))
  
      carry = [gen[0] | prop[0] & cin]
      sum_bit = prop[0] ^ cin
  
      cur_gen = gen[0]
      cur_prop = prop[0]
      for i in range(1, len(prop)):
          cur_gen = gen[i] | (prop[i] & cur_gen)
          cur_prop = cur_prop & prop[i]
          sum_bit = pyrtl.concat(prop[i] ^ carry[i - 1], sum_bit)
          carry.append(gen[i] | (prop[i] & carry[i-1]))
      cout = cur_gen | (cur_prop & cin)
      return sum_bit, cout
docs: Carry generation and propogation signals will be calculated only using
      the inputs; their values don't rely on the sum.  Every unit generates
      a cout signal which is used as cin for the next unit.