code: def rtl_any(*vectorlist):
      
      if len(vectorlist) <= 0:
          raise PyrtlError('rtl_any requires at least 1 argument')
      converted_vectorlist = [as_wires(v) for v in vectorlist]
      if any(len(v) != 1 for v in converted_vectorlist):
          raise PyrtlError('only length 1 WireVectors can be inputs to rtl_any')
      return or_all_bits(concat_list(converted_vectorlist))
docs: Hardware equivalent of python native "any".
  
      :param WireVector vectorlist: all arguments are WireVectors of length 1
      :return: WireVector of length 1
  
      Returns a 1-bit WireVector which will hold a '1' if any of the inputs
      are '1' (i.e. it is a big ol' OR gate)