code: def simple_mult(A, B, start):
      
      triv_result = _trivial_mult(A, B)
      if triv_result is not None:
          return triv_result, pyrtl.Const(1, 1)
  
      alen = len(A)
      blen = len(B)
      areg = pyrtl.Register(alen)
      breg = pyrtl.Register(blen + alen)
      accum = pyrtl.Register(blen + alen)
      done = (areg == 0)  # Multiplication is finished when a becomes 0
  
      # During multiplication, shift a right every cycle, b left every cycle
      with pyrtl.conditional_assignment:
          with start:  # initialization
              areg.next |= A
              breg.next |= B
              accum.next |= 0
          with ~done:  # don't run when there's no work to do
              areg.next |= areg[1:]  # right shift
              breg.next |= pyrtl.concat(breg, pyrtl.Const(0, 1))  # left shift
              a_0_val = areg[0].sign_extended(len(accum))
  
              # adds to accum only when LSB of areg is 1
              accum.next |= accum + (a_0_val & breg)
  
      return accum, done
docs: Builds a slow, small multiplier using the simple shift-and-add algorithm.
      Requires very small area (it uses only a single adder), but has long delay
      (worst case is len(A) cycles). start is a one-bit input to indicate inputs are ready.
      done is a one-bit output signal raised when the multiplication is finished.
  
      :param WireVector A, B: two input wires for the multiplication
      :returns: Register containing the product; the "done" signal