code: def write_PIA0_A_control(self, cpu_cycles, op_address, address, value):
          
          log.error(
              "%04x| write $%02x (%s) to $%04x -> PIA 0 A side Control reg.\t|%s",
              op_address, value, byte2bit_string(value), address,
              self.cfg.mem_info.get_shortest(op_address)
          )
          if not is_bit_set(value, bit=2):
              self.pia_0_A_register.select_pdr()
          else:
              self.pia_0_A_register.deselect_pdr()
docs: write to 0xff01 -> PIA 0 A side control register
  
          TODO: Handle IRQ
  
          bit 7 | IRQ 1 (HSYNC) flag
          bit 6 | IRQ 2 flag(not used)
          bit 5 | Control line 2 (CA2) is an output = 1
          bit 4 | Control line 2 (CA2) set by bit 3 = 1
          bit 3 | select line LSB of analog multiplexor (MUX): 0 = control line 2 LO / 1 = control line 2 HI
          bit 2 | set data direction: 0 = $FF00 is DDR / 1 = $FF00 is normal data lines
          bit 1 | control line 1 (CA1): IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI
          bit 0 | HSYNC IRQ: 0 = disabled IRQ / 1 = enabled IRQ