code: def _one_cycle_mult(areg, breg, rem_bits, sum_sf=0, curr_bit=0):
      
      if rem_bits == 0:
          return sum_sf
      else:
          a_curr_val = areg[curr_bit].sign_extended(len(breg))
          if curr_bit == 0:  # if no shift
              return(_one_cycle_mult(areg, breg, rem_bits-1,  # areg, breg, rem_bits
                                     sum_sf + (a_curr_val & breg),  # sum_sf
                                     curr_bit+1))  # curr_bit
          else:
              return _one_cycle_mult(
                  areg, breg, rem_bits-1,  # areg, breg, rem_bits
                  sum_sf + (a_curr_val &
                            pyrtl.concat(breg, pyrtl.Const(0, curr_bit))),  # sum_sf
                  curr_bit+1  # curr_bit
              )
docs: returns a WireVector sum of rem_bits multiplies (in one clock cycle)
      note: this method requires a lot of area because of the indexing in the else statement