code: def select(sel, truecase, falsecase):
      
      sel, f, t = (as_wires(w) for w in (sel, falsecase, truecase))
      f, t = match_bitwidth(f, t)
      outwire = WireVector(bitwidth=len(f))
  
      net = LogicNet(op='x', op_param=None, args=(sel, f, t), dests=(outwire,))
      working_block().add_net(net)  # this includes sanity check on the mux
      return outwire
docs: Multiplexer returning falsecase for select==0, otherwise truecase.
  
      :param WireVector sel: used as the select input to the multiplexer
      :param WireVector falsecase: the WireVector selected if select==0
      :param WireVector truecase: the WireVector selected if select==1
  
      The hardware this generates is exactly the same as "mux" but by putting the
      true case as the first argument it matches more of the C-style ternary operator
      semantics which can be helpful for readablity.
  
      Example of mux as "ternary operator" to take the max of 'a' and 5: ::
  
          select( a<5, truecase=a, falsecase=5 )