code: def sanity_check_memory_sync(self, wire_src_dict=None):
          
          sync_mems = set(m for m in self.logic_subset('m') if not m.op_param[1].asynchronous)
          if not len(sync_mems):
              return  # nothing to check here
  
          if wire_src_dict is None:
              wire_src_dict, wdd = self.net_connections()
  
          from .wire import Input, Const
          sync_src = 'r'
          sync_prop = 'wcs'
          for net in sync_mems:
              wires_to_check = list(net.args)
              while len(wires_to_check):
                  wire = wires_to_check.pop()
                  if isinstance(wire, (Input, Const)):
                      continue
                  src_net = wire_src_dict[wire]
                  if src_net.op == sync_src:
                      continue
                  elif src_net.op in sync_prop:
                      wires_to_check.extend(src_net.args)
                  else:
                      raise PyrtlError(
                          'memory "%s" is not specified as asynchronous but has an index '
                          '"%s" that is not ready at the start of the cycle due to net "%s"'
                          % (net.op_param[1].name, net.args[0].name, str(src_net)))
docs: Check that all memories are synchronous unless explicitly specified as async.
  
          While the semantics of 'm' memories reads is asynchronous, if you want your design
          to use a block ram (on an FPGA or otherwise) you want to make sure the index is
          available at the beginning of the clock edge.  This check will walk the logic structure
          and throw an error on any memory if finds that has an index that is not ready at the
          beginning of the cycle.