code: def ASR(self, a):
          
          r = (a >> 1) | (a & 0x80)
          self.clear_NZC()
          self.C = get_bit(a, bit=0) # same as: self.C |= (a & 1)
          self.update_NZ_8(r)
          return r
docs: ASR (Arithmetic Shift Right) alias LSR (Logical Shift Right)
  
          Shifts all bits of the register one place to the right. Bit seven is held
          constant. Bit zero is shifted into the C (carry) bit.
  
          source code forms: ASR Q; ASRA; ASRB
  
          CC bits "HNZVC": uaa-s