code: def instruction_PUL(self, opcode, m, register):
          
          assert register in (self.system_stack_pointer, self.user_stack_pointer)
  
          def pull(register_str, stack_pointer):
              reg_obj = self.register_str2object[register_str]
  
              reg_width = reg_obj.WIDTH # 8 / 16
              if reg_width == 8:
                  data = self.pull_byte(stack_pointer)
              else:
                  assert reg_width == 16
                  data = self.pull_word(stack_pointer)
  
              reg_obj.set(data)
  
  #        log.debug("$%x PUL%s:", self.program_counter, register.name)
  
          # m = postbyte
          if m & 0x01: pull(REG_CC, register) # 8 bit condition code register
          if m & 0x02: pull(REG_A, register) # 8 bit accumulator
          if m & 0x04: pull(REG_B, register) # 8 bit accumulator
          if m & 0x08: pull(REG_DP, register) # 8 bit direct page register
          if m & 0x10: pull(REG_X, register) # 16 bit index register
          if m & 0x20: pull(REG_Y, register) # 16 bit index register
          if m & 0x40: pull(REG_U, register) # 16 bit user-stack pointer
          if m & 0x80: pull(REG_PC, register)
docs: All, some, or none of the processor registers are pulled from stack
          (with the exception of stack pointer itself).
  
          A single register may be pulled from the stack with condition codes set
          by doing an autoincrement load from the stack (example: LDX ,S++).
  
          source code forms: b7 b6 b5 b4 b3 b2 b1 b0 PC U Y X DP B A CC = pull
          order
  
          CC bits "HNZVC": ccccc